drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_regs.h"
  27
  28 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  29 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  30
  31 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  32
  33 int hns3_logtype_init;
  34 int hns3_logtype_driver;
  35
  36 static int
  37 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
  38                 unsigned int tso_mss_max)
  39 {
  40         struct hns3_cfg_tso_status_cmd *req;
  41         struct hns3_cmd_desc desc;
  42         uint16_t tso_mss;
  43
  44         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
  45
  46         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
  47
  48         tso_mss = 0;
  49         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  50                        tso_mss_min);
  51         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
  52
  53         tso_mss = 0;
  54         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  55                        tso_mss_max);
  56         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
  57
  58         return hns3_cmd_send(hw, &desc, 1);
  59 }
  60
  61 int
  62 hns3_config_gro(struct hns3_hw *hw, bool en)
  63 {
  64         struct hns3_cfg_gro_status_cmd *req;
  65         struct hns3_cmd_desc desc;
  66         int ret;
  67
  68         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
  69         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
  70
  71         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
  72
  73         ret = hns3_cmd_send(hw, &desc, 1);
  74         if (ret)
  75                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
  76
  77         return ret;
  78 }
  79
  80 static int
  81 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
  82                    uint16_t *allocated_size, bool is_alloc)
  83 {
  84         struct hns3_umv_spc_alc_cmd *req;
  85         struct hns3_cmd_desc desc;
  86         int ret;
  87
  88         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
  89         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
  90         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
  91         req->space_size = rte_cpu_to_le_32(space_size);
  92
  93         ret = hns3_cmd_send(hw, &desc, 1);
  94         if (ret) {
  95                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
  96                              is_alloc ? "allocate" : "free", ret);
  97                 return ret;
  98         }
  99
 100         if (is_alloc && allocated_size)
 101                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 102
 103         return 0;
 104 }
 105
 106 static int
 107 hns3_init_umv_space(struct hns3_hw *hw)
 108 {
 109         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 110         struct hns3_pf *pf = &hns->pf;
 111         uint16_t allocated_size = 0;
 112         int ret;
 113
 114         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 115                                  true);
 116         if (ret)
 117                 return ret;
 118
 119         if (allocated_size < pf->wanted_umv_size)
 120                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 121                              pf->wanted_umv_size, allocated_size);
 122
 123         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 124                                                 pf->wanted_umv_size;
 125         pf->used_umv_size = 0;
 126         return 0;
 127 }
 128
 129 static int
 130 hns3_uninit_umv_space(struct hns3_hw *hw)
 131 {
 132         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 133         struct hns3_pf *pf = &hns->pf;
 134         int ret;
 135
 136         if (pf->max_umv_size == 0)
 137                 return 0;
 138
 139         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 140         if (ret)
 141                 return ret;
 142
 143         pf->max_umv_size = 0;
 144
 145         return 0;
 146 }
 147
 148 static bool
 149 hns3_is_umv_space_full(struct hns3_hw *hw)
 150 {
 151         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 152         struct hns3_pf *pf = &hns->pf;
 153         bool is_full;
 154
 155         is_full = (pf->used_umv_size >= pf->max_umv_size);
 156
 157         return is_full;
 158 }
 159
 160 static void
 161 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 162 {
 163         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 164         struct hns3_pf *pf = &hns->pf;
 165
 166         if (is_free) {
 167                 if (pf->used_umv_size > 0)
 168                         pf->used_umv_size--;
 169         } else
 170                 pf->used_umv_size++;
 171 }
 172
 173 static void
 174 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 175                       const uint8_t *addr, bool is_mc)
 176 {
 177         const unsigned char *mac_addr = addr;
 178         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 179                             ((uint32_t)mac_addr[2] << 16) |
 180                             ((uint32_t)mac_addr[1] << 8) |
 181                             (uint32_t)mac_addr[0];
 182         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 183
 184         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 185         if (is_mc) {
 186                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 187                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 188                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 189         }
 190
 191         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 192         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 193 }
 194
 195 static int
 196 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 197                              uint8_t resp_code,
 198                              enum hns3_mac_vlan_tbl_opcode op)
 199 {
 200         if (cmdq_resp) {
 201                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 202                          cmdq_resp);
 203                 return -EIO;
 204         }
 205
 206         if (op == HNS3_MAC_VLAN_ADD) {
 207                 if (resp_code == 0 || resp_code == 1) {
 208                         return 0;
 209                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 210                         hns3_err(hw, "add mac addr failed for uc_overflow");
 211                         return -ENOSPC;
 212                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 213                         hns3_err(hw, "add mac addr failed for mc_overflow");
 214                         return -ENOSPC;
 215                 }
 216
 217                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 218                          resp_code);
 219                 return -EIO;
 220         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 221                 if (resp_code == 0) {
 222                         return 0;
 223                 } else if (resp_code == 1) {
 224                         hns3_dbg(hw, "remove mac addr failed for miss");
 225                         return -ENOENT;
 226                 }
 227
 228                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 229                          resp_code);
 230                 return -EIO;
 231         } else if (op == HNS3_MAC_VLAN_LKUP) {
 232                 if (resp_code == 0) {
 233                         return 0;
 234                 } else if (resp_code == 1) {
 235                         hns3_dbg(hw, "lookup mac addr failed for miss");
 236                         return -ENOENT;
 237                 }
 238
 239                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 240                          resp_code);
 241                 return -EIO;
 242         }
 243
 244         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 245                  op);
 246
 247         return -EINVAL;
 248 }
 249
 250 static int
 251 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 252                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 253                          struct hns3_cmd_desc *desc, bool is_mc)
 254 {
 255         uint8_t resp_code;
 256         uint16_t retval;
 257         int ret;
 258
 259         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 260         if (is_mc) {
 261                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 262                 memcpy(desc[0].data, req,
 263                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 264                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 265                                           true);
 266                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 267                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 268                                           true);
 269                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 270         } else {
 271                 memcpy(desc[0].data, req,
 272                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 273                 ret = hns3_cmd_send(hw, desc, 1);
 274         }
 275         if (ret) {
 276                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 277                          ret);
 278                 return ret;
 279         }
 280         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 281         retval = rte_le_to_cpu_16(desc[0].retval);
 282
 283         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 284                                             HNS3_MAC_VLAN_LKUP);
 285 }
 286
 287 static int
 288 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 289                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 290                       struct hns3_cmd_desc *mc_desc)
 291 {
 292         uint8_t resp_code;
 293         uint16_t retval;
 294         int cfg_status;
 295         int ret;
 296
 297         if (mc_desc == NULL) {
 298                 struct hns3_cmd_desc desc;
 299
 300                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 301                 memcpy(desc.data, req,
 302                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 303                 ret = hns3_cmd_send(hw, &desc, 1);
 304                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 305                 retval = rte_le_to_cpu_16(desc.retval);
 306
 307                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 308                                                           HNS3_MAC_VLAN_ADD);
 309         } else {
 310                 hns3_cmd_reuse_desc(&mc_desc[0], false);
 311                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 312                 hns3_cmd_reuse_desc(&mc_desc[1], false);
 313                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 314                 hns3_cmd_reuse_desc(&mc_desc[2], false);
 315                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
 316                 memcpy(mc_desc[0].data, req,
 317                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 318                 mc_desc[0].retval = 0;
 319                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 320                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
 321                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
 322
 323                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 324                                                           HNS3_MAC_VLAN_ADD);
 325         }
 326
 327         if (ret) {
 328                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
 329                 return ret;
 330         }
 331
 332         return cfg_status;
 333 }
 334
 335 static int
 336 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
 337                          struct hns3_mac_vlan_tbl_entry_cmd *req)
 338 {
 339         struct hns3_cmd_desc desc;
 340         uint8_t resp_code;
 341         uint16_t retval;
 342         int ret;
 343
 344         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
 345
 346         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 347
 348         ret = hns3_cmd_send(hw, &desc, 1);
 349         if (ret) {
 350                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
 351                 return ret;
 352         }
 353         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 354         retval = rte_le_to_cpu_16(desc.retval);
 355
 356         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 357                                             HNS3_MAC_VLAN_REMOVE);
 358 }
 359
 360 static int
 361 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 362 {
 363         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 364         struct hns3_mac_vlan_tbl_entry_cmd req;
 365         struct hns3_pf *pf = &hns->pf;
 366         struct hns3_cmd_desc desc;
 367         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 368         uint16_t egress_port = 0;
 369         uint8_t vf_id;
 370         int ret;
 371
 372         /* check if mac addr is valid */
 373         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 374                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 375                                       mac_addr);
 376                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
 377                          mac_str);
 378                 return -EINVAL;
 379         }
 380
 381         memset(&req, 0, sizeof(req));
 382
 383         /*
 384          * In current version VF is not supported when PF is driven by DPDK
 385          * driver, the PF-related vf_id is 0, just need to configure parameters
 386          * for vf_id 0.
 387          */
 388         vf_id = 0;
 389         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
 390                        HNS3_MAC_EPORT_VFID_S, vf_id);
 391
 392         req.egress_port = rte_cpu_to_le_16(egress_port);
 393
 394         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 395
 396         /*
 397          * Lookup the mac address in the mac_vlan table, and add
 398          * it if the entry is inexistent. Repeated unicast entry
 399          * is not allowed in the mac vlan table.
 400          */
 401         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
 402         if (ret == -ENOENT) {
 403                 if (!hns3_is_umv_space_full(hw)) {
 404                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
 405                         if (!ret)
 406                                 hns3_update_umv_space(hw, false);
 407                         return ret;
 408                 }
 409
 410                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
 411
 412                 return -ENOSPC;
 413         }
 414
 415         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
 416
 417         /* check if we just hit the duplicate */
 418         if (ret == 0) {
 419                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
 420                 return 0;
 421         }
 422
 423         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
 424                  mac_str);
 425
 426         return ret;
 427 }
 428
 429 static int
 430 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 431                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
 432 {
 433         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 435         int ret;
 436
 437         rte_spinlock_lock(&hw->lock);
 438         ret = hns3_add_uc_addr_common(hw, mac_addr);
 439         if (ret) {
 440                 rte_spinlock_unlock(&hw->lock);
 441                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 442                                       mac_addr);
 443                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
 444                 return ret;
 445         }
 446
 447         if (idx == 0)
 448                 hw->mac.default_addr_setted = true;
 449         rte_spinlock_unlock(&hw->lock);
 450
 451         return ret;
 452 }
 453
 454 static int
 455 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 456 {
 457         struct hns3_mac_vlan_tbl_entry_cmd req;
 458         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 459         int ret;
 460
 461         /* check if mac addr is valid */
 462         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 463                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 464                                       mac_addr);
 465                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
 466                          mac_str);
 467                 return -EINVAL;
 468         }
 469
 470         memset(&req, 0, sizeof(req));
 471         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 472         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 473         ret = hns3_remove_mac_vlan_tbl(hw, &req);
 474         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
 475                 return 0;
 476         else if (ret == 0)
 477                 hns3_update_umv_space(hw, true);
 478
 479         return ret;
 480 }
 481
 482 static void
 483 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 484 {
 485         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 486         /* index will be checked by upper level rte interface */
 487         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 488         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 489         int ret;
 490
 491         rte_spinlock_lock(&hw->lock);
 492         ret = hns3_remove_uc_addr_common(hw, mac_addr);
 493         if (ret) {
 494                 rte_spinlock_unlock(&hw->lock);
 495                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 496                                       mac_addr);
 497                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
 498                 return;
 499         }
 500
 501         if (idx == 0)
 502                 hw->mac.default_addr_setted = false;
 503         rte_spinlock_unlock(&hw->lock);
 504 }
 505
 506 static int
 507 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
 508                           struct rte_ether_addr *mac_addr)
 509 {
 510         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511         struct rte_ether_addr *oaddr;
 512         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 513         bool default_addr_setted;
 514         bool rm_succes = false;
 515         int ret, ret_val;
 516
 517         /* check if mac addr is valid */
 518         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 519                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 520                                       mac_addr);
 521                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
 522                          mac_str);
 523                 return -EINVAL;
 524         }
 525
 526         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
 527         default_addr_setted = hw->mac.default_addr_setted;
 528         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
 529                 return 0;
 530
 531         rte_spinlock_lock(&hw->lock);
 532         if (default_addr_setted) {
 533                 ret = hns3_remove_uc_addr_common(hw, oaddr);
 534                 if (ret) {
 535                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 536                                               oaddr);
 537                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
 538                                   mac_str, ret);
 539                         rm_succes = false;
 540                 } else
 541                         rm_succes = true;
 542         }
 543
 544         ret = hns3_add_uc_addr_common(hw, mac_addr);
 545         if (ret) {
 546                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 547                                       mac_addr);
 548                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
 549                 goto err_add_uc_addr;
 550         }
 551
 552         rte_ether_addr_copy(mac_addr,
 553                             (struct rte_ether_addr *)hw->mac.mac_addr);
 554         hw->mac.default_addr_setted = true;
 555         rte_spinlock_unlock(&hw->lock);
 556
 557         return 0;
 558
 559 err_add_uc_addr:
 560         if (rm_succes) {
 561                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
 562                 if (ret_val) {
 563                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 564                                               oaddr);
 565                         hns3_warn(hw,
 566                                   "Failed to restore old uc mac addr(%s): %d",
 567                                   mac_str, ret_val);
 568                         hw->mac.default_addr_setted = false;
 569                 }
 570         }
 571         rte_spinlock_unlock(&hw->lock);
 572
 573         return ret;
 574 }
 575
 576 static void
 577 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
 578 {
 579 #define HNS3_VF_NUM_IN_FIRST_DESC 192
 580         uint8_t word_num;
 581         uint8_t bit_num;
 582
 583         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
 584                 word_num = vfid / 32;
 585                 bit_num = vfid % 32;
 586                 if (clr)
 587                         desc[1].data[word_num] &=
 588                             rte_cpu_to_le_32(~(1UL << bit_num));
 589                 else
 590                         desc[1].data[word_num] |=
 591                             rte_cpu_to_le_32(1UL << bit_num);
 592         } else {
 593                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
 594                 bit_num = vfid % 32;
 595                 if (clr)
 596                         desc[2].data[word_num] &=
 597                             rte_cpu_to_le_32(~(1UL << bit_num));
 598                 else
 599                         desc[2].data[word_num] |=
 600                             rte_cpu_to_le_32(1UL << bit_num);
 601         }
 602 }
 603
 604 static int
 605 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 606 {
 607         struct hns3_mac_vlan_tbl_entry_cmd req;
 608         struct hns3_cmd_desc desc[3];
 609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 610         uint8_t vf_id;
 611         int ret;
 612
 613         /* Check if mac addr is valid */
 614         if (!rte_is_multicast_ether_addr(mac_addr)) {
 615                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 616                                       mac_addr);
 617                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
 618                          mac_str);
 619                 return -EINVAL;
 620         }
 621
 622         memset(&req, 0, sizeof(req));
 623         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 624         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 625         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 626         if (ret) {
 627                 /* This mac addr do not exist, add new entry for it */
 628                 memset(desc[0].data, 0, sizeof(desc[0].data));
 629                 memset(desc[1].data, 0, sizeof(desc[0].data));
 630                 memset(desc[2].data, 0, sizeof(desc[0].data));
 631         }
 632
 633         /*
 634          * In current version VF is not supported when PF is driven by DPDK
 635          * driver, the PF-related vf_id is 0, just need to configure parameters
 636          * for vf_id 0.
 637          */
 638         vf_id = 0;
 639         hns3_update_desc_vfid(desc, vf_id, false);
 640         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
 641         if (ret) {
 642                 if (ret == -ENOSPC)
 643                         hns3_err(hw, "mc mac vlan table is full");
 644                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 645                                       mac_addr);
 646                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
 647         }
 648
 649         return ret;
 650 }
 651
 652 static int
 653 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 654 {
 655         struct hns3_mac_vlan_tbl_entry_cmd req;
 656         struct hns3_cmd_desc desc[3];
 657         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 658         uint8_t vf_id;
 659         int ret;
 660
 661         /* Check if mac addr is valid */
 662         if (!rte_is_multicast_ether_addr(mac_addr)) {
 663                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 664                                       mac_addr);
 665                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
 666                          mac_str);
 667                 return -EINVAL;
 668         }
 669
 670         memset(&req, 0, sizeof(req));
 671         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 672         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 673         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 674         if (ret == 0) {
 675                 /*
 676                  * This mac addr exist, remove this handle's VFID for it.
 677                  * In current version VF is not supported when PF is driven by
 678                  * DPDK driver, the PF-related vf_id is 0, just need to
 679                  * configure parameters for vf_id 0.
 680                  */
 681                 vf_id = 0;
 682                 hns3_update_desc_vfid(desc, vf_id, true);
 683
 684                 /* All the vfid is zero, so need to delete this entry */
 685                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
 686         } else if (ret == -ENOENT) {
 687                 /* This mac addr doesn't exist. */
 688                 return 0;
 689         }
 690
 691         if (ret) {
 692                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 693                                       mac_addr);
 694                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
 695         }
 696
 697         return ret;
 698 }
 699
 700 static int
 701 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
 702                            struct rte_ether_addr *mc_addr_set,
 703                            uint32_t nb_mc_addr)
 704 {
 705         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 706         struct rte_ether_addr *addr;
 707         uint32_t i;
 708         uint32_t j;
 709
 710         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 711                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 712                          "invalid. valid range: 0~%d",
 713                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 714                 return -EINVAL;
 715         }
 716
 717         /* Check if input mac addresses are valid */
 718         for (i = 0; i < nb_mc_addr; i++) {
 719                 addr = &mc_addr_set[i];
 720                 if (!rte_is_multicast_ether_addr(addr)) {
 721                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 722                                               addr);
 723                         hns3_err(hw,
 724                                  "Failed to set mc mac addr, addr(%s) invalid.",
 725                                  mac_str);
 726                         return -EINVAL;
 727                 }
 728
 729                 /* Check if there are duplicate addresses */
 730                 for (j = i + 1; j < nb_mc_addr; j++) {
 731                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 732                                 rte_ether_format_addr(mac_str,
 733                                                       RTE_ETHER_ADDR_FMT_SIZE,
 734                                                       addr);
 735                                 hns3_err(hw, "Failed to set mc mac addr, "
 736                                          "addrs invalid. two same addrs(%s).",
 737                                          mac_str);
 738                                 return -EINVAL;
 739                         }
 740                 }
 741         }
 742
 743         return 0;
 744 }
 745
 746 static void
 747 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
 748                            struct rte_ether_addr *mc_addr_set,
 749                            int mc_addr_num,
 750                            struct rte_ether_addr *reserved_addr_list,
 751                            int *reserved_addr_num,
 752                            struct rte_ether_addr *add_addr_list,
 753                            int *add_addr_num,
 754                            struct rte_ether_addr *rm_addr_list,
 755                            int *rm_addr_num)
 756 {
 757         struct rte_ether_addr *addr;
 758         int current_addr_num;
 759         int reserved_num = 0;
 760         int add_num = 0;
 761         int rm_num = 0;
 762         int num;
 763         int i;
 764         int j;
 765         bool same_addr;
 766
 767         /* Calculate the mc mac address list that should be removed */
 768         current_addr_num = hw->mc_addrs_num;
 769         for (i = 0; i < current_addr_num; i++) {
 770                 addr = &hw->mc_addrs[i];
 771                 same_addr = false;
 772                 for (j = 0; j < mc_addr_num; j++) {
 773                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 774                                 same_addr = true;
 775                                 break;
 776                         }
 777                 }
 778
 779                 if (!same_addr) {
 780                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
 781                         rm_num++;
 782                 } else {
 783                         rte_ether_addr_copy(addr,
 784                                             &reserved_addr_list[reserved_num]);
 785                         reserved_num++;
 786                 }
 787         }
 788
 789         /* Calculate the mc mac address list that should be added */
 790         for (i = 0; i < mc_addr_num; i++) {
 791                 addr = &mc_addr_set[i];
 792                 same_addr = false;
 793                 for (j = 0; j < current_addr_num; j++) {
 794                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
 795                                 same_addr = true;
 796                                 break;
 797                         }
 798                 }
 799
 800                 if (!same_addr) {
 801                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
 802                         add_num++;
 803                 }
 804         }
 805
 806         /* Reorder the mc mac address list maintained by driver */
 807         for (i = 0; i < reserved_num; i++)
 808                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
 809
 810         for (i = 0; i < rm_num; i++) {
 811                 num = reserved_num + i;
 812                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
 813         }
 814
 815         *reserved_addr_num = reserved_num;
 816         *add_addr_num = add_num;
 817         *rm_addr_num = rm_num;
 818 }
 819
 820 static int
 821 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 822                           struct rte_ether_addr *mc_addr_set,
 823                           uint32_t nb_mc_addr)
 824 {
 825         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 826         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
 827         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
 828         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
 829         struct rte_ether_addr *addr;
 830         int reserved_addr_num;
 831         int add_addr_num;
 832         int rm_addr_num;
 833         int mc_addr_num;
 834         int num;
 835         int ret;
 836         int i;
 837
 838         /* Check if input parameters are valid */
 839         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 840         if (ret)
 841                 return ret;
 842
 843         rte_spinlock_lock(&hw->lock);
 844
 845         /*
 846          * Calculate the mc mac address lists those should be removed and be
 847          * added, Reorder the mc mac address list maintained by driver.
 848          */
 849         mc_addr_num = (int)nb_mc_addr;
 850         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
 851                                    reserved_addr_list, &reserved_addr_num,
 852                                    add_addr_list, &add_addr_num,
 853                                    rm_addr_list, &rm_addr_num);
 854
 855         /* Remove mc mac addresses */
 856         for (i = 0; i < rm_addr_num; i++) {
 857                 num = rm_addr_num - i - 1;
 858                 addr = &rm_addr_list[num];
 859                 ret = hns3_remove_mc_addr(hw, addr);
 860                 if (ret) {
 861                         rte_spinlock_unlock(&hw->lock);
 862                         return ret;
 863                 }
 864                 hw->mc_addrs_num--;
 865         }
 866
 867         /* Add mc mac addresses */
 868         for (i = 0; i < add_addr_num; i++) {
 869                 addr = &add_addr_list[i];
 870                 ret = hns3_add_mc_addr(hw, addr);
 871                 if (ret) {
 872                         rte_spinlock_unlock(&hw->lock);
 873                         return ret;
 874                 }
 875
 876                 num = reserved_addr_num + i;
 877                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
 878                 hw->mc_addrs_num++;
 879         }
 880         rte_spinlock_unlock(&hw->lock);
 881
 882         return 0;
 883 }
 884
 885 static int
 886 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 887 {
 888         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 889         struct hns3_hw *hw = &hns->hw;
 890         struct rte_ether_addr *addr;
 891         int err = 0;
 892         int ret;
 893         int i;
 894
 895         for (i = 0; i < hw->mc_addrs_num; i++) {
 896                 addr = &hw->mc_addrs[i];
 897                 if (!rte_is_multicast_ether_addr(addr))
 898                         continue;
 899                 if (del)
 900                         ret = hns3_remove_mc_addr(hw, addr);
 901                 else
 902                         ret = hns3_add_mc_addr(hw, addr);
 903                 if (ret) {
 904                         err = ret;
 905                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 906                                               addr);
 907                         hns3_dbg(hw, "%s mc mac addr: %s failed",
 908                                  del ? "Remove" : "Restore", mac_str);
 909                 }
 910         }
 911         return err;
 912 }
 913
 914 static int
 915 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
 916 {
 917         struct hns3_config_max_frm_size_cmd *req;
 918         struct hns3_cmd_desc desc;
 919
 920         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
 921
 922         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
 923         req->max_frm_size = rte_cpu_to_le_16(new_mps);
 924         req->min_frm_size = HNS3_MIN_FRAME_LEN;
 925
 926         return hns3_cmd_send(hw, &desc, 1);
 927 }
 928
 929 static int
 930 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
 931 {
 932         int ret;
 933
 934         ret = hns3_set_mac_mtu(hw, mps);
 935         if (ret) {
 936                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
 937                 return ret;
 938         }
 939
 940         ret = hns3_buffer_alloc(hw);
 941         if (ret) {
 942                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
 943                 return ret;
 944         }
 945
 946         return 0;
 947 }
 948
 949 static int
 950 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 951 {
 952         struct hns3_adapter *hns = dev->data->dev_private;
 953         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 954         struct hns3_hw *hw = &hns->hw;
 955         bool is_jumbo_frame;
 956         int ret;
 957
 958         if (dev->data->dev_started) {
 959                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
 960                          "before configuration", dev->data->port_id);
 961                 return -EBUSY;
 962         }
 963
 964         rte_spinlock_lock(&hw->lock);
 965         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
 966         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
 967
 968         /*
 969          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
 970          * assign to "uint16_t" type variable.
 971          */
 972         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
 973         if (ret) {
 974                 rte_spinlock_unlock(&hw->lock);
 975                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
 976                          dev->data->port_id, mtu, ret);
 977                 return ret;
 978         }
 979         hns->pf.mps = (uint16_t)frame_size;
 980         if (is_jumbo_frame)
 981                 dev->data->dev_conf.rxmode.offloads |=
 982                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 983         else
 984                 dev->data->dev_conf.rxmode.offloads &=
 985                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 986         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 987         rte_spinlock_unlock(&hw->lock);
 988
 989         return 0;
 990 }
 991
 992 static int
 993 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 994 {
 995         struct hns3_adapter *hns = eth_dev->data->dev_private;
 996         struct hns3_hw *hw = &hns->hw;
 997
 998         info->max_rx_queues = hw->tqps_num;
 999         info->max_tx_queues = hw->tqps_num;
1000         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
1001         info->min_rx_bufsize = hw->rx_buf_len;
1002         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1003         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1004         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1005                                  DEV_RX_OFFLOAD_TCP_CKSUM |
1006                                  DEV_RX_OFFLOAD_UDP_CKSUM |
1007                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
1008                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1009                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1010                                  DEV_RX_OFFLOAD_KEEP_CRC |
1011                                  DEV_RX_OFFLOAD_SCATTER |
1012                                  DEV_RX_OFFLOAD_VLAN_STRIP |
1013                                  DEV_RX_OFFLOAD_QINQ_STRIP |
1014                                  DEV_RX_OFFLOAD_VLAN_FILTER |
1015                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
1016                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
1017         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1018         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1019                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
1020                                  DEV_TX_OFFLOAD_TCP_CKSUM |
1021                                  DEV_TX_OFFLOAD_UDP_CKSUM |
1022                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
1023                                  DEV_TX_OFFLOAD_VLAN_INSERT |
1024                                  DEV_TX_OFFLOAD_QINQ_INSERT |
1025                                  DEV_TX_OFFLOAD_MULTI_SEGS |
1026                                  info->tx_queue_offload_capa);
1027
1028         info->vmdq_queue_num = 0;
1029
1030         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1031         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1032         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1033
1034         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1035         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1036         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1037         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1038
1039         return 0;
1040 }
1041
1042 static int
1043 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1044                     size_t fw_size)
1045 {
1046         struct hns3_adapter *hns = eth_dev->data->dev_private;
1047         struct hns3_hw *hw = &hns->hw;
1048         int ret;
1049
1050         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1051         ret += 1; /* add the size of '\0' */
1052         if (fw_size < (uint32_t)ret)
1053                 return ret;
1054         else
1055                 return 0;
1056 }
1057
1058 static int
1059 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
1060                      __rte_unused int wait_to_complete)
1061 {
1062         struct hns3_adapter *hns = eth_dev->data->dev_private;
1063         struct hns3_hw *hw = &hns->hw;
1064         struct hns3_mac *mac = &hw->mac;
1065         struct rte_eth_link new_link;
1066
1067         memset(&new_link, 0, sizeof(new_link));
1068         switch (mac->link_speed) {
1069         case ETH_SPEED_NUM_10M:
1070         case ETH_SPEED_NUM_100M:
1071         case ETH_SPEED_NUM_1G:
1072         case ETH_SPEED_NUM_10G:
1073         case ETH_SPEED_NUM_25G:
1074         case ETH_SPEED_NUM_40G:
1075         case ETH_SPEED_NUM_50G:
1076         case ETH_SPEED_NUM_100G:
1077                 new_link.link_speed = mac->link_speed;
1078                 break;
1079         default:
1080                 new_link.link_speed = ETH_SPEED_NUM_100M;
1081                 break;
1082         }
1083
1084         new_link.link_duplex = mac->link_duplex;
1085         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1086         new_link.link_autoneg =
1087             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1088
1089         return rte_eth_linkstatus_set(eth_dev, &new_link);
1090 }
1091
1092 static int
1093 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1094 {
1095         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1096         struct hns3_pf *pf = &hns->pf;
1097
1098         if (!(status->pf_state & HNS3_PF_STATE_DONE))
1099                 return -EINVAL;
1100
1101         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1102
1103         return 0;
1104 }
1105
1106 static int
1107 hns3_query_function_status(struct hns3_hw *hw)
1108 {
1109 #define HNS3_QUERY_MAX_CNT              10
1110 #define HNS3_QUERY_SLEEP_MSCOEND        1
1111         struct hns3_func_status_cmd *req;
1112         struct hns3_cmd_desc desc;
1113         int timeout = 0;
1114         int ret;
1115
1116         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1117         req = (struct hns3_func_status_cmd *)desc.data;
1118
1119         do {
1120                 ret = hns3_cmd_send(hw, &desc, 1);
1121                 if (ret) {
1122                         PMD_INIT_LOG(ERR, "query function status failed %d",
1123                                      ret);
1124                         return ret;
1125                 }
1126
1127                 /* Check pf reset is done */
1128                 if (req->pf_state)
1129                         break;
1130
1131                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1132         } while (timeout++ < HNS3_QUERY_MAX_CNT);
1133
1134         return hns3_parse_func_status(hw, req);
1135 }
1136
1137 static int
1138 hns3_query_pf_resource(struct hns3_hw *hw)
1139 {
1140         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1141         struct hns3_pf *pf = &hns->pf;
1142         struct hns3_pf_res_cmd *req;
1143         struct hns3_cmd_desc desc;
1144         int ret;
1145
1146         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1147         ret = hns3_cmd_send(hw, &desc, 1);
1148         if (ret) {
1149                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1150                 return ret;
1151         }
1152
1153         req = (struct hns3_pf_res_cmd *)desc.data;
1154         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1155         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1156         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1157
1158         if (req->tx_buf_size)
1159                 pf->tx_buf_size =
1160                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1161         else
1162                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1163
1164         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1165
1166         if (req->dv_buf_size)
1167                 pf->dv_buf_size =
1168                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1169         else
1170                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1171
1172         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1173
1174         hw->num_msi =
1175             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1176                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1177
1178         return 0;
1179 }
1180
1181 static void
1182 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1183 {
1184         struct hns3_cfg_param_cmd *req;
1185         uint64_t mac_addr_tmp_high;
1186         uint64_t mac_addr_tmp;
1187         uint32_t i;
1188
1189         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1190
1191         /* get the configuration */
1192         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1193                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1194         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1195                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1196         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1197                                            HNS3_CFG_TQP_DESC_N_M,
1198                                            HNS3_CFG_TQP_DESC_N_S);
1199
1200         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1201                                        HNS3_CFG_PHY_ADDR_M,
1202                                        HNS3_CFG_PHY_ADDR_S);
1203         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1204                                          HNS3_CFG_MEDIA_TP_M,
1205                                          HNS3_CFG_MEDIA_TP_S);
1206         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1207                                          HNS3_CFG_RX_BUF_LEN_M,
1208                                          HNS3_CFG_RX_BUF_LEN_S);
1209         /* get mac address */
1210         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1211         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1212                                            HNS3_CFG_MAC_ADDR_H_M,
1213                                            HNS3_CFG_MAC_ADDR_H_S);
1214
1215         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1216
1217         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1218                                             HNS3_CFG_DEFAULT_SPEED_M,
1219                                             HNS3_CFG_DEFAULT_SPEED_S);
1220         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1221                                            HNS3_CFG_RSS_SIZE_M,
1222                                            HNS3_CFG_RSS_SIZE_S);
1223
1224         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1225                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1226
1227         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1228         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1229
1230         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1231                                             HNS3_CFG_SPEED_ABILITY_M,
1232                                             HNS3_CFG_SPEED_ABILITY_S);
1233         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1234                                         HNS3_CFG_UMV_TBL_SPACE_M,
1235                                         HNS3_CFG_UMV_TBL_SPACE_S);
1236         if (!cfg->umv_space)
1237                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1238 }
1239
1240 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1241  * @hw: pointer to struct hns3_hw
1242  * @hcfg: the config structure to be getted
1243  */
1244 static int
1245 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1246 {
1247         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1248         struct hns3_cfg_param_cmd *req;
1249         uint32_t offset;
1250         uint32_t i;
1251         int ret;
1252
1253         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1254                 offset = 0;
1255                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1256                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1257                                           true);
1258                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1259                                i * HNS3_CFG_RD_LEN_BYTES);
1260                 /* Len should be divided by 4 when send to hardware */
1261                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1262                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1263                 req->offset = rte_cpu_to_le_32(offset);
1264         }
1265
1266         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1267         if (ret) {
1268                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1269                 return ret;
1270         }
1271
1272         hns3_parse_cfg(hcfg, desc);
1273
1274         return 0;
1275 }
1276
1277 static int
1278 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1279 {
1280         switch (speed_cmd) {
1281         case HNS3_CFG_SPEED_10M:
1282                 *speed = ETH_SPEED_NUM_10M;
1283                 break;
1284         case HNS3_CFG_SPEED_100M:
1285                 *speed = ETH_SPEED_NUM_100M;
1286                 break;
1287         case HNS3_CFG_SPEED_1G:
1288                 *speed = ETH_SPEED_NUM_1G;
1289                 break;
1290         case HNS3_CFG_SPEED_10G:
1291                 *speed = ETH_SPEED_NUM_10G;
1292                 break;
1293         case HNS3_CFG_SPEED_25G:
1294                 *speed = ETH_SPEED_NUM_25G;
1295                 break;
1296         case HNS3_CFG_SPEED_40G:
1297                 *speed = ETH_SPEED_NUM_40G;
1298                 break;
1299         case HNS3_CFG_SPEED_50G:
1300                 *speed = ETH_SPEED_NUM_50G;
1301                 break;
1302         case HNS3_CFG_SPEED_100G:
1303                 *speed = ETH_SPEED_NUM_100G;
1304                 break;
1305         default:
1306                 return -EINVAL;
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int
1313 hns3_get_board_configuration(struct hns3_hw *hw)
1314 {
1315         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1316         struct hns3_pf *pf = &hns->pf;
1317         struct hns3_cfg cfg;
1318         int ret;
1319
1320         ret = hns3_get_board_cfg(hw, &cfg);
1321         if (ret) {
1322                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
1323                 return ret;
1324         }
1325
1326         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
1327                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
1328                 return -EOPNOTSUPP;
1329         }
1330
1331         hw->mac.media_type = cfg.media_type;
1332         hw->rss_size_max = cfg.rss_size_max;
1333         hw->rx_buf_len = cfg.rx_buf_len;
1334         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
1335         hw->mac.phy_addr = cfg.phy_addr;
1336         hw->mac.default_addr_setted = false;
1337         hw->num_tx_desc = cfg.tqp_desc_num;
1338         hw->num_rx_desc = cfg.tqp_desc_num;
1339         hw->dcb_info.num_pg = 1;
1340         hw->dcb_info.hw_pfc_map = 0;
1341
1342         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
1343         if (ret) {
1344                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
1345                              cfg.default_speed, ret);
1346                 return ret;
1347         }
1348
1349         pf->tc_max = cfg.tc_num;
1350         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
1351                 PMD_INIT_LOG(WARNING,
1352                              "Get TC num(%u) from flash, set TC num to 1",
1353                              pf->tc_max);
1354                 pf->tc_max = 1;
1355         }
1356
1357         /* Dev does not support DCB */
1358         if (!hns3_dev_dcb_supported(hw)) {
1359                 pf->tc_max = 1;
1360                 pf->pfc_max = 0;
1361         } else
1362                 pf->pfc_max = pf->tc_max;
1363
1364         hw->dcb_info.num_tc = 1;
1365         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
1366                                      hw->tqps_num / hw->dcb_info.num_tc);
1367         hns3_set_bit(hw->hw_tc_map, 0, 1);
1368         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
1369
1370         pf->wanted_umv_size = cfg.umv_space;
1371
1372         return ret;
1373 }
1374
1375 static int
1376 hns3_get_configuration(struct hns3_hw *hw)
1377 {
1378         int ret;
1379
1380         ret = hns3_query_function_status(hw);
1381         if (ret) {
1382                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
1383                 return ret;
1384         }
1385
1386         /* Get pf resource */
1387         ret = hns3_query_pf_resource(hw);
1388         if (ret) {
1389                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
1390                 return ret;
1391         }
1392
1393         ret = hns3_get_board_configuration(hw);
1394         if (ret) {
1395                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
1396                 return ret;
1397         }
1398
1399         return 0;
1400 }
1401
1402 static int
1403 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
1404                       uint16_t tqp_vid, bool is_pf)
1405 {
1406         struct hns3_tqp_map_cmd *req;
1407         struct hns3_cmd_desc desc;
1408         int ret;
1409
1410         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
1411
1412         req = (struct hns3_tqp_map_cmd *)desc.data;
1413         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
1414         req->tqp_vf = func_id;
1415         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
1416         if (!is_pf)
1417                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
1418         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
1419
1420         ret = hns3_cmd_send(hw, &desc, 1);
1421         if (ret)
1422                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
1423
1424         return ret;
1425 }
1426
1427 static int
1428 hns3_map_tqp(struct hns3_hw *hw)
1429 {
1430         uint16_t tqps_num = hw->total_tqps_num;
1431         uint16_t func_id;
1432         uint16_t tqp_id;
1433         int num;
1434         int ret;
1435         int i;
1436
1437         /*
1438          * In current version VF is not supported when PF is driven by DPDK
1439          * driver, so we allocate tqps to PF as much as possible.
1440          */
1441         tqp_id = 0;
1442         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1443         for (func_id = 0; func_id < num; func_id++) {
1444                 for (i = 0;
1445                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
1446                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
1447                                                     true);
1448                         if (ret)
1449                                 return ret;
1450                 }
1451         }
1452
1453         return 0;
1454 }
1455
1456 static int
1457 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
1458 {
1459         struct hns3_config_mac_speed_dup_cmd *req;
1460         struct hns3_cmd_desc desc;
1461         int ret;
1462
1463         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
1464
1465         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
1466
1467         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
1468
1469         switch (speed) {
1470         case ETH_SPEED_NUM_10M:
1471                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1472                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
1473                 break;
1474         case ETH_SPEED_NUM_100M:
1475                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1476                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
1477                 break;
1478         case ETH_SPEED_NUM_1G:
1479                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1480                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
1481                 break;
1482         case ETH_SPEED_NUM_10G:
1483                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1484                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
1485                 break;
1486         case ETH_SPEED_NUM_25G:
1487                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1488                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
1489                 break;
1490         case ETH_SPEED_NUM_40G:
1491                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1492                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
1493                 break;
1494         case ETH_SPEED_NUM_50G:
1495                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1496                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
1497                 break;
1498         case ETH_SPEED_NUM_100G:
1499                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1500                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
1501                 break;
1502         default:
1503                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
1504                 return -EINVAL;
1505         }
1506
1507         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
1508
1509         ret = hns3_cmd_send(hw, &desc, 1);
1510         if (ret)
1511                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
1512
1513         return ret;
1514 }
1515
1516 static int
1517 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1518 {
1519         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1520         struct hns3_pf *pf = &hns->pf;
1521         struct hns3_priv_buf *priv;
1522         uint32_t i, total_size;
1523
1524         total_size = pf->pkt_buf_size;
1525
1526         /* alloc tx buffer for all enabled tc */
1527         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1528                 priv = &buf_alloc->priv_buf[i];
1529
1530                 if (hw->hw_tc_map & BIT(i)) {
1531                         if (total_size < pf->tx_buf_size)
1532                                 return -ENOMEM;
1533
1534                         priv->tx_buf_size = pf->tx_buf_size;
1535                 } else
1536                         priv->tx_buf_size = 0;
1537
1538                 total_size -= priv->tx_buf_size;
1539         }
1540
1541         return 0;
1542 }
1543
1544 static int
1545 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1546 {
1547 /* TX buffer size is unit by 128 byte */
1548 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
1549 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
1550         struct hns3_tx_buff_alloc_cmd *req;
1551         struct hns3_cmd_desc desc;
1552         uint32_t buf_size;
1553         uint32_t i;
1554         int ret;
1555
1556         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
1557
1558         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
1559         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1560                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1561
1562                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
1563                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
1564                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
1565         }
1566
1567         ret = hns3_cmd_send(hw, &desc, 1);
1568         if (ret)
1569                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
1570
1571         return ret;
1572 }
1573
1574 static int
1575 hns3_get_tc_num(struct hns3_hw *hw)
1576 {
1577         int cnt = 0;
1578         uint8_t i;
1579
1580         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1581                 if (hw->hw_tc_map & BIT(i))
1582                         cnt++;
1583         return cnt;
1584 }
1585
1586 static uint32_t
1587 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1588 {
1589         struct hns3_priv_buf *priv;
1590         uint32_t rx_priv = 0;
1591         int i;
1592
1593         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1594                 priv = &buf_alloc->priv_buf[i];
1595                 if (priv->enable)
1596                         rx_priv += priv->buf_size;
1597         }
1598         return rx_priv;
1599 }
1600
1601 static uint32_t
1602 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1603 {
1604         uint32_t total_tx_size = 0;
1605         uint32_t i;
1606
1607         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1608                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1609
1610         return total_tx_size;
1611 }
1612
1613 /* Get the number of pfc enabled TCs, which have private buffer */
1614 static int
1615 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1616 {
1617         struct hns3_priv_buf *priv;
1618         int cnt = 0;
1619         uint8_t i;
1620
1621         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1622                 priv = &buf_alloc->priv_buf[i];
1623                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1624                         cnt++;
1625         }
1626
1627         return cnt;
1628 }
1629
1630 /* Get the number of pfc disabled TCs, which have private buffer */
1631 static int
1632 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
1633                          struct hns3_pkt_buf_alloc *buf_alloc)
1634 {
1635         struct hns3_priv_buf *priv;
1636         int cnt = 0;
1637         uint8_t i;
1638
1639         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1640                 priv = &buf_alloc->priv_buf[i];
1641                 if (hw->hw_tc_map & BIT(i) &&
1642                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1643                         cnt++;
1644         }
1645
1646         return cnt;
1647 }
1648
1649 static bool
1650 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
1651                   uint32_t rx_all)
1652 {
1653         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1654         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1655         struct hns3_pf *pf = &hns->pf;
1656         uint32_t shared_buf, aligned_mps;
1657         uint32_t rx_priv;
1658         uint8_t tc_num;
1659         uint8_t i;
1660
1661         tc_num = hns3_get_tc_num(hw);
1662         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1663
1664         if (hns3_dev_dcb_supported(hw))
1665                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
1666                                         pf->dv_buf_size;
1667         else
1668                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
1669                                         + pf->dv_buf_size;
1670
1671         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1672         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
1673                              HNS3_BUF_SIZE_UNIT);
1674
1675         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
1676         if (rx_all < rx_priv + shared_std)
1677                 return false;
1678
1679         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
1680         buf_alloc->s_buf.buf_size = shared_buf;
1681         if (hns3_dev_dcb_supported(hw)) {
1682                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
1683                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1684                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
1685                                   HNS3_BUF_SIZE_UNIT);
1686         } else {
1687                 buf_alloc->s_buf.self.high =
1688                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1689                 buf_alloc->s_buf.self.low = aligned_mps;
1690         }
1691
1692         if (hns3_dev_dcb_supported(hw)) {
1693                 hi_thrd = shared_buf - pf->dv_buf_size;
1694
1695                 if (tc_num <= NEED_RESERVE_TC_NUM)
1696                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1697                                         / BUF_MAX_PERCENT;
1698
1699                 if (tc_num)
1700                         hi_thrd = hi_thrd / tc_num;
1701
1702                 hi_thrd = max_t(uint32_t, hi_thrd,
1703                                 HNS3_BUF_MUL_BY * aligned_mps);
1704                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
1705                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
1706         } else {
1707                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1708                 lo_thrd = aligned_mps;
1709         }
1710
1711         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1712                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
1713                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
1714         }
1715
1716         return true;
1717 }
1718
1719 static bool
1720 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
1721                      struct hns3_pkt_buf_alloc *buf_alloc)
1722 {
1723         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1724         struct hns3_pf *pf = &hns->pf;
1725         struct hns3_priv_buf *priv;
1726         uint32_t aligned_mps;
1727         uint32_t rx_all;
1728         uint8_t i;
1729
1730         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1731         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1732
1733         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1734                 priv = &buf_alloc->priv_buf[i];
1735
1736                 priv->enable = 0;
1737                 priv->wl.low = 0;
1738                 priv->wl.high = 0;
1739                 priv->buf_size = 0;
1740
1741                 if (!(hw->hw_tc_map & BIT(i)))
1742                         continue;
1743
1744                 priv->enable = 1;
1745                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
1746                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
1747                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
1748                                                 HNS3_BUF_SIZE_UNIT);
1749                 } else {
1750                         priv->wl.low = 0;
1751                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
1752                                         aligned_mps;
1753                 }
1754
1755                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
1756         }
1757
1758         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1759 }
1760
1761 static bool
1762 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
1763                              struct hns3_pkt_buf_alloc *buf_alloc)
1764 {
1765         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1766         struct hns3_pf *pf = &hns->pf;
1767         struct hns3_priv_buf *priv;
1768         int no_pfc_priv_num;
1769         uint32_t rx_all;
1770         uint8_t mask;
1771         int i;
1772
1773         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1774         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
1775
1776         /* let the last to be cleared first */
1777         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1778                 priv = &buf_alloc->priv_buf[i];
1779                 mask = BIT((uint8_t)i);
1780
1781                 if (hw->hw_tc_map & mask &&
1782                     !(hw->dcb_info.hw_pfc_map & mask)) {
1783                         /* Clear the no pfc TC private buffer */
1784                         priv->wl.low = 0;
1785                         priv->wl.high = 0;
1786                         priv->buf_size = 0;
1787                         priv->enable = 0;
1788                         no_pfc_priv_num--;
1789                 }
1790
1791                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1792                     no_pfc_priv_num == 0)
1793                         break;
1794         }
1795
1796         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1797 }
1798
1799 static bool
1800 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
1801                            struct hns3_pkt_buf_alloc *buf_alloc)
1802 {
1803         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1804         struct hns3_pf *pf = &hns->pf;
1805         struct hns3_priv_buf *priv;
1806         uint32_t rx_all;
1807         int pfc_priv_num;
1808         uint8_t mask;
1809         int i;
1810
1811         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1812         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
1813
1814         /* let the last to be cleared first */
1815         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1816                 priv = &buf_alloc->priv_buf[i];
1817                 mask = BIT((uint8_t)i);
1818
1819                 if (hw->hw_tc_map & mask &&
1820                     hw->dcb_info.hw_pfc_map & mask) {
1821                         /* Reduce the number of pfc TC with private buffer */
1822                         priv->wl.low = 0;
1823                         priv->enable = 0;
1824                         priv->wl.high = 0;
1825                         priv->buf_size = 0;
1826                         pfc_priv_num--;
1827                 }
1828                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1829                     pfc_priv_num == 0)
1830                         break;
1831         }
1832
1833         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1834 }
1835
1836 static bool
1837 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
1838                           struct hns3_pkt_buf_alloc *buf_alloc)
1839 {
1840 #define COMPENSATE_BUFFER       0x3C00
1841 #define COMPENSATE_HALF_MPS_NUM 5
1842 #define PRIV_WL_GAP             0x1800
1843         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1844         struct hns3_pf *pf = &hns->pf;
1845         uint32_t tc_num = hns3_get_tc_num(hw);
1846         uint32_t half_mps = pf->mps >> 1;
1847         struct hns3_priv_buf *priv;
1848         uint32_t min_rx_priv;
1849         uint32_t rx_priv;
1850         uint8_t i;
1851
1852         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1853         if (tc_num)
1854                 rx_priv = rx_priv / tc_num;
1855
1856         if (tc_num <= NEED_RESERVE_TC_NUM)
1857                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
1858
1859         /*
1860          * Minimum value of private buffer in rx direction (min_rx_priv) is
1861          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
1862          * buffer if rx_priv is greater than min_rx_priv.
1863          */
1864         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
1865                         COMPENSATE_HALF_MPS_NUM * half_mps;
1866         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
1867         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
1868
1869         if (rx_priv < min_rx_priv)
1870                 return false;
1871
1872         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1873                 priv = &buf_alloc->priv_buf[i];
1874
1875                 priv->enable = 0;
1876                 priv->wl.low = 0;
1877                 priv->wl.high = 0;
1878                 priv->buf_size = 0;
1879
1880                 if (!(hw->hw_tc_map & BIT(i)))
1881                         continue;
1882
1883                 priv->enable = 1;
1884                 priv->buf_size = rx_priv;
1885                 priv->wl.high = rx_priv - pf->dv_buf_size;
1886                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
1887         }
1888
1889         buf_alloc->s_buf.buf_size = 0;
1890
1891         return true;
1892 }
1893
1894 /*
1895  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
1896  * @hw: pointer to struct hns3_hw
1897  * @buf_alloc: pointer to buffer calculation data
1898  * @return: 0: calculate sucessful, negative: fail
1899  */
1900 static int
1901 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1902 {
1903         /* When DCB is not supported, rx private buffer is not allocated. */
1904         if (!hns3_dev_dcb_supported(hw)) {
1905                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1906                 struct hns3_pf *pf = &hns->pf;
1907                 uint32_t rx_all = pf->pkt_buf_size;
1908
1909                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
1910                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
1911                         return -ENOMEM;
1912
1913                 return 0;
1914         }
1915
1916         /*
1917          * Try to allocate privated packet buffer for all TCs without share
1918          * buffer.
1919          */
1920         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
1921                 return 0;
1922
1923         /*
1924          * Try to allocate privated packet buffer for all TCs with share
1925          * buffer.
1926          */
1927         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
1928                 return 0;
1929
1930         /*
1931          * For different application scenes, the enabled port number, TC number
1932          * and no_drop TC number are different. In order to obtain the better
1933          * performance, software could allocate the buffer size and configure
1934          * the waterline by tring to decrease the private buffer size according
1935          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
1936          * enabled tc.
1937          */
1938         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
1939                 return 0;
1940
1941         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
1942                 return 0;
1943
1944         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
1945                 return 0;
1946
1947         return -ENOMEM;
1948 }
1949
1950 static int
1951 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1952 {
1953         struct hns3_rx_priv_buff_cmd *req;
1954         struct hns3_cmd_desc desc;
1955         uint32_t buf_size;
1956         int ret;
1957         int i;
1958
1959         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
1960         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
1961
1962         /* Alloc private buffer TCs */
1963         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1964                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
1965
1966                 req->buf_num[i] =
1967                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
1968                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
1969         }
1970
1971         buf_size = buf_alloc->s_buf.buf_size;
1972         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
1973                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
1974
1975         ret = hns3_cmd_send(hw, &desc, 1);
1976         if (ret)
1977                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
1978
1979         return ret;
1980 }
1981
1982 static int
1983 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1984 {
1985 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
1986         struct hns3_rx_priv_wl_buf *req;
1987         struct hns3_priv_buf *priv;
1988         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
1989         int i, j;
1990         int ret;
1991
1992         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
1993                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
1994                                           false);
1995                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
1996
1997                 /* The first descriptor set the NEXT bit to 1 */
1998                 if (i == 0)
1999                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2000                 else
2001                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2002
2003                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2004                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
2005
2006                         priv = &buf_alloc->priv_buf[idx];
2007                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
2008                                                         HNS3_BUF_UNIT_S);
2009                         req->tc_wl[j].high |=
2010                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2011                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
2012                                                         HNS3_BUF_UNIT_S);
2013                         req->tc_wl[j].low |=
2014                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2015                 }
2016         }
2017
2018         /* Send 2 descriptor at one time */
2019         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
2020         if (ret)
2021                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
2022                              ret);
2023         return ret;
2024 }
2025
2026 static int
2027 hns3_common_thrd_config(struct hns3_hw *hw,
2028                         struct hns3_pkt_buf_alloc *buf_alloc)
2029 {
2030 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
2031         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
2032         struct hns3_rx_com_thrd *req;
2033         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
2034         struct hns3_tc_thrd *tc;
2035         int tc_idx;
2036         int i, j;
2037         int ret;
2038
2039         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2040                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2041                                           false);
2042                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2043
2044                 /* The first descriptor set the NEXT bit to 1 */
2045                 if (i == 0)
2046                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2047                 else
2048                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2049
2050                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2051                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2052                         tc = &s_buf->tc_thrd[tc_idx];
2053
2054                         req->com_thrd[j].high =
2055                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2056                         req->com_thrd[j].high |=
2057                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2058                         req->com_thrd[j].low =
2059                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2060                         req->com_thrd[j].low |=
2061                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2062                 }
2063         }
2064
2065         /* Send 2 descriptors at one time */
2066         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2067         if (ret)
2068                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2069
2070         return ret;
2071 }
2072
2073 static int
2074 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2075 {
2076         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2077         struct hns3_rx_com_wl *req;
2078         struct hns3_cmd_desc desc;
2079         int ret;
2080
2081         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2082
2083         req = (struct hns3_rx_com_wl *)desc.data;
2084         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2085         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2086
2087         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2088         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2089
2090         ret = hns3_cmd_send(hw, &desc, 1);
2091         if (ret)
2092                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2093
2094         return ret;
2095 }
2096
2097 int
2098 hns3_buffer_alloc(struct hns3_hw *hw)
2099 {
2100         struct hns3_pkt_buf_alloc pkt_buf;
2101         int ret;
2102
2103         memset(&pkt_buf, 0, sizeof(pkt_buf));
2104         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2105         if (ret) {
2106                 PMD_INIT_LOG(ERR,
2107                              "could not calc tx buffer size for all TCs %d",
2108                              ret);
2109                 return ret;
2110         }
2111
2112         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2113         if (ret) {
2114                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2115                 return ret;
2116         }
2117
2118         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2119         if (ret) {
2120                 PMD_INIT_LOG(ERR,
2121                              "could not calc rx priv buffer size for all TCs %d",
2122                              ret);
2123                 return ret;
2124         }
2125
2126         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2127         if (ret) {
2128                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2129                 return ret;
2130         }
2131
2132         if (hns3_dev_dcb_supported(hw)) {
2133                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2134                 if (ret) {
2135                         PMD_INIT_LOG(ERR,
2136                                      "could not configure rx private waterline %d",
2137                                      ret);
2138                         return ret;
2139                 }
2140
2141                 ret = hns3_common_thrd_config(hw, &pkt_buf);
2142                 if (ret) {
2143                         PMD_INIT_LOG(ERR,
2144                                      "could not configure common threshold %d",
2145                                      ret);
2146                         return ret;
2147                 }
2148         }
2149
2150         ret = hns3_common_wl_config(hw, &pkt_buf);
2151         if (ret)
2152                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2153                              ret);
2154
2155         return ret;
2156 }
2157
2158 static int
2159 hns3_mac_init(struct hns3_hw *hw)
2160 {
2161         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2162         struct hns3_mac *mac = &hw->mac;
2163         struct hns3_pf *pf = &hns->pf;
2164         int ret;
2165
2166         pf->support_sfp_query = true;
2167         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2168         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2169         if (ret) {
2170                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2171                 return ret;
2172         }
2173
2174         mac->link_status = ETH_LINK_DOWN;
2175
2176         return hns3_config_mtu(hw, pf->mps);
2177 }
2178
2179 static int
2180 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2181 {
2182 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2183 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2184 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2185 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2186         int return_status;
2187
2188         if (cmdq_resp) {
2189                 PMD_INIT_LOG(ERR,
2190                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2191                              cmdq_resp);
2192                 return -EIO;
2193         }
2194
2195         switch (resp_code) {
2196         case HNS3_ETHERTYPE_SUCCESS_ADD:
2197         case HNS3_ETHERTYPE_ALREADY_ADD:
2198                 return_status = 0;
2199                 break;
2200         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2201                 PMD_INIT_LOG(ERR,
2202                              "add mac ethertype failed for manager table overflow.");
2203                 return_status = -EIO;
2204                 break;
2205         case HNS3_ETHERTYPE_KEY_CONFLICT:
2206                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2207                 return_status = -EIO;
2208                 break;
2209         default:
2210                 PMD_INIT_LOG(ERR,
2211                              "add mac ethertype failed for undefined, code=%d.",
2212                              resp_code);
2213                 return_status = -EIO;
2214         }
2215
2216         return return_status;
2217 }
2218
2219 static int
2220 hns3_add_mgr_tbl(struct hns3_hw *hw,
2221                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2222 {
2223         struct hns3_cmd_desc desc;
2224         uint8_t resp_code;
2225         uint16_t retval;
2226         int ret;
2227
2228         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2229         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2230
2231         ret = hns3_cmd_send(hw, &desc, 1);
2232         if (ret) {
2233                 PMD_INIT_LOG(ERR,
2234                              "add mac ethertype failed for cmd_send, ret =%d.",
2235                              ret);
2236                 return ret;
2237         }
2238
2239         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2240         retval = rte_le_to_cpu_16(desc.retval);
2241
2242         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2243 }
2244
2245 static void
2246 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2247                      int *table_item_num)
2248 {
2249         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2250
2251         /*
2252          * In current version, we add one item in management table as below:
2253          * 0x0180C200000E -- LLDP MC address
2254          */
2255         tbl = mgr_table;
2256         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2257         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2258         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2259         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2260         tbl->i_port_bitmap = 0x1;
2261         *table_item_num = 1;
2262 }
2263
2264 static int
2265 hns3_init_mgr_tbl(struct hns3_hw *hw)
2266 {
2267 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2268         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2269         int table_item_num;
2270         int ret;
2271         int i;
2272
2273         memset(mgr_table, 0, sizeof(mgr_table));
2274         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2275         for (i = 0; i < table_item_num; i++) {
2276                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2277                 if (ret) {
2278                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2279                                      ret);
2280                         return ret;
2281                 }
2282         }
2283
2284         return 0;
2285 }
2286
2287 static void
2288 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2289                         bool en_mc, bool en_bc, int vport_id)
2290 {
2291         if (!param)
2292                 return;
2293
2294         memset(param, 0, sizeof(struct hns3_promisc_param));
2295         if (en_uc)
2296                 param->enable = HNS3_PROMISC_EN_UC;
2297         if (en_mc)
2298                 param->enable |= HNS3_PROMISC_EN_MC;
2299         if (en_bc)
2300                 param->enable |= HNS3_PROMISC_EN_BC;
2301         param->vf_id = vport_id;
2302 }
2303
2304 static int
2305 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2306 {
2307         struct hns3_promisc_cfg_cmd *req;
2308         struct hns3_cmd_desc desc;
2309         int ret;
2310
2311         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
2312
2313         req = (struct hns3_promisc_cfg_cmd *)desc.data;
2314         req->vf_id = param->vf_id;
2315         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
2316             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
2317
2318         ret = hns3_cmd_send(hw, &desc, 1);
2319         if (ret)
2320                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
2321
2322         return ret;
2323 }
2324
2325 static int
2326 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
2327 {
2328         struct hns3_promisc_param param;
2329         bool en_bc_pmc = true;
2330         uint8_t vf_id;
2331         int ret;
2332
2333         /*
2334          * In current version VF is not supported when PF is driven by DPDK
2335          * driver, the PF-related vf_id is 0, just need to configure parameters
2336          * for vf_id 0.
2337          */
2338         vf_id = 0;
2339
2340         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
2341         ret = hns3_cmd_set_promisc_mode(hw, &param);
2342         if (ret)
2343                 return ret;
2344
2345         return 0;
2346 }
2347
2348 static int
2349 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
2350 {
2351         struct hns3_sfp_speed_cmd *resp;
2352         struct hns3_cmd_desc desc;
2353         int ret;
2354
2355         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
2356         resp = (struct hns3_sfp_speed_cmd *)desc.data;
2357         ret = hns3_cmd_send(hw, &desc, 1);
2358         if (ret == -EOPNOTSUPP) {
2359                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
2360                 return ret;
2361         } else if (ret) {
2362                 hns3_err(hw, "get sfp speed failed %d", ret);
2363                 return ret;
2364         }
2365
2366         *speed = resp->sfp_speed;
2367
2368         return 0;
2369 }
2370
2371 static uint8_t
2372 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
2373 {
2374         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
2375                 duplex = ETH_LINK_FULL_DUPLEX;
2376
2377         return duplex;
2378 }
2379
2380 static int
2381 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2382 {
2383         struct hns3_mac *mac = &hw->mac;
2384         int ret;
2385
2386         duplex = hns3_check_speed_dup(duplex, speed);
2387         if (mac->link_speed == speed && mac->link_duplex == duplex)
2388                 return 0;
2389
2390         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
2391         if (ret)
2392                 return ret;
2393
2394         mac->link_speed = speed;
2395         mac->link_duplex = duplex;
2396
2397         return 0;
2398 }
2399
2400 static int
2401 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
2402 {
2403         struct hns3_adapter *hns = eth_dev->data->dev_private;
2404         struct hns3_hw *hw = &hns->hw;
2405         struct hns3_pf *pf = &hns->pf;
2406         uint32_t speed;
2407         int ret;
2408
2409         /* If IMP do not support get SFP/qSFP speed, return directly */
2410         if (!pf->support_sfp_query)
2411                 return 0;
2412
2413         ret = hns3_get_sfp_speed(hw, &speed);
2414         if (ret == -EOPNOTSUPP) {
2415                 pf->support_sfp_query = false;
2416                 return ret;
2417         } else if (ret)
2418                 return ret;
2419
2420         if (speed == ETH_SPEED_NUM_NONE)
2421                 return 0; /* do nothing if no SFP */
2422
2423         /* Config full duplex for SFP */
2424         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
2425 }
2426
2427 static int
2428 hns3_get_mac_link_status(struct hns3_hw *hw)
2429 {
2430         struct hns3_link_status_cmd *req;
2431         struct hns3_cmd_desc desc;
2432         int link_status;
2433         int ret;
2434
2435         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
2436         ret = hns3_cmd_send(hw, &desc, 1);
2437         if (ret) {
2438                 hns3_err(hw, "get link status cmd failed %d", ret);
2439                 return ret;
2440         }
2441
2442         req = (struct hns3_link_status_cmd *)desc.data;
2443         link_status = req->status & HNS3_LINK_STATUS_UP_M;
2444
2445         return !!link_status;
2446 }
2447
2448 static void
2449 hns3_update_link_status(struct hns3_hw *hw)
2450 {
2451         int state;
2452
2453         state = hns3_get_mac_link_status(hw);
2454         if (state != hw->mac.link_status)
2455                 hw->mac.link_status = state;
2456 }
2457
2458 static void
2459 hns3_service_handler(void *param)
2460 {
2461         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
2462         struct hns3_adapter *hns = eth_dev->data->dev_private;
2463         struct hns3_hw *hw = &hns->hw;
2464
2465         hns3_update_speed_duplex(eth_dev);
2466         hns3_update_link_status(hw);
2467
2468         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2469 }
2470
2471 static int
2472 hns3_init_hardware(struct hns3_adapter *hns)
2473 {
2474         struct hns3_hw *hw = &hns->hw;
2475         int ret;
2476
2477         ret = hns3_map_tqp(hw);
2478         if (ret) {
2479                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
2480                 return ret;
2481         }
2482
2483         ret = hns3_init_umv_space(hw);
2484         if (ret) {
2485                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
2486                 return ret;
2487         }
2488
2489         ret = hns3_mac_init(hw);
2490         if (ret) {
2491                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
2492                 goto err_mac_init;
2493         }
2494
2495         ret = hns3_init_mgr_tbl(hw);
2496         if (ret) {
2497                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
2498                 goto err_mac_init;
2499         }
2500
2501         ret = hns3_set_promisc_mode(hw, false, false);
2502         if (ret) {
2503                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
2504                 goto err_mac_init;
2505         }
2506
2507         ret = hns3_init_fd_config(hns);
2508         if (ret) {
2509                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
2510                 goto err_mac_init;
2511         }
2512
2513         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
2514         if (ret) {
2515                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
2516                 goto err_mac_init;
2517         }
2518
2519         ret = hns3_config_gro(hw, false);
2520         if (ret) {
2521                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
2522                 goto err_mac_init;
2523         }
2524         return 0;
2525
2526 err_mac_init:
2527         hns3_uninit_umv_space(hw);
2528         return ret;
2529 }
2530
2531 static int
2532 hns3_init_pf(struct rte_eth_dev *eth_dev)
2533 {
2534         struct rte_device *dev = eth_dev->device;
2535         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2536         struct hns3_adapter *hns = eth_dev->data->dev_private;
2537         struct hns3_hw *hw = &hns->hw;
2538         int ret;
2539
2540         PMD_INIT_FUNC_TRACE();
2541
2542         /* Get hardware io base address from pcie BAR2 IO space */
2543         hw->io_base = pci_dev->mem_resource[2].addr;
2544
2545         /* Firmware command queue initialize */
2546         ret = hns3_cmd_init_queue(hw);
2547         if (ret) {
2548                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
2549                 goto err_cmd_init_queue;
2550         }
2551
2552         /* Firmware command initialize */
2553         ret = hns3_cmd_init(hw);
2554         if (ret) {
2555                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
2556                 goto err_cmd_init;
2557         }
2558
2559         /* Get configuration */
2560         ret = hns3_get_configuration(hw);
2561         if (ret) {
2562                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2563                 goto err_get_config;
2564         }
2565
2566         ret = hns3_init_hardware(hns);
2567         if (ret) {
2568                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
2569                 goto err_get_config;
2570         }
2571
2572         /* Initialize flow director filter list & hash */
2573         ret = hns3_fdir_filter_init(hns);
2574         if (ret) {
2575                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
2576                 goto err_hw_init;
2577         }
2578
2579         hns3_set_default_rss_args(hw);
2580
2581         return 0;
2582
2583 err_hw_init:
2584         hns3_uninit_umv_space(hw);
2585
2586 err_get_config:
2587         hns3_cmd_uninit(hw);
2588
2589 err_cmd_init:
2590         hns3_cmd_destroy_queue(hw);
2591
2592 err_cmd_init_queue:
2593         hw->io_base = NULL;
2594
2595         return ret;
2596 }
2597
2598 static void
2599 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
2600 {
2601         struct hns3_adapter *hns = eth_dev->data->dev_private;
2602         struct hns3_hw *hw = &hns->hw;
2603
2604         PMD_INIT_FUNC_TRACE();
2605
2606         hns3_rss_uninit(hns);
2607         hns3_fdir_filter_uninit(hns);
2608         hns3_uninit_umv_space(hw);
2609         hns3_cmd_uninit(hw);
2610         hns3_cmd_destroy_queue(hw);
2611         hw->io_base = NULL;
2612 }
2613
2614 static void
2615 hns3_dev_close(struct rte_eth_dev *eth_dev)
2616 {
2617         struct hns3_adapter *hns = eth_dev->data->dev_private;
2618         struct hns3_hw *hw = &hns->hw;
2619
2620         hw->adapter_state = HNS3_NIC_CLOSING;
2621         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
2622
2623         hns3_configure_all_mc_mac_addr(hns, true);
2624         hns3_uninit_pf(eth_dev);
2625         rte_free(eth_dev->process_private);
2626         eth_dev->process_private = NULL;
2627         hw->adapter_state = HNS3_NIC_CLOSED;
2628 }
2629
2630 static const struct eth_dev_ops hns3_eth_dev_ops = {
2631         .dev_close          = hns3_dev_close,
2632         .mtu_set            = hns3_dev_mtu_set,
2633         .dev_infos_get          = hns3_dev_infos_get,
2634         .fw_version_get         = hns3_fw_version_get,
2635         .mac_addr_add           = hns3_add_mac_addr,
2636         .mac_addr_remove        = hns3_remove_mac_addr,
2637         .mac_addr_set           = hns3_set_default_mac_addr,
2638         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
2639         .link_update            = hns3_dev_link_update,
2640         .rss_hash_update        = hns3_dev_rss_hash_update,
2641         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
2642         .reta_update            = hns3_dev_rss_reta_update,
2643         .reta_query             = hns3_dev_rss_reta_query,
2644         .filter_ctrl            = hns3_dev_filter_ctrl,
2645 };
2646
2647 static int
2648 hns3_dev_init(struct rte_eth_dev *eth_dev)
2649 {
2650         struct hns3_adapter *hns = eth_dev->data->dev_private;
2651         struct hns3_hw *hw = &hns->hw;
2652         int ret;
2653
2654         PMD_INIT_FUNC_TRACE();
2655         eth_dev->process_private = (struct hns3_process_private *)
2656             rte_zmalloc_socket("hns3_filter_list",
2657                                sizeof(struct hns3_process_private),
2658                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2659         if (eth_dev->process_private == NULL) {
2660                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2661                 return -ENOMEM;
2662         }
2663         /* initialize flow filter lists */
2664         hns3_filterlist_init(eth_dev);
2665
2666         eth_dev->dev_ops = &hns3_eth_dev_ops;
2667         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2668                 return 0;
2669
2670         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2671         hns->is_vf = false;
2672         hw->data = eth_dev->data;
2673
2674         /*
2675          * Set default max packet size according to the mtu
2676          * default vale in DPDK frame.
2677          */
2678         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
2679
2680         ret = hns3_init_pf(eth_dev);
2681         if (ret) {
2682                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
2683                 goto err_init_pf;
2684         }
2685
2686         /* Allocate memory for storing MAC addresses */
2687         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
2688                                                sizeof(struct rte_ether_addr) *
2689                                                HNS3_UC_MACADDR_NUM, 0);
2690         if (eth_dev->data->mac_addrs == NULL) {
2691                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2692                              "to store MAC addresses",
2693                              sizeof(struct rte_ether_addr) *
2694                              HNS3_UC_MACADDR_NUM);
2695                 ret = -ENOMEM;
2696                 goto err_rte_zmalloc;
2697         }
2698
2699         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2700                             &eth_dev->data->mac_addrs[0]);
2701
2702         hw->adapter_state = HNS3_NIC_INITIALIZED;
2703         /*
2704          * Pass the information to the rte_eth_dev_close() that it should also
2705          * release the private port resources.
2706          */
2707         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2708
2709         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2710         hns3_info(hw, "hns3 dev initialization successful!");
2711         return 0;
2712
2713 err_rte_zmalloc:
2714         hns3_uninit_pf(eth_dev);
2715
2716 err_init_pf:
2717         eth_dev->dev_ops = NULL;
2718         eth_dev->rx_pkt_burst = NULL;
2719         eth_dev->tx_pkt_burst = NULL;
2720         eth_dev->tx_pkt_prepare = NULL;
2721         rte_free(eth_dev->process_private);
2722         eth_dev->process_private = NULL;
2723         return ret;
2724 }
2725
2726 static int
2727 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
2728 {
2729         struct hns3_adapter *hns = eth_dev->data->dev_private;
2730         struct hns3_hw *hw = &hns->hw;
2731
2732         PMD_INIT_FUNC_TRACE();
2733
2734         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2735                 return -EPERM;
2736
2737         eth_dev->dev_ops = NULL;
2738         eth_dev->rx_pkt_burst = NULL;
2739         eth_dev->tx_pkt_burst = NULL;
2740         eth_dev->tx_pkt_prepare = NULL;
2741         if (hw->adapter_state < HNS3_NIC_CLOSING)
2742                 hns3_dev_close(eth_dev);
2743
2744         hw->adapter_state = HNS3_NIC_REMOVED;
2745         return 0;
2746 }
2747
2748 static int
2749 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2750                    struct rte_pci_device *pci_dev)
2751 {
2752         return rte_eth_dev_pci_generic_probe(pci_dev,
2753                                              sizeof(struct hns3_adapter),
2754                                              hns3_dev_init);
2755 }
2756
2757 static int
2758 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
2759 {
2760         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
2761 }
2762
2763 static const struct rte_pci_id pci_id_hns3_map[] = {
2764         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
2765         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
2766         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
2767         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
2768         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
2769         { .vendor_id = 0, /* sentinel */ },
2770 };
2771
2772 static struct rte_pci_driver rte_hns3_pmd = {
2773         .id_table = pci_id_hns3_map,
2774         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2775         .probe = eth_hns3_pci_probe,
2776         .remove = eth_hns3_pci_remove,
2777 };
2778
2779 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
2780 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
2781 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
2782
2783 RTE_INIT(hns3_init_log)
2784 {
2785         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
2786         if (hns3_logtype_init >= 0)
2787                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
2788         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
2789         if (hns3_logtype_driver >= 0)
2790                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
2791 }