drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80
  81 static void
  82 hns3_pf_disable_irq0(struct hns3_hw *hw)
  83 {
  84         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  85 }
  86
  87 static void
  88 hns3_pf_enable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  91 }
  92
  93 static enum hns3_evt_cause
  94 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  95 {
  96         struct hns3_hw *hw = &hns->hw;
  97         uint32_t vector0_int_stats;
  98         uint32_t cmdq_src_val;
  99         uint32_t val;
 100         enum hns3_evt_cause ret;
 101
 102         /* fetch the events from their corresponding regs */
 103         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 104         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 105
 106         /*
 107          * Assumption: If by any chance reset and mailbox events are reported
 108          * together then we will only process reset event and defer the
 109          * processing of the mailbox events. Since, we would have not cleared
 110          * RX CMDQ event this time we would receive again another interrupt
 111          * from H/W just for the mailbox.
 112          */
 113         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 114                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 115                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 116                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 117                 if (clearval) {
 118                         hw->reset.stats.imp_cnt++;
 119                         hns3_warn(hw, "IMP reset detected, clear reset status");
 120                 } else {
 121                         hns3_schedule_delayed_reset(hns);
 122                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 123                 }
 124
 125                 ret = HNS3_VECTOR0_EVENT_RST;
 126                 goto out;
 127         }
 128
 129         /* Global reset */
 130         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 131                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 132                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 133                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 134                 if (clearval) {
 135                         hw->reset.stats.global_cnt++;
 136                         hns3_warn(hw, "Global reset detected, clear reset status");
 137                 } else {
 138                         hns3_schedule_delayed_reset(hns);
 139                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 140                 }
 141
 142                 ret = HNS3_VECTOR0_EVENT_RST;
 143                 goto out;
 144         }
 145
 146         /* check for vector0 msix event source */
 147         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 148                 val = vector0_int_stats;
 149                 ret = HNS3_VECTOR0_EVENT_ERR;
 150                 goto out;
 151         }
 152
 153         /* check for vector0 mailbox(=CMDQ RX) event source */
 154         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 155                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 156                 val = cmdq_src_val;
 157                 ret = HNS3_VECTOR0_EVENT_MBX;
 158                 goto out;
 159         }
 160
 161         if (clearval && (vector0_int_stats || cmdq_src_val))
 162                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 163                           vector0_int_stats, cmdq_src_val);
 164         val = vector0_int_stats;
 165         ret = HNS3_VECTOR0_EVENT_OTHER;
 166 out:
 167
 168         if (clearval)
 169                 *clearval = val;
 170         return ret;
 171 }
 172
 173 static void
 174 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 175 {
 176         if (event_type == HNS3_VECTOR0_EVENT_RST)
 177                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 178         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 179                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 180 }
 181
 182 static void
 183 hns3_clear_all_event_cause(struct hns3_hw *hw)
 184 {
 185         uint32_t vector0_int_stats;
 186         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 187
 188         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 189                 hns3_warn(hw, "Probe during IMP reset interrupt");
 190
 191         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 192                 hns3_warn(hw, "Probe during Global reset interrupt");
 193
 194         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 195                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 196                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 198         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 199 }
 200
 201 static void
 202 hns3_interrupt_handler(void *param)
 203 {
 204         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 205         struct hns3_adapter *hns = dev->data->dev_private;
 206         struct hns3_hw *hw = &hns->hw;
 207         enum hns3_evt_cause event_cause;
 208         uint32_t clearval = 0;
 209
 210         /* Disable interrupt */
 211         hns3_pf_disable_irq0(hw);
 212
 213         event_cause = hns3_check_event_cause(hns, &clearval);
 214
 215         /* vector 0 interrupt is shared with reset and mailbox source events. */
 216         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 217                 hns3_handle_msix_error(hns, &hw->reset.request);
 218                 hns3_schedule_reset(hns);
 219         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 220                 hns3_schedule_reset(hns);
 221         else
 222                 hns3_err(hw, "Received unknown event");
 223
 224         hns3_clear_event_cause(hw, event_cause, clearval);
 225         /* Enable interrupt if it is not cause by reset */
 226         hns3_pf_enable_irq0(hw);
 227 }
 228
 229 static int
 230 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 231 {
 232 #define HNS3_VLAN_OFFSET_160            160
 233         struct hns3_vlan_filter_pf_cfg_cmd *req;
 234         struct hns3_hw *hw = &hns->hw;
 235         uint8_t vlan_offset_byte_val;
 236         struct hns3_cmd_desc desc;
 237         uint8_t vlan_offset_byte;
 238         uint8_t vlan_offset_160;
 239         int ret;
 240
 241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 242
 243         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 244         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 245         vlan_offset_byte_val = 1 << (vlan_id % 8);
 246
 247         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 248         req->vlan_offset = vlan_offset_160;
 249         req->vlan_cfg = on ? 0 : 1;
 250         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 251
 252         ret = hns3_cmd_send(hw, &desc, 1);
 253         if (ret)
 254                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 255                          vlan_id, ret);
 256
 257         return ret;
 258 }
 259
 260 static void
 261 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 262 {
 263         struct hns3_user_vlan_table *vlan_entry;
 264         struct hns3_pf *pf = &hns->pf;
 265
 266         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 267                 if (vlan_entry->vlan_id == vlan_id) {
 268                         if (vlan_entry->hd_tbl_status)
 269                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 270                         LIST_REMOVE(vlan_entry, next);
 271                         rte_free(vlan_entry);
 272                         break;
 273                 }
 274         }
 275 }
 276
 277 static void
 278 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 279                         bool writen_to_tbl)
 280 {
 281         struct hns3_user_vlan_table *vlan_entry;
 282         struct hns3_hw *hw = &hns->hw;
 283         struct hns3_pf *pf = &hns->pf;
 284
 285         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 286                 if (vlan_entry->vlan_id == vlan_id)
 287                         return;
 288         }
 289
 290         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 291         if (vlan_entry == NULL) {
 292                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 293                 return;
 294         }
 295
 296         vlan_entry->hd_tbl_status = writen_to_tbl;
 297         vlan_entry->vlan_id = vlan_id;
 298
 299         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 300 }
 301
 302 static int
 303 hns3_restore_vlan_table(struct hns3_adapter *hns)
 304 {
 305         struct hns3_user_vlan_table *vlan_entry;
 306         struct hns3_pf *pf = &hns->pf;
 307         uint16_t vlan_id;
 308         int ret = 0;
 309
 310         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 311                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 312                                                1);
 313                 return ret;
 314         }
 315
 316         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 317                 if (vlan_entry->hd_tbl_status) {
 318                         vlan_id = vlan_entry->vlan_id;
 319                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 320                         if (ret)
 321                                 break;
 322                 }
 323         }
 324
 325         return ret;
 326 }
 327
 328 static int
 329 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 330 {
 331         struct hns3_pf *pf = &hns->pf;
 332         bool writen_to_tbl = false;
 333         int ret = 0;
 334
 335         /*
 336          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 337          * for normal packet, deleting vlan id 0 is not allowed.
 338          */
 339         if (on == 0 && vlan_id == 0)
 340                 return 0;
 341
 342         /*
 343          * When port base vlan enabled, we use port base vlan as the vlan
 344          * filter condition. In this case, we don't update vlan filter table
 345          * when user add new vlan or remove exist vlan, just update the
 346          * vlan list. The vlan id in vlan list will be writen in vlan filter
 347          * table until port base vlan disabled
 348          */
 349         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 350                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 351                 writen_to_tbl = true;
 352         }
 353
 354         if (ret == 0 && vlan_id) {
 355                 if (on)
 356                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 357                 else
 358                         hns3_rm_dev_vlan_table(hns, vlan_id);
 359         }
 360         return ret;
 361 }
 362
 363 static int
 364 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 365 {
 366         struct hns3_adapter *hns = dev->data->dev_private;
 367         struct hns3_hw *hw = &hns->hw;
 368         int ret;
 369
 370         rte_spinlock_lock(&hw->lock);
 371         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 372         rte_spinlock_unlock(&hw->lock);
 373         return ret;
 374 }
 375
 376 static int
 377 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 378                          uint16_t tpid)
 379 {
 380         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 381         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 382         struct hns3_hw *hw = &hns->hw;
 383         struct hns3_cmd_desc desc;
 384         int ret;
 385
 386         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 387              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 388                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 389                 return -EINVAL;
 390         }
 391
 392         if (tpid != RTE_ETHER_TYPE_VLAN) {
 393                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 394                 return -EINVAL;
 395         }
 396
 397         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 398         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 399
 400         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 401                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 402                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 403         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 407                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 408         }
 409
 410         ret = hns3_cmd_send(hw, &desc, 1);
 411         if (ret) {
 412                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 413                          ret);
 414                 return ret;
 415         }
 416
 417         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 418
 419         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 420         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 421         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 422
 423         ret = hns3_cmd_send(hw, &desc, 1);
 424         if (ret)
 425                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 426                          ret);
 427         return ret;
 428 }
 429
 430 static int
 431 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 432                    uint16_t tpid)
 433 {
 434         struct hns3_adapter *hns = dev->data->dev_private;
 435         struct hns3_hw *hw = &hns->hw;
 436         int ret;
 437
 438         rte_spinlock_lock(&hw->lock);
 439         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 440         rte_spinlock_unlock(&hw->lock);
 441         return ret;
 442 }
 443
 444 static int
 445 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 446                              struct hns3_rx_vtag_cfg *vcfg)
 447 {
 448         struct hns3_vport_vtag_rx_cfg_cmd *req;
 449         struct hns3_hw *hw = &hns->hw;
 450         struct hns3_cmd_desc desc;
 451         uint16_t vport_id;
 452         uint8_t bitmap;
 453         int ret;
 454
 455         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 456
 457         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 458         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 459                      vcfg->strip_tag1_en ? 1 : 0);
 460         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 461                      vcfg->strip_tag2_en ? 1 : 0);
 462         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 463                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 464         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 465                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 466
 467         /*
 468          * In current version VF is not supported when PF is driven by DPDK
 469          * driver, the PF-related vf_id is 0, just need to configure parameters
 470          * for vport_id 0.
 471          */
 472         vport_id = 0;
 473         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 474         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 475         req->vf_bitmap[req->vf_offset] = bitmap;
 476
 477         ret = hns3_cmd_send(hw, &desc, 1);
 478         if (ret)
 479                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 480         return ret;
 481 }
 482
 483 static void
 484 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 485                            struct hns3_rx_vtag_cfg *vcfg)
 486 {
 487         struct hns3_pf *pf = &hns->pf;
 488         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 489 }
 490
 491 static void
 492 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 493                            struct hns3_tx_vtag_cfg *vcfg)
 494 {
 495         struct hns3_pf *pf = &hns->pf;
 496         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 497 }
 498
 499 static int
 500 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 501 {
 502         struct hns3_rx_vtag_cfg rxvlan_cfg;
 503         struct hns3_pf *pf = &hns->pf;
 504         struct hns3_hw *hw = &hns->hw;
 505         int ret;
 506
 507         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 508                 rxvlan_cfg.strip_tag1_en = false;
 509                 rxvlan_cfg.strip_tag2_en = enable;
 510         } else {
 511                 rxvlan_cfg.strip_tag1_en = enable;
 512                 rxvlan_cfg.strip_tag2_en = true;
 513         }
 514
 515         rxvlan_cfg.vlan1_vlan_prionly = false;
 516         rxvlan_cfg.vlan2_vlan_prionly = false;
 517         rxvlan_cfg.rx_vlan_offload_en = enable;
 518
 519         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 520         if (ret) {
 521                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 522                 return ret;
 523         }
 524
 525         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 526
 527         return ret;
 528 }
 529
 530 static int
 531 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 532                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 533 {
 534         struct hns3_vlan_filter_ctrl_cmd *req;
 535         struct hns3_cmd_desc desc;
 536         int ret;
 537
 538         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 539
 540         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 541         req->vlan_type = vlan_type;
 542         req->vlan_fe = filter_en ? fe_type : 0;
 543         req->vf_id = vf_id;
 544
 545         ret = hns3_cmd_send(hw, &desc, 1);
 546         if (ret)
 547                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 548
 549         return ret;
 550 }
 551
 552 static int
 553 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 554 {
 555         struct hns3_hw *hw = &hns->hw;
 556         int ret;
 557
 558         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 559                                         HNS3_FILTER_FE_EGRESS, false, 0);
 560         if (ret) {
 561                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 562                 return ret;
 563         }
 564
 565         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 566                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 567         if (ret)
 568                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 569
 570         return ret;
 571 }
 572
 573 static int
 574 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 575 {
 576         struct hns3_adapter *hns = dev->data->dev_private;
 577         struct hns3_hw *hw = &hns->hw;
 578         struct rte_eth_rxmode *rxmode;
 579         unsigned int tmp_mask;
 580         bool enable;
 581         int ret = 0;
 582
 583         rte_spinlock_lock(&hw->lock);
 584         rxmode = &dev->data->dev_conf.rxmode;
 585         tmp_mask = (unsigned int)mask;
 586         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 587                 /* Enable or disable VLAN stripping */
 588                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 589                     true : false;
 590
 591                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 592                 if (ret) {
 593                         rte_spinlock_unlock(&hw->lock);
 594                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 595                         return ret;
 596                 }
 597         }
 598
 599         rte_spinlock_unlock(&hw->lock);
 600
 601         return ret;
 602 }
 603
 604 static int
 605 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 606                              struct hns3_tx_vtag_cfg *vcfg)
 607 {
 608         struct hns3_vport_vtag_tx_cfg_cmd *req;
 609         struct hns3_cmd_desc desc;
 610         struct hns3_hw *hw = &hns->hw;
 611         uint16_t vport_id;
 612         uint8_t bitmap;
 613         int ret;
 614
 615         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 616
 617         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 618         req->def_vlan_tag1 = vcfg->default_tag1;
 619         req->def_vlan_tag2 = vcfg->default_tag2;
 620         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 621                      vcfg->accept_tag1 ? 1 : 0);
 622         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 623                      vcfg->accept_untag1 ? 1 : 0);
 624         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 625                      vcfg->accept_tag2 ? 1 : 0);
 626         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 627                      vcfg->accept_untag2 ? 1 : 0);
 628         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 629                      vcfg->insert_tag1_en ? 1 : 0);
 630         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 631                      vcfg->insert_tag2_en ? 1 : 0);
 632         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 633
 634         /*
 635          * In current version VF is not supported when PF is driven by DPDK
 636          * driver, the PF-related vf_id is 0, just need to configure parameters
 637          * for vport_id 0.
 638          */
 639         vport_id = 0;
 640         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 641         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 642         req->vf_bitmap[req->vf_offset] = bitmap;
 643
 644         ret = hns3_cmd_send(hw, &desc, 1);
 645         if (ret)
 646                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 647
 648         return ret;
 649 }
 650
 651 static int
 652 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 653                      uint16_t pvid)
 654 {
 655         struct hns3_hw *hw = &hns->hw;
 656         struct hns3_tx_vtag_cfg txvlan_cfg;
 657         int ret;
 658
 659         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 660                 txvlan_cfg.accept_tag1 = true;
 661                 txvlan_cfg.insert_tag1_en = false;
 662                 txvlan_cfg.default_tag1 = 0;
 663         } else {
 664                 txvlan_cfg.accept_tag1 = false;
 665                 txvlan_cfg.insert_tag1_en = true;
 666                 txvlan_cfg.default_tag1 = pvid;
 667         }
 668
 669         txvlan_cfg.accept_untag1 = true;
 670         txvlan_cfg.accept_tag2 = true;
 671         txvlan_cfg.accept_untag2 = true;
 672         txvlan_cfg.insert_tag2_en = false;
 673         txvlan_cfg.default_tag2 = 0;
 674
 675         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 676         if (ret) {
 677                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 678                          ret);
 679                 return ret;
 680         }
 681
 682         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 683         return ret;
 684 }
 685
 686 static void
 687 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 688 {
 689         struct hns3_pf *pf = &hns->pf;
 690
 691         pf->port_base_vlan_cfg.state = on ?
 692             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 693
 694         pf->port_base_vlan_cfg.pvid = pvid;
 695 }
 696
 697 static void
 698 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 699 {
 700         struct hns3_user_vlan_table *vlan_entry;
 701         struct hns3_pf *pf = &hns->pf;
 702
 703         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 704                 if (vlan_entry->hd_tbl_status)
 705                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 706
 707                 vlan_entry->hd_tbl_status = false;
 708         }
 709
 710         if (is_del_list) {
 711                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 712                 while (vlan_entry) {
 713                         LIST_REMOVE(vlan_entry, next);
 714                         rte_free(vlan_entry);
 715                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 716                 }
 717         }
 718 }
 719
 720 static void
 721 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 722 {
 723         struct hns3_user_vlan_table *vlan_entry;
 724         struct hns3_pf *pf = &hns->pf;
 725
 726         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 727                 if (!vlan_entry->hd_tbl_status)
 728                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 729
 730                 vlan_entry->hd_tbl_status = true;
 731         }
 732 }
 733
 734 static void
 735 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 736 {
 737         struct hns3_hw *hw = &hns->hw;
 738         struct hns3_pf *pf = &hns->pf;
 739         int ret;
 740
 741         hns3_rm_all_vlan_table(hns, true);
 742         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 743                 ret = hns3_set_port_vlan_filter(hns,
 744                                                 pf->port_base_vlan_cfg.pvid, 0);
 745                 if (ret) {
 746                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 747                                  ret);
 748                         return;
 749                 }
 750         }
 751 }
 752
 753 static int
 754 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 755                                 uint16_t port_base_vlan_state,
 756                                 uint16_t new_pvid, uint16_t old_pvid)
 757 {
 758         struct hns3_pf *pf = &hns->pf;
 759         struct hns3_hw *hw = &hns->hw;
 760         int ret = 0;
 761
 762         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 763                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 764                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 765                         if (ret) {
 766                                 hns3_err(hw,
 767                                          "Failed to clear clear old pvid filter, ret =%d",
 768                                          ret);
 769                                 return ret;
 770                         }
 771                 }
 772
 773                 hns3_rm_all_vlan_table(hns, false);
 774                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 775         }
 776
 777         if (new_pvid != 0) {
 778                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 779                 if (ret) {
 780                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 781                                  ret);
 782                         return ret;
 783                 }
 784         }
 785
 786         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 787                 hns3_add_all_vlan_table(hns);
 788
 789         return ret;
 790 }
 791
 792 static int
 793 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 794 {
 795         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 796         struct hns3_hw *hw = &hns->hw;
 797         bool rx_strip_en;
 798         int ret;
 799
 800         rx_strip_en = on ? true : false;
 801         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 802         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 803         rx_vlan_cfg.vlan1_vlan_prionly = false;
 804         rx_vlan_cfg.vlan2_vlan_prionly = false;
 805         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 806
 807         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 808         if (ret) {
 809                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 810                 return ret;
 811         }
 812
 813         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 814         return ret;
 815 }
 816
 817 static int
 818 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 819 {
 820         struct hns3_pf *pf = &hns->pf;
 821         struct hns3_hw *hw = &hns->hw;
 822         uint16_t port_base_vlan_state;
 823         uint16_t old_pvid;
 824         int ret;
 825
 826         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 827                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 828                         hns3_warn(hw, "Invalid operation! As current pvid set "
 829                                   "is %u, disable pvid %u is invalid",
 830                                   pf->port_base_vlan_cfg.pvid, pvid);
 831                 return 0;
 832         }
 833
 834         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 835                                     HNS3_PORT_BASE_VLAN_DISABLE;
 836         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 837         if (ret) {
 838                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 839                 return ret;
 840         }
 841
 842         ret = hns3_en_rx_strip_all(hns, on);
 843         if (ret) {
 844                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 845                 return ret;
 846         }
 847
 848         if (pvid == HNS3_INVLID_PVID)
 849                 goto out;
 850         old_pvid = pf->port_base_vlan_cfg.pvid;
 851         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 852                                               old_pvid);
 853         if (ret) {
 854                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 855                          ret);
 856                 return ret;
 857         }
 858
 859 out:
 860         hns3_store_port_base_vlan_info(hns, pvid, on);
 861         return ret;
 862 }
 863
 864 static int
 865 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 866 {
 867         struct hns3_adapter *hns = dev->data->dev_private;
 868         struct hns3_hw *hw = &hns->hw;
 869         int ret;
 870
 871         rte_spinlock_lock(&hw->lock);
 872         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 873         rte_spinlock_unlock(&hw->lock);
 874         return ret;
 875 }
 876
 877 static void
 878 init_port_base_vlan_info(struct hns3_hw *hw)
 879 {
 880         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 881         struct hns3_pf *pf = &hns->pf;
 882
 883         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 884         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 885 }
 886
 887 static int
 888 hns3_default_vlan_config(struct hns3_adapter *hns)
 889 {
 890         struct hns3_hw *hw = &hns->hw;
 891         int ret;
 892
 893         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 894         if (ret)
 895                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 896         return ret;
 897 }
 898
 899 static int
 900 hns3_init_vlan_config(struct hns3_adapter *hns)
 901 {
 902         struct hns3_hw *hw = &hns->hw;
 903         int ret;
 904
 905         /*
 906          * This function can be called in the initialization and reset process,
 907          * when in reset process, it means that hardware had been reseted
 908          * successfully and we need to restore the hardware configuration to
 909          * ensure that the hardware configuration remains unchanged before and
 910          * after reset.
 911          */
 912         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 913                 init_port_base_vlan_info(hw);
 914
 915         ret = hns3_enable_vlan_filter(hns, true);
 916         if (ret) {
 917                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 918                 return ret;
 919         }
 920
 921         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 922                                        RTE_ETHER_TYPE_VLAN);
 923         if (ret) {
 924                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 925                 return ret;
 926         }
 927
 928         /*
 929          * When in the reinit dev stage of the reset process, the following
 930          * vlan-related configurations may differ from those at initialization,
 931          * we will restore configurations to hardware in hns3_restore_vlan_table
 932          * and hns3_restore_vlan_conf later.
 933          */
 934         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 935                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 936                 if (ret) {
 937                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 938                         return ret;
 939                 }
 940
 941                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 942                 if (ret) {
 943                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 944                                  ret);
 945                         return ret;
 946                 }
 947         }
 948
 949         return hns3_default_vlan_config(hns);
 950 }
 951
 952 static int
 953 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 954 {
 955         struct hns3_pf *pf = &hns->pf;
 956         struct hns3_hw *hw = &hns->hw;
 957         int ret;
 958
 959         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 960         if (ret) {
 961                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 962                 return ret;
 963         }
 964
 965         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 966         if (ret)
 967                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 968
 969         return ret;
 970 }
 971
 972 static int
 973 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 974 {
 975         struct hns3_adapter *hns = dev->data->dev_private;
 976         struct rte_eth_dev_data *data = dev->data;
 977         struct rte_eth_txmode *txmode;
 978         struct hns3_hw *hw = &hns->hw;
 979         int ret;
 980
 981         txmode = &data->dev_conf.txmode;
 982         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 983                 hns3_warn(hw,
 984                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 985                           "configuration is not supported! Ignore these two "
 986                           "parameters: hw_vlan_reject_tagged(%d), "
 987                           "hw_vlan_reject_untagged(%d)",
 988                           txmode->hw_vlan_reject_tagged,
 989                           txmode->hw_vlan_reject_untagged);
 990
 991         /* Apply vlan offload setting */
 992         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 993         if (ret) {
 994                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 995                 return ret;
 996         }
 997
 998         /* Apply pvid setting */
 999         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1000                                  txmode->hw_vlan_insert_pvid);
1001         if (ret)
1002                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1003                          txmode->pvid, ret);
1004
1005         return ret;
1006 }
1007
1008 static int
1009 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1010                 unsigned int tso_mss_max)
1011 {
1012         struct hns3_cfg_tso_status_cmd *req;
1013         struct hns3_cmd_desc desc;
1014         uint16_t tso_mss;
1015
1016         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1017
1018         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1019
1020         tso_mss = 0;
1021         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1022                        tso_mss_min);
1023         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1024
1025         tso_mss = 0;
1026         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1027                        tso_mss_max);
1028         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1029
1030         return hns3_cmd_send(hw, &desc, 1);
1031 }
1032
1033 int
1034 hns3_config_gro(struct hns3_hw *hw, bool en)
1035 {
1036         struct hns3_cfg_gro_status_cmd *req;
1037         struct hns3_cmd_desc desc;
1038         int ret;
1039
1040         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1041         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1042
1043         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1044
1045         ret = hns3_cmd_send(hw, &desc, 1);
1046         if (ret)
1047                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1048
1049         return ret;
1050 }
1051
1052 static int
1053 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1054                    uint16_t *allocated_size, bool is_alloc)
1055 {
1056         struct hns3_umv_spc_alc_cmd *req;
1057         struct hns3_cmd_desc desc;
1058         int ret;
1059
1060         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1061         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1062         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1063         req->space_size = rte_cpu_to_le_32(space_size);
1064
1065         ret = hns3_cmd_send(hw, &desc, 1);
1066         if (ret) {
1067                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1068                              is_alloc ? "allocate" : "free", ret);
1069                 return ret;
1070         }
1071
1072         if (is_alloc && allocated_size)
1073                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1074
1075         return 0;
1076 }
1077
1078 static int
1079 hns3_init_umv_space(struct hns3_hw *hw)
1080 {
1081         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1082         struct hns3_pf *pf = &hns->pf;
1083         uint16_t allocated_size = 0;
1084         int ret;
1085
1086         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1087                                  true);
1088         if (ret)
1089                 return ret;
1090
1091         if (allocated_size < pf->wanted_umv_size)
1092                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1093                              pf->wanted_umv_size, allocated_size);
1094
1095         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1096                                                 pf->wanted_umv_size;
1097         pf->used_umv_size = 0;
1098         return 0;
1099 }
1100
1101 static int
1102 hns3_uninit_umv_space(struct hns3_hw *hw)
1103 {
1104         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1105         struct hns3_pf *pf = &hns->pf;
1106         int ret;
1107
1108         if (pf->max_umv_size == 0)
1109                 return 0;
1110
1111         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1112         if (ret)
1113                 return ret;
1114
1115         pf->max_umv_size = 0;
1116
1117         return 0;
1118 }
1119
1120 static bool
1121 hns3_is_umv_space_full(struct hns3_hw *hw)
1122 {
1123         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1124         struct hns3_pf *pf = &hns->pf;
1125         bool is_full;
1126
1127         is_full = (pf->used_umv_size >= pf->max_umv_size);
1128
1129         return is_full;
1130 }
1131
1132 static void
1133 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1134 {
1135         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1136         struct hns3_pf *pf = &hns->pf;
1137
1138         if (is_free) {
1139                 if (pf->used_umv_size > 0)
1140                         pf->used_umv_size--;
1141         } else
1142                 pf->used_umv_size++;
1143 }
1144
1145 static void
1146 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1147                       const uint8_t *addr, bool is_mc)
1148 {
1149         const unsigned char *mac_addr = addr;
1150         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1151                             ((uint32_t)mac_addr[2] << 16) |
1152                             ((uint32_t)mac_addr[1] << 8) |
1153                             (uint32_t)mac_addr[0];
1154         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1155
1156         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1157         if (is_mc) {
1158                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1159                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1160                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1161         }
1162
1163         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1164         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1165 }
1166
1167 static int
1168 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1169                              uint8_t resp_code,
1170                              enum hns3_mac_vlan_tbl_opcode op)
1171 {
1172         if (cmdq_resp) {
1173                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1174                          cmdq_resp);
1175                 return -EIO;
1176         }
1177
1178         if (op == HNS3_MAC_VLAN_ADD) {
1179                 if (resp_code == 0 || resp_code == 1) {
1180                         return 0;
1181                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1182                         hns3_err(hw, "add mac addr failed for uc_overflow");
1183                         return -ENOSPC;
1184                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1185                         hns3_err(hw, "add mac addr failed for mc_overflow");
1186                         return -ENOSPC;
1187                 }
1188
1189                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1190                          resp_code);
1191                 return -EIO;
1192         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1193                 if (resp_code == 0) {
1194                         return 0;
1195                 } else if (resp_code == 1) {
1196                         hns3_dbg(hw, "remove mac addr failed for miss");
1197                         return -ENOENT;
1198                 }
1199
1200                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1201                          resp_code);
1202                 return -EIO;
1203         } else if (op == HNS3_MAC_VLAN_LKUP) {
1204                 if (resp_code == 0) {
1205                         return 0;
1206                 } else if (resp_code == 1) {
1207                         hns3_dbg(hw, "lookup mac addr failed for miss");
1208                         return -ENOENT;
1209                 }
1210
1211                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1212                          resp_code);
1213                 return -EIO;
1214         }
1215
1216         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1217                  op);
1218
1219         return -EINVAL;
1220 }
1221
1222 static int
1223 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1224                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1225                          struct hns3_cmd_desc *desc, bool is_mc)
1226 {
1227         uint8_t resp_code;
1228         uint16_t retval;
1229         int ret;
1230
1231         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1232         if (is_mc) {
1233                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1234                 memcpy(desc[0].data, req,
1235                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1236                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1237                                           true);
1238                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1239                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1240                                           true);
1241                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1242         } else {
1243                 memcpy(desc[0].data, req,
1244                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1245                 ret = hns3_cmd_send(hw, desc, 1);
1246         }
1247         if (ret) {
1248                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1249                          ret);
1250                 return ret;
1251         }
1252         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1253         retval = rte_le_to_cpu_16(desc[0].retval);
1254
1255         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1256                                             HNS3_MAC_VLAN_LKUP);
1257 }
1258
1259 static int
1260 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1261                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1262                       struct hns3_cmd_desc *mc_desc)
1263 {
1264         uint8_t resp_code;
1265         uint16_t retval;
1266         int cfg_status;
1267         int ret;
1268
1269         if (mc_desc == NULL) {
1270                 struct hns3_cmd_desc desc;
1271
1272                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1273                 memcpy(desc.data, req,
1274                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1275                 ret = hns3_cmd_send(hw, &desc, 1);
1276                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1277                 retval = rte_le_to_cpu_16(desc.retval);
1278
1279                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1280                                                           HNS3_MAC_VLAN_ADD);
1281         } else {
1282                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1283                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1284                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1285                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1286                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1287                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1288                 memcpy(mc_desc[0].data, req,
1289                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1290                 mc_desc[0].retval = 0;
1291                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1292                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1293                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1294
1295                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1296                                                           HNS3_MAC_VLAN_ADD);
1297         }
1298
1299         if (ret) {
1300                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1301                 return ret;
1302         }
1303
1304         return cfg_status;
1305 }
1306
1307 static int
1308 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1309                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1310 {
1311         struct hns3_cmd_desc desc;
1312         uint8_t resp_code;
1313         uint16_t retval;
1314         int ret;
1315
1316         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1317
1318         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1319
1320         ret = hns3_cmd_send(hw, &desc, 1);
1321         if (ret) {
1322                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1323                 return ret;
1324         }
1325         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1326         retval = rte_le_to_cpu_16(desc.retval);
1327
1328         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1329                                             HNS3_MAC_VLAN_REMOVE);
1330 }
1331
1332 static int
1333 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1334 {
1335         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1336         struct hns3_mac_vlan_tbl_entry_cmd req;
1337         struct hns3_pf *pf = &hns->pf;
1338         struct hns3_cmd_desc desc;
1339         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1340         uint16_t egress_port = 0;
1341         uint8_t vf_id;
1342         int ret;
1343
1344         /* check if mac addr is valid */
1345         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1346                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1347                                       mac_addr);
1348                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1349                          mac_str);
1350                 return -EINVAL;
1351         }
1352
1353         memset(&req, 0, sizeof(req));
1354
1355         /*
1356          * In current version VF is not supported when PF is driven by DPDK
1357          * driver, the PF-related vf_id is 0, just need to configure parameters
1358          * for vf_id 0.
1359          */
1360         vf_id = 0;
1361         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1362                        HNS3_MAC_EPORT_VFID_S, vf_id);
1363
1364         req.egress_port = rte_cpu_to_le_16(egress_port);
1365
1366         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1367
1368         /*
1369          * Lookup the mac address in the mac_vlan table, and add
1370          * it if the entry is inexistent. Repeated unicast entry
1371          * is not allowed in the mac vlan table.
1372          */
1373         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1374         if (ret == -ENOENT) {
1375                 if (!hns3_is_umv_space_full(hw)) {
1376                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1377                         if (!ret)
1378                                 hns3_update_umv_space(hw, false);
1379                         return ret;
1380                 }
1381
1382                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1383
1384                 return -ENOSPC;
1385         }
1386
1387         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1388
1389         /* check if we just hit the duplicate */
1390         if (ret == 0) {
1391                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1392                 return 0;
1393         }
1394
1395         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1396                  mac_str);
1397
1398         return ret;
1399 }
1400
1401 static int
1402 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1403                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1404 {
1405         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1407         int ret;
1408
1409         rte_spinlock_lock(&hw->lock);
1410         ret = hns3_add_uc_addr_common(hw, mac_addr);
1411         if (ret) {
1412                 rte_spinlock_unlock(&hw->lock);
1413                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1414                                       mac_addr);
1415                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1416                 return ret;
1417         }
1418
1419         if (idx == 0)
1420                 hw->mac.default_addr_setted = true;
1421         rte_spinlock_unlock(&hw->lock);
1422
1423         return ret;
1424 }
1425
1426 static int
1427 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1428 {
1429         struct hns3_mac_vlan_tbl_entry_cmd req;
1430         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1431         int ret;
1432
1433         /* check if mac addr is valid */
1434         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1435                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1436                                       mac_addr);
1437                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1438                          mac_str);
1439                 return -EINVAL;
1440         }
1441
1442         memset(&req, 0, sizeof(req));
1443         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1444         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1445         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1446         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1447                 return 0;
1448         else if (ret == 0)
1449                 hns3_update_umv_space(hw, true);
1450
1451         return ret;
1452 }
1453
1454 static void
1455 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1456 {
1457         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1458         /* index will be checked by upper level rte interface */
1459         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1460         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1461         int ret;
1462
1463         rte_spinlock_lock(&hw->lock);
1464         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1465         if (ret) {
1466                 rte_spinlock_unlock(&hw->lock);
1467                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1468                                       mac_addr);
1469                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1470                 return;
1471         }
1472
1473         if (idx == 0)
1474                 hw->mac.default_addr_setted = false;
1475         rte_spinlock_unlock(&hw->lock);
1476 }
1477
1478 static int
1479 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1480                           struct rte_ether_addr *mac_addr)
1481 {
1482         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1483         struct rte_ether_addr *oaddr;
1484         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1485         bool default_addr_setted;
1486         bool rm_succes = false;
1487         int ret, ret_val;
1488
1489         /* check if mac addr is valid */
1490         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1491                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1492                                       mac_addr);
1493                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1494                          mac_str);
1495                 return -EINVAL;
1496         }
1497
1498         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1499         default_addr_setted = hw->mac.default_addr_setted;
1500         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1501                 return 0;
1502
1503         rte_spinlock_lock(&hw->lock);
1504         if (default_addr_setted) {
1505                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1506                 if (ret) {
1507                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1508                                               oaddr);
1509                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1510                                   mac_str, ret);
1511                         rm_succes = false;
1512                 } else
1513                         rm_succes = true;
1514         }
1515
1516         ret = hns3_add_uc_addr_common(hw, mac_addr);
1517         if (ret) {
1518                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1519                                       mac_addr);
1520                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1521                 goto err_add_uc_addr;
1522         }
1523
1524         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1525         if (ret) {
1526                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1527                 goto err_pause_addr_cfg;
1528         }
1529
1530         rte_ether_addr_copy(mac_addr,
1531                             (struct rte_ether_addr *)hw->mac.mac_addr);
1532         hw->mac.default_addr_setted = true;
1533         rte_spinlock_unlock(&hw->lock);
1534
1535         return 0;
1536
1537 err_pause_addr_cfg:
1538         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1539         if (ret_val) {
1540                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1541                                       mac_addr);
1542                 hns3_warn(hw,
1543                           "Failed to roll back to del setted mac addr(%s): %d",
1544                           mac_str, ret_val);
1545         }
1546
1547 err_add_uc_addr:
1548         if (rm_succes) {
1549                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1550                 if (ret_val) {
1551                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1552                                               oaddr);
1553                         hns3_warn(hw,
1554                                   "Failed to restore old uc mac addr(%s): %d",
1555                                   mac_str, ret_val);
1556                         hw->mac.default_addr_setted = false;
1557                 }
1558         }
1559         rte_spinlock_unlock(&hw->lock);
1560
1561         return ret;
1562 }
1563
1564 static int
1565 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1566 {
1567         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1568         struct hns3_hw *hw = &hns->hw;
1569         struct rte_ether_addr *addr;
1570         int err = 0;
1571         int ret;
1572         int i;
1573
1574         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1575                 addr = &hw->data->mac_addrs[i];
1576                 if (!rte_is_valid_assigned_ether_addr(addr))
1577                         continue;
1578                 if (del)
1579                         ret = hns3_remove_uc_addr_common(hw, addr);
1580                 else
1581                         ret = hns3_add_uc_addr_common(hw, addr);
1582                 if (ret) {
1583                         err = ret;
1584                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1585                                               addr);
1586                         hns3_dbg(hw,
1587                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1588                                  del ? "remove" : "restore", mac_str, ret, i);
1589                 }
1590         }
1591         return err;
1592 }
1593
1594 static void
1595 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1596 {
1597 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1598         uint8_t word_num;
1599         uint8_t bit_num;
1600
1601         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1602                 word_num = vfid / 32;
1603                 bit_num = vfid % 32;
1604                 if (clr)
1605                         desc[1].data[word_num] &=
1606                             rte_cpu_to_le_32(~(1UL << bit_num));
1607                 else
1608                         desc[1].data[word_num] |=
1609                             rte_cpu_to_le_32(1UL << bit_num);
1610         } else {
1611                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1612                 bit_num = vfid % 32;
1613                 if (clr)
1614                         desc[2].data[word_num] &=
1615                             rte_cpu_to_le_32(~(1UL << bit_num));
1616                 else
1617                         desc[2].data[word_num] |=
1618                             rte_cpu_to_le_32(1UL << bit_num);
1619         }
1620 }
1621
1622 static int
1623 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1624 {
1625         struct hns3_mac_vlan_tbl_entry_cmd req;
1626         struct hns3_cmd_desc desc[3];
1627         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1628         uint8_t vf_id;
1629         int ret;
1630
1631         /* Check if mac addr is valid */
1632         if (!rte_is_multicast_ether_addr(mac_addr)) {
1633                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1634                                       mac_addr);
1635                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1636                          mac_str);
1637                 return -EINVAL;
1638         }
1639
1640         memset(&req, 0, sizeof(req));
1641         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1642         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1643         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1644         if (ret) {
1645                 /* This mac addr do not exist, add new entry for it */
1646                 memset(desc[0].data, 0, sizeof(desc[0].data));
1647                 memset(desc[1].data, 0, sizeof(desc[0].data));
1648                 memset(desc[2].data, 0, sizeof(desc[0].data));
1649         }
1650
1651         /*
1652          * In current version VF is not supported when PF is driven by DPDK
1653          * driver, the PF-related vf_id is 0, just need to configure parameters
1654          * for vf_id 0.
1655          */
1656         vf_id = 0;
1657         hns3_update_desc_vfid(desc, vf_id, false);
1658         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1659         if (ret) {
1660                 if (ret == -ENOSPC)
1661                         hns3_err(hw, "mc mac vlan table is full");
1662                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1663                                       mac_addr);
1664                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1665         }
1666
1667         return ret;
1668 }
1669
1670 static int
1671 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1672 {
1673         struct hns3_mac_vlan_tbl_entry_cmd req;
1674         struct hns3_cmd_desc desc[3];
1675         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1676         uint8_t vf_id;
1677         int ret;
1678
1679         /* Check if mac addr is valid */
1680         if (!rte_is_multicast_ether_addr(mac_addr)) {
1681                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1682                                       mac_addr);
1683                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1684                          mac_str);
1685                 return -EINVAL;
1686         }
1687
1688         memset(&req, 0, sizeof(req));
1689         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1690         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1691         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1692         if (ret == 0) {
1693                 /*
1694                  * This mac addr exist, remove this handle's VFID for it.
1695                  * In current version VF is not supported when PF is driven by
1696                  * DPDK driver, the PF-related vf_id is 0, just need to
1697                  * configure parameters for vf_id 0.
1698                  */
1699                 vf_id = 0;
1700                 hns3_update_desc_vfid(desc, vf_id, true);
1701
1702                 /* All the vfid is zero, so need to delete this entry */
1703                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1704         } else if (ret == -ENOENT) {
1705                 /* This mac addr doesn't exist. */
1706                 return 0;
1707         }
1708
1709         if (ret) {
1710                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1711                                       mac_addr);
1712                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1713         }
1714
1715         return ret;
1716 }
1717
1718 static int
1719 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1720                            struct rte_ether_addr *mc_addr_set,
1721                            uint32_t nb_mc_addr)
1722 {
1723         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1724         struct rte_ether_addr *addr;
1725         uint32_t i;
1726         uint32_t j;
1727
1728         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1729                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1730                          "invalid. valid range: 0~%d",
1731                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1732                 return -EINVAL;
1733         }
1734
1735         /* Check if input mac addresses are valid */
1736         for (i = 0; i < nb_mc_addr; i++) {
1737                 addr = &mc_addr_set[i];
1738                 if (!rte_is_multicast_ether_addr(addr)) {
1739                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1740                                               addr);
1741                         hns3_err(hw,
1742                                  "Failed to set mc mac addr, addr(%s) invalid.",
1743                                  mac_str);
1744                         return -EINVAL;
1745                 }
1746
1747                 /* Check if there are duplicate addresses */
1748                 for (j = i + 1; j < nb_mc_addr; j++) {
1749                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1750                                 rte_ether_format_addr(mac_str,
1751                                                       RTE_ETHER_ADDR_FMT_SIZE,
1752                                                       addr);
1753                                 hns3_err(hw, "Failed to set mc mac addr, "
1754                                          "addrs invalid. two same addrs(%s).",
1755                                          mac_str);
1756                                 return -EINVAL;
1757                         }
1758                 }
1759         }
1760
1761         return 0;
1762 }
1763
1764 static void
1765 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1766                            struct rte_ether_addr *mc_addr_set,
1767                            int mc_addr_num,
1768                            struct rte_ether_addr *reserved_addr_list,
1769                            int *reserved_addr_num,
1770                            struct rte_ether_addr *add_addr_list,
1771                            int *add_addr_num,
1772                            struct rte_ether_addr *rm_addr_list,
1773                            int *rm_addr_num)
1774 {
1775         struct rte_ether_addr *addr;
1776         int current_addr_num;
1777         int reserved_num = 0;
1778         int add_num = 0;
1779         int rm_num = 0;
1780         int num;
1781         int i;
1782         int j;
1783         bool same_addr;
1784
1785         /* Calculate the mc mac address list that should be removed */
1786         current_addr_num = hw->mc_addrs_num;
1787         for (i = 0; i < current_addr_num; i++) {
1788                 addr = &hw->mc_addrs[i];
1789                 same_addr = false;
1790                 for (j = 0; j < mc_addr_num; j++) {
1791                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1792                                 same_addr = true;
1793                                 break;
1794                         }
1795                 }
1796
1797                 if (!same_addr) {
1798                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1799                         rm_num++;
1800                 } else {
1801                         rte_ether_addr_copy(addr,
1802                                             &reserved_addr_list[reserved_num]);
1803                         reserved_num++;
1804                 }
1805         }
1806
1807         /* Calculate the mc mac address list that should be added */
1808         for (i = 0; i < mc_addr_num; i++) {
1809                 addr = &mc_addr_set[i];
1810                 same_addr = false;
1811                 for (j = 0; j < current_addr_num; j++) {
1812                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1813                                 same_addr = true;
1814                                 break;
1815                         }
1816                 }
1817
1818                 if (!same_addr) {
1819                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1820                         add_num++;
1821                 }
1822         }
1823
1824         /* Reorder the mc mac address list maintained by driver */
1825         for (i = 0; i < reserved_num; i++)
1826                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1827
1828         for (i = 0; i < rm_num; i++) {
1829                 num = reserved_num + i;
1830                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1831         }
1832
1833         *reserved_addr_num = reserved_num;
1834         *add_addr_num = add_num;
1835         *rm_addr_num = rm_num;
1836 }
1837
1838 static int
1839 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1840                           struct rte_ether_addr *mc_addr_set,
1841                           uint32_t nb_mc_addr)
1842 {
1843         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1844         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1845         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1846         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1847         struct rte_ether_addr *addr;
1848         int reserved_addr_num;
1849         int add_addr_num;
1850         int rm_addr_num;
1851         int mc_addr_num;
1852         int num;
1853         int ret;
1854         int i;
1855
1856         /* Check if input parameters are valid */
1857         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1858         if (ret)
1859                 return ret;
1860
1861         rte_spinlock_lock(&hw->lock);
1862
1863         /*
1864          * Calculate the mc mac address lists those should be removed and be
1865          * added, Reorder the mc mac address list maintained by driver.
1866          */
1867         mc_addr_num = (int)nb_mc_addr;
1868         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1869                                    reserved_addr_list, &reserved_addr_num,
1870                                    add_addr_list, &add_addr_num,
1871                                    rm_addr_list, &rm_addr_num);
1872
1873         /* Remove mc mac addresses */
1874         for (i = 0; i < rm_addr_num; i++) {
1875                 num = rm_addr_num - i - 1;
1876                 addr = &rm_addr_list[num];
1877                 ret = hns3_remove_mc_addr(hw, addr);
1878                 if (ret) {
1879                         rte_spinlock_unlock(&hw->lock);
1880                         return ret;
1881                 }
1882                 hw->mc_addrs_num--;
1883         }
1884
1885         /* Add mc mac addresses */
1886         for (i = 0; i < add_addr_num; i++) {
1887                 addr = &add_addr_list[i];
1888                 ret = hns3_add_mc_addr(hw, addr);
1889                 if (ret) {
1890                         rte_spinlock_unlock(&hw->lock);
1891                         return ret;
1892                 }
1893
1894                 num = reserved_addr_num + i;
1895                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1896                 hw->mc_addrs_num++;
1897         }
1898         rte_spinlock_unlock(&hw->lock);
1899
1900         return 0;
1901 }
1902
1903 static int
1904 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1905 {
1906         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1907         struct hns3_hw *hw = &hns->hw;
1908         struct rte_ether_addr *addr;
1909         int err = 0;
1910         int ret;
1911         int i;
1912
1913         for (i = 0; i < hw->mc_addrs_num; i++) {
1914                 addr = &hw->mc_addrs[i];
1915                 if (!rte_is_multicast_ether_addr(addr))
1916                         continue;
1917                 if (del)
1918                         ret = hns3_remove_mc_addr(hw, addr);
1919                 else
1920                         ret = hns3_add_mc_addr(hw, addr);
1921                 if (ret) {
1922                         err = ret;
1923                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1924                                               addr);
1925                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1926                                  del ? "Remove" : "Restore", mac_str);
1927                 }
1928         }
1929         return err;
1930 }
1931
1932 static int
1933 hns3_check_mq_mode(struct rte_eth_dev *dev)
1934 {
1935         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1936         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1937         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1939         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1940         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1941         uint8_t num_tc;
1942         int max_tc = 0;
1943         int i;
1944
1945         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1946         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1947
1948         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1949                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1950                          "rx_mq_mode = %d", rx_mq_mode);
1951                 return -EINVAL;
1952         }
1953
1954         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1955             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1956                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1957                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1958                          rx_mq_mode, tx_mq_mode);
1959                 return -EINVAL;
1960         }
1961
1962         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1963                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1964                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1965                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1966                         return -EINVAL;
1967                 }
1968
1969                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1970                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1971                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1972                                  "nb_tcs(%d) != %d or %d in rx direction.",
1973                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1974                         return -EINVAL;
1975                 }
1976
1977                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1978                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1979                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1980                         return -EINVAL;
1981                 }
1982
1983                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1984                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1985                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1986                                          "is not equal to one in tx direction.",
1987                                          i, dcb_rx_conf->dcb_tc[i]);
1988                                 return -EINVAL;
1989                         }
1990                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1991                                 max_tc = dcb_rx_conf->dcb_tc[i];
1992                 }
1993
1994                 num_tc = max_tc + 1;
1995                 if (num_tc > dcb_rx_conf->nb_tcs) {
1996                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1997                                  num_tc, dcb_rx_conf->nb_tcs);
1998                         return -EINVAL;
1999                 }
2000         }
2001
2002         return 0;
2003 }
2004
2005 static int
2006 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2007 {
2008         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009
2010         if (!hns3_dev_dcb_supported(hw)) {
2011                 hns3_err(hw, "this port does not support dcb configurations.");
2012                 return -EOPNOTSUPP;
2013         }
2014
2015         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2016                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2017                 return -EOPNOTSUPP;
2018         }
2019
2020         /* Check multiple queue mode */
2021         return hns3_check_mq_mode(dev);
2022 }
2023
2024 static int
2025 hns3_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
2026                            bool mmap, uint16_t queue_id)
2027 {
2028         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         struct hns3_cmd_desc desc;
2030         struct hns3_ctrl_vector_chain_cmd *req =
2031                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2032         enum hns3_cmd_status status;
2033         enum hns3_opcode_type op;
2034         uint16_t tqp_type_and_id = 0;
2035
2036         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2037         hns3_cmd_setup_basic_desc(&desc, op, false);
2038         req->int_vector_id = vector_id;
2039
2040         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2041                        HNS3_RING_TYPE_RX);
2042         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2043         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2044                        HNS3_RING_GL_RX);
2045         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2046
2047         req->int_cause_num = 1;
2048         status = hns3_cmd_send(hw, &desc, 1);
2049         if (status) {
2050                 hns3_err(hw, "Map TQP %d fail, vector_id is %d, status is %d.",
2051                          queue_id, vector_id, status);
2052                 return -EIO;
2053         }
2054
2055         return 0;
2056 }
2057
2058 static int
2059 hns3_dev_configure(struct rte_eth_dev *dev)
2060 {
2061         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2063         struct rte_eth_conf *conf = &dev->data->dev_conf;
2064         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2065         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2066         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2067         struct rte_eth_rss_conf rss_conf;
2068         uint16_t mtu;
2069         int ret;
2070
2071         /*
2072          * Hardware does not support where the number of rx and tx queues is
2073          * not equal in hip08.
2074          */
2075         if (nb_rx_q != nb_tx_q) {
2076                 hns3_err(hw,
2077                          "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! "
2078                          "Hardware does not support this configuration!",
2079                          nb_rx_q, nb_tx_q);
2080                 return -EINVAL;
2081         }
2082
2083         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2084                 hns3_err(hw, "setting link speed/duplex not supported");
2085                 return -EINVAL;
2086         }
2087
2088         hw->adapter_state = HNS3_NIC_CONFIGURING;
2089         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2090                 ret = hns3_check_dcb_cfg(dev);
2091                 if (ret)
2092                         goto cfg_err;
2093         }
2094
2095         /* When RSS is not configured, redirect the packet queue 0 */
2096         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2097                 rss_conf = conf->rx_adv_conf.rss_conf;
2098                 if (rss_conf.rss_key == NULL) {
2099                         rss_conf.rss_key = rss_cfg->key;
2100                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2101                 }
2102
2103                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2104                 if (ret)
2105                         goto cfg_err;
2106         }
2107
2108         /*
2109          * If jumbo frames are enabled, MTU needs to be refreshed
2110          * according to the maximum RX packet length.
2111          */
2112         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2113                 /*
2114                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2115                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2116                  * can safely assign to "uint16_t" type variable.
2117                  */
2118                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2119                 ret = hns3_dev_mtu_set(dev, mtu);
2120                 if (ret)
2121                         goto cfg_err;
2122                 dev->data->mtu = mtu;
2123         }
2124
2125         ret = hns3_dev_configure_vlan(dev);
2126         if (ret)
2127                 goto cfg_err;
2128
2129         hw->adapter_state = HNS3_NIC_CONFIGURED;
2130
2131         return 0;
2132
2133 cfg_err:
2134         hw->adapter_state = HNS3_NIC_INITIALIZED;
2135         return ret;
2136 }
2137
2138 static int
2139 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2140 {
2141         struct hns3_config_max_frm_size_cmd *req;
2142         struct hns3_cmd_desc desc;
2143
2144         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2145
2146         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2147         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2148         req->min_frm_size = HNS3_MIN_FRAME_LEN;
2149
2150         return hns3_cmd_send(hw, &desc, 1);
2151 }
2152
2153 static int
2154 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2155 {
2156         int ret;
2157
2158         ret = hns3_set_mac_mtu(hw, mps);
2159         if (ret) {
2160                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2161                 return ret;
2162         }
2163
2164         ret = hns3_buffer_alloc(hw);
2165         if (ret) {
2166                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2167                 return ret;
2168         }
2169
2170         return 0;
2171 }
2172
2173 static int
2174 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2175 {
2176         struct hns3_adapter *hns = dev->data->dev_private;
2177         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2178         struct hns3_hw *hw = &hns->hw;
2179         bool is_jumbo_frame;
2180         int ret;
2181
2182         if (dev->data->dev_started) {
2183                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2184                          "before configuration", dev->data->port_id);
2185                 return -EBUSY;
2186         }
2187
2188         rte_spinlock_lock(&hw->lock);
2189         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2190         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2191
2192         /*
2193          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2194          * assign to "uint16_t" type variable.
2195          */
2196         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2197         if (ret) {
2198                 rte_spinlock_unlock(&hw->lock);
2199                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2200                          dev->data->port_id, mtu, ret);
2201                 return ret;
2202         }
2203         hns->pf.mps = (uint16_t)frame_size;
2204         if (is_jumbo_frame)
2205                 dev->data->dev_conf.rxmode.offloads |=
2206                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2207         else
2208                 dev->data->dev_conf.rxmode.offloads &=
2209                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2210         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2211         rte_spinlock_unlock(&hw->lock);
2212
2213         return 0;
2214 }
2215
2216 static int
2217 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2218 {
2219         struct hns3_adapter *hns = eth_dev->data->dev_private;
2220         struct hns3_hw *hw = &hns->hw;
2221
2222         info->max_rx_queues = hw->tqps_num;
2223         info->max_tx_queues = hw->tqps_num;
2224         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2225         info->min_rx_bufsize = hw->rx_buf_len;
2226         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2227         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2228         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2229                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2230                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2231                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2232                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2233                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2234                                  DEV_RX_OFFLOAD_KEEP_CRC |
2235                                  DEV_RX_OFFLOAD_SCATTER |
2236                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2237                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2238                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2239                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2240                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2241         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2242         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2243                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2244                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2245                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2246                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2247                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2248                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2249                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2250                                  info->tx_queue_offload_capa);
2251
2252         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2253                 .nb_max = HNS3_MAX_RING_DESC,
2254                 .nb_min = HNS3_MIN_RING_DESC,
2255                 .nb_align = HNS3_ALIGN_RING_DESC,
2256         };
2257
2258         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2259                 .nb_max = HNS3_MAX_RING_DESC,
2260                 .nb_min = HNS3_MIN_RING_DESC,
2261                 .nb_align = HNS3_ALIGN_RING_DESC,
2262         };
2263
2264         info->vmdq_queue_num = 0;
2265
2266         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2267         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2268         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2269
2270         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2271         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2272         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2273         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2274         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2275         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2276
2277         return 0;
2278 }
2279
2280 static int
2281 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2282                     size_t fw_size)
2283 {
2284         struct hns3_adapter *hns = eth_dev->data->dev_private;
2285         struct hns3_hw *hw = &hns->hw;
2286         int ret;
2287
2288         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2289         ret += 1; /* add the size of '\0' */
2290         if (fw_size < (uint32_t)ret)
2291                 return ret;
2292         else
2293                 return 0;
2294 }
2295
2296 static int
2297 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2298                      __rte_unused int wait_to_complete)
2299 {
2300         struct hns3_adapter *hns = eth_dev->data->dev_private;
2301         struct hns3_hw *hw = &hns->hw;
2302         struct hns3_mac *mac = &hw->mac;
2303         struct rte_eth_link new_link;
2304
2305         memset(&new_link, 0, sizeof(new_link));
2306         switch (mac->link_speed) {
2307         case ETH_SPEED_NUM_10M:
2308         case ETH_SPEED_NUM_100M:
2309         case ETH_SPEED_NUM_1G:
2310         case ETH_SPEED_NUM_10G:
2311         case ETH_SPEED_NUM_25G:
2312         case ETH_SPEED_NUM_40G:
2313         case ETH_SPEED_NUM_50G:
2314         case ETH_SPEED_NUM_100G:
2315                 new_link.link_speed = mac->link_speed;
2316                 break;
2317         default:
2318                 new_link.link_speed = ETH_SPEED_NUM_100M;
2319                 break;
2320         }
2321
2322         new_link.link_duplex = mac->link_duplex;
2323         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2324         new_link.link_autoneg =
2325             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2326
2327         return rte_eth_linkstatus_set(eth_dev, &new_link);
2328 }
2329
2330 static int
2331 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2332 {
2333         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2334         struct hns3_pf *pf = &hns->pf;
2335
2336         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2337                 return -EINVAL;
2338
2339         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2340
2341         return 0;
2342 }
2343
2344 static int
2345 hns3_query_function_status(struct hns3_hw *hw)
2346 {
2347 #define HNS3_QUERY_MAX_CNT              10
2348 #define HNS3_QUERY_SLEEP_MSCOEND        1
2349         struct hns3_func_status_cmd *req;
2350         struct hns3_cmd_desc desc;
2351         int timeout = 0;
2352         int ret;
2353
2354         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2355         req = (struct hns3_func_status_cmd *)desc.data;
2356
2357         do {
2358                 ret = hns3_cmd_send(hw, &desc, 1);
2359                 if (ret) {
2360                         PMD_INIT_LOG(ERR, "query function status failed %d",
2361                                      ret);
2362                         return ret;
2363                 }
2364
2365                 /* Check pf reset is done */
2366                 if (req->pf_state)
2367                         break;
2368
2369                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2370         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2371
2372         return hns3_parse_func_status(hw, req);
2373 }
2374
2375 static int
2376 hns3_query_pf_resource(struct hns3_hw *hw)
2377 {
2378         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2379         struct hns3_pf *pf = &hns->pf;
2380         struct hns3_pf_res_cmd *req;
2381         struct hns3_cmd_desc desc;
2382         int ret;
2383
2384         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2385         ret = hns3_cmd_send(hw, &desc, 1);
2386         if (ret) {
2387                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2388                 return ret;
2389         }
2390
2391         req = (struct hns3_pf_res_cmd *)desc.data;
2392         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2393         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2394         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2395
2396         if (req->tx_buf_size)
2397                 pf->tx_buf_size =
2398                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2399         else
2400                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2401
2402         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2403
2404         if (req->dv_buf_size)
2405                 pf->dv_buf_size =
2406                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2407         else
2408                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2409
2410         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2411
2412         hw->num_msi =
2413             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2414                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2415
2416         return 0;
2417 }
2418
2419 static void
2420 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2421 {
2422         struct hns3_cfg_param_cmd *req;
2423         uint64_t mac_addr_tmp_high;
2424         uint64_t mac_addr_tmp;
2425         uint32_t i;
2426
2427         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2428
2429         /* get the configuration */
2430         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2431                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2432         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2433                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2434         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2435                                            HNS3_CFG_TQP_DESC_N_M,
2436                                            HNS3_CFG_TQP_DESC_N_S);
2437
2438         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2439                                        HNS3_CFG_PHY_ADDR_M,
2440                                        HNS3_CFG_PHY_ADDR_S);
2441         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2442                                          HNS3_CFG_MEDIA_TP_M,
2443                                          HNS3_CFG_MEDIA_TP_S);
2444         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2445                                          HNS3_CFG_RX_BUF_LEN_M,
2446                                          HNS3_CFG_RX_BUF_LEN_S);
2447         /* get mac address */
2448         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2449         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2450                                            HNS3_CFG_MAC_ADDR_H_M,
2451                                            HNS3_CFG_MAC_ADDR_H_S);
2452
2453         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2454
2455         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2456                                             HNS3_CFG_DEFAULT_SPEED_M,
2457                                             HNS3_CFG_DEFAULT_SPEED_S);
2458         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2459                                            HNS3_CFG_RSS_SIZE_M,
2460                                            HNS3_CFG_RSS_SIZE_S);
2461
2462         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2463                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2464
2465         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2466         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2467
2468         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2469                                             HNS3_CFG_SPEED_ABILITY_M,
2470                                             HNS3_CFG_SPEED_ABILITY_S);
2471         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2472                                         HNS3_CFG_UMV_TBL_SPACE_M,
2473                                         HNS3_CFG_UMV_TBL_SPACE_S);
2474         if (!cfg->umv_space)
2475                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2476 }
2477
2478 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2479  * @hw: pointer to struct hns3_hw
2480  * @hcfg: the config structure to be getted
2481  */
2482 static int
2483 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2484 {
2485         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2486         struct hns3_cfg_param_cmd *req;
2487         uint32_t offset;
2488         uint32_t i;
2489         int ret;
2490
2491         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2492                 offset = 0;
2493                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2494                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2495                                           true);
2496                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2497                                i * HNS3_CFG_RD_LEN_BYTES);
2498                 /* Len should be divided by 4 when send to hardware */
2499                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2500                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2501                 req->offset = rte_cpu_to_le_32(offset);
2502         }
2503
2504         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2505         if (ret) {
2506                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2507                 return ret;
2508         }
2509
2510         hns3_parse_cfg(hcfg, desc);
2511
2512         return 0;
2513 }
2514
2515 static int
2516 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2517 {
2518         switch (speed_cmd) {
2519         case HNS3_CFG_SPEED_10M:
2520                 *speed = ETH_SPEED_NUM_10M;
2521                 break;
2522         case HNS3_CFG_SPEED_100M:
2523                 *speed = ETH_SPEED_NUM_100M;
2524                 break;
2525         case HNS3_CFG_SPEED_1G:
2526                 *speed = ETH_SPEED_NUM_1G;
2527                 break;
2528         case HNS3_CFG_SPEED_10G:
2529                 *speed = ETH_SPEED_NUM_10G;
2530                 break;
2531         case HNS3_CFG_SPEED_25G:
2532                 *speed = ETH_SPEED_NUM_25G;
2533                 break;
2534         case HNS3_CFG_SPEED_40G:
2535                 *speed = ETH_SPEED_NUM_40G;
2536                 break;
2537         case HNS3_CFG_SPEED_50G:
2538                 *speed = ETH_SPEED_NUM_50G;
2539                 break;
2540         case HNS3_CFG_SPEED_100G:
2541                 *speed = ETH_SPEED_NUM_100G;
2542                 break;
2543         default:
2544                 return -EINVAL;
2545         }
2546
2547         return 0;
2548 }
2549
2550 static int
2551 hns3_get_board_configuration(struct hns3_hw *hw)
2552 {
2553         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2554         struct hns3_pf *pf = &hns->pf;
2555         struct hns3_cfg cfg;
2556         int ret;
2557
2558         ret = hns3_get_board_cfg(hw, &cfg);
2559         if (ret) {
2560                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2561                 return ret;
2562         }
2563
2564         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2565                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2566                 return -EOPNOTSUPP;
2567         }
2568
2569         hw->mac.media_type = cfg.media_type;
2570         hw->rss_size_max = cfg.rss_size_max;
2571         hw->rx_buf_len = cfg.rx_buf_len;
2572         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2573         hw->mac.phy_addr = cfg.phy_addr;
2574         hw->mac.default_addr_setted = false;
2575         hw->num_tx_desc = cfg.tqp_desc_num;
2576         hw->num_rx_desc = cfg.tqp_desc_num;
2577         hw->dcb_info.num_pg = 1;
2578         hw->dcb_info.hw_pfc_map = 0;
2579
2580         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2581         if (ret) {
2582                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2583                              cfg.default_speed, ret);
2584                 return ret;
2585         }
2586
2587         pf->tc_max = cfg.tc_num;
2588         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2589                 PMD_INIT_LOG(WARNING,
2590                              "Get TC num(%u) from flash, set TC num to 1",
2591                              pf->tc_max);
2592                 pf->tc_max = 1;
2593         }
2594
2595         /* Dev does not support DCB */
2596         if (!hns3_dev_dcb_supported(hw)) {
2597                 pf->tc_max = 1;
2598                 pf->pfc_max = 0;
2599         } else
2600                 pf->pfc_max = pf->tc_max;
2601
2602         hw->dcb_info.num_tc = 1;
2603         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2604                                      hw->tqps_num / hw->dcb_info.num_tc);
2605         hns3_set_bit(hw->hw_tc_map, 0, 1);
2606         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2607
2608         pf->wanted_umv_size = cfg.umv_space;
2609
2610         return ret;
2611 }
2612
2613 static int
2614 hns3_get_configuration(struct hns3_hw *hw)
2615 {
2616         int ret;
2617
2618         ret = hns3_query_function_status(hw);
2619         if (ret) {
2620                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2621                 return ret;
2622         }
2623
2624         /* Get pf resource */
2625         ret = hns3_query_pf_resource(hw);
2626         if (ret) {
2627                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2628                 return ret;
2629         }
2630
2631         ret = hns3_get_board_configuration(hw);
2632         if (ret) {
2633                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2634                 return ret;
2635         }
2636
2637         return 0;
2638 }
2639
2640 static int
2641 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2642                       uint16_t tqp_vid, bool is_pf)
2643 {
2644         struct hns3_tqp_map_cmd *req;
2645         struct hns3_cmd_desc desc;
2646         int ret;
2647
2648         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2649
2650         req = (struct hns3_tqp_map_cmd *)desc.data;
2651         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2652         req->tqp_vf = func_id;
2653         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2654         if (!is_pf)
2655                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2656         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2657
2658         ret = hns3_cmd_send(hw, &desc, 1);
2659         if (ret)
2660                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2661
2662         return ret;
2663 }
2664
2665 static int
2666 hns3_map_tqp(struct hns3_hw *hw)
2667 {
2668         uint16_t tqps_num = hw->total_tqps_num;
2669         uint16_t func_id;
2670         uint16_t tqp_id;
2671         int num;
2672         int ret;
2673         int i;
2674
2675         /*
2676          * In current version VF is not supported when PF is driven by DPDK
2677          * driver, so we allocate tqps to PF as much as possible.
2678          */
2679         tqp_id = 0;
2680         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2681         for (func_id = 0; func_id < num; func_id++) {
2682                 for (i = 0;
2683                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2684                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2685                                                     true);
2686                         if (ret)
2687                                 return ret;
2688                 }
2689         }
2690
2691         return 0;
2692 }
2693
2694 static int
2695 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2696 {
2697         struct hns3_config_mac_speed_dup_cmd *req;
2698         struct hns3_cmd_desc desc;
2699         int ret;
2700
2701         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2702
2703         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2704
2705         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2706
2707         switch (speed) {
2708         case ETH_SPEED_NUM_10M:
2709                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2710                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2711                 break;
2712         case ETH_SPEED_NUM_100M:
2713                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2714                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2715                 break;
2716         case ETH_SPEED_NUM_1G:
2717                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2718                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2719                 break;
2720         case ETH_SPEED_NUM_10G:
2721                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2722                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2723                 break;
2724         case ETH_SPEED_NUM_25G:
2725                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2726                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2727                 break;
2728         case ETH_SPEED_NUM_40G:
2729                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2730                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2731                 break;
2732         case ETH_SPEED_NUM_50G:
2733                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2734                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2735                 break;
2736         case ETH_SPEED_NUM_100G:
2737                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2738                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2739                 break;
2740         default:
2741                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2742                 return -EINVAL;
2743         }
2744
2745         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2746
2747         ret = hns3_cmd_send(hw, &desc, 1);
2748         if (ret)
2749                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2750
2751         return ret;
2752 }
2753
2754 static int
2755 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2756 {
2757         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2758         struct hns3_pf *pf = &hns->pf;
2759         struct hns3_priv_buf *priv;
2760         uint32_t i, total_size;
2761
2762         total_size = pf->pkt_buf_size;
2763
2764         /* alloc tx buffer for all enabled tc */
2765         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2766                 priv = &buf_alloc->priv_buf[i];
2767
2768                 if (hw->hw_tc_map & BIT(i)) {
2769                         if (total_size < pf->tx_buf_size)
2770                                 return -ENOMEM;
2771
2772                         priv->tx_buf_size = pf->tx_buf_size;
2773                 } else
2774                         priv->tx_buf_size = 0;
2775
2776                 total_size -= priv->tx_buf_size;
2777         }
2778
2779         return 0;
2780 }
2781
2782 static int
2783 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2784 {
2785 /* TX buffer size is unit by 128 byte */
2786 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2787 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2788         struct hns3_tx_buff_alloc_cmd *req;
2789         struct hns3_cmd_desc desc;
2790         uint32_t buf_size;
2791         uint32_t i;
2792         int ret;
2793
2794         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2795
2796         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2797         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2798                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2799
2800                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2801                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2802                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2803         }
2804
2805         ret = hns3_cmd_send(hw, &desc, 1);
2806         if (ret)
2807                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2808
2809         return ret;
2810 }
2811
2812 static int
2813 hns3_get_tc_num(struct hns3_hw *hw)
2814 {
2815         int cnt = 0;
2816         uint8_t i;
2817
2818         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2819                 if (hw->hw_tc_map & BIT(i))
2820                         cnt++;
2821         return cnt;
2822 }
2823
2824 static uint32_t
2825 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2826 {
2827         struct hns3_priv_buf *priv;
2828         uint32_t rx_priv = 0;
2829         int i;
2830
2831         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2832                 priv = &buf_alloc->priv_buf[i];
2833                 if (priv->enable)
2834                         rx_priv += priv->buf_size;
2835         }
2836         return rx_priv;
2837 }
2838
2839 static uint32_t
2840 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2841 {
2842         uint32_t total_tx_size = 0;
2843         uint32_t i;
2844
2845         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2846                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2847
2848         return total_tx_size;
2849 }
2850
2851 /* Get the number of pfc enabled TCs, which have private buffer */
2852 static int
2853 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2854 {
2855         struct hns3_priv_buf *priv;
2856         int cnt = 0;
2857         uint8_t i;
2858
2859         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2860                 priv = &buf_alloc->priv_buf[i];
2861                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2862                         cnt++;
2863         }
2864
2865         return cnt;
2866 }
2867
2868 /* Get the number of pfc disabled TCs, which have private buffer */
2869 static int
2870 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2871                          struct hns3_pkt_buf_alloc *buf_alloc)
2872 {
2873         struct hns3_priv_buf *priv;
2874         int cnt = 0;
2875         uint8_t i;
2876
2877         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2878                 priv = &buf_alloc->priv_buf[i];
2879                 if (hw->hw_tc_map & BIT(i) &&
2880                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2881                         cnt++;
2882         }
2883
2884         return cnt;
2885 }
2886
2887 static bool
2888 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2889                   uint32_t rx_all)
2890 {
2891         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2892         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2893         struct hns3_pf *pf = &hns->pf;
2894         uint32_t shared_buf, aligned_mps;
2895         uint32_t rx_priv;
2896         uint8_t tc_num;
2897         uint8_t i;
2898
2899         tc_num = hns3_get_tc_num(hw);
2900         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2901
2902         if (hns3_dev_dcb_supported(hw))
2903                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2904                                         pf->dv_buf_size;
2905         else
2906                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2907                                         + pf->dv_buf_size;
2908
2909         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2910         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2911                              HNS3_BUF_SIZE_UNIT);
2912
2913         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2914         if (rx_all < rx_priv + shared_std)
2915                 return false;
2916
2917         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2918         buf_alloc->s_buf.buf_size = shared_buf;
2919         if (hns3_dev_dcb_supported(hw)) {
2920                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2921                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2922                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2923                                   HNS3_BUF_SIZE_UNIT);
2924         } else {
2925                 buf_alloc->s_buf.self.high =
2926                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2927                 buf_alloc->s_buf.self.low = aligned_mps;
2928         }
2929
2930         if (hns3_dev_dcb_supported(hw)) {
2931                 hi_thrd = shared_buf - pf->dv_buf_size;
2932
2933                 if (tc_num <= NEED_RESERVE_TC_NUM)
2934                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2935                                         / BUF_MAX_PERCENT;
2936
2937                 if (tc_num)
2938                         hi_thrd = hi_thrd / tc_num;
2939
2940                 hi_thrd = max_t(uint32_t, hi_thrd,
2941                                 HNS3_BUF_MUL_BY * aligned_mps);
2942                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2943                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2944         } else {
2945                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2946                 lo_thrd = aligned_mps;
2947         }
2948
2949         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2950                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2951                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2952         }
2953
2954         return true;
2955 }
2956
2957 static bool
2958 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2959                      struct hns3_pkt_buf_alloc *buf_alloc)
2960 {
2961         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2962         struct hns3_pf *pf = &hns->pf;
2963         struct hns3_priv_buf *priv;
2964         uint32_t aligned_mps;
2965         uint32_t rx_all;
2966         uint8_t i;
2967
2968         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2969         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2970
2971         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2972                 priv = &buf_alloc->priv_buf[i];
2973
2974                 priv->enable = 0;
2975                 priv->wl.low = 0;
2976                 priv->wl.high = 0;
2977                 priv->buf_size = 0;
2978
2979                 if (!(hw->hw_tc_map & BIT(i)))
2980                         continue;
2981
2982                 priv->enable = 1;
2983                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
2984                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
2985                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2986                                                 HNS3_BUF_SIZE_UNIT);
2987                 } else {
2988                         priv->wl.low = 0;
2989                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
2990                                         aligned_mps;
2991                 }
2992
2993                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
2994         }
2995
2996         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2997 }
2998
2999 static bool
3000 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3001                              struct hns3_pkt_buf_alloc *buf_alloc)
3002 {
3003         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3004         struct hns3_pf *pf = &hns->pf;
3005         struct hns3_priv_buf *priv;
3006         int no_pfc_priv_num;
3007         uint32_t rx_all;
3008         uint8_t mask;
3009         int i;
3010
3011         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3012         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3013
3014         /* let the last to be cleared first */
3015         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3016                 priv = &buf_alloc->priv_buf[i];
3017                 mask = BIT((uint8_t)i);
3018
3019                 if (hw->hw_tc_map & mask &&
3020                     !(hw->dcb_info.hw_pfc_map & mask)) {
3021                         /* Clear the no pfc TC private buffer */
3022                         priv->wl.low = 0;
3023                         priv->wl.high = 0;
3024                         priv->buf_size = 0;
3025                         priv->enable = 0;
3026                         no_pfc_priv_num--;
3027                 }
3028
3029                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3030                     no_pfc_priv_num == 0)
3031                         break;
3032         }
3033
3034         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3035 }
3036
3037 static bool
3038 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3039                            struct hns3_pkt_buf_alloc *buf_alloc)
3040 {
3041         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3042         struct hns3_pf *pf = &hns->pf;
3043         struct hns3_priv_buf *priv;
3044         uint32_t rx_all;
3045         int pfc_priv_num;
3046         uint8_t mask;
3047         int i;
3048
3049         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3050         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3051
3052         /* let the last to be cleared first */
3053         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3054                 priv = &buf_alloc->priv_buf[i];
3055                 mask = BIT((uint8_t)i);
3056
3057                 if (hw->hw_tc_map & mask &&
3058                     hw->dcb_info.hw_pfc_map & mask) {
3059                         /* Reduce the number of pfc TC with private buffer */
3060                         priv->wl.low = 0;
3061                         priv->enable = 0;
3062                         priv->wl.high = 0;
3063                         priv->buf_size = 0;
3064                         pfc_priv_num--;
3065                 }
3066                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3067                     pfc_priv_num == 0)
3068                         break;
3069         }
3070
3071         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3072 }
3073
3074 static bool
3075 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3076                           struct hns3_pkt_buf_alloc *buf_alloc)
3077 {
3078 #define COMPENSATE_BUFFER       0x3C00
3079 #define COMPENSATE_HALF_MPS_NUM 5
3080 #define PRIV_WL_GAP             0x1800
3081         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3082         struct hns3_pf *pf = &hns->pf;
3083         uint32_t tc_num = hns3_get_tc_num(hw);
3084         uint32_t half_mps = pf->mps >> 1;
3085         struct hns3_priv_buf *priv;
3086         uint32_t min_rx_priv;
3087         uint32_t rx_priv;
3088         uint8_t i;
3089
3090         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3091         if (tc_num)
3092                 rx_priv = rx_priv / tc_num;
3093
3094         if (tc_num <= NEED_RESERVE_TC_NUM)
3095                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3096
3097         /*
3098          * Minimum value of private buffer in rx direction (min_rx_priv) is
3099          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3100          * buffer if rx_priv is greater than min_rx_priv.
3101          */
3102         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3103                         COMPENSATE_HALF_MPS_NUM * half_mps;
3104         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3105         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3106
3107         if (rx_priv < min_rx_priv)
3108                 return false;
3109
3110         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3111                 priv = &buf_alloc->priv_buf[i];
3112
3113                 priv->enable = 0;
3114                 priv->wl.low = 0;
3115                 priv->wl.high = 0;
3116                 priv->buf_size = 0;
3117
3118                 if (!(hw->hw_tc_map & BIT(i)))
3119                         continue;
3120
3121                 priv->enable = 1;
3122                 priv->buf_size = rx_priv;
3123                 priv->wl.high = rx_priv - pf->dv_buf_size;
3124                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3125         }
3126
3127         buf_alloc->s_buf.buf_size = 0;
3128
3129         return true;
3130 }
3131
3132 /*
3133  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3134  * @hw: pointer to struct hns3_hw
3135  * @buf_alloc: pointer to buffer calculation data
3136  * @return: 0: calculate sucessful, negative: fail
3137  */
3138 static int
3139 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3140 {
3141         /* When DCB is not supported, rx private buffer is not allocated. */
3142         if (!hns3_dev_dcb_supported(hw)) {
3143                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3144                 struct hns3_pf *pf = &hns->pf;
3145                 uint32_t rx_all = pf->pkt_buf_size;
3146
3147                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3148                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3149                         return -ENOMEM;
3150
3151                 return 0;
3152         }
3153
3154         /*
3155          * Try to allocate privated packet buffer for all TCs without share
3156          * buffer.
3157          */
3158         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3159                 return 0;
3160
3161         /*
3162          * Try to allocate privated packet buffer for all TCs with share
3163          * buffer.
3164          */
3165         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3166                 return 0;
3167
3168         /*
3169          * For different application scenes, the enabled port number, TC number
3170          * and no_drop TC number are different. In order to obtain the better
3171          * performance, software could allocate the buffer size and configure
3172          * the waterline by tring to decrease the private buffer size according
3173          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3174          * enabled tc.
3175          */
3176         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3177                 return 0;
3178
3179         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3180                 return 0;
3181
3182         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3183                 return 0;
3184
3185         return -ENOMEM;
3186 }
3187
3188 static int
3189 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3190 {
3191         struct hns3_rx_priv_buff_cmd *req;
3192         struct hns3_cmd_desc desc;
3193         uint32_t buf_size;
3194         int ret;
3195         int i;
3196
3197         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3198         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3199
3200         /* Alloc private buffer TCs */
3201         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3202                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3203
3204                 req->buf_num[i] =
3205                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3206                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3207         }
3208
3209         buf_size = buf_alloc->s_buf.buf_size;
3210         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3211                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3212
3213         ret = hns3_cmd_send(hw, &desc, 1);
3214         if (ret)
3215                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3216
3217         return ret;
3218 }
3219
3220 static int
3221 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3222 {
3223 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3224         struct hns3_rx_priv_wl_buf *req;
3225         struct hns3_priv_buf *priv;
3226         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3227         int i, j;
3228         int ret;
3229
3230         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3231                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3232                                           false);
3233                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3234
3235                 /* The first descriptor set the NEXT bit to 1 */
3236                 if (i == 0)
3237                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3238                 else
3239                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3240
3241                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3242                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3243
3244                         priv = &buf_alloc->priv_buf[idx];
3245                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3246                                                         HNS3_BUF_UNIT_S);
3247                         req->tc_wl[j].high |=
3248                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3249                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3250                                                         HNS3_BUF_UNIT_S);
3251                         req->tc_wl[j].low |=
3252                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3253                 }
3254         }
3255
3256         /* Send 2 descriptor at one time */
3257         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3258         if (ret)
3259                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3260                              ret);
3261         return ret;
3262 }
3263
3264 static int
3265 hns3_common_thrd_config(struct hns3_hw *hw,
3266                         struct hns3_pkt_buf_alloc *buf_alloc)
3267 {
3268 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3269         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3270         struct hns3_rx_com_thrd *req;
3271         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3272         struct hns3_tc_thrd *tc;
3273         int tc_idx;
3274         int i, j;
3275         int ret;
3276
3277         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3278                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3279                                           false);
3280                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3281
3282                 /* The first descriptor set the NEXT bit to 1 */
3283                 if (i == 0)
3284                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3285                 else
3286                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3287
3288                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3289                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3290                         tc = &s_buf->tc_thrd[tc_idx];
3291
3292                         req->com_thrd[j].high =
3293                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3294                         req->com_thrd[j].high |=
3295                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3296                         req->com_thrd[j].low =
3297                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3298                         req->com_thrd[j].low |=
3299                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3300                 }
3301         }
3302
3303         /* Send 2 descriptors at one time */
3304         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3305         if (ret)
3306                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3307
3308         return ret;
3309 }
3310
3311 static int
3312 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3313 {
3314         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3315         struct hns3_rx_com_wl *req;
3316         struct hns3_cmd_desc desc;
3317         int ret;
3318
3319         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3320
3321         req = (struct hns3_rx_com_wl *)desc.data;
3322         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3323         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3324
3325         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3326         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3327
3328         ret = hns3_cmd_send(hw, &desc, 1);
3329         if (ret)
3330                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3331
3332         return ret;
3333 }
3334
3335 int
3336 hns3_buffer_alloc(struct hns3_hw *hw)
3337 {
3338         struct hns3_pkt_buf_alloc pkt_buf;
3339         int ret;
3340
3341         memset(&pkt_buf, 0, sizeof(pkt_buf));
3342         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3343         if (ret) {
3344                 PMD_INIT_LOG(ERR,
3345                              "could not calc tx buffer size for all TCs %d",
3346                              ret);
3347                 return ret;
3348         }
3349
3350         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3351         if (ret) {
3352                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3353                 return ret;
3354         }
3355
3356         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3357         if (ret) {
3358                 PMD_INIT_LOG(ERR,
3359                              "could not calc rx priv buffer size for all TCs %d",
3360                              ret);
3361                 return ret;
3362         }
3363
3364         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3365         if (ret) {
3366                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3367                 return ret;
3368         }
3369
3370         if (hns3_dev_dcb_supported(hw)) {
3371                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3372                 if (ret) {
3373                         PMD_INIT_LOG(ERR,
3374                                      "could not configure rx private waterline %d",
3375                                      ret);
3376                         return ret;
3377                 }
3378
3379                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3380                 if (ret) {
3381                         PMD_INIT_LOG(ERR,
3382                                      "could not configure common threshold %d",
3383                                      ret);
3384                         return ret;
3385                 }
3386         }
3387
3388         ret = hns3_common_wl_config(hw, &pkt_buf);
3389         if (ret)
3390                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3391                              ret);
3392
3393         return ret;
3394 }
3395
3396 static int
3397 hns3_mac_init(struct hns3_hw *hw)
3398 {
3399         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3400         struct hns3_mac *mac = &hw->mac;
3401         struct hns3_pf *pf = &hns->pf;
3402         int ret;
3403
3404         pf->support_sfp_query = true;
3405         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3406         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3407         if (ret) {
3408                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3409                 return ret;
3410         }
3411
3412         mac->link_status = ETH_LINK_DOWN;
3413
3414         return hns3_config_mtu(hw, pf->mps);
3415 }
3416
3417 static int
3418 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3419 {
3420 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3421 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3422 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3423 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3424         int return_status;
3425
3426         if (cmdq_resp) {
3427                 PMD_INIT_LOG(ERR,
3428                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3429                              cmdq_resp);
3430                 return -EIO;
3431         }
3432
3433         switch (resp_code) {
3434         case HNS3_ETHERTYPE_SUCCESS_ADD:
3435         case HNS3_ETHERTYPE_ALREADY_ADD:
3436                 return_status = 0;
3437                 break;
3438         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3439                 PMD_INIT_LOG(ERR,
3440                              "add mac ethertype failed for manager table overflow.");
3441                 return_status = -EIO;
3442                 break;
3443         case HNS3_ETHERTYPE_KEY_CONFLICT:
3444                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3445                 return_status = -EIO;
3446                 break;
3447         default:
3448                 PMD_INIT_LOG(ERR,
3449                              "add mac ethertype failed for undefined, code=%d.",
3450                              resp_code);
3451                 return_status = -EIO;
3452         }
3453
3454         return return_status;
3455 }
3456
3457 static int
3458 hns3_add_mgr_tbl(struct hns3_hw *hw,
3459                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3460 {
3461         struct hns3_cmd_desc desc;
3462         uint8_t resp_code;
3463         uint16_t retval;
3464         int ret;
3465
3466         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3467         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3468
3469         ret = hns3_cmd_send(hw, &desc, 1);
3470         if (ret) {
3471                 PMD_INIT_LOG(ERR,
3472                              "add mac ethertype failed for cmd_send, ret =%d.",
3473                              ret);
3474                 return ret;
3475         }
3476
3477         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3478         retval = rte_le_to_cpu_16(desc.retval);
3479
3480         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3481 }
3482
3483 static void
3484 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3485                      int *table_item_num)
3486 {
3487         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3488
3489         /*
3490          * In current version, we add one item in management table as below:
3491          * 0x0180C200000E -- LLDP MC address
3492          */
3493         tbl = mgr_table;
3494         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3495         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3496         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3497         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3498         tbl->i_port_bitmap = 0x1;
3499         *table_item_num = 1;
3500 }
3501
3502 static int
3503 hns3_init_mgr_tbl(struct hns3_hw *hw)
3504 {
3505 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3506         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3507         int table_item_num;
3508         int ret;
3509         int i;
3510
3511         memset(mgr_table, 0, sizeof(mgr_table));
3512         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3513         for (i = 0; i < table_item_num; i++) {
3514                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3515                 if (ret) {
3516                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3517                                      ret);
3518                         return ret;
3519                 }
3520         }
3521
3522         return 0;
3523 }
3524
3525 static void
3526 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3527                         bool en_mc, bool en_bc, int vport_id)
3528 {
3529         if (!param)
3530                 return;
3531
3532         memset(param, 0, sizeof(struct hns3_promisc_param));
3533         if (en_uc)
3534                 param->enable = HNS3_PROMISC_EN_UC;
3535         if (en_mc)
3536                 param->enable |= HNS3_PROMISC_EN_MC;
3537         if (en_bc)
3538                 param->enable |= HNS3_PROMISC_EN_BC;
3539         param->vf_id = vport_id;
3540 }
3541
3542 static int
3543 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3544 {
3545         struct hns3_promisc_cfg_cmd *req;
3546         struct hns3_cmd_desc desc;
3547         int ret;
3548
3549         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3550
3551         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3552         req->vf_id = param->vf_id;
3553         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3554             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3555
3556         ret = hns3_cmd_send(hw, &desc, 1);
3557         if (ret)
3558                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3559
3560         return ret;
3561 }
3562
3563 static int
3564 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3565 {
3566         struct hns3_promisc_param param;
3567         bool en_bc_pmc = true;
3568         uint8_t vf_id;
3569         int ret;
3570
3571         /*
3572          * In current version VF is not supported when PF is driven by DPDK
3573          * driver, the PF-related vf_id is 0, just need to configure parameters
3574          * for vf_id 0.
3575          */
3576         vf_id = 0;
3577
3578         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3579         ret = hns3_cmd_set_promisc_mode(hw, &param);
3580         if (ret)
3581                 return ret;
3582
3583         return 0;
3584 }
3585
3586 static int
3587 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3588 {
3589         struct hns3_adapter *hns = dev->data->dev_private;
3590         struct hns3_hw *hw = &hns->hw;
3591         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3592         int ret = 0;
3593
3594         rte_spinlock_lock(&hw->lock);
3595         ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3596         rte_spinlock_unlock(&hw->lock);
3597         if (ret)
3598                 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3599
3600         return ret;
3601 }
3602
3603 static int
3604 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3605 {
3606         struct hns3_adapter *hns = dev->data->dev_private;
3607         struct hns3_hw *hw = &hns->hw;
3608         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3609         int ret = 0;
3610
3611         /* If now in all_multicast mode, must remain in all_multicast mode. */
3612         rte_spinlock_lock(&hw->lock);
3613         ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3614         rte_spinlock_unlock(&hw->lock);
3615         if (ret)
3616                 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3617
3618         return ret;
3619 }
3620
3621 static int
3622 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3623 {
3624         struct hns3_adapter *hns = dev->data->dev_private;
3625         struct hns3_hw *hw = &hns->hw;
3626         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3627         int ret = 0;
3628
3629         rte_spinlock_lock(&hw->lock);
3630         ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3631         rte_spinlock_unlock(&hw->lock);
3632         if (ret)
3633                 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3634
3635         return ret;
3636 }
3637
3638 static int
3639 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3640 {
3641         struct hns3_adapter *hns = dev->data->dev_private;
3642         struct hns3_hw *hw = &hns->hw;
3643         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3644         int ret = 0;
3645
3646         /* If now in promiscuous mode, must remain in all_multicast mode. */
3647         if (dev->data->promiscuous == 1)
3648                 return 0;
3649
3650         rte_spinlock_lock(&hw->lock);
3651         ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3652         rte_spinlock_unlock(&hw->lock);
3653         if (ret)
3654                 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3655
3656         return ret;
3657 }
3658
3659 static int
3660 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3661 {
3662         struct hns3_hw *hw = &hns->hw;
3663         bool en_mc_pmc;
3664         bool en_uc_pmc;
3665
3666         en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3667         en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3668
3669         return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3670 }
3671
3672 static int
3673 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3674 {
3675         struct hns3_sfp_speed_cmd *resp;
3676         struct hns3_cmd_desc desc;
3677         int ret;
3678
3679         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3680         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3681         ret = hns3_cmd_send(hw, &desc, 1);
3682         if (ret == -EOPNOTSUPP) {
3683                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3684                 return ret;
3685         } else if (ret) {
3686                 hns3_err(hw, "get sfp speed failed %d", ret);
3687                 return ret;
3688         }
3689
3690         *speed = resp->sfp_speed;
3691
3692         return 0;
3693 }
3694
3695 static uint8_t
3696 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3697 {
3698         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3699                 duplex = ETH_LINK_FULL_DUPLEX;
3700
3701         return duplex;
3702 }
3703
3704 static int
3705 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3706 {
3707         struct hns3_mac *mac = &hw->mac;
3708         int ret;
3709
3710         duplex = hns3_check_speed_dup(duplex, speed);
3711         if (mac->link_speed == speed && mac->link_duplex == duplex)
3712                 return 0;
3713
3714         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3715         if (ret)
3716                 return ret;
3717
3718         mac->link_speed = speed;
3719         mac->link_duplex = duplex;
3720
3721         return 0;
3722 }
3723
3724 static int
3725 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3726 {
3727         struct hns3_adapter *hns = eth_dev->data->dev_private;
3728         struct hns3_hw *hw = &hns->hw;
3729         struct hns3_pf *pf = &hns->pf;
3730         uint32_t speed;
3731         int ret;
3732
3733         /* If IMP do not support get SFP/qSFP speed, return directly */
3734         if (!pf->support_sfp_query)
3735                 return 0;
3736
3737         ret = hns3_get_sfp_speed(hw, &speed);
3738         if (ret == -EOPNOTSUPP) {
3739                 pf->support_sfp_query = false;
3740                 return ret;
3741         } else if (ret)
3742                 return ret;
3743
3744         if (speed == ETH_SPEED_NUM_NONE)
3745                 return 0; /* do nothing if no SFP */
3746
3747         /* Config full duplex for SFP */
3748         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3749 }
3750
3751 static int
3752 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3753 {
3754         struct hns3_config_mac_mode_cmd *req;
3755         struct hns3_cmd_desc desc;
3756         uint32_t loop_en = 0;
3757         uint8_t val = 0;
3758         int ret;
3759
3760         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3761
3762         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3763         if (enable)
3764                 val = 1;
3765         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3766         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3767         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3768         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3769         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3770         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3771         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3772         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3773         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3774         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3775         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3776         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3777         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3778         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3779         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3780
3781         ret = hns3_cmd_send(hw, &desc, 1);
3782         if (ret)
3783                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3784
3785         return ret;
3786 }
3787
3788 static int
3789 hns3_get_mac_link_status(struct hns3_hw *hw)
3790 {
3791         struct hns3_link_status_cmd *req;
3792         struct hns3_cmd_desc desc;
3793         int link_status;
3794         int ret;
3795
3796         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3797         ret = hns3_cmd_send(hw, &desc, 1);
3798         if (ret) {
3799                 hns3_err(hw, "get link status cmd failed %d", ret);
3800                 return ret;
3801         }
3802
3803         req = (struct hns3_link_status_cmd *)desc.data;
3804         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3805
3806         return !!link_status;
3807 }
3808
3809 static void
3810 hns3_update_link_status(struct hns3_hw *hw)
3811 {
3812         int state;
3813
3814         state = hns3_get_mac_link_status(hw);
3815         if (state != hw->mac.link_status)
3816                 hw->mac.link_status = state;
3817 }
3818
3819 static void
3820 hns3_service_handler(void *param)
3821 {
3822         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3823         struct hns3_adapter *hns = eth_dev->data->dev_private;
3824         struct hns3_hw *hw = &hns->hw;
3825
3826         if (!hns3_is_reset_pending(hns)) {
3827                 hns3_update_speed_duplex(eth_dev);
3828                 hns3_update_link_status(hw);
3829         } else
3830                 hns3_warn(hw, "Cancel the query when reset is pending");
3831
3832         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3833 }
3834
3835 static int
3836 hns3_init_hardware(struct hns3_adapter *hns)
3837 {
3838         struct hns3_hw *hw = &hns->hw;
3839         int ret;
3840
3841         ret = hns3_map_tqp(hw);
3842         if (ret) {
3843                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3844                 return ret;
3845         }
3846
3847         ret = hns3_init_umv_space(hw);
3848         if (ret) {
3849                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3850                 return ret;
3851         }
3852
3853         ret = hns3_mac_init(hw);
3854         if (ret) {
3855                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3856                 goto err_mac_init;
3857         }
3858
3859         ret = hns3_init_mgr_tbl(hw);
3860         if (ret) {
3861                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3862                 goto err_mac_init;
3863         }
3864
3865         ret = hns3_set_promisc_mode(hw, false, false);
3866         if (ret) {
3867                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3868                 goto err_mac_init;
3869         }
3870
3871         ret = hns3_init_vlan_config(hns);
3872         if (ret) {
3873                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3874                 goto err_mac_init;
3875         }
3876
3877         ret = hns3_dcb_init(hw);
3878         if (ret) {
3879                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3880                 goto err_mac_init;
3881         }
3882
3883         ret = hns3_init_fd_config(hns);
3884         if (ret) {
3885                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3886                 goto err_mac_init;
3887         }
3888
3889         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3890         if (ret) {
3891                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3892                 goto err_mac_init;
3893         }
3894
3895         ret = hns3_config_gro(hw, false);
3896         if (ret) {
3897                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3898                 goto err_mac_init;
3899         }
3900         return 0;
3901
3902 err_mac_init:
3903         hns3_uninit_umv_space(hw);
3904         return ret;
3905 }
3906
3907 static int
3908 hns3_init_pf(struct rte_eth_dev *eth_dev)
3909 {
3910         struct rte_device *dev = eth_dev->device;
3911         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3912         struct hns3_adapter *hns = eth_dev->data->dev_private;
3913         struct hns3_hw *hw = &hns->hw;
3914         int ret;
3915
3916         PMD_INIT_FUNC_TRACE();
3917
3918         /* Get hardware io base address from pcie BAR2 IO space */
3919         hw->io_base = pci_dev->mem_resource[2].addr;
3920
3921         /* Firmware command queue initialize */
3922         ret = hns3_cmd_init_queue(hw);
3923         if (ret) {
3924                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3925                 goto err_cmd_init_queue;
3926         }
3927
3928         hns3_clear_all_event_cause(hw);
3929
3930         /* Firmware command initialize */
3931         ret = hns3_cmd_init(hw);
3932         if (ret) {
3933                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3934                 goto err_cmd_init;
3935         }
3936
3937         ret = rte_intr_callback_register(&pci_dev->intr_handle,
3938                                          hns3_interrupt_handler,
3939                                          eth_dev);
3940         if (ret) {
3941                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3942                 goto err_intr_callback_register;
3943         }
3944
3945         /* Enable interrupt */
3946         rte_intr_enable(&pci_dev->intr_handle);
3947         hns3_pf_enable_irq0(hw);
3948
3949         /* Get configuration */
3950         ret = hns3_get_configuration(hw);
3951         if (ret) {
3952                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3953                 goto err_get_config;
3954         }
3955
3956         ret = hns3_init_hardware(hns);
3957         if (ret) {
3958                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
3959                 goto err_get_config;
3960         }
3961
3962         /* Initialize flow director filter list & hash */
3963         ret = hns3_fdir_filter_init(hns);
3964         if (ret) {
3965                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
3966                 goto err_hw_init;
3967         }
3968
3969         hns3_set_default_rss_args(hw);
3970
3971         ret = hns3_enable_hw_error_intr(hns, true);
3972         if (ret) {
3973                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
3974                              ret);
3975                 goto err_fdir;
3976         }
3977
3978         return 0;
3979
3980 err_fdir:
3981         hns3_fdir_filter_uninit(hns);
3982 err_hw_init:
3983         hns3_uninit_umv_space(hw);
3984
3985 err_get_config:
3986         hns3_pf_disable_irq0(hw);
3987         rte_intr_disable(&pci_dev->intr_handle);
3988         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
3989                              eth_dev);
3990
3991 err_intr_callback_register:
3992         hns3_cmd_uninit(hw);
3993
3994 err_cmd_init:
3995         hns3_cmd_destroy_queue(hw);
3996
3997 err_cmd_init_queue:
3998         hw->io_base = NULL;
3999
4000         return ret;
4001 }
4002
4003 static void
4004 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4005 {
4006         struct hns3_adapter *hns = eth_dev->data->dev_private;
4007         struct rte_device *dev = eth_dev->device;
4008         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4009         struct hns3_hw *hw = &hns->hw;
4010
4011         PMD_INIT_FUNC_TRACE();
4012
4013         hns3_enable_hw_error_intr(hns, false);
4014         hns3_rss_uninit(hns);
4015         hns3_fdir_filter_uninit(hns);
4016         hns3_uninit_umv_space(hw);
4017         hns3_pf_disable_irq0(hw);
4018         rte_intr_disable(&pci_dev->intr_handle);
4019         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4020                              eth_dev);
4021         hns3_cmd_uninit(hw);
4022         hns3_cmd_destroy_queue(hw);
4023         hw->io_base = NULL;
4024 }
4025
4026 static int
4027 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4028 {
4029         struct hns3_hw *hw = &hns->hw;
4030         int ret;
4031
4032         ret = hns3_dcb_cfg_update(hns);
4033         if (ret)
4034                 return ret;
4035
4036         /* Enable queues */
4037         ret = hns3_start_queues(hns, reset_queue);
4038         if (ret) {
4039                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4040                 return ret;
4041         }
4042
4043         /* Enable MAC */
4044         ret = hns3_cfg_mac_mode(hw, true);
4045         if (ret) {
4046                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4047                 goto err_config_mac_mode;
4048         }
4049         return 0;
4050
4051 err_config_mac_mode:
4052         hns3_stop_queues(hns, true);
4053         return ret;
4054 }
4055
4056 static int
4057 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4058 {
4059         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4061         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4062         uint32_t intr_vector;
4063         uint8_t base = 0;
4064         uint8_t vec = 0;
4065         uint16_t q_id;
4066         int ret;
4067
4068         if (dev->data->dev_conf.intr_conf.rxq == 0)
4069                 return 0;
4070
4071         /* disable uio/vfio intr/eventfd mapping */
4072         rte_intr_disable(intr_handle);
4073
4074         /* check and configure queue intr-vector mapping */
4075         if (rte_intr_cap_multiple(intr_handle) ||
4076             !RTE_ETH_DEV_SRIOV(dev).active) {
4077                 intr_vector = dev->data->nb_rx_queues;
4078                 /* creates event fd for each intr vector when MSIX is used */
4079                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4080                         return -EINVAL;
4081         }
4082         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4083                 intr_handle->intr_vec =
4084                         rte_zmalloc("intr_vec",
4085                                     dev->data->nb_rx_queues * sizeof(int), 0);
4086                 if (intr_handle->intr_vec == NULL) {
4087                         hns3_err(hw, "Failed to allocate %d rx_queues"
4088                                      " intr_vec", dev->data->nb_rx_queues);
4089                         ret = -ENOMEM;
4090                         goto alloc_intr_vec_error;
4091                 }
4092         }
4093
4094         if (rte_intr_allow_others(intr_handle)) {
4095                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4096                 base = RTE_INTR_VEC_RXTX_OFFSET;
4097         }
4098         if (rte_intr_dp_is_en(intr_handle)) {
4099                 for (q_id = 0; q_id < dev->data->nb_rx_queues; q_id++) {
4100                         ret = hns3_bind_ring_with_vector(dev, vec, true, q_id);
4101                         if (ret)
4102                                 goto bind_vector_error;
4103                         intr_handle->intr_vec[q_id] = vec;
4104                         if (vec < base + intr_handle->nb_efd - 1)
4105                                 vec++;
4106                 }
4107         }
4108         rte_intr_enable(intr_handle);
4109         return 0;
4110
4111 bind_vector_error:
4112         rte_intr_efd_disable(intr_handle);
4113         if (intr_handle->intr_vec) {
4114                 free(intr_handle->intr_vec);
4115                 intr_handle->intr_vec = NULL;
4116         }
4117         return ret;
4118 alloc_intr_vec_error:
4119         rte_intr_efd_disable(intr_handle);
4120         return ret;
4121 }
4122
4123 static int
4124 hns3_dev_start(struct rte_eth_dev *dev)
4125 {
4126         struct hns3_adapter *hns = dev->data->dev_private;
4127         struct hns3_hw *hw = &hns->hw;
4128         int ret = 0;
4129
4130         PMD_INIT_FUNC_TRACE();
4131         if (rte_atomic16_read(&hw->reset.resetting))
4132                 return -EBUSY;
4133
4134         rte_spinlock_lock(&hw->lock);
4135         hw->adapter_state = HNS3_NIC_STARTING;
4136
4137         ret = hns3_do_start(hns, true);
4138         if (ret) {
4139                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4140                 rte_spinlock_unlock(&hw->lock);
4141                 return ret;
4142         }
4143
4144         hw->adapter_state = HNS3_NIC_STARTED;
4145         rte_spinlock_unlock(&hw->lock);
4146
4147         ret = hns3_map_rx_interrupt(dev);
4148         if (ret)
4149                 return ret;
4150         hns3_set_rxtx_function(dev);
4151         hns3_mp_req_start_rxtx(dev);
4152
4153         hns3_info(hw, "hns3 dev start successful!");
4154         return 0;
4155 }
4156
4157 static int
4158 hns3_do_stop(struct hns3_adapter *hns)
4159 {
4160         struct hns3_hw *hw = &hns->hw;
4161         bool reset_queue;
4162         int ret;
4163
4164         ret = hns3_cfg_mac_mode(hw, false);
4165         if (ret)
4166                 return ret;
4167         hw->mac.link_status = ETH_LINK_DOWN;
4168
4169         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4170                 hns3_configure_all_mac_addr(hns, true);
4171                 reset_queue = true;
4172         } else
4173                 reset_queue = false;
4174         hw->mac.default_addr_setted = false;
4175         return hns3_stop_queues(hns, reset_queue);
4176 }
4177
4178 static void
4179 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4180 {
4181         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4182         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4183         uint8_t base = 0;
4184         uint8_t vec = 0;
4185         uint16_t q_id;
4186
4187         if (dev->data->dev_conf.intr_conf.rxq == 0)
4188                 return;
4189
4190         /* unmap the ring with vector */
4191         if (rte_intr_allow_others(intr_handle)) {
4192                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4193                 base = RTE_INTR_VEC_RXTX_OFFSET;
4194         }
4195         if (rte_intr_dp_is_en(intr_handle)) {
4196                 for (q_id = 0; q_id < dev->data->nb_rx_queues; q_id++) {
4197                         (void)hns3_bind_ring_with_vector(dev, vec, false, q_id);
4198                         if (vec < base + intr_handle->nb_efd - 1)
4199                                 vec++;
4200                 }
4201         }
4202         /* Clean datapath event and queue/vec mapping */
4203         rte_intr_efd_disable(intr_handle);
4204         if (intr_handle->intr_vec) {
4205                 rte_free(intr_handle->intr_vec);
4206                 intr_handle->intr_vec = NULL;
4207         }
4208 }
4209
4210 static void
4211 hns3_dev_stop(struct rte_eth_dev *dev)
4212 {
4213         struct hns3_adapter *hns = dev->data->dev_private;
4214         struct hns3_hw *hw = &hns->hw;
4215
4216         PMD_INIT_FUNC_TRACE();
4217
4218         hw->adapter_state = HNS3_NIC_STOPPING;
4219         hns3_set_rxtx_function(dev);
4220         rte_wmb();
4221         /* Disable datapath on secondary process. */
4222         hns3_mp_req_stop_rxtx(dev);
4223         /* Prevent crashes when queues are still in use. */
4224         rte_delay_ms(hw->tqps_num);
4225
4226         rte_spinlock_lock(&hw->lock);
4227         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4228                 hns3_do_stop(hns);
4229                 hns3_dev_release_mbufs(hns);
4230                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4231         }
4232         rte_spinlock_unlock(&hw->lock);
4233         hns3_unmap_rx_interrupt(dev);
4234 }
4235
4236 static void
4237 hns3_dev_close(struct rte_eth_dev *eth_dev)
4238 {
4239         struct hns3_adapter *hns = eth_dev->data->dev_private;
4240         struct hns3_hw *hw = &hns->hw;
4241
4242         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4243                 rte_free(eth_dev->process_private);
4244                 eth_dev->process_private = NULL;
4245                 return;
4246         }
4247
4248         if (hw->adapter_state == HNS3_NIC_STARTED)
4249                 hns3_dev_stop(eth_dev);
4250
4251         hw->adapter_state = HNS3_NIC_CLOSING;
4252         hns3_reset_abort(hns);
4253         hw->adapter_state = HNS3_NIC_CLOSED;
4254         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4255
4256         hns3_configure_all_mc_mac_addr(hns, true);
4257         hns3_remove_all_vlan_table(hns);
4258         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4259         hns3_uninit_pf(eth_dev);
4260         hns3_free_all_queues(eth_dev);
4261         rte_free(hw->reset.wait_data);
4262         rte_free(eth_dev->process_private);
4263         eth_dev->process_private = NULL;
4264         hns3_mp_uninit_primary();
4265         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4266 }
4267
4268 static int
4269 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4270 {
4271         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4272         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4273
4274         fc_conf->pause_time = pf->pause_time;
4275
4276         /* return fc current mode */
4277         switch (hw->current_mode) {
4278         case HNS3_FC_FULL:
4279                 fc_conf->mode = RTE_FC_FULL;
4280                 break;
4281         case HNS3_FC_TX_PAUSE:
4282                 fc_conf->mode = RTE_FC_TX_PAUSE;
4283                 break;
4284         case HNS3_FC_RX_PAUSE:
4285                 fc_conf->mode = RTE_FC_RX_PAUSE;
4286                 break;
4287         case HNS3_FC_NONE:
4288         default:
4289                 fc_conf->mode = RTE_FC_NONE;
4290                 break;
4291         }
4292
4293         return 0;
4294 }
4295
4296 static void
4297 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4298 {
4299         switch (mode) {
4300         case RTE_FC_NONE:
4301                 hw->requested_mode = HNS3_FC_NONE;
4302                 break;
4303         case RTE_FC_RX_PAUSE:
4304                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4305                 break;
4306         case RTE_FC_TX_PAUSE:
4307                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4308                 break;
4309         case RTE_FC_FULL:
4310                 hw->requested_mode = HNS3_FC_FULL;
4311                 break;
4312         default:
4313                 hw->requested_mode = HNS3_FC_NONE;
4314                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4315                           "configured to RTE_FC_NONE", mode);
4316                 break;
4317         }
4318 }
4319
4320 static int
4321 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4322 {
4323         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4325         int ret;
4326
4327         if (fc_conf->high_water || fc_conf->low_water ||
4328             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4329                 hns3_err(hw, "Unsupported flow control settings specified, "
4330                          "high_water(%u), low_water(%u), send_xon(%u) and "
4331                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4332                          fc_conf->high_water, fc_conf->low_water,
4333                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4334                 return -EINVAL;
4335         }
4336         if (fc_conf->autoneg) {
4337                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4338                 return -EINVAL;
4339         }
4340         if (!fc_conf->pause_time) {
4341                 hns3_err(hw, "Invalid pause time %d setting.",
4342                          fc_conf->pause_time);
4343                 return -EINVAL;
4344         }
4345
4346         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4347             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4348                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4349                          "current_fc_status = %d", hw->current_fc_status);
4350                 return -EOPNOTSUPP;
4351         }
4352
4353         hns3_get_fc_mode(hw, fc_conf->mode);
4354         if (hw->requested_mode == hw->current_mode &&
4355             pf->pause_time == fc_conf->pause_time)
4356                 return 0;
4357
4358         rte_spinlock_lock(&hw->lock);
4359         ret = hns3_fc_enable(dev, fc_conf);
4360         rte_spinlock_unlock(&hw->lock);
4361
4362         return ret;
4363 }
4364
4365 static int
4366 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4367                             struct rte_eth_pfc_conf *pfc_conf)
4368 {
4369         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4371         uint8_t priority;
4372         int ret;
4373
4374         if (!hns3_dev_dcb_supported(hw)) {
4375                 hns3_err(hw, "This port does not support dcb configurations.");
4376                 return -EOPNOTSUPP;
4377         }
4378
4379         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4380             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4381                 hns3_err(hw, "Unsupported flow control settings specified, "
4382                          "high_water(%u), low_water(%u), send_xon(%u) and "
4383                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4384                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4385                          pfc_conf->fc.send_xon,
4386                          pfc_conf->fc.mac_ctrl_frame_fwd);
4387                 return -EINVAL;
4388         }
4389         if (pfc_conf->fc.autoneg) {
4390                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4391                 return -EINVAL;
4392         }
4393         if (pfc_conf->fc.pause_time == 0) {
4394                 hns3_err(hw, "Invalid pause time %d setting.",
4395                          pfc_conf->fc.pause_time);
4396                 return -EINVAL;
4397         }
4398
4399         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4400             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4401                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4402                              "current_fc_status = %d", hw->current_fc_status);
4403                 return -EOPNOTSUPP;
4404         }
4405
4406         priority = pfc_conf->priority;
4407         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4408         if (hw->dcb_info.pfc_en & BIT(priority) &&
4409             hw->requested_mode == hw->current_mode &&
4410             pfc_conf->fc.pause_time == pf->pause_time)
4411                 return 0;
4412
4413         rte_spinlock_lock(&hw->lock);
4414         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4415         rte_spinlock_unlock(&hw->lock);
4416
4417         return ret;
4418 }
4419
4420 static int
4421 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4422 {
4423         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4424         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4425         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4426         int i;
4427
4428         rte_spinlock_lock(&hw->lock);
4429         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4430                 dcb_info->nb_tcs = pf->local_max_tc;
4431         else
4432                 dcb_info->nb_tcs = 1;
4433
4434         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4435                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4436         for (i = 0; i < dcb_info->nb_tcs; i++)
4437                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4438
4439         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4440                 dcb_info->tc_queue.tc_rxq[0][i].base =
4441                                         hw->tc_queue[i].tqp_offset;
4442                 dcb_info->tc_queue.tc_txq[0][i].base =
4443                                         hw->tc_queue[i].tqp_offset;
4444                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
4445                                         hw->tc_queue[i].tqp_count;
4446                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4447                                         hw->tc_queue[i].tqp_count;
4448         }
4449         rte_spinlock_unlock(&hw->lock);
4450
4451         return 0;
4452 }
4453
4454 static int
4455 hns3_reinit_dev(struct hns3_adapter *hns)
4456 {
4457         struct hns3_hw *hw = &hns->hw;
4458         int ret;
4459
4460         ret = hns3_cmd_init(hw);
4461         if (ret) {
4462                 hns3_err(hw, "Failed to init cmd: %d", ret);
4463                 return ret;
4464         }
4465
4466         ret = hns3_reset_all_queues(hns);
4467         if (ret) {
4468                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4469                 goto err_init;
4470         }
4471
4472         ret = hns3_init_hardware(hns);
4473         if (ret) {
4474                 hns3_err(hw, "Failed to init hardware: %d", ret);
4475                 goto err_init;
4476         }
4477
4478         ret = hns3_enable_hw_error_intr(hns, true);
4479         if (ret) {
4480                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4481                              ret);
4482                 goto err_mac_init;
4483         }
4484         hns3_info(hw, "Reset done, driver initialization finished.");
4485
4486         return 0;
4487
4488 err_mac_init:
4489         hns3_uninit_umv_space(hw);
4490 err_init:
4491         hns3_cmd_uninit(hw);
4492
4493         return ret;
4494 }
4495
4496 static bool
4497 is_pf_reset_done(struct hns3_hw *hw)
4498 {
4499         uint32_t val, reg, reg_bit;
4500
4501         switch (hw->reset.level) {
4502         case HNS3_IMP_RESET:
4503                 reg = HNS3_GLOBAL_RESET_REG;
4504                 reg_bit = HNS3_IMP_RESET_BIT;
4505                 break;
4506         case HNS3_GLOBAL_RESET:
4507                 reg = HNS3_GLOBAL_RESET_REG;
4508                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4509                 break;
4510         case HNS3_FUNC_RESET:
4511                 reg = HNS3_FUN_RST_ING;
4512                 reg_bit = HNS3_FUN_RST_ING_B;
4513                 break;
4514         case HNS3_FLR_RESET:
4515         default:
4516                 hns3_err(hw, "Wait for unsupported reset level: %d",
4517                          hw->reset.level);
4518                 return true;
4519         }
4520         val = hns3_read_dev(hw, reg);
4521         if (hns3_get_bit(val, reg_bit))
4522                 return false;
4523         else
4524                 return true;
4525 }
4526
4527 bool
4528 hns3_is_reset_pending(struct hns3_adapter *hns)
4529 {
4530         struct hns3_hw *hw = &hns->hw;
4531         enum hns3_reset_level reset;
4532
4533         hns3_check_event_cause(hns, NULL);
4534         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4535         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4536                 hns3_warn(hw, "High level reset %d is pending", reset);
4537                 return true;
4538         }
4539         reset = hns3_get_reset_level(hns, &hw->reset.request);
4540         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4541                 hns3_warn(hw, "High level reset %d is request", reset);
4542                 return true;
4543         }
4544         return false;
4545 }
4546
4547 static int
4548 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4549 {
4550         struct hns3_hw *hw = &hns->hw;
4551         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4552         struct timeval tv;
4553
4554         if (wait_data->result == HNS3_WAIT_SUCCESS)
4555                 return 0;
4556         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4557                 gettimeofday(&tv, NULL);
4558                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4559                           tv.tv_sec, tv.tv_usec);
4560                 return -ETIME;
4561         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4562                 return -EAGAIN;
4563
4564         wait_data->hns = hns;
4565         wait_data->check_completion = is_pf_reset_done;
4566         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4567                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4568         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4569         wait_data->count = HNS3_RESET_WAIT_CNT;
4570         wait_data->result = HNS3_WAIT_REQUEST;
4571         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4572         return -EAGAIN;
4573 }
4574
4575 static int
4576 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4577 {
4578         struct hns3_cmd_desc desc;
4579         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4580
4581         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4582         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4583         req->fun_reset_vfid = func_id;
4584
4585         return hns3_cmd_send(hw, &desc, 1);
4586 }
4587
4588 static int
4589 hns3_imp_reset_cmd(struct hns3_hw *hw)
4590 {
4591         struct hns3_cmd_desc desc;
4592
4593         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4594         desc.data[0] = 0xeedd;
4595
4596         return hns3_cmd_send(hw, &desc, 1);
4597 }
4598
4599 static void
4600 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4601 {
4602         struct hns3_hw *hw = &hns->hw;
4603         struct timeval tv;
4604         uint32_t val;
4605
4606         gettimeofday(&tv, NULL);
4607         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4608             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4609                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4610                           tv.tv_sec, tv.tv_usec);
4611                 return;
4612         }
4613
4614         switch (reset_level) {
4615         case HNS3_IMP_RESET:
4616                 hns3_imp_reset_cmd(hw);
4617                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4618                           tv.tv_sec, tv.tv_usec);
4619                 break;
4620         case HNS3_GLOBAL_RESET:
4621                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4622                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4623                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4624                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4625                           tv.tv_sec, tv.tv_usec);
4626                 break;
4627         case HNS3_FUNC_RESET:
4628                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4629                           tv.tv_sec, tv.tv_usec);
4630                 /* schedule again to check later */
4631                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4632                 hns3_schedule_reset(hns);
4633                 break;
4634         default:
4635                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4636                 return;
4637         }
4638         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4639 }
4640
4641 static enum hns3_reset_level
4642 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4643 {
4644         struct hns3_hw *hw = &hns->hw;
4645         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4646
4647         /* Return the highest priority reset level amongst all */
4648         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4649                 reset_level = HNS3_IMP_RESET;
4650         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4651                 reset_level = HNS3_GLOBAL_RESET;
4652         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4653                 reset_level = HNS3_FUNC_RESET;
4654         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4655                 reset_level = HNS3_FLR_RESET;
4656
4657         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4658                 return HNS3_NONE_RESET;
4659
4660         return reset_level;
4661 }
4662
4663 static int
4664 hns3_prepare_reset(struct hns3_adapter *hns)
4665 {
4666         struct hns3_hw *hw = &hns->hw;
4667         uint32_t reg_val;
4668         int ret;
4669
4670         switch (hw->reset.level) {
4671         case HNS3_FUNC_RESET:
4672                 ret = hns3_func_reset_cmd(hw, 0);
4673                 if (ret)
4674                         return ret;
4675
4676                 /*
4677                  * After performaning pf reset, it is not necessary to do the
4678                  * mailbox handling or send any command to firmware, because
4679                  * any mailbox handling or command to firmware is only valid
4680                  * after hns3_cmd_init is called.
4681                  */
4682                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4683                 hw->reset.stats.request_cnt++;
4684                 break;
4685         case HNS3_IMP_RESET:
4686                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4687                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4688                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4689                 break;
4690         default:
4691                 break;
4692         }
4693         return 0;
4694 }
4695
4696 static int
4697 hns3_set_rst_done(struct hns3_hw *hw)
4698 {
4699         struct hns3_pf_rst_done_cmd *req;
4700         struct hns3_cmd_desc desc;
4701
4702         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4703         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4704         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4705         return hns3_cmd_send(hw, &desc, 1);
4706 }
4707
4708 static int
4709 hns3_stop_service(struct hns3_adapter *hns)
4710 {
4711         struct hns3_hw *hw = &hns->hw;
4712         struct rte_eth_dev *eth_dev;
4713
4714         eth_dev = &rte_eth_devices[hw->data->port_id];
4715         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4716         hw->mac.link_status = ETH_LINK_DOWN;
4717
4718         hns3_set_rxtx_function(eth_dev);
4719         rte_wmb();
4720         /* Disable datapath on secondary process. */
4721         hns3_mp_req_stop_rxtx(eth_dev);
4722         rte_delay_ms(hw->tqps_num);
4723
4724         rte_spinlock_lock(&hw->lock);
4725         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4726             hw->adapter_state == HNS3_NIC_STOPPING) {
4727                 hns3_do_stop(hns);
4728                 hw->reset.mbuf_deferred_free = true;
4729         } else
4730                 hw->reset.mbuf_deferred_free = false;
4731
4732         /*
4733          * It is cumbersome for hardware to pick-and-choose entries for deletion
4734          * from table space. Hence, for function reset software intervention is
4735          * required to delete the entries
4736          */
4737         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4738                 hns3_configure_all_mc_mac_addr(hns, true);
4739         rte_spinlock_unlock(&hw->lock);
4740
4741         return 0;
4742 }
4743
4744 static int
4745 hns3_start_service(struct hns3_adapter *hns)
4746 {
4747         struct hns3_hw *hw = &hns->hw;
4748         struct rte_eth_dev *eth_dev;
4749
4750         if (hw->reset.level == HNS3_IMP_RESET ||
4751             hw->reset.level == HNS3_GLOBAL_RESET)
4752                 hns3_set_rst_done(hw);
4753         eth_dev = &rte_eth_devices[hw->data->port_id];
4754         hns3_set_rxtx_function(eth_dev);
4755         hns3_mp_req_start_rxtx(eth_dev);
4756         hns3_service_handler(eth_dev);
4757         return 0;
4758 }
4759
4760 static int
4761 hns3_restore_conf(struct hns3_adapter *hns)
4762 {
4763         struct hns3_hw *hw = &hns->hw;
4764         int ret;
4765
4766         ret = hns3_configure_all_mac_addr(hns, false);
4767         if (ret)
4768                 return ret;
4769
4770         ret = hns3_configure_all_mc_mac_addr(hns, false);
4771         if (ret)
4772                 goto err_mc_mac;
4773
4774         ret = hns3_dev_promisc_restore(hns);
4775         if (ret)
4776                 goto err_promisc;
4777
4778         ret = hns3_restore_vlan_table(hns);
4779         if (ret)
4780                 goto err_promisc;
4781
4782         ret = hns3_restore_vlan_conf(hns);
4783         if (ret)
4784                 goto err_promisc;
4785
4786         ret = hns3_restore_all_fdir_filter(hns);
4787         if (ret)
4788                 goto err_promisc;
4789
4790         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4791                 ret = hns3_do_start(hns, false);
4792                 if (ret)
4793                         goto err_promisc;
4794                 hns3_info(hw, "hns3 dev restart successful!");
4795         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4796                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4797         return 0;
4798
4799 err_promisc:
4800         hns3_configure_all_mc_mac_addr(hns, true);
4801 err_mc_mac:
4802         hns3_configure_all_mac_addr(hns, true);
4803         return ret;
4804 }
4805
4806 static void
4807 hns3_reset_service(void *param)
4808 {
4809         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4810         struct hns3_hw *hw = &hns->hw;
4811         enum hns3_reset_level reset_level;
4812         struct timeval tv_delta;
4813         struct timeval tv_start;
4814         struct timeval tv;
4815         uint64_t msec;
4816         int ret;
4817
4818         /*
4819          * The interrupt is not triggered within the delay time.
4820          * The interrupt may have been lost. It is necessary to handle
4821          * the interrupt to recover from the error.
4822          */
4823         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4824                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4825                 hns3_err(hw, "Handling interrupts in delayed tasks");
4826                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4827                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4828                 if (reset_level == HNS3_NONE_RESET) {
4829                         hns3_err(hw, "No reset level is set, try IMP reset");
4830                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4831                 }
4832         }
4833         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4834
4835         /*
4836          * Check if there is any ongoing reset in the hardware. This status can
4837          * be checked from reset_pending. If there is then, we need to wait for
4838          * hardware to complete reset.
4839          *    a. If we are able to figure out in reasonable time that hardware
4840          *       has fully resetted then, we can proceed with driver, client
4841          *       reset.
4842          *    b. else, we can come back later to check this status so re-sched
4843          *       now.
4844          */
4845         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4846         if (reset_level != HNS3_NONE_RESET) {
4847                 gettimeofday(&tv_start, NULL);
4848                 ret = hns3_reset_process(hns, reset_level);
4849                 gettimeofday(&tv, NULL);
4850                 timersub(&tv, &tv_start, &tv_delta);
4851                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4852                        tv_delta.tv_usec / USEC_PER_MSEC;
4853                 if (msec > HNS3_RESET_PROCESS_MS)
4854                         hns3_err(hw, "%d handle long time delta %" PRIx64
4855                                      " ms time=%ld.%.6ld",
4856                                  hw->reset.level, msec,
4857                                  tv.tv_sec, tv.tv_usec);
4858                 if (ret == -EAGAIN)
4859                         return;
4860         }
4861
4862         /* Check if we got any *new* reset requests to be honored */
4863         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4864         if (reset_level != HNS3_NONE_RESET)
4865                 hns3_msix_process(hns, reset_level);
4866 }
4867
4868 static const struct eth_dev_ops hns3_eth_dev_ops = {
4869         .dev_start          = hns3_dev_start,
4870         .dev_stop           = hns3_dev_stop,
4871         .dev_close          = hns3_dev_close,
4872         .promiscuous_enable = hns3_dev_promiscuous_enable,
4873         .promiscuous_disable = hns3_dev_promiscuous_disable,
4874         .allmulticast_enable  = hns3_dev_allmulticast_enable,
4875         .allmulticast_disable = hns3_dev_allmulticast_disable,
4876         .mtu_set            = hns3_dev_mtu_set,
4877         .stats_get          = hns3_stats_get,
4878         .stats_reset        = hns3_stats_reset,
4879         .xstats_get         = hns3_dev_xstats_get,
4880         .xstats_get_names   = hns3_dev_xstats_get_names,
4881         .xstats_reset       = hns3_dev_xstats_reset,
4882         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
4883         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4884         .dev_infos_get          = hns3_dev_infos_get,
4885         .fw_version_get         = hns3_fw_version_get,
4886         .rx_queue_setup         = hns3_rx_queue_setup,
4887         .tx_queue_setup         = hns3_tx_queue_setup,
4888         .rx_queue_release       = hns3_dev_rx_queue_release,
4889         .tx_queue_release       = hns3_dev_tx_queue_release,
4890         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
4891         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
4892         .dev_configure          = hns3_dev_configure,
4893         .flow_ctrl_get          = hns3_flow_ctrl_get,
4894         .flow_ctrl_set          = hns3_flow_ctrl_set,
4895         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4896         .mac_addr_add           = hns3_add_mac_addr,
4897         .mac_addr_remove        = hns3_remove_mac_addr,
4898         .mac_addr_set           = hns3_set_default_mac_addr,
4899         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
4900         .link_update            = hns3_dev_link_update,
4901         .rss_hash_update        = hns3_dev_rss_hash_update,
4902         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
4903         .reta_update            = hns3_dev_rss_reta_update,
4904         .reta_query             = hns3_dev_rss_reta_query,
4905         .filter_ctrl            = hns3_dev_filter_ctrl,
4906         .vlan_filter_set        = hns3_vlan_filter_set,
4907         .vlan_tpid_set          = hns3_vlan_tpid_set,
4908         .vlan_offload_set       = hns3_vlan_offload_set,
4909         .vlan_pvid_set          = hns3_vlan_pvid_set,
4910         .get_reg                = hns3_get_regs,
4911         .get_dcb_info           = hns3_get_dcb_info,
4912         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4913 };
4914
4915 static const struct hns3_reset_ops hns3_reset_ops = {
4916         .reset_service       = hns3_reset_service,
4917         .stop_service        = hns3_stop_service,
4918         .prepare_reset       = hns3_prepare_reset,
4919         .wait_hardware_ready = hns3_wait_hardware_ready,
4920         .reinit_dev          = hns3_reinit_dev,
4921         .restore_conf        = hns3_restore_conf,
4922         .start_service       = hns3_start_service,
4923 };
4924
4925 static int
4926 hns3_dev_init(struct rte_eth_dev *eth_dev)
4927 {
4928         struct rte_device *dev = eth_dev->device;
4929         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4930         struct hns3_adapter *hns = eth_dev->data->dev_private;
4931         struct hns3_hw *hw = &hns->hw;
4932         uint16_t device_id = pci_dev->id.device_id;
4933         int ret;
4934
4935         PMD_INIT_FUNC_TRACE();
4936         eth_dev->process_private = (struct hns3_process_private *)
4937             rte_zmalloc_socket("hns3_filter_list",
4938                                sizeof(struct hns3_process_private),
4939                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4940         if (eth_dev->process_private == NULL) {
4941                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4942                 return -ENOMEM;
4943         }
4944         /* initialize flow filter lists */
4945         hns3_filterlist_init(eth_dev);
4946
4947         hns3_set_rxtx_function(eth_dev);
4948         eth_dev->dev_ops = &hns3_eth_dev_ops;
4949         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4950                 hns3_mp_init_secondary();
4951                 hw->secondary_cnt++;
4952                 return 0;
4953         }
4954
4955         hns3_mp_init_primary();
4956         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
4957
4958         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
4959             device_id == HNS3_DEV_ID_50GE_RDMA ||
4960             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
4961                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
4962
4963         hns->is_vf = false;
4964         hw->data = eth_dev->data;
4965
4966         /*
4967          * Set default max packet size according to the mtu
4968          * default vale in DPDK frame.
4969          */
4970         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
4971
4972         ret = hns3_reset_init(hw);
4973         if (ret)
4974                 goto err_init_reset;
4975         hw->reset.ops = &hns3_reset_ops;
4976
4977         ret = hns3_init_pf(eth_dev);
4978         if (ret) {
4979                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
4980                 goto err_init_pf;
4981         }
4982
4983         /* Allocate memory for storing MAC addresses */
4984         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
4985                                                sizeof(struct rte_ether_addr) *
4986                                                HNS3_UC_MACADDR_NUM, 0);
4987         if (eth_dev->data->mac_addrs == NULL) {
4988                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
4989                              "to store MAC addresses",
4990                              sizeof(struct rte_ether_addr) *
4991                              HNS3_UC_MACADDR_NUM);
4992                 ret = -ENOMEM;
4993                 goto err_rte_zmalloc;
4994         }
4995
4996         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
4997                             &eth_dev->data->mac_addrs[0]);
4998
4999         hw->adapter_state = HNS3_NIC_INITIALIZED;
5000         /*
5001          * Pass the information to the rte_eth_dev_close() that it should also
5002          * release the private port resources.
5003          */
5004         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5005
5006         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5007                 hns3_err(hw, "Reschedule reset service after dev_init");
5008                 hns3_schedule_reset(hns);
5009         } else {
5010                 /* IMP will wait ready flag before reset */
5011                 hns3_notify_reset_ready(hw, false);
5012         }
5013
5014         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
5015         hns3_info(hw, "hns3 dev initialization successful!");
5016         return 0;
5017
5018 err_rte_zmalloc:
5019         hns3_uninit_pf(eth_dev);
5020
5021 err_init_pf:
5022         rte_free(hw->reset.wait_data);
5023 err_init_reset:
5024         eth_dev->dev_ops = NULL;
5025         eth_dev->rx_pkt_burst = NULL;
5026         eth_dev->tx_pkt_burst = NULL;
5027         eth_dev->tx_pkt_prepare = NULL;
5028         rte_free(eth_dev->process_private);
5029         eth_dev->process_private = NULL;
5030         return ret;
5031 }
5032
5033 static int
5034 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5035 {
5036         struct hns3_adapter *hns = eth_dev->data->dev_private;
5037         struct hns3_hw *hw = &hns->hw;
5038
5039         PMD_INIT_FUNC_TRACE();
5040
5041         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5042                 return -EPERM;
5043
5044         eth_dev->dev_ops = NULL;
5045         eth_dev->rx_pkt_burst = NULL;
5046         eth_dev->tx_pkt_burst = NULL;
5047         eth_dev->tx_pkt_prepare = NULL;
5048         if (hw->adapter_state < HNS3_NIC_CLOSING)
5049                 hns3_dev_close(eth_dev);
5050
5051         hw->adapter_state = HNS3_NIC_REMOVED;
5052         return 0;
5053 }
5054
5055 static int
5056 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5057                    struct rte_pci_device *pci_dev)
5058 {
5059         return rte_eth_dev_pci_generic_probe(pci_dev,
5060                                              sizeof(struct hns3_adapter),
5061                                              hns3_dev_init);
5062 }
5063
5064 static int
5065 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5066 {
5067         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5068 }
5069
5070 static const struct rte_pci_id pci_id_hns3_map[] = {
5071         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5072         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5073         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5074         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5075         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5076         { .vendor_id = 0, /* sentinel */ },
5077 };
5078
5079 static struct rte_pci_driver rte_hns3_pmd = {
5080         .id_table = pci_id_hns3_map,
5081         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5082         .probe = eth_hns3_pci_probe,
5083         .remove = eth_hns3_pci_remove,
5084 };
5085
5086 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5087 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5088 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5089
5090 RTE_INIT(hns3_init_log)
5091 {
5092         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5093         if (hns3_logtype_init >= 0)
5094                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5095         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5096         if (hns3_logtype_driver >= 0)
5097                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5098 }