drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_OFFSET_160            160
 236         struct hns3_vlan_filter_pf_cfg_cmd *req;
 237         struct hns3_hw *hw = &hns->hw;
 238         uint8_t vlan_offset_byte_val;
 239         struct hns3_cmd_desc desc;
 240         uint8_t vlan_offset_byte;
 241         uint8_t vlan_offset_160;
 242         int ret;
 243
 244         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 245
 246         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 247         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 248         vlan_offset_byte_val = 1 << (vlan_id % 8);
 249
 250         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 251         req->vlan_offset = vlan_offset_160;
 252         req->vlan_cfg = on ? 0 : 1;
 253         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 254
 255         ret = hns3_cmd_send(hw, &desc, 1);
 256         if (ret)
 257                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 258                          vlan_id, ret);
 259
 260         return ret;
 261 }
 262
 263 static void
 264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 265 {
 266         struct hns3_user_vlan_table *vlan_entry;
 267         struct hns3_pf *pf = &hns->pf;
 268
 269         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 270                 if (vlan_entry->vlan_id == vlan_id) {
 271                         if (vlan_entry->hd_tbl_status)
 272                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 273                         LIST_REMOVE(vlan_entry, next);
 274                         rte_free(vlan_entry);
 275                         break;
 276                 }
 277         }
 278 }
 279
 280 static void
 281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 282                         bool writen_to_tbl)
 283 {
 284         struct hns3_user_vlan_table *vlan_entry;
 285         struct hns3_hw *hw = &hns->hw;
 286         struct hns3_pf *pf = &hns->pf;
 287
 288         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 289                 if (vlan_entry->vlan_id == vlan_id)
 290                         return;
 291         }
 292
 293         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 294         if (vlan_entry == NULL) {
 295                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 296                 return;
 297         }
 298
 299         vlan_entry->hd_tbl_status = writen_to_tbl;
 300         vlan_entry->vlan_id = vlan_id;
 301
 302         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 303 }
 304
 305 static int
 306 hns3_restore_vlan_table(struct hns3_adapter *hns)
 307 {
 308         struct hns3_user_vlan_table *vlan_entry;
 309         struct hns3_pf *pf = &hns->pf;
 310         uint16_t vlan_id;
 311         int ret = 0;
 312
 313         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 314                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 315                                                1);
 316                 return ret;
 317         }
 318
 319         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 320                 if (vlan_entry->hd_tbl_status) {
 321                         vlan_id = vlan_entry->vlan_id;
 322                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 323                         if (ret)
 324                                 break;
 325                 }
 326         }
 327
 328         return ret;
 329 }
 330
 331 static int
 332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 333 {
 334         struct hns3_pf *pf = &hns->pf;
 335         bool writen_to_tbl = false;
 336         int ret = 0;
 337
 338         /*
 339          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 340          * for normal packet, deleting vlan id 0 is not allowed.
 341          */
 342         if (on == 0 && vlan_id == 0)
 343                 return 0;
 344
 345         /*
 346          * When port base vlan enabled, we use port base vlan as the vlan
 347          * filter condition. In this case, we don't update vlan filter table
 348          * when user add new vlan or remove exist vlan, just update the
 349          * vlan list. The vlan id in vlan list will be writen in vlan filter
 350          * table until port base vlan disabled
 351          */
 352         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 353                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 354                 writen_to_tbl = true;
 355         }
 356
 357         if (ret == 0 && vlan_id) {
 358                 if (on)
 359                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 360                 else
 361                         hns3_rm_dev_vlan_table(hns, vlan_id);
 362         }
 363         return ret;
 364 }
 365
 366 static int
 367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 368 {
 369         struct hns3_adapter *hns = dev->data->dev_private;
 370         struct hns3_hw *hw = &hns->hw;
 371         int ret;
 372
 373         rte_spinlock_lock(&hw->lock);
 374         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 375         rte_spinlock_unlock(&hw->lock);
 376         return ret;
 377 }
 378
 379 static int
 380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 381                          uint16_t tpid)
 382 {
 383         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 384         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_cmd_desc desc;
 387         int ret;
 388
 389         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 390              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 391                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 392                 return -EINVAL;
 393         }
 394
 395         if (tpid != RTE_ETHER_TYPE_VLAN) {
 396                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 401         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 402
 403         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 407                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 408                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         }
 412
 413         ret = hns3_cmd_send(hw, &desc, 1);
 414         if (ret) {
 415                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 416                          ret);
 417                 return ret;
 418         }
 419
 420         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 421
 422         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 423         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 424         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 425
 426         ret = hns3_cmd_send(hw, &desc, 1);
 427         if (ret)
 428                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 429                          ret);
 430         return ret;
 431 }
 432
 433 static int
 434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 435                    uint16_t tpid)
 436 {
 437         struct hns3_adapter *hns = dev->data->dev_private;
 438         struct hns3_hw *hw = &hns->hw;
 439         int ret;
 440
 441         rte_spinlock_lock(&hw->lock);
 442         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 443         rte_spinlock_unlock(&hw->lock);
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 449                              struct hns3_rx_vtag_cfg *vcfg)
 450 {
 451         struct hns3_vport_vtag_rx_cfg_cmd *req;
 452         struct hns3_hw *hw = &hns->hw;
 453         struct hns3_cmd_desc desc;
 454         uint16_t vport_id;
 455         uint8_t bitmap;
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 459
 460         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 461         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 462                      vcfg->strip_tag1_en ? 1 : 0);
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 464                      vcfg->strip_tag2_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 466                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 468                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 469
 470         /*
 471          * In current version VF is not supported when PF is driven by DPDK
 472          * driver, the PF-related vf_id is 0, just need to configure parameters
 473          * for vport_id 0.
 474          */
 475         vport_id = 0;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_pf *pf = &hns->pf;
 507         struct hns3_hw *hw = &hns->hw;
 508         int ret;
 509
 510         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 511                 rxvlan_cfg.strip_tag1_en = false;
 512                 rxvlan_cfg.strip_tag2_en = enable;
 513         } else {
 514                 rxvlan_cfg.strip_tag1_en = enable;
 515                 rxvlan_cfg.strip_tag2_en = true;
 516         }
 517
 518         rxvlan_cfg.vlan1_vlan_prionly = false;
 519         rxvlan_cfg.vlan2_vlan_prionly = false;
 520         rxvlan_cfg.rx_vlan_offload_en = enable;
 521
 522         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 523         if (ret) {
 524                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 525                 return ret;
 526         }
 527
 528         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 535                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 536 {
 537         struct hns3_vlan_filter_ctrl_cmd *req;
 538         struct hns3_cmd_desc desc;
 539         int ret;
 540
 541         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 542
 543         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 544         req->vlan_type = vlan_type;
 545         req->vlan_fe = filter_en ? fe_type : 0;
 546         req->vf_id = vf_id;
 547
 548         ret = hns3_cmd_send(hw, &desc, 1);
 549         if (ret)
 550                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 551
 552         return ret;
 553 }
 554
 555 static int
 556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 557 {
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 562                                         HNS3_FILTER_FE_EGRESS, false, 0);
 563         if (ret) {
 564                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 570         if (ret)
 571                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 572
 573         return ret;
 574 }
 575
 576 static int
 577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 578 {
 579         struct hns3_adapter *hns = dev->data->dev_private;
 580         struct hns3_hw *hw = &hns->hw;
 581         struct rte_eth_rxmode *rxmode;
 582         unsigned int tmp_mask;
 583         bool enable;
 584         int ret = 0;
 585
 586         rte_spinlock_lock(&hw->lock);
 587         rxmode = &dev->data->dev_conf.rxmode;
 588         tmp_mask = (unsigned int)mask;
 589         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 590                 /* Enable or disable VLAN stripping */
 591                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 592                     true : false;
 593
 594                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 595                 if (ret) {
 596                         rte_spinlock_unlock(&hw->lock);
 597                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 598                         return ret;
 599                 }
 600         }
 601
 602         rte_spinlock_unlock(&hw->lock);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 609                              struct hns3_tx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_vport_vtag_tx_cfg_cmd *req;
 612         struct hns3_cmd_desc desc;
 613         struct hns3_hw *hw = &hns->hw;
 614         uint16_t vport_id;
 615         uint8_t bitmap;
 616         int ret;
 617
 618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 619
 620         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 621         req->def_vlan_tag1 = vcfg->default_tag1;
 622         req->def_vlan_tag2 = vcfg->default_tag2;
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 624                      vcfg->accept_tag1 ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 626                      vcfg->accept_untag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 628                      vcfg->accept_tag2 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 630                      vcfg->accept_untag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 632                      vcfg->insert_tag1_en ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 634                      vcfg->insert_tag2_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 636
 637         /*
 638          * In current version VF is not supported when PF is driven by DPDK
 639          * driver, the PF-related vf_id is 0, just need to configure parameters
 640          * for vport_id 0.
 641          */
 642         vport_id = 0;
 643         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 644         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 645         req->vf_bitmap[req->vf_offset] = bitmap;
 646
 647         ret = hns3_cmd_send(hw, &desc, 1);
 648         if (ret)
 649                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 656                      uint16_t pvid)
 657 {
 658         struct hns3_hw *hw = &hns->hw;
 659         struct hns3_tx_vtag_cfg txvlan_cfg;
 660         int ret;
 661
 662         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 663                 txvlan_cfg.accept_tag1 = true;
 664                 txvlan_cfg.insert_tag1_en = false;
 665                 txvlan_cfg.default_tag1 = 0;
 666         } else {
 667                 txvlan_cfg.accept_tag1 = false;
 668                 txvlan_cfg.insert_tag1_en = true;
 669                 txvlan_cfg.default_tag1 = pvid;
 670         }
 671
 672         txvlan_cfg.accept_untag1 = true;
 673         txvlan_cfg.accept_tag2 = true;
 674         txvlan_cfg.accept_untag2 = true;
 675         txvlan_cfg.insert_tag2_en = false;
 676         txvlan_cfg.default_tag2 = 0;
 677
 678         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 679         if (ret) {
 680                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 681                          ret);
 682                 return ret;
 683         }
 684
 685         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 686         return ret;
 687 }
 688
 689 static void
 690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 691 {
 692         struct hns3_pf *pf = &hns->pf;
 693
 694         pf->port_base_vlan_cfg.state = on ?
 695             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 696
 697         pf->port_base_vlan_cfg.pvid = pvid;
 698 }
 699
 700 static void
 701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 702 {
 703         struct hns3_user_vlan_table *vlan_entry;
 704         struct hns3_pf *pf = &hns->pf;
 705
 706         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 707                 if (vlan_entry->hd_tbl_status)
 708                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 709
 710                 vlan_entry->hd_tbl_status = false;
 711         }
 712
 713         if (is_del_list) {
 714                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 715                 while (vlan_entry) {
 716                         LIST_REMOVE(vlan_entry, next);
 717                         rte_free(vlan_entry);
 718                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 719                 }
 720         }
 721 }
 722
 723 static void
 724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 725 {
 726         struct hns3_user_vlan_table *vlan_entry;
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 730                 if (!vlan_entry->hd_tbl_status)
 731                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 732
 733                 vlan_entry->hd_tbl_status = true;
 734         }
 735 }
 736
 737 static void
 738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         struct hns3_pf *pf = &hns->pf;
 742         int ret;
 743
 744         hns3_rm_all_vlan_table(hns, true);
 745         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 746                 ret = hns3_set_port_vlan_filter(hns,
 747                                                 pf->port_base_vlan_cfg.pvid, 0);
 748                 if (ret) {
 749                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 750                                  ret);
 751                         return;
 752                 }
 753         }
 754 }
 755
 756 static int
 757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 758                                 uint16_t port_base_vlan_state,
 759                                 uint16_t new_pvid, uint16_t old_pvid)
 760 {
 761         struct hns3_pf *pf = &hns->pf;
 762         struct hns3_hw *hw = &hns->hw;
 763         int ret = 0;
 764
 765         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 766                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 767                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 768                         if (ret) {
 769                                 hns3_err(hw,
 770                                          "Failed to clear clear old pvid filter, ret =%d",
 771                                          ret);
 772                                 return ret;
 773                         }
 774                 }
 775
 776                 hns3_rm_all_vlan_table(hns, false);
 777                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 778         }
 779
 780         if (new_pvid != 0) {
 781                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 782                 if (ret) {
 783                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 784                                  ret);
 785                         return ret;
 786                 }
 787         }
 788
 789         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 790                 hns3_add_all_vlan_table(hns);
 791
 792         return ret;
 793 }
 794
 795 static int
 796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 797 {
 798         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 799         struct hns3_hw *hw = &hns->hw;
 800         bool rx_strip_en;
 801         int ret;
 802
 803         rx_strip_en = on ? true : false;
 804         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 805         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 806         rx_vlan_cfg.vlan1_vlan_prionly = false;
 807         rx_vlan_cfg.vlan2_vlan_prionly = false;
 808         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 809
 810         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 811         if (ret) {
 812                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 813                 return ret;
 814         }
 815
 816         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 817         return ret;
 818 }
 819
 820 static int
 821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 822 {
 823         struct hns3_pf *pf = &hns->pf;
 824         struct hns3_hw *hw = &hns->hw;
 825         uint16_t port_base_vlan_state;
 826         uint16_t old_pvid;
 827         int ret;
 828
 829         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 830                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 831                         hns3_warn(hw, "Invalid operation! As current pvid set "
 832                                   "is %u, disable pvid %u is invalid",
 833                                   pf->port_base_vlan_cfg.pvid, pvid);
 834                 return 0;
 835         }
 836
 837         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 838                                     HNS3_PORT_BASE_VLAN_DISABLE;
 839         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 840         if (ret) {
 841                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_en_rx_strip_all(hns, on);
 846         if (ret) {
 847                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         if (pvid == HNS3_INVLID_PVID)
 852                 goto out;
 853         old_pvid = pf->port_base_vlan_cfg.pvid;
 854         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 855                                               old_pvid);
 856         if (ret) {
 857                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 858                          ret);
 859                 return ret;
 860         }
 861
 862 out:
 863         hns3_store_port_base_vlan_info(hns, pvid, on);
 864         return ret;
 865 }
 866
 867 static int
 868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 869 {
 870         struct hns3_adapter *hns = dev->data->dev_private;
 871         struct hns3_hw *hw = &hns->hw;
 872         int ret;
 873
 874         rte_spinlock_lock(&hw->lock);
 875         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 876         rte_spinlock_unlock(&hw->lock);
 877         return ret;
 878 }
 879
 880 static void
 881 init_port_base_vlan_info(struct hns3_hw *hw)
 882 {
 883         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 884         struct hns3_pf *pf = &hns->pf;
 885
 886         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 887         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 888 }
 889
 890 static int
 891 hns3_default_vlan_config(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 897         if (ret)
 898                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 899         return ret;
 900 }
 901
 902 static int
 903 hns3_init_vlan_config(struct hns3_adapter *hns)
 904 {
 905         struct hns3_hw *hw = &hns->hw;
 906         int ret;
 907
 908         /*
 909          * This function can be called in the initialization and reset process,
 910          * when in reset process, it means that hardware had been reseted
 911          * successfully and we need to restore the hardware configuration to
 912          * ensure that the hardware configuration remains unchanged before and
 913          * after reset.
 914          */
 915         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 916                 init_port_base_vlan_info(hw);
 917
 918         ret = hns3_enable_vlan_filter(hns, true);
 919         if (ret) {
 920                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 921                 return ret;
 922         }
 923
 924         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 925                                        RTE_ETHER_TYPE_VLAN);
 926         if (ret) {
 927                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 928                 return ret;
 929         }
 930
 931         /*
 932          * When in the reinit dev stage of the reset process, the following
 933          * vlan-related configurations may differ from those at initialization,
 934          * we will restore configurations to hardware in hns3_restore_vlan_table
 935          * and hns3_restore_vlan_conf later.
 936          */
 937         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 938                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 939                 if (ret) {
 940                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 941                         return ret;
 942                 }
 943
 944                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 945                 if (ret) {
 946                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 947                                  ret);
 948                         return ret;
 949                 }
 950         }
 951
 952         return hns3_default_vlan_config(hns);
 953 }
 954
 955 static int
 956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 957 {
 958         struct hns3_pf *pf = &hns->pf;
 959         struct hns3_hw *hw = &hns->hw;
 960         int ret;
 961
 962         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 963         if (ret) {
 964                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 969         if (ret)
 970                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 977 {
 978         struct hns3_adapter *hns = dev->data->dev_private;
 979         struct rte_eth_dev_data *data = dev->data;
 980         struct rte_eth_txmode *txmode;
 981         struct hns3_hw *hw = &hns->hw;
 982         int ret;
 983
 984         txmode = &data->dev_conf.txmode;
 985         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 986                 hns3_warn(hw,
 987                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 988                           "configuration is not supported! Ignore these two "
 989                           "parameters: hw_vlan_reject_tagged(%d), "
 990                           "hw_vlan_reject_untagged(%d)",
 991                           txmode->hw_vlan_reject_tagged,
 992                           txmode->hw_vlan_reject_untagged);
 993
 994         /* Apply vlan offload setting */
 995         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 996         if (ret) {
 997                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 998                 return ret;
 999         }
1000
1001         /* Apply pvid setting */
1002         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003                                  txmode->hw_vlan_insert_pvid);
1004         if (ret)
1005                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1006                          txmode->pvid, ret);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013                 unsigned int tso_mss_max)
1014 {
1015         struct hns3_cfg_tso_status_cmd *req;
1016         struct hns3_cmd_desc desc;
1017         uint16_t tso_mss;
1018
1019         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1020
1021         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1022
1023         tso_mss = 0;
1024         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1025                        tso_mss_min);
1026         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1027
1028         tso_mss = 0;
1029         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1030                        tso_mss_max);
1031         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1032
1033         return hns3_cmd_send(hw, &desc, 1);
1034 }
1035
1036 int
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1038 {
1039         struct hns3_cfg_gro_status_cmd *req;
1040         struct hns3_cmd_desc desc;
1041         int ret;
1042
1043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1045
1046         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1047
1048         ret = hns3_cmd_send(hw, &desc, 1);
1049         if (ret)
1050                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057                    uint16_t *allocated_size, bool is_alloc)
1058 {
1059         struct hns3_umv_spc_alc_cmd *req;
1060         struct hns3_cmd_desc desc;
1061         int ret;
1062
1063         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066         req->space_size = rte_cpu_to_le_32(space_size);
1067
1068         ret = hns3_cmd_send(hw, &desc, 1);
1069         if (ret) {
1070                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071                              is_alloc ? "allocate" : "free", ret);
1072                 return ret;
1073         }
1074
1075         if (is_alloc && allocated_size)
1076                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_init_umv_space(struct hns3_hw *hw)
1083 {
1084         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085         struct hns3_pf *pf = &hns->pf;
1086         uint16_t allocated_size = 0;
1087         int ret;
1088
1089         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1090                                  true);
1091         if (ret)
1092                 return ret;
1093
1094         if (allocated_size < pf->wanted_umv_size)
1095                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096                              pf->wanted_umv_size, allocated_size);
1097
1098         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099                                                 pf->wanted_umv_size;
1100         pf->used_umv_size = 0;
1101         return 0;
1102 }
1103
1104 static int
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1106 {
1107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108         struct hns3_pf *pf = &hns->pf;
1109         int ret;
1110
1111         if (pf->max_umv_size == 0)
1112                 return 0;
1113
1114         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1115         if (ret)
1116                 return ret;
1117
1118         pf->max_umv_size = 0;
1119
1120         return 0;
1121 }
1122
1123 static bool
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1125 {
1126         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127         struct hns3_pf *pf = &hns->pf;
1128         bool is_full;
1129
1130         is_full = (pf->used_umv_size >= pf->max_umv_size);
1131
1132         return is_full;
1133 }
1134
1135 static void
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1137 {
1138         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139         struct hns3_pf *pf = &hns->pf;
1140
1141         if (is_free) {
1142                 if (pf->used_umv_size > 0)
1143                         pf->used_umv_size--;
1144         } else
1145                 pf->used_umv_size++;
1146 }
1147
1148 static void
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150                       const uint8_t *addr, bool is_mc)
1151 {
1152         const unsigned char *mac_addr = addr;
1153         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154                             ((uint32_t)mac_addr[2] << 16) |
1155                             ((uint32_t)mac_addr[1] << 8) |
1156                             (uint32_t)mac_addr[0];
1157         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1158
1159         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1160         if (is_mc) {
1161                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1164         }
1165
1166         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1168 }
1169
1170 static int
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1172                              uint8_t resp_code,
1173                              enum hns3_mac_vlan_tbl_opcode op)
1174 {
1175         if (cmdq_resp) {
1176                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1177                          cmdq_resp);
1178                 return -EIO;
1179         }
1180
1181         if (op == HNS3_MAC_VLAN_ADD) {
1182                 if (resp_code == 0 || resp_code == 1) {
1183                         return 0;
1184                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185                         hns3_err(hw, "add mac addr failed for uc_overflow");
1186                         return -ENOSPC;
1187                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188                         hns3_err(hw, "add mac addr failed for mc_overflow");
1189                         return -ENOSPC;
1190                 }
1191
1192                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1193                          resp_code);
1194                 return -EIO;
1195         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196                 if (resp_code == 0) {
1197                         return 0;
1198                 } else if (resp_code == 1) {
1199                         hns3_dbg(hw, "remove mac addr failed for miss");
1200                         return -ENOENT;
1201                 }
1202
1203                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_LKUP) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "lookup mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         }
1218
1219         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1220                  op);
1221
1222         return -EINVAL;
1223 }
1224
1225 static int
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1228                          struct hns3_cmd_desc *desc, bool is_mc)
1229 {
1230         uint8_t resp_code;
1231         uint16_t retval;
1232         int ret;
1233
1234         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1235         if (is_mc) {
1236                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237                 memcpy(desc[0].data, req,
1238                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1240                                           true);
1241                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1243                                           true);
1244                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1245         } else {
1246                 memcpy(desc[0].data, req,
1247                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248                 ret = hns3_cmd_send(hw, desc, 1);
1249         }
1250         if (ret) {
1251                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1252                          ret);
1253                 return ret;
1254         }
1255         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256         retval = rte_le_to_cpu_16(desc[0].retval);
1257
1258         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259                                             HNS3_MAC_VLAN_LKUP);
1260 }
1261
1262 static int
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1265                       struct hns3_cmd_desc *mc_desc)
1266 {
1267         uint8_t resp_code;
1268         uint16_t retval;
1269         int cfg_status;
1270         int ret;
1271
1272         if (mc_desc == NULL) {
1273                 struct hns3_cmd_desc desc;
1274
1275                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276                 memcpy(desc.data, req,
1277                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278                 ret = hns3_cmd_send(hw, &desc, 1);
1279                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280                 retval = rte_le_to_cpu_16(desc.retval);
1281
1282                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1283                                                           HNS3_MAC_VLAN_ADD);
1284         } else {
1285                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291                 memcpy(mc_desc[0].data, req,
1292                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293                 mc_desc[0].retval = 0;
1294                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1297
1298                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1299                                                           HNS3_MAC_VLAN_ADD);
1300         }
1301
1302         if (ret) {
1303                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1304                 return ret;
1305         }
1306
1307         return cfg_status;
1308 }
1309
1310 static int
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1313 {
1314         struct hns3_cmd_desc desc;
1315         uint8_t resp_code;
1316         uint16_t retval;
1317         int ret;
1318
1319         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1320
1321         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322
1323         ret = hns3_cmd_send(hw, &desc, 1);
1324         if (ret) {
1325                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1326                 return ret;
1327         }
1328         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329         retval = rte_le_to_cpu_16(desc.retval);
1330
1331         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332                                             HNS3_MAC_VLAN_REMOVE);
1333 }
1334
1335 static int
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1337 {
1338         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339         struct hns3_mac_vlan_tbl_entry_cmd req;
1340         struct hns3_pf *pf = &hns->pf;
1341         struct hns3_cmd_desc desc;
1342         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343         uint16_t egress_port = 0;
1344         uint8_t vf_id;
1345         int ret;
1346
1347         /* check if mac addr is valid */
1348         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1350                                       mac_addr);
1351                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1352                          mac_str);
1353                 return -EINVAL;
1354         }
1355
1356         memset(&req, 0, sizeof(req));
1357
1358         /*
1359          * In current version VF is not supported when PF is driven by DPDK
1360          * driver, the PF-related vf_id is 0, just need to configure parameters
1361          * for vf_id 0.
1362          */
1363         vf_id = 0;
1364         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365                        HNS3_MAC_EPORT_VFID_S, vf_id);
1366
1367         req.egress_port = rte_cpu_to_le_16(egress_port);
1368
1369         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1370
1371         /*
1372          * Lookup the mac address in the mac_vlan table, and add
1373          * it if the entry is inexistent. Repeated unicast entry
1374          * is not allowed in the mac vlan table.
1375          */
1376         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377         if (ret == -ENOENT) {
1378                 if (!hns3_is_umv_space_full(hw)) {
1379                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1380                         if (!ret)
1381                                 hns3_update_umv_space(hw, false);
1382                         return ret;
1383                 }
1384
1385                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1386
1387                 return -ENOSPC;
1388         }
1389
1390         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1391
1392         /* check if we just hit the duplicate */
1393         if (ret == 0) {
1394                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1395                 return 0;
1396         }
1397
1398         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1399                  mac_str);
1400
1401         return ret;
1402 }
1403
1404 static int
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1407 {
1408         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1410         int ret;
1411
1412         rte_spinlock_lock(&hw->lock);
1413         ret = hns3_add_uc_addr_common(hw, mac_addr);
1414         if (ret) {
1415                 rte_spinlock_unlock(&hw->lock);
1416                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1417                                       mac_addr);
1418                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1419                 return ret;
1420         }
1421
1422         if (idx == 0)
1423                 hw->mac.default_addr_setted = true;
1424         rte_spinlock_unlock(&hw->lock);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1431 {
1432         struct hns3_mac_vlan_tbl_entry_cmd req;
1433         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1434         int ret;
1435
1436         /* check if mac addr is valid */
1437         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1441                          mac_str);
1442                 return -EINVAL;
1443         }
1444
1445         memset(&req, 0, sizeof(req));
1446         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1450                 return 0;
1451         else if (ret == 0)
1452                 hns3_update_umv_space(hw, true);
1453
1454         return ret;
1455 }
1456
1457 static void
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1459 {
1460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         /* index will be checked by upper level rte interface */
1462         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464         int ret;
1465
1466         rte_spinlock_lock(&hw->lock);
1467         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1468         if (ret) {
1469                 rte_spinlock_unlock(&hw->lock);
1470                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1471                                       mac_addr);
1472                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1473                 return;
1474         }
1475
1476         rte_spinlock_unlock(&hw->lock);
1477 }
1478
1479 static int
1480 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1481                           struct rte_ether_addr *mac_addr)
1482 {
1483         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         struct rte_ether_addr *oaddr;
1485         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1486         bool default_addr_setted;
1487         bool rm_succes = false;
1488         int ret, ret_val;
1489
1490         /* check if mac addr is valid */
1491         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1492                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1493                                       mac_addr);
1494                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1495                          mac_str);
1496                 return -EINVAL;
1497         }
1498
1499         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1500         default_addr_setted = hw->mac.default_addr_setted;
1501         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1502                 return 0;
1503
1504         rte_spinlock_lock(&hw->lock);
1505         if (default_addr_setted) {
1506                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1507                 if (ret) {
1508                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1509                                               oaddr);
1510                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1511                                   mac_str, ret);
1512                         rm_succes = false;
1513                 } else
1514                         rm_succes = true;
1515         }
1516
1517         ret = hns3_add_uc_addr_common(hw, mac_addr);
1518         if (ret) {
1519                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1520                                       mac_addr);
1521                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1522                 goto err_add_uc_addr;
1523         }
1524
1525         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1526         if (ret) {
1527                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1528                 goto err_pause_addr_cfg;
1529         }
1530
1531         rte_ether_addr_copy(mac_addr,
1532                             (struct rte_ether_addr *)hw->mac.mac_addr);
1533         hw->mac.default_addr_setted = true;
1534         rte_spinlock_unlock(&hw->lock);
1535
1536         return 0;
1537
1538 err_pause_addr_cfg:
1539         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1540         if (ret_val) {
1541                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1542                                       mac_addr);
1543                 hns3_warn(hw,
1544                           "Failed to roll back to del setted mac addr(%s): %d",
1545                           mac_str, ret_val);
1546         }
1547
1548 err_add_uc_addr:
1549         if (rm_succes) {
1550                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1551                 if (ret_val) {
1552                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1553                                               oaddr);
1554                         hns3_warn(hw,
1555                                   "Failed to restore old uc mac addr(%s): %d",
1556                                   mac_str, ret_val);
1557                         hw->mac.default_addr_setted = false;
1558                 }
1559         }
1560         rte_spinlock_unlock(&hw->lock);
1561
1562         return ret;
1563 }
1564
1565 static int
1566 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1567 {
1568         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1569         struct hns3_hw *hw = &hns->hw;
1570         struct rte_ether_addr *addr;
1571         int err = 0;
1572         int ret;
1573         int i;
1574
1575         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1576                 addr = &hw->data->mac_addrs[i];
1577                 if (!rte_is_valid_assigned_ether_addr(addr))
1578                         continue;
1579                 if (del)
1580                         ret = hns3_remove_uc_addr_common(hw, addr);
1581                 else
1582                         ret = hns3_add_uc_addr_common(hw, addr);
1583                 if (ret) {
1584                         err = ret;
1585                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1586                                               addr);
1587                         hns3_dbg(hw,
1588                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1589                                  del ? "remove" : "restore", mac_str, ret, i);
1590                 }
1591         }
1592         return err;
1593 }
1594
1595 static void
1596 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1597 {
1598 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1599         uint8_t word_num;
1600         uint8_t bit_num;
1601
1602         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1603                 word_num = vfid / 32;
1604                 bit_num = vfid % 32;
1605                 if (clr)
1606                         desc[1].data[word_num] &=
1607                             rte_cpu_to_le_32(~(1UL << bit_num));
1608                 else
1609                         desc[1].data[word_num] |=
1610                             rte_cpu_to_le_32(1UL << bit_num);
1611         } else {
1612                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1613                 bit_num = vfid % 32;
1614                 if (clr)
1615                         desc[2].data[word_num] &=
1616                             rte_cpu_to_le_32(~(1UL << bit_num));
1617                 else
1618                         desc[2].data[word_num] |=
1619                             rte_cpu_to_le_32(1UL << bit_num);
1620         }
1621 }
1622
1623 static int
1624 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1625 {
1626         struct hns3_mac_vlan_tbl_entry_cmd req;
1627         struct hns3_cmd_desc desc[3];
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         uint8_t vf_id;
1630         int ret;
1631
1632         /* Check if mac addr is valid */
1633         if (!rte_is_multicast_ether_addr(mac_addr)) {
1634                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1635                                       mac_addr);
1636                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1637                          mac_str);
1638                 return -EINVAL;
1639         }
1640
1641         memset(&req, 0, sizeof(req));
1642         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1643         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1644         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1645         if (ret) {
1646                 /* This mac addr do not exist, add new entry for it */
1647                 memset(desc[0].data, 0, sizeof(desc[0].data));
1648                 memset(desc[1].data, 0, sizeof(desc[0].data));
1649                 memset(desc[2].data, 0, sizeof(desc[0].data));
1650         }
1651
1652         /*
1653          * In current version VF is not supported when PF is driven by DPDK
1654          * driver, the PF-related vf_id is 0, just need to configure parameters
1655          * for vf_id 0.
1656          */
1657         vf_id = 0;
1658         hns3_update_desc_vfid(desc, vf_id, false);
1659         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1660         if (ret) {
1661                 if (ret == -ENOSPC)
1662                         hns3_err(hw, "mc mac vlan table is full");
1663                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1664                                       mac_addr);
1665                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1666         }
1667
1668         return ret;
1669 }
1670
1671 static int
1672 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1673 {
1674         struct hns3_mac_vlan_tbl_entry_cmd req;
1675         struct hns3_cmd_desc desc[3];
1676         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1677         uint8_t vf_id;
1678         int ret;
1679
1680         /* Check if mac addr is valid */
1681         if (!rte_is_multicast_ether_addr(mac_addr)) {
1682                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1683                                       mac_addr);
1684                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1685                          mac_str);
1686                 return -EINVAL;
1687         }
1688
1689         memset(&req, 0, sizeof(req));
1690         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1691         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1692         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1693         if (ret == 0) {
1694                 /*
1695                  * This mac addr exist, remove this handle's VFID for it.
1696                  * In current version VF is not supported when PF is driven by
1697                  * DPDK driver, the PF-related vf_id is 0, just need to
1698                  * configure parameters for vf_id 0.
1699                  */
1700                 vf_id = 0;
1701                 hns3_update_desc_vfid(desc, vf_id, true);
1702
1703                 /* All the vfid is zero, so need to delete this entry */
1704                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1705         } else if (ret == -ENOENT) {
1706                 /* This mac addr doesn't exist. */
1707                 return 0;
1708         }
1709
1710         if (ret) {
1711                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1714         }
1715
1716         return ret;
1717 }
1718
1719 static int
1720 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1721                            struct rte_ether_addr *mc_addr_set,
1722                            uint32_t nb_mc_addr)
1723 {
1724         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1725         struct rte_ether_addr *addr;
1726         uint32_t i;
1727         uint32_t j;
1728
1729         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1730                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1731                          "invalid. valid range: 0~%d",
1732                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1733                 return -EINVAL;
1734         }
1735
1736         /* Check if input mac addresses are valid */
1737         for (i = 0; i < nb_mc_addr; i++) {
1738                 addr = &mc_addr_set[i];
1739                 if (!rte_is_multicast_ether_addr(addr)) {
1740                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1741                                               addr);
1742                         hns3_err(hw,
1743                                  "Failed to set mc mac addr, addr(%s) invalid.",
1744                                  mac_str);
1745                         return -EINVAL;
1746                 }
1747
1748                 /* Check if there are duplicate addresses */
1749                 for (j = i + 1; j < nb_mc_addr; j++) {
1750                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1751                                 rte_ether_format_addr(mac_str,
1752                                                       RTE_ETHER_ADDR_FMT_SIZE,
1753                                                       addr);
1754                                 hns3_err(hw, "Failed to set mc mac addr, "
1755                                          "addrs invalid. two same addrs(%s).",
1756                                          mac_str);
1757                                 return -EINVAL;
1758                         }
1759                 }
1760         }
1761
1762         return 0;
1763 }
1764
1765 static void
1766 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1767                            struct rte_ether_addr *mc_addr_set,
1768                            int mc_addr_num,
1769                            struct rte_ether_addr *reserved_addr_list,
1770                            int *reserved_addr_num,
1771                            struct rte_ether_addr *add_addr_list,
1772                            int *add_addr_num,
1773                            struct rte_ether_addr *rm_addr_list,
1774                            int *rm_addr_num)
1775 {
1776         struct rte_ether_addr *addr;
1777         int current_addr_num;
1778         int reserved_num = 0;
1779         int add_num = 0;
1780         int rm_num = 0;
1781         int num;
1782         int i;
1783         int j;
1784         bool same_addr;
1785
1786         /* Calculate the mc mac address list that should be removed */
1787         current_addr_num = hw->mc_addrs_num;
1788         for (i = 0; i < current_addr_num; i++) {
1789                 addr = &hw->mc_addrs[i];
1790                 same_addr = false;
1791                 for (j = 0; j < mc_addr_num; j++) {
1792                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1793                                 same_addr = true;
1794                                 break;
1795                         }
1796                 }
1797
1798                 if (!same_addr) {
1799                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1800                         rm_num++;
1801                 } else {
1802                         rte_ether_addr_copy(addr,
1803                                             &reserved_addr_list[reserved_num]);
1804                         reserved_num++;
1805                 }
1806         }
1807
1808         /* Calculate the mc mac address list that should be added */
1809         for (i = 0; i < mc_addr_num; i++) {
1810                 addr = &mc_addr_set[i];
1811                 same_addr = false;
1812                 for (j = 0; j < current_addr_num; j++) {
1813                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1814                                 same_addr = true;
1815                                 break;
1816                         }
1817                 }
1818
1819                 if (!same_addr) {
1820                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1821                         add_num++;
1822                 }
1823         }
1824
1825         /* Reorder the mc mac address list maintained by driver */
1826         for (i = 0; i < reserved_num; i++)
1827                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1828
1829         for (i = 0; i < rm_num; i++) {
1830                 num = reserved_num + i;
1831                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1832         }
1833
1834         *reserved_addr_num = reserved_num;
1835         *add_addr_num = add_num;
1836         *rm_addr_num = rm_num;
1837 }
1838
1839 static int
1840 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1841                           struct rte_ether_addr *mc_addr_set,
1842                           uint32_t nb_mc_addr)
1843 {
1844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1846         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1847         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1848         struct rte_ether_addr *addr;
1849         int reserved_addr_num;
1850         int add_addr_num;
1851         int rm_addr_num;
1852         int mc_addr_num;
1853         int num;
1854         int ret;
1855         int i;
1856
1857         /* Check if input parameters are valid */
1858         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1859         if (ret)
1860                 return ret;
1861
1862         rte_spinlock_lock(&hw->lock);
1863
1864         /*
1865          * Calculate the mc mac address lists those should be removed and be
1866          * added, Reorder the mc mac address list maintained by driver.
1867          */
1868         mc_addr_num = (int)nb_mc_addr;
1869         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1870                                    reserved_addr_list, &reserved_addr_num,
1871                                    add_addr_list, &add_addr_num,
1872                                    rm_addr_list, &rm_addr_num);
1873
1874         /* Remove mc mac addresses */
1875         for (i = 0; i < rm_addr_num; i++) {
1876                 num = rm_addr_num - i - 1;
1877                 addr = &rm_addr_list[num];
1878                 ret = hns3_remove_mc_addr(hw, addr);
1879                 if (ret) {
1880                         rte_spinlock_unlock(&hw->lock);
1881                         return ret;
1882                 }
1883                 hw->mc_addrs_num--;
1884         }
1885
1886         /* Add mc mac addresses */
1887         for (i = 0; i < add_addr_num; i++) {
1888                 addr = &add_addr_list[i];
1889                 ret = hns3_add_mc_addr(hw, addr);
1890                 if (ret) {
1891                         rte_spinlock_unlock(&hw->lock);
1892                         return ret;
1893                 }
1894
1895                 num = reserved_addr_num + i;
1896                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1897                 hw->mc_addrs_num++;
1898         }
1899         rte_spinlock_unlock(&hw->lock);
1900
1901         return 0;
1902 }
1903
1904 static int
1905 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1906 {
1907         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1908         struct hns3_hw *hw = &hns->hw;
1909         struct rte_ether_addr *addr;
1910         int err = 0;
1911         int ret;
1912         int i;
1913
1914         for (i = 0; i < hw->mc_addrs_num; i++) {
1915                 addr = &hw->mc_addrs[i];
1916                 if (!rte_is_multicast_ether_addr(addr))
1917                         continue;
1918                 if (del)
1919                         ret = hns3_remove_mc_addr(hw, addr);
1920                 else
1921                         ret = hns3_add_mc_addr(hw, addr);
1922                 if (ret) {
1923                         err = ret;
1924                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1925                                               addr);
1926                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1927                                  del ? "Remove" : "Restore", mac_str);
1928                 }
1929         }
1930         return err;
1931 }
1932
1933 static int
1934 hns3_check_mq_mode(struct rte_eth_dev *dev)
1935 {
1936         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1937         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1938         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1941         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1942         uint8_t num_tc;
1943         int max_tc = 0;
1944         int i;
1945
1946         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1947         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1948
1949         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1950                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1951                          "rx_mq_mode = %d", rx_mq_mode);
1952                 return -EINVAL;
1953         }
1954
1955         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1956             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1957                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1958                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1959                          rx_mq_mode, tx_mq_mode);
1960                 return -EINVAL;
1961         }
1962
1963         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1964                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1965                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1966                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1967                         return -EINVAL;
1968                 }
1969
1970                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1971                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1972                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1973                                  "nb_tcs(%d) != %d or %d in rx direction.",
1974                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1975                         return -EINVAL;
1976                 }
1977
1978                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1979                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1980                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1981                         return -EINVAL;
1982                 }
1983
1984                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1985                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1986                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1987                                          "is not equal to one in tx direction.",
1988                                          i, dcb_rx_conf->dcb_tc[i]);
1989                                 return -EINVAL;
1990                         }
1991                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1992                                 max_tc = dcb_rx_conf->dcb_tc[i];
1993                 }
1994
1995                 num_tc = max_tc + 1;
1996                 if (num_tc > dcb_rx_conf->nb_tcs) {
1997                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1998                                  num_tc, dcb_rx_conf->nb_tcs);
1999                         return -EINVAL;
2000                 }
2001         }
2002
2003         return 0;
2004 }
2005
2006 static int
2007 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2008 {
2009         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010
2011         if (!hns3_dev_dcb_supported(hw)) {
2012                 hns3_err(hw, "this port does not support dcb configurations.");
2013                 return -EOPNOTSUPP;
2014         }
2015
2016         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2017                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2018                 return -EOPNOTSUPP;
2019         }
2020
2021         /* Check multiple queue mode */
2022         return hns3_check_mq_mode(dev);
2023 }
2024
2025 static int
2026 hns3_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
2027                            bool mmap, uint16_t queue_id)
2028 {
2029         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct hns3_cmd_desc desc;
2031         struct hns3_ctrl_vector_chain_cmd *req =
2032                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2033         enum hns3_cmd_status status;
2034         enum hns3_opcode_type op;
2035         uint16_t tqp_type_and_id = 0;
2036
2037         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2038         hns3_cmd_setup_basic_desc(&desc, op, false);
2039         req->int_vector_id = vector_id;
2040
2041         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2042                        HNS3_RING_TYPE_RX);
2043         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2044         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2045                        HNS3_RING_GL_RX);
2046         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2047
2048         req->int_cause_num = 1;
2049         status = hns3_cmd_send(hw, &desc, 1);
2050         if (status) {
2051                 hns3_err(hw, "Map TQP %d fail, vector_id is %d, status is %d.",
2052                          queue_id, vector_id, status);
2053                 return -EIO;
2054         }
2055
2056         return 0;
2057 }
2058
2059 static int
2060 hns3_dev_configure(struct rte_eth_dev *dev)
2061 {
2062         struct hns3_adapter *hns = dev->data->dev_private;
2063         struct rte_eth_conf *conf = &dev->data->dev_conf;
2064         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2065         struct hns3_hw *hw = &hns->hw;
2066         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2067         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2068         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2069         struct rte_eth_rss_conf rss_conf;
2070         uint16_t mtu;
2071         int ret;
2072
2073         /*
2074          * Hardware does not support individually enable/disable/reset the Tx or
2075          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2076          * and Rx queues at the same time. When the numbers of Tx queues
2077          * allocated by upper applications are not equal to the numbers of Rx
2078          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2079          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2080          * these fake queues are imperceptible, and can not be used by upper
2081          * applications.
2082          */
2083         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2084         if (ret) {
2085                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2086                 return ret;
2087         }
2088
2089         hw->adapter_state = HNS3_NIC_CONFIGURING;
2090         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2091                 hns3_err(hw, "setting link speed/duplex not supported");
2092                 ret = -EINVAL;
2093                 goto cfg_err;
2094         }
2095
2096         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2097                 ret = hns3_check_dcb_cfg(dev);
2098                 if (ret)
2099                         goto cfg_err;
2100         }
2101
2102         /* When RSS is not configured, redirect the packet queue 0 */
2103         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2104                 rss_conf = conf->rx_adv_conf.rss_conf;
2105                 if (rss_conf.rss_key == NULL) {
2106                         rss_conf.rss_key = rss_cfg->key;
2107                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2108                 }
2109
2110                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2111                 if (ret)
2112                         goto cfg_err;
2113         }
2114
2115         /*
2116          * If jumbo frames are enabled, MTU needs to be refreshed
2117          * according to the maximum RX packet length.
2118          */
2119         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2120                 /*
2121                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2122                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2123                  * can safely assign to "uint16_t" type variable.
2124                  */
2125                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2126                 ret = hns3_dev_mtu_set(dev, mtu);
2127                 if (ret)
2128                         goto cfg_err;
2129                 dev->data->mtu = mtu;
2130         }
2131
2132         ret = hns3_dev_configure_vlan(dev);
2133         if (ret)
2134                 goto cfg_err;
2135
2136         hw->adapter_state = HNS3_NIC_CONFIGURED;
2137
2138         return 0;
2139
2140 cfg_err:
2141         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2142         hw->adapter_state = HNS3_NIC_INITIALIZED;
2143
2144         return ret;
2145 }
2146
2147 static int
2148 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2149 {
2150         struct hns3_config_max_frm_size_cmd *req;
2151         struct hns3_cmd_desc desc;
2152
2153         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2154
2155         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2156         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2157         req->min_frm_size = RTE_ETHER_MIN_LEN;
2158
2159         return hns3_cmd_send(hw, &desc, 1);
2160 }
2161
2162 static int
2163 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2164 {
2165         int ret;
2166
2167         ret = hns3_set_mac_mtu(hw, mps);
2168         if (ret) {
2169                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2170                 return ret;
2171         }
2172
2173         ret = hns3_buffer_alloc(hw);
2174         if (ret) {
2175                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2176                 return ret;
2177         }
2178
2179         return 0;
2180 }
2181
2182 static int
2183 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2184 {
2185         struct hns3_adapter *hns = dev->data->dev_private;
2186         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2187         struct hns3_hw *hw = &hns->hw;
2188         bool is_jumbo_frame;
2189         int ret;
2190
2191         if (dev->data->dev_started) {
2192                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2193                          "before configuration", dev->data->port_id);
2194                 return -EBUSY;
2195         }
2196
2197         rte_spinlock_lock(&hw->lock);
2198         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2199         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2200
2201         /*
2202          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2203          * assign to "uint16_t" type variable.
2204          */
2205         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2206         if (ret) {
2207                 rte_spinlock_unlock(&hw->lock);
2208                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2209                          dev->data->port_id, mtu, ret);
2210                 return ret;
2211         }
2212         hns->pf.mps = (uint16_t)frame_size;
2213         if (is_jumbo_frame)
2214                 dev->data->dev_conf.rxmode.offloads |=
2215                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2216         else
2217                 dev->data->dev_conf.rxmode.offloads &=
2218                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2219         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2220         rte_spinlock_unlock(&hw->lock);
2221
2222         return 0;
2223 }
2224
2225 static int
2226 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2227 {
2228         struct hns3_adapter *hns = eth_dev->data->dev_private;
2229         struct hns3_hw *hw = &hns->hw;
2230
2231         info->max_rx_queues = hw->tqps_num;
2232         info->max_tx_queues = hw->tqps_num;
2233         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2234         info->min_rx_bufsize = hw->rx_buf_len;
2235         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2236         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2237         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2238                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2239                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2240                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2241                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2242                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2243                                  DEV_RX_OFFLOAD_KEEP_CRC |
2244                                  DEV_RX_OFFLOAD_SCATTER |
2245                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2246                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2247                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2248                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2249                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2250         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2251         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2252                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2253                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2254                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2255                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2256                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2257                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2258                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2259                                  info->tx_queue_offload_capa);
2260
2261         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2262                 .nb_max = HNS3_MAX_RING_DESC,
2263                 .nb_min = HNS3_MIN_RING_DESC,
2264                 .nb_align = HNS3_ALIGN_RING_DESC,
2265         };
2266
2267         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2268                 .nb_max = HNS3_MAX_RING_DESC,
2269                 .nb_min = HNS3_MIN_RING_DESC,
2270                 .nb_align = HNS3_ALIGN_RING_DESC,
2271         };
2272
2273         info->vmdq_queue_num = 0;
2274
2275         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2276         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2277         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2278
2279         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2280         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2281         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2282         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2283         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2284         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2285
2286         return 0;
2287 }
2288
2289 static int
2290 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2291                     size_t fw_size)
2292 {
2293         struct hns3_adapter *hns = eth_dev->data->dev_private;
2294         struct hns3_hw *hw = &hns->hw;
2295         int ret;
2296
2297         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2298         ret += 1; /* add the size of '\0' */
2299         if (fw_size < (uint32_t)ret)
2300                 return ret;
2301         else
2302                 return 0;
2303 }
2304
2305 static int
2306 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2307                      __rte_unused int wait_to_complete)
2308 {
2309         struct hns3_adapter *hns = eth_dev->data->dev_private;
2310         struct hns3_hw *hw = &hns->hw;
2311         struct hns3_mac *mac = &hw->mac;
2312         struct rte_eth_link new_link;
2313
2314         if (!hns3_is_reset_pending(hns)) {
2315                 hns3_update_speed_duplex(eth_dev);
2316                 hns3_update_link_status(hw);
2317         }
2318
2319         memset(&new_link, 0, sizeof(new_link));
2320         switch (mac->link_speed) {
2321         case ETH_SPEED_NUM_10M:
2322         case ETH_SPEED_NUM_100M:
2323         case ETH_SPEED_NUM_1G:
2324         case ETH_SPEED_NUM_10G:
2325         case ETH_SPEED_NUM_25G:
2326         case ETH_SPEED_NUM_40G:
2327         case ETH_SPEED_NUM_50G:
2328         case ETH_SPEED_NUM_100G:
2329                 new_link.link_speed = mac->link_speed;
2330                 break;
2331         default:
2332                 new_link.link_speed = ETH_SPEED_NUM_100M;
2333                 break;
2334         }
2335
2336         new_link.link_duplex = mac->link_duplex;
2337         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2338         new_link.link_autoneg =
2339             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2340
2341         return rte_eth_linkstatus_set(eth_dev, &new_link);
2342 }
2343
2344 static int
2345 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2346 {
2347         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2348         struct hns3_pf *pf = &hns->pf;
2349
2350         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2351                 return -EINVAL;
2352
2353         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2354
2355         return 0;
2356 }
2357
2358 static int
2359 hns3_query_function_status(struct hns3_hw *hw)
2360 {
2361 #define HNS3_QUERY_MAX_CNT              10
2362 #define HNS3_QUERY_SLEEP_MSCOEND        1
2363         struct hns3_func_status_cmd *req;
2364         struct hns3_cmd_desc desc;
2365         int timeout = 0;
2366         int ret;
2367
2368         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2369         req = (struct hns3_func_status_cmd *)desc.data;
2370
2371         do {
2372                 ret = hns3_cmd_send(hw, &desc, 1);
2373                 if (ret) {
2374                         PMD_INIT_LOG(ERR, "query function status failed %d",
2375                                      ret);
2376                         return ret;
2377                 }
2378
2379                 /* Check pf reset is done */
2380                 if (req->pf_state)
2381                         break;
2382
2383                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2384         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2385
2386         return hns3_parse_func_status(hw, req);
2387 }
2388
2389 static int
2390 hns3_query_pf_resource(struct hns3_hw *hw)
2391 {
2392         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2393         struct hns3_pf *pf = &hns->pf;
2394         struct hns3_pf_res_cmd *req;
2395         struct hns3_cmd_desc desc;
2396         int ret;
2397
2398         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2399         ret = hns3_cmd_send(hw, &desc, 1);
2400         if (ret) {
2401                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2402                 return ret;
2403         }
2404
2405         req = (struct hns3_pf_res_cmd *)desc.data;
2406         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2407         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2408         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2409         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2410
2411         if (req->tx_buf_size)
2412                 pf->tx_buf_size =
2413                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2414         else
2415                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2416
2417         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2418
2419         if (req->dv_buf_size)
2420                 pf->dv_buf_size =
2421                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2422         else
2423                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2424
2425         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2426
2427         hw->num_msi =
2428             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2429                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2430
2431         return 0;
2432 }
2433
2434 static void
2435 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2436 {
2437         struct hns3_cfg_param_cmd *req;
2438         uint64_t mac_addr_tmp_high;
2439         uint64_t mac_addr_tmp;
2440         uint32_t i;
2441
2442         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2443
2444         /* get the configuration */
2445         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2446                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2447         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2448                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2449         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2450                                            HNS3_CFG_TQP_DESC_N_M,
2451                                            HNS3_CFG_TQP_DESC_N_S);
2452
2453         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2454                                        HNS3_CFG_PHY_ADDR_M,
2455                                        HNS3_CFG_PHY_ADDR_S);
2456         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2457                                          HNS3_CFG_MEDIA_TP_M,
2458                                          HNS3_CFG_MEDIA_TP_S);
2459         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2460                                          HNS3_CFG_RX_BUF_LEN_M,
2461                                          HNS3_CFG_RX_BUF_LEN_S);
2462         /* get mac address */
2463         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2464         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2465                                            HNS3_CFG_MAC_ADDR_H_M,
2466                                            HNS3_CFG_MAC_ADDR_H_S);
2467
2468         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2469
2470         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2471                                             HNS3_CFG_DEFAULT_SPEED_M,
2472                                             HNS3_CFG_DEFAULT_SPEED_S);
2473         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2474                                            HNS3_CFG_RSS_SIZE_M,
2475                                            HNS3_CFG_RSS_SIZE_S);
2476
2477         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2478                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2479
2480         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2481         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2482
2483         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2484                                             HNS3_CFG_SPEED_ABILITY_M,
2485                                             HNS3_CFG_SPEED_ABILITY_S);
2486         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2487                                         HNS3_CFG_UMV_TBL_SPACE_M,
2488                                         HNS3_CFG_UMV_TBL_SPACE_S);
2489         if (!cfg->umv_space)
2490                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2491 }
2492
2493 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2494  * @hw: pointer to struct hns3_hw
2495  * @hcfg: the config structure to be getted
2496  */
2497 static int
2498 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2499 {
2500         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2501         struct hns3_cfg_param_cmd *req;
2502         uint32_t offset;
2503         uint32_t i;
2504         int ret;
2505
2506         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2507                 offset = 0;
2508                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2509                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2510                                           true);
2511                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2512                                i * HNS3_CFG_RD_LEN_BYTES);
2513                 /* Len should be divided by 4 when send to hardware */
2514                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2515                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2516                 req->offset = rte_cpu_to_le_32(offset);
2517         }
2518
2519         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2520         if (ret) {
2521                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2522                 return ret;
2523         }
2524
2525         hns3_parse_cfg(hcfg, desc);
2526
2527         return 0;
2528 }
2529
2530 static int
2531 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2532 {
2533         switch (speed_cmd) {
2534         case HNS3_CFG_SPEED_10M:
2535                 *speed = ETH_SPEED_NUM_10M;
2536                 break;
2537         case HNS3_CFG_SPEED_100M:
2538                 *speed = ETH_SPEED_NUM_100M;
2539                 break;
2540         case HNS3_CFG_SPEED_1G:
2541                 *speed = ETH_SPEED_NUM_1G;
2542                 break;
2543         case HNS3_CFG_SPEED_10G:
2544                 *speed = ETH_SPEED_NUM_10G;
2545                 break;
2546         case HNS3_CFG_SPEED_25G:
2547                 *speed = ETH_SPEED_NUM_25G;
2548                 break;
2549         case HNS3_CFG_SPEED_40G:
2550                 *speed = ETH_SPEED_NUM_40G;
2551                 break;
2552         case HNS3_CFG_SPEED_50G:
2553                 *speed = ETH_SPEED_NUM_50G;
2554                 break;
2555         case HNS3_CFG_SPEED_100G:
2556                 *speed = ETH_SPEED_NUM_100G;
2557                 break;
2558         default:
2559                 return -EINVAL;
2560         }
2561
2562         return 0;
2563 }
2564
2565 static int
2566 hns3_get_board_configuration(struct hns3_hw *hw)
2567 {
2568         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2569         struct hns3_pf *pf = &hns->pf;
2570         struct hns3_cfg cfg;
2571         int ret;
2572
2573         ret = hns3_get_board_cfg(hw, &cfg);
2574         if (ret) {
2575                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2576                 return ret;
2577         }
2578
2579         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2580                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2581                 return -EOPNOTSUPP;
2582         }
2583
2584         hw->mac.media_type = cfg.media_type;
2585         hw->rss_size_max = cfg.rss_size_max;
2586         hw->rx_buf_len = cfg.rx_buf_len;
2587         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2588         hw->mac.phy_addr = cfg.phy_addr;
2589         hw->mac.default_addr_setted = false;
2590         hw->num_tx_desc = cfg.tqp_desc_num;
2591         hw->num_rx_desc = cfg.tqp_desc_num;
2592         hw->dcb_info.num_pg = 1;
2593         hw->dcb_info.hw_pfc_map = 0;
2594
2595         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2596         if (ret) {
2597                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2598                              cfg.default_speed, ret);
2599                 return ret;
2600         }
2601
2602         pf->tc_max = cfg.tc_num;
2603         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2604                 PMD_INIT_LOG(WARNING,
2605                              "Get TC num(%u) from flash, set TC num to 1",
2606                              pf->tc_max);
2607                 pf->tc_max = 1;
2608         }
2609
2610         /* Dev does not support DCB */
2611         if (!hns3_dev_dcb_supported(hw)) {
2612                 pf->tc_max = 1;
2613                 pf->pfc_max = 0;
2614         } else
2615                 pf->pfc_max = pf->tc_max;
2616
2617         hw->dcb_info.num_tc = 1;
2618         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2619                                      hw->tqps_num / hw->dcb_info.num_tc);
2620         hns3_set_bit(hw->hw_tc_map, 0, 1);
2621         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2622
2623         pf->wanted_umv_size = cfg.umv_space;
2624
2625         return ret;
2626 }
2627
2628 static int
2629 hns3_get_configuration(struct hns3_hw *hw)
2630 {
2631         int ret;
2632
2633         ret = hns3_query_function_status(hw);
2634         if (ret) {
2635                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2636                 return ret;
2637         }
2638
2639         /* Get pf resource */
2640         ret = hns3_query_pf_resource(hw);
2641         if (ret) {
2642                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2643                 return ret;
2644         }
2645
2646         ret = hns3_get_board_configuration(hw);
2647         if (ret) {
2648                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2649                 return ret;
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int
2656 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2657                       uint16_t tqp_vid, bool is_pf)
2658 {
2659         struct hns3_tqp_map_cmd *req;
2660         struct hns3_cmd_desc desc;
2661         int ret;
2662
2663         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2664
2665         req = (struct hns3_tqp_map_cmd *)desc.data;
2666         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2667         req->tqp_vf = func_id;
2668         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2669         if (!is_pf)
2670                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2671         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2672
2673         ret = hns3_cmd_send(hw, &desc, 1);
2674         if (ret)
2675                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2676
2677         return ret;
2678 }
2679
2680 static int
2681 hns3_map_tqp(struct hns3_hw *hw)
2682 {
2683         uint16_t tqps_num = hw->total_tqps_num;
2684         uint16_t func_id;
2685         uint16_t tqp_id;
2686         bool is_pf;
2687         int num;
2688         int ret;
2689         int i;
2690
2691         /*
2692          * In current version VF is not supported when PF is driven by DPDK
2693          * driver, so we allocate tqps to PF as much as possible.
2694          */
2695         tqp_id = 0;
2696         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2697         for (func_id = 0; func_id < num; func_id++) {
2698                 is_pf = func_id == 0 ? true : false;
2699                 for (i = 0;
2700                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2701                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2702                                                     is_pf);
2703                         if (ret)
2704                                 return ret;
2705                 }
2706         }
2707
2708         return 0;
2709 }
2710
2711 static int
2712 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2713 {
2714         struct hns3_config_mac_speed_dup_cmd *req;
2715         struct hns3_cmd_desc desc;
2716         int ret;
2717
2718         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2719
2720         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2721
2722         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2723
2724         switch (speed) {
2725         case ETH_SPEED_NUM_10M:
2726                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2727                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2728                 break;
2729         case ETH_SPEED_NUM_100M:
2730                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2731                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2732                 break;
2733         case ETH_SPEED_NUM_1G:
2734                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2735                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2736                 break;
2737         case ETH_SPEED_NUM_10G:
2738                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2739                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2740                 break;
2741         case ETH_SPEED_NUM_25G:
2742                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2743                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2744                 break;
2745         case ETH_SPEED_NUM_40G:
2746                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2747                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2748                 break;
2749         case ETH_SPEED_NUM_50G:
2750                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2751                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2752                 break;
2753         case ETH_SPEED_NUM_100G:
2754                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2755                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2756                 break;
2757         default:
2758                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2759                 return -EINVAL;
2760         }
2761
2762         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2763
2764         ret = hns3_cmd_send(hw, &desc, 1);
2765         if (ret)
2766                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2767
2768         return ret;
2769 }
2770
2771 static int
2772 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2773 {
2774         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2775         struct hns3_pf *pf = &hns->pf;
2776         struct hns3_priv_buf *priv;
2777         uint32_t i, total_size;
2778
2779         total_size = pf->pkt_buf_size;
2780
2781         /* alloc tx buffer for all enabled tc */
2782         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2783                 priv = &buf_alloc->priv_buf[i];
2784
2785                 if (hw->hw_tc_map & BIT(i)) {
2786                         if (total_size < pf->tx_buf_size)
2787                                 return -ENOMEM;
2788
2789                         priv->tx_buf_size = pf->tx_buf_size;
2790                 } else
2791                         priv->tx_buf_size = 0;
2792
2793                 total_size -= priv->tx_buf_size;
2794         }
2795
2796         return 0;
2797 }
2798
2799 static int
2800 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2801 {
2802 /* TX buffer size is unit by 128 byte */
2803 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2804 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2805         struct hns3_tx_buff_alloc_cmd *req;
2806         struct hns3_cmd_desc desc;
2807         uint32_t buf_size;
2808         uint32_t i;
2809         int ret;
2810
2811         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2812
2813         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2814         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2815                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2816
2817                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2818                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2819                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2820         }
2821
2822         ret = hns3_cmd_send(hw, &desc, 1);
2823         if (ret)
2824                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2825
2826         return ret;
2827 }
2828
2829 static int
2830 hns3_get_tc_num(struct hns3_hw *hw)
2831 {
2832         int cnt = 0;
2833         uint8_t i;
2834
2835         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2836                 if (hw->hw_tc_map & BIT(i))
2837                         cnt++;
2838         return cnt;
2839 }
2840
2841 static uint32_t
2842 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2843 {
2844         struct hns3_priv_buf *priv;
2845         uint32_t rx_priv = 0;
2846         int i;
2847
2848         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2849                 priv = &buf_alloc->priv_buf[i];
2850                 if (priv->enable)
2851                         rx_priv += priv->buf_size;
2852         }
2853         return rx_priv;
2854 }
2855
2856 static uint32_t
2857 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2858 {
2859         uint32_t total_tx_size = 0;
2860         uint32_t i;
2861
2862         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2863                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2864
2865         return total_tx_size;
2866 }
2867
2868 /* Get the number of pfc enabled TCs, which have private buffer */
2869 static int
2870 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2871 {
2872         struct hns3_priv_buf *priv;
2873         int cnt = 0;
2874         uint8_t i;
2875
2876         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2877                 priv = &buf_alloc->priv_buf[i];
2878                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2879                         cnt++;
2880         }
2881
2882         return cnt;
2883 }
2884
2885 /* Get the number of pfc disabled TCs, which have private buffer */
2886 static int
2887 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2888                          struct hns3_pkt_buf_alloc *buf_alloc)
2889 {
2890         struct hns3_priv_buf *priv;
2891         int cnt = 0;
2892         uint8_t i;
2893
2894         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2895                 priv = &buf_alloc->priv_buf[i];
2896                 if (hw->hw_tc_map & BIT(i) &&
2897                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2898                         cnt++;
2899         }
2900
2901         return cnt;
2902 }
2903
2904 static bool
2905 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2906                   uint32_t rx_all)
2907 {
2908         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2909         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2910         struct hns3_pf *pf = &hns->pf;
2911         uint32_t shared_buf, aligned_mps;
2912         uint32_t rx_priv;
2913         uint8_t tc_num;
2914         uint8_t i;
2915
2916         tc_num = hns3_get_tc_num(hw);
2917         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2918
2919         if (hns3_dev_dcb_supported(hw))
2920                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2921                                         pf->dv_buf_size;
2922         else
2923                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2924                                         + pf->dv_buf_size;
2925
2926         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2927         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2928                              HNS3_BUF_SIZE_UNIT);
2929
2930         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2931         if (rx_all < rx_priv + shared_std)
2932                 return false;
2933
2934         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2935         buf_alloc->s_buf.buf_size = shared_buf;
2936         if (hns3_dev_dcb_supported(hw)) {
2937                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2938                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2939                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2940                                   HNS3_BUF_SIZE_UNIT);
2941         } else {
2942                 buf_alloc->s_buf.self.high =
2943                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2944                 buf_alloc->s_buf.self.low = aligned_mps;
2945         }
2946
2947         if (hns3_dev_dcb_supported(hw)) {
2948                 hi_thrd = shared_buf - pf->dv_buf_size;
2949
2950                 if (tc_num <= NEED_RESERVE_TC_NUM)
2951                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2952                                         / BUF_MAX_PERCENT;
2953
2954                 if (tc_num)
2955                         hi_thrd = hi_thrd / tc_num;
2956
2957                 hi_thrd = max_t(uint32_t, hi_thrd,
2958                                 HNS3_BUF_MUL_BY * aligned_mps);
2959                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2960                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2961         } else {
2962                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2963                 lo_thrd = aligned_mps;
2964         }
2965
2966         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2967                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2968                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2969         }
2970
2971         return true;
2972 }
2973
2974 static bool
2975 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2976                      struct hns3_pkt_buf_alloc *buf_alloc)
2977 {
2978         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2979         struct hns3_pf *pf = &hns->pf;
2980         struct hns3_priv_buf *priv;
2981         uint32_t aligned_mps;
2982         uint32_t rx_all;
2983         uint8_t i;
2984
2985         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2986         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2987
2988         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2989                 priv = &buf_alloc->priv_buf[i];
2990
2991                 priv->enable = 0;
2992                 priv->wl.low = 0;
2993                 priv->wl.high = 0;
2994                 priv->buf_size = 0;
2995
2996                 if (!(hw->hw_tc_map & BIT(i)))
2997                         continue;
2998
2999                 priv->enable = 1;
3000                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3001                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3002                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3003                                                 HNS3_BUF_SIZE_UNIT);
3004                 } else {
3005                         priv->wl.low = 0;
3006                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3007                                         aligned_mps;
3008                 }
3009
3010                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3011         }
3012
3013         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3014 }
3015
3016 static bool
3017 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3018                              struct hns3_pkt_buf_alloc *buf_alloc)
3019 {
3020         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3021         struct hns3_pf *pf = &hns->pf;
3022         struct hns3_priv_buf *priv;
3023         int no_pfc_priv_num;
3024         uint32_t rx_all;
3025         uint8_t mask;
3026         int i;
3027
3028         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3029         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3030
3031         /* let the last to be cleared first */
3032         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3033                 priv = &buf_alloc->priv_buf[i];
3034                 mask = BIT((uint8_t)i);
3035
3036                 if (hw->hw_tc_map & mask &&
3037                     !(hw->dcb_info.hw_pfc_map & mask)) {
3038                         /* Clear the no pfc TC private buffer */
3039                         priv->wl.low = 0;
3040                         priv->wl.high = 0;
3041                         priv->buf_size = 0;
3042                         priv->enable = 0;
3043                         no_pfc_priv_num--;
3044                 }
3045
3046                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3047                     no_pfc_priv_num == 0)
3048                         break;
3049         }
3050
3051         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3052 }
3053
3054 static bool
3055 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3056                            struct hns3_pkt_buf_alloc *buf_alloc)
3057 {
3058         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3059         struct hns3_pf *pf = &hns->pf;
3060         struct hns3_priv_buf *priv;
3061         uint32_t rx_all;
3062         int pfc_priv_num;
3063         uint8_t mask;
3064         int i;
3065
3066         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3067         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3068
3069         /* let the last to be cleared first */
3070         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3071                 priv = &buf_alloc->priv_buf[i];
3072                 mask = BIT((uint8_t)i);
3073
3074                 if (hw->hw_tc_map & mask &&
3075                     hw->dcb_info.hw_pfc_map & mask) {
3076                         /* Reduce the number of pfc TC with private buffer */
3077                         priv->wl.low = 0;
3078                         priv->enable = 0;
3079                         priv->wl.high = 0;
3080                         priv->buf_size = 0;
3081                         pfc_priv_num--;
3082                 }
3083                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3084                     pfc_priv_num == 0)
3085                         break;
3086         }
3087
3088         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3089 }
3090
3091 static bool
3092 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3093                           struct hns3_pkt_buf_alloc *buf_alloc)
3094 {
3095 #define COMPENSATE_BUFFER       0x3C00
3096 #define COMPENSATE_HALF_MPS_NUM 5
3097 #define PRIV_WL_GAP             0x1800
3098         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3099         struct hns3_pf *pf = &hns->pf;
3100         uint32_t tc_num = hns3_get_tc_num(hw);
3101         uint32_t half_mps = pf->mps >> 1;
3102         struct hns3_priv_buf *priv;
3103         uint32_t min_rx_priv;
3104         uint32_t rx_priv;
3105         uint8_t i;
3106
3107         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3108         if (tc_num)
3109                 rx_priv = rx_priv / tc_num;
3110
3111         if (tc_num <= NEED_RESERVE_TC_NUM)
3112                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3113
3114         /*
3115          * Minimum value of private buffer in rx direction (min_rx_priv) is
3116          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3117          * buffer if rx_priv is greater than min_rx_priv.
3118          */
3119         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3120                         COMPENSATE_HALF_MPS_NUM * half_mps;
3121         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3122         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3123
3124         if (rx_priv < min_rx_priv)
3125                 return false;
3126
3127         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3128                 priv = &buf_alloc->priv_buf[i];
3129
3130                 priv->enable = 0;
3131                 priv->wl.low = 0;
3132                 priv->wl.high = 0;
3133                 priv->buf_size = 0;
3134
3135                 if (!(hw->hw_tc_map & BIT(i)))
3136                         continue;
3137
3138                 priv->enable = 1;
3139                 priv->buf_size = rx_priv;
3140                 priv->wl.high = rx_priv - pf->dv_buf_size;
3141                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3142         }
3143
3144         buf_alloc->s_buf.buf_size = 0;
3145
3146         return true;
3147 }
3148
3149 /*
3150  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3151  * @hw: pointer to struct hns3_hw
3152  * @buf_alloc: pointer to buffer calculation data
3153  * @return: 0: calculate sucessful, negative: fail
3154  */
3155 static int
3156 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3157 {
3158         /* When DCB is not supported, rx private buffer is not allocated. */
3159         if (!hns3_dev_dcb_supported(hw)) {
3160                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3161                 struct hns3_pf *pf = &hns->pf;
3162                 uint32_t rx_all = pf->pkt_buf_size;
3163
3164                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3165                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3166                         return -ENOMEM;
3167
3168                 return 0;
3169         }
3170
3171         /*
3172          * Try to allocate privated packet buffer for all TCs without share
3173          * buffer.
3174          */
3175         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3176                 return 0;
3177
3178         /*
3179          * Try to allocate privated packet buffer for all TCs with share
3180          * buffer.
3181          */
3182         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3183                 return 0;
3184
3185         /*
3186          * For different application scenes, the enabled port number, TC number
3187          * and no_drop TC number are different. In order to obtain the better
3188          * performance, software could allocate the buffer size and configure
3189          * the waterline by tring to decrease the private buffer size according
3190          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3191          * enabled tc.
3192          */
3193         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3194                 return 0;
3195
3196         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3197                 return 0;
3198
3199         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3200                 return 0;
3201
3202         return -ENOMEM;
3203 }
3204
3205 static int
3206 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3207 {
3208         struct hns3_rx_priv_buff_cmd *req;
3209         struct hns3_cmd_desc desc;
3210         uint32_t buf_size;
3211         int ret;
3212         int i;
3213
3214         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3215         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3216
3217         /* Alloc private buffer TCs */
3218         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3219                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3220
3221                 req->buf_num[i] =
3222                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3223                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3224         }
3225
3226         buf_size = buf_alloc->s_buf.buf_size;
3227         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3228                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3229
3230         ret = hns3_cmd_send(hw, &desc, 1);
3231         if (ret)
3232                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3233
3234         return ret;
3235 }
3236
3237 static int
3238 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3239 {
3240 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3241         struct hns3_rx_priv_wl_buf *req;
3242         struct hns3_priv_buf *priv;
3243         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3244         int i, j;
3245         int ret;
3246
3247         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3248                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3249                                           false);
3250                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3251
3252                 /* The first descriptor set the NEXT bit to 1 */
3253                 if (i == 0)
3254                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3255                 else
3256                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3257
3258                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3259                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3260
3261                         priv = &buf_alloc->priv_buf[idx];
3262                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3263                                                         HNS3_BUF_UNIT_S);
3264                         req->tc_wl[j].high |=
3265                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3266                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3267                                                         HNS3_BUF_UNIT_S);
3268                         req->tc_wl[j].low |=
3269                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3270                 }
3271         }
3272
3273         /* Send 2 descriptor at one time */
3274         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3275         if (ret)
3276                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3277                              ret);
3278         return ret;
3279 }
3280
3281 static int
3282 hns3_common_thrd_config(struct hns3_hw *hw,
3283                         struct hns3_pkt_buf_alloc *buf_alloc)
3284 {
3285 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3286         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3287         struct hns3_rx_com_thrd *req;
3288         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3289         struct hns3_tc_thrd *tc;
3290         int tc_idx;
3291         int i, j;
3292         int ret;
3293
3294         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3295                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3296                                           false);
3297                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3298
3299                 /* The first descriptor set the NEXT bit to 1 */
3300                 if (i == 0)
3301                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3302                 else
3303                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3304
3305                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3306                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3307                         tc = &s_buf->tc_thrd[tc_idx];
3308
3309                         req->com_thrd[j].high =
3310                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3311                         req->com_thrd[j].high |=
3312                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3313                         req->com_thrd[j].low =
3314                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3315                         req->com_thrd[j].low |=
3316                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3317                 }
3318         }
3319
3320         /* Send 2 descriptors at one time */
3321         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3322         if (ret)
3323                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3324
3325         return ret;
3326 }
3327
3328 static int
3329 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3330 {
3331         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3332         struct hns3_rx_com_wl *req;
3333         struct hns3_cmd_desc desc;
3334         int ret;
3335
3336         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3337
3338         req = (struct hns3_rx_com_wl *)desc.data;
3339         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3340         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3341
3342         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3343         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3344
3345         ret = hns3_cmd_send(hw, &desc, 1);
3346         if (ret)
3347                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3348
3349         return ret;
3350 }
3351
3352 int
3353 hns3_buffer_alloc(struct hns3_hw *hw)
3354 {
3355         struct hns3_pkt_buf_alloc pkt_buf;
3356         int ret;
3357
3358         memset(&pkt_buf, 0, sizeof(pkt_buf));
3359         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3360         if (ret) {
3361                 PMD_INIT_LOG(ERR,
3362                              "could not calc tx buffer size for all TCs %d",
3363                              ret);
3364                 return ret;
3365         }
3366
3367         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3368         if (ret) {
3369                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3370                 return ret;
3371         }
3372
3373         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3374         if (ret) {
3375                 PMD_INIT_LOG(ERR,
3376                              "could not calc rx priv buffer size for all TCs %d",
3377                              ret);
3378                 return ret;
3379         }
3380
3381         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3382         if (ret) {
3383                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3384                 return ret;
3385         }
3386
3387         if (hns3_dev_dcb_supported(hw)) {
3388                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3389                 if (ret) {
3390                         PMD_INIT_LOG(ERR,
3391                                      "could not configure rx private waterline %d",
3392                                      ret);
3393                         return ret;
3394                 }
3395
3396                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3397                 if (ret) {
3398                         PMD_INIT_LOG(ERR,
3399                                      "could not configure common threshold %d",
3400                                      ret);
3401                         return ret;
3402                 }
3403         }
3404
3405         ret = hns3_common_wl_config(hw, &pkt_buf);
3406         if (ret)
3407                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3408                              ret);
3409
3410         return ret;
3411 }
3412
3413 static int
3414 hns3_mac_init(struct hns3_hw *hw)
3415 {
3416         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3417         struct hns3_mac *mac = &hw->mac;
3418         struct hns3_pf *pf = &hns->pf;
3419         int ret;
3420
3421         pf->support_sfp_query = true;
3422         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3423         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3424         if (ret) {
3425                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3426                 return ret;
3427         }
3428
3429         mac->link_status = ETH_LINK_DOWN;
3430
3431         return hns3_config_mtu(hw, pf->mps);
3432 }
3433
3434 static int
3435 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3436 {
3437 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3438 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3439 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3440 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3441         int return_status;
3442
3443         if (cmdq_resp) {
3444                 PMD_INIT_LOG(ERR,
3445                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3446                              cmdq_resp);
3447                 return -EIO;
3448         }
3449
3450         switch (resp_code) {
3451         case HNS3_ETHERTYPE_SUCCESS_ADD:
3452         case HNS3_ETHERTYPE_ALREADY_ADD:
3453                 return_status = 0;
3454                 break;
3455         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3456                 PMD_INIT_LOG(ERR,
3457                              "add mac ethertype failed for manager table overflow.");
3458                 return_status = -EIO;
3459                 break;
3460         case HNS3_ETHERTYPE_KEY_CONFLICT:
3461                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3462                 return_status = -EIO;
3463                 break;
3464         default:
3465                 PMD_INIT_LOG(ERR,
3466                              "add mac ethertype failed for undefined, code=%d.",
3467                              resp_code);
3468                 return_status = -EIO;
3469         }
3470
3471         return return_status;
3472 }
3473
3474 static int
3475 hns3_add_mgr_tbl(struct hns3_hw *hw,
3476                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3477 {
3478         struct hns3_cmd_desc desc;
3479         uint8_t resp_code;
3480         uint16_t retval;
3481         int ret;
3482
3483         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3484         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3485
3486         ret = hns3_cmd_send(hw, &desc, 1);
3487         if (ret) {
3488                 PMD_INIT_LOG(ERR,
3489                              "add mac ethertype failed for cmd_send, ret =%d.",
3490                              ret);
3491                 return ret;
3492         }
3493
3494         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3495         retval = rte_le_to_cpu_16(desc.retval);
3496
3497         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3498 }
3499
3500 static void
3501 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3502                      int *table_item_num)
3503 {
3504         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3505
3506         /*
3507          * In current version, we add one item in management table as below:
3508          * 0x0180C200000E -- LLDP MC address
3509          */
3510         tbl = mgr_table;
3511         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3512         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3513         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3514         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3515         tbl->i_port_bitmap = 0x1;
3516         *table_item_num = 1;
3517 }
3518
3519 static int
3520 hns3_init_mgr_tbl(struct hns3_hw *hw)
3521 {
3522 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3523         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3524         int table_item_num;
3525         int ret;
3526         int i;
3527
3528         memset(mgr_table, 0, sizeof(mgr_table));
3529         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3530         for (i = 0; i < table_item_num; i++) {
3531                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3532                 if (ret) {
3533                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3534                                      ret);
3535                         return ret;
3536                 }
3537         }
3538
3539         return 0;
3540 }
3541
3542 static void
3543 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3544                         bool en_mc, bool en_bc, int vport_id)
3545 {
3546         if (!param)
3547                 return;
3548
3549         memset(param, 0, sizeof(struct hns3_promisc_param));
3550         if (en_uc)
3551                 param->enable = HNS3_PROMISC_EN_UC;
3552         if (en_mc)
3553                 param->enable |= HNS3_PROMISC_EN_MC;
3554         if (en_bc)
3555                 param->enable |= HNS3_PROMISC_EN_BC;
3556         param->vf_id = vport_id;
3557 }
3558
3559 static int
3560 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3561 {
3562         struct hns3_promisc_cfg_cmd *req;
3563         struct hns3_cmd_desc desc;
3564         int ret;
3565
3566         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3567
3568         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3569         req->vf_id = param->vf_id;
3570         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3571             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3572
3573         ret = hns3_cmd_send(hw, &desc, 1);
3574         if (ret)
3575                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3576
3577         return ret;
3578 }
3579
3580 static int
3581 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3582 {
3583         struct hns3_promisc_param param;
3584         bool en_bc_pmc = true;
3585         uint8_t vf_id;
3586         int ret;
3587
3588         /*
3589          * In current version VF is not supported when PF is driven by DPDK
3590          * driver, the PF-related vf_id is 0, just need to configure parameters
3591          * for vf_id 0.
3592          */
3593         vf_id = 0;
3594
3595         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3596         ret = hns3_cmd_set_promisc_mode(hw, &param);
3597         if (ret)
3598                 return ret;
3599
3600         return 0;
3601 }
3602
3603 static int
3604 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3605 {
3606         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3607         struct hns3_pf *pf = &hns->pf;
3608         struct hns3_promisc_param param;
3609         uint16_t func_id;
3610         int ret;
3611
3612         /* func_id 0 is denoted PF, the VFs start from 1 */
3613         for (func_id = 1; func_id < pf->func_num; func_id++) {
3614                 hns3_promisc_param_init(&param, false, false, false, func_id);
3615                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3616                 if (ret)
3617                         return ret;
3618         }
3619
3620         return 0;
3621 }
3622
3623 static int
3624 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3625 {
3626         struct hns3_adapter *hns = dev->data->dev_private;
3627         struct hns3_hw *hw = &hns->hw;
3628         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3629         int ret;
3630
3631         rte_spinlock_lock(&hw->lock);
3632         ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3633         rte_spinlock_unlock(&hw->lock);
3634         if (ret)
3635                 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3636
3637         return ret;
3638 }
3639
3640 static int
3641 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3642 {
3643         struct hns3_adapter *hns = dev->data->dev_private;
3644         struct hns3_hw *hw = &hns->hw;
3645         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3646         int ret;
3647
3648         /* If now in all_multicast mode, must remain in all_multicast mode. */
3649         rte_spinlock_lock(&hw->lock);
3650         ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3651         rte_spinlock_unlock(&hw->lock);
3652         if (ret)
3653                 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3654
3655         return ret;
3656 }
3657
3658 static int
3659 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3660 {
3661         struct hns3_adapter *hns = dev->data->dev_private;
3662         struct hns3_hw *hw = &hns->hw;
3663         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3664         int ret;
3665
3666         rte_spinlock_lock(&hw->lock);
3667         ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3668         rte_spinlock_unlock(&hw->lock);
3669         if (ret)
3670                 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3671
3672         return ret;
3673 }
3674
3675 static int
3676 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3677 {
3678         struct hns3_adapter *hns = dev->data->dev_private;
3679         struct hns3_hw *hw = &hns->hw;
3680         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3681         int ret;
3682
3683         /* If now in promiscuous mode, must remain in all_multicast mode. */
3684         if (dev->data->promiscuous == 1)
3685                 return 0;
3686
3687         rte_spinlock_lock(&hw->lock);
3688         ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3689         rte_spinlock_unlock(&hw->lock);
3690         if (ret)
3691                 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3692
3693         return ret;
3694 }
3695
3696 static int
3697 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3698 {
3699         struct hns3_hw *hw = &hns->hw;
3700         bool en_mc_pmc;
3701         bool en_uc_pmc;
3702
3703         en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3704         en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3705
3706         return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3707 }
3708
3709 static int
3710 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3711 {
3712         struct hns3_sfp_speed_cmd *resp;
3713         struct hns3_cmd_desc desc;
3714         int ret;
3715
3716         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3717         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3718         ret = hns3_cmd_send(hw, &desc, 1);
3719         if (ret == -EOPNOTSUPP) {
3720                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3721                 return ret;
3722         } else if (ret) {
3723                 hns3_err(hw, "get sfp speed failed %d", ret);
3724                 return ret;
3725         }
3726
3727         *speed = resp->sfp_speed;
3728
3729         return 0;
3730 }
3731
3732 static uint8_t
3733 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3734 {
3735         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3736                 duplex = ETH_LINK_FULL_DUPLEX;
3737
3738         return duplex;
3739 }
3740
3741 static int
3742 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3743 {
3744         struct hns3_mac *mac = &hw->mac;
3745         int ret;
3746
3747         duplex = hns3_check_speed_dup(duplex, speed);
3748         if (mac->link_speed == speed && mac->link_duplex == duplex)
3749                 return 0;
3750
3751         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3752         if (ret)
3753                 return ret;
3754
3755         mac->link_speed = speed;
3756         mac->link_duplex = duplex;
3757
3758         return 0;
3759 }
3760
3761 static int
3762 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3763 {
3764         struct hns3_adapter *hns = eth_dev->data->dev_private;
3765         struct hns3_hw *hw = &hns->hw;
3766         struct hns3_pf *pf = &hns->pf;
3767         uint32_t speed;
3768         int ret;
3769
3770         /* If IMP do not support get SFP/qSFP speed, return directly */
3771         if (!pf->support_sfp_query)
3772                 return 0;
3773
3774         ret = hns3_get_sfp_speed(hw, &speed);
3775         if (ret == -EOPNOTSUPP) {
3776                 pf->support_sfp_query = false;
3777                 return ret;
3778         } else if (ret)
3779                 return ret;
3780
3781         if (speed == ETH_SPEED_NUM_NONE)
3782                 return 0; /* do nothing if no SFP */
3783
3784         /* Config full duplex for SFP */
3785         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3786 }
3787
3788 static int
3789 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3790 {
3791         struct hns3_config_mac_mode_cmd *req;
3792         struct hns3_cmd_desc desc;
3793         uint32_t loop_en = 0;
3794         uint8_t val = 0;
3795         int ret;
3796
3797         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3798
3799         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3800         if (enable)
3801                 val = 1;
3802         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3803         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3804         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3805         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3806         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3807         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3808         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3809         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3810         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3811         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3812         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3813         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3814         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3815         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3816         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3817
3818         ret = hns3_cmd_send(hw, &desc, 1);
3819         if (ret)
3820                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3821
3822         return ret;
3823 }
3824
3825 static int
3826 hns3_get_mac_link_status(struct hns3_hw *hw)
3827 {
3828         struct hns3_link_status_cmd *req;
3829         struct hns3_cmd_desc desc;
3830         int link_status;
3831         int ret;
3832
3833         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3834         ret = hns3_cmd_send(hw, &desc, 1);
3835         if (ret) {
3836                 hns3_err(hw, "get link status cmd failed %d", ret);
3837                 return ETH_LINK_DOWN;
3838         }
3839
3840         req = (struct hns3_link_status_cmd *)desc.data;
3841         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3842
3843         return !!link_status;
3844 }
3845
3846 void
3847 hns3_update_link_status(struct hns3_hw *hw)
3848 {
3849         int state;
3850
3851         state = hns3_get_mac_link_status(hw);
3852         if (state != hw->mac.link_status) {
3853                 hw->mac.link_status = state;
3854                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3855         }
3856 }
3857
3858 static void
3859 hns3_service_handler(void *param)
3860 {
3861         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3862         struct hns3_adapter *hns = eth_dev->data->dev_private;
3863         struct hns3_hw *hw = &hns->hw;
3864
3865         if (!hns3_is_reset_pending(hns)) {
3866                 hns3_update_speed_duplex(eth_dev);
3867                 hns3_update_link_status(hw);
3868         } else
3869                 hns3_warn(hw, "Cancel the query when reset is pending");
3870
3871         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3872 }
3873
3874 static int
3875 hns3_init_hardware(struct hns3_adapter *hns)
3876 {
3877         struct hns3_hw *hw = &hns->hw;
3878         int ret;
3879
3880         ret = hns3_map_tqp(hw);
3881         if (ret) {
3882                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3883                 return ret;
3884         }
3885
3886         ret = hns3_init_umv_space(hw);
3887         if (ret) {
3888                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3889                 return ret;
3890         }
3891
3892         ret = hns3_mac_init(hw);
3893         if (ret) {
3894                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3895                 goto err_mac_init;
3896         }
3897
3898         ret = hns3_init_mgr_tbl(hw);
3899         if (ret) {
3900                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3901                 goto err_mac_init;
3902         }
3903
3904         ret = hns3_set_promisc_mode(hw, false, false);
3905         if (ret) {
3906                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3907                 goto err_mac_init;
3908         }
3909
3910         ret = hns3_clear_all_vfs_promisc_mode(hw);
3911         if (ret) {
3912                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3913                              ret);
3914                 goto err_mac_init;
3915         }
3916
3917         ret = hns3_init_vlan_config(hns);
3918         if (ret) {
3919                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3920                 goto err_mac_init;
3921         }
3922
3923         ret = hns3_dcb_init(hw);
3924         if (ret) {
3925                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3926                 goto err_mac_init;
3927         }
3928
3929         ret = hns3_init_fd_config(hns);
3930         if (ret) {
3931                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3932                 goto err_mac_init;
3933         }
3934
3935         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3936         if (ret) {
3937                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3938                 goto err_mac_init;
3939         }
3940
3941         ret = hns3_config_gro(hw, false);
3942         if (ret) {
3943                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3944                 goto err_mac_init;
3945         }
3946         return 0;
3947
3948 err_mac_init:
3949         hns3_uninit_umv_space(hw);
3950         return ret;
3951 }
3952
3953 static int
3954 hns3_init_pf(struct rte_eth_dev *eth_dev)
3955 {
3956         struct rte_device *dev = eth_dev->device;
3957         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3958         struct hns3_adapter *hns = eth_dev->data->dev_private;
3959         struct hns3_hw *hw = &hns->hw;
3960         int ret;
3961
3962         PMD_INIT_FUNC_TRACE();
3963
3964         /* Get hardware io base address from pcie BAR2 IO space */
3965         hw->io_base = pci_dev->mem_resource[2].addr;
3966
3967         /* Firmware command queue initialize */
3968         ret = hns3_cmd_init_queue(hw);
3969         if (ret) {
3970                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3971                 goto err_cmd_init_queue;
3972         }
3973
3974         hns3_clear_all_event_cause(hw);
3975
3976         /* Firmware command initialize */
3977         ret = hns3_cmd_init(hw);
3978         if (ret) {
3979                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3980                 goto err_cmd_init;
3981         }
3982
3983         ret = rte_intr_callback_register(&pci_dev->intr_handle,
3984                                          hns3_interrupt_handler,
3985                                          eth_dev);
3986         if (ret) {
3987                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3988                 goto err_intr_callback_register;
3989         }
3990
3991         /* Enable interrupt */
3992         rte_intr_enable(&pci_dev->intr_handle);
3993         hns3_pf_enable_irq0(hw);
3994
3995         /* Get configuration */
3996         ret = hns3_get_configuration(hw);
3997         if (ret) {
3998                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3999                 goto err_get_config;
4000         }
4001
4002         ret = hns3_init_hardware(hns);
4003         if (ret) {
4004                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4005                 goto err_get_config;
4006         }
4007
4008         /* Initialize flow director filter list & hash */
4009         ret = hns3_fdir_filter_init(hns);
4010         if (ret) {
4011                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4012                 goto err_hw_init;
4013         }
4014
4015         hns3_set_default_rss_args(hw);
4016
4017         ret = hns3_enable_hw_error_intr(hns, true);
4018         if (ret) {
4019                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4020                              ret);
4021                 goto err_fdir;
4022         }
4023
4024         return 0;
4025
4026 err_fdir:
4027         hns3_fdir_filter_uninit(hns);
4028 err_hw_init:
4029         hns3_uninit_umv_space(hw);
4030
4031 err_get_config:
4032         hns3_pf_disable_irq0(hw);
4033         rte_intr_disable(&pci_dev->intr_handle);
4034         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4035                              eth_dev);
4036
4037 err_intr_callback_register:
4038         hns3_cmd_uninit(hw);
4039
4040 err_cmd_init:
4041         hns3_cmd_destroy_queue(hw);
4042
4043 err_cmd_init_queue:
4044         hw->io_base = NULL;
4045
4046         return ret;
4047 }
4048
4049 static void
4050 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4051 {
4052         struct hns3_adapter *hns = eth_dev->data->dev_private;
4053         struct rte_device *dev = eth_dev->device;
4054         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4055         struct hns3_hw *hw = &hns->hw;
4056
4057         PMD_INIT_FUNC_TRACE();
4058
4059         hns3_enable_hw_error_intr(hns, false);
4060         hns3_rss_uninit(hns);
4061         hns3_fdir_filter_uninit(hns);
4062         hns3_uninit_umv_space(hw);
4063         hns3_pf_disable_irq0(hw);
4064         rte_intr_disable(&pci_dev->intr_handle);
4065         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4066                              eth_dev);
4067         hns3_cmd_uninit(hw);
4068         hns3_cmd_destroy_queue(hw);
4069         hw->io_base = NULL;
4070 }
4071
4072 static int
4073 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4074 {
4075         struct hns3_hw *hw = &hns->hw;
4076         int ret;
4077
4078         ret = hns3_dcb_cfg_update(hns);
4079         if (ret)
4080                 return ret;
4081
4082         /* Enable queues */
4083         ret = hns3_start_queues(hns, reset_queue);
4084         if (ret) {
4085                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4086                 return ret;
4087         }
4088
4089         /* Enable MAC */
4090         ret = hns3_cfg_mac_mode(hw, true);
4091         if (ret) {
4092                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4093                 goto err_config_mac_mode;
4094         }
4095         return 0;
4096
4097 err_config_mac_mode:
4098         hns3_stop_queues(hns, true);
4099         return ret;
4100 }
4101
4102 static int
4103 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4104 {
4105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4106         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4107         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108         uint32_t intr_vector;
4109         uint8_t base = 0;
4110         uint8_t vec = 0;
4111         uint16_t q_id;
4112         int ret;
4113
4114         if (dev->data->dev_conf.intr_conf.rxq == 0)
4115                 return 0;
4116
4117         /* disable uio/vfio intr/eventfd mapping */
4118         rte_intr_disable(intr_handle);
4119
4120         /* check and configure queue intr-vector mapping */
4121         if (rte_intr_cap_multiple(intr_handle) ||
4122             !RTE_ETH_DEV_SRIOV(dev).active) {
4123                 intr_vector = hw->used_rx_queues;
4124                 /* creates event fd for each intr vector when MSIX is used */
4125                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4126                         return -EINVAL;
4127         }
4128         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4129                 intr_handle->intr_vec =
4130                         rte_zmalloc("intr_vec",
4131                                     hw->used_rx_queues * sizeof(int), 0);
4132                 if (intr_handle->intr_vec == NULL) {
4133                         hns3_err(hw, "Failed to allocate %d rx_queues"
4134                                      " intr_vec", hw->used_rx_queues);
4135                         ret = -ENOMEM;
4136                         goto alloc_intr_vec_error;
4137                 }
4138         }
4139
4140         if (rte_intr_allow_others(intr_handle)) {
4141                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4142                 base = RTE_INTR_VEC_RXTX_OFFSET;
4143         }
4144         if (rte_intr_dp_is_en(intr_handle)) {
4145                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4146                         ret = hns3_bind_ring_with_vector(dev, vec, true, q_id);
4147                         if (ret)
4148                                 goto bind_vector_error;
4149                         intr_handle->intr_vec[q_id] = vec;
4150                         if (vec < base + intr_handle->nb_efd - 1)
4151                                 vec++;
4152                 }
4153         }
4154         rte_intr_enable(intr_handle);
4155         return 0;
4156
4157 bind_vector_error:
4158         rte_intr_efd_disable(intr_handle);
4159         if (intr_handle->intr_vec) {
4160                 free(intr_handle->intr_vec);
4161                 intr_handle->intr_vec = NULL;
4162         }
4163         return ret;
4164 alloc_intr_vec_error:
4165         rte_intr_efd_disable(intr_handle);
4166         return ret;
4167 }
4168
4169 static int
4170 hns3_dev_start(struct rte_eth_dev *dev)
4171 {
4172         struct hns3_adapter *hns = dev->data->dev_private;
4173         struct hns3_hw *hw = &hns->hw;
4174         int ret;
4175
4176         PMD_INIT_FUNC_TRACE();
4177         if (rte_atomic16_read(&hw->reset.resetting))
4178                 return -EBUSY;
4179
4180         rte_spinlock_lock(&hw->lock);
4181         hw->adapter_state = HNS3_NIC_STARTING;
4182
4183         ret = hns3_do_start(hns, true);
4184         if (ret) {
4185                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4186                 rte_spinlock_unlock(&hw->lock);
4187                 return ret;
4188         }
4189
4190         hw->adapter_state = HNS3_NIC_STARTED;
4191         rte_spinlock_unlock(&hw->lock);
4192
4193         ret = hns3_map_rx_interrupt(dev);
4194         if (ret)
4195                 return ret;
4196         hns3_set_rxtx_function(dev);
4197         hns3_mp_req_start_rxtx(dev);
4198         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4199
4200         hns3_info(hw, "hns3 dev start successful!");
4201         return 0;
4202 }
4203
4204 static int
4205 hns3_do_stop(struct hns3_adapter *hns)
4206 {
4207         struct hns3_hw *hw = &hns->hw;
4208         bool reset_queue;
4209         int ret;
4210
4211         ret = hns3_cfg_mac_mode(hw, false);
4212         if (ret)
4213                 return ret;
4214         hw->mac.link_status = ETH_LINK_DOWN;
4215
4216         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4217                 hns3_configure_all_mac_addr(hns, true);
4218                 reset_queue = true;
4219         } else
4220                 reset_queue = false;
4221         hw->mac.default_addr_setted = false;
4222         return hns3_stop_queues(hns, reset_queue);
4223 }
4224
4225 static void
4226 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4227 {
4228         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4229         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4230         struct hns3_adapter *hns = dev->data->dev_private;
4231         struct hns3_hw *hw = &hns->hw;
4232         uint8_t base = 0;
4233         uint8_t vec = 0;
4234         uint16_t q_id;
4235
4236         if (dev->data->dev_conf.intr_conf.rxq == 0)
4237                 return;
4238
4239         /* unmap the ring with vector */
4240         if (rte_intr_allow_others(intr_handle)) {
4241                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4242                 base = RTE_INTR_VEC_RXTX_OFFSET;
4243         }
4244         if (rte_intr_dp_is_en(intr_handle)) {
4245                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4246                         (void)hns3_bind_ring_with_vector(dev, vec, false, q_id);
4247                         if (vec < base + intr_handle->nb_efd - 1)
4248                                 vec++;
4249                 }
4250         }
4251         /* Clean datapath event and queue/vec mapping */
4252         rte_intr_efd_disable(intr_handle);
4253         if (intr_handle->intr_vec) {
4254                 rte_free(intr_handle->intr_vec);
4255                 intr_handle->intr_vec = NULL;
4256         }
4257 }
4258
4259 static void
4260 hns3_dev_stop(struct rte_eth_dev *dev)
4261 {
4262         struct hns3_adapter *hns = dev->data->dev_private;
4263         struct hns3_hw *hw = &hns->hw;
4264
4265         PMD_INIT_FUNC_TRACE();
4266
4267         hw->adapter_state = HNS3_NIC_STOPPING;
4268         hns3_set_rxtx_function(dev);
4269         rte_wmb();
4270         /* Disable datapath on secondary process. */
4271         hns3_mp_req_stop_rxtx(dev);
4272         /* Prevent crashes when queues are still in use. */
4273         rte_delay_ms(hw->tqps_num);
4274
4275         rte_spinlock_lock(&hw->lock);
4276         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4277                 hns3_do_stop(hns);
4278                 hns3_dev_release_mbufs(hns);
4279                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4280         }
4281         rte_eal_alarm_cancel(hns3_service_handler, dev);
4282         rte_spinlock_unlock(&hw->lock);
4283         hns3_unmap_rx_interrupt(dev);
4284 }
4285
4286 static void
4287 hns3_dev_close(struct rte_eth_dev *eth_dev)
4288 {
4289         struct hns3_adapter *hns = eth_dev->data->dev_private;
4290         struct hns3_hw *hw = &hns->hw;
4291
4292         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4293                 rte_free(eth_dev->process_private);
4294                 eth_dev->process_private = NULL;
4295                 return;
4296         }
4297
4298         if (hw->adapter_state == HNS3_NIC_STARTED)
4299                 hns3_dev_stop(eth_dev);
4300
4301         hw->adapter_state = HNS3_NIC_CLOSING;
4302         hns3_reset_abort(hns);
4303         hw->adapter_state = HNS3_NIC_CLOSED;
4304
4305         hns3_configure_all_mc_mac_addr(hns, true);
4306         hns3_remove_all_vlan_table(hns);
4307         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4308         hns3_uninit_pf(eth_dev);
4309         hns3_free_all_queues(eth_dev);
4310         rte_free(hw->reset.wait_data);
4311         rte_free(eth_dev->process_private);
4312         eth_dev->process_private = NULL;
4313         hns3_mp_uninit_primary();
4314         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4315 }
4316
4317 static int
4318 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4319 {
4320         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4321         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4322
4323         fc_conf->pause_time = pf->pause_time;
4324
4325         /* return fc current mode */
4326         switch (hw->current_mode) {
4327         case HNS3_FC_FULL:
4328                 fc_conf->mode = RTE_FC_FULL;
4329                 break;
4330         case HNS3_FC_TX_PAUSE:
4331                 fc_conf->mode = RTE_FC_TX_PAUSE;
4332                 break;
4333         case HNS3_FC_RX_PAUSE:
4334                 fc_conf->mode = RTE_FC_RX_PAUSE;
4335                 break;
4336         case HNS3_FC_NONE:
4337         default:
4338                 fc_conf->mode = RTE_FC_NONE;
4339                 break;
4340         }
4341
4342         return 0;
4343 }
4344
4345 static void
4346 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4347 {
4348         switch (mode) {
4349         case RTE_FC_NONE:
4350                 hw->requested_mode = HNS3_FC_NONE;
4351                 break;
4352         case RTE_FC_RX_PAUSE:
4353                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4354                 break;
4355         case RTE_FC_TX_PAUSE:
4356                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4357                 break;
4358         case RTE_FC_FULL:
4359                 hw->requested_mode = HNS3_FC_FULL;
4360                 break;
4361         default:
4362                 hw->requested_mode = HNS3_FC_NONE;
4363                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4364                           "configured to RTE_FC_NONE", mode);
4365                 break;
4366         }
4367 }
4368
4369 static int
4370 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4371 {
4372         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4373         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4374         int ret;
4375
4376         if (fc_conf->high_water || fc_conf->low_water ||
4377             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4378                 hns3_err(hw, "Unsupported flow control settings specified, "
4379                          "high_water(%u), low_water(%u), send_xon(%u) and "
4380                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4381                          fc_conf->high_water, fc_conf->low_water,
4382                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4383                 return -EINVAL;
4384         }
4385         if (fc_conf->autoneg) {
4386                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4387                 return -EINVAL;
4388         }
4389         if (!fc_conf->pause_time) {
4390                 hns3_err(hw, "Invalid pause time %d setting.",
4391                          fc_conf->pause_time);
4392                 return -EINVAL;
4393         }
4394
4395         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4396             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4397                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4398                          "current_fc_status = %d", hw->current_fc_status);
4399                 return -EOPNOTSUPP;
4400         }
4401
4402         hns3_get_fc_mode(hw, fc_conf->mode);
4403         if (hw->requested_mode == hw->current_mode &&
4404             pf->pause_time == fc_conf->pause_time)
4405                 return 0;
4406
4407         rte_spinlock_lock(&hw->lock);
4408         ret = hns3_fc_enable(dev, fc_conf);
4409         rte_spinlock_unlock(&hw->lock);
4410
4411         return ret;
4412 }
4413
4414 static int
4415 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4416                             struct rte_eth_pfc_conf *pfc_conf)
4417 {
4418         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4419         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4420         uint8_t priority;
4421         int ret;
4422
4423         if (!hns3_dev_dcb_supported(hw)) {
4424                 hns3_err(hw, "This port does not support dcb configurations.");
4425                 return -EOPNOTSUPP;
4426         }
4427
4428         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4429             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4430                 hns3_err(hw, "Unsupported flow control settings specified, "
4431                          "high_water(%u), low_water(%u), send_xon(%u) and "
4432                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4433                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4434                          pfc_conf->fc.send_xon,
4435                          pfc_conf->fc.mac_ctrl_frame_fwd);
4436                 return -EINVAL;
4437         }
4438         if (pfc_conf->fc.autoneg) {
4439                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4440                 return -EINVAL;
4441         }
4442         if (pfc_conf->fc.pause_time == 0) {
4443                 hns3_err(hw, "Invalid pause time %d setting.",
4444                          pfc_conf->fc.pause_time);
4445                 return -EINVAL;
4446         }
4447
4448         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4449             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4450                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4451                              "current_fc_status = %d", hw->current_fc_status);
4452                 return -EOPNOTSUPP;
4453         }
4454
4455         priority = pfc_conf->priority;
4456         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4457         if (hw->dcb_info.pfc_en & BIT(priority) &&
4458             hw->requested_mode == hw->current_mode &&
4459             pfc_conf->fc.pause_time == pf->pause_time)
4460                 return 0;
4461
4462         rte_spinlock_lock(&hw->lock);
4463         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4464         rte_spinlock_unlock(&hw->lock);
4465
4466         return ret;
4467 }
4468
4469 static int
4470 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4471 {
4472         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4474         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4475         int i;
4476
4477         rte_spinlock_lock(&hw->lock);
4478         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4479                 dcb_info->nb_tcs = pf->local_max_tc;
4480         else
4481                 dcb_info->nb_tcs = 1;
4482
4483         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4484                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4485         for (i = 0; i < dcb_info->nb_tcs; i++)
4486                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4487
4488         for (i = 0; i < hw->num_tc; i++) {
4489                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4490                 dcb_info->tc_queue.tc_txq[0][i].base =
4491                                                 hw->tc_queue[i].tqp_offset;
4492                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4493                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4494                                                 hw->tc_queue[i].tqp_count;
4495         }
4496         rte_spinlock_unlock(&hw->lock);
4497
4498         return 0;
4499 }
4500
4501 static int
4502 hns3_reinit_dev(struct hns3_adapter *hns)
4503 {
4504         struct hns3_hw *hw = &hns->hw;
4505         int ret;
4506
4507         ret = hns3_cmd_init(hw);
4508         if (ret) {
4509                 hns3_err(hw, "Failed to init cmd: %d", ret);
4510                 return ret;
4511         }
4512
4513         ret = hns3_reset_all_queues(hns);
4514         if (ret) {
4515                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4516                 goto err_init;
4517         }
4518
4519         ret = hns3_init_hardware(hns);
4520         if (ret) {
4521                 hns3_err(hw, "Failed to init hardware: %d", ret);
4522                 goto err_init;
4523         }
4524
4525         ret = hns3_enable_hw_error_intr(hns, true);
4526         if (ret) {
4527                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4528                              ret);
4529                 goto err_mac_init;
4530         }
4531         hns3_info(hw, "Reset done, driver initialization finished.");
4532
4533         return 0;
4534
4535 err_mac_init:
4536         hns3_uninit_umv_space(hw);
4537 err_init:
4538         hns3_cmd_uninit(hw);
4539
4540         return ret;
4541 }
4542
4543 static bool
4544 is_pf_reset_done(struct hns3_hw *hw)
4545 {
4546         uint32_t val, reg, reg_bit;
4547
4548         switch (hw->reset.level) {
4549         case HNS3_IMP_RESET:
4550                 reg = HNS3_GLOBAL_RESET_REG;
4551                 reg_bit = HNS3_IMP_RESET_BIT;
4552                 break;
4553         case HNS3_GLOBAL_RESET:
4554                 reg = HNS3_GLOBAL_RESET_REG;
4555                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4556                 break;
4557         case HNS3_FUNC_RESET:
4558                 reg = HNS3_FUN_RST_ING;
4559                 reg_bit = HNS3_FUN_RST_ING_B;
4560                 break;
4561         case HNS3_FLR_RESET:
4562         default:
4563                 hns3_err(hw, "Wait for unsupported reset level: %d",
4564                          hw->reset.level);
4565                 return true;
4566         }
4567         val = hns3_read_dev(hw, reg);
4568         if (hns3_get_bit(val, reg_bit))
4569                 return false;
4570         else
4571                 return true;
4572 }
4573
4574 bool
4575 hns3_is_reset_pending(struct hns3_adapter *hns)
4576 {
4577         struct hns3_hw *hw = &hns->hw;
4578         enum hns3_reset_level reset;
4579
4580         hns3_check_event_cause(hns, NULL);
4581         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4582         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4583                 hns3_warn(hw, "High level reset %d is pending", reset);
4584                 return true;
4585         }
4586         reset = hns3_get_reset_level(hns, &hw->reset.request);
4587         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4588                 hns3_warn(hw, "High level reset %d is request", reset);
4589                 return true;
4590         }
4591         return false;
4592 }
4593
4594 static int
4595 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4596 {
4597         struct hns3_hw *hw = &hns->hw;
4598         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4599         struct timeval tv;
4600
4601         if (wait_data->result == HNS3_WAIT_SUCCESS)
4602                 return 0;
4603         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4604                 gettimeofday(&tv, NULL);
4605                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4606                           tv.tv_sec, tv.tv_usec);
4607                 return -ETIME;
4608         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4609                 return -EAGAIN;
4610
4611         wait_data->hns = hns;
4612         wait_data->check_completion = is_pf_reset_done;
4613         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4614                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4615         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4616         wait_data->count = HNS3_RESET_WAIT_CNT;
4617         wait_data->result = HNS3_WAIT_REQUEST;
4618         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4619         return -EAGAIN;
4620 }
4621
4622 static int
4623 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4624 {
4625         struct hns3_cmd_desc desc;
4626         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4627
4628         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4629         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4630         req->fun_reset_vfid = func_id;
4631
4632         return hns3_cmd_send(hw, &desc, 1);
4633 }
4634
4635 static int
4636 hns3_imp_reset_cmd(struct hns3_hw *hw)
4637 {
4638         struct hns3_cmd_desc desc;
4639
4640         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4641         desc.data[0] = 0xeedd;
4642
4643         return hns3_cmd_send(hw, &desc, 1);
4644 }
4645
4646 static void
4647 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4648 {
4649         struct hns3_hw *hw = &hns->hw;
4650         struct timeval tv;
4651         uint32_t val;
4652
4653         gettimeofday(&tv, NULL);
4654         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4655             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4656                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4657                           tv.tv_sec, tv.tv_usec);
4658                 return;
4659         }
4660
4661         switch (reset_level) {
4662         case HNS3_IMP_RESET:
4663                 hns3_imp_reset_cmd(hw);
4664                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4665                           tv.tv_sec, tv.tv_usec);
4666                 break;
4667         case HNS3_GLOBAL_RESET:
4668                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4669                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4670                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4671                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4672                           tv.tv_sec, tv.tv_usec);
4673                 break;
4674         case HNS3_FUNC_RESET:
4675                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4676                           tv.tv_sec, tv.tv_usec);
4677                 /* schedule again to check later */
4678                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4679                 hns3_schedule_reset(hns);
4680                 break;
4681         default:
4682                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4683                 return;
4684         }
4685         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4686 }
4687
4688 static enum hns3_reset_level
4689 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4690 {
4691         struct hns3_hw *hw = &hns->hw;
4692         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4693
4694         /* Return the highest priority reset level amongst all */
4695         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4696                 reset_level = HNS3_IMP_RESET;
4697         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4698                 reset_level = HNS3_GLOBAL_RESET;
4699         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4700                 reset_level = HNS3_FUNC_RESET;
4701         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4702                 reset_level = HNS3_FLR_RESET;
4703
4704         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4705                 return HNS3_NONE_RESET;
4706
4707         return reset_level;
4708 }
4709
4710 static int
4711 hns3_prepare_reset(struct hns3_adapter *hns)
4712 {
4713         struct hns3_hw *hw = &hns->hw;
4714         uint32_t reg_val;
4715         int ret;
4716
4717         switch (hw->reset.level) {
4718         case HNS3_FUNC_RESET:
4719                 ret = hns3_func_reset_cmd(hw, 0);
4720                 if (ret)
4721                         return ret;
4722
4723                 /*
4724                  * After performaning pf reset, it is not necessary to do the
4725                  * mailbox handling or send any command to firmware, because
4726                  * any mailbox handling or command to firmware is only valid
4727                  * after hns3_cmd_init is called.
4728                  */
4729                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4730                 hw->reset.stats.request_cnt++;
4731                 break;
4732         case HNS3_IMP_RESET:
4733                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4734                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4735                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4736                 break;
4737         default:
4738                 break;
4739         }
4740         return 0;
4741 }
4742
4743 static int
4744 hns3_set_rst_done(struct hns3_hw *hw)
4745 {
4746         struct hns3_pf_rst_done_cmd *req;
4747         struct hns3_cmd_desc desc;
4748
4749         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4750         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4751         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4752         return hns3_cmd_send(hw, &desc, 1);
4753 }
4754
4755 static int
4756 hns3_stop_service(struct hns3_adapter *hns)
4757 {
4758         struct hns3_hw *hw = &hns->hw;
4759         struct rte_eth_dev *eth_dev;
4760
4761         eth_dev = &rte_eth_devices[hw->data->port_id];
4762         if (hw->adapter_state == HNS3_NIC_STARTED)
4763                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4764         hw->mac.link_status = ETH_LINK_DOWN;
4765
4766         hns3_set_rxtx_function(eth_dev);
4767         rte_wmb();
4768         /* Disable datapath on secondary process. */
4769         hns3_mp_req_stop_rxtx(eth_dev);
4770         rte_delay_ms(hw->tqps_num);
4771
4772         rte_spinlock_lock(&hw->lock);
4773         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4774             hw->adapter_state == HNS3_NIC_STOPPING) {
4775                 hns3_do_stop(hns);
4776                 hw->reset.mbuf_deferred_free = true;
4777         } else
4778                 hw->reset.mbuf_deferred_free = false;
4779
4780         /*
4781          * It is cumbersome for hardware to pick-and-choose entries for deletion
4782          * from table space. Hence, for function reset software intervention is
4783          * required to delete the entries
4784          */
4785         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4786                 hns3_configure_all_mc_mac_addr(hns, true);
4787         rte_spinlock_unlock(&hw->lock);
4788
4789         return 0;
4790 }
4791
4792 static int
4793 hns3_start_service(struct hns3_adapter *hns)
4794 {
4795         struct hns3_hw *hw = &hns->hw;
4796         struct rte_eth_dev *eth_dev;
4797
4798         if (hw->reset.level == HNS3_IMP_RESET ||
4799             hw->reset.level == HNS3_GLOBAL_RESET)
4800                 hns3_set_rst_done(hw);
4801         eth_dev = &rte_eth_devices[hw->data->port_id];
4802         hns3_set_rxtx_function(eth_dev);
4803         hns3_mp_req_start_rxtx(eth_dev);
4804         if (hw->adapter_state == HNS3_NIC_STARTED)
4805                 hns3_service_handler(eth_dev);
4806
4807         return 0;
4808 }
4809
4810 static int
4811 hns3_restore_conf(struct hns3_adapter *hns)
4812 {
4813         struct hns3_hw *hw = &hns->hw;
4814         int ret;
4815
4816         ret = hns3_configure_all_mac_addr(hns, false);
4817         if (ret)
4818                 return ret;
4819
4820         ret = hns3_configure_all_mc_mac_addr(hns, false);
4821         if (ret)
4822                 goto err_mc_mac;
4823
4824         ret = hns3_dev_promisc_restore(hns);
4825         if (ret)
4826                 goto err_promisc;
4827
4828         ret = hns3_restore_vlan_table(hns);
4829         if (ret)
4830                 goto err_promisc;
4831
4832         ret = hns3_restore_vlan_conf(hns);
4833         if (ret)
4834                 goto err_promisc;
4835
4836         ret = hns3_restore_all_fdir_filter(hns);
4837         if (ret)
4838                 goto err_promisc;
4839
4840         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4841                 ret = hns3_do_start(hns, false);
4842                 if (ret)
4843                         goto err_promisc;
4844                 hns3_info(hw, "hns3 dev restart successful!");
4845         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4846                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4847         return 0;
4848
4849 err_promisc:
4850         hns3_configure_all_mc_mac_addr(hns, true);
4851 err_mc_mac:
4852         hns3_configure_all_mac_addr(hns, true);
4853         return ret;
4854 }
4855
4856 static void
4857 hns3_reset_service(void *param)
4858 {
4859         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4860         struct hns3_hw *hw = &hns->hw;
4861         enum hns3_reset_level reset_level;
4862         struct timeval tv_delta;
4863         struct timeval tv_start;
4864         struct timeval tv;
4865         uint64_t msec;
4866         int ret;
4867
4868         /*
4869          * The interrupt is not triggered within the delay time.
4870          * The interrupt may have been lost. It is necessary to handle
4871          * the interrupt to recover from the error.
4872          */
4873         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4874                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4875                 hns3_err(hw, "Handling interrupts in delayed tasks");
4876                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4877                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4878                 if (reset_level == HNS3_NONE_RESET) {
4879                         hns3_err(hw, "No reset level is set, try IMP reset");
4880                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4881                 }
4882         }
4883         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4884
4885         /*
4886          * Check if there is any ongoing reset in the hardware. This status can
4887          * be checked from reset_pending. If there is then, we need to wait for
4888          * hardware to complete reset.
4889          *    a. If we are able to figure out in reasonable time that hardware
4890          *       has fully resetted then, we can proceed with driver, client
4891          *       reset.
4892          *    b. else, we can come back later to check this status so re-sched
4893          *       now.
4894          */
4895         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4896         if (reset_level != HNS3_NONE_RESET) {
4897                 gettimeofday(&tv_start, NULL);
4898                 ret = hns3_reset_process(hns, reset_level);
4899                 gettimeofday(&tv, NULL);
4900                 timersub(&tv, &tv_start, &tv_delta);
4901                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4902                        tv_delta.tv_usec / USEC_PER_MSEC;
4903                 if (msec > HNS3_RESET_PROCESS_MS)
4904                         hns3_err(hw, "%d handle long time delta %" PRIx64
4905                                      " ms time=%ld.%.6ld",
4906                                  hw->reset.level, msec,
4907                                  tv.tv_sec, tv.tv_usec);
4908                 if (ret == -EAGAIN)
4909                         return;
4910         }
4911
4912         /* Check if we got any *new* reset requests to be honored */
4913         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4914         if (reset_level != HNS3_NONE_RESET)
4915                 hns3_msix_process(hns, reset_level);
4916 }
4917
4918 static const struct eth_dev_ops hns3_eth_dev_ops = {
4919         .dev_start          = hns3_dev_start,
4920         .dev_stop           = hns3_dev_stop,
4921         .dev_close          = hns3_dev_close,
4922         .promiscuous_enable = hns3_dev_promiscuous_enable,
4923         .promiscuous_disable = hns3_dev_promiscuous_disable,
4924         .allmulticast_enable  = hns3_dev_allmulticast_enable,
4925         .allmulticast_disable = hns3_dev_allmulticast_disable,
4926         .mtu_set            = hns3_dev_mtu_set,
4927         .stats_get          = hns3_stats_get,
4928         .stats_reset        = hns3_stats_reset,
4929         .xstats_get         = hns3_dev_xstats_get,
4930         .xstats_get_names   = hns3_dev_xstats_get_names,
4931         .xstats_reset       = hns3_dev_xstats_reset,
4932         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
4933         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4934         .dev_infos_get          = hns3_dev_infos_get,
4935         .fw_version_get         = hns3_fw_version_get,
4936         .rx_queue_setup         = hns3_rx_queue_setup,
4937         .tx_queue_setup         = hns3_tx_queue_setup,
4938         .rx_queue_release       = hns3_dev_rx_queue_release,
4939         .tx_queue_release       = hns3_dev_tx_queue_release,
4940         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
4941         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
4942         .dev_configure          = hns3_dev_configure,
4943         .flow_ctrl_get          = hns3_flow_ctrl_get,
4944         .flow_ctrl_set          = hns3_flow_ctrl_set,
4945         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4946         .mac_addr_add           = hns3_add_mac_addr,
4947         .mac_addr_remove        = hns3_remove_mac_addr,
4948         .mac_addr_set           = hns3_set_default_mac_addr,
4949         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
4950         .link_update            = hns3_dev_link_update,
4951         .rss_hash_update        = hns3_dev_rss_hash_update,
4952         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
4953         .reta_update            = hns3_dev_rss_reta_update,
4954         .reta_query             = hns3_dev_rss_reta_query,
4955         .filter_ctrl            = hns3_dev_filter_ctrl,
4956         .vlan_filter_set        = hns3_vlan_filter_set,
4957         .vlan_tpid_set          = hns3_vlan_tpid_set,
4958         .vlan_offload_set       = hns3_vlan_offload_set,
4959         .vlan_pvid_set          = hns3_vlan_pvid_set,
4960         .get_reg                = hns3_get_regs,
4961         .get_dcb_info           = hns3_get_dcb_info,
4962         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4963 };
4964
4965 static const struct hns3_reset_ops hns3_reset_ops = {
4966         .reset_service       = hns3_reset_service,
4967         .stop_service        = hns3_stop_service,
4968         .prepare_reset       = hns3_prepare_reset,
4969         .wait_hardware_ready = hns3_wait_hardware_ready,
4970         .reinit_dev          = hns3_reinit_dev,
4971         .restore_conf        = hns3_restore_conf,
4972         .start_service       = hns3_start_service,
4973 };
4974
4975 static int
4976 hns3_dev_init(struct rte_eth_dev *eth_dev)
4977 {
4978         struct rte_device *dev = eth_dev->device;
4979         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4980         struct hns3_adapter *hns = eth_dev->data->dev_private;
4981         struct hns3_hw *hw = &hns->hw;
4982         uint16_t device_id = pci_dev->id.device_id;
4983         int ret;
4984
4985         PMD_INIT_FUNC_TRACE();
4986         eth_dev->process_private = (struct hns3_process_private *)
4987             rte_zmalloc_socket("hns3_filter_list",
4988                                sizeof(struct hns3_process_private),
4989                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4990         if (eth_dev->process_private == NULL) {
4991                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4992                 return -ENOMEM;
4993         }
4994         /* initialize flow filter lists */
4995         hns3_filterlist_init(eth_dev);
4996
4997         hns3_set_rxtx_function(eth_dev);
4998         eth_dev->dev_ops = &hns3_eth_dev_ops;
4999         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5000                 hns3_mp_init_secondary();
5001                 hw->secondary_cnt++;
5002                 return 0;
5003         }
5004
5005         hns3_mp_init_primary();
5006         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5007
5008         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5009             device_id == HNS3_DEV_ID_50GE_RDMA ||
5010             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5011                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5012
5013         hns->is_vf = false;
5014         hw->data = eth_dev->data;
5015
5016         /*
5017          * Set default max packet size according to the mtu
5018          * default vale in DPDK frame.
5019          */
5020         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5021
5022         ret = hns3_reset_init(hw);
5023         if (ret)
5024                 goto err_init_reset;
5025         hw->reset.ops = &hns3_reset_ops;
5026
5027         ret = hns3_init_pf(eth_dev);
5028         if (ret) {
5029                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5030                 goto err_init_pf;
5031         }
5032
5033         /* Allocate memory for storing MAC addresses */
5034         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5035                                                sizeof(struct rte_ether_addr) *
5036                                                HNS3_UC_MACADDR_NUM, 0);
5037         if (eth_dev->data->mac_addrs == NULL) {
5038                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5039                              "to store MAC addresses",
5040                              sizeof(struct rte_ether_addr) *
5041                              HNS3_UC_MACADDR_NUM);
5042                 ret = -ENOMEM;
5043                 goto err_rte_zmalloc;
5044         }
5045
5046         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5047                             &eth_dev->data->mac_addrs[0]);
5048
5049         hw->adapter_state = HNS3_NIC_INITIALIZED;
5050         /*
5051          * Pass the information to the rte_eth_dev_close() that it should also
5052          * release the private port resources.
5053          */
5054         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5055
5056         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5057                 hns3_err(hw, "Reschedule reset service after dev_init");
5058                 hns3_schedule_reset(hns);
5059         } else {
5060                 /* IMP will wait ready flag before reset */
5061                 hns3_notify_reset_ready(hw, false);
5062         }
5063
5064         hns3_info(hw, "hns3 dev initialization successful!");
5065         return 0;
5066
5067 err_rte_zmalloc:
5068         hns3_uninit_pf(eth_dev);
5069
5070 err_init_pf:
5071         rte_free(hw->reset.wait_data);
5072 err_init_reset:
5073         eth_dev->dev_ops = NULL;
5074         eth_dev->rx_pkt_burst = NULL;
5075         eth_dev->tx_pkt_burst = NULL;
5076         eth_dev->tx_pkt_prepare = NULL;
5077         rte_free(eth_dev->process_private);
5078         eth_dev->process_private = NULL;
5079         return ret;
5080 }
5081
5082 static int
5083 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5084 {
5085         struct hns3_adapter *hns = eth_dev->data->dev_private;
5086         struct hns3_hw *hw = &hns->hw;
5087
5088         PMD_INIT_FUNC_TRACE();
5089
5090         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5091                 return -EPERM;
5092
5093         eth_dev->dev_ops = NULL;
5094         eth_dev->rx_pkt_burst = NULL;
5095         eth_dev->tx_pkt_burst = NULL;
5096         eth_dev->tx_pkt_prepare = NULL;
5097         if (hw->adapter_state < HNS3_NIC_CLOSING)
5098                 hns3_dev_close(eth_dev);
5099
5100         hw->adapter_state = HNS3_NIC_REMOVED;
5101         return 0;
5102 }
5103
5104 static int
5105 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5106                    struct rte_pci_device *pci_dev)
5107 {
5108         return rte_eth_dev_pci_generic_probe(pci_dev,
5109                                              sizeof(struct hns3_adapter),
5110                                              hns3_dev_init);
5111 }
5112
5113 static int
5114 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5115 {
5116         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5117 }
5118
5119 static const struct rte_pci_id pci_id_hns3_map[] = {
5120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5125         { .vendor_id = 0, /* sentinel */ },
5126 };
5127
5128 static struct rte_pci_driver rte_hns3_pmd = {
5129         .id_table = pci_id_hns3_map,
5130         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5131         .probe = eth_hns3_pci_probe,
5132         .remove = eth_hns3_pci_remove,
5133 };
5134
5135 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5136 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5137 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5138
5139 RTE_INIT(hns3_init_log)
5140 {
5141         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5142         if (hns3_logtype_init >= 0)
5143                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5144         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5145         if (hns3_logtype_driver >= 0)
5146                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5147 }