drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_rxtx.h"
  27 #include "hns3_regs.h"
  28 #include "hns3_dcb.h"
  29
  30 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  31 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  32
  33 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  34 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  35 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  36 #define HNS3_INVLID_PVID                0xFFFF
  37
  38 #define HNS3_FILTER_TYPE_VF             0
  39 #define HNS3_FILTER_TYPE_PORT           1
  40 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  41 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  42 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  43 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  44 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  45 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  46                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  47 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  48                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  49
  50 int hns3_logtype_init;
  51 int hns3_logtype_driver;
  52
  53 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  54                                     int on);
  55
  56 static int
  57 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
  58 {
  59 #define HNS3_VLAN_OFFSET_160            160
  60         struct hns3_vlan_filter_pf_cfg_cmd *req;
  61         struct hns3_hw *hw = &hns->hw;
  62         uint8_t vlan_offset_byte_val;
  63         struct hns3_cmd_desc desc;
  64         uint8_t vlan_offset_byte;
  65         uint8_t vlan_offset_160;
  66         int ret;
  67
  68         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
  69
  70         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
  71         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
  72         vlan_offset_byte_val = 1 << (vlan_id % 8);
  73
  74         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
  75         req->vlan_offset = vlan_offset_160;
  76         req->vlan_cfg = on ? 0 : 1;
  77         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
  78
  79         ret = hns3_cmd_send(hw, &desc, 1);
  80         if (ret)
  81                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
  82                          vlan_id, ret);
  83
  84         return ret;
  85 }
  86
  87 static void
  88 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
  89 {
  90         struct hns3_user_vlan_table *vlan_entry;
  91         struct hns3_pf *pf = &hns->pf;
  92
  93         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
  94                 if (vlan_entry->vlan_id == vlan_id) {
  95                         if (vlan_entry->hd_tbl_status)
  96                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
  97                         LIST_REMOVE(vlan_entry, next);
  98                         rte_free(vlan_entry);
  99                         break;
 100                 }
 101         }
 102 }
 103
 104 static void
 105 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 106                         bool writen_to_tbl)
 107 {
 108         struct hns3_user_vlan_table *vlan_entry;
 109         struct hns3_hw *hw = &hns->hw;
 110         struct hns3_pf *pf = &hns->pf;
 111
 112         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 113         if (vlan_entry == NULL) {
 114                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 115                 return;
 116         }
 117
 118         vlan_entry->hd_tbl_status = writen_to_tbl;
 119         vlan_entry->vlan_id = vlan_id;
 120
 121         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 122 }
 123
 124 static int
 125 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 126 {
 127         struct hns3_pf *pf = &hns->pf;
 128         bool writen_to_tbl = false;
 129         int ret = 0;
 130
 131         /*
 132          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 133          * for normal packet, deleting vlan id 0 is not allowed.
 134          */
 135         if (on == 0 && vlan_id == 0)
 136                 return 0;
 137
 138         /*
 139          * When port base vlan enabled, we use port base vlan as the vlan
 140          * filter condition. In this case, we don't update vlan filter table
 141          * when user add new vlan or remove exist vlan, just update the
 142          * vlan list. The vlan id in vlan list will be writen in vlan filter
 143          * table until port base vlan disabled
 144          */
 145         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 146                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 147                 writen_to_tbl = true;
 148         }
 149
 150         if (ret == 0 && vlan_id) {
 151                 if (on)
 152                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 153                 else
 154                         hns3_rm_dev_vlan_table(hns, vlan_id);
 155         }
 156         return ret;
 157 }
 158
 159 static int
 160 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 161 {
 162         struct hns3_adapter *hns = dev->data->dev_private;
 163         struct hns3_hw *hw = &hns->hw;
 164         int ret;
 165
 166         rte_spinlock_lock(&hw->lock);
 167         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 168         rte_spinlock_unlock(&hw->lock);
 169         return ret;
 170 }
 171
 172 static int
 173 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 174                          uint16_t tpid)
 175 {
 176         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 177         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 178         struct hns3_hw *hw = &hns->hw;
 179         struct hns3_cmd_desc desc;
 180         int ret;
 181
 182         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 183              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 184                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 185                 return -EINVAL;
 186         }
 187
 188         if (tpid != RTE_ETHER_TYPE_VLAN) {
 189                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 190                 return -EINVAL;
 191         }
 192
 193         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 194         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 195
 196         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 197                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 198                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 199         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 200                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 201                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 202                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 203                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 204         }
 205
 206         ret = hns3_cmd_send(hw, &desc, 1);
 207         if (ret) {
 208                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 209                          ret);
 210                 return ret;
 211         }
 212
 213         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 214
 215         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 216         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 217         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 218
 219         ret = hns3_cmd_send(hw, &desc, 1);
 220         if (ret)
 221                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 222                          ret);
 223         return ret;
 224 }
 225
 226 static int
 227 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 228                    uint16_t tpid)
 229 {
 230         struct hns3_adapter *hns = dev->data->dev_private;
 231         struct hns3_hw *hw = &hns->hw;
 232         int ret;
 233
 234         rte_spinlock_lock(&hw->lock);
 235         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 236         rte_spinlock_unlock(&hw->lock);
 237         return ret;
 238 }
 239
 240 static int
 241 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 242                              struct hns3_rx_vtag_cfg *vcfg)
 243 {
 244         struct hns3_vport_vtag_rx_cfg_cmd *req;
 245         struct hns3_hw *hw = &hns->hw;
 246         struct hns3_cmd_desc desc;
 247         uint16_t vport_id;
 248         uint8_t bitmap;
 249         int ret;
 250
 251         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 252
 253         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 254         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 255                      vcfg->strip_tag1_en ? 1 : 0);
 256         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 257                      vcfg->strip_tag2_en ? 1 : 0);
 258         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 259                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 260         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 261                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 262
 263         /*
 264          * In current version VF is not supported when PF is driven by DPDK
 265          * driver, the PF-related vf_id is 0, just need to configure parameters
 266          * for vport_id 0.
 267          */
 268         vport_id = 0;
 269         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 270         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 271         req->vf_bitmap[req->vf_offset] = bitmap;
 272
 273         ret = hns3_cmd_send(hw, &desc, 1);
 274         if (ret)
 275                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 276         return ret;
 277 }
 278
 279 static void
 280 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 281                            struct hns3_rx_vtag_cfg *vcfg)
 282 {
 283         struct hns3_pf *pf = &hns->pf;
 284         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 285 }
 286
 287 static void
 288 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 289                            struct hns3_tx_vtag_cfg *vcfg)
 290 {
 291         struct hns3_pf *pf = &hns->pf;
 292         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 293 }
 294
 295 static int
 296 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 297 {
 298         struct hns3_rx_vtag_cfg rxvlan_cfg;
 299         struct hns3_pf *pf = &hns->pf;
 300         struct hns3_hw *hw = &hns->hw;
 301         int ret;
 302
 303         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 304                 rxvlan_cfg.strip_tag1_en = false;
 305                 rxvlan_cfg.strip_tag2_en = enable;
 306         } else {
 307                 rxvlan_cfg.strip_tag1_en = enable;
 308                 rxvlan_cfg.strip_tag2_en = true;
 309         }
 310
 311         rxvlan_cfg.vlan1_vlan_prionly = false;
 312         rxvlan_cfg.vlan2_vlan_prionly = false;
 313         rxvlan_cfg.rx_vlan_offload_en = enable;
 314
 315         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 316         if (ret) {
 317                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 318                 return ret;
 319         }
 320
 321         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 322
 323         return ret;
 324 }
 325
 326 static int
 327 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 328                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 329 {
 330         struct hns3_vlan_filter_ctrl_cmd *req;
 331         struct hns3_cmd_desc desc;
 332         int ret;
 333
 334         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 335
 336         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 337         req->vlan_type = vlan_type;
 338         req->vlan_fe = filter_en ? fe_type : 0;
 339         req->vf_id = vf_id;
 340
 341         ret = hns3_cmd_send(hw, &desc, 1);
 342         if (ret)
 343                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 344
 345         return ret;
 346 }
 347
 348 static int
 349 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 350 {
 351         struct hns3_hw *hw = &hns->hw;
 352         int ret;
 353
 354         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 355                                         HNS3_FILTER_FE_EGRESS, false, 0);
 356         if (ret) {
 357                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 358                 return ret;
 359         }
 360
 361         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 362                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 363         if (ret)
 364                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 365
 366         return ret;
 367 }
 368
 369 static int
 370 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 371 {
 372         struct hns3_adapter *hns = dev->data->dev_private;
 373         struct hns3_hw *hw = &hns->hw;
 374         struct rte_eth_rxmode *rxmode;
 375         unsigned int tmp_mask;
 376         bool enable;
 377         int ret = 0;
 378
 379         rte_spinlock_lock(&hw->lock);
 380         rxmode = &dev->data->dev_conf.rxmode;
 381         tmp_mask = (unsigned int)mask;
 382         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 383                 /* Enable or disable VLAN stripping */
 384                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 385                     true : false;
 386
 387                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 388                 if (ret) {
 389                         rte_spinlock_unlock(&hw->lock);
 390                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 391                         return ret;
 392                 }
 393         }
 394
 395         rte_spinlock_unlock(&hw->lock);
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 402                              struct hns3_tx_vtag_cfg *vcfg)
 403 {
 404         struct hns3_vport_vtag_tx_cfg_cmd *req;
 405         struct hns3_cmd_desc desc;
 406         struct hns3_hw *hw = &hns->hw;
 407         uint16_t vport_id;
 408         uint8_t bitmap;
 409         int ret;
 410
 411         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 412
 413         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 414         req->def_vlan_tag1 = vcfg->default_tag1;
 415         req->def_vlan_tag2 = vcfg->default_tag2;
 416         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 417                      vcfg->accept_tag1 ? 1 : 0);
 418         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 419                      vcfg->accept_untag1 ? 1 : 0);
 420         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 421                      vcfg->accept_tag2 ? 1 : 0);
 422         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 423                      vcfg->accept_untag2 ? 1 : 0);
 424         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 425                      vcfg->insert_tag1_en ? 1 : 0);
 426         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 427                      vcfg->insert_tag2_en ? 1 : 0);
 428         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 429
 430         /*
 431          * In current version VF is not supported when PF is driven by DPDK
 432          * driver, the PF-related vf_id is 0, just need to configure parameters
 433          * for vport_id 0.
 434          */
 435         vport_id = 0;
 436         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 437         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 438         req->vf_bitmap[req->vf_offset] = bitmap;
 439
 440         ret = hns3_cmd_send(hw, &desc, 1);
 441         if (ret)
 442                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 443
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 449                      uint16_t pvid)
 450 {
 451         struct hns3_hw *hw = &hns->hw;
 452         struct hns3_tx_vtag_cfg txvlan_cfg;
 453         int ret;
 454
 455         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 456                 txvlan_cfg.accept_tag1 = true;
 457                 txvlan_cfg.insert_tag1_en = false;
 458                 txvlan_cfg.default_tag1 = 0;
 459         } else {
 460                 txvlan_cfg.accept_tag1 = false;
 461                 txvlan_cfg.insert_tag1_en = true;
 462                 txvlan_cfg.default_tag1 = pvid;
 463         }
 464
 465         txvlan_cfg.accept_untag1 = true;
 466         txvlan_cfg.accept_tag2 = true;
 467         txvlan_cfg.accept_untag2 = true;
 468         txvlan_cfg.insert_tag2_en = false;
 469         txvlan_cfg.default_tag2 = 0;
 470
 471         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 472         if (ret) {
 473                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 474                          ret);
 475                 return ret;
 476         }
 477
 478         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 479         return ret;
 480 }
 481
 482 static void
 483 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 484 {
 485         struct hns3_pf *pf = &hns->pf;
 486
 487         pf->port_base_vlan_cfg.state = on ?
 488             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 489
 490         pf->port_base_vlan_cfg.pvid = pvid;
 491 }
 492
 493 static void
 494 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 495 {
 496         struct hns3_user_vlan_table *vlan_entry;
 497         struct hns3_pf *pf = &hns->pf;
 498
 499         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 500                 if (vlan_entry->hd_tbl_status)
 501                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 502
 503                 vlan_entry->hd_tbl_status = false;
 504         }
 505
 506         if (is_del_list) {
 507                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 508                 while (vlan_entry) {
 509                         LIST_REMOVE(vlan_entry, next);
 510                         rte_free(vlan_entry);
 511                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 512                 }
 513         }
 514 }
 515
 516 static void
 517 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 518 {
 519         struct hns3_user_vlan_table *vlan_entry;
 520         struct hns3_pf *pf = &hns->pf;
 521
 522         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 523                 if (!vlan_entry->hd_tbl_status)
 524                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 525
 526                 vlan_entry->hd_tbl_status = true;
 527         }
 528 }
 529
 530 static int
 531 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 532                                 uint16_t port_base_vlan_state,
 533                                 uint16_t new_pvid, uint16_t old_pvid)
 534 {
 535         struct hns3_pf *pf = &hns->pf;
 536         struct hns3_hw *hw = &hns->hw;
 537         int ret = 0;
 538
 539         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 540                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 541                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 542                         if (ret) {
 543                                 hns3_err(hw,
 544                                          "Failed to clear clear old pvid filter, ret =%d",
 545                                          ret);
 546                                 return ret;
 547                         }
 548                 }
 549
 550                 hns3_rm_all_vlan_table(hns, false);
 551                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 552         }
 553
 554         if (new_pvid != 0) {
 555                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 556                 if (ret) {
 557                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 558                                  ret);
 559                         return ret;
 560                 }
 561         }
 562
 563         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 564                 hns3_add_all_vlan_table(hns);
 565
 566         return ret;
 567 }
 568
 569 static int
 570 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 571 {
 572         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 573         struct hns3_hw *hw = &hns->hw;
 574         bool rx_strip_en;
 575         int ret;
 576
 577         rx_strip_en = on ? true : false;
 578         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 579         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 580         rx_vlan_cfg.vlan1_vlan_prionly = false;
 581         rx_vlan_cfg.vlan2_vlan_prionly = false;
 582         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 583
 584         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 585         if (ret) {
 586                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 587                 return ret;
 588         }
 589
 590         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 591         return ret;
 592 }
 593
 594 static int
 595 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 596 {
 597         struct hns3_pf *pf = &hns->pf;
 598         struct hns3_hw *hw = &hns->hw;
 599         uint16_t port_base_vlan_state;
 600         uint16_t old_pvid;
 601         int ret;
 602
 603         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 604                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 605                         hns3_warn(hw, "Invalid operation! As current pvid set "
 606                                   "is %u, disable pvid %u is invalid",
 607                                   pf->port_base_vlan_cfg.pvid, pvid);
 608                 return 0;
 609         }
 610
 611         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 612                                     HNS3_PORT_BASE_VLAN_DISABLE;
 613         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 614         if (ret) {
 615                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 616                 return ret;
 617         }
 618
 619         ret = hns3_en_rx_strip_all(hns, on);
 620         if (ret) {
 621                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 622                 return ret;
 623         }
 624
 625         if (pvid == HNS3_INVLID_PVID)
 626                 goto out;
 627         old_pvid = pf->port_base_vlan_cfg.pvid;
 628         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 629                                               old_pvid);
 630         if (ret) {
 631                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 632                          ret);
 633                 return ret;
 634         }
 635
 636 out:
 637         hns3_store_port_base_vlan_info(hns, pvid, on);
 638         return ret;
 639 }
 640
 641 static int
 642 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 643 {
 644         struct hns3_adapter *hns = dev->data->dev_private;
 645         struct hns3_hw *hw = &hns->hw;
 646         int ret;
 647
 648         rte_spinlock_lock(&hw->lock);
 649         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 650         rte_spinlock_unlock(&hw->lock);
 651         return ret;
 652 }
 653
 654 static void
 655 init_port_base_vlan_info(struct hns3_hw *hw)
 656 {
 657         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 658         struct hns3_pf *pf = &hns->pf;
 659
 660         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 661         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 662 }
 663
 664 static int
 665 hns3_default_vlan_config(struct hns3_adapter *hns)
 666 {
 667         struct hns3_hw *hw = &hns->hw;
 668         int ret;
 669
 670         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 671         if (ret)
 672                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 673         return ret;
 674 }
 675
 676 static int
 677 hns3_init_vlan_config(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         int ret;
 681
 682         /*
 683          * This function can be called in the initialization and reset process,
 684          * when in reset process, it means that hardware had been reseted
 685          * successfully and we need to restore the hardware configuration to
 686          * ensure that the hardware configuration remains unchanged before and
 687          * after reset.
 688          */
 689         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 690                 init_port_base_vlan_info(hw);
 691
 692         ret = hns3_enable_vlan_filter(hns, true);
 693         if (ret) {
 694                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 695                 return ret;
 696         }
 697
 698         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 699                                        RTE_ETHER_TYPE_VLAN);
 700         if (ret) {
 701                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 702                 return ret;
 703         }
 704
 705         /*
 706          * When in the reinit dev stage of the reset process, the following
 707          * vlan-related configurations may differ from those at initialization,
 708          * we will restore configurations to hardware in hns3_restore_vlan_table
 709          * and hns3_restore_vlan_conf later.
 710          */
 711         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 712                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 713                 if (ret) {
 714                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 715                         return ret;
 716                 }
 717
 718                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 719                 if (ret) {
 720                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 721                                  ret);
 722                         return ret;
 723                 }
 724         }
 725
 726         return hns3_default_vlan_config(hns);
 727 }
 728
 729 static int
 730 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
 731                 unsigned int tso_mss_max)
 732 {
 733         struct hns3_cfg_tso_status_cmd *req;
 734         struct hns3_cmd_desc desc;
 735         uint16_t tso_mss;
 736
 737         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
 738
 739         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
 740
 741         tso_mss = 0;
 742         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
 743                        tso_mss_min);
 744         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
 745
 746         tso_mss = 0;
 747         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
 748                        tso_mss_max);
 749         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
 750
 751         return hns3_cmd_send(hw, &desc, 1);
 752 }
 753
 754 int
 755 hns3_config_gro(struct hns3_hw *hw, bool en)
 756 {
 757         struct hns3_cfg_gro_status_cmd *req;
 758         struct hns3_cmd_desc desc;
 759         int ret;
 760
 761         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
 762         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
 763
 764         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
 765
 766         ret = hns3_cmd_send(hw, &desc, 1);
 767         if (ret)
 768                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
 769
 770         return ret;
 771 }
 772
 773 static int
 774 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
 775                    uint16_t *allocated_size, bool is_alloc)
 776 {
 777         struct hns3_umv_spc_alc_cmd *req;
 778         struct hns3_cmd_desc desc;
 779         int ret;
 780
 781         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
 782         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
 783         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
 784         req->space_size = rte_cpu_to_le_32(space_size);
 785
 786         ret = hns3_cmd_send(hw, &desc, 1);
 787         if (ret) {
 788                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
 789                              is_alloc ? "allocate" : "free", ret);
 790                 return ret;
 791         }
 792
 793         if (is_alloc && allocated_size)
 794                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 795
 796         return 0;
 797 }
 798
 799 static int
 800 hns3_init_umv_space(struct hns3_hw *hw)
 801 {
 802         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 803         struct hns3_pf *pf = &hns->pf;
 804         uint16_t allocated_size = 0;
 805         int ret;
 806
 807         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 808                                  true);
 809         if (ret)
 810                 return ret;
 811
 812         if (allocated_size < pf->wanted_umv_size)
 813                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 814                              pf->wanted_umv_size, allocated_size);
 815
 816         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 817                                                 pf->wanted_umv_size;
 818         pf->used_umv_size = 0;
 819         return 0;
 820 }
 821
 822 static int
 823 hns3_uninit_umv_space(struct hns3_hw *hw)
 824 {
 825         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 826         struct hns3_pf *pf = &hns->pf;
 827         int ret;
 828
 829         if (pf->max_umv_size == 0)
 830                 return 0;
 831
 832         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 833         if (ret)
 834                 return ret;
 835
 836         pf->max_umv_size = 0;
 837
 838         return 0;
 839 }
 840
 841 static bool
 842 hns3_is_umv_space_full(struct hns3_hw *hw)
 843 {
 844         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 845         struct hns3_pf *pf = &hns->pf;
 846         bool is_full;
 847
 848         is_full = (pf->used_umv_size >= pf->max_umv_size);
 849
 850         return is_full;
 851 }
 852
 853 static void
 854 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 855 {
 856         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 857         struct hns3_pf *pf = &hns->pf;
 858
 859         if (is_free) {
 860                 if (pf->used_umv_size > 0)
 861                         pf->used_umv_size--;
 862         } else
 863                 pf->used_umv_size++;
 864 }
 865
 866 static void
 867 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 868                       const uint8_t *addr, bool is_mc)
 869 {
 870         const unsigned char *mac_addr = addr;
 871         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 872                             ((uint32_t)mac_addr[2] << 16) |
 873                             ((uint32_t)mac_addr[1] << 8) |
 874                             (uint32_t)mac_addr[0];
 875         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 876
 877         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 878         if (is_mc) {
 879                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 880                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 881                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 882         }
 883
 884         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 885         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 886 }
 887
 888 static int
 889 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 890                              uint8_t resp_code,
 891                              enum hns3_mac_vlan_tbl_opcode op)
 892 {
 893         if (cmdq_resp) {
 894                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 895                          cmdq_resp);
 896                 return -EIO;
 897         }
 898
 899         if (op == HNS3_MAC_VLAN_ADD) {
 900                 if (resp_code == 0 || resp_code == 1) {
 901                         return 0;
 902                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 903                         hns3_err(hw, "add mac addr failed for uc_overflow");
 904                         return -ENOSPC;
 905                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 906                         hns3_err(hw, "add mac addr failed for mc_overflow");
 907                         return -ENOSPC;
 908                 }
 909
 910                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 911                          resp_code);
 912                 return -EIO;
 913         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 914                 if (resp_code == 0) {
 915                         return 0;
 916                 } else if (resp_code == 1) {
 917                         hns3_dbg(hw, "remove mac addr failed for miss");
 918                         return -ENOENT;
 919                 }
 920
 921                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 922                          resp_code);
 923                 return -EIO;
 924         } else if (op == HNS3_MAC_VLAN_LKUP) {
 925                 if (resp_code == 0) {
 926                         return 0;
 927                 } else if (resp_code == 1) {
 928                         hns3_dbg(hw, "lookup mac addr failed for miss");
 929                         return -ENOENT;
 930                 }
 931
 932                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 933                          resp_code);
 934                 return -EIO;
 935         }
 936
 937         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 938                  op);
 939
 940         return -EINVAL;
 941 }
 942
 943 static int
 944 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 945                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 946                          struct hns3_cmd_desc *desc, bool is_mc)
 947 {
 948         uint8_t resp_code;
 949         uint16_t retval;
 950         int ret;
 951
 952         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 953         if (is_mc) {
 954                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 955                 memcpy(desc[0].data, req,
 956                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 957                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 958                                           true);
 959                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 960                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 961                                           true);
 962                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 963         } else {
 964                 memcpy(desc[0].data, req,
 965                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 966                 ret = hns3_cmd_send(hw, desc, 1);
 967         }
 968         if (ret) {
 969                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 970                          ret);
 971                 return ret;
 972         }
 973         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 974         retval = rte_le_to_cpu_16(desc[0].retval);
 975
 976         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 977                                             HNS3_MAC_VLAN_LKUP);
 978 }
 979
 980 static int
 981 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 982                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 983                       struct hns3_cmd_desc *mc_desc)
 984 {
 985         uint8_t resp_code;
 986         uint16_t retval;
 987         int cfg_status;
 988         int ret;
 989
 990         if (mc_desc == NULL) {
 991                 struct hns3_cmd_desc desc;
 992
 993                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 994                 memcpy(desc.data, req,
 995                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 996                 ret = hns3_cmd_send(hw, &desc, 1);
 997                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 998                 retval = rte_le_to_cpu_16(desc.retval);
 999
1000                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1001                                                           HNS3_MAC_VLAN_ADD);
1002         } else {
1003                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1004                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1005                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1006                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1007                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1008                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1009                 memcpy(mc_desc[0].data, req,
1010                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1011                 mc_desc[0].retval = 0;
1012                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1013                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1014                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1015
1016                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1017                                                           HNS3_MAC_VLAN_ADD);
1018         }
1019
1020         if (ret) {
1021                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1022                 return ret;
1023         }
1024
1025         return cfg_status;
1026 }
1027
1028 static int
1029 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1030                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1031 {
1032         struct hns3_cmd_desc desc;
1033         uint8_t resp_code;
1034         uint16_t retval;
1035         int ret;
1036
1037         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1038
1039         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1040
1041         ret = hns3_cmd_send(hw, &desc, 1);
1042         if (ret) {
1043                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1044                 return ret;
1045         }
1046         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1047         retval = rte_le_to_cpu_16(desc.retval);
1048
1049         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1050                                             HNS3_MAC_VLAN_REMOVE);
1051 }
1052
1053 static int
1054 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1055 {
1056         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1057         struct hns3_mac_vlan_tbl_entry_cmd req;
1058         struct hns3_pf *pf = &hns->pf;
1059         struct hns3_cmd_desc desc;
1060         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1061         uint16_t egress_port = 0;
1062         uint8_t vf_id;
1063         int ret;
1064
1065         /* check if mac addr is valid */
1066         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1067                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1068                                       mac_addr);
1069                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1070                          mac_str);
1071                 return -EINVAL;
1072         }
1073
1074         memset(&req, 0, sizeof(req));
1075
1076         /*
1077          * In current version VF is not supported when PF is driven by DPDK
1078          * driver, the PF-related vf_id is 0, just need to configure parameters
1079          * for vf_id 0.
1080          */
1081         vf_id = 0;
1082         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1083                        HNS3_MAC_EPORT_VFID_S, vf_id);
1084
1085         req.egress_port = rte_cpu_to_le_16(egress_port);
1086
1087         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1088
1089         /*
1090          * Lookup the mac address in the mac_vlan table, and add
1091          * it if the entry is inexistent. Repeated unicast entry
1092          * is not allowed in the mac vlan table.
1093          */
1094         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1095         if (ret == -ENOENT) {
1096                 if (!hns3_is_umv_space_full(hw)) {
1097                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1098                         if (!ret)
1099                                 hns3_update_umv_space(hw, false);
1100                         return ret;
1101                 }
1102
1103                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1104
1105                 return -ENOSPC;
1106         }
1107
1108         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1109
1110         /* check if we just hit the duplicate */
1111         if (ret == 0) {
1112                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1113                 return 0;
1114         }
1115
1116         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1117                  mac_str);
1118
1119         return ret;
1120 }
1121
1122 static int
1123 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1124                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1125 {
1126         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1128         int ret;
1129
1130         rte_spinlock_lock(&hw->lock);
1131         ret = hns3_add_uc_addr_common(hw, mac_addr);
1132         if (ret) {
1133                 rte_spinlock_unlock(&hw->lock);
1134                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1135                                       mac_addr);
1136                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1137                 return ret;
1138         }
1139
1140         if (idx == 0)
1141                 hw->mac.default_addr_setted = true;
1142         rte_spinlock_unlock(&hw->lock);
1143
1144         return ret;
1145 }
1146
1147 static int
1148 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1149 {
1150         struct hns3_mac_vlan_tbl_entry_cmd req;
1151         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1152         int ret;
1153
1154         /* check if mac addr is valid */
1155         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1156                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1157                                       mac_addr);
1158                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1159                          mac_str);
1160                 return -EINVAL;
1161         }
1162
1163         memset(&req, 0, sizeof(req));
1164         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1165         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1166         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1167         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1168                 return 0;
1169         else if (ret == 0)
1170                 hns3_update_umv_space(hw, true);
1171
1172         return ret;
1173 }
1174
1175 static void
1176 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1177 {
1178         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1179         /* index will be checked by upper level rte interface */
1180         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1181         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1182         int ret;
1183
1184         rte_spinlock_lock(&hw->lock);
1185         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1186         if (ret) {
1187                 rte_spinlock_unlock(&hw->lock);
1188                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1189                                       mac_addr);
1190                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1191                 return;
1192         }
1193
1194         if (idx == 0)
1195                 hw->mac.default_addr_setted = false;
1196         rte_spinlock_unlock(&hw->lock);
1197 }
1198
1199 static int
1200 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1201                           struct rte_ether_addr *mac_addr)
1202 {
1203         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1204         struct rte_ether_addr *oaddr;
1205         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1206         bool default_addr_setted;
1207         bool rm_succes = false;
1208         int ret, ret_val;
1209
1210         /* check if mac addr is valid */
1211         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1212                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1213                                       mac_addr);
1214                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1215                          mac_str);
1216                 return -EINVAL;
1217         }
1218
1219         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1220         default_addr_setted = hw->mac.default_addr_setted;
1221         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1222                 return 0;
1223
1224         rte_spinlock_lock(&hw->lock);
1225         if (default_addr_setted) {
1226                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1227                 if (ret) {
1228                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1229                                               oaddr);
1230                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1231                                   mac_str, ret);
1232                         rm_succes = false;
1233                 } else
1234                         rm_succes = true;
1235         }
1236
1237         ret = hns3_add_uc_addr_common(hw, mac_addr);
1238         if (ret) {
1239                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1240                                       mac_addr);
1241                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1242                 goto err_add_uc_addr;
1243         }
1244
1245         rte_ether_addr_copy(mac_addr,
1246                             (struct rte_ether_addr *)hw->mac.mac_addr);
1247         hw->mac.default_addr_setted = true;
1248         rte_spinlock_unlock(&hw->lock);
1249
1250         return 0;
1251
1252 err_add_uc_addr:
1253         if (rm_succes) {
1254                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1255                 if (ret_val) {
1256                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1257                                               oaddr);
1258                         hns3_warn(hw,
1259                                   "Failed to restore old uc mac addr(%s): %d",
1260                                   mac_str, ret_val);
1261                         hw->mac.default_addr_setted = false;
1262                 }
1263         }
1264         rte_spinlock_unlock(&hw->lock);
1265
1266         return ret;
1267 }
1268
1269 static void
1270 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1271 {
1272 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1273         uint8_t word_num;
1274         uint8_t bit_num;
1275
1276         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1277                 word_num = vfid / 32;
1278                 bit_num = vfid % 32;
1279                 if (clr)
1280                         desc[1].data[word_num] &=
1281                             rte_cpu_to_le_32(~(1UL << bit_num));
1282                 else
1283                         desc[1].data[word_num] |=
1284                             rte_cpu_to_le_32(1UL << bit_num);
1285         } else {
1286                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1287                 bit_num = vfid % 32;
1288                 if (clr)
1289                         desc[2].data[word_num] &=
1290                             rte_cpu_to_le_32(~(1UL << bit_num));
1291                 else
1292                         desc[2].data[word_num] |=
1293                             rte_cpu_to_le_32(1UL << bit_num);
1294         }
1295 }
1296
1297 static int
1298 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1299 {
1300         struct hns3_mac_vlan_tbl_entry_cmd req;
1301         struct hns3_cmd_desc desc[3];
1302         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1303         uint8_t vf_id;
1304         int ret;
1305
1306         /* Check if mac addr is valid */
1307         if (!rte_is_multicast_ether_addr(mac_addr)) {
1308                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1309                                       mac_addr);
1310                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1311                          mac_str);
1312                 return -EINVAL;
1313         }
1314
1315         memset(&req, 0, sizeof(req));
1316         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1317         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1318         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1319         if (ret) {
1320                 /* This mac addr do not exist, add new entry for it */
1321                 memset(desc[0].data, 0, sizeof(desc[0].data));
1322                 memset(desc[1].data, 0, sizeof(desc[0].data));
1323                 memset(desc[2].data, 0, sizeof(desc[0].data));
1324         }
1325
1326         /*
1327          * In current version VF is not supported when PF is driven by DPDK
1328          * driver, the PF-related vf_id is 0, just need to configure parameters
1329          * for vf_id 0.
1330          */
1331         vf_id = 0;
1332         hns3_update_desc_vfid(desc, vf_id, false);
1333         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1334         if (ret) {
1335                 if (ret == -ENOSPC)
1336                         hns3_err(hw, "mc mac vlan table is full");
1337                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1338                                       mac_addr);
1339                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1340         }
1341
1342         return ret;
1343 }
1344
1345 static int
1346 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1347 {
1348         struct hns3_mac_vlan_tbl_entry_cmd req;
1349         struct hns3_cmd_desc desc[3];
1350         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1351         uint8_t vf_id;
1352         int ret;
1353
1354         /* Check if mac addr is valid */
1355         if (!rte_is_multicast_ether_addr(mac_addr)) {
1356                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1357                                       mac_addr);
1358                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1359                          mac_str);
1360                 return -EINVAL;
1361         }
1362
1363         memset(&req, 0, sizeof(req));
1364         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1365         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1366         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1367         if (ret == 0) {
1368                 /*
1369                  * This mac addr exist, remove this handle's VFID for it.
1370                  * In current version VF is not supported when PF is driven by
1371                  * DPDK driver, the PF-related vf_id is 0, just need to
1372                  * configure parameters for vf_id 0.
1373                  */
1374                 vf_id = 0;
1375                 hns3_update_desc_vfid(desc, vf_id, true);
1376
1377                 /* All the vfid is zero, so need to delete this entry */
1378                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1379         } else if (ret == -ENOENT) {
1380                 /* This mac addr doesn't exist. */
1381                 return 0;
1382         }
1383
1384         if (ret) {
1385                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1386                                       mac_addr);
1387                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1388         }
1389
1390         return ret;
1391 }
1392
1393 static int
1394 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1395                            struct rte_ether_addr *mc_addr_set,
1396                            uint32_t nb_mc_addr)
1397 {
1398         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1399         struct rte_ether_addr *addr;
1400         uint32_t i;
1401         uint32_t j;
1402
1403         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1404                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1405                          "invalid. valid range: 0~%d",
1406                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1407                 return -EINVAL;
1408         }
1409
1410         /* Check if input mac addresses are valid */
1411         for (i = 0; i < nb_mc_addr; i++) {
1412                 addr = &mc_addr_set[i];
1413                 if (!rte_is_multicast_ether_addr(addr)) {
1414                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1415                                               addr);
1416                         hns3_err(hw,
1417                                  "Failed to set mc mac addr, addr(%s) invalid.",
1418                                  mac_str);
1419                         return -EINVAL;
1420                 }
1421
1422                 /* Check if there are duplicate addresses */
1423                 for (j = i + 1; j < nb_mc_addr; j++) {
1424                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1425                                 rte_ether_format_addr(mac_str,
1426                                                       RTE_ETHER_ADDR_FMT_SIZE,
1427                                                       addr);
1428                                 hns3_err(hw, "Failed to set mc mac addr, "
1429                                          "addrs invalid. two same addrs(%s).",
1430                                          mac_str);
1431                                 return -EINVAL;
1432                         }
1433                 }
1434         }
1435
1436         return 0;
1437 }
1438
1439 static void
1440 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1441                            struct rte_ether_addr *mc_addr_set,
1442                            int mc_addr_num,
1443                            struct rte_ether_addr *reserved_addr_list,
1444                            int *reserved_addr_num,
1445                            struct rte_ether_addr *add_addr_list,
1446                            int *add_addr_num,
1447                            struct rte_ether_addr *rm_addr_list,
1448                            int *rm_addr_num)
1449 {
1450         struct rte_ether_addr *addr;
1451         int current_addr_num;
1452         int reserved_num = 0;
1453         int add_num = 0;
1454         int rm_num = 0;
1455         int num;
1456         int i;
1457         int j;
1458         bool same_addr;
1459
1460         /* Calculate the mc mac address list that should be removed */
1461         current_addr_num = hw->mc_addrs_num;
1462         for (i = 0; i < current_addr_num; i++) {
1463                 addr = &hw->mc_addrs[i];
1464                 same_addr = false;
1465                 for (j = 0; j < mc_addr_num; j++) {
1466                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1467                                 same_addr = true;
1468                                 break;
1469                         }
1470                 }
1471
1472                 if (!same_addr) {
1473                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1474                         rm_num++;
1475                 } else {
1476                         rte_ether_addr_copy(addr,
1477                                             &reserved_addr_list[reserved_num]);
1478                         reserved_num++;
1479                 }
1480         }
1481
1482         /* Calculate the mc mac address list that should be added */
1483         for (i = 0; i < mc_addr_num; i++) {
1484                 addr = &mc_addr_set[i];
1485                 same_addr = false;
1486                 for (j = 0; j < current_addr_num; j++) {
1487                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1488                                 same_addr = true;
1489                                 break;
1490                         }
1491                 }
1492
1493                 if (!same_addr) {
1494                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1495                         add_num++;
1496                 }
1497         }
1498
1499         /* Reorder the mc mac address list maintained by driver */
1500         for (i = 0; i < reserved_num; i++)
1501                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1502
1503         for (i = 0; i < rm_num; i++) {
1504                 num = reserved_num + i;
1505                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1506         }
1507
1508         *reserved_addr_num = reserved_num;
1509         *add_addr_num = add_num;
1510         *rm_addr_num = rm_num;
1511 }
1512
1513 static int
1514 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1515                           struct rte_ether_addr *mc_addr_set,
1516                           uint32_t nb_mc_addr)
1517 {
1518         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1519         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1520         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1521         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1522         struct rte_ether_addr *addr;
1523         int reserved_addr_num;
1524         int add_addr_num;
1525         int rm_addr_num;
1526         int mc_addr_num;
1527         int num;
1528         int ret;
1529         int i;
1530
1531         /* Check if input parameters are valid */
1532         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1533         if (ret)
1534                 return ret;
1535
1536         rte_spinlock_lock(&hw->lock);
1537
1538         /*
1539          * Calculate the mc mac address lists those should be removed and be
1540          * added, Reorder the mc mac address list maintained by driver.
1541          */
1542         mc_addr_num = (int)nb_mc_addr;
1543         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1544                                    reserved_addr_list, &reserved_addr_num,
1545                                    add_addr_list, &add_addr_num,
1546                                    rm_addr_list, &rm_addr_num);
1547
1548         /* Remove mc mac addresses */
1549         for (i = 0; i < rm_addr_num; i++) {
1550                 num = rm_addr_num - i - 1;
1551                 addr = &rm_addr_list[num];
1552                 ret = hns3_remove_mc_addr(hw, addr);
1553                 if (ret) {
1554                         rte_spinlock_unlock(&hw->lock);
1555                         return ret;
1556                 }
1557                 hw->mc_addrs_num--;
1558         }
1559
1560         /* Add mc mac addresses */
1561         for (i = 0; i < add_addr_num; i++) {
1562                 addr = &add_addr_list[i];
1563                 ret = hns3_add_mc_addr(hw, addr);
1564                 if (ret) {
1565                         rte_spinlock_unlock(&hw->lock);
1566                         return ret;
1567                 }
1568
1569                 num = reserved_addr_num + i;
1570                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1571                 hw->mc_addrs_num++;
1572         }
1573         rte_spinlock_unlock(&hw->lock);
1574
1575         return 0;
1576 }
1577
1578 static int
1579 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1580 {
1581         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1582         struct hns3_hw *hw = &hns->hw;
1583         struct rte_ether_addr *addr;
1584         int err = 0;
1585         int ret;
1586         int i;
1587
1588         for (i = 0; i < hw->mc_addrs_num; i++) {
1589                 addr = &hw->mc_addrs[i];
1590                 if (!rte_is_multicast_ether_addr(addr))
1591                         continue;
1592                 if (del)
1593                         ret = hns3_remove_mc_addr(hw, addr);
1594                 else
1595                         ret = hns3_add_mc_addr(hw, addr);
1596                 if (ret) {
1597                         err = ret;
1598                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1599                                               addr);
1600                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1601                                  del ? "Remove" : "Restore", mac_str);
1602                 }
1603         }
1604         return err;
1605 }
1606
1607 static int
1608 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
1609 {
1610         struct hns3_config_max_frm_size_cmd *req;
1611         struct hns3_cmd_desc desc;
1612
1613         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
1614
1615         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
1616         req->max_frm_size = rte_cpu_to_le_16(new_mps);
1617         req->min_frm_size = HNS3_MIN_FRAME_LEN;
1618
1619         return hns3_cmd_send(hw, &desc, 1);
1620 }
1621
1622 static int
1623 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
1624 {
1625         int ret;
1626
1627         ret = hns3_set_mac_mtu(hw, mps);
1628         if (ret) {
1629                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
1630                 return ret;
1631         }
1632
1633         ret = hns3_buffer_alloc(hw);
1634         if (ret) {
1635                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
1636                 return ret;
1637         }
1638
1639         return 0;
1640 }
1641
1642 static int
1643 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1644 {
1645         struct hns3_adapter *hns = dev->data->dev_private;
1646         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
1647         struct hns3_hw *hw = &hns->hw;
1648         bool is_jumbo_frame;
1649         int ret;
1650
1651         if (dev->data->dev_started) {
1652                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
1653                          "before configuration", dev->data->port_id);
1654                 return -EBUSY;
1655         }
1656
1657         rte_spinlock_lock(&hw->lock);
1658         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
1659         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
1660
1661         /*
1662          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
1663          * assign to "uint16_t" type variable.
1664          */
1665         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
1666         if (ret) {
1667                 rte_spinlock_unlock(&hw->lock);
1668                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
1669                          dev->data->port_id, mtu, ret);
1670                 return ret;
1671         }
1672         hns->pf.mps = (uint16_t)frame_size;
1673         if (is_jumbo_frame)
1674                 dev->data->dev_conf.rxmode.offloads |=
1675                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
1676         else
1677                 dev->data->dev_conf.rxmode.offloads &=
1678                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1679         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1680         rte_spinlock_unlock(&hw->lock);
1681
1682         return 0;
1683 }
1684
1685 static int
1686 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
1687 {
1688         struct hns3_adapter *hns = eth_dev->data->dev_private;
1689         struct hns3_hw *hw = &hns->hw;
1690
1691         info->max_rx_queues = hw->tqps_num;
1692         info->max_tx_queues = hw->tqps_num;
1693         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
1694         info->min_rx_bufsize = hw->rx_buf_len;
1695         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1696         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1697         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1698                                  DEV_RX_OFFLOAD_TCP_CKSUM |
1699                                  DEV_RX_OFFLOAD_UDP_CKSUM |
1700                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
1701                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1702                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1703                                  DEV_RX_OFFLOAD_KEEP_CRC |
1704                                  DEV_RX_OFFLOAD_SCATTER |
1705                                  DEV_RX_OFFLOAD_VLAN_STRIP |
1706                                  DEV_RX_OFFLOAD_QINQ_STRIP |
1707                                  DEV_RX_OFFLOAD_VLAN_FILTER |
1708                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
1709                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
1710         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1711         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1712                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
1713                                  DEV_TX_OFFLOAD_TCP_CKSUM |
1714                                  DEV_TX_OFFLOAD_UDP_CKSUM |
1715                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
1716                                  DEV_TX_OFFLOAD_VLAN_INSERT |
1717                                  DEV_TX_OFFLOAD_QINQ_INSERT |
1718                                  DEV_TX_OFFLOAD_MULTI_SEGS |
1719                                  info->tx_queue_offload_capa);
1720
1721         info->rx_desc_lim = (struct rte_eth_desc_lim) {
1722                 .nb_max = HNS3_MAX_RING_DESC,
1723                 .nb_min = HNS3_MIN_RING_DESC,
1724                 .nb_align = HNS3_ALIGN_RING_DESC,
1725         };
1726
1727         info->tx_desc_lim = (struct rte_eth_desc_lim) {
1728                 .nb_max = HNS3_MAX_RING_DESC,
1729                 .nb_min = HNS3_MIN_RING_DESC,
1730                 .nb_align = HNS3_ALIGN_RING_DESC,
1731         };
1732
1733         info->vmdq_queue_num = 0;
1734
1735         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
1736         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1737         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1738
1739         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1740         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1741         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1742         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1743         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1744         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1745
1746         return 0;
1747 }
1748
1749 static int
1750 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1751                     size_t fw_size)
1752 {
1753         struct hns3_adapter *hns = eth_dev->data->dev_private;
1754         struct hns3_hw *hw = &hns->hw;
1755         int ret;
1756
1757         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1758         ret += 1; /* add the size of '\0' */
1759         if (fw_size < (uint32_t)ret)
1760                 return ret;
1761         else
1762                 return 0;
1763 }
1764
1765 static int
1766 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
1767                      __rte_unused int wait_to_complete)
1768 {
1769         struct hns3_adapter *hns = eth_dev->data->dev_private;
1770         struct hns3_hw *hw = &hns->hw;
1771         struct hns3_mac *mac = &hw->mac;
1772         struct rte_eth_link new_link;
1773
1774         memset(&new_link, 0, sizeof(new_link));
1775         switch (mac->link_speed) {
1776         case ETH_SPEED_NUM_10M:
1777         case ETH_SPEED_NUM_100M:
1778         case ETH_SPEED_NUM_1G:
1779         case ETH_SPEED_NUM_10G:
1780         case ETH_SPEED_NUM_25G:
1781         case ETH_SPEED_NUM_40G:
1782         case ETH_SPEED_NUM_50G:
1783         case ETH_SPEED_NUM_100G:
1784                 new_link.link_speed = mac->link_speed;
1785                 break;
1786         default:
1787                 new_link.link_speed = ETH_SPEED_NUM_100M;
1788                 break;
1789         }
1790
1791         new_link.link_duplex = mac->link_duplex;
1792         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1793         new_link.link_autoneg =
1794             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1795
1796         return rte_eth_linkstatus_set(eth_dev, &new_link);
1797 }
1798
1799 static int
1800 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1801 {
1802         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1803         struct hns3_pf *pf = &hns->pf;
1804
1805         if (!(status->pf_state & HNS3_PF_STATE_DONE))
1806                 return -EINVAL;
1807
1808         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1809
1810         return 0;
1811 }
1812
1813 static int
1814 hns3_query_function_status(struct hns3_hw *hw)
1815 {
1816 #define HNS3_QUERY_MAX_CNT              10
1817 #define HNS3_QUERY_SLEEP_MSCOEND        1
1818         struct hns3_func_status_cmd *req;
1819         struct hns3_cmd_desc desc;
1820         int timeout = 0;
1821         int ret;
1822
1823         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1824         req = (struct hns3_func_status_cmd *)desc.data;
1825
1826         do {
1827                 ret = hns3_cmd_send(hw, &desc, 1);
1828                 if (ret) {
1829                         PMD_INIT_LOG(ERR, "query function status failed %d",
1830                                      ret);
1831                         return ret;
1832                 }
1833
1834                 /* Check pf reset is done */
1835                 if (req->pf_state)
1836                         break;
1837
1838                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1839         } while (timeout++ < HNS3_QUERY_MAX_CNT);
1840
1841         return hns3_parse_func_status(hw, req);
1842 }
1843
1844 static int
1845 hns3_query_pf_resource(struct hns3_hw *hw)
1846 {
1847         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1848         struct hns3_pf *pf = &hns->pf;
1849         struct hns3_pf_res_cmd *req;
1850         struct hns3_cmd_desc desc;
1851         int ret;
1852
1853         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1854         ret = hns3_cmd_send(hw, &desc, 1);
1855         if (ret) {
1856                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1857                 return ret;
1858         }
1859
1860         req = (struct hns3_pf_res_cmd *)desc.data;
1861         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1862         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1863         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1864
1865         if (req->tx_buf_size)
1866                 pf->tx_buf_size =
1867                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1868         else
1869                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1870
1871         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1872
1873         if (req->dv_buf_size)
1874                 pf->dv_buf_size =
1875                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1876         else
1877                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1878
1879         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1880
1881         hw->num_msi =
1882             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1883                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1884
1885         return 0;
1886 }
1887
1888 static void
1889 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1890 {
1891         struct hns3_cfg_param_cmd *req;
1892         uint64_t mac_addr_tmp_high;
1893         uint64_t mac_addr_tmp;
1894         uint32_t i;
1895
1896         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1897
1898         /* get the configuration */
1899         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1900                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1901         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1902                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1903         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1904                                            HNS3_CFG_TQP_DESC_N_M,
1905                                            HNS3_CFG_TQP_DESC_N_S);
1906
1907         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1908                                        HNS3_CFG_PHY_ADDR_M,
1909                                        HNS3_CFG_PHY_ADDR_S);
1910         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1911                                          HNS3_CFG_MEDIA_TP_M,
1912                                          HNS3_CFG_MEDIA_TP_S);
1913         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1914                                          HNS3_CFG_RX_BUF_LEN_M,
1915                                          HNS3_CFG_RX_BUF_LEN_S);
1916         /* get mac address */
1917         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1918         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1919                                            HNS3_CFG_MAC_ADDR_H_M,
1920                                            HNS3_CFG_MAC_ADDR_H_S);
1921
1922         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1923
1924         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1925                                             HNS3_CFG_DEFAULT_SPEED_M,
1926                                             HNS3_CFG_DEFAULT_SPEED_S);
1927         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1928                                            HNS3_CFG_RSS_SIZE_M,
1929                                            HNS3_CFG_RSS_SIZE_S);
1930
1931         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1932                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1933
1934         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1935         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1936
1937         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1938                                             HNS3_CFG_SPEED_ABILITY_M,
1939                                             HNS3_CFG_SPEED_ABILITY_S);
1940         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1941                                         HNS3_CFG_UMV_TBL_SPACE_M,
1942                                         HNS3_CFG_UMV_TBL_SPACE_S);
1943         if (!cfg->umv_space)
1944                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1945 }
1946
1947 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1948  * @hw: pointer to struct hns3_hw
1949  * @hcfg: the config structure to be getted
1950  */
1951 static int
1952 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1953 {
1954         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1955         struct hns3_cfg_param_cmd *req;
1956         uint32_t offset;
1957         uint32_t i;
1958         int ret;
1959
1960         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1961                 offset = 0;
1962                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1963                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1964                                           true);
1965                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1966                                i * HNS3_CFG_RD_LEN_BYTES);
1967                 /* Len should be divided by 4 when send to hardware */
1968                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1969                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1970                 req->offset = rte_cpu_to_le_32(offset);
1971         }
1972
1973         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1974         if (ret) {
1975                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1976                 return ret;
1977         }
1978
1979         hns3_parse_cfg(hcfg, desc);
1980
1981         return 0;
1982 }
1983
1984 static int
1985 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1986 {
1987         switch (speed_cmd) {
1988         case HNS3_CFG_SPEED_10M:
1989                 *speed = ETH_SPEED_NUM_10M;
1990                 break;
1991         case HNS3_CFG_SPEED_100M:
1992                 *speed = ETH_SPEED_NUM_100M;
1993                 break;
1994         case HNS3_CFG_SPEED_1G:
1995                 *speed = ETH_SPEED_NUM_1G;
1996                 break;
1997         case HNS3_CFG_SPEED_10G:
1998                 *speed = ETH_SPEED_NUM_10G;
1999                 break;
2000         case HNS3_CFG_SPEED_25G:
2001                 *speed = ETH_SPEED_NUM_25G;
2002                 break;
2003         case HNS3_CFG_SPEED_40G:
2004                 *speed = ETH_SPEED_NUM_40G;
2005                 break;
2006         case HNS3_CFG_SPEED_50G:
2007                 *speed = ETH_SPEED_NUM_50G;
2008                 break;
2009         case HNS3_CFG_SPEED_100G:
2010                 *speed = ETH_SPEED_NUM_100G;
2011                 break;
2012         default:
2013                 return -EINVAL;
2014         }
2015
2016         return 0;
2017 }
2018
2019 static int
2020 hns3_get_board_configuration(struct hns3_hw *hw)
2021 {
2022         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2023         struct hns3_pf *pf = &hns->pf;
2024         struct hns3_cfg cfg;
2025         int ret;
2026
2027         ret = hns3_get_board_cfg(hw, &cfg);
2028         if (ret) {
2029                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2030                 return ret;
2031         }
2032
2033         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2034                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2035                 return -EOPNOTSUPP;
2036         }
2037
2038         hw->mac.media_type = cfg.media_type;
2039         hw->rss_size_max = cfg.rss_size_max;
2040         hw->rx_buf_len = cfg.rx_buf_len;
2041         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2042         hw->mac.phy_addr = cfg.phy_addr;
2043         hw->mac.default_addr_setted = false;
2044         hw->num_tx_desc = cfg.tqp_desc_num;
2045         hw->num_rx_desc = cfg.tqp_desc_num;
2046         hw->dcb_info.num_pg = 1;
2047         hw->dcb_info.hw_pfc_map = 0;
2048
2049         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2050         if (ret) {
2051                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2052                              cfg.default_speed, ret);
2053                 return ret;
2054         }
2055
2056         pf->tc_max = cfg.tc_num;
2057         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2058                 PMD_INIT_LOG(WARNING,
2059                              "Get TC num(%u) from flash, set TC num to 1",
2060                              pf->tc_max);
2061                 pf->tc_max = 1;
2062         }
2063
2064         /* Dev does not support DCB */
2065         if (!hns3_dev_dcb_supported(hw)) {
2066                 pf->tc_max = 1;
2067                 pf->pfc_max = 0;
2068         } else
2069                 pf->pfc_max = pf->tc_max;
2070
2071         hw->dcb_info.num_tc = 1;
2072         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2073                                      hw->tqps_num / hw->dcb_info.num_tc);
2074         hns3_set_bit(hw->hw_tc_map, 0, 1);
2075         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2076
2077         pf->wanted_umv_size = cfg.umv_space;
2078
2079         return ret;
2080 }
2081
2082 static int
2083 hns3_get_configuration(struct hns3_hw *hw)
2084 {
2085         int ret;
2086
2087         ret = hns3_query_function_status(hw);
2088         if (ret) {
2089                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2090                 return ret;
2091         }
2092
2093         /* Get pf resource */
2094         ret = hns3_query_pf_resource(hw);
2095         if (ret) {
2096                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2097                 return ret;
2098         }
2099
2100         ret = hns3_get_board_configuration(hw);
2101         if (ret) {
2102                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2103                 return ret;
2104         }
2105
2106         return 0;
2107 }
2108
2109 static int
2110 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2111                       uint16_t tqp_vid, bool is_pf)
2112 {
2113         struct hns3_tqp_map_cmd *req;
2114         struct hns3_cmd_desc desc;
2115         int ret;
2116
2117         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2118
2119         req = (struct hns3_tqp_map_cmd *)desc.data;
2120         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2121         req->tqp_vf = func_id;
2122         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2123         if (!is_pf)
2124                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2125         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2126
2127         ret = hns3_cmd_send(hw, &desc, 1);
2128         if (ret)
2129                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2130
2131         return ret;
2132 }
2133
2134 static int
2135 hns3_map_tqp(struct hns3_hw *hw)
2136 {
2137         uint16_t tqps_num = hw->total_tqps_num;
2138         uint16_t func_id;
2139         uint16_t tqp_id;
2140         int num;
2141         int ret;
2142         int i;
2143
2144         /*
2145          * In current version VF is not supported when PF is driven by DPDK
2146          * driver, so we allocate tqps to PF as much as possible.
2147          */
2148         tqp_id = 0;
2149         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2150         for (func_id = 0; func_id < num; func_id++) {
2151                 for (i = 0;
2152                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2153                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2154                                                     true);
2155                         if (ret)
2156                                 return ret;
2157                 }
2158         }
2159
2160         return 0;
2161 }
2162
2163 static int
2164 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2165 {
2166         struct hns3_config_mac_speed_dup_cmd *req;
2167         struct hns3_cmd_desc desc;
2168         int ret;
2169
2170         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2171
2172         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2173
2174         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2175
2176         switch (speed) {
2177         case ETH_SPEED_NUM_10M:
2178                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2179                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2180                 break;
2181         case ETH_SPEED_NUM_100M:
2182                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2183                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2184                 break;
2185         case ETH_SPEED_NUM_1G:
2186                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2187                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2188                 break;
2189         case ETH_SPEED_NUM_10G:
2190                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2191                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2192                 break;
2193         case ETH_SPEED_NUM_25G:
2194                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2195                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2196                 break;
2197         case ETH_SPEED_NUM_40G:
2198                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2199                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2200                 break;
2201         case ETH_SPEED_NUM_50G:
2202                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2203                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2204                 break;
2205         case ETH_SPEED_NUM_100G:
2206                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2207                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2208                 break;
2209         default:
2210                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2211                 return -EINVAL;
2212         }
2213
2214         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2215
2216         ret = hns3_cmd_send(hw, &desc, 1);
2217         if (ret)
2218                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2219
2220         return ret;
2221 }
2222
2223 static int
2224 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2225 {
2226         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2227         struct hns3_pf *pf = &hns->pf;
2228         struct hns3_priv_buf *priv;
2229         uint32_t i, total_size;
2230
2231         total_size = pf->pkt_buf_size;
2232
2233         /* alloc tx buffer for all enabled tc */
2234         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2235                 priv = &buf_alloc->priv_buf[i];
2236
2237                 if (hw->hw_tc_map & BIT(i)) {
2238                         if (total_size < pf->tx_buf_size)
2239                                 return -ENOMEM;
2240
2241                         priv->tx_buf_size = pf->tx_buf_size;
2242                 } else
2243                         priv->tx_buf_size = 0;
2244
2245                 total_size -= priv->tx_buf_size;
2246         }
2247
2248         return 0;
2249 }
2250
2251 static int
2252 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2253 {
2254 /* TX buffer size is unit by 128 byte */
2255 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2256 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2257         struct hns3_tx_buff_alloc_cmd *req;
2258         struct hns3_cmd_desc desc;
2259         uint32_t buf_size;
2260         uint32_t i;
2261         int ret;
2262
2263         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2264
2265         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2266         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2267                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2268
2269                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2270                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2271                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2272         }
2273
2274         ret = hns3_cmd_send(hw, &desc, 1);
2275         if (ret)
2276                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2277
2278         return ret;
2279 }
2280
2281 static int
2282 hns3_get_tc_num(struct hns3_hw *hw)
2283 {
2284         int cnt = 0;
2285         uint8_t i;
2286
2287         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2288                 if (hw->hw_tc_map & BIT(i))
2289                         cnt++;
2290         return cnt;
2291 }
2292
2293 static uint32_t
2294 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2295 {
2296         struct hns3_priv_buf *priv;
2297         uint32_t rx_priv = 0;
2298         int i;
2299
2300         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2301                 priv = &buf_alloc->priv_buf[i];
2302                 if (priv->enable)
2303                         rx_priv += priv->buf_size;
2304         }
2305         return rx_priv;
2306 }
2307
2308 static uint32_t
2309 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2310 {
2311         uint32_t total_tx_size = 0;
2312         uint32_t i;
2313
2314         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2315                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2316
2317         return total_tx_size;
2318 }
2319
2320 /* Get the number of pfc enabled TCs, which have private buffer */
2321 static int
2322 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2323 {
2324         struct hns3_priv_buf *priv;
2325         int cnt = 0;
2326         uint8_t i;
2327
2328         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2329                 priv = &buf_alloc->priv_buf[i];
2330                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2331                         cnt++;
2332         }
2333
2334         return cnt;
2335 }
2336
2337 /* Get the number of pfc disabled TCs, which have private buffer */
2338 static int
2339 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2340                          struct hns3_pkt_buf_alloc *buf_alloc)
2341 {
2342         struct hns3_priv_buf *priv;
2343         int cnt = 0;
2344         uint8_t i;
2345
2346         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2347                 priv = &buf_alloc->priv_buf[i];
2348                 if (hw->hw_tc_map & BIT(i) &&
2349                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2350                         cnt++;
2351         }
2352
2353         return cnt;
2354 }
2355
2356 static bool
2357 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2358                   uint32_t rx_all)
2359 {
2360         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2361         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2362         struct hns3_pf *pf = &hns->pf;
2363         uint32_t shared_buf, aligned_mps;
2364         uint32_t rx_priv;
2365         uint8_t tc_num;
2366         uint8_t i;
2367
2368         tc_num = hns3_get_tc_num(hw);
2369         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2370
2371         if (hns3_dev_dcb_supported(hw))
2372                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2373                                         pf->dv_buf_size;
2374         else
2375                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2376                                         + pf->dv_buf_size;
2377
2378         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2379         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2380                              HNS3_BUF_SIZE_UNIT);
2381
2382         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2383         if (rx_all < rx_priv + shared_std)
2384                 return false;
2385
2386         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2387         buf_alloc->s_buf.buf_size = shared_buf;
2388         if (hns3_dev_dcb_supported(hw)) {
2389                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2390                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2391                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2392                                   HNS3_BUF_SIZE_UNIT);
2393         } else {
2394                 buf_alloc->s_buf.self.high =
2395                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2396                 buf_alloc->s_buf.self.low = aligned_mps;
2397         }
2398
2399         if (hns3_dev_dcb_supported(hw)) {
2400                 hi_thrd = shared_buf - pf->dv_buf_size;
2401
2402                 if (tc_num <= NEED_RESERVE_TC_NUM)
2403                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2404                                         / BUF_MAX_PERCENT;
2405
2406                 if (tc_num)
2407                         hi_thrd = hi_thrd / tc_num;
2408
2409                 hi_thrd = max_t(uint32_t, hi_thrd,
2410                                 HNS3_BUF_MUL_BY * aligned_mps);
2411                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2412                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2413         } else {
2414                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2415                 lo_thrd = aligned_mps;
2416         }
2417
2418         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2419                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2420                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2421         }
2422
2423         return true;
2424 }
2425
2426 static bool
2427 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2428                      struct hns3_pkt_buf_alloc *buf_alloc)
2429 {
2430         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2431         struct hns3_pf *pf = &hns->pf;
2432         struct hns3_priv_buf *priv;
2433         uint32_t aligned_mps;
2434         uint32_t rx_all;
2435         uint8_t i;
2436
2437         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2438         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2439
2440         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2441                 priv = &buf_alloc->priv_buf[i];
2442
2443                 priv->enable = 0;
2444                 priv->wl.low = 0;
2445                 priv->wl.high = 0;
2446                 priv->buf_size = 0;
2447
2448                 if (!(hw->hw_tc_map & BIT(i)))
2449                         continue;
2450
2451                 priv->enable = 1;
2452                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
2453                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
2454                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2455                                                 HNS3_BUF_SIZE_UNIT);
2456                 } else {
2457                         priv->wl.low = 0;
2458                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
2459                                         aligned_mps;
2460                 }
2461
2462                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
2463         }
2464
2465         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2466 }
2467
2468 static bool
2469 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
2470                              struct hns3_pkt_buf_alloc *buf_alloc)
2471 {
2472         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2473         struct hns3_pf *pf = &hns->pf;
2474         struct hns3_priv_buf *priv;
2475         int no_pfc_priv_num;
2476         uint32_t rx_all;
2477         uint8_t mask;
2478         int i;
2479
2480         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2481         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
2482
2483         /* let the last to be cleared first */
2484         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
2485                 priv = &buf_alloc->priv_buf[i];
2486                 mask = BIT((uint8_t)i);
2487
2488                 if (hw->hw_tc_map & mask &&
2489                     !(hw->dcb_info.hw_pfc_map & mask)) {
2490                         /* Clear the no pfc TC private buffer */
2491                         priv->wl.low = 0;
2492                         priv->wl.high = 0;
2493                         priv->buf_size = 0;
2494                         priv->enable = 0;
2495                         no_pfc_priv_num--;
2496                 }
2497
2498                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
2499                     no_pfc_priv_num == 0)
2500                         break;
2501         }
2502
2503         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2504 }
2505
2506 static bool
2507 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
2508                            struct hns3_pkt_buf_alloc *buf_alloc)
2509 {
2510         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2511         struct hns3_pf *pf = &hns->pf;
2512         struct hns3_priv_buf *priv;
2513         uint32_t rx_all;
2514         int pfc_priv_num;
2515         uint8_t mask;
2516         int i;
2517
2518         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2519         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
2520
2521         /* let the last to be cleared first */
2522         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
2523                 priv = &buf_alloc->priv_buf[i];
2524                 mask = BIT((uint8_t)i);
2525
2526                 if (hw->hw_tc_map & mask &&
2527                     hw->dcb_info.hw_pfc_map & mask) {
2528                         /* Reduce the number of pfc TC with private buffer */
2529                         priv->wl.low = 0;
2530                         priv->enable = 0;
2531                         priv->wl.high = 0;
2532                         priv->buf_size = 0;
2533                         pfc_priv_num--;
2534                 }
2535                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
2536                     pfc_priv_num == 0)
2537                         break;
2538         }
2539
2540         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2541 }
2542
2543 static bool
2544 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
2545                           struct hns3_pkt_buf_alloc *buf_alloc)
2546 {
2547 #define COMPENSATE_BUFFER       0x3C00
2548 #define COMPENSATE_HALF_MPS_NUM 5
2549 #define PRIV_WL_GAP             0x1800
2550         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2551         struct hns3_pf *pf = &hns->pf;
2552         uint32_t tc_num = hns3_get_tc_num(hw);
2553         uint32_t half_mps = pf->mps >> 1;
2554         struct hns3_priv_buf *priv;
2555         uint32_t min_rx_priv;
2556         uint32_t rx_priv;
2557         uint8_t i;
2558
2559         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2560         if (tc_num)
2561                 rx_priv = rx_priv / tc_num;
2562
2563         if (tc_num <= NEED_RESERVE_TC_NUM)
2564                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
2565
2566         /*
2567          * Minimum value of private buffer in rx direction (min_rx_priv) is
2568          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
2569          * buffer if rx_priv is greater than min_rx_priv.
2570          */
2571         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
2572                         COMPENSATE_HALF_MPS_NUM * half_mps;
2573         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
2574         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
2575
2576         if (rx_priv < min_rx_priv)
2577                 return false;
2578
2579         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2580                 priv = &buf_alloc->priv_buf[i];
2581
2582                 priv->enable = 0;
2583                 priv->wl.low = 0;
2584                 priv->wl.high = 0;
2585                 priv->buf_size = 0;
2586
2587                 if (!(hw->hw_tc_map & BIT(i)))
2588                         continue;
2589
2590                 priv->enable = 1;
2591                 priv->buf_size = rx_priv;
2592                 priv->wl.high = rx_priv - pf->dv_buf_size;
2593                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
2594         }
2595
2596         buf_alloc->s_buf.buf_size = 0;
2597
2598         return true;
2599 }
2600
2601 /*
2602  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
2603  * @hw: pointer to struct hns3_hw
2604  * @buf_alloc: pointer to buffer calculation data
2605  * @return: 0: calculate sucessful, negative: fail
2606  */
2607 static int
2608 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2609 {
2610         /* When DCB is not supported, rx private buffer is not allocated. */
2611         if (!hns3_dev_dcb_supported(hw)) {
2612                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2613                 struct hns3_pf *pf = &hns->pf;
2614                 uint32_t rx_all = pf->pkt_buf_size;
2615
2616                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
2617                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
2618                         return -ENOMEM;
2619
2620                 return 0;
2621         }
2622
2623         /*
2624          * Try to allocate privated packet buffer for all TCs without share
2625          * buffer.
2626          */
2627         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
2628                 return 0;
2629
2630         /*
2631          * Try to allocate privated packet buffer for all TCs with share
2632          * buffer.
2633          */
2634         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
2635                 return 0;
2636
2637         /*
2638          * For different application scenes, the enabled port number, TC number
2639          * and no_drop TC number are different. In order to obtain the better
2640          * performance, software could allocate the buffer size and configure
2641          * the waterline by tring to decrease the private buffer size according
2642          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
2643          * enabled tc.
2644          */
2645         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
2646                 return 0;
2647
2648         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
2649                 return 0;
2650
2651         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
2652                 return 0;
2653
2654         return -ENOMEM;
2655 }
2656
2657 static int
2658 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2659 {
2660         struct hns3_rx_priv_buff_cmd *req;
2661         struct hns3_cmd_desc desc;
2662         uint32_t buf_size;
2663         int ret;
2664         int i;
2665
2666         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
2667         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
2668
2669         /* Alloc private buffer TCs */
2670         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2671                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
2672
2673                 req->buf_num[i] =
2674                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
2675                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
2676         }
2677
2678         buf_size = buf_alloc->s_buf.buf_size;
2679         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
2680                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
2681
2682         ret = hns3_cmd_send(hw, &desc, 1);
2683         if (ret)
2684                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
2685
2686         return ret;
2687 }
2688
2689 static int
2690 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2691 {
2692 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
2693         struct hns3_rx_priv_wl_buf *req;
2694         struct hns3_priv_buf *priv;
2695         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
2696         int i, j;
2697         int ret;
2698
2699         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
2700                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
2701                                           false);
2702                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
2703
2704                 /* The first descriptor set the NEXT bit to 1 */
2705                 if (i == 0)
2706                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2707                 else
2708                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2709
2710                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2711                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
2712
2713                         priv = &buf_alloc->priv_buf[idx];
2714                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
2715                                                         HNS3_BUF_UNIT_S);
2716                         req->tc_wl[j].high |=
2717                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2718                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
2719                                                         HNS3_BUF_UNIT_S);
2720                         req->tc_wl[j].low |=
2721                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2722                 }
2723         }
2724
2725         /* Send 2 descriptor at one time */
2726         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
2727         if (ret)
2728                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
2729                              ret);
2730         return ret;
2731 }
2732
2733 static int
2734 hns3_common_thrd_config(struct hns3_hw *hw,
2735                         struct hns3_pkt_buf_alloc *buf_alloc)
2736 {
2737 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
2738         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
2739         struct hns3_rx_com_thrd *req;
2740         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
2741         struct hns3_tc_thrd *tc;
2742         int tc_idx;
2743         int i, j;
2744         int ret;
2745
2746         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2747                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2748                                           false);
2749                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2750
2751                 /* The first descriptor set the NEXT bit to 1 */
2752                 if (i == 0)
2753                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2754                 else
2755                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2756
2757                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2758                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2759                         tc = &s_buf->tc_thrd[tc_idx];
2760
2761                         req->com_thrd[j].high =
2762                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2763                         req->com_thrd[j].high |=
2764                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2765                         req->com_thrd[j].low =
2766                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2767                         req->com_thrd[j].low |=
2768                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2769                 }
2770         }
2771
2772         /* Send 2 descriptors at one time */
2773         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2774         if (ret)
2775                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2776
2777         return ret;
2778 }
2779
2780 static int
2781 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2782 {
2783         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2784         struct hns3_rx_com_wl *req;
2785         struct hns3_cmd_desc desc;
2786         int ret;
2787
2788         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2789
2790         req = (struct hns3_rx_com_wl *)desc.data;
2791         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2792         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2793
2794         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2795         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2796
2797         ret = hns3_cmd_send(hw, &desc, 1);
2798         if (ret)
2799                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2800
2801         return ret;
2802 }
2803
2804 int
2805 hns3_buffer_alloc(struct hns3_hw *hw)
2806 {
2807         struct hns3_pkt_buf_alloc pkt_buf;
2808         int ret;
2809
2810         memset(&pkt_buf, 0, sizeof(pkt_buf));
2811         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2812         if (ret) {
2813                 PMD_INIT_LOG(ERR,
2814                              "could not calc tx buffer size for all TCs %d",
2815                              ret);
2816                 return ret;
2817         }
2818
2819         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2820         if (ret) {
2821                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2822                 return ret;
2823         }
2824
2825         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2826         if (ret) {
2827                 PMD_INIT_LOG(ERR,
2828                              "could not calc rx priv buffer size for all TCs %d",
2829                              ret);
2830                 return ret;
2831         }
2832
2833         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2834         if (ret) {
2835                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2836                 return ret;
2837         }
2838
2839         if (hns3_dev_dcb_supported(hw)) {
2840                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2841                 if (ret) {
2842                         PMD_INIT_LOG(ERR,
2843                                      "could not configure rx private waterline %d",
2844                                      ret);
2845                         return ret;
2846                 }
2847
2848                 ret = hns3_common_thrd_config(hw, &pkt_buf);
2849                 if (ret) {
2850                         PMD_INIT_LOG(ERR,
2851                                      "could not configure common threshold %d",
2852                                      ret);
2853                         return ret;
2854                 }
2855         }
2856
2857         ret = hns3_common_wl_config(hw, &pkt_buf);
2858         if (ret)
2859                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2860                              ret);
2861
2862         return ret;
2863 }
2864
2865 static int
2866 hns3_mac_init(struct hns3_hw *hw)
2867 {
2868         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2869         struct hns3_mac *mac = &hw->mac;
2870         struct hns3_pf *pf = &hns->pf;
2871         int ret;
2872
2873         pf->support_sfp_query = true;
2874         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2875         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2876         if (ret) {
2877                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2878                 return ret;
2879         }
2880
2881         mac->link_status = ETH_LINK_DOWN;
2882
2883         return hns3_config_mtu(hw, pf->mps);
2884 }
2885
2886 static int
2887 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2888 {
2889 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2890 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2891 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2892 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2893         int return_status;
2894
2895         if (cmdq_resp) {
2896                 PMD_INIT_LOG(ERR,
2897                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2898                              cmdq_resp);
2899                 return -EIO;
2900         }
2901
2902         switch (resp_code) {
2903         case HNS3_ETHERTYPE_SUCCESS_ADD:
2904         case HNS3_ETHERTYPE_ALREADY_ADD:
2905                 return_status = 0;
2906                 break;
2907         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2908                 PMD_INIT_LOG(ERR,
2909                              "add mac ethertype failed for manager table overflow.");
2910                 return_status = -EIO;
2911                 break;
2912         case HNS3_ETHERTYPE_KEY_CONFLICT:
2913                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2914                 return_status = -EIO;
2915                 break;
2916         default:
2917                 PMD_INIT_LOG(ERR,
2918                              "add mac ethertype failed for undefined, code=%d.",
2919                              resp_code);
2920                 return_status = -EIO;
2921         }
2922
2923         return return_status;
2924 }
2925
2926 static int
2927 hns3_add_mgr_tbl(struct hns3_hw *hw,
2928                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2929 {
2930         struct hns3_cmd_desc desc;
2931         uint8_t resp_code;
2932         uint16_t retval;
2933         int ret;
2934
2935         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2936         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2937
2938         ret = hns3_cmd_send(hw, &desc, 1);
2939         if (ret) {
2940                 PMD_INIT_LOG(ERR,
2941                              "add mac ethertype failed for cmd_send, ret =%d.",
2942                              ret);
2943                 return ret;
2944         }
2945
2946         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2947         retval = rte_le_to_cpu_16(desc.retval);
2948
2949         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2950 }
2951
2952 static void
2953 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2954                      int *table_item_num)
2955 {
2956         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2957
2958         /*
2959          * In current version, we add one item in management table as below:
2960          * 0x0180C200000E -- LLDP MC address
2961          */
2962         tbl = mgr_table;
2963         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2964         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2965         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2966         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2967         tbl->i_port_bitmap = 0x1;
2968         *table_item_num = 1;
2969 }
2970
2971 static int
2972 hns3_init_mgr_tbl(struct hns3_hw *hw)
2973 {
2974 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2975         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2976         int table_item_num;
2977         int ret;
2978         int i;
2979
2980         memset(mgr_table, 0, sizeof(mgr_table));
2981         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2982         for (i = 0; i < table_item_num; i++) {
2983                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2984                 if (ret) {
2985                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2986                                      ret);
2987                         return ret;
2988                 }
2989         }
2990
2991         return 0;
2992 }
2993
2994 static void
2995 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2996                         bool en_mc, bool en_bc, int vport_id)
2997 {
2998         if (!param)
2999                 return;
3000
3001         memset(param, 0, sizeof(struct hns3_promisc_param));
3002         if (en_uc)
3003                 param->enable = HNS3_PROMISC_EN_UC;
3004         if (en_mc)
3005                 param->enable |= HNS3_PROMISC_EN_MC;
3006         if (en_bc)
3007                 param->enable |= HNS3_PROMISC_EN_BC;
3008         param->vf_id = vport_id;
3009 }
3010
3011 static int
3012 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3013 {
3014         struct hns3_promisc_cfg_cmd *req;
3015         struct hns3_cmd_desc desc;
3016         int ret;
3017
3018         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3019
3020         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3021         req->vf_id = param->vf_id;
3022         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3023             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3024
3025         ret = hns3_cmd_send(hw, &desc, 1);
3026         if (ret)
3027                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3028
3029         return ret;
3030 }
3031
3032 static int
3033 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3034 {
3035         struct hns3_promisc_param param;
3036         bool en_bc_pmc = true;
3037         uint8_t vf_id;
3038         int ret;
3039
3040         /*
3041          * In current version VF is not supported when PF is driven by DPDK
3042          * driver, the PF-related vf_id is 0, just need to configure parameters
3043          * for vf_id 0.
3044          */
3045         vf_id = 0;
3046
3047         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3048         ret = hns3_cmd_set_promisc_mode(hw, &param);
3049         if (ret)
3050                 return ret;
3051
3052         return 0;
3053 }
3054
3055 static int
3056 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3057 {
3058         struct hns3_sfp_speed_cmd *resp;
3059         struct hns3_cmd_desc desc;
3060         int ret;
3061
3062         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3063         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3064         ret = hns3_cmd_send(hw, &desc, 1);
3065         if (ret == -EOPNOTSUPP) {
3066                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3067                 return ret;
3068         } else if (ret) {
3069                 hns3_err(hw, "get sfp speed failed %d", ret);
3070                 return ret;
3071         }
3072
3073         *speed = resp->sfp_speed;
3074
3075         return 0;
3076 }
3077
3078 static uint8_t
3079 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3080 {
3081         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3082                 duplex = ETH_LINK_FULL_DUPLEX;
3083
3084         return duplex;
3085 }
3086
3087 static int
3088 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3089 {
3090         struct hns3_mac *mac = &hw->mac;
3091         int ret;
3092
3093         duplex = hns3_check_speed_dup(duplex, speed);
3094         if (mac->link_speed == speed && mac->link_duplex == duplex)
3095                 return 0;
3096
3097         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3098         if (ret)
3099                 return ret;
3100
3101         mac->link_speed = speed;
3102         mac->link_duplex = duplex;
3103
3104         return 0;
3105 }
3106
3107 static int
3108 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3109 {
3110         struct hns3_adapter *hns = eth_dev->data->dev_private;
3111         struct hns3_hw *hw = &hns->hw;
3112         struct hns3_pf *pf = &hns->pf;
3113         uint32_t speed;
3114         int ret;
3115
3116         /* If IMP do not support get SFP/qSFP speed, return directly */
3117         if (!pf->support_sfp_query)
3118                 return 0;
3119
3120         ret = hns3_get_sfp_speed(hw, &speed);
3121         if (ret == -EOPNOTSUPP) {
3122                 pf->support_sfp_query = false;
3123                 return ret;
3124         } else if (ret)
3125                 return ret;
3126
3127         if (speed == ETH_SPEED_NUM_NONE)
3128                 return 0; /* do nothing if no SFP */
3129
3130         /* Config full duplex for SFP */
3131         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3132 }
3133
3134 static int
3135 hns3_get_mac_link_status(struct hns3_hw *hw)
3136 {
3137         struct hns3_link_status_cmd *req;
3138         struct hns3_cmd_desc desc;
3139         int link_status;
3140         int ret;
3141
3142         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3143         ret = hns3_cmd_send(hw, &desc, 1);
3144         if (ret) {
3145                 hns3_err(hw, "get link status cmd failed %d", ret);
3146                 return ret;
3147         }
3148
3149         req = (struct hns3_link_status_cmd *)desc.data;
3150         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3151
3152         return !!link_status;
3153 }
3154
3155 static void
3156 hns3_update_link_status(struct hns3_hw *hw)
3157 {
3158         int state;
3159
3160         state = hns3_get_mac_link_status(hw);
3161         if (state != hw->mac.link_status)
3162                 hw->mac.link_status = state;
3163 }
3164
3165 static void
3166 hns3_service_handler(void *param)
3167 {
3168         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3169         struct hns3_adapter *hns = eth_dev->data->dev_private;
3170         struct hns3_hw *hw = &hns->hw;
3171
3172         hns3_update_speed_duplex(eth_dev);
3173         hns3_update_link_status(hw);
3174
3175         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3176 }
3177
3178 static int
3179 hns3_init_hardware(struct hns3_adapter *hns)
3180 {
3181         struct hns3_hw *hw = &hns->hw;
3182         int ret;
3183
3184         ret = hns3_map_tqp(hw);
3185         if (ret) {
3186                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3187                 return ret;
3188         }
3189
3190         ret = hns3_init_umv_space(hw);
3191         if (ret) {
3192                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3193                 return ret;
3194         }
3195
3196         ret = hns3_mac_init(hw);
3197         if (ret) {
3198                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3199                 goto err_mac_init;
3200         }
3201
3202         ret = hns3_init_mgr_tbl(hw);
3203         if (ret) {
3204                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3205                 goto err_mac_init;
3206         }
3207
3208         ret = hns3_set_promisc_mode(hw, false, false);
3209         if (ret) {
3210                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3211                 goto err_mac_init;
3212         }
3213
3214         ret = hns3_init_vlan_config(hns);
3215         if (ret) {
3216                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3217                 goto err_mac_init;
3218         }
3219
3220         ret = hns3_dcb_init(hw);
3221         if (ret) {
3222                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3223                 goto err_mac_init;
3224         }
3225
3226         ret = hns3_init_fd_config(hns);
3227         if (ret) {
3228                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3229                 goto err_mac_init;
3230         }
3231
3232         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3233         if (ret) {
3234                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3235                 goto err_mac_init;
3236         }
3237
3238         ret = hns3_config_gro(hw, false);
3239         if (ret) {
3240                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3241                 goto err_mac_init;
3242         }
3243         return 0;
3244
3245 err_mac_init:
3246         hns3_uninit_umv_space(hw);
3247         return ret;
3248 }
3249
3250 static int
3251 hns3_init_pf(struct rte_eth_dev *eth_dev)
3252 {
3253         struct rte_device *dev = eth_dev->device;
3254         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3255         struct hns3_adapter *hns = eth_dev->data->dev_private;
3256         struct hns3_hw *hw = &hns->hw;
3257         int ret;
3258
3259         PMD_INIT_FUNC_TRACE();
3260
3261         /* Get hardware io base address from pcie BAR2 IO space */
3262         hw->io_base = pci_dev->mem_resource[2].addr;
3263
3264         /* Firmware command queue initialize */
3265         ret = hns3_cmd_init_queue(hw);
3266         if (ret) {
3267                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3268                 goto err_cmd_init_queue;
3269         }
3270
3271         /* Firmware command initialize */
3272         ret = hns3_cmd_init(hw);
3273         if (ret) {
3274                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3275                 goto err_cmd_init;
3276         }
3277
3278         /* Get configuration */
3279         ret = hns3_get_configuration(hw);
3280         if (ret) {
3281                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3282                 goto err_get_config;
3283         }
3284
3285         ret = hns3_init_hardware(hns);
3286         if (ret) {
3287                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
3288                 goto err_get_config;
3289         }
3290
3291         /* Initialize flow director filter list & hash */
3292         ret = hns3_fdir_filter_init(hns);
3293         if (ret) {
3294                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
3295                 goto err_hw_init;
3296         }
3297
3298         hns3_set_default_rss_args(hw);
3299
3300         return 0;
3301
3302 err_hw_init:
3303         hns3_uninit_umv_space(hw);
3304
3305 err_get_config:
3306         hns3_cmd_uninit(hw);
3307
3308 err_cmd_init:
3309         hns3_cmd_destroy_queue(hw);
3310
3311 err_cmd_init_queue:
3312         hw->io_base = NULL;
3313
3314         return ret;
3315 }
3316
3317 static void
3318 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
3319 {
3320         struct hns3_adapter *hns = eth_dev->data->dev_private;
3321         struct hns3_hw *hw = &hns->hw;
3322
3323         PMD_INIT_FUNC_TRACE();
3324
3325         hns3_rss_uninit(hns);
3326         hns3_fdir_filter_uninit(hns);
3327         hns3_uninit_umv_space(hw);
3328         hns3_cmd_uninit(hw);
3329         hns3_cmd_destroy_queue(hw);
3330         hw->io_base = NULL;
3331 }
3332
3333 static void
3334 hns3_dev_close(struct rte_eth_dev *eth_dev)
3335 {
3336         struct hns3_adapter *hns = eth_dev->data->dev_private;
3337         struct hns3_hw *hw = &hns->hw;
3338
3339         hw->adapter_state = HNS3_NIC_CLOSING;
3340         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
3341
3342         hns3_configure_all_mc_mac_addr(hns, true);
3343         hns3_uninit_pf(eth_dev);
3344         hns3_free_all_queues(eth_dev);
3345         rte_free(eth_dev->process_private);
3346         eth_dev->process_private = NULL;
3347         hw->adapter_state = HNS3_NIC_CLOSED;
3348 }
3349
3350 static int
3351 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3352 {
3353         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3354         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3355
3356         fc_conf->pause_time = pf->pause_time;
3357
3358         /* return fc current mode */
3359         switch (hw->current_mode) {
3360         case HNS3_FC_FULL:
3361                 fc_conf->mode = RTE_FC_FULL;
3362                 break;
3363         case HNS3_FC_TX_PAUSE:
3364                 fc_conf->mode = RTE_FC_TX_PAUSE;
3365                 break;
3366         case HNS3_FC_RX_PAUSE:
3367                 fc_conf->mode = RTE_FC_RX_PAUSE;
3368                 break;
3369         case HNS3_FC_NONE:
3370         default:
3371                 fc_conf->mode = RTE_FC_NONE;
3372                 break;
3373         }
3374
3375         return 0;
3376 }
3377
3378 static void
3379 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
3380 {
3381         switch (mode) {
3382         case RTE_FC_NONE:
3383                 hw->requested_mode = HNS3_FC_NONE;
3384                 break;
3385         case RTE_FC_RX_PAUSE:
3386                 hw->requested_mode = HNS3_FC_RX_PAUSE;
3387                 break;
3388         case RTE_FC_TX_PAUSE:
3389                 hw->requested_mode = HNS3_FC_TX_PAUSE;
3390                 break;
3391         case RTE_FC_FULL:
3392                 hw->requested_mode = HNS3_FC_FULL;
3393                 break;
3394         default:
3395                 hw->requested_mode = HNS3_FC_NONE;
3396                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
3397                           "configured to RTE_FC_NONE", mode);
3398                 break;
3399         }
3400 }
3401
3402 static int
3403 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3404 {
3405         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3407         int ret;
3408
3409         if (fc_conf->high_water || fc_conf->low_water ||
3410             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
3411                 hns3_err(hw, "Unsupported flow control settings specified, "
3412                          "high_water(%u), low_water(%u), send_xon(%u) and "
3413                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
3414                          fc_conf->high_water, fc_conf->low_water,
3415                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
3416                 return -EINVAL;
3417         }
3418         if (fc_conf->autoneg) {
3419                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
3420                 return -EINVAL;
3421         }
3422         if (!fc_conf->pause_time) {
3423                 hns3_err(hw, "Invalid pause time %d setting.",
3424                          fc_conf->pause_time);
3425                 return -EINVAL;
3426         }
3427
3428         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
3429             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
3430                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
3431                          "current_fc_status = %d", hw->current_fc_status);
3432                 return -EOPNOTSUPP;
3433         }
3434
3435         hns3_get_fc_mode(hw, fc_conf->mode);
3436         if (hw->requested_mode == hw->current_mode &&
3437             pf->pause_time == fc_conf->pause_time)
3438                 return 0;
3439
3440         rte_spinlock_lock(&hw->lock);
3441         ret = hns3_fc_enable(dev, fc_conf);
3442         rte_spinlock_unlock(&hw->lock);
3443
3444         return ret;
3445 }
3446
3447 static int
3448 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3449                             struct rte_eth_pfc_conf *pfc_conf)
3450 {
3451         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3452         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3453         uint8_t priority;
3454         int ret;
3455
3456         if (!hns3_dev_dcb_supported(hw)) {
3457                 hns3_err(hw, "This port does not support dcb configurations.");
3458                 return -EOPNOTSUPP;
3459         }
3460
3461         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
3462             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
3463                 hns3_err(hw, "Unsupported flow control settings specified, "
3464                          "high_water(%u), low_water(%u), send_xon(%u) and "
3465                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
3466                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
3467                          pfc_conf->fc.send_xon,
3468                          pfc_conf->fc.mac_ctrl_frame_fwd);
3469                 return -EINVAL;
3470         }
3471         if (pfc_conf->fc.autoneg) {
3472                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
3473                 return -EINVAL;
3474         }
3475         if (pfc_conf->fc.pause_time == 0) {
3476                 hns3_err(hw, "Invalid pause time %d setting.",
3477                          pfc_conf->fc.pause_time);
3478                 return -EINVAL;
3479         }
3480
3481         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
3482             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
3483                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
3484                              "current_fc_status = %d", hw->current_fc_status);
3485                 return -EOPNOTSUPP;
3486         }
3487
3488         priority = pfc_conf->priority;
3489         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
3490         if (hw->dcb_info.pfc_en & BIT(priority) &&
3491             hw->requested_mode == hw->current_mode &&
3492             pfc_conf->fc.pause_time == pf->pause_time)
3493                 return 0;
3494
3495         rte_spinlock_lock(&hw->lock);
3496         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
3497         rte_spinlock_unlock(&hw->lock);
3498
3499         return ret;
3500 }
3501
3502 static int
3503 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
3504 {
3505         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3506         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3507         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
3508         int i;
3509
3510         rte_spinlock_lock(&hw->lock);
3511         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
3512                 dcb_info->nb_tcs = pf->local_max_tc;
3513         else
3514                 dcb_info->nb_tcs = 1;
3515
3516         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
3517                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
3518         for (i = 0; i < dcb_info->nb_tcs; i++)
3519                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
3520
3521         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3522                 dcb_info->tc_queue.tc_rxq[0][i].base =
3523                                         hw->tc_queue[i].tqp_offset;
3524                 dcb_info->tc_queue.tc_txq[0][i].base =
3525                                         hw->tc_queue[i].tqp_offset;
3526                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
3527                                         hw->tc_queue[i].tqp_count;
3528                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
3529                                         hw->tc_queue[i].tqp_count;
3530         }
3531         rte_spinlock_unlock(&hw->lock);
3532
3533         return 0;
3534 }
3535
3536 static const struct eth_dev_ops hns3_eth_dev_ops = {
3537         .dev_close          = hns3_dev_close,
3538         .mtu_set            = hns3_dev_mtu_set,
3539         .dev_infos_get          = hns3_dev_infos_get,
3540         .fw_version_get         = hns3_fw_version_get,
3541         .rx_queue_setup         = hns3_rx_queue_setup,
3542         .tx_queue_setup         = hns3_tx_queue_setup,
3543         .rx_queue_release       = hns3_dev_rx_queue_release,
3544         .tx_queue_release       = hns3_dev_tx_queue_release,
3545         .flow_ctrl_get          = hns3_flow_ctrl_get,
3546         .flow_ctrl_set          = hns3_flow_ctrl_set,
3547         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
3548         .mac_addr_add           = hns3_add_mac_addr,
3549         .mac_addr_remove        = hns3_remove_mac_addr,
3550         .mac_addr_set           = hns3_set_default_mac_addr,
3551         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
3552         .link_update            = hns3_dev_link_update,
3553         .rss_hash_update        = hns3_dev_rss_hash_update,
3554         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
3555         .reta_update            = hns3_dev_rss_reta_update,
3556         .reta_query             = hns3_dev_rss_reta_query,
3557         .filter_ctrl            = hns3_dev_filter_ctrl,
3558         .vlan_filter_set        = hns3_vlan_filter_set,
3559         .vlan_tpid_set          = hns3_vlan_tpid_set,
3560         .vlan_offload_set       = hns3_vlan_offload_set,
3561         .vlan_pvid_set          = hns3_vlan_pvid_set,
3562         .get_dcb_info           = hns3_get_dcb_info,
3563         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
3564 };
3565
3566 static int
3567 hns3_dev_init(struct rte_eth_dev *eth_dev)
3568 {
3569         struct rte_device *dev = eth_dev->device;
3570         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3571         struct hns3_adapter *hns = eth_dev->data->dev_private;
3572         struct hns3_hw *hw = &hns->hw;
3573         uint16_t device_id = pci_dev->id.device_id;
3574         int ret;
3575
3576         PMD_INIT_FUNC_TRACE();
3577         eth_dev->process_private = (struct hns3_process_private *)
3578             rte_zmalloc_socket("hns3_filter_list",
3579                                sizeof(struct hns3_process_private),
3580                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
3581         if (eth_dev->process_private == NULL) {
3582                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
3583                 return -ENOMEM;
3584         }
3585         /* initialize flow filter lists */
3586         hns3_filterlist_init(eth_dev);
3587
3588         hns3_set_rxtx_function(eth_dev);
3589         eth_dev->dev_ops = &hns3_eth_dev_ops;
3590         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3591                 return 0;
3592
3593         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
3594
3595         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3596             device_id == HNS3_DEV_ID_50GE_RDMA ||
3597             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
3598                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
3599
3600         hns->is_vf = false;
3601         hw->data = eth_dev->data;
3602
3603         /*
3604          * Set default max packet size according to the mtu
3605          * default vale in DPDK frame.
3606          */
3607         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
3608
3609         ret = hns3_init_pf(eth_dev);
3610         if (ret) {
3611                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
3612                 goto err_init_pf;
3613         }
3614
3615         /* Allocate memory for storing MAC addresses */
3616         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
3617                                                sizeof(struct rte_ether_addr) *
3618                                                HNS3_UC_MACADDR_NUM, 0);
3619         if (eth_dev->data->mac_addrs == NULL) {
3620                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
3621                              "to store MAC addresses",
3622                              sizeof(struct rte_ether_addr) *
3623                              HNS3_UC_MACADDR_NUM);
3624                 ret = -ENOMEM;
3625                 goto err_rte_zmalloc;
3626         }
3627
3628         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
3629                             &eth_dev->data->mac_addrs[0]);
3630
3631         hw->adapter_state = HNS3_NIC_INITIALIZED;
3632         /*
3633          * Pass the information to the rte_eth_dev_close() that it should also
3634          * release the private port resources.
3635          */
3636         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
3637
3638         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3639         hns3_info(hw, "hns3 dev initialization successful!");
3640         return 0;
3641
3642 err_rte_zmalloc:
3643         hns3_uninit_pf(eth_dev);
3644
3645 err_init_pf:
3646         eth_dev->dev_ops = NULL;
3647         eth_dev->rx_pkt_burst = NULL;
3648         eth_dev->tx_pkt_burst = NULL;
3649         eth_dev->tx_pkt_prepare = NULL;
3650         rte_free(eth_dev->process_private);
3651         eth_dev->process_private = NULL;
3652         return ret;
3653 }
3654
3655 static int
3656 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
3657 {
3658         struct hns3_adapter *hns = eth_dev->data->dev_private;
3659         struct hns3_hw *hw = &hns->hw;
3660
3661         PMD_INIT_FUNC_TRACE();
3662
3663         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3664                 return -EPERM;
3665
3666         eth_dev->dev_ops = NULL;
3667         eth_dev->rx_pkt_burst = NULL;
3668         eth_dev->tx_pkt_burst = NULL;
3669         eth_dev->tx_pkt_prepare = NULL;
3670         if (hw->adapter_state < HNS3_NIC_CLOSING)
3671                 hns3_dev_close(eth_dev);
3672
3673         hw->adapter_state = HNS3_NIC_REMOVED;
3674         return 0;
3675 }
3676
3677 static int
3678 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3679                    struct rte_pci_device *pci_dev)
3680 {
3681         return rte_eth_dev_pci_generic_probe(pci_dev,
3682                                              sizeof(struct hns3_adapter),
3683                                              hns3_dev_init);
3684 }
3685
3686 static int
3687 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
3688 {
3689         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
3690 }
3691
3692 static const struct rte_pci_id pci_id_hns3_map[] = {
3693         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
3694         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
3695         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
3696         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
3697         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
3698         { .vendor_id = 0, /* sentinel */ },
3699 };
3700
3701 static struct rte_pci_driver rte_hns3_pmd = {
3702         .id_table = pci_id_hns3_map,
3703         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
3704         .probe = eth_hns3_pci_probe,
3705         .remove = eth_hns3_pci_remove,
3706 };
3707
3708 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
3709 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
3710 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
3711
3712 RTE_INIT(hns3_init_log)
3713 {
3714         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
3715         if (hns3_logtype_init >= 0)
3716                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
3717         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
3718         if (hns3_logtype_driver >= 0)
3719                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
3720 }