drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108
 109 void hns3_ether_format_addr(char *buf, uint16_t size,
 110                             const struct rte_ether_addr *ether_addr)
 111 {
 112         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 113                 ether_addr->addr_bytes[0],
 114                 ether_addr->addr_bytes[4],
 115                 ether_addr->addr_bytes[5]);
 116 }
 117
 118 static void
 119 hns3_pf_disable_irq0(struct hns3_hw *hw)
 120 {
 121         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 122 }
 123
 124 static void
 125 hns3_pf_enable_irq0(struct hns3_hw *hw)
 126 {
 127         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 128 }
 129
 130 static enum hns3_evt_cause
 131 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 132                           uint32_t *vec_val)
 133 {
 134         struct hns3_hw *hw = &hns->hw;
 135
 136         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 137         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 138         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 139         if (!is_delay) {
 140                 hw->reset.stats.imp_cnt++;
 141                 hns3_warn(hw, "IMP reset detected, clear reset status");
 142         } else {
 143                 hns3_schedule_delayed_reset(hns);
 144                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 145         }
 146
 147         return HNS3_VECTOR0_EVENT_RST;
 148 }
 149
 150 static enum hns3_evt_cause
 151 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 152                              uint32_t *vec_val)
 153 {
 154         struct hns3_hw *hw = &hns->hw;
 155
 156         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 157         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 158         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 159         if (!is_delay) {
 160                 hw->reset.stats.global_cnt++;
 161                 hns3_warn(hw, "Global reset detected, clear reset status");
 162         } else {
 163                 hns3_schedule_delayed_reset(hns);
 164                 hns3_warn(hw,
 165                           "Global reset detected, don't clear reset status");
 166         }
 167
 168         return HNS3_VECTOR0_EVENT_RST;
 169 }
 170
 171 static enum hns3_evt_cause
 172 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 173 {
 174         struct hns3_hw *hw = &hns->hw;
 175         uint32_t vector0_int_stats;
 176         uint32_t cmdq_src_val;
 177         uint32_t hw_err_src_reg;
 178         uint32_t val;
 179         enum hns3_evt_cause ret;
 180         bool is_delay;
 181
 182         /* fetch the events from their corresponding regs */
 183         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 184         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 185         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 186
 187         is_delay = clearval == NULL ? true : false;
 188         /*
 189          * Assumption: If by any chance reset and mailbox events are reported
 190          * together then we will only process reset event and defer the
 191          * processing of the mailbox events. Since, we would have not cleared
 192          * RX CMDQ event this time we would receive again another interrupt
 193          * from H/W just for the mailbox.
 194          */
 195         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 196                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 197                 goto out;
 198         }
 199
 200         /* Global reset */
 201         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 202                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 203                 goto out;
 204         }
 205
 206         /* Check for vector0 1588 event source */
 207         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 208                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 209                 ret = HNS3_VECTOR0_EVENT_PTP;
 210                 goto out;
 211         }
 212
 213         /* check for vector0 msix event source */
 214         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 215             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 216                 val = vector0_int_stats | hw_err_src_reg;
 217                 ret = HNS3_VECTOR0_EVENT_ERR;
 218                 goto out;
 219         }
 220
 221         /* check for vector0 mailbox(=CMDQ RX) event source */
 222         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 223                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 224                 val = cmdq_src_val;
 225                 ret = HNS3_VECTOR0_EVENT_MBX;
 226                 goto out;
 227         }
 228
 229         val = vector0_int_stats;
 230         ret = HNS3_VECTOR0_EVENT_OTHER;
 231 out:
 232
 233         if (clearval)
 234                 *clearval = val;
 235         return ret;
 236 }
 237
 238 static bool
 239 hns3_is_1588_event_type(uint32_t event_type)
 240 {
 241         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 242 }
 243
 244 static void
 245 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 246 {
 247         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 248             hns3_is_1588_event_type(event_type))
 249                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 250         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 251                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 252 }
 253
 254 static void
 255 hns3_clear_all_event_cause(struct hns3_hw *hw)
 256 {
 257         uint32_t vector0_int_stats;
 258         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 259
 260         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 261                 hns3_warn(hw, "Probe during IMP reset interrupt");
 262
 263         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 264                 hns3_warn(hw, "Probe during Global reset interrupt");
 265
 266         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 267                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 268                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 270         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 272                                 BIT(HNS3_VECTOR0_1588_INT_B));
 273 }
 274
 275 static void
 276 hns3_handle_mac_tnl(struct hns3_hw *hw)
 277 {
 278         struct hns3_cmd_desc desc;
 279         uint32_t status;
 280         int ret;
 281
 282         /* query and clear mac tnl interruptions */
 283         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 284         ret = hns3_cmd_send(hw, &desc, 1);
 285         if (ret) {
 286                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 287                 return;
 288         }
 289
 290         status = rte_le_to_cpu_32(desc.data[0]);
 291         if (status) {
 292                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 293                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 294                                           false);
 295                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 296                 ret = hns3_cmd_send(hw, &desc, 1);
 297                 if (ret)
 298                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 299                                  ret);
 300         }
 301 }
 302
 303 static void
 304 hns3_interrupt_handler(void *param)
 305 {
 306         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 307         struct hns3_adapter *hns = dev->data->dev_private;
 308         struct hns3_hw *hw = &hns->hw;
 309         enum hns3_evt_cause event_cause;
 310         uint32_t clearval = 0;
 311         uint32_t vector0_int;
 312         uint32_t ras_int;
 313         uint32_t cmdq_int;
 314
 315         /* Disable interrupt */
 316         hns3_pf_disable_irq0(hw);
 317
 318         event_cause = hns3_check_event_cause(hns, &clearval);
 319         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 320         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 321         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 322         /* vector 0 interrupt is shared with reset and mailbox source events. */
 323         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 324                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 325                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 326                           vector0_int, ras_int, cmdq_int);
 327                 hns3_handle_mac_tnl(hw);
 328                 hns3_handle_error(hns);
 329         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 330                 hns3_warn(hw, "received reset interrupt");
 331                 hns3_schedule_reset(hns);
 332         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 333                 hns3_dev_handle_mbx_msg(hw);
 334         } else {
 335                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 336                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 337                           vector0_int, ras_int, cmdq_int);
 338         }
 339
 340         hns3_clear_event_cause(hw, event_cause, clearval);
 341         /* Enable interrupt if it is not cause by reset */
 342         hns3_pf_enable_irq0(hw);
 343 }
 344
 345 static int
 346 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 347 {
 348 #define HNS3_VLAN_ID_OFFSET_STEP        160
 349 #define HNS3_VLAN_BYTE_SIZE             8
 350         struct hns3_vlan_filter_pf_cfg_cmd *req;
 351         struct hns3_hw *hw = &hns->hw;
 352         uint8_t vlan_offset_byte_val;
 353         struct hns3_cmd_desc desc;
 354         uint8_t vlan_offset_byte;
 355         uint8_t vlan_offset_base;
 356         int ret;
 357
 358         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 359
 360         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 361         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 362                            HNS3_VLAN_BYTE_SIZE;
 363         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 364
 365         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 366         req->vlan_offset = vlan_offset_base;
 367         req->vlan_cfg = on ? 0 : 1;
 368         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 369
 370         ret = hns3_cmd_send(hw, &desc, 1);
 371         if (ret)
 372                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 373                          vlan_id, ret);
 374
 375         return ret;
 376 }
 377
 378 static void
 379 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 380 {
 381         struct hns3_user_vlan_table *vlan_entry;
 382         struct hns3_pf *pf = &hns->pf;
 383
 384         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 385                 if (vlan_entry->vlan_id == vlan_id) {
 386                         if (vlan_entry->hd_tbl_status)
 387                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 388                         LIST_REMOVE(vlan_entry, next);
 389                         rte_free(vlan_entry);
 390                         break;
 391                 }
 392         }
 393 }
 394
 395 static void
 396 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 397                         bool writen_to_tbl)
 398 {
 399         struct hns3_user_vlan_table *vlan_entry;
 400         struct hns3_hw *hw = &hns->hw;
 401         struct hns3_pf *pf = &hns->pf;
 402
 403         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 404                 if (vlan_entry->vlan_id == vlan_id)
 405                         return;
 406         }
 407
 408         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 409         if (vlan_entry == NULL) {
 410                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 411                 return;
 412         }
 413
 414         vlan_entry->hd_tbl_status = writen_to_tbl;
 415         vlan_entry->vlan_id = vlan_id;
 416
 417         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 418 }
 419
 420 static int
 421 hns3_restore_vlan_table(struct hns3_adapter *hns)
 422 {
 423         struct hns3_user_vlan_table *vlan_entry;
 424         struct hns3_hw *hw = &hns->hw;
 425         struct hns3_pf *pf = &hns->pf;
 426         uint16_t vlan_id;
 427         int ret = 0;
 428
 429         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 430                 return hns3_vlan_pvid_configure(hns,
 431                                                 hw->port_base_vlan_cfg.pvid, 1);
 432
 433         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 434                 if (vlan_entry->hd_tbl_status) {
 435                         vlan_id = vlan_entry->vlan_id;
 436                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 437                         if (ret)
 438                                 break;
 439                 }
 440         }
 441
 442         return ret;
 443 }
 444
 445 static int
 446 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 447 {
 448         struct hns3_hw *hw = &hns->hw;
 449         bool writen_to_tbl = false;
 450         int ret = 0;
 451
 452         /*
 453          * When vlan filter is enabled, hardware regards packets without vlan
 454          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 455          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 456          */
 457         if (on == 0 && vlan_id == 0)
 458                 return 0;
 459
 460         /*
 461          * When port base vlan enabled, we use port base vlan as the vlan
 462          * filter condition. In this case, we don't update vlan filter table
 463          * when user add new vlan or remove exist vlan, just update the
 464          * vlan list. The vlan id in vlan list will be writen in vlan filter
 465          * table until port base vlan disabled
 466          */
 467         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 468                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 469                 writen_to_tbl = true;
 470         }
 471
 472         if (ret == 0) {
 473                 if (on)
 474                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 475                 else
 476                         hns3_rm_dev_vlan_table(hns, vlan_id);
 477         }
 478         return ret;
 479 }
 480
 481 static int
 482 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 483 {
 484         struct hns3_adapter *hns = dev->data->dev_private;
 485         struct hns3_hw *hw = &hns->hw;
 486         int ret;
 487
 488         rte_spinlock_lock(&hw->lock);
 489         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 490         rte_spinlock_unlock(&hw->lock);
 491         return ret;
 492 }
 493
 494 static int
 495 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 496                          uint16_t tpid)
 497 {
 498         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 499         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 500         struct hns3_hw *hw = &hns->hw;
 501         struct hns3_cmd_desc desc;
 502         int ret;
 503
 504         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 505              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 506                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 507                 return -EINVAL;
 508         }
 509
 510         if (tpid != RTE_ETHER_TYPE_VLAN) {
 511                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 512                 return -EINVAL;
 513         }
 514
 515         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 516         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 517
 518         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 519                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 520                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 521         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 522                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 523                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 526         }
 527
 528         ret = hns3_cmd_send(hw, &desc, 1);
 529         if (ret) {
 530                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 531                          ret);
 532                 return ret;
 533         }
 534
 535         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 536
 537         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 538         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 539         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 540
 541         ret = hns3_cmd_send(hw, &desc, 1);
 542         if (ret)
 543                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 544                          ret);
 545         return ret;
 546 }
 547
 548 static int
 549 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 550                    uint16_t tpid)
 551 {
 552         struct hns3_adapter *hns = dev->data->dev_private;
 553         struct hns3_hw *hw = &hns->hw;
 554         int ret;
 555
 556         rte_spinlock_lock(&hw->lock);
 557         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 558         rte_spinlock_unlock(&hw->lock);
 559         return ret;
 560 }
 561
 562 static int
 563 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 564                              struct hns3_rx_vtag_cfg *vcfg)
 565 {
 566         struct hns3_vport_vtag_rx_cfg_cmd *req;
 567         struct hns3_hw *hw = &hns->hw;
 568         struct hns3_cmd_desc desc;
 569         uint16_t vport_id;
 570         uint8_t bitmap;
 571         int ret;
 572
 573         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 574
 575         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 576         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 577                      vcfg->strip_tag1_en ? 1 : 0);
 578         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 579                      vcfg->strip_tag2_en ? 1 : 0);
 580         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 581                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 582         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 583                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 584
 585         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 586         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 587                      vcfg->strip_tag1_discard_en ? 1 : 0);
 588         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 589                      vcfg->strip_tag2_discard_en ? 1 : 0);
 590         /*
 591          * In current version VF is not supported when PF is driven by DPDK
 592          * driver, just need to configure parameters for PF vport.
 593          */
 594         vport_id = HNS3_PF_FUNC_ID;
 595         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 596         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 597         req->vf_bitmap[req->vf_offset] = bitmap;
 598
 599         ret = hns3_cmd_send(hw, &desc, 1);
 600         if (ret)
 601                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 602         return ret;
 603 }
 604
 605 static void
 606 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 607                            struct hns3_rx_vtag_cfg *vcfg)
 608 {
 609         struct hns3_pf *pf = &hns->pf;
 610         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 611 }
 612
 613 static void
 614 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 615                            struct hns3_tx_vtag_cfg *vcfg)
 616 {
 617         struct hns3_pf *pf = &hns->pf;
 618         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 619 }
 620
 621 static int
 622 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 623 {
 624         struct hns3_rx_vtag_cfg rxvlan_cfg;
 625         struct hns3_hw *hw = &hns->hw;
 626         int ret;
 627
 628         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 629                 rxvlan_cfg.strip_tag1_en = false;
 630                 rxvlan_cfg.strip_tag2_en = enable;
 631                 rxvlan_cfg.strip_tag2_discard_en = false;
 632         } else {
 633                 rxvlan_cfg.strip_tag1_en = enable;
 634                 rxvlan_cfg.strip_tag2_en = true;
 635                 rxvlan_cfg.strip_tag2_discard_en = true;
 636         }
 637
 638         rxvlan_cfg.strip_tag1_discard_en = false;
 639         rxvlan_cfg.vlan1_vlan_prionly = false;
 640         rxvlan_cfg.vlan2_vlan_prionly = false;
 641         rxvlan_cfg.rx_vlan_offload_en = enable;
 642
 643         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 644         if (ret) {
 645                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 646                 return ret;
 647         }
 648
 649         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 656                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 657 {
 658         struct hns3_vlan_filter_ctrl_cmd *req;
 659         struct hns3_cmd_desc desc;
 660         int ret;
 661
 662         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 663
 664         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 665         req->vlan_type = vlan_type;
 666         req->vlan_fe = filter_en ? fe_type : 0;
 667         req->vf_id = vf_id;
 668
 669         ret = hns3_cmd_send(hw, &desc, 1);
 670         if (ret)
 671                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 672
 673         return ret;
 674 }
 675
 676 static int
 677 hns3_vlan_filter_init(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         int ret;
 681
 682         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 683                                         HNS3_FILTER_FE_EGRESS, false,
 684                                         HNS3_PF_FUNC_ID);
 685         if (ret) {
 686                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 687                 return ret;
 688         }
 689
 690         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 691                                         HNS3_FILTER_FE_INGRESS, false,
 692                                         HNS3_PF_FUNC_ID);
 693         if (ret)
 694                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 695
 696         return ret;
 697 }
 698
 699 static int
 700 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 701 {
 702         struct hns3_hw *hw = &hns->hw;
 703         int ret;
 704
 705         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 706                                         HNS3_FILTER_FE_INGRESS, enable,
 707                                         HNS3_PF_FUNC_ID);
 708         if (ret)
 709                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 710                          enable ? "enable" : "disable", ret);
 711
 712         return ret;
 713 }
 714
 715 static int
 716 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 717 {
 718         struct hns3_adapter *hns = dev->data->dev_private;
 719         struct hns3_hw *hw = &hns->hw;
 720         struct rte_eth_rxmode *rxmode;
 721         unsigned int tmp_mask;
 722         bool enable;
 723         int ret = 0;
 724
 725         rte_spinlock_lock(&hw->lock);
 726         rxmode = &dev->data->dev_conf.rxmode;
 727         tmp_mask = (unsigned int)mask;
 728         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 729                 /* ignore vlan filter configuration during promiscuous mode */
 730                 if (!dev->data->promiscuous) {
 731                         /* Enable or disable VLAN filter */
 732                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 733                                  true : false;
 734
 735                         ret = hns3_enable_vlan_filter(hns, enable);
 736                         if (ret) {
 737                                 rte_spinlock_unlock(&hw->lock);
 738                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 739                                          enable ? "enable" : "disable", ret);
 740                                 return ret;
 741                         }
 742                 }
 743         }
 744
 745         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 746                 /* Enable or disable VLAN stripping */
 747                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 748                     true : false;
 749
 750                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 751                 if (ret) {
 752                         rte_spinlock_unlock(&hw->lock);
 753                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 754                                  enable ? "enable" : "disable", ret);
 755                         return ret;
 756                 }
 757         }
 758
 759         rte_spinlock_unlock(&hw->lock);
 760
 761         return ret;
 762 }
 763
 764 static int
 765 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 766                              struct hns3_tx_vtag_cfg *vcfg)
 767 {
 768         struct hns3_vport_vtag_tx_cfg_cmd *req;
 769         struct hns3_cmd_desc desc;
 770         struct hns3_hw *hw = &hns->hw;
 771         uint16_t vport_id;
 772         uint8_t bitmap;
 773         int ret;
 774
 775         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 776
 777         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 778         req->def_vlan_tag1 = vcfg->default_tag1;
 779         req->def_vlan_tag2 = vcfg->default_tag2;
 780         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 781                      vcfg->accept_tag1 ? 1 : 0);
 782         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 783                      vcfg->accept_untag1 ? 1 : 0);
 784         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 785                      vcfg->accept_tag2 ? 1 : 0);
 786         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 787                      vcfg->accept_untag2 ? 1 : 0);
 788         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 789                      vcfg->insert_tag1_en ? 1 : 0);
 790         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 791                      vcfg->insert_tag2_en ? 1 : 0);
 792         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 793
 794         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 795         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 796                      vcfg->tag_shift_mode_en ? 1 : 0);
 797
 798         /*
 799          * In current version VF is not supported when PF is driven by DPDK
 800          * driver, just need to configure parameters for PF vport.
 801          */
 802         vport_id = HNS3_PF_FUNC_ID;
 803         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 804         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 805         req->vf_bitmap[req->vf_offset] = bitmap;
 806
 807         ret = hns3_cmd_send(hw, &desc, 1);
 808         if (ret)
 809                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 810
 811         return ret;
 812 }
 813
 814 static int
 815 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 816                      uint16_t pvid)
 817 {
 818         struct hns3_hw *hw = &hns->hw;
 819         struct hns3_tx_vtag_cfg txvlan_cfg;
 820         int ret;
 821
 822         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 823                 txvlan_cfg.accept_tag1 = true;
 824                 txvlan_cfg.insert_tag1_en = false;
 825                 txvlan_cfg.default_tag1 = 0;
 826         } else {
 827                 txvlan_cfg.accept_tag1 =
 828                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 829                 txvlan_cfg.insert_tag1_en = true;
 830                 txvlan_cfg.default_tag1 = pvid;
 831         }
 832
 833         txvlan_cfg.accept_untag1 = true;
 834         txvlan_cfg.accept_tag2 = true;
 835         txvlan_cfg.accept_untag2 = true;
 836         txvlan_cfg.insert_tag2_en = false;
 837         txvlan_cfg.default_tag2 = 0;
 838         txvlan_cfg.tag_shift_mode_en = true;
 839
 840         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 841         if (ret) {
 842                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 843                          ret);
 844                 return ret;
 845         }
 846
 847         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 848         return ret;
 849 }
 850
 851
 852 static void
 853 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 854 {
 855         struct hns3_user_vlan_table *vlan_entry;
 856         struct hns3_pf *pf = &hns->pf;
 857
 858         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 859                 if (vlan_entry->hd_tbl_status) {
 860                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 861                         vlan_entry->hd_tbl_status = false;
 862                 }
 863         }
 864
 865         if (is_del_list) {
 866                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 867                 while (vlan_entry) {
 868                         LIST_REMOVE(vlan_entry, next);
 869                         rte_free(vlan_entry);
 870                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 871                 }
 872         }
 873 }
 874
 875 static void
 876 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 877 {
 878         struct hns3_user_vlan_table *vlan_entry;
 879         struct hns3_pf *pf = &hns->pf;
 880
 881         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 882                 if (!vlan_entry->hd_tbl_status) {
 883                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 884                         vlan_entry->hd_tbl_status = true;
 885                 }
 886         }
 887 }
 888
 889 static void
 890 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 891 {
 892         struct hns3_hw *hw = &hns->hw;
 893         int ret;
 894
 895         hns3_rm_all_vlan_table(hns, true);
 896         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 897                 ret = hns3_set_port_vlan_filter(hns,
 898                                                 hw->port_base_vlan_cfg.pvid, 0);
 899                 if (ret) {
 900                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 901                                  ret);
 902                         return;
 903                 }
 904         }
 905 }
 906
 907 static int
 908 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 909                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 910 {
 911         struct hns3_hw *hw = &hns->hw;
 912         uint16_t old_pvid;
 913         int ret;
 914
 915         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 916                 old_pvid = hw->port_base_vlan_cfg.pvid;
 917                 if (old_pvid != HNS3_INVALID_PVID) {
 918                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 919                         if (ret) {
 920                                 hns3_err(hw, "failed to remove old pvid %u, "
 921                                                 "ret = %d", old_pvid, ret);
 922                                 return ret;
 923                         }
 924                 }
 925
 926                 hns3_rm_all_vlan_table(hns, false);
 927                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 928                 if (ret) {
 929                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 930                                         new_pvid, ret);
 931                         return ret;
 932                 }
 933         } else {
 934                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 935                 if (ret) {
 936                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 937                                         new_pvid, ret);
 938                         return ret;
 939                 }
 940
 941                 hns3_add_all_vlan_table(hns);
 942         }
 943         return 0;
 944 }
 945
 946 static int
 947 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 948 {
 949         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 950         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 951         bool rx_strip_en;
 952         int ret;
 953
 954         rx_strip_en = old_cfg->rx_vlan_offload_en;
 955         if (on) {
 956                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 957                 rx_vlan_cfg.strip_tag2_en = true;
 958                 rx_vlan_cfg.strip_tag2_discard_en = true;
 959         } else {
 960                 rx_vlan_cfg.strip_tag1_en = false;
 961                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 962                 rx_vlan_cfg.strip_tag2_discard_en = false;
 963         }
 964         rx_vlan_cfg.strip_tag1_discard_en = false;
 965         rx_vlan_cfg.vlan1_vlan_prionly = false;
 966         rx_vlan_cfg.vlan2_vlan_prionly = false;
 967         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 968
 969         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 970         if (ret)
 971                 return ret;
 972
 973         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 974         return ret;
 975 }
 976
 977 static int
 978 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 979 {
 980         struct hns3_hw *hw = &hns->hw;
 981         uint16_t port_base_vlan_state;
 982         int ret, err;
 983
 984         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 985                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 986                         hns3_warn(hw, "Invalid operation! As current pvid set "
 987                                   "is %u, disable pvid %u is invalid",
 988                                   hw->port_base_vlan_cfg.pvid, pvid);
 989                 return 0;
 990         }
 991
 992         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 993                                     HNS3_PORT_BASE_VLAN_DISABLE;
 994         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 995         if (ret) {
 996                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 997                          ret);
 998                 return ret;
 999         }
1000
1001         ret = hns3_en_pvid_strip(hns, on);
1002         if (ret) {
1003                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1004                          "ret = %d", ret);
1005                 goto pvid_vlan_strip_fail;
1006         }
1007
1008         if (pvid == HNS3_INVALID_PVID)
1009                 goto out;
1010         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1011         if (ret) {
1012                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1013                          ret);
1014                 goto vlan_filter_set_fail;
1015         }
1016
1017 out:
1018         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1019         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1020         return ret;
1021
1022 vlan_filter_set_fail:
1023         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1024                                         HNS3_PORT_BASE_VLAN_ENABLE);
1025         if (err)
1026                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1027
1028 pvid_vlan_strip_fail:
1029         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1030                                         hw->port_base_vlan_cfg.pvid);
1031         if (err)
1032                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1039 {
1040         struct hns3_adapter *hns = dev->data->dev_private;
1041         struct hns3_hw *hw = &hns->hw;
1042         bool pvid_en_state_change;
1043         uint16_t pvid_state;
1044         int ret;
1045
1046         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1047                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1048                          RTE_ETHER_MAX_VLAN_ID);
1049                 return -EINVAL;
1050         }
1051
1052         /*
1053          * If PVID configuration state change, should refresh the PVID
1054          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1055          */
1056         pvid_state = hw->port_base_vlan_cfg.state;
1057         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1058             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1059                 pvid_en_state_change = false;
1060         else
1061                 pvid_en_state_change = true;
1062
1063         rte_spinlock_lock(&hw->lock);
1064         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1065         rte_spinlock_unlock(&hw->lock);
1066         if (ret)
1067                 return ret;
1068         /*
1069          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1070          * need be processed by PMD driver.
1071          */
1072         if (pvid_en_state_change &&
1073             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1074                 hns3_update_all_queues_pvid_proc_en(hw);
1075
1076         return 0;
1077 }
1078
1079 static int
1080 hns3_default_vlan_config(struct hns3_adapter *hns)
1081 {
1082         struct hns3_hw *hw = &hns->hw;
1083         int ret;
1084
1085         /*
1086          * When vlan filter is enabled, hardware regards packets without vlan
1087          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1088          * table, packets without vlan won't be received. So, add vlan 0 as
1089          * the default vlan.
1090          */
1091         ret = hns3_vlan_filter_configure(hns, 0, 1);
1092         if (ret)
1093                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1094         return ret;
1095 }
1096
1097 static int
1098 hns3_init_vlan_config(struct hns3_adapter *hns)
1099 {
1100         struct hns3_hw *hw = &hns->hw;
1101         int ret;
1102
1103         /*
1104          * This function can be called in the initialization and reset process,
1105          * when in reset process, it means that hardware had been reseted
1106          * successfully and we need to restore the hardware configuration to
1107          * ensure that the hardware configuration remains unchanged before and
1108          * after reset.
1109          */
1110         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1111                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1112                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1113         }
1114
1115         ret = hns3_vlan_filter_init(hns);
1116         if (ret) {
1117                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1118                 return ret;
1119         }
1120
1121         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1122                                        RTE_ETHER_TYPE_VLAN);
1123         if (ret) {
1124                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1125                 return ret;
1126         }
1127
1128         /*
1129          * When in the reinit dev stage of the reset process, the following
1130          * vlan-related configurations may differ from those at initialization,
1131          * we will restore configurations to hardware in hns3_restore_vlan_table
1132          * and hns3_restore_vlan_conf later.
1133          */
1134         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1135                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1136                 if (ret) {
1137                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1138                         return ret;
1139                 }
1140
1141                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1142                 if (ret) {
1143                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1144                                  ret);
1145                         return ret;
1146                 }
1147         }
1148
1149         return hns3_default_vlan_config(hns);
1150 }
1151
1152 static int
1153 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1154 {
1155         struct hns3_pf *pf = &hns->pf;
1156         struct hns3_hw *hw = &hns->hw;
1157         uint64_t offloads;
1158         bool enable;
1159         int ret;
1160
1161         if (!hw->data->promiscuous) {
1162                 /* restore vlan filter states */
1163                 offloads = hw->data->dev_conf.rxmode.offloads;
1164                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1165                 ret = hns3_enable_vlan_filter(hns, enable);
1166                 if (ret) {
1167                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1168                                  "ret = %d", ret);
1169                         return ret;
1170                 }
1171         }
1172
1173         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1174         if (ret) {
1175                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1176                 return ret;
1177         }
1178
1179         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1180         if (ret)
1181                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1182
1183         return ret;
1184 }
1185
1186 static int
1187 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1188 {
1189         struct hns3_adapter *hns = dev->data->dev_private;
1190         struct rte_eth_dev_data *data = dev->data;
1191         struct rte_eth_txmode *txmode;
1192         struct hns3_hw *hw = &hns->hw;
1193         int mask;
1194         int ret;
1195
1196         txmode = &data->dev_conf.txmode;
1197         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1198                 hns3_warn(hw,
1199                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1200                           "configuration is not supported! Ignore these two "
1201                           "parameters: hw_vlan_reject_tagged(%u), "
1202                           "hw_vlan_reject_untagged(%u)",
1203                           txmode->hw_vlan_reject_tagged,
1204                           txmode->hw_vlan_reject_untagged);
1205
1206         /* Apply vlan offload setting */
1207         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1208         ret = hns3_vlan_offload_set(dev, mask);
1209         if (ret) {
1210                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1211                          ret);
1212                 return ret;
1213         }
1214
1215         /*
1216          * If pvid config is not set in rte_eth_conf, driver needn't to set
1217          * VLAN pvid related configuration to hardware.
1218          */
1219         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1220                 return 0;
1221
1222         /* Apply pvid setting */
1223         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1224                                  txmode->hw_vlan_insert_pvid);
1225         if (ret)
1226                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1227                          txmode->pvid, ret);
1228
1229         return ret;
1230 }
1231
1232 static int
1233 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1234                 unsigned int tso_mss_max)
1235 {
1236         struct hns3_cfg_tso_status_cmd *req;
1237         struct hns3_cmd_desc desc;
1238         uint16_t tso_mss;
1239
1240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1241
1242         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1243
1244         tso_mss = 0;
1245         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1246                        tso_mss_min);
1247         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1248
1249         tso_mss = 0;
1250         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1251                        tso_mss_max);
1252         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1253
1254         return hns3_cmd_send(hw, &desc, 1);
1255 }
1256
1257 static int
1258 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1259                    uint16_t *allocated_size, bool is_alloc)
1260 {
1261         struct hns3_umv_spc_alc_cmd *req;
1262         struct hns3_cmd_desc desc;
1263         int ret;
1264
1265         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1266         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1267         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1268         req->space_size = rte_cpu_to_le_32(space_size);
1269
1270         ret = hns3_cmd_send(hw, &desc, 1);
1271         if (ret) {
1272                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1273                              is_alloc ? "allocate" : "free", ret);
1274                 return ret;
1275         }
1276
1277         if (is_alloc && allocated_size)
1278                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1279
1280         return 0;
1281 }
1282
1283 static int
1284 hns3_init_umv_space(struct hns3_hw *hw)
1285 {
1286         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1287         struct hns3_pf *pf = &hns->pf;
1288         uint16_t allocated_size = 0;
1289         int ret;
1290
1291         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1292                                  true);
1293         if (ret)
1294                 return ret;
1295
1296         if (allocated_size < pf->wanted_umv_size)
1297                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1298                              pf->wanted_umv_size, allocated_size);
1299
1300         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1301                                                 pf->wanted_umv_size;
1302         pf->used_umv_size = 0;
1303         return 0;
1304 }
1305
1306 static int
1307 hns3_uninit_umv_space(struct hns3_hw *hw)
1308 {
1309         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1310         struct hns3_pf *pf = &hns->pf;
1311         int ret;
1312
1313         if (pf->max_umv_size == 0)
1314                 return 0;
1315
1316         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1317         if (ret)
1318                 return ret;
1319
1320         pf->max_umv_size = 0;
1321
1322         return 0;
1323 }
1324
1325 static bool
1326 hns3_is_umv_space_full(struct hns3_hw *hw)
1327 {
1328         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1329         struct hns3_pf *pf = &hns->pf;
1330         bool is_full;
1331
1332         is_full = (pf->used_umv_size >= pf->max_umv_size);
1333
1334         return is_full;
1335 }
1336
1337 static void
1338 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1339 {
1340         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1341         struct hns3_pf *pf = &hns->pf;
1342
1343         if (is_free) {
1344                 if (pf->used_umv_size > 0)
1345                         pf->used_umv_size--;
1346         } else
1347                 pf->used_umv_size++;
1348 }
1349
1350 static void
1351 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1352                       const uint8_t *addr, bool is_mc)
1353 {
1354         const unsigned char *mac_addr = addr;
1355         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1356                             ((uint32_t)mac_addr[2] << 16) |
1357                             ((uint32_t)mac_addr[1] << 8) |
1358                             (uint32_t)mac_addr[0];
1359         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1360
1361         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1362         if (is_mc) {
1363                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1365                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1366         }
1367
1368         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1369         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1370 }
1371
1372 static int
1373 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1374                              uint8_t resp_code,
1375                              enum hns3_mac_vlan_tbl_opcode op)
1376 {
1377         if (cmdq_resp) {
1378                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1379                          cmdq_resp);
1380                 return -EIO;
1381         }
1382
1383         if (op == HNS3_MAC_VLAN_ADD) {
1384                 if (resp_code == 0 || resp_code == 1) {
1385                         return 0;
1386                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1387                         hns3_err(hw, "add mac addr failed for uc_overflow");
1388                         return -ENOSPC;
1389                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1390                         hns3_err(hw, "add mac addr failed for mc_overflow");
1391                         return -ENOSPC;
1392                 }
1393
1394                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1395                          resp_code);
1396                 return -EIO;
1397         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1398                 if (resp_code == 0) {
1399                         return 0;
1400                 } else if (resp_code == 1) {
1401                         hns3_dbg(hw, "remove mac addr failed for miss");
1402                         return -ENOENT;
1403                 }
1404
1405                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1406                          resp_code);
1407                 return -EIO;
1408         } else if (op == HNS3_MAC_VLAN_LKUP) {
1409                 if (resp_code == 0) {
1410                         return 0;
1411                 } else if (resp_code == 1) {
1412                         hns3_dbg(hw, "lookup mac addr failed for miss");
1413                         return -ENOENT;
1414                 }
1415
1416                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1417                          resp_code);
1418                 return -EIO;
1419         }
1420
1421         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1422                  op);
1423
1424         return -EINVAL;
1425 }
1426
1427 static int
1428 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1429                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1430                          struct hns3_cmd_desc *desc, bool is_mc)
1431 {
1432         uint8_t resp_code;
1433         uint16_t retval;
1434         int ret;
1435
1436         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1437         if (is_mc) {
1438                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1439                 memcpy(desc[0].data, req,
1440                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1441                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1442                                           true);
1443                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1444                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1445                                           true);
1446                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1447         } else {
1448                 memcpy(desc[0].data, req,
1449                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1450                 ret = hns3_cmd_send(hw, desc, 1);
1451         }
1452         if (ret) {
1453                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1454                          ret);
1455                 return ret;
1456         }
1457         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1458         retval = rte_le_to_cpu_16(desc[0].retval);
1459
1460         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1461                                             HNS3_MAC_VLAN_LKUP);
1462 }
1463
1464 static int
1465 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1466                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1467                       struct hns3_cmd_desc *mc_desc)
1468 {
1469         uint8_t resp_code;
1470         uint16_t retval;
1471         int cfg_status;
1472         int ret;
1473
1474         if (mc_desc == NULL) {
1475                 struct hns3_cmd_desc desc;
1476
1477                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1478                 memcpy(desc.data, req,
1479                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1480                 ret = hns3_cmd_send(hw, &desc, 1);
1481                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1482                 retval = rte_le_to_cpu_16(desc.retval);
1483
1484                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1485                                                           HNS3_MAC_VLAN_ADD);
1486         } else {
1487                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1488                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1489                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1490                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1491                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1492                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1493                 memcpy(mc_desc[0].data, req,
1494                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1495                 mc_desc[0].retval = 0;
1496                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1497                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1498                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1499
1500                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1501                                                           HNS3_MAC_VLAN_ADD);
1502         }
1503
1504         if (ret) {
1505                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1506                 return ret;
1507         }
1508
1509         return cfg_status;
1510 }
1511
1512 static int
1513 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1514                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1515 {
1516         struct hns3_cmd_desc desc;
1517         uint8_t resp_code;
1518         uint16_t retval;
1519         int ret;
1520
1521         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1522
1523         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1524
1525         ret = hns3_cmd_send(hw, &desc, 1);
1526         if (ret) {
1527                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1528                 return ret;
1529         }
1530         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1531         retval = rte_le_to_cpu_16(desc.retval);
1532
1533         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1534                                             HNS3_MAC_VLAN_REMOVE);
1535 }
1536
1537 static int
1538 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1539 {
1540         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1541         struct hns3_mac_vlan_tbl_entry_cmd req;
1542         struct hns3_pf *pf = &hns->pf;
1543         struct hns3_cmd_desc desc[3];
1544         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1545         uint16_t egress_port = 0;
1546         uint8_t vf_id;
1547         int ret;
1548
1549         /* check if mac addr is valid */
1550         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1551                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1552                                       mac_addr);
1553                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1554                          mac_str);
1555                 return -EINVAL;
1556         }
1557
1558         memset(&req, 0, sizeof(req));
1559
1560         /*
1561          * In current version VF is not supported when PF is driven by DPDK
1562          * driver, just need to configure parameters for PF vport.
1563          */
1564         vf_id = HNS3_PF_FUNC_ID;
1565         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1566                        HNS3_MAC_EPORT_VFID_S, vf_id);
1567
1568         req.egress_port = rte_cpu_to_le_16(egress_port);
1569
1570         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1571
1572         /*
1573          * Lookup the mac address in the mac_vlan table, and add
1574          * it if the entry is inexistent. Repeated unicast entry
1575          * is not allowed in the mac vlan table.
1576          */
1577         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1578         if (ret == -ENOENT) {
1579                 if (!hns3_is_umv_space_full(hw)) {
1580                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1581                         if (!ret)
1582                                 hns3_update_umv_space(hw, false);
1583                         return ret;
1584                 }
1585
1586                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1587
1588                 return -ENOSPC;
1589         }
1590
1591         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1592
1593         /* check if we just hit the duplicate */
1594         if (ret == 0) {
1595                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1596                 return 0;
1597         }
1598
1599         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1600                  mac_str);
1601
1602         return ret;
1603 }
1604
1605 static int
1606 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1607 {
1608         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1609         struct rte_ether_addr *addr;
1610         int ret;
1611         int i;
1612
1613         for (i = 0; i < hw->mc_addrs_num; i++) {
1614                 addr = &hw->mc_addrs[i];
1615                 /* Check if there are duplicate addresses */
1616                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1617                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1618                                               addr);
1619                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1620                                  "(%s) is added by the set_mc_mac_addr_list "
1621                                  "API", mac_str);
1622                         return -EINVAL;
1623                 }
1624         }
1625
1626         ret = hns3_add_mc_addr(hw, mac_addr);
1627         if (ret) {
1628                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                       mac_addr);
1630                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1631                          mac_str, ret);
1632         }
1633         return ret;
1634 }
1635
1636 static int
1637 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1638 {
1639         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1640         int ret;
1641
1642         ret = hns3_remove_mc_addr(hw, mac_addr);
1643         if (ret) {
1644                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1645                                       mac_addr);
1646                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1647                          mac_str, ret);
1648         }
1649         return ret;
1650 }
1651
1652 static int
1653 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1654                   uint32_t idx, __rte_unused uint32_t pool)
1655 {
1656         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1658         int ret;
1659
1660         rte_spinlock_lock(&hw->lock);
1661
1662         /*
1663          * In hns3 network engine adding UC and MC mac address with different
1664          * commands with firmware. We need to determine whether the input
1665          * address is a UC or a MC address to call different commands.
1666          * By the way, it is recommended calling the API function named
1667          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1668          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1669          * may affect the specifications of UC mac addresses.
1670          */
1671         if (rte_is_multicast_ether_addr(mac_addr))
1672                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1673         else
1674                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1675
1676         if (ret) {
1677                 rte_spinlock_unlock(&hw->lock);
1678                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1679                                       mac_addr);
1680                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1681                          ret);
1682                 return ret;
1683         }
1684
1685         if (idx == 0)
1686                 hw->mac.default_addr_setted = true;
1687         rte_spinlock_unlock(&hw->lock);
1688
1689         return ret;
1690 }
1691
1692 static int
1693 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1694 {
1695         struct hns3_mac_vlan_tbl_entry_cmd req;
1696         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1697         int ret;
1698
1699         /* check if mac addr is valid */
1700         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1701                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1702                                       mac_addr);
1703                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1704                          mac_str);
1705                 return -EINVAL;
1706         }
1707
1708         memset(&req, 0, sizeof(req));
1709         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1710         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1711         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1712         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1713                 return 0;
1714         else if (ret == 0)
1715                 hns3_update_umv_space(hw, true);
1716
1717         return ret;
1718 }
1719
1720 static void
1721 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1722 {
1723         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724         /* index will be checked by upper level rte interface */
1725         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1726         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1727         int ret;
1728
1729         rte_spinlock_lock(&hw->lock);
1730
1731         if (rte_is_multicast_ether_addr(mac_addr))
1732                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1733         else
1734                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1735         rte_spinlock_unlock(&hw->lock);
1736         if (ret) {
1737                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1738                                       mac_addr);
1739                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1740                          ret);
1741         }
1742 }
1743
1744 static int
1745 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1746                           struct rte_ether_addr *mac_addr)
1747 {
1748         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749         struct rte_ether_addr *oaddr;
1750         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1751         bool default_addr_setted;
1752         bool rm_succes = false;
1753         int ret, ret_val;
1754
1755         /*
1756          * It has been guaranteed that input parameter named mac_addr is valid
1757          * address in the rte layer of DPDK framework.
1758          */
1759         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1760         default_addr_setted = hw->mac.default_addr_setted;
1761         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1762                 return 0;
1763
1764         rte_spinlock_lock(&hw->lock);
1765         if (default_addr_setted) {
1766                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1767                 if (ret) {
1768                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1769                                               oaddr);
1770                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1771                                   mac_str, ret);
1772                         rm_succes = false;
1773                 } else
1774                         rm_succes = true;
1775         }
1776
1777         ret = hns3_add_uc_addr_common(hw, mac_addr);
1778         if (ret) {
1779                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1780                                       mac_addr);
1781                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1782                 goto err_add_uc_addr;
1783         }
1784
1785         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1786         if (ret) {
1787                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1788                 goto err_pause_addr_cfg;
1789         }
1790
1791         rte_ether_addr_copy(mac_addr,
1792                             (struct rte_ether_addr *)hw->mac.mac_addr);
1793         hw->mac.default_addr_setted = true;
1794         rte_spinlock_unlock(&hw->lock);
1795
1796         return 0;
1797
1798 err_pause_addr_cfg:
1799         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1800         if (ret_val) {
1801                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1802                                       mac_addr);
1803                 hns3_warn(hw,
1804                           "Failed to roll back to del setted mac addr(%s): %d",
1805                           mac_str, ret_val);
1806         }
1807
1808 err_add_uc_addr:
1809         if (rm_succes) {
1810                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1811                 if (ret_val) {
1812                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1813                                               oaddr);
1814                         hns3_warn(hw,
1815                                   "Failed to restore old uc mac addr(%s): %d",
1816                                   mac_str, ret_val);
1817                         hw->mac.default_addr_setted = false;
1818                 }
1819         }
1820         rte_spinlock_unlock(&hw->lock);
1821
1822         return ret;
1823 }
1824
1825 static int
1826 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1827 {
1828         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1829         struct hns3_hw *hw = &hns->hw;
1830         struct rte_ether_addr *addr;
1831         int err = 0;
1832         int ret;
1833         int i;
1834
1835         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1836                 addr = &hw->data->mac_addrs[i];
1837                 if (rte_is_zero_ether_addr(addr))
1838                         continue;
1839                 if (rte_is_multicast_ether_addr(addr))
1840                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1841                               hns3_add_mc_addr(hw, addr);
1842                 else
1843                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1844                               hns3_add_uc_addr_common(hw, addr);
1845
1846                 if (ret) {
1847                         err = ret;
1848                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1849                                               addr);
1850                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1851                                  "ret = %d.", del ? "remove" : "restore",
1852                                  mac_str, i, ret);
1853                 }
1854         }
1855         return err;
1856 }
1857
1858 static void
1859 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1860 {
1861 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1862         uint8_t word_num;
1863         uint8_t bit_num;
1864
1865         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1866                 word_num = vfid / 32;
1867                 bit_num = vfid % 32;
1868                 if (clr)
1869                         desc[1].data[word_num] &=
1870                             rte_cpu_to_le_32(~(1UL << bit_num));
1871                 else
1872                         desc[1].data[word_num] |=
1873                             rte_cpu_to_le_32(1UL << bit_num);
1874         } else {
1875                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1876                 bit_num = vfid % 32;
1877                 if (clr)
1878                         desc[2].data[word_num] &=
1879                             rte_cpu_to_le_32(~(1UL << bit_num));
1880                 else
1881                         desc[2].data[word_num] |=
1882                             rte_cpu_to_le_32(1UL << bit_num);
1883         }
1884 }
1885
1886 static int
1887 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1888 {
1889         struct hns3_mac_vlan_tbl_entry_cmd req;
1890         struct hns3_cmd_desc desc[3];
1891         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1892         uint8_t vf_id;
1893         int ret;
1894
1895         /* Check if mac addr is valid */
1896         if (!rte_is_multicast_ether_addr(mac_addr)) {
1897                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1898                                       mac_addr);
1899                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1900                          mac_str);
1901                 return -EINVAL;
1902         }
1903
1904         memset(&req, 0, sizeof(req));
1905         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1906         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1907         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1908         if (ret) {
1909                 /* This mac addr do not exist, add new entry for it */
1910                 memset(desc[0].data, 0, sizeof(desc[0].data));
1911                 memset(desc[1].data, 0, sizeof(desc[0].data));
1912                 memset(desc[2].data, 0, sizeof(desc[0].data));
1913         }
1914
1915         /*
1916          * In current version VF is not supported when PF is driven by DPDK
1917          * driver, just need to configure parameters for PF vport.
1918          */
1919         vf_id = HNS3_PF_FUNC_ID;
1920         hns3_update_desc_vfid(desc, vf_id, false);
1921         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1922         if (ret) {
1923                 if (ret == -ENOSPC)
1924                         hns3_err(hw, "mc mac vlan table is full");
1925                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1926                                       mac_addr);
1927                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1928         }
1929
1930         return ret;
1931 }
1932
1933 static int
1934 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1935 {
1936         struct hns3_mac_vlan_tbl_entry_cmd req;
1937         struct hns3_cmd_desc desc[3];
1938         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1939         uint8_t vf_id;
1940         int ret;
1941
1942         /* Check if mac addr is valid */
1943         if (!rte_is_multicast_ether_addr(mac_addr)) {
1944                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1945                                       mac_addr);
1946                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1947                          mac_str);
1948                 return -EINVAL;
1949         }
1950
1951         memset(&req, 0, sizeof(req));
1952         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1953         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1954         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1955         if (ret == 0) {
1956                 /*
1957                  * This mac addr exist, remove this handle's VFID for it.
1958                  * In current version VF is not supported when PF is driven by
1959                  * DPDK driver, just need to configure parameters for PF vport.
1960                  */
1961                 vf_id = HNS3_PF_FUNC_ID;
1962                 hns3_update_desc_vfid(desc, vf_id, true);
1963
1964                 /* All the vfid is zero, so need to delete this entry */
1965                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1966         } else if (ret == -ENOENT) {
1967                 /* This mac addr doesn't exist. */
1968                 return 0;
1969         }
1970
1971         if (ret) {
1972                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1973                                       mac_addr);
1974                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1975         }
1976
1977         return ret;
1978 }
1979
1980 static int
1981 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1982                            struct rte_ether_addr *mc_addr_set,
1983                            uint32_t nb_mc_addr)
1984 {
1985         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1986         struct rte_ether_addr *addr;
1987         uint32_t i;
1988         uint32_t j;
1989
1990         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1991                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1992                          "invalid. valid range: 0~%d",
1993                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1994                 return -EINVAL;
1995         }
1996
1997         /* Check if input mac addresses are valid */
1998         for (i = 0; i < nb_mc_addr; i++) {
1999                 addr = &mc_addr_set[i];
2000                 if (!rte_is_multicast_ether_addr(addr)) {
2001                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2002                                               addr);
2003                         hns3_err(hw,
2004                                  "failed to set mc mac addr, addr(%s) invalid.",
2005                                  mac_str);
2006                         return -EINVAL;
2007                 }
2008
2009                 /* Check if there are duplicate addresses */
2010                 for (j = i + 1; j < nb_mc_addr; j++) {
2011                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2012                                 hns3_ether_format_addr(mac_str,
2013                                                       RTE_ETHER_ADDR_FMT_SIZE,
2014                                                       addr);
2015                                 hns3_err(hw, "failed to set mc mac addr, "
2016                                          "addrs invalid. two same addrs(%s).",
2017                                          mac_str);
2018                                 return -EINVAL;
2019                         }
2020                 }
2021
2022                 /*
2023                  * Check if there are duplicate addresses between mac_addrs
2024                  * and mc_addr_set
2025                  */
2026                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2027                         if (rte_is_same_ether_addr(addr,
2028                                                    &hw->data->mac_addrs[j])) {
2029                                 hns3_ether_format_addr(mac_str,
2030                                                       RTE_ETHER_ADDR_FMT_SIZE,
2031                                                       addr);
2032                                 hns3_err(hw, "failed to set mc mac addr, "
2033                                          "addrs invalid. addrs(%s) has already "
2034                                          "configured in mac_addr add API",
2035                                          mac_str);
2036                                 return -EINVAL;
2037                         }
2038                 }
2039         }
2040
2041         return 0;
2042 }
2043
2044 static void
2045 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2046                            struct rte_ether_addr *mc_addr_set,
2047                            int mc_addr_num,
2048                            struct rte_ether_addr *reserved_addr_list,
2049                            int *reserved_addr_num,
2050                            struct rte_ether_addr *add_addr_list,
2051                            int *add_addr_num,
2052                            struct rte_ether_addr *rm_addr_list,
2053                            int *rm_addr_num)
2054 {
2055         struct rte_ether_addr *addr;
2056         int current_addr_num;
2057         int reserved_num = 0;
2058         int add_num = 0;
2059         int rm_num = 0;
2060         int num;
2061         int i;
2062         int j;
2063         bool same_addr;
2064
2065         /* Calculate the mc mac address list that should be removed */
2066         current_addr_num = hw->mc_addrs_num;
2067         for (i = 0; i < current_addr_num; i++) {
2068                 addr = &hw->mc_addrs[i];
2069                 same_addr = false;
2070                 for (j = 0; j < mc_addr_num; j++) {
2071                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2072                                 same_addr = true;
2073                                 break;
2074                         }
2075                 }
2076
2077                 if (!same_addr) {
2078                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2079                         rm_num++;
2080                 } else {
2081                         rte_ether_addr_copy(addr,
2082                                             &reserved_addr_list[reserved_num]);
2083                         reserved_num++;
2084                 }
2085         }
2086
2087         /* Calculate the mc mac address list that should be added */
2088         for (i = 0; i < mc_addr_num; i++) {
2089                 addr = &mc_addr_set[i];
2090                 same_addr = false;
2091                 for (j = 0; j < current_addr_num; j++) {
2092                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2093                                 same_addr = true;
2094                                 break;
2095                         }
2096                 }
2097
2098                 if (!same_addr) {
2099                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2100                         add_num++;
2101                 }
2102         }
2103
2104         /* Reorder the mc mac address list maintained by driver */
2105         for (i = 0; i < reserved_num; i++)
2106                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2107
2108         for (i = 0; i < rm_num; i++) {
2109                 num = reserved_num + i;
2110                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2111         }
2112
2113         *reserved_addr_num = reserved_num;
2114         *add_addr_num = add_num;
2115         *rm_addr_num = rm_num;
2116 }
2117
2118 static int
2119 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2120                           struct rte_ether_addr *mc_addr_set,
2121                           uint32_t nb_mc_addr)
2122 {
2123         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2124         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2125         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2126         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr *addr;
2128         int reserved_addr_num;
2129         int add_addr_num;
2130         int rm_addr_num;
2131         int mc_addr_num;
2132         int num;
2133         int ret;
2134         int i;
2135
2136         /* Check if input parameters are valid */
2137         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2138         if (ret)
2139                 return ret;
2140
2141         rte_spinlock_lock(&hw->lock);
2142
2143         /*
2144          * Calculate the mc mac address lists those should be removed and be
2145          * added, Reorder the mc mac address list maintained by driver.
2146          */
2147         mc_addr_num = (int)nb_mc_addr;
2148         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2149                                    reserved_addr_list, &reserved_addr_num,
2150                                    add_addr_list, &add_addr_num,
2151                                    rm_addr_list, &rm_addr_num);
2152
2153         /* Remove mc mac addresses */
2154         for (i = 0; i < rm_addr_num; i++) {
2155                 num = rm_addr_num - i - 1;
2156                 addr = &rm_addr_list[num];
2157                 ret = hns3_remove_mc_addr(hw, addr);
2158                 if (ret) {
2159                         rte_spinlock_unlock(&hw->lock);
2160                         return ret;
2161                 }
2162                 hw->mc_addrs_num--;
2163         }
2164
2165         /* Add mc mac addresses */
2166         for (i = 0; i < add_addr_num; i++) {
2167                 addr = &add_addr_list[i];
2168                 ret = hns3_add_mc_addr(hw, addr);
2169                 if (ret) {
2170                         rte_spinlock_unlock(&hw->lock);
2171                         return ret;
2172                 }
2173
2174                 num = reserved_addr_num + i;
2175                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2176                 hw->mc_addrs_num++;
2177         }
2178         rte_spinlock_unlock(&hw->lock);
2179
2180         return 0;
2181 }
2182
2183 static int
2184 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2185 {
2186         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2187         struct hns3_hw *hw = &hns->hw;
2188         struct rte_ether_addr *addr;
2189         int err = 0;
2190         int ret;
2191         int i;
2192
2193         for (i = 0; i < hw->mc_addrs_num; i++) {
2194                 addr = &hw->mc_addrs[i];
2195                 if (!rte_is_multicast_ether_addr(addr))
2196                         continue;
2197                 if (del)
2198                         ret = hns3_remove_mc_addr(hw, addr);
2199                 else
2200                         ret = hns3_add_mc_addr(hw, addr);
2201                 if (ret) {
2202                         err = ret;
2203                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2204                                               addr);
2205                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2206                                  del ? "Remove" : "Restore", mac_str, ret);
2207                 }
2208         }
2209         return err;
2210 }
2211
2212 static int
2213 hns3_check_mq_mode(struct rte_eth_dev *dev)
2214 {
2215         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2216         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2217         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2218         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2219         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2220         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2221         uint8_t num_tc;
2222         int max_tc = 0;
2223         int i;
2224
2225         if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2226             (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2227              tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2228                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2229                          rx_mq_mode, tx_mq_mode);
2230                 return -EOPNOTSUPP;
2231         }
2232
2233         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2234         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2235         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2236                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2237                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2238                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2239                         return -EINVAL;
2240                 }
2241
2242                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2243                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2244                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2245                                  "nb_tcs(%d) != %d or %d in rx direction.",
2246                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2247                         return -EINVAL;
2248                 }
2249
2250                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2251                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2252                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2253                         return -EINVAL;
2254                 }
2255
2256                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2257                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2258                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2259                                          "is not equal to one in tx direction.",
2260                                          i, dcb_rx_conf->dcb_tc[i]);
2261                                 return -EINVAL;
2262                         }
2263                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2264                                 max_tc = dcb_rx_conf->dcb_tc[i];
2265                 }
2266
2267                 num_tc = max_tc + 1;
2268                 if (num_tc > dcb_rx_conf->nb_tcs) {
2269                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2270                                  num_tc, dcb_rx_conf->nb_tcs);
2271                         return -EINVAL;
2272                 }
2273         }
2274
2275         return 0;
2276 }
2277
2278 static int
2279 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2280 {
2281         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2282
2283         if (!hns3_dev_dcb_supported(hw)) {
2284                 hns3_err(hw, "this port does not support dcb configurations.");
2285                 return -EOPNOTSUPP;
2286         }
2287
2288         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2289                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2290                 return -EOPNOTSUPP;
2291         }
2292
2293         return 0;
2294 }
2295
2296 static int
2297 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2298                            enum hns3_ring_type queue_type, uint16_t queue_id)
2299 {
2300         struct hns3_cmd_desc desc;
2301         struct hns3_ctrl_vector_chain_cmd *req =
2302                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2303         enum hns3_opcode_type op;
2304         uint16_t tqp_type_and_id = 0;
2305         uint16_t type;
2306         uint16_t gl;
2307         int ret;
2308
2309         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2310         hns3_cmd_setup_basic_desc(&desc, op, false);
2311         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2312                                               HNS3_TQP_INT_ID_L_S);
2313         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2314                                               HNS3_TQP_INT_ID_H_S);
2315
2316         if (queue_type == HNS3_RING_TYPE_RX)
2317                 gl = HNS3_RING_GL_RX;
2318         else
2319                 gl = HNS3_RING_GL_TX;
2320
2321         type = queue_type;
2322
2323         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2324                        type);
2325         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2326         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2327                        gl);
2328         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2329         req->int_cause_num = 1;
2330         ret = hns3_cmd_send(hw, &desc, 1);
2331         if (ret) {
2332                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2333                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2334                 return ret;
2335         }
2336
2337         return 0;
2338 }
2339
2340 static int
2341 hns3_init_ring_with_vector(struct hns3_hw *hw)
2342 {
2343         uint16_t vec;
2344         int ret;
2345         int i;
2346
2347         /*
2348          * In hns3 network engine, vector 0 is always the misc interrupt of this
2349          * function, vector 1~N can be used respectively for the queues of the
2350          * function. Tx and Rx queues with the same number share the interrupt
2351          * vector. In the initialization clearing the all hardware mapping
2352          * relationship configurations between queues and interrupt vectors is
2353          * needed, so some error caused by the residual configurations, such as
2354          * the unexpected Tx interrupt, can be avoid.
2355          */
2356         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2357         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2358                 vec = vec - 1; /* the last interrupt is reserved */
2359         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2360         for (i = 0; i < hw->intr_tqps_num; i++) {
2361                 /*
2362                  * Set gap limiter/rate limiter/quanity limiter algorithm
2363                  * configuration for interrupt coalesce of queue's interrupt.
2364                  */
2365                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2366                                        HNS3_TQP_INTR_GL_DEFAULT);
2367                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2368                                        HNS3_TQP_INTR_GL_DEFAULT);
2369                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2370                 /*
2371                  * QL(quantity limiter) is not used currently, just set 0 to
2372                  * close it.
2373                  */
2374                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2375
2376                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2377                                                  HNS3_RING_TYPE_TX, i);
2378                 if (ret) {
2379                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2380                                           "vector: %u, ret=%d", i, vec, ret);
2381                         return ret;
2382                 }
2383
2384                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2385                                                  HNS3_RING_TYPE_RX, i);
2386                 if (ret) {
2387                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2388                                           "vector: %u, ret=%d", i, vec, ret);
2389                         return ret;
2390                 }
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int
2397 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2398 {
2399         struct hns3_adapter *hns = dev->data->dev_private;
2400         struct hns3_hw *hw = &hns->hw;
2401         uint32_t max_rx_pkt_len;
2402         uint16_t mtu;
2403         int ret;
2404
2405         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2406                 return 0;
2407
2408         /*
2409          * If jumbo frames are enabled, MTU needs to be refreshed
2410          * according to the maximum RX packet length.
2411          */
2412         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2413         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2414             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2415                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2416                          "and no more than %u when jumbo frame enabled.",
2417                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2418                          (uint16_t)HNS3_MAX_FRAME_LEN);
2419                 return -EINVAL;
2420         }
2421
2422         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2423         ret = hns3_dev_mtu_set(dev, mtu);
2424         if (ret)
2425                 return ret;
2426         dev->data->mtu = mtu;
2427
2428         return 0;
2429 }
2430
2431 static int
2432 hns3_dev_configure(struct rte_eth_dev *dev)
2433 {
2434         struct hns3_adapter *hns = dev->data->dev_private;
2435         struct rte_eth_conf *conf = &dev->data->dev_conf;
2436         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2437         struct hns3_hw *hw = &hns->hw;
2438         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2439         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2440         struct rte_eth_rss_conf rss_conf;
2441         bool gro_en;
2442         int ret;
2443
2444         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2445
2446         /*
2447          * Some versions of hardware network engine does not support
2448          * individually enable/disable/reset the Tx or Rx queue. These devices
2449          * must enable/disable/reset Tx and Rx queues at the same time. When the
2450          * numbers of Tx queues allocated by upper applications are not equal to
2451          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2452          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2453          * work as usual. But these fake queues are imperceptible, and can not
2454          * be used by upper applications.
2455          */
2456         if (!hns3_dev_indep_txrx_supported(hw)) {
2457                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2458                 if (ret) {
2459                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2460                                  ret);
2461                         return ret;
2462                 }
2463         }
2464
2465         hw->adapter_state = HNS3_NIC_CONFIGURING;
2466         ret = hns3_check_mq_mode(dev);
2467         if (ret)
2468                 goto cfg_err;
2469
2470         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2471                 ret = hns3_check_dcb_cfg(dev);
2472                 if (ret)
2473                         goto cfg_err;
2474         }
2475
2476         /* When RSS is not configured, redirect the packet queue 0 */
2477         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2478                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2479                 rss_conf = conf->rx_adv_conf.rss_conf;
2480                 hw->rss_dis_flag = false;
2481                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2482                 if (ret)
2483                         goto cfg_err;
2484         }
2485
2486         ret = hns3_refresh_mtu(dev, conf);
2487         if (ret)
2488                 goto cfg_err;
2489
2490         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2491         if (ret)
2492                 goto cfg_err;
2493
2494         ret = hns3_dev_configure_vlan(dev);
2495         if (ret)
2496                 goto cfg_err;
2497
2498         /* config hardware GRO */
2499         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2500         ret = hns3_config_gro(hw, gro_en);
2501         if (ret)
2502                 goto cfg_err;
2503
2504         hns3_init_rx_ptype_tble(dev);
2505         hw->adapter_state = HNS3_NIC_CONFIGURED;
2506
2507         return 0;
2508
2509 cfg_err:
2510         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2511         hw->adapter_state = HNS3_NIC_INITIALIZED;
2512
2513         return ret;
2514 }
2515
2516 static int
2517 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2518 {
2519         struct hns3_config_max_frm_size_cmd *req;
2520         struct hns3_cmd_desc desc;
2521
2522         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2523
2524         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2525         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2526         req->min_frm_size = RTE_ETHER_MIN_LEN;
2527
2528         return hns3_cmd_send(hw, &desc, 1);
2529 }
2530
2531 static int
2532 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2533 {
2534         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2535         uint16_t original_mps = hns->pf.mps;
2536         int err;
2537         int ret;
2538
2539         ret = hns3_set_mac_mtu(hw, mps);
2540         if (ret) {
2541                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2542                 return ret;
2543         }
2544
2545         hns->pf.mps = mps;
2546         ret = hns3_buffer_alloc(hw);
2547         if (ret) {
2548                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2549                 goto rollback;
2550         }
2551
2552         return 0;
2553
2554 rollback:
2555         err = hns3_set_mac_mtu(hw, original_mps);
2556         if (err) {
2557                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2558                 return ret;
2559         }
2560         hns->pf.mps = original_mps;
2561
2562         return ret;
2563 }
2564
2565 static int
2566 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2567 {
2568         struct hns3_adapter *hns = dev->data->dev_private;
2569         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2570         struct hns3_hw *hw = &hns->hw;
2571         bool is_jumbo_frame;
2572         int ret;
2573
2574         if (dev->data->dev_started) {
2575                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2576                          "before configuration", dev->data->port_id);
2577                 return -EBUSY;
2578         }
2579
2580         rte_spinlock_lock(&hw->lock);
2581         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2582         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2583
2584         /*
2585          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2586          * assign to "uint16_t" type variable.
2587          */
2588         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2589         if (ret) {
2590                 rte_spinlock_unlock(&hw->lock);
2591                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2592                          dev->data->port_id, mtu, ret);
2593                 return ret;
2594         }
2595
2596         if (is_jumbo_frame)
2597                 dev->data->dev_conf.rxmode.offloads |=
2598                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2599         else
2600                 dev->data->dev_conf.rxmode.offloads &=
2601                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2602         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2603         rte_spinlock_unlock(&hw->lock);
2604
2605         return 0;
2606 }
2607
2608 static uint32_t
2609 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2610 {
2611         uint32_t speed_capa = 0;
2612
2613         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2614                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2615         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2616                 speed_capa |= ETH_LINK_SPEED_10M;
2617         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2618                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2619         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2620                 speed_capa |= ETH_LINK_SPEED_100M;
2621         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2622                 speed_capa |= ETH_LINK_SPEED_1G;
2623
2624         return speed_capa;
2625 }
2626
2627 static uint32_t
2628 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2629 {
2630         uint32_t speed_capa = 0;
2631
2632         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2633                 speed_capa |= ETH_LINK_SPEED_1G;
2634         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2635                 speed_capa |= ETH_LINK_SPEED_10G;
2636         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2637                 speed_capa |= ETH_LINK_SPEED_25G;
2638         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2639                 speed_capa |= ETH_LINK_SPEED_40G;
2640         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2641                 speed_capa |= ETH_LINK_SPEED_50G;
2642         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2643                 speed_capa |= ETH_LINK_SPEED_100G;
2644         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2645                 speed_capa |= ETH_LINK_SPEED_200G;
2646
2647         return speed_capa;
2648 }
2649
2650 static uint32_t
2651 hns3_get_speed_capa(struct hns3_hw *hw)
2652 {
2653         struct hns3_mac *mac = &hw->mac;
2654         uint32_t speed_capa;
2655
2656         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2657                 speed_capa =
2658                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2659         else
2660                 speed_capa =
2661                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2662
2663         if (mac->support_autoneg == 0)
2664                 speed_capa |= ETH_LINK_SPEED_FIXED;
2665
2666         return speed_capa;
2667 }
2668
2669 int
2670 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2671 {
2672         struct hns3_adapter *hns = eth_dev->data->dev_private;
2673         struct hns3_hw *hw = &hns->hw;
2674         uint16_t queue_num = hw->tqps_num;
2675
2676         /*
2677          * In interrupt mode, 'max_rx_queues' is set based on the number of
2678          * MSI-X interrupt resources of the hardware.
2679          */
2680         if (hw->data->dev_conf.intr_conf.rxq == 1)
2681                 queue_num = hw->intr_tqps_num;
2682
2683         info->max_rx_queues = queue_num;
2684         info->max_tx_queues = hw->tqps_num;
2685         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2686         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2687         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2688         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2689         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2690         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2691                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2692                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2693                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2694                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2695                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2696                                  DEV_RX_OFFLOAD_KEEP_CRC |
2697                                  DEV_RX_OFFLOAD_SCATTER |
2698                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2699                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2700                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2701                                  DEV_RX_OFFLOAD_RSS_HASH |
2702                                  DEV_RX_OFFLOAD_TCP_LRO);
2703         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2704                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2705                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2706                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2707                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2708                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2709                                  DEV_TX_OFFLOAD_TCP_TSO |
2710                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2711                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2712                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2713                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2714                                  hns3_txvlan_cap_get(hw));
2715
2716         if (hns3_dev_outer_udp_cksum_supported(hw))
2717                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2718
2719         if (hns3_dev_indep_txrx_supported(hw))
2720                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2721                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2722
2723         if (hns3_dev_ptp_supported(hw))
2724                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2725
2726         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2727                 .nb_max = HNS3_MAX_RING_DESC,
2728                 .nb_min = HNS3_MIN_RING_DESC,
2729                 .nb_align = HNS3_ALIGN_RING_DESC,
2730         };
2731
2732         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2733                 .nb_max = HNS3_MAX_RING_DESC,
2734                 .nb_min = HNS3_MIN_RING_DESC,
2735                 .nb_align = HNS3_ALIGN_RING_DESC,
2736                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2737                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2738         };
2739
2740         info->speed_capa = hns3_get_speed_capa(hw);
2741         info->default_rxconf = (struct rte_eth_rxconf) {
2742                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2743                 /*
2744                  * If there are no available Rx buffer descriptors, incoming
2745                  * packets are always dropped by hardware based on hns3 network
2746                  * engine.
2747                  */
2748                 .rx_drop_en = 1,
2749                 .offloads = 0,
2750         };
2751         info->default_txconf = (struct rte_eth_txconf) {
2752                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2753                 .offloads = 0,
2754         };
2755
2756         info->vmdq_queue_num = 0;
2757
2758         info->reta_size = hw->rss_ind_tbl_size;
2759         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2760         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2761
2762         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2763         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2764         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2765         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2766         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2767         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2768
2769         return 0;
2770 }
2771
2772 static int
2773 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2774                     size_t fw_size)
2775 {
2776         struct hns3_adapter *hns = eth_dev->data->dev_private;
2777         struct hns3_hw *hw = &hns->hw;
2778         uint32_t version = hw->fw_version;
2779         int ret;
2780
2781         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2782                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2783                                       HNS3_FW_VERSION_BYTE3_S),
2784                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2785                                       HNS3_FW_VERSION_BYTE2_S),
2786                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2787                                       HNS3_FW_VERSION_BYTE1_S),
2788                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2789                                       HNS3_FW_VERSION_BYTE0_S));
2790         ret += 1; /* add the size of '\0' */
2791         if (fw_size < (uint32_t)ret)
2792                 return ret;
2793         else
2794                 return 0;
2795 }
2796
2797 static int
2798 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2799 {
2800         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2801         int ret;
2802
2803         (void)hns3_update_link_status(hw);
2804
2805         ret = hns3_update_link_info(eth_dev);
2806         if (ret)
2807                 hw->mac.link_status = ETH_LINK_DOWN;
2808
2809         return ret;
2810 }
2811
2812 static void
2813 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2814                       struct rte_eth_link *new_link)
2815 {
2816         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2817         struct hns3_mac *mac = &hw->mac;
2818
2819         switch (mac->link_speed) {
2820         case ETH_SPEED_NUM_10M:
2821         case ETH_SPEED_NUM_100M:
2822         case ETH_SPEED_NUM_1G:
2823         case ETH_SPEED_NUM_10G:
2824         case ETH_SPEED_NUM_25G:
2825         case ETH_SPEED_NUM_40G:
2826         case ETH_SPEED_NUM_50G:
2827         case ETH_SPEED_NUM_100G:
2828         case ETH_SPEED_NUM_200G:
2829                 new_link->link_speed = mac->link_speed;
2830                 break;
2831         default:
2832                 if (mac->link_status)
2833                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2834                 else
2835                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2836                 break;
2837         }
2838
2839         new_link->link_duplex = mac->link_duplex;
2840         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2841         new_link->link_autoneg = mac->link_autoneg;
2842 }
2843
2844 static int
2845 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2846 {
2847 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2848 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2849
2850         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2851         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2852         struct hns3_mac *mac = &hw->mac;
2853         struct rte_eth_link new_link;
2854         int ret;
2855
2856         do {
2857                 ret = hns3_update_port_link_info(eth_dev);
2858                 if (ret) {
2859                         hns3_err(hw, "failed to get port link info, ret = %d.",
2860                                  ret);
2861                         break;
2862                 }
2863
2864                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2865                         break;
2866
2867                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2868         } while (retry_cnt--);
2869
2870         memset(&new_link, 0, sizeof(new_link));
2871         hns3_setup_linkstatus(eth_dev, &new_link);
2872
2873         return rte_eth_linkstatus_set(eth_dev, &new_link);
2874 }
2875
2876 static int
2877 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2878 {
2879         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2880         struct hns3_pf *pf = &hns->pf;
2881
2882         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2883                 return -EINVAL;
2884
2885         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2886
2887         return 0;
2888 }
2889
2890 static int
2891 hns3_query_function_status(struct hns3_hw *hw)
2892 {
2893 #define HNS3_QUERY_MAX_CNT              10
2894 #define HNS3_QUERY_SLEEP_MSCOEND        1
2895         struct hns3_func_status_cmd *req;
2896         struct hns3_cmd_desc desc;
2897         int timeout = 0;
2898         int ret;
2899
2900         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2901         req = (struct hns3_func_status_cmd *)desc.data;
2902
2903         do {
2904                 ret = hns3_cmd_send(hw, &desc, 1);
2905                 if (ret) {
2906                         PMD_INIT_LOG(ERR, "query function status failed %d",
2907                                      ret);
2908                         return ret;
2909                 }
2910
2911                 /* Check pf reset is done */
2912                 if (req->pf_state)
2913                         break;
2914
2915                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2916         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2917
2918         return hns3_parse_func_status(hw, req);
2919 }
2920
2921 static int
2922 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2923 {
2924         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2925         struct hns3_pf *pf = &hns->pf;
2926
2927         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2928                 /*
2929                  * The total_tqps_num obtained from firmware is maximum tqp
2930                  * numbers of this port, which should be used for PF and VFs.
2931                  * There is no need for pf to have so many tqp numbers in
2932                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2933                  * coming from config file, is assigned to maximum queue number
2934                  * for the PF of this port by user. So users can modify the
2935                  * maximum queue number of PF according to their own application
2936                  * scenarios, which is more flexible to use. In addition, many
2937                  * memories can be saved due to allocating queue statistics
2938                  * room according to the actual number of queues required. The
2939                  * maximum queue number of PF for network engine with
2940                  * revision_id greater than 0x30 is assigned by config file.
2941                  */
2942                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2943                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2944                                  "must be greater than 0.",
2945                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2946                         return -EINVAL;
2947                 }
2948
2949                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2950                                        hw->total_tqps_num);
2951         } else {
2952                 /*
2953                  * Due to the limitation on the number of PF interrupts
2954                  * available, the maximum queue number assigned to PF on
2955                  * the network engine with revision_id 0x21 is 64.
2956                  */
2957                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2958                                        HNS3_MAX_TQP_NUM_HIP08_PF);
2959         }
2960
2961         return 0;
2962 }
2963
2964 static int
2965 hns3_query_pf_resource(struct hns3_hw *hw)
2966 {
2967         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2968         struct hns3_pf *pf = &hns->pf;
2969         struct hns3_pf_res_cmd *req;
2970         struct hns3_cmd_desc desc;
2971         int ret;
2972
2973         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2974         ret = hns3_cmd_send(hw, &desc, 1);
2975         if (ret) {
2976                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2977                 return ret;
2978         }
2979
2980         req = (struct hns3_pf_res_cmd *)desc.data;
2981         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
2982                              rte_le_to_cpu_16(req->ext_tqp_num);
2983         ret = hns3_get_pf_max_tqp_num(hw);
2984         if (ret)
2985                 return ret;
2986
2987         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2988         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2989
2990         if (req->tx_buf_size)
2991                 pf->tx_buf_size =
2992                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2993         else
2994                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2995
2996         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2997
2998         if (req->dv_buf_size)
2999                 pf->dv_buf_size =
3000                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3001         else
3002                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3003
3004         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3005
3006         hw->num_msi =
3007                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3008                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3009
3010         return 0;
3011 }
3012
3013 static void
3014 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3015 {
3016         struct hns3_cfg_param_cmd *req;
3017         uint64_t mac_addr_tmp_high;
3018         uint8_t ext_rss_size_max;
3019         uint64_t mac_addr_tmp;
3020         uint32_t i;
3021
3022         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3023
3024         /* get the configuration */
3025         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3026                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3027         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3028                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3029         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3030                                            HNS3_CFG_TQP_DESC_N_M,
3031                                            HNS3_CFG_TQP_DESC_N_S);
3032
3033         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3034                                        HNS3_CFG_PHY_ADDR_M,
3035                                        HNS3_CFG_PHY_ADDR_S);
3036         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3037                                          HNS3_CFG_MEDIA_TP_M,
3038                                          HNS3_CFG_MEDIA_TP_S);
3039         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3040                                          HNS3_CFG_RX_BUF_LEN_M,
3041                                          HNS3_CFG_RX_BUF_LEN_S);
3042         /* get mac address */
3043         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3044         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3045                                            HNS3_CFG_MAC_ADDR_H_M,
3046                                            HNS3_CFG_MAC_ADDR_H_S);
3047
3048         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3049
3050         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3051                                             HNS3_CFG_DEFAULT_SPEED_M,
3052                                             HNS3_CFG_DEFAULT_SPEED_S);
3053         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3054                                            HNS3_CFG_RSS_SIZE_M,
3055                                            HNS3_CFG_RSS_SIZE_S);
3056
3057         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3058                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3059
3060         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3061         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3062
3063         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3064                                             HNS3_CFG_SPEED_ABILITY_M,
3065                                             HNS3_CFG_SPEED_ABILITY_S);
3066         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3067                                         HNS3_CFG_UMV_TBL_SPACE_M,
3068                                         HNS3_CFG_UMV_TBL_SPACE_S);
3069         if (!cfg->umv_space)
3070                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3071
3072         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3073                                                HNS3_CFG_EXT_RSS_SIZE_M,
3074                                                HNS3_CFG_EXT_RSS_SIZE_S);
3075
3076         /*
3077          * Field ext_rss_size_max obtained from firmware will be more flexible
3078          * for future changes and expansions, which is an exponent of 2, instead
3079          * of reading out directly. If this field is not zero, hns3 PF PMD
3080          * driver uses it as rss_size_max under one TC. Device, whose revision
3081          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3082          * maximum number of queues supported under a TC through this field.
3083          */
3084         if (ext_rss_size_max)
3085                 cfg->rss_size_max = 1U << ext_rss_size_max;
3086 }
3087
3088 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3089  * @hw: pointer to struct hns3_hw
3090  * @hcfg: the config structure to be getted
3091  */
3092 static int
3093 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3094 {
3095         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3096         struct hns3_cfg_param_cmd *req;
3097         uint32_t offset;
3098         uint32_t i;
3099         int ret;
3100
3101         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3102                 offset = 0;
3103                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3104                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3105                                           true);
3106                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3107                                i * HNS3_CFG_RD_LEN_BYTES);
3108                 /* Len should be divided by 4 when send to hardware */
3109                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3110                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3111                 req->offset = rte_cpu_to_le_32(offset);
3112         }
3113
3114         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3115         if (ret) {
3116                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3117                 return ret;
3118         }
3119
3120         hns3_parse_cfg(hcfg, desc);
3121
3122         return 0;
3123 }
3124
3125 static int
3126 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3127 {
3128         switch (speed_cmd) {
3129         case HNS3_CFG_SPEED_10M:
3130                 *speed = ETH_SPEED_NUM_10M;
3131                 break;
3132         case HNS3_CFG_SPEED_100M:
3133                 *speed = ETH_SPEED_NUM_100M;
3134                 break;
3135         case HNS3_CFG_SPEED_1G:
3136                 *speed = ETH_SPEED_NUM_1G;
3137                 break;
3138         case HNS3_CFG_SPEED_10G:
3139                 *speed = ETH_SPEED_NUM_10G;
3140                 break;
3141         case HNS3_CFG_SPEED_25G:
3142                 *speed = ETH_SPEED_NUM_25G;
3143                 break;
3144         case HNS3_CFG_SPEED_40G:
3145                 *speed = ETH_SPEED_NUM_40G;
3146                 break;
3147         case HNS3_CFG_SPEED_50G:
3148                 *speed = ETH_SPEED_NUM_50G;
3149                 break;
3150         case HNS3_CFG_SPEED_100G:
3151                 *speed = ETH_SPEED_NUM_100G;
3152                 break;
3153         case HNS3_CFG_SPEED_200G:
3154                 *speed = ETH_SPEED_NUM_200G;
3155                 break;
3156         default:
3157                 return -EINVAL;
3158         }
3159
3160         return 0;
3161 }
3162
3163 static void
3164 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3165 {
3166         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3167         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3168         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3169         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3170         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3171 }
3172
3173 static void
3174 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3175 {
3176         struct hns3_dev_specs_0_cmd *req0;
3177
3178         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3179
3180         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3181         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3182         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3183         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3184         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3185 }
3186
3187 static int
3188 hns3_check_dev_specifications(struct hns3_hw *hw)
3189 {
3190         if (hw->rss_ind_tbl_size == 0 ||
3191             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3192                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3193                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3194                               HNS3_RSS_IND_TBL_SIZE_MAX);
3195                 return -EINVAL;
3196         }
3197
3198         return 0;
3199 }
3200
3201 static int
3202 hns3_query_dev_specifications(struct hns3_hw *hw)
3203 {
3204         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3205         int ret;
3206         int i;
3207
3208         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3209                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3210                                           true);
3211                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3212         }
3213         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3214
3215         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3216         if (ret)
3217                 return ret;
3218
3219         hns3_parse_dev_specifications(hw, desc);
3220
3221         return hns3_check_dev_specifications(hw);
3222 }
3223
3224 static int
3225 hns3_get_capability(struct hns3_hw *hw)
3226 {
3227         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3228         struct rte_pci_device *pci_dev;
3229         struct hns3_pf *pf = &hns->pf;
3230         struct rte_eth_dev *eth_dev;
3231         uint16_t device_id;
3232         uint8_t revision;
3233         int ret;
3234
3235         eth_dev = &rte_eth_devices[hw->data->port_id];
3236         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3237         device_id = pci_dev->id.device_id;
3238
3239         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3240             device_id == HNS3_DEV_ID_50GE_RDMA ||
3241             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3242             device_id == HNS3_DEV_ID_200G_RDMA)
3243                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3244
3245         /* Get PCI revision id */
3246         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3247                                   HNS3_PCI_REVISION_ID);
3248         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3249                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3250                              ret);
3251                 return -EIO;
3252         }
3253         hw->revision = revision;
3254
3255         if (revision < PCI_REVISION_ID_HIP09_A) {
3256                 hns3_set_default_dev_specifications(hw);
3257                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3258                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3259                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3260                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3261                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3262                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3263                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3264                 hw->rss_info.ipv6_sctp_offload_supported = false;
3265                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3266                 return 0;
3267         }
3268
3269         ret = hns3_query_dev_specifications(hw);
3270         if (ret) {
3271                 PMD_INIT_LOG(ERR,
3272                              "failed to query dev specifications, ret = %d",
3273                              ret);
3274                 return ret;
3275         }
3276
3277         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3278         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3279         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3280         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3281         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3282         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3283         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3284         hw->rss_info.ipv6_sctp_offload_supported = true;
3285         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3286
3287         return 0;
3288 }
3289
3290 static int
3291 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3292 {
3293         int ret;
3294
3295         switch (media_type) {
3296         case HNS3_MEDIA_TYPE_COPPER:
3297                 if (!hns3_dev_copper_supported(hw)) {
3298                         PMD_INIT_LOG(ERR,
3299                                      "Media type is copper, not supported.");
3300                         ret = -EOPNOTSUPP;
3301                 } else {
3302                         ret = 0;
3303                 }
3304                 break;
3305         case HNS3_MEDIA_TYPE_FIBER:
3306                 ret = 0;
3307                 break;
3308         case HNS3_MEDIA_TYPE_BACKPLANE:
3309                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3310                 ret = -EOPNOTSUPP;
3311                 break;
3312         default:
3313                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3314                 ret = -EINVAL;
3315                 break;
3316         }
3317
3318         return ret;
3319 }
3320
3321 static int
3322 hns3_get_board_configuration(struct hns3_hw *hw)
3323 {
3324         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3325         struct hns3_pf *pf = &hns->pf;
3326         struct hns3_cfg cfg;
3327         int ret;
3328
3329         ret = hns3_get_board_cfg(hw, &cfg);
3330         if (ret) {
3331                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3332                 return ret;
3333         }
3334
3335         ret = hns3_check_media_type(hw, cfg.media_type);
3336         if (ret)
3337                 return ret;
3338
3339         hw->mac.media_type = cfg.media_type;
3340         hw->rss_size_max = cfg.rss_size_max;
3341         hw->rss_dis_flag = false;
3342         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3343         hw->mac.phy_addr = cfg.phy_addr;
3344         hw->mac.default_addr_setted = false;
3345         hw->num_tx_desc = cfg.tqp_desc_num;
3346         hw->num_rx_desc = cfg.tqp_desc_num;
3347         hw->dcb_info.num_pg = 1;
3348         hw->dcb_info.hw_pfc_map = 0;
3349
3350         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3351         if (ret) {
3352                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3353                              cfg.default_speed, ret);
3354                 return ret;
3355         }
3356
3357         pf->tc_max = cfg.tc_num;
3358         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3359                 PMD_INIT_LOG(WARNING,
3360                              "Get TC num(%u) from flash, set TC num to 1",
3361                              pf->tc_max);
3362                 pf->tc_max = 1;
3363         }
3364
3365         /* Dev does not support DCB */
3366         if (!hns3_dev_dcb_supported(hw)) {
3367                 pf->tc_max = 1;
3368                 pf->pfc_max = 0;
3369         } else
3370                 pf->pfc_max = pf->tc_max;
3371
3372         hw->dcb_info.num_tc = 1;
3373         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3374                                      hw->tqps_num / hw->dcb_info.num_tc);
3375         hns3_set_bit(hw->hw_tc_map, 0, 1);
3376         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3377
3378         pf->wanted_umv_size = cfg.umv_space;
3379
3380         return ret;
3381 }
3382
3383 static int
3384 hns3_get_configuration(struct hns3_hw *hw)
3385 {
3386         int ret;
3387
3388         ret = hns3_query_function_status(hw);
3389         if (ret) {
3390                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3391                 return ret;
3392         }
3393
3394         /* Get device capability */
3395         ret = hns3_get_capability(hw);
3396         if (ret) {
3397                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3398                 return ret;
3399         }
3400
3401         /* Get pf resource */
3402         ret = hns3_query_pf_resource(hw);
3403         if (ret) {
3404                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3405                 return ret;
3406         }
3407
3408         ret = hns3_get_board_configuration(hw);
3409         if (ret) {
3410                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3411                 return ret;
3412         }
3413
3414         ret = hns3_query_dev_fec_info(hw);
3415         if (ret)
3416                 PMD_INIT_LOG(ERR,
3417                              "failed to query FEC information, ret = %d", ret);
3418
3419         return ret;
3420 }
3421
3422 static int
3423 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3424                       uint16_t tqp_vid, bool is_pf)
3425 {
3426         struct hns3_tqp_map_cmd *req;
3427         struct hns3_cmd_desc desc;
3428         int ret;
3429
3430         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3431
3432         req = (struct hns3_tqp_map_cmd *)desc.data;
3433         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3434         req->tqp_vf = func_id;
3435         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3436         if (!is_pf)
3437                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3438         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3439
3440         ret = hns3_cmd_send(hw, &desc, 1);
3441         if (ret)
3442                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3443
3444         return ret;
3445 }
3446
3447 static int
3448 hns3_map_tqp(struct hns3_hw *hw)
3449 {
3450         int ret;
3451         int i;
3452
3453         /*
3454          * In current version, VF is not supported when PF is driven by DPDK
3455          * driver, so we assign total tqps_num tqps allocated to this port
3456          * to PF.
3457          */
3458         for (i = 0; i < hw->total_tqps_num; i++) {
3459                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3460                 if (ret)
3461                         return ret;
3462         }
3463
3464         return 0;
3465 }
3466
3467 static int
3468 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3469 {
3470         struct hns3_config_mac_speed_dup_cmd *req;
3471         struct hns3_cmd_desc desc;
3472         int ret;
3473
3474         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3475
3476         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3477
3478         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3479
3480         switch (speed) {
3481         case ETH_SPEED_NUM_10M:
3482                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3483                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3484                 break;
3485         case ETH_SPEED_NUM_100M:
3486                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3487                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3488                 break;
3489         case ETH_SPEED_NUM_1G:
3490                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3491                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3492                 break;
3493         case ETH_SPEED_NUM_10G:
3494                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3495                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3496                 break;
3497         case ETH_SPEED_NUM_25G:
3498                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3499                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3500                 break;
3501         case ETH_SPEED_NUM_40G:
3502                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3503                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3504                 break;
3505         case ETH_SPEED_NUM_50G:
3506                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3507                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3508                 break;
3509         case ETH_SPEED_NUM_100G:
3510                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3511                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3512                 break;
3513         case ETH_SPEED_NUM_200G:
3514                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3515                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3516                 break;
3517         default:
3518                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3519                 return -EINVAL;
3520         }
3521
3522         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3523
3524         ret = hns3_cmd_send(hw, &desc, 1);
3525         if (ret)
3526                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3527
3528         return ret;
3529 }
3530
3531 static int
3532 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3533 {
3534         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3535         struct hns3_pf *pf = &hns->pf;
3536         struct hns3_priv_buf *priv;
3537         uint32_t i, total_size;
3538
3539         total_size = pf->pkt_buf_size;
3540
3541         /* alloc tx buffer for all enabled tc */
3542         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3543                 priv = &buf_alloc->priv_buf[i];
3544
3545                 if (hw->hw_tc_map & BIT(i)) {
3546                         if (total_size < pf->tx_buf_size)
3547                                 return -ENOMEM;
3548
3549                         priv->tx_buf_size = pf->tx_buf_size;
3550                 } else
3551                         priv->tx_buf_size = 0;
3552
3553                 total_size -= priv->tx_buf_size;
3554         }
3555
3556         return 0;
3557 }
3558
3559 static int
3560 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3561 {
3562 /* TX buffer size is unit by 128 byte */
3563 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3564 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3565         struct hns3_tx_buff_alloc_cmd *req;
3566         struct hns3_cmd_desc desc;
3567         uint32_t buf_size;
3568         uint32_t i;
3569         int ret;
3570
3571         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3572
3573         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3574         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3575                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3576
3577                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3578                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3579                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3580         }
3581
3582         ret = hns3_cmd_send(hw, &desc, 1);
3583         if (ret)
3584                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3585
3586         return ret;
3587 }
3588
3589 static int
3590 hns3_get_tc_num(struct hns3_hw *hw)
3591 {
3592         int cnt = 0;
3593         uint8_t i;
3594
3595         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3596                 if (hw->hw_tc_map & BIT(i))
3597                         cnt++;
3598         return cnt;
3599 }
3600
3601 static uint32_t
3602 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3603 {
3604         struct hns3_priv_buf *priv;
3605         uint32_t rx_priv = 0;
3606         int i;
3607
3608         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3609                 priv = &buf_alloc->priv_buf[i];
3610                 if (priv->enable)
3611                         rx_priv += priv->buf_size;
3612         }
3613         return rx_priv;
3614 }
3615
3616 static uint32_t
3617 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3618 {
3619         uint32_t total_tx_size = 0;
3620         uint32_t i;
3621
3622         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3623                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3624
3625         return total_tx_size;
3626 }
3627
3628 /* Get the number of pfc enabled TCs, which have private buffer */
3629 static int
3630 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3631 {
3632         struct hns3_priv_buf *priv;
3633         int cnt = 0;
3634         uint8_t i;
3635
3636         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3637                 priv = &buf_alloc->priv_buf[i];
3638                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3639                         cnt++;
3640         }
3641
3642         return cnt;
3643 }
3644
3645 /* Get the number of pfc disabled TCs, which have private buffer */
3646 static int
3647 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3648                          struct hns3_pkt_buf_alloc *buf_alloc)
3649 {
3650         struct hns3_priv_buf *priv;
3651         int cnt = 0;
3652         uint8_t i;
3653
3654         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3655                 priv = &buf_alloc->priv_buf[i];
3656                 if (hw->hw_tc_map & BIT(i) &&
3657                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3658                         cnt++;
3659         }
3660
3661         return cnt;
3662 }
3663
3664 static bool
3665 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3666                   uint32_t rx_all)
3667 {
3668         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3669         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3670         struct hns3_pf *pf = &hns->pf;
3671         uint32_t shared_buf, aligned_mps;
3672         uint32_t rx_priv;
3673         uint8_t tc_num;
3674         uint8_t i;
3675
3676         tc_num = hns3_get_tc_num(hw);
3677         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3678
3679         if (hns3_dev_dcb_supported(hw))
3680                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3681                                         pf->dv_buf_size;
3682         else
3683                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3684                                         + pf->dv_buf_size;
3685
3686         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3687         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3688                              HNS3_BUF_SIZE_UNIT);
3689
3690         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3691         if (rx_all < rx_priv + shared_std)
3692                 return false;
3693
3694         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3695         buf_alloc->s_buf.buf_size = shared_buf;
3696         if (hns3_dev_dcb_supported(hw)) {
3697                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3698                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3699                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3700                                   HNS3_BUF_SIZE_UNIT);
3701         } else {
3702                 buf_alloc->s_buf.self.high =
3703                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3704                 buf_alloc->s_buf.self.low = aligned_mps;
3705         }
3706
3707         if (hns3_dev_dcb_supported(hw)) {
3708                 hi_thrd = shared_buf - pf->dv_buf_size;
3709
3710                 if (tc_num <= NEED_RESERVE_TC_NUM)
3711                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3712                                   BUF_MAX_PERCENT;
3713
3714                 if (tc_num)
3715                         hi_thrd = hi_thrd / tc_num;
3716
3717                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3718                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3719                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3720         } else {
3721                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3722                 lo_thrd = aligned_mps;
3723         }
3724
3725         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3726                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3727                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3728         }
3729
3730         return true;
3731 }
3732
3733 static bool
3734 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3735                      struct hns3_pkt_buf_alloc *buf_alloc)
3736 {
3737         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3738         struct hns3_pf *pf = &hns->pf;
3739         struct hns3_priv_buf *priv;
3740         uint32_t aligned_mps;
3741         uint32_t rx_all;
3742         uint8_t i;
3743
3744         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3745         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3746
3747         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3748                 priv = &buf_alloc->priv_buf[i];
3749
3750                 priv->enable = 0;
3751                 priv->wl.low = 0;
3752                 priv->wl.high = 0;
3753                 priv->buf_size = 0;
3754
3755                 if (!(hw->hw_tc_map & BIT(i)))
3756                         continue;
3757
3758                 priv->enable = 1;
3759                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3760                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3761                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3762                                                 HNS3_BUF_SIZE_UNIT);
3763                 } else {
3764                         priv->wl.low = 0;
3765                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3766                                         aligned_mps;
3767                 }
3768
3769                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3770         }
3771
3772         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3773 }
3774
3775 static bool
3776 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3777                              struct hns3_pkt_buf_alloc *buf_alloc)
3778 {
3779         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3780         struct hns3_pf *pf = &hns->pf;
3781         struct hns3_priv_buf *priv;
3782         int no_pfc_priv_num;
3783         uint32_t rx_all;
3784         uint8_t mask;
3785         int i;
3786
3787         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3788         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3789
3790         /* let the last to be cleared first */
3791         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3792                 priv = &buf_alloc->priv_buf[i];
3793                 mask = BIT((uint8_t)i);
3794
3795                 if (hw->hw_tc_map & mask &&
3796                     !(hw->dcb_info.hw_pfc_map & mask)) {
3797                         /* Clear the no pfc TC private buffer */
3798                         priv->wl.low = 0;
3799                         priv->wl.high = 0;
3800                         priv->buf_size = 0;
3801                         priv->enable = 0;
3802                         no_pfc_priv_num--;
3803                 }
3804
3805                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3806                     no_pfc_priv_num == 0)
3807                         break;
3808         }
3809
3810         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3811 }
3812
3813 static bool
3814 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3815                            struct hns3_pkt_buf_alloc *buf_alloc)
3816 {
3817         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3818         struct hns3_pf *pf = &hns->pf;
3819         struct hns3_priv_buf *priv;
3820         uint32_t rx_all;
3821         int pfc_priv_num;
3822         uint8_t mask;
3823         int i;
3824
3825         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3826         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3827
3828         /* let the last to be cleared first */
3829         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3830                 priv = &buf_alloc->priv_buf[i];
3831                 mask = BIT((uint8_t)i);
3832                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3833                         /* Reduce the number of pfc TC with private buffer */
3834                         priv->wl.low = 0;
3835                         priv->enable = 0;
3836                         priv->wl.high = 0;
3837                         priv->buf_size = 0;
3838                         pfc_priv_num--;
3839                 }
3840                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3841                     pfc_priv_num == 0)
3842                         break;
3843         }
3844
3845         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3846 }
3847
3848 static bool
3849 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3850                           struct hns3_pkt_buf_alloc *buf_alloc)
3851 {
3852 #define COMPENSATE_BUFFER       0x3C00
3853 #define COMPENSATE_HALF_MPS_NUM 5
3854 #define PRIV_WL_GAP             0x1800
3855         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3856         struct hns3_pf *pf = &hns->pf;
3857         uint32_t tc_num = hns3_get_tc_num(hw);
3858         uint32_t half_mps = pf->mps >> 1;
3859         struct hns3_priv_buf *priv;
3860         uint32_t min_rx_priv;
3861         uint32_t rx_priv;
3862         uint8_t i;
3863
3864         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3865         if (tc_num)
3866                 rx_priv = rx_priv / tc_num;
3867
3868         if (tc_num <= NEED_RESERVE_TC_NUM)
3869                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3870
3871         /*
3872          * Minimum value of private buffer in rx direction (min_rx_priv) is
3873          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3874          * buffer if rx_priv is greater than min_rx_priv.
3875          */
3876         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3877                         COMPENSATE_HALF_MPS_NUM * half_mps;
3878         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3879         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3880
3881         if (rx_priv < min_rx_priv)
3882                 return false;
3883
3884         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3885                 priv = &buf_alloc->priv_buf[i];
3886                 priv->enable = 0;
3887                 priv->wl.low = 0;
3888                 priv->wl.high = 0;
3889                 priv->buf_size = 0;
3890
3891                 if (!(hw->hw_tc_map & BIT(i)))
3892                         continue;
3893
3894                 priv->enable = 1;
3895                 priv->buf_size = rx_priv;
3896                 priv->wl.high = rx_priv - pf->dv_buf_size;
3897                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3898         }
3899
3900         buf_alloc->s_buf.buf_size = 0;
3901
3902         return true;
3903 }
3904
3905 /*
3906  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3907  * @hw: pointer to struct hns3_hw
3908  * @buf_alloc: pointer to buffer calculation data
3909  * @return: 0: calculate sucessful, negative: fail
3910  */
3911 static int
3912 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3913 {
3914         /* When DCB is not supported, rx private buffer is not allocated. */
3915         if (!hns3_dev_dcb_supported(hw)) {
3916                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3917                 struct hns3_pf *pf = &hns->pf;
3918                 uint32_t rx_all = pf->pkt_buf_size;
3919
3920                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3921                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3922                         return -ENOMEM;
3923
3924                 return 0;
3925         }
3926
3927         /*
3928          * Try to allocate privated packet buffer for all TCs without share
3929          * buffer.
3930          */
3931         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3932                 return 0;
3933
3934         /*
3935          * Try to allocate privated packet buffer for all TCs with share
3936          * buffer.
3937          */
3938         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3939                 return 0;
3940
3941         /*
3942          * For different application scenes, the enabled port number, TC number
3943          * and no_drop TC number are different. In order to obtain the better
3944          * performance, software could allocate the buffer size and configure
3945          * the waterline by tring to decrease the private buffer size according
3946          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3947          * enabled tc.
3948          */
3949         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3950                 return 0;
3951
3952         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3953                 return 0;
3954
3955         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3956                 return 0;
3957
3958         return -ENOMEM;
3959 }
3960
3961 static int
3962 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3963 {
3964         struct hns3_rx_priv_buff_cmd *req;
3965         struct hns3_cmd_desc desc;
3966         uint32_t buf_size;
3967         int ret;
3968         int i;
3969
3970         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3971         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3972
3973         /* Alloc private buffer TCs */
3974         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3975                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3976
3977                 req->buf_num[i] =
3978                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3979                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3980         }
3981
3982         buf_size = buf_alloc->s_buf.buf_size;
3983         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3984                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3985
3986         ret = hns3_cmd_send(hw, &desc, 1);
3987         if (ret)
3988                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3989
3990         return ret;
3991 }
3992
3993 static int
3994 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3995 {
3996 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3997         struct hns3_rx_priv_wl_buf *req;
3998         struct hns3_priv_buf *priv;
3999         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4000         int i, j;
4001         int ret;
4002
4003         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4004                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4005                                           false);
4006                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4007
4008                 /* The first descriptor set the NEXT bit to 1 */
4009                 if (i == 0)
4010                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4011                 else
4012                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4013
4014                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4015                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4016
4017                         priv = &buf_alloc->priv_buf[idx];
4018                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4019                                                         HNS3_BUF_UNIT_S);
4020                         req->tc_wl[j].high |=
4021                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4022                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4023                                                         HNS3_BUF_UNIT_S);
4024                         req->tc_wl[j].low |=
4025                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4026                 }
4027         }
4028
4029         /* Send 2 descriptor at one time */
4030         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4031         if (ret)
4032                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4033                              ret);
4034         return ret;
4035 }
4036
4037 static int
4038 hns3_common_thrd_config(struct hns3_hw *hw,
4039                         struct hns3_pkt_buf_alloc *buf_alloc)
4040 {
4041 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4042         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4043         struct hns3_rx_com_thrd *req;
4044         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4045         struct hns3_tc_thrd *tc;
4046         int tc_idx;
4047         int i, j;
4048         int ret;
4049
4050         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4051                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4052                                           false);
4053                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4054
4055                 /* The first descriptor set the NEXT bit to 1 */
4056                 if (i == 0)
4057                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4058                 else
4059                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4060
4061                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4062                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4063                         tc = &s_buf->tc_thrd[tc_idx];
4064
4065                         req->com_thrd[j].high =
4066                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4067                         req->com_thrd[j].high |=
4068                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4069                         req->com_thrd[j].low =
4070                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4071                         req->com_thrd[j].low |=
4072                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4073                 }
4074         }
4075
4076         /* Send 2 descriptors at one time */
4077         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4078         if (ret)
4079                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4080
4081         return ret;
4082 }
4083
4084 static int
4085 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4086 {
4087         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4088         struct hns3_rx_com_wl *req;
4089         struct hns3_cmd_desc desc;
4090         int ret;
4091
4092         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4093
4094         req = (struct hns3_rx_com_wl *)desc.data;
4095         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4096         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4097
4098         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4099         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4100
4101         ret = hns3_cmd_send(hw, &desc, 1);
4102         if (ret)
4103                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4104
4105         return ret;
4106 }
4107
4108 int
4109 hns3_buffer_alloc(struct hns3_hw *hw)
4110 {
4111         struct hns3_pkt_buf_alloc pkt_buf;
4112         int ret;
4113
4114         memset(&pkt_buf, 0, sizeof(pkt_buf));
4115         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4116         if (ret) {
4117                 PMD_INIT_LOG(ERR,
4118                              "could not calc tx buffer size for all TCs %d",
4119                              ret);
4120                 return ret;
4121         }
4122
4123         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4124         if (ret) {
4125                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4126                 return ret;
4127         }
4128
4129         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4130         if (ret) {
4131                 PMD_INIT_LOG(ERR,
4132                              "could not calc rx priv buffer size for all TCs %d",
4133                              ret);
4134                 return ret;
4135         }
4136
4137         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4138         if (ret) {
4139                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4140                 return ret;
4141         }
4142
4143         if (hns3_dev_dcb_supported(hw)) {
4144                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4145                 if (ret) {
4146                         PMD_INIT_LOG(ERR,
4147                                      "could not configure rx private waterline %d",
4148                                      ret);
4149                         return ret;
4150                 }
4151
4152                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4153                 if (ret) {
4154                         PMD_INIT_LOG(ERR,
4155                                      "could not configure common threshold %d",
4156                                      ret);
4157                         return ret;
4158                 }
4159         }
4160
4161         ret = hns3_common_wl_config(hw, &pkt_buf);
4162         if (ret)
4163                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4164                              ret);
4165
4166         return ret;
4167 }
4168
4169 static int
4170 hns3_mac_init(struct hns3_hw *hw)
4171 {
4172         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4173         struct hns3_mac *mac = &hw->mac;
4174         struct hns3_pf *pf = &hns->pf;
4175         int ret;
4176
4177         pf->support_sfp_query = true;
4178         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4179         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4180         if (ret) {
4181                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4182                 return ret;
4183         }
4184
4185         mac->link_status = ETH_LINK_DOWN;
4186
4187         return hns3_config_mtu(hw, pf->mps);
4188 }
4189
4190 static int
4191 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4192 {
4193 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4194 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4195 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4196 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4197         int return_status;
4198
4199         if (cmdq_resp) {
4200                 PMD_INIT_LOG(ERR,
4201                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4202                              cmdq_resp);
4203                 return -EIO;
4204         }
4205
4206         switch (resp_code) {
4207         case HNS3_ETHERTYPE_SUCCESS_ADD:
4208         case HNS3_ETHERTYPE_ALREADY_ADD:
4209                 return_status = 0;
4210                 break;
4211         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4212                 PMD_INIT_LOG(ERR,
4213                              "add mac ethertype failed for manager table overflow.");
4214                 return_status = -EIO;
4215                 break;
4216         case HNS3_ETHERTYPE_KEY_CONFLICT:
4217                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4218                 return_status = -EIO;
4219                 break;
4220         default:
4221                 PMD_INIT_LOG(ERR,
4222                              "add mac ethertype failed for undefined, code=%u.",
4223                              resp_code);
4224                 return_status = -EIO;
4225                 break;
4226         }
4227
4228         return return_status;
4229 }
4230
4231 static int
4232 hns3_add_mgr_tbl(struct hns3_hw *hw,
4233                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4234 {
4235         struct hns3_cmd_desc desc;
4236         uint8_t resp_code;
4237         uint16_t retval;
4238         int ret;
4239
4240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4241         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4242
4243         ret = hns3_cmd_send(hw, &desc, 1);
4244         if (ret) {
4245                 PMD_INIT_LOG(ERR,
4246                              "add mac ethertype failed for cmd_send, ret =%d.",
4247                              ret);
4248                 return ret;
4249         }
4250
4251         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4252         retval = rte_le_to_cpu_16(desc.retval);
4253
4254         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4255 }
4256
4257 static void
4258 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4259                      int *table_item_num)
4260 {
4261         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4262
4263         /*
4264          * In current version, we add one item in management table as below:
4265          * 0x0180C200000E -- LLDP MC address
4266          */
4267         tbl = mgr_table;
4268         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4269         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4270         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4271         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4272         tbl->i_port_bitmap = 0x1;
4273         *table_item_num = 1;
4274 }
4275
4276 static int
4277 hns3_init_mgr_tbl(struct hns3_hw *hw)
4278 {
4279 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4280         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4281         int table_item_num;
4282         int ret;
4283         int i;
4284
4285         memset(mgr_table, 0, sizeof(mgr_table));
4286         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4287         for (i = 0; i < table_item_num; i++) {
4288                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4289                 if (ret) {
4290                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4291                                      ret);
4292                         return ret;
4293                 }
4294         }
4295
4296         return 0;
4297 }
4298
4299 static void
4300 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4301                         bool en_mc, bool en_bc, int vport_id)
4302 {
4303         if (!param)
4304                 return;
4305
4306         memset(param, 0, sizeof(struct hns3_promisc_param));
4307         if (en_uc)
4308                 param->enable = HNS3_PROMISC_EN_UC;
4309         if (en_mc)
4310                 param->enable |= HNS3_PROMISC_EN_MC;
4311         if (en_bc)
4312                 param->enable |= HNS3_PROMISC_EN_BC;
4313         param->vf_id = vport_id;
4314 }
4315
4316 static int
4317 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4318 {
4319         struct hns3_promisc_cfg_cmd *req;
4320         struct hns3_cmd_desc desc;
4321         int ret;
4322
4323         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4324
4325         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4326         req->vf_id = param->vf_id;
4327         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4328             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4329
4330         ret = hns3_cmd_send(hw, &desc, 1);
4331         if (ret)
4332                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4333
4334         return ret;
4335 }
4336
4337 static int
4338 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4339 {
4340         struct hns3_promisc_param param;
4341         bool en_bc_pmc = true;
4342         uint8_t vf_id;
4343
4344         /*
4345          * In current version VF is not supported when PF is driven by DPDK
4346          * driver, just need to configure parameters for PF vport.
4347          */
4348         vf_id = HNS3_PF_FUNC_ID;
4349
4350         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4351         return hns3_cmd_set_promisc_mode(hw, &param);
4352 }
4353
4354 static int
4355 hns3_promisc_init(struct hns3_hw *hw)
4356 {
4357         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4358         struct hns3_pf *pf = &hns->pf;
4359         struct hns3_promisc_param param;
4360         uint16_t func_id;
4361         int ret;
4362
4363         ret = hns3_set_promisc_mode(hw, false, false);
4364         if (ret) {
4365                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4366                 return ret;
4367         }
4368
4369         /*
4370          * In current version VFs are not supported when PF is driven by DPDK
4371          * driver. After PF has been taken over by DPDK, the original VF will
4372          * be invalid. So, there is a possibility of entry residues. It should
4373          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4374          * during init.
4375          */
4376         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4377                 hns3_promisc_param_init(&param, false, false, false, func_id);
4378                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4379                 if (ret) {
4380                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4381                                         " ret = %d", func_id, ret);
4382                         return ret;
4383                 }
4384         }
4385
4386         return 0;
4387 }
4388
4389 static void
4390 hns3_promisc_uninit(struct hns3_hw *hw)
4391 {
4392         struct hns3_promisc_param param;
4393         uint16_t func_id;
4394         int ret;
4395
4396         func_id = HNS3_PF_FUNC_ID;
4397
4398         /*
4399          * In current version VFs are not supported when PF is driven by
4400          * DPDK driver, and VFs' promisc mode status has been cleared during
4401          * init and their status will not change. So just clear PF's promisc
4402          * mode status during uninit.
4403          */
4404         hns3_promisc_param_init(&param, false, false, false, func_id);
4405         ret = hns3_cmd_set_promisc_mode(hw, &param);
4406         if (ret)
4407                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4408                                 " uninit, ret = %d", ret);
4409 }
4410
4411 static int
4412 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4413 {
4414         bool allmulti = dev->data->all_multicast ? true : false;
4415         struct hns3_adapter *hns = dev->data->dev_private;
4416         struct hns3_hw *hw = &hns->hw;
4417         uint64_t offloads;
4418         int err;
4419         int ret;
4420
4421         rte_spinlock_lock(&hw->lock);
4422         ret = hns3_set_promisc_mode(hw, true, true);
4423         if (ret) {
4424                 rte_spinlock_unlock(&hw->lock);
4425                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4426                          ret);
4427                 return ret;
4428         }
4429
4430         /*
4431          * When promiscuous mode was enabled, disable the vlan filter to let
4432          * all packets coming in in the receiving direction.
4433          */
4434         offloads = dev->data->dev_conf.rxmode.offloads;
4435         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4436                 ret = hns3_enable_vlan_filter(hns, false);
4437                 if (ret) {
4438                         hns3_err(hw, "failed to enable promiscuous mode due to "
4439                                      "failure to disable vlan filter, ret = %d",
4440                                  ret);
4441                         err = hns3_set_promisc_mode(hw, false, allmulti);
4442                         if (err)
4443                                 hns3_err(hw, "failed to restore promiscuous "
4444                                          "status after disable vlan filter "
4445                                          "failed during enabling promiscuous "
4446                                          "mode, ret = %d", ret);
4447                 }
4448         }
4449
4450         rte_spinlock_unlock(&hw->lock);
4451
4452         return ret;
4453 }
4454
4455 static int
4456 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4457 {
4458         bool allmulti = dev->data->all_multicast ? true : false;
4459         struct hns3_adapter *hns = dev->data->dev_private;
4460         struct hns3_hw *hw = &hns->hw;
4461         uint64_t offloads;
4462         int err;
4463         int ret;
4464
4465         /* If now in all_multicast mode, must remain in all_multicast mode. */
4466         rte_spinlock_lock(&hw->lock);
4467         ret = hns3_set_promisc_mode(hw, false, allmulti);
4468         if (ret) {
4469                 rte_spinlock_unlock(&hw->lock);
4470                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4471                          ret);
4472                 return ret;
4473         }
4474         /* when promiscuous mode was disabled, restore the vlan filter status */
4475         offloads = dev->data->dev_conf.rxmode.offloads;
4476         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4477                 ret = hns3_enable_vlan_filter(hns, true);
4478                 if (ret) {
4479                         hns3_err(hw, "failed to disable promiscuous mode due to"
4480                                  " failure to restore vlan filter, ret = %d",
4481                                  ret);
4482                         err = hns3_set_promisc_mode(hw, true, true);
4483                         if (err)
4484                                 hns3_err(hw, "failed to restore promiscuous "
4485                                          "status after enabling vlan filter "
4486                                          "failed during disabling promiscuous "
4487                                          "mode, ret = %d", ret);
4488                 }
4489         }
4490         rte_spinlock_unlock(&hw->lock);
4491
4492         return ret;
4493 }
4494
4495 static int
4496 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4497 {
4498         struct hns3_adapter *hns = dev->data->dev_private;
4499         struct hns3_hw *hw = &hns->hw;
4500         int ret;
4501
4502         if (dev->data->promiscuous)
4503                 return 0;
4504
4505         rte_spinlock_lock(&hw->lock);
4506         ret = hns3_set_promisc_mode(hw, false, true);
4507         rte_spinlock_unlock(&hw->lock);
4508         if (ret)
4509                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4510                          ret);
4511
4512         return ret;
4513 }
4514
4515 static int
4516 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4517 {
4518         struct hns3_adapter *hns = dev->data->dev_private;
4519         struct hns3_hw *hw = &hns->hw;
4520         int ret;
4521
4522         /* If now in promiscuous mode, must remain in all_multicast mode. */
4523         if (dev->data->promiscuous)
4524                 return 0;
4525
4526         rte_spinlock_lock(&hw->lock);
4527         ret = hns3_set_promisc_mode(hw, false, false);
4528         rte_spinlock_unlock(&hw->lock);
4529         if (ret)
4530                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4531                          ret);
4532
4533         return ret;
4534 }
4535
4536 static int
4537 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4538 {
4539         struct hns3_hw *hw = &hns->hw;
4540         bool allmulti = hw->data->all_multicast ? true : false;
4541         int ret;
4542
4543         if (hw->data->promiscuous) {
4544                 ret = hns3_set_promisc_mode(hw, true, true);
4545                 if (ret)
4546                         hns3_err(hw, "failed to restore promiscuous mode, "
4547                                  "ret = %d", ret);
4548                 return ret;
4549         }
4550
4551         ret = hns3_set_promisc_mode(hw, false, allmulti);
4552         if (ret)
4553                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4554                          ret);
4555         return ret;
4556 }
4557
4558 static int
4559 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4560 {
4561         struct hns3_sfp_info_cmd *resp;
4562         struct hns3_cmd_desc desc;
4563         int ret;
4564
4565         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4566         resp = (struct hns3_sfp_info_cmd *)desc.data;
4567         resp->query_type = HNS3_ACTIVE_QUERY;
4568
4569         ret = hns3_cmd_send(hw, &desc, 1);
4570         if (ret == -EOPNOTSUPP) {
4571                 hns3_warn(hw, "firmware does not support get SFP info,"
4572                           " ret = %d.", ret);
4573                 return ret;
4574         } else if (ret) {
4575                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4576                 return ret;
4577         }
4578
4579         /*
4580          * In some case, the speed of MAC obtained from firmware may be 0, it
4581          * shouldn't be set to mac->speed.
4582          */
4583         if (!rte_le_to_cpu_32(resp->sfp_speed))
4584                 return 0;
4585
4586         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4587         /*
4588          * if resp->supported_speed is 0, it means it's an old version
4589          * firmware, do not update these params.
4590          */
4591         if (resp->supported_speed) {
4592                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4593                 mac_info->supported_speed =
4594                                         rte_le_to_cpu_32(resp->supported_speed);
4595                 mac_info->support_autoneg = resp->autoneg_ability;
4596                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4597                                         : ETH_LINK_AUTONEG;
4598         } else {
4599                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4600         }
4601
4602         return 0;
4603 }
4604
4605 static uint8_t
4606 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4607 {
4608         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4609                 duplex = ETH_LINK_FULL_DUPLEX;
4610
4611         return duplex;
4612 }
4613
4614 static int
4615 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4616 {
4617         struct hns3_mac *mac = &hw->mac;
4618         int ret;
4619
4620         duplex = hns3_check_speed_dup(duplex, speed);
4621         if (mac->link_speed == speed && mac->link_duplex == duplex)
4622                 return 0;
4623
4624         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4625         if (ret)
4626                 return ret;
4627
4628         ret = hns3_port_shaper_update(hw, speed);
4629         if (ret)
4630                 return ret;
4631
4632         mac->link_speed = speed;
4633         mac->link_duplex = duplex;
4634
4635         return 0;
4636 }
4637
4638 static int
4639 hns3_update_fiber_link_info(struct hns3_hw *hw)
4640 {
4641         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4642         struct hns3_mac *mac = &hw->mac;
4643         struct hns3_mac mac_info;
4644         int ret;
4645
4646         /* If firmware do not support get SFP/qSFP speed, return directly */
4647         if (!pf->support_sfp_query)
4648                 return 0;
4649
4650         memset(&mac_info, 0, sizeof(struct hns3_mac));
4651         ret = hns3_get_sfp_info(hw, &mac_info);
4652         if (ret == -EOPNOTSUPP) {
4653                 pf->support_sfp_query = false;
4654                 return ret;
4655         } else if (ret)
4656                 return ret;
4657
4658         /* Do nothing if no SFP */
4659         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4660                 return 0;
4661
4662         /*
4663          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4664          * to reconfigure the speed of MAC. Otherwise, it indicates
4665          * that the current firmware only supports to obtain the
4666          * speed of the SFP, and the speed of MAC needs to reconfigure.
4667          */
4668         mac->query_type = mac_info.query_type;
4669         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4670                 if (mac_info.link_speed != mac->link_speed) {
4671                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4672                         if (ret)
4673                                 return ret;
4674                 }
4675
4676                 mac->link_speed = mac_info.link_speed;
4677                 mac->supported_speed = mac_info.supported_speed;
4678                 mac->support_autoneg = mac_info.support_autoneg;
4679                 mac->link_autoneg = mac_info.link_autoneg;
4680
4681                 return 0;
4682         }
4683
4684         /* Config full duplex for SFP */
4685         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4686                                       ETH_LINK_FULL_DUPLEX);
4687 }
4688
4689 static void
4690 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4691 {
4692 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4693
4694         struct hns3_phy_params_bd0_cmd *req;
4695         uint32_t supported;
4696
4697         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4698         mac->link_speed = rte_le_to_cpu_32(req->speed);
4699         mac->link_duplex = hns3_get_bit(req->duplex,
4700                                            HNS3_PHY_DUPLEX_CFG_B);
4701         mac->link_autoneg = hns3_get_bit(req->autoneg,
4702                                            HNS3_PHY_AUTONEG_CFG_B);
4703         mac->advertising = rte_le_to_cpu_32(req->advertising);
4704         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4705         supported = rte_le_to_cpu_32(req->supported);
4706         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4707         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4708 }
4709
4710 static int
4711 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4712 {
4713         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4714         uint16_t i;
4715         int ret;
4716
4717         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4718                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4719                                           true);
4720                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4721         }
4722         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4723
4724         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4725         if (ret) {
4726                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4727                 return ret;
4728         }
4729
4730         hns3_parse_copper_phy_params(desc, mac);
4731
4732         return 0;
4733 }
4734
4735 static int
4736 hns3_update_copper_link_info(struct hns3_hw *hw)
4737 {
4738         struct hns3_mac *mac = &hw->mac;
4739         struct hns3_mac mac_info;
4740         int ret;
4741
4742         memset(&mac_info, 0, sizeof(struct hns3_mac));
4743         ret = hns3_get_copper_phy_params(hw, &mac_info);
4744         if (ret)
4745                 return ret;
4746
4747         if (mac_info.link_speed != mac->link_speed) {
4748                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4749                 if (ret)
4750                         return ret;
4751         }
4752
4753         mac->link_speed = mac_info.link_speed;
4754         mac->link_duplex = mac_info.link_duplex;
4755         mac->link_autoneg = mac_info.link_autoneg;
4756         mac->supported_speed = mac_info.supported_speed;
4757         mac->advertising = mac_info.advertising;
4758         mac->lp_advertising = mac_info.lp_advertising;
4759         mac->support_autoneg = mac_info.support_autoneg;
4760
4761         return 0;
4762 }
4763
4764 static int
4765 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4766 {
4767         struct hns3_adapter *hns = eth_dev->data->dev_private;
4768         struct hns3_hw *hw = &hns->hw;
4769         int ret = 0;
4770
4771         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4772                 ret = hns3_update_copper_link_info(hw);
4773         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4774                 ret = hns3_update_fiber_link_info(hw);
4775
4776         return ret;
4777 }
4778
4779 static int
4780 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4781 {
4782         struct hns3_config_mac_mode_cmd *req;
4783         struct hns3_cmd_desc desc;
4784         uint32_t loop_en = 0;
4785         uint8_t val = 0;
4786         int ret;
4787
4788         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4789
4790         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4791         if (enable)
4792                 val = 1;
4793         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4794         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4795         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4796         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4797         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4798         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4799         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4800         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4801         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4802         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4803
4804         /*
4805          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4806          * when receiving frames. Otherwise, CRC will be stripped.
4807          */
4808         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4809                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4810         else
4811                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4812         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4813         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4814         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4815         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4816
4817         ret = hns3_cmd_send(hw, &desc, 1);
4818         if (ret)
4819                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4820
4821         return ret;
4822 }
4823
4824 static int
4825 hns3_get_mac_link_status(struct hns3_hw *hw)
4826 {
4827         struct hns3_link_status_cmd *req;
4828         struct hns3_cmd_desc desc;
4829         int link_status;
4830         int ret;
4831
4832         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4833         ret = hns3_cmd_send(hw, &desc, 1);
4834         if (ret) {
4835                 hns3_err(hw, "get link status cmd failed %d", ret);
4836                 return ETH_LINK_DOWN;
4837         }
4838
4839         req = (struct hns3_link_status_cmd *)desc.data;
4840         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4841
4842         return !!link_status;
4843 }
4844
4845 static bool
4846 hns3_update_link_status(struct hns3_hw *hw)
4847 {
4848         int state;
4849
4850         state = hns3_get_mac_link_status(hw);
4851         if (state != hw->mac.link_status) {
4852                 hw->mac.link_status = state;
4853                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4854                 hns3_config_mac_tnl_int(hw,
4855                                         state == ETH_LINK_UP ? true : false);
4856                 return true;
4857         }
4858
4859         return false;
4860 }
4861
4862 void
4863 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4864 {
4865         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4866         struct rte_eth_link new_link;
4867         int ret;
4868
4869         if (query)
4870                 hns3_update_port_link_info(dev);
4871
4872         memset(&new_link, 0, sizeof(new_link));
4873         hns3_setup_linkstatus(dev, &new_link);
4874
4875         ret = rte_eth_linkstatus_set(dev, &new_link);
4876         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4877                 hns3_start_report_lse(dev);
4878 }
4879
4880 static void
4881 hns3_service_handler(void *param)
4882 {
4883         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4884         struct hns3_adapter *hns = eth_dev->data->dev_private;
4885         struct hns3_hw *hw = &hns->hw;
4886
4887         if (!hns3_is_reset_pending(hns))
4888                 hns3_update_linkstatus_and_event(hw, true);
4889         else
4890                 hns3_warn(hw, "Cancel the query when reset is pending");
4891
4892         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4893 }
4894
4895 static int
4896 hns3_init_hardware(struct hns3_adapter *hns)
4897 {
4898         struct hns3_hw *hw = &hns->hw;
4899         int ret;
4900
4901         ret = hns3_map_tqp(hw);
4902         if (ret) {
4903                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4904                 return ret;
4905         }
4906
4907         ret = hns3_init_umv_space(hw);
4908         if (ret) {
4909                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4910                 return ret;
4911         }
4912
4913         ret = hns3_mac_init(hw);
4914         if (ret) {
4915                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4916                 goto err_mac_init;
4917         }
4918
4919         ret = hns3_init_mgr_tbl(hw);
4920         if (ret) {
4921                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4922                 goto err_mac_init;
4923         }
4924
4925         ret = hns3_promisc_init(hw);
4926         if (ret) {
4927                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4928                              ret);
4929                 goto err_mac_init;
4930         }
4931
4932         ret = hns3_init_vlan_config(hns);
4933         if (ret) {
4934                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4935                 goto err_mac_init;
4936         }
4937
4938         ret = hns3_dcb_init(hw);
4939         if (ret) {
4940                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4941                 goto err_mac_init;
4942         }
4943
4944         ret = hns3_init_fd_config(hns);
4945         if (ret) {
4946                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4947                 goto err_mac_init;
4948         }
4949
4950         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4951         if (ret) {
4952                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4953                 goto err_mac_init;
4954         }
4955
4956         ret = hns3_config_gro(hw, false);
4957         if (ret) {
4958                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4959                 goto err_mac_init;
4960         }
4961
4962         /*
4963          * In the initialization clearing the all hardware mapping relationship
4964          * configurations between queues and interrupt vectors is needed, so
4965          * some error caused by the residual configurations, such as the
4966          * unexpected interrupt, can be avoid.
4967          */
4968         ret = hns3_init_ring_with_vector(hw);
4969         if (ret) {
4970                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4971                 goto err_mac_init;
4972         }
4973
4974         return 0;
4975
4976 err_mac_init:
4977         hns3_uninit_umv_space(hw);
4978         return ret;
4979 }
4980
4981 static int
4982 hns3_clear_hw(struct hns3_hw *hw)
4983 {
4984         struct hns3_cmd_desc desc;
4985         int ret;
4986
4987         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
4988
4989         ret = hns3_cmd_send(hw, &desc, 1);
4990         if (ret && ret != -EOPNOTSUPP)
4991                 return ret;
4992
4993         return 0;
4994 }
4995
4996 static void
4997 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
4998 {
4999         uint32_t val;
5000
5001         /*
5002          * The new firmware support report more hardware error types by
5003          * msix mode. These errors are defined as RAS errors in hardware
5004          * and belong to a different type from the MSI-x errors processed
5005          * by the network driver.
5006          *
5007          * Network driver should open the new error report on initialition
5008          */
5009         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5010         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5011         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5012 }
5013
5014 static uint32_t
5015 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5016 {
5017         struct hns3_mac *mac = &hw->mac;
5018
5019         switch (mac->link_speed) {
5020         case ETH_SPEED_NUM_1G:
5021                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5022         case ETH_SPEED_NUM_10G:
5023                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5024         case ETH_SPEED_NUM_25G:
5025                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5026         case ETH_SPEED_NUM_40G:
5027                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5028         case ETH_SPEED_NUM_50G:
5029                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5030         case ETH_SPEED_NUM_100G:
5031                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5032         case ETH_SPEED_NUM_200G:
5033                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5034         default:
5035                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5036                 return 0;
5037         }
5038 }
5039
5040 /*
5041  * Validity of supported_speed for firber and copper media type can be
5042  * guaranteed by the following policy:
5043  * Copper:
5044  *       Although the initialization of the phy in the firmware may not be
5045  *       completed, the firmware can guarantees that the supported_speed is
5046  *       an valid value.
5047  * Firber:
5048  *       If the version of firmware supports the acitive query way of the
5049  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5050  *       through it. If unsupported, use the SFP's speed as the value of the
5051  *       supported_speed.
5052  */
5053 static int
5054 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5055 {
5056         struct hns3_adapter *hns = eth_dev->data->dev_private;
5057         struct hns3_hw *hw = &hns->hw;
5058         struct hns3_mac *mac = &hw->mac;
5059         int ret;
5060
5061         ret = hns3_update_link_info(eth_dev);
5062         if (ret)
5063                 return ret;
5064
5065         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5066                 /*
5067                  * Some firmware does not support the report of supported_speed,
5068                  * and only report the effective speed of SFP. In this case, it
5069                  * is necessary to use the SFP's speed as the supported_speed.
5070                  */
5071                 if (mac->supported_speed == 0)
5072                         mac->supported_speed =
5073                                 hns3_set_firber_default_support_speed(hw);
5074         }
5075
5076         return 0;
5077 }
5078
5079 static void
5080 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5081 {
5082         struct hns3_mac *mac = &hns->hw.mac;
5083
5084         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5085                 hns->pf.support_fc_autoneg = true;
5086                 return;
5087         }
5088
5089         /*
5090          * Flow control auto-negotiation requires the cooperation of the driver
5091          * and firmware. Currently, the optical port does not support flow
5092          * control auto-negotiation.
5093          */
5094         hns->pf.support_fc_autoneg = false;
5095 }
5096
5097 static int
5098 hns3_init_pf(struct rte_eth_dev *eth_dev)
5099 {
5100         struct rte_device *dev = eth_dev->device;
5101         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5102         struct hns3_adapter *hns = eth_dev->data->dev_private;
5103         struct hns3_hw *hw = &hns->hw;
5104         int ret;
5105
5106         PMD_INIT_FUNC_TRACE();
5107
5108         /* Get hardware io base address from pcie BAR2 IO space */
5109         hw->io_base = pci_dev->mem_resource[2].addr;
5110
5111         /* Firmware command queue initialize */
5112         ret = hns3_cmd_init_queue(hw);
5113         if (ret) {
5114                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5115                 goto err_cmd_init_queue;
5116         }
5117
5118         hns3_clear_all_event_cause(hw);
5119
5120         /* Firmware command initialize */
5121         ret = hns3_cmd_init(hw);
5122         if (ret) {
5123                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5124                 goto err_cmd_init;
5125         }
5126
5127         /*
5128          * To ensure that the hardware environment is clean during
5129          * initialization, the driver actively clear the hardware environment
5130          * during initialization, including PF and corresponding VFs' vlan, mac,
5131          * flow table configurations, etc.
5132          */
5133         ret = hns3_clear_hw(hw);
5134         if (ret) {
5135                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5136                 goto err_cmd_init;
5137         }
5138
5139         /* Hardware statistics of imissed registers cleared. */
5140         ret = hns3_update_imissed_stats(hw, true);
5141         if (ret) {
5142                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5143                 goto err_cmd_init;
5144         }
5145
5146         hns3_config_all_msix_error(hw, true);
5147
5148         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5149                                          hns3_interrupt_handler,
5150                                          eth_dev);
5151         if (ret) {
5152                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5153                 goto err_intr_callback_register;
5154         }
5155
5156         ret = hns3_ptp_init(hw);
5157         if (ret)
5158                 goto err_get_config;
5159
5160         /* Enable interrupt */
5161         rte_intr_enable(&pci_dev->intr_handle);
5162         hns3_pf_enable_irq0(hw);
5163
5164         /* Get configuration */
5165         ret = hns3_get_configuration(hw);
5166         if (ret) {
5167                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5168                 goto err_get_config;
5169         }
5170
5171         ret = hns3_tqp_stats_init(hw);
5172         if (ret)
5173                 goto err_get_config;
5174
5175         ret = hns3_init_hardware(hns);
5176         if (ret) {
5177                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5178                 goto err_init_hw;
5179         }
5180
5181         /* Initialize flow director filter list & hash */
5182         ret = hns3_fdir_filter_init(hns);
5183         if (ret) {
5184                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5185                 goto err_fdir;
5186         }
5187
5188         hns3_rss_set_default_args(hw);
5189
5190         ret = hns3_enable_hw_error_intr(hns, true);
5191         if (ret) {
5192                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5193                              ret);
5194                 goto err_enable_intr;
5195         }
5196
5197         ret = hns3_get_port_supported_speed(eth_dev);
5198         if (ret) {
5199                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5200                              "by device, ret = %d.", ret);
5201                 goto err_supported_speed;
5202         }
5203
5204         hns3_get_fc_autoneg_capability(hns);
5205
5206         hns3_tm_conf_init(eth_dev);
5207
5208         return 0;
5209
5210 err_supported_speed:
5211         (void)hns3_enable_hw_error_intr(hns, false);
5212 err_enable_intr:
5213         hns3_fdir_filter_uninit(hns);
5214 err_fdir:
5215         hns3_uninit_umv_space(hw);
5216 err_init_hw:
5217         hns3_tqp_stats_uninit(hw);
5218 err_get_config:
5219         hns3_pf_disable_irq0(hw);
5220         rte_intr_disable(&pci_dev->intr_handle);
5221         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5222                              eth_dev);
5223 err_intr_callback_register:
5224 err_cmd_init:
5225         hns3_cmd_uninit(hw);
5226         hns3_cmd_destroy_queue(hw);
5227 err_cmd_init_queue:
5228         hw->io_base = NULL;
5229
5230         return ret;
5231 }
5232
5233 static void
5234 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5235 {
5236         struct hns3_adapter *hns = eth_dev->data->dev_private;
5237         struct rte_device *dev = eth_dev->device;
5238         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5239         struct hns3_hw *hw = &hns->hw;
5240
5241         PMD_INIT_FUNC_TRACE();
5242
5243         hns3_tm_conf_uninit(eth_dev);
5244         hns3_enable_hw_error_intr(hns, false);
5245         hns3_rss_uninit(hns);
5246         (void)hns3_config_gro(hw, false);
5247         hns3_promisc_uninit(hw);
5248         hns3_fdir_filter_uninit(hns);
5249         hns3_uninit_umv_space(hw);
5250         hns3_tqp_stats_uninit(hw);
5251         hns3_config_mac_tnl_int(hw, false);
5252         hns3_pf_disable_irq0(hw);
5253         rte_intr_disable(&pci_dev->intr_handle);
5254         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5255                              eth_dev);
5256         hns3_config_all_msix_error(hw, false);
5257         hns3_cmd_uninit(hw);
5258         hns3_cmd_destroy_queue(hw);
5259         hw->io_base = NULL;
5260 }
5261
5262 static uint32_t
5263 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5264 {
5265         uint32_t speed_bit;
5266
5267         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5268         case ETH_LINK_SPEED_10M:
5269                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5270                 break;
5271         case ETH_LINK_SPEED_10M_HD:
5272                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5273                 break;
5274         case ETH_LINK_SPEED_100M:
5275                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5276                 break;
5277         case ETH_LINK_SPEED_100M_HD:
5278                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5279                 break;
5280         case ETH_LINK_SPEED_1G:
5281                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5282                 break;
5283         default:
5284                 speed_bit = 0;
5285                 break;
5286         }
5287
5288         return speed_bit;
5289 }
5290
5291 static uint32_t
5292 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5293 {
5294         uint32_t speed_bit;
5295
5296         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5297         case ETH_LINK_SPEED_1G:
5298                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5299                 break;
5300         case ETH_LINK_SPEED_10G:
5301                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5302                 break;
5303         case ETH_LINK_SPEED_25G:
5304                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5305                 break;
5306         case ETH_LINK_SPEED_40G:
5307                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5308                 break;
5309         case ETH_LINK_SPEED_50G:
5310                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5311                 break;
5312         case ETH_LINK_SPEED_100G:
5313                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5314                 break;
5315         case ETH_LINK_SPEED_200G:
5316                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5317                 break;
5318         default:
5319                 speed_bit = 0;
5320                 break;
5321         }
5322
5323         return speed_bit;
5324 }
5325
5326 static int
5327 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5328 {
5329         struct hns3_mac *mac = &hw->mac;
5330         uint32_t supported_speed = mac->supported_speed;
5331         uint32_t speed_bit = 0;
5332
5333         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5334                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5335         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5336                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5337
5338         if (!(speed_bit & supported_speed)) {
5339                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5340                          link_speeds);
5341                 return -EINVAL;
5342         }
5343
5344         return 0;
5345 }
5346
5347 static inline uint32_t
5348 hns3_get_link_speed(uint32_t link_speeds)
5349 {
5350         uint32_t speed = ETH_SPEED_NUM_NONE;
5351
5352         if (link_speeds & ETH_LINK_SPEED_10M ||
5353             link_speeds & ETH_LINK_SPEED_10M_HD)
5354                 speed = ETH_SPEED_NUM_10M;
5355         if (link_speeds & ETH_LINK_SPEED_100M ||
5356             link_speeds & ETH_LINK_SPEED_100M_HD)
5357                 speed = ETH_SPEED_NUM_100M;
5358         if (link_speeds & ETH_LINK_SPEED_1G)
5359                 speed = ETH_SPEED_NUM_1G;
5360         if (link_speeds & ETH_LINK_SPEED_10G)
5361                 speed = ETH_SPEED_NUM_10G;
5362         if (link_speeds & ETH_LINK_SPEED_25G)
5363                 speed = ETH_SPEED_NUM_25G;
5364         if (link_speeds & ETH_LINK_SPEED_40G)
5365                 speed = ETH_SPEED_NUM_40G;
5366         if (link_speeds & ETH_LINK_SPEED_50G)
5367                 speed = ETH_SPEED_NUM_50G;
5368         if (link_speeds & ETH_LINK_SPEED_100G)
5369                 speed = ETH_SPEED_NUM_100G;
5370         if (link_speeds & ETH_LINK_SPEED_200G)
5371                 speed = ETH_SPEED_NUM_200G;
5372
5373         return speed;
5374 }
5375
5376 static uint8_t
5377 hns3_get_link_duplex(uint32_t link_speeds)
5378 {
5379         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5380             (link_speeds & ETH_LINK_SPEED_100M_HD))
5381                 return ETH_LINK_HALF_DUPLEX;
5382         else
5383                 return ETH_LINK_FULL_DUPLEX;
5384 }
5385
5386 static int
5387 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5388                                 struct hns3_set_link_speed_cfg *cfg)
5389 {
5390         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5391         struct hns3_phy_params_bd0_cmd *req;
5392         uint16_t i;
5393
5394         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5395                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5396                                           false);
5397                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5398         }
5399         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5400         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5401         req->autoneg = cfg->autoneg;
5402
5403         /*
5404          * The full speed capability is used to negotiate when
5405          * auto-negotiation is enabled.
5406          */
5407         if (cfg->autoneg) {
5408                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5409                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5410                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5411                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5412                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5413         } else {
5414                 req->speed = cfg->speed;
5415                 req->duplex = cfg->duplex;
5416         }
5417
5418         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5419 }
5420
5421 static int
5422 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5423 {
5424         struct hns3_config_auto_neg_cmd *req;
5425         struct hns3_cmd_desc desc;
5426         uint32_t flag = 0;
5427         int ret;
5428
5429         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5430
5431         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5432         if (enable)
5433                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5434         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5435
5436         ret = hns3_cmd_send(hw, &desc, 1);
5437         if (ret)
5438                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5439
5440         return ret;
5441 }
5442
5443 static int
5444 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5445                                struct hns3_set_link_speed_cfg *cfg)
5446 {
5447         int ret;
5448
5449         if (hw->mac.support_autoneg) {
5450                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5451                 if (ret) {
5452                         hns3_err(hw, "failed to configure auto-negotiation.");
5453                         return ret;
5454                 }
5455
5456                 /*
5457                  * To enable auto-negotiation, we only need to open the switch
5458                  * of auto-negotiation, then firmware sets all speed
5459                  * capabilities.
5460                  */
5461                 if (cfg->autoneg)
5462                         return 0;
5463         }
5464
5465         /*
5466          * Some hardware doesn't support auto-negotiation, but users may not
5467          * configure link_speeds (default 0), which means auto-negotiation
5468          * In this case, a warning message need to be printed, instead of
5469          * an error.
5470          */
5471         if (cfg->autoneg) {
5472                 hns3_warn(hw, "auto-negotiation is not supported.");
5473                 return 0;
5474         }
5475
5476         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5477 }
5478
5479 static int
5480 hns3_set_port_link_speed(struct hns3_hw *hw,
5481                          struct hns3_set_link_speed_cfg *cfg)
5482 {
5483         int ret;
5484
5485         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5486 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5487                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5488                 if (pf->is_tmp_phy)
5489                         return 0;
5490 #endif
5491
5492                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5493                 if (ret) {
5494                         hns3_err(hw, "failed to set copper port link speed,"
5495                                  "ret = %d.", ret);
5496                         return ret;
5497                 }
5498         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5499                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5500                 if (ret) {
5501                         hns3_err(hw, "failed to set fiber port link speed,"
5502                                  "ret = %d.", ret);
5503                         return ret;
5504                 }
5505         }
5506
5507         return 0;
5508 }
5509
5510 static int
5511 hns3_apply_link_speed(struct hns3_hw *hw)
5512 {
5513         struct rte_eth_conf *conf = &hw->data->dev_conf;
5514         struct hns3_set_link_speed_cfg cfg;
5515         int ret;
5516
5517         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5518         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5519                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5520         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5521                 ret = hns3_check_port_speed(hw, conf->link_speeds);
5522                 if (ret)
5523                         return ret;
5524
5525                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5526                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5527         }
5528
5529         return hns3_set_port_link_speed(hw, &cfg);
5530 }
5531
5532 static int
5533 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5534 {
5535         struct hns3_hw *hw = &hns->hw;
5536         int ret;
5537
5538         ret = hns3_dcb_cfg_update(hns);
5539         if (ret)
5540                 return ret;
5541
5542         /*
5543          * The hns3_dcb_cfg_update may configure TM module, so
5544          * hns3_tm_conf_update must called later.
5545          */
5546         ret = hns3_tm_conf_update(hw);
5547         if (ret) {
5548                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5549                 return ret;
5550         }
5551
5552         hns3_enable_rxd_adv_layout(hw);
5553
5554         ret = hns3_init_queues(hns, reset_queue);
5555         if (ret) {
5556                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5557                 return ret;
5558         }
5559
5560         ret = hns3_cfg_mac_mode(hw, true);
5561         if (ret) {
5562                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5563                 goto err_config_mac_mode;
5564         }
5565
5566         ret = hns3_apply_link_speed(hw);
5567         if (ret)
5568                 goto err_config_mac_mode;
5569
5570         return 0;
5571
5572 err_config_mac_mode:
5573         (void)hns3_cfg_mac_mode(hw, false);
5574         hns3_dev_release_mbufs(hns);
5575         /*
5576          * Here is exception handling, hns3_reset_all_tqps will have the
5577          * corresponding error message if it is handled incorrectly, so it is
5578          * not necessary to check hns3_reset_all_tqps return value, here keep
5579          * ret as the error code causing the exception.
5580          */
5581         (void)hns3_reset_all_tqps(hns);
5582         return ret;
5583 }
5584
5585 static int
5586 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5587 {
5588         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5589         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5591         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5592         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5593         uint32_t intr_vector;
5594         uint16_t q_id;
5595         int ret;
5596
5597         /*
5598          * hns3 needs a separate interrupt to be used as event interrupt which
5599          * could not be shared with task queue pair, so KERNEL drivers need
5600          * support multiple interrupt vectors.
5601          */
5602         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5603             !rte_intr_cap_multiple(intr_handle))
5604                 return 0;
5605
5606         rte_intr_disable(intr_handle);
5607         intr_vector = hw->used_rx_queues;
5608         /* creates event fd for each intr vector when MSIX is used */
5609         if (rte_intr_efd_enable(intr_handle, intr_vector))
5610                 return -EINVAL;
5611
5612         if (intr_handle->intr_vec == NULL) {
5613                 intr_handle->intr_vec =
5614                         rte_zmalloc("intr_vec",
5615                                     hw->used_rx_queues * sizeof(int), 0);
5616                 if (intr_handle->intr_vec == NULL) {
5617                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5618                                         hw->used_rx_queues);
5619                         ret = -ENOMEM;
5620                         goto alloc_intr_vec_error;
5621                 }
5622         }
5623
5624         if (rte_intr_allow_others(intr_handle)) {
5625                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5626                 base = RTE_INTR_VEC_RXTX_OFFSET;
5627         }
5628
5629         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5630                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5631                                                  HNS3_RING_TYPE_RX, q_id);
5632                 if (ret)
5633                         goto bind_vector_error;
5634                 intr_handle->intr_vec[q_id] = vec;
5635                 /*
5636                  * If there are not enough efds (e.g. not enough interrupt),
5637                  * remaining queues will be bond to the last interrupt.
5638                  */
5639                 if (vec < base + intr_handle->nb_efd - 1)
5640                         vec++;
5641         }
5642         rte_intr_enable(intr_handle);
5643         return 0;
5644
5645 bind_vector_error:
5646         rte_free(intr_handle->intr_vec);
5647         intr_handle->intr_vec = NULL;
5648 alloc_intr_vec_error:
5649         rte_intr_efd_disable(intr_handle);
5650         return ret;
5651 }
5652
5653 static int
5654 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5655 {
5656         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5657         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5658         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5659         uint16_t q_id;
5660         int ret;
5661
5662         if (dev->data->dev_conf.intr_conf.rxq == 0)
5663                 return 0;
5664
5665         if (rte_intr_dp_is_en(intr_handle)) {
5666                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5667                         ret = hns3_bind_ring_with_vector(hw,
5668                                         intr_handle->intr_vec[q_id], true,
5669                                         HNS3_RING_TYPE_RX, q_id);
5670                         if (ret)
5671                                 return ret;
5672                 }
5673         }
5674
5675         return 0;
5676 }
5677
5678 static void
5679 hns3_restore_filter(struct rte_eth_dev *dev)
5680 {
5681         hns3_restore_rss_filter(dev);
5682 }
5683
5684 static int
5685 hns3_dev_start(struct rte_eth_dev *dev)
5686 {
5687         struct hns3_adapter *hns = dev->data->dev_private;
5688         struct hns3_hw *hw = &hns->hw;
5689         int ret;
5690
5691         PMD_INIT_FUNC_TRACE();
5692         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5693                 return -EBUSY;
5694
5695         rte_spinlock_lock(&hw->lock);
5696         hw->adapter_state = HNS3_NIC_STARTING;
5697
5698         ret = hns3_do_start(hns, true);
5699         if (ret) {
5700                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5701                 rte_spinlock_unlock(&hw->lock);
5702                 return ret;
5703         }
5704         ret = hns3_map_rx_interrupt(dev);
5705         if (ret)
5706                 goto map_rx_inter_err;
5707
5708         /*
5709          * There are three register used to control the status of a TQP
5710          * (contains a pair of Tx queue and Rx queue) in the new version network
5711          * engine. One is used to control the enabling of Tx queue, the other is
5712          * used to control the enabling of Rx queue, and the last is the master
5713          * switch used to control the enabling of the tqp. The Tx register and
5714          * TQP register must be enabled at the same time to enable a Tx queue.
5715          * The same applies to the Rx queue. For the older network engine, this
5716          * function only refresh the enabled flag, and it is used to update the
5717          * status of queue in the dpdk framework.
5718          */
5719         ret = hns3_start_all_txqs(dev);
5720         if (ret)
5721                 goto map_rx_inter_err;
5722
5723         ret = hns3_start_all_rxqs(dev);
5724         if (ret)
5725                 goto start_all_rxqs_fail;
5726
5727         hw->adapter_state = HNS3_NIC_STARTED;
5728         rte_spinlock_unlock(&hw->lock);
5729
5730         hns3_rx_scattered_calc(dev);
5731         hns3_set_rxtx_function(dev);
5732         hns3_mp_req_start_rxtx(dev);
5733
5734         hns3_restore_filter(dev);
5735
5736         /* Enable interrupt of all rx queues before enabling queues */
5737         hns3_dev_all_rx_queue_intr_enable(hw, true);
5738
5739         /*
5740          * After finished the initialization, enable tqps to receive/transmit
5741          * packets and refresh all queue status.
5742          */
5743         hns3_start_tqps(hw);
5744
5745         hns3_tm_dev_start_proc(hw);
5746
5747         if (dev->data->dev_conf.intr_conf.lsc != 0)
5748                 hns3_dev_link_update(dev, 0);
5749         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5750
5751         hns3_info(hw, "hns3 dev start successful!");
5752
5753         return 0;
5754
5755 start_all_rxqs_fail:
5756         hns3_stop_all_txqs(dev);
5757 map_rx_inter_err:
5758         (void)hns3_do_stop(hns);
5759         hw->adapter_state = HNS3_NIC_CONFIGURED;
5760         rte_spinlock_unlock(&hw->lock);
5761
5762         return ret;
5763 }
5764
5765 static int
5766 hns3_do_stop(struct hns3_adapter *hns)
5767 {
5768         struct hns3_hw *hw = &hns->hw;
5769         int ret;
5770
5771         /*
5772          * The "hns3_do_stop" function will also be called by .stop_service to
5773          * prepare reset. At the time of global or IMP reset, the command cannot
5774          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5775          * accessed during the reset process. So the mbuf can not be released
5776          * during reset and is required to be released after the reset is
5777          * completed.
5778          */
5779         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5780                 hns3_dev_release_mbufs(hns);
5781
5782         ret = hns3_cfg_mac_mode(hw, false);
5783         if (ret)
5784                 return ret;
5785         hw->mac.link_status = ETH_LINK_DOWN;
5786
5787         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5788                 hns3_configure_all_mac_addr(hns, true);
5789                 ret = hns3_reset_all_tqps(hns);
5790                 if (ret) {
5791                         hns3_err(hw, "failed to reset all queues ret = %d.",
5792                                  ret);
5793                         return ret;
5794                 }
5795         }
5796         hw->mac.default_addr_setted = false;
5797         return 0;
5798 }
5799
5800 static void
5801 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5802 {
5803         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5804         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5805         struct hns3_adapter *hns = dev->data->dev_private;
5806         struct hns3_hw *hw = &hns->hw;
5807         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5808         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5809         uint16_t q_id;
5810
5811         if (dev->data->dev_conf.intr_conf.rxq == 0)
5812                 return;
5813
5814         /* unmap the ring with vector */
5815         if (rte_intr_allow_others(intr_handle)) {
5816                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5817                 base = RTE_INTR_VEC_RXTX_OFFSET;
5818         }
5819         if (rte_intr_dp_is_en(intr_handle)) {
5820                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5821                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5822                                                          HNS3_RING_TYPE_RX,
5823                                                          q_id);
5824                         if (vec < base + intr_handle->nb_efd - 1)
5825                                 vec++;
5826                 }
5827         }
5828         /* Clean datapath event and queue/vec mapping */
5829         rte_intr_efd_disable(intr_handle);
5830         if (intr_handle->intr_vec) {
5831                 rte_free(intr_handle->intr_vec);
5832                 intr_handle->intr_vec = NULL;
5833         }
5834 }
5835
5836 static int
5837 hns3_dev_stop(struct rte_eth_dev *dev)
5838 {
5839         struct hns3_adapter *hns = dev->data->dev_private;
5840         struct hns3_hw *hw = &hns->hw;
5841
5842         PMD_INIT_FUNC_TRACE();
5843         dev->data->dev_started = 0;
5844
5845         hw->adapter_state = HNS3_NIC_STOPPING;
5846         hns3_set_rxtx_function(dev);
5847         rte_wmb();
5848         /* Disable datapath on secondary process. */
5849         hns3_mp_req_stop_rxtx(dev);
5850         /* Prevent crashes when queues are still in use. */
5851         rte_delay_ms(hw->tqps_num);
5852
5853         rte_spinlock_lock(&hw->lock);
5854         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5855                 hns3_tm_dev_stop_proc(hw);
5856                 hns3_config_mac_tnl_int(hw, false);
5857                 hns3_stop_tqps(hw);
5858                 hns3_do_stop(hns);
5859                 hns3_unmap_rx_interrupt(dev);
5860                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5861         }
5862         hns3_rx_scattered_reset(dev);
5863         rte_eal_alarm_cancel(hns3_service_handler, dev);
5864         hns3_stop_report_lse(dev);
5865         rte_spinlock_unlock(&hw->lock);
5866
5867         return 0;
5868 }
5869
5870 static int
5871 hns3_dev_close(struct rte_eth_dev *eth_dev)
5872 {
5873         struct hns3_adapter *hns = eth_dev->data->dev_private;
5874         struct hns3_hw *hw = &hns->hw;
5875         int ret = 0;
5876
5877         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5878                 rte_free(eth_dev->process_private);
5879                 eth_dev->process_private = NULL;
5880                 return 0;
5881         }
5882
5883         if (hw->adapter_state == HNS3_NIC_STARTED)
5884                 ret = hns3_dev_stop(eth_dev);
5885
5886         hw->adapter_state = HNS3_NIC_CLOSING;
5887         hns3_reset_abort(hns);
5888         hw->adapter_state = HNS3_NIC_CLOSED;
5889
5890         hns3_configure_all_mc_mac_addr(hns, true);
5891         hns3_remove_all_vlan_table(hns);
5892         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5893         hns3_uninit_pf(eth_dev);
5894         hns3_free_all_queues(eth_dev);
5895         rte_free(hw->reset.wait_data);
5896         rte_free(eth_dev->process_private);
5897         eth_dev->process_private = NULL;
5898         hns3_mp_uninit_primary();
5899         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5900
5901         return ret;
5902 }
5903
5904 static void
5905 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5906                                    bool *tx_pause)
5907 {
5908         struct hns3_mac *mac = &hw->mac;
5909         uint32_t advertising = mac->advertising;
5910         uint32_t lp_advertising = mac->lp_advertising;
5911         *rx_pause = false;
5912         *tx_pause = false;
5913
5914         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5915                 *rx_pause = true;
5916                 *tx_pause = true;
5917         } else if (advertising & lp_advertising &
5918                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5919                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5920                         *rx_pause = true;
5921                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5922                         *tx_pause = true;
5923         }
5924 }
5925
5926 static enum hns3_fc_mode
5927 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5928 {
5929         enum hns3_fc_mode current_mode;
5930         bool rx_pause = false;
5931         bool tx_pause = false;
5932
5933         switch (hw->mac.media_type) {
5934         case HNS3_MEDIA_TYPE_COPPER:
5935                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5936                 break;
5937
5938         /*
5939          * Flow control auto-negotiation is not supported for fiber and
5940          * backpalne media type.
5941          */
5942         case HNS3_MEDIA_TYPE_FIBER:
5943         case HNS3_MEDIA_TYPE_BACKPLANE:
5944                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5945                 current_mode = hw->requested_fc_mode;
5946                 goto out;
5947         default:
5948                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5949                          hw->mac.media_type);
5950                 current_mode = HNS3_FC_NONE;
5951                 goto out;
5952         }
5953
5954         if (rx_pause && tx_pause)
5955                 current_mode = HNS3_FC_FULL;
5956         else if (rx_pause)
5957                 current_mode = HNS3_FC_RX_PAUSE;
5958         else if (tx_pause)
5959                 current_mode = HNS3_FC_TX_PAUSE;
5960         else
5961                 current_mode = HNS3_FC_NONE;
5962
5963 out:
5964         return current_mode;
5965 }
5966
5967 static enum hns3_fc_mode
5968 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
5969 {
5970         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5972         struct hns3_mac *mac = &hw->mac;
5973
5974         /*
5975          * When the flow control mode is obtained, the device may not complete
5976          * auto-negotiation. It is necessary to wait for link establishment.
5977          */
5978         (void)hns3_dev_link_update(dev, 1);
5979
5980         /*
5981          * If the link auto-negotiation of the nic is disabled, or the flow
5982          * control auto-negotiation is not supported, the forced flow control
5983          * mode is used.
5984          */
5985         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
5986                 return hw->requested_fc_mode;
5987
5988         return hns3_get_autoneg_fc_mode(hw);
5989 }
5990
5991 static int
5992 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
5993 {
5994         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5995         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5996         enum hns3_fc_mode current_mode;
5997
5998         current_mode = hns3_get_current_fc_mode(dev);
5999         switch (current_mode) {
6000         case HNS3_FC_FULL:
6001                 fc_conf->mode = RTE_FC_FULL;
6002                 break;
6003         case HNS3_FC_TX_PAUSE:
6004                 fc_conf->mode = RTE_FC_TX_PAUSE;
6005                 break;
6006         case HNS3_FC_RX_PAUSE:
6007                 fc_conf->mode = RTE_FC_RX_PAUSE;
6008                 break;
6009         case HNS3_FC_NONE:
6010         default:
6011                 fc_conf->mode = RTE_FC_NONE;
6012                 break;
6013         }
6014
6015         fc_conf->pause_time = pf->pause_time;
6016         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6017
6018         return 0;
6019 }
6020
6021 static void
6022 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6023 {
6024         switch (mode) {
6025         case RTE_FC_NONE:
6026                 hw->requested_fc_mode = HNS3_FC_NONE;
6027                 break;
6028         case RTE_FC_RX_PAUSE:
6029                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6030                 break;
6031         case RTE_FC_TX_PAUSE:
6032                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6033                 break;
6034         case RTE_FC_FULL:
6035                 hw->requested_fc_mode = HNS3_FC_FULL;
6036                 break;
6037         default:
6038                 hw->requested_fc_mode = HNS3_FC_NONE;
6039                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6040                           "configured to RTE_FC_NONE", mode);
6041                 break;
6042         }
6043 }
6044
6045 static int
6046 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6047 {
6048         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6049
6050         if (!pf->support_fc_autoneg) {
6051                 if (autoneg != 0) {
6052                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6053                         return -EOPNOTSUPP;
6054                 }
6055
6056                 /*
6057                  * Flow control auto-negotiation of the NIC is not supported,
6058                  * but other auto-negotiation features may be supported.
6059                  */
6060                 if (autoneg != hw->mac.link_autoneg) {
6061                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6062                         return -EOPNOTSUPP;
6063                 }
6064
6065                 return 0;
6066         }
6067
6068         /*
6069          * If flow control auto-negotiation of the NIC is supported, all
6070          * auto-negotiation features are supported.
6071          */
6072         if (autoneg != hw->mac.link_autoneg) {
6073                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6074                 return -EOPNOTSUPP;
6075         }
6076
6077         return 0;
6078 }
6079
6080 static int
6081 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6082 {
6083         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6084         int ret;
6085
6086         if (fc_conf->high_water || fc_conf->low_water ||
6087             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6088                 hns3_err(hw, "Unsupported flow control settings specified, "
6089                          "high_water(%u), low_water(%u), send_xon(%u) and "
6090                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6091                          fc_conf->high_water, fc_conf->low_water,
6092                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6093                 return -EINVAL;
6094         }
6095
6096         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6097         if (ret)
6098                 return ret;
6099
6100         if (!fc_conf->pause_time) {
6101                 hns3_err(hw, "Invalid pause time %u setting.",
6102                          fc_conf->pause_time);
6103                 return -EINVAL;
6104         }
6105
6106         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6107             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6108                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6109                          "current_fc_status = %d", hw->current_fc_status);
6110                 return -EOPNOTSUPP;
6111         }
6112
6113         if (hw->num_tc > 1) {
6114                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6115                 return -EOPNOTSUPP;
6116         }
6117
6118         hns3_get_fc_mode(hw, fc_conf->mode);
6119
6120         rte_spinlock_lock(&hw->lock);
6121         ret = hns3_fc_enable(dev, fc_conf);
6122         rte_spinlock_unlock(&hw->lock);
6123
6124         return ret;
6125 }
6126
6127 static int
6128 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6129                             struct rte_eth_pfc_conf *pfc_conf)
6130 {
6131         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6132         int ret;
6133
6134         if (!hns3_dev_dcb_supported(hw)) {
6135                 hns3_err(hw, "This port does not support dcb configurations.");
6136                 return -EOPNOTSUPP;
6137         }
6138
6139         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6140             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6141                 hns3_err(hw, "Unsupported flow control settings specified, "
6142                          "high_water(%u), low_water(%u), send_xon(%u) and "
6143                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6144                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6145                          pfc_conf->fc.send_xon,
6146                          pfc_conf->fc.mac_ctrl_frame_fwd);
6147                 return -EINVAL;
6148         }
6149         if (pfc_conf->fc.autoneg) {
6150                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6151                 return -EINVAL;
6152         }
6153         if (pfc_conf->fc.pause_time == 0) {
6154                 hns3_err(hw, "Invalid pause time %u setting.",
6155                          pfc_conf->fc.pause_time);
6156                 return -EINVAL;
6157         }
6158
6159         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6160             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6161                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6162                              "current_fc_status = %d", hw->current_fc_status);
6163                 return -EOPNOTSUPP;
6164         }
6165
6166         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6167
6168         rte_spinlock_lock(&hw->lock);
6169         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6170         rte_spinlock_unlock(&hw->lock);
6171
6172         return ret;
6173 }
6174
6175 static int
6176 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6177 {
6178         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6179         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6180         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6181         int i;
6182
6183         rte_spinlock_lock(&hw->lock);
6184         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6185                 dcb_info->nb_tcs = pf->local_max_tc;
6186         else
6187                 dcb_info->nb_tcs = 1;
6188
6189         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6190                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6191         for (i = 0; i < dcb_info->nb_tcs; i++)
6192                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6193
6194         for (i = 0; i < hw->num_tc; i++) {
6195                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6196                 dcb_info->tc_queue.tc_txq[0][i].base =
6197                                                 hw->tc_queue[i].tqp_offset;
6198                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6199                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6200                                                 hw->tc_queue[i].tqp_count;
6201         }
6202         rte_spinlock_unlock(&hw->lock);
6203
6204         return 0;
6205 }
6206
6207 static int
6208 hns3_reinit_dev(struct hns3_adapter *hns)
6209 {
6210         struct hns3_hw *hw = &hns->hw;
6211         int ret;
6212
6213         ret = hns3_cmd_init(hw);
6214         if (ret) {
6215                 hns3_err(hw, "Failed to init cmd: %d", ret);
6216                 return ret;
6217         }
6218
6219         ret = hns3_reset_all_tqps(hns);
6220         if (ret) {
6221                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6222                 return ret;
6223         }
6224
6225         ret = hns3_init_hardware(hns);
6226         if (ret) {
6227                 hns3_err(hw, "Failed to init hardware: %d", ret);
6228                 return ret;
6229         }
6230
6231         ret = hns3_enable_hw_error_intr(hns, true);
6232         if (ret) {
6233                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6234                              ret);
6235                 return ret;
6236         }
6237         hns3_info(hw, "Reset done, driver initialization finished.");
6238
6239         return 0;
6240 }
6241
6242 static bool
6243 is_pf_reset_done(struct hns3_hw *hw)
6244 {
6245         uint32_t val, reg, reg_bit;
6246
6247         switch (hw->reset.level) {
6248         case HNS3_IMP_RESET:
6249                 reg = HNS3_GLOBAL_RESET_REG;
6250                 reg_bit = HNS3_IMP_RESET_BIT;
6251                 break;
6252         case HNS3_GLOBAL_RESET:
6253                 reg = HNS3_GLOBAL_RESET_REG;
6254                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6255                 break;
6256         case HNS3_FUNC_RESET:
6257                 reg = HNS3_FUN_RST_ING;
6258                 reg_bit = HNS3_FUN_RST_ING_B;
6259                 break;
6260         case HNS3_FLR_RESET:
6261         default:
6262                 hns3_err(hw, "Wait for unsupported reset level: %d",
6263                          hw->reset.level);
6264                 return true;
6265         }
6266         val = hns3_read_dev(hw, reg);
6267         if (hns3_get_bit(val, reg_bit))
6268                 return false;
6269         else
6270                 return true;
6271 }
6272
6273 bool
6274 hns3_is_reset_pending(struct hns3_adapter *hns)
6275 {
6276         struct hns3_hw *hw = &hns->hw;
6277         enum hns3_reset_level reset;
6278
6279         hns3_check_event_cause(hns, NULL);
6280         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6281
6282         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6283             hw->reset.level < reset) {
6284                 hns3_warn(hw, "High level reset %d is pending", reset);
6285                 return true;
6286         }
6287         reset = hns3_get_reset_level(hns, &hw->reset.request);
6288         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6289             hw->reset.level < reset) {
6290                 hns3_warn(hw, "High level reset %d is request", reset);
6291                 return true;
6292         }
6293         return false;
6294 }
6295
6296 static int
6297 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6298 {
6299         struct hns3_hw *hw = &hns->hw;
6300         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6301         struct timeval tv;
6302
6303         if (wait_data->result == HNS3_WAIT_SUCCESS)
6304                 return 0;
6305         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6306                 gettimeofday(&tv, NULL);
6307                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6308                           tv.tv_sec, tv.tv_usec);
6309                 return -ETIME;
6310         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6311                 return -EAGAIN;
6312
6313         wait_data->hns = hns;
6314         wait_data->check_completion = is_pf_reset_done;
6315         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6316                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
6317         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6318         wait_data->count = HNS3_RESET_WAIT_CNT;
6319         wait_data->result = HNS3_WAIT_REQUEST;
6320         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6321         return -EAGAIN;
6322 }
6323
6324 static int
6325 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6326 {
6327         struct hns3_cmd_desc desc;
6328         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6329
6330         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6331         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6332         req->fun_reset_vfid = func_id;
6333
6334         return hns3_cmd_send(hw, &desc, 1);
6335 }
6336
6337 static int
6338 hns3_imp_reset_cmd(struct hns3_hw *hw)
6339 {
6340         struct hns3_cmd_desc desc;
6341
6342         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6343         desc.data[0] = 0xeedd;
6344
6345         return hns3_cmd_send(hw, &desc, 1);
6346 }
6347
6348 static void
6349 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6350 {
6351         struct hns3_hw *hw = &hns->hw;
6352         struct timeval tv;
6353         uint32_t val;
6354
6355         gettimeofday(&tv, NULL);
6356         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6357             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6358                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6359                           tv.tv_sec, tv.tv_usec);
6360                 return;
6361         }
6362
6363         switch (reset_level) {
6364         case HNS3_IMP_RESET:
6365                 hns3_imp_reset_cmd(hw);
6366                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6367                           tv.tv_sec, tv.tv_usec);
6368                 break;
6369         case HNS3_GLOBAL_RESET:
6370                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6371                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6372                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6373                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6374                           tv.tv_sec, tv.tv_usec);
6375                 break;
6376         case HNS3_FUNC_RESET:
6377                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6378                           tv.tv_sec, tv.tv_usec);
6379                 /* schedule again to check later */
6380                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6381                 hns3_schedule_reset(hns);
6382                 break;
6383         default:
6384                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6385                 return;
6386         }
6387         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6388 }
6389
6390 static enum hns3_reset_level
6391 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6392 {
6393         struct hns3_hw *hw = &hns->hw;
6394         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6395
6396         /* Return the highest priority reset level amongst all */
6397         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6398                 reset_level = HNS3_IMP_RESET;
6399         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6400                 reset_level = HNS3_GLOBAL_RESET;
6401         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6402                 reset_level = HNS3_FUNC_RESET;
6403         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6404                 reset_level = HNS3_FLR_RESET;
6405
6406         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6407                 return HNS3_NONE_RESET;
6408
6409         return reset_level;
6410 }
6411
6412 static void
6413 hns3_record_imp_error(struct hns3_adapter *hns)
6414 {
6415         struct hns3_hw *hw = &hns->hw;
6416         uint32_t reg_val;
6417
6418         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6419         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6420                 hns3_warn(hw, "Detected IMP RD poison!");
6421                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6422                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6423         }
6424
6425         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6426                 hns3_warn(hw, "Detected IMP CMDQ error!");
6427                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6428                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6429         }
6430 }
6431
6432 static int
6433 hns3_prepare_reset(struct hns3_adapter *hns)
6434 {
6435         struct hns3_hw *hw = &hns->hw;
6436         uint32_t reg_val;
6437         int ret;
6438
6439         switch (hw->reset.level) {
6440         case HNS3_FUNC_RESET:
6441                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6442                 if (ret)
6443                         return ret;
6444
6445                 /*
6446                  * After performaning pf reset, it is not necessary to do the
6447                  * mailbox handling or send any command to firmware, because
6448                  * any mailbox handling or command to firmware is only valid
6449                  * after hns3_cmd_init is called.
6450                  */
6451                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6452                 hw->reset.stats.request_cnt++;
6453                 break;
6454         case HNS3_IMP_RESET:
6455                 hns3_record_imp_error(hns);
6456                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6457                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6458                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6459                 break;
6460         default:
6461                 break;
6462         }
6463         return 0;
6464 }
6465
6466 static int
6467 hns3_set_rst_done(struct hns3_hw *hw)
6468 {
6469         struct hns3_pf_rst_done_cmd *req;
6470         struct hns3_cmd_desc desc;
6471
6472         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6473         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6474         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6475         return hns3_cmd_send(hw, &desc, 1);
6476 }
6477
6478 static int
6479 hns3_stop_service(struct hns3_adapter *hns)
6480 {
6481         struct hns3_hw *hw = &hns->hw;
6482         struct rte_eth_dev *eth_dev;
6483
6484         eth_dev = &rte_eth_devices[hw->data->port_id];
6485         hw->mac.link_status = ETH_LINK_DOWN;
6486         if (hw->adapter_state == HNS3_NIC_STARTED) {
6487                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6488                 hns3_update_linkstatus_and_event(hw, false);
6489         }
6490
6491         hns3_set_rxtx_function(eth_dev);
6492         rte_wmb();
6493         /* Disable datapath on secondary process. */
6494         hns3_mp_req_stop_rxtx(eth_dev);
6495         rte_delay_ms(hw->tqps_num);
6496
6497         rte_spinlock_lock(&hw->lock);
6498         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6499             hw->adapter_state == HNS3_NIC_STOPPING) {
6500                 hns3_enable_all_queues(hw, false);
6501                 hns3_do_stop(hns);
6502                 hw->reset.mbuf_deferred_free = true;
6503         } else
6504                 hw->reset.mbuf_deferred_free = false;
6505
6506         /*
6507          * It is cumbersome for hardware to pick-and-choose entries for deletion
6508          * from table space. Hence, for function reset software intervention is
6509          * required to delete the entries
6510          */
6511         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6512                 hns3_configure_all_mc_mac_addr(hns, true);
6513         rte_spinlock_unlock(&hw->lock);
6514
6515         return 0;
6516 }
6517
6518 static int
6519 hns3_start_service(struct hns3_adapter *hns)
6520 {
6521         struct hns3_hw *hw = &hns->hw;
6522         struct rte_eth_dev *eth_dev;
6523
6524         if (hw->reset.level == HNS3_IMP_RESET ||
6525             hw->reset.level == HNS3_GLOBAL_RESET)
6526                 hns3_set_rst_done(hw);
6527         eth_dev = &rte_eth_devices[hw->data->port_id];
6528         hns3_set_rxtx_function(eth_dev);
6529         hns3_mp_req_start_rxtx(eth_dev);
6530         if (hw->adapter_state == HNS3_NIC_STARTED) {
6531                 /*
6532                  * This API parent function already hold the hns3_hw.lock, the
6533                  * hns3_service_handler may report lse, in bonding application
6534                  * it will call driver's ops which may acquire the hns3_hw.lock
6535                  * again, thus lead to deadlock.
6536                  * We defer calls hns3_service_handler to avoid the deadlock.
6537                  */
6538                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6539                                   hns3_service_handler, eth_dev);
6540
6541                 /* Enable interrupt of all rx queues before enabling queues */
6542                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6543                 /*
6544                  * Enable state of each rxq and txq will be recovered after
6545                  * reset, so we need to restore them before enable all tqps;
6546                  */
6547                 hns3_restore_tqp_enable_state(hw);
6548                 /*
6549                  * When finished the initialization, enable queues to receive
6550                  * and transmit packets.
6551                  */
6552                 hns3_enable_all_queues(hw, true);
6553         }
6554
6555         return 0;
6556 }
6557
6558 static int
6559 hns3_restore_conf(struct hns3_adapter *hns)
6560 {
6561         struct hns3_hw *hw = &hns->hw;
6562         int ret;
6563
6564         ret = hns3_configure_all_mac_addr(hns, false);
6565         if (ret)
6566                 return ret;
6567
6568         ret = hns3_configure_all_mc_mac_addr(hns, false);
6569         if (ret)
6570                 goto err_mc_mac;
6571
6572         ret = hns3_dev_promisc_restore(hns);
6573         if (ret)
6574                 goto err_promisc;
6575
6576         ret = hns3_restore_vlan_table(hns);
6577         if (ret)
6578                 goto err_promisc;
6579
6580         ret = hns3_restore_vlan_conf(hns);
6581         if (ret)
6582                 goto err_promisc;
6583
6584         ret = hns3_restore_all_fdir_filter(hns);
6585         if (ret)
6586                 goto err_promisc;
6587
6588         ret = hns3_restore_ptp(hns);
6589         if (ret)
6590                 goto err_promisc;
6591
6592         ret = hns3_restore_rx_interrupt(hw);
6593         if (ret)
6594                 goto err_promisc;
6595
6596         ret = hns3_restore_gro_conf(hw);
6597         if (ret)
6598                 goto err_promisc;
6599
6600         ret = hns3_restore_fec(hw);
6601         if (ret)
6602                 goto err_promisc;
6603
6604         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6605                 ret = hns3_do_start(hns, false);
6606                 if (ret)
6607                         goto err_promisc;
6608                 hns3_info(hw, "hns3 dev restart successful!");
6609         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6610                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6611         return 0;
6612
6613 err_promisc:
6614         hns3_configure_all_mc_mac_addr(hns, true);
6615 err_mc_mac:
6616         hns3_configure_all_mac_addr(hns, true);
6617         return ret;
6618 }
6619
6620 static void
6621 hns3_reset_service(void *param)
6622 {
6623         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6624         struct hns3_hw *hw = &hns->hw;
6625         enum hns3_reset_level reset_level;
6626         struct timeval tv_delta;
6627         struct timeval tv_start;
6628         struct timeval tv;
6629         uint64_t msec;
6630         int ret;
6631
6632         /*
6633          * The interrupt is not triggered within the delay time.
6634          * The interrupt may have been lost. It is necessary to handle
6635          * the interrupt to recover from the error.
6636          */
6637         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6638                             SCHEDULE_DEFERRED) {
6639                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6640                                   __ATOMIC_RELAXED);
6641                 hns3_err(hw, "Handling interrupts in delayed tasks");
6642                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6643                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6644                 if (reset_level == HNS3_NONE_RESET) {
6645                         hns3_err(hw, "No reset level is set, try IMP reset");
6646                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6647                 }
6648         }
6649         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6650
6651         /*
6652          * Check if there is any ongoing reset in the hardware. This status can
6653          * be checked from reset_pending. If there is then, we need to wait for
6654          * hardware to complete reset.
6655          *    a. If we are able to figure out in reasonable time that hardware
6656          *       has fully resetted then, we can proceed with driver, client
6657          *       reset.
6658          *    b. else, we can come back later to check this status so re-sched
6659          *       now.
6660          */
6661         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6662         if (reset_level != HNS3_NONE_RESET) {
6663                 gettimeofday(&tv_start, NULL);
6664                 ret = hns3_reset_process(hns, reset_level);
6665                 gettimeofday(&tv, NULL);
6666                 timersub(&tv, &tv_start, &tv_delta);
6667                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6668                        tv_delta.tv_usec / USEC_PER_MSEC;
6669                 if (msec > HNS3_RESET_PROCESS_MS)
6670                         hns3_err(hw, "%d handle long time delta %" PRIx64
6671                                      " ms time=%ld.%.6ld",
6672                                  hw->reset.level, msec,
6673                                  tv.tv_sec, tv.tv_usec);
6674                 if (ret == -EAGAIN)
6675                         return;
6676         }
6677
6678         /* Check if we got any *new* reset requests to be honored */
6679         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6680         if (reset_level != HNS3_NONE_RESET)
6681                 hns3_msix_process(hns, reset_level);
6682 }
6683
6684 static unsigned int
6685 hns3_get_speed_capa_num(uint16_t device_id)
6686 {
6687         unsigned int num;
6688
6689         switch (device_id) {
6690         case HNS3_DEV_ID_25GE:
6691         case HNS3_DEV_ID_25GE_RDMA:
6692                 num = 2;
6693                 break;
6694         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6695         case HNS3_DEV_ID_200G_RDMA:
6696                 num = 1;
6697                 break;
6698         default:
6699                 num = 0;
6700                 break;
6701         }
6702
6703         return num;
6704 }
6705
6706 static int
6707 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6708                         uint16_t device_id)
6709 {
6710         switch (device_id) {
6711         case HNS3_DEV_ID_25GE:
6712         /* fallthrough */
6713         case HNS3_DEV_ID_25GE_RDMA:
6714                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6715                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6716
6717                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6718                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6719                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6720                 break;
6721         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6722                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6723                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6724                 break;
6725         case HNS3_DEV_ID_200G_RDMA:
6726                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6727                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6728                 break;
6729         default:
6730                 return -ENOTSUP;
6731         }
6732
6733         return 0;
6734 }
6735
6736 static int
6737 hns3_fec_get_capability(struct rte_eth_dev *dev,
6738                         struct rte_eth_fec_capa *speed_fec_capa,
6739                         unsigned int num)
6740 {
6741         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6742         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6743         uint16_t device_id = pci_dev->id.device_id;
6744         unsigned int capa_num;
6745         int ret;
6746
6747         capa_num = hns3_get_speed_capa_num(device_id);
6748         if (capa_num == 0) {
6749                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6750                          device_id);
6751                 return -ENOTSUP;
6752         }
6753
6754         if (speed_fec_capa == NULL || num < capa_num)
6755                 return capa_num;
6756
6757         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6758         if (ret)
6759                 return -ENOTSUP;
6760
6761         return capa_num;
6762 }
6763
6764 static int
6765 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6766 {
6767         struct hns3_config_fec_cmd *req;
6768         struct hns3_cmd_desc desc;
6769         int ret;
6770
6771         /*
6772          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6773          * in device of link speed
6774          * below 10 Gbps.
6775          */
6776         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6777                 *state = 0;
6778                 return 0;
6779         }
6780
6781         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6782         req = (struct hns3_config_fec_cmd *)desc.data;
6783         ret = hns3_cmd_send(hw, &desc, 1);
6784         if (ret) {
6785                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6786                          ret);
6787                 return ret;
6788         }
6789
6790         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6791         return 0;
6792 }
6793
6794 static int
6795 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6796 {
6797         struct hns3_sfp_info_cmd *resp;
6798         uint32_t tmp_fec_capa;
6799         uint8_t auto_state;
6800         struct hns3_cmd_desc desc;
6801         int ret;
6802
6803         /*
6804          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6805          * configured FEC mode is returned.
6806          * If link is up, current FEC mode is returned.
6807          */
6808         if (hw->mac.link_status == ETH_LINK_DOWN) {
6809                 ret = get_current_fec_auto_state(hw, &auto_state);
6810                 if (ret)
6811                         return ret;
6812
6813                 if (auto_state == 0x1) {
6814                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6815                         return 0;
6816                 }
6817         }
6818
6819         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6820         resp = (struct hns3_sfp_info_cmd *)desc.data;
6821         resp->query_type = HNS3_ACTIVE_QUERY;
6822
6823         ret = hns3_cmd_send(hw, &desc, 1);
6824         if (ret == -EOPNOTSUPP) {
6825                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6826                 return ret;
6827         } else if (ret) {
6828                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6829                 return ret;
6830         }
6831
6832         /*
6833          * FEC mode order defined in hns3 hardware is inconsistend with
6834          * that defined in the ethdev library. So the sequence needs
6835          * to be converted.
6836          */
6837         switch (resp->active_fec) {
6838         case HNS3_HW_FEC_MODE_NOFEC:
6839                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6840                 break;
6841         case HNS3_HW_FEC_MODE_BASER:
6842                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6843                 break;
6844         case HNS3_HW_FEC_MODE_RS:
6845                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6846                 break;
6847         default:
6848                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6849                 break;
6850         }
6851
6852         *fec_capa = tmp_fec_capa;
6853         return 0;
6854 }
6855
6856 static int
6857 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6858 {
6859         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860
6861         return hns3_fec_get_internal(hw, fec_capa);
6862 }
6863
6864 static int
6865 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6866 {
6867         struct hns3_config_fec_cmd *req;
6868         struct hns3_cmd_desc desc;
6869         int ret;
6870
6871         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6872
6873         req = (struct hns3_config_fec_cmd *)desc.data;
6874         switch (mode) {
6875         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6876                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6877                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6878                 break;
6879         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6880                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6881                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6882                 break;
6883         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6884                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6885                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6886                 break;
6887         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6888                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6889                 break;
6890         default:
6891                 return 0;
6892         }
6893         ret = hns3_cmd_send(hw, &desc, 1);
6894         if (ret)
6895                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6896
6897         return ret;
6898 }
6899
6900 static uint32_t
6901 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6902 {
6903         struct hns3_mac *mac = &hw->mac;
6904         uint32_t cur_capa;
6905
6906         switch (mac->link_speed) {
6907         case ETH_SPEED_NUM_10G:
6908                 cur_capa = fec_capa[1].capa;
6909                 break;
6910         case ETH_SPEED_NUM_25G:
6911         case ETH_SPEED_NUM_100G:
6912         case ETH_SPEED_NUM_200G:
6913                 cur_capa = fec_capa[0].capa;
6914                 break;
6915         default:
6916                 cur_capa = 0;
6917                 break;
6918         }
6919
6920         return cur_capa;
6921 }
6922
6923 static bool
6924 is_fec_mode_one_bit_set(uint32_t mode)
6925 {
6926         int cnt = 0;
6927         uint8_t i;
6928
6929         for (i = 0; i < sizeof(mode); i++)
6930                 if (mode >> i & 0x1)
6931                         cnt++;
6932
6933         return cnt == 1 ? true : false;
6934 }
6935
6936 static int
6937 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6938 {
6939 #define FEC_CAPA_NUM 2
6940         struct hns3_adapter *hns = dev->data->dev_private;
6941         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6942         struct hns3_pf *pf = &hns->pf;
6943
6944         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6945         uint32_t cur_capa;
6946         uint32_t num = FEC_CAPA_NUM;
6947         int ret;
6948
6949         ret = hns3_fec_get_capability(dev, fec_capa, num);
6950         if (ret < 0)
6951                 return ret;
6952
6953         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6954         if (!is_fec_mode_one_bit_set(mode))
6955                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6956                              "FEC mode should be only one bit set", mode);
6957
6958         /*
6959          * Check whether the configured mode is within the FEC capability.
6960          * If not, the configured mode will not be supported.
6961          */
6962         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6963         if (!(cur_capa & mode)) {
6964                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6965                 return -EINVAL;
6966         }
6967
6968         rte_spinlock_lock(&hw->lock);
6969         ret = hns3_set_fec_hw(hw, mode);
6970         if (ret) {
6971                 rte_spinlock_unlock(&hw->lock);
6972                 return ret;
6973         }
6974
6975         pf->fec_mode = mode;
6976         rte_spinlock_unlock(&hw->lock);
6977
6978         return 0;
6979 }
6980
6981 static int
6982 hns3_restore_fec(struct hns3_hw *hw)
6983 {
6984         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
6985         struct hns3_pf *pf = &hns->pf;
6986         uint32_t mode = pf->fec_mode;
6987         int ret;
6988
6989         ret = hns3_set_fec_hw(hw, mode);
6990         if (ret)
6991                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
6992                          mode, ret);
6993
6994         return ret;
6995 }
6996
6997 static int
6998 hns3_query_dev_fec_info(struct hns3_hw *hw)
6999 {
7000         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7001         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7002         int ret;
7003
7004         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7005         if (ret)
7006                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7007
7008         return ret;
7009 }
7010
7011 static bool
7012 hns3_optical_module_existed(struct hns3_hw *hw)
7013 {
7014         struct hns3_cmd_desc desc;
7015         bool existed;
7016         int ret;
7017
7018         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7019         ret = hns3_cmd_send(hw, &desc, 1);
7020         if (ret) {
7021                 hns3_err(hw,
7022                          "fail to get optical module exist state, ret = %d.\n",
7023                          ret);
7024                 return false;
7025         }
7026         existed = !!desc.data[0];
7027
7028         return existed;
7029 }
7030
7031 static int
7032 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7033                                 uint32_t len, uint8_t *data)
7034 {
7035 #define HNS3_SFP_INFO_CMD_NUM 6
7036 #define HNS3_SFP_INFO_MAX_LEN \
7037         (HNS3_SFP_INFO_BD0_LEN + \
7038         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7039         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7040         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7041         uint16_t read_len;
7042         uint16_t copy_len;
7043         int ret;
7044         int i;
7045
7046         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7047                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7048                                           true);
7049                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7050                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7051         }
7052
7053         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7054         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7055         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7056         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7057
7058         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7059         if (ret) {
7060                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7061                                 ret);
7062                 return ret;
7063         }
7064
7065         /* The data format in BD0 is different with the others. */
7066         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7067         memcpy(data, sfp_info_bd0->data, copy_len);
7068         read_len = copy_len;
7069
7070         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7071                 if (read_len >= len)
7072                         break;
7073
7074                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7075                 memcpy(data + read_len, desc[i].data, copy_len);
7076                 read_len += copy_len;
7077         }
7078
7079         return (int)read_len;
7080 }
7081
7082 static int
7083 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7084                        struct rte_dev_eeprom_info *info)
7085 {
7086         struct hns3_adapter *hns = dev->data->dev_private;
7087         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7088         uint32_t offset = info->offset;
7089         uint32_t len = info->length;
7090         uint8_t *data = info->data;
7091         uint32_t read_len = 0;
7092
7093         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7094                 return -ENOTSUP;
7095
7096         if (!hns3_optical_module_existed(hw)) {
7097                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7098                 return -EIO;
7099         }
7100
7101         while (read_len < len) {
7102                 int ret;
7103                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7104                                                   len - read_len,
7105                                                   data + read_len);
7106                 if (ret < 0)
7107                         return -EIO;
7108                 read_len += ret;
7109         }
7110
7111         return 0;
7112 }
7113
7114 static int
7115 hns3_get_module_info(struct rte_eth_dev *dev,
7116                      struct rte_eth_dev_module_info *modinfo)
7117 {
7118 #define HNS3_SFF8024_ID_SFP             0x03
7119 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7120 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7121 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7122 #define HNS3_SFF_8636_V1_3              0x03
7123         struct hns3_adapter *hns = dev->data->dev_private;
7124         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7125         struct rte_dev_eeprom_info info;
7126         struct hns3_sfp_type sfp_type;
7127         int ret;
7128
7129         memset(&sfp_type, 0, sizeof(sfp_type));
7130         memset(&info, 0, sizeof(info));
7131         info.data = (uint8_t *)&sfp_type;
7132         info.length = sizeof(sfp_type);
7133         ret = hns3_get_module_eeprom(dev, &info);
7134         if (ret)
7135                 return ret;
7136
7137         switch (sfp_type.type) {
7138         case HNS3_SFF8024_ID_SFP:
7139                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7140                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7141                 break;
7142         case HNS3_SFF8024_ID_QSFP_8438:
7143                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7144                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7145                 break;
7146         case HNS3_SFF8024_ID_QSFP_8436_8636:
7147                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7148                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7149                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7150                 } else {
7151                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7152                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7153                 }
7154                 break;
7155         case HNS3_SFF8024_ID_QSFP28_8636:
7156                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7157                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7158                 break;
7159         default:
7160                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7161                          sfp_type.type, sfp_type.ext_type);
7162                 return -EINVAL;
7163         }
7164
7165         return 0;
7166 }
7167
7168 static int
7169 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7170 {
7171         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7172
7173         RTE_SET_USED(key);
7174
7175         if (strcmp(value, "vec") == 0)
7176                 hint = HNS3_IO_FUNC_HINT_VEC;
7177         else if (strcmp(value, "sve") == 0)
7178                 hint = HNS3_IO_FUNC_HINT_SVE;
7179         else if (strcmp(value, "simple") == 0)
7180                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7181         else if (strcmp(value, "common") == 0)
7182                 hint = HNS3_IO_FUNC_HINT_COMMON;
7183
7184         /* If the hint is valid then update output parameters */
7185         if (hint != HNS3_IO_FUNC_HINT_NONE)
7186                 *(uint32_t *)extra_args = hint;
7187
7188         return 0;
7189 }
7190
7191 static const char *
7192 hns3_get_io_hint_func_name(uint32_t hint)
7193 {
7194         switch (hint) {
7195         case HNS3_IO_FUNC_HINT_VEC:
7196                 return "vec";
7197         case HNS3_IO_FUNC_HINT_SVE:
7198                 return "sve";
7199         case HNS3_IO_FUNC_HINT_SIMPLE:
7200                 return "simple";
7201         case HNS3_IO_FUNC_HINT_COMMON:
7202                 return "common";
7203         default:
7204                 return "none";
7205         }
7206 }
7207
7208 static int
7209 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7210 {
7211         uint64_t val;
7212
7213         RTE_SET_USED(key);
7214
7215         val = strtoull(value, NULL, 16);
7216         *(uint64_t *)extra_args = val;
7217
7218         return 0;
7219 }
7220
7221 void
7222 hns3_parse_devargs(struct rte_eth_dev *dev)
7223 {
7224         struct hns3_adapter *hns = dev->data->dev_private;
7225         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7226         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7227         struct hns3_hw *hw = &hns->hw;
7228         uint64_t dev_caps_mask = 0;
7229         struct rte_kvargs *kvlist;
7230
7231         if (dev->device->devargs == NULL)
7232                 return;
7233
7234         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7235         if (!kvlist)
7236                 return;
7237
7238         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7239                            &hns3_parse_io_hint_func, &rx_func_hint);
7240         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7241                            &hns3_parse_io_hint_func, &tx_func_hint);
7242         rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7243                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7244         rte_kvargs_free(kvlist);
7245
7246         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7247                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7248                           hns3_get_io_hint_func_name(rx_func_hint));
7249         hns->rx_func_hint = rx_func_hint;
7250         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7251                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7252                           hns3_get_io_hint_func_name(tx_func_hint));
7253         hns->tx_func_hint = tx_func_hint;
7254
7255         if (dev_caps_mask != 0)
7256                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7257                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7258         hns->dev_caps_mask = dev_caps_mask;
7259 }
7260
7261 static const struct eth_dev_ops hns3_eth_dev_ops = {
7262         .dev_configure      = hns3_dev_configure,
7263         .dev_start          = hns3_dev_start,
7264         .dev_stop           = hns3_dev_stop,
7265         .dev_close          = hns3_dev_close,
7266         .promiscuous_enable = hns3_dev_promiscuous_enable,
7267         .promiscuous_disable = hns3_dev_promiscuous_disable,
7268         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7269         .allmulticast_disable = hns3_dev_allmulticast_disable,
7270         .mtu_set            = hns3_dev_mtu_set,
7271         .stats_get          = hns3_stats_get,
7272         .stats_reset        = hns3_stats_reset,
7273         .xstats_get         = hns3_dev_xstats_get,
7274         .xstats_get_names   = hns3_dev_xstats_get_names,
7275         .xstats_reset       = hns3_dev_xstats_reset,
7276         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7277         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7278         .dev_infos_get          = hns3_dev_infos_get,
7279         .fw_version_get         = hns3_fw_version_get,
7280         .rx_queue_setup         = hns3_rx_queue_setup,
7281         .tx_queue_setup         = hns3_tx_queue_setup,
7282         .rx_queue_release       = hns3_dev_rx_queue_release,
7283         .tx_queue_release       = hns3_dev_tx_queue_release,
7284         .rx_queue_start         = hns3_dev_rx_queue_start,
7285         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7286         .tx_queue_start         = hns3_dev_tx_queue_start,
7287         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7288         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7289         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7290         .rxq_info_get           = hns3_rxq_info_get,
7291         .txq_info_get           = hns3_txq_info_get,
7292         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7293         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7294         .flow_ctrl_get          = hns3_flow_ctrl_get,
7295         .flow_ctrl_set          = hns3_flow_ctrl_set,
7296         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7297         .mac_addr_add           = hns3_add_mac_addr,
7298         .mac_addr_remove        = hns3_remove_mac_addr,
7299         .mac_addr_set           = hns3_set_default_mac_addr,
7300         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7301         .link_update            = hns3_dev_link_update,
7302         .rss_hash_update        = hns3_dev_rss_hash_update,
7303         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7304         .reta_update            = hns3_dev_rss_reta_update,
7305         .reta_query             = hns3_dev_rss_reta_query,
7306         .flow_ops_get           = hns3_dev_flow_ops_get,
7307         .vlan_filter_set        = hns3_vlan_filter_set,
7308         .vlan_tpid_set          = hns3_vlan_tpid_set,
7309         .vlan_offload_set       = hns3_vlan_offload_set,
7310         .vlan_pvid_set          = hns3_vlan_pvid_set,
7311         .get_reg                = hns3_get_regs,
7312         .get_module_info        = hns3_get_module_info,
7313         .get_module_eeprom      = hns3_get_module_eeprom,
7314         .get_dcb_info           = hns3_get_dcb_info,
7315         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7316         .fec_get_capability     = hns3_fec_get_capability,
7317         .fec_get                = hns3_fec_get,
7318         .fec_set                = hns3_fec_set,
7319         .tm_ops_get             = hns3_tm_ops_get,
7320         .tx_done_cleanup        = hns3_tx_done_cleanup,
7321         .timesync_enable            = hns3_timesync_enable,
7322         .timesync_disable           = hns3_timesync_disable,
7323         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7324         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7325         .timesync_adjust_time       = hns3_timesync_adjust_time,
7326         .timesync_read_time         = hns3_timesync_read_time,
7327         .timesync_write_time        = hns3_timesync_write_time,
7328 };
7329
7330 static const struct hns3_reset_ops hns3_reset_ops = {
7331         .reset_service       = hns3_reset_service,
7332         .stop_service        = hns3_stop_service,
7333         .prepare_reset       = hns3_prepare_reset,
7334         .wait_hardware_ready = hns3_wait_hardware_ready,
7335         .reinit_dev          = hns3_reinit_dev,
7336         .restore_conf        = hns3_restore_conf,
7337         .start_service       = hns3_start_service,
7338 };
7339
7340 static int
7341 hns3_dev_init(struct rte_eth_dev *eth_dev)
7342 {
7343         struct hns3_adapter *hns = eth_dev->data->dev_private;
7344         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7345         struct rte_ether_addr *eth_addr;
7346         struct hns3_hw *hw = &hns->hw;
7347         int ret;
7348
7349         PMD_INIT_FUNC_TRACE();
7350
7351         eth_dev->process_private = (struct hns3_process_private *)
7352             rte_zmalloc_socket("hns3_filter_list",
7353                                sizeof(struct hns3_process_private),
7354                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7355         if (eth_dev->process_private == NULL) {
7356                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7357                 return -ENOMEM;
7358         }
7359
7360         hns3_flow_init(eth_dev);
7361
7362         hns3_set_rxtx_function(eth_dev);
7363         eth_dev->dev_ops = &hns3_eth_dev_ops;
7364         eth_dev->rx_queue_count = hns3_rx_queue_count;
7365         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7366                 ret = hns3_mp_init_secondary();
7367                 if (ret) {
7368                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7369                                      "process, ret = %d", ret);
7370                         goto err_mp_init_secondary;
7371                 }
7372
7373                 hw->secondary_cnt++;
7374                 return 0;
7375         }
7376
7377         ret = hns3_mp_init_primary();
7378         if (ret) {
7379                 PMD_INIT_LOG(ERR,
7380                              "Failed to init for primary process, ret = %d",
7381                              ret);
7382                 goto err_mp_init_primary;
7383         }
7384
7385         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7386         hns->is_vf = false;
7387         hw->data = eth_dev->data;
7388         hns3_parse_devargs(eth_dev);
7389
7390         /*
7391          * Set default max packet size according to the mtu
7392          * default vale in DPDK frame.
7393          */
7394         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7395
7396         ret = hns3_reset_init(hw);
7397         if (ret)
7398                 goto err_init_reset;
7399         hw->reset.ops = &hns3_reset_ops;
7400
7401         ret = hns3_init_pf(eth_dev);
7402         if (ret) {
7403                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7404                 goto err_init_pf;
7405         }
7406
7407         /* Allocate memory for storing MAC addresses */
7408         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7409                                                sizeof(struct rte_ether_addr) *
7410                                                HNS3_UC_MACADDR_NUM, 0);
7411         if (eth_dev->data->mac_addrs == NULL) {
7412                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7413                              "to store MAC addresses",
7414                              sizeof(struct rte_ether_addr) *
7415                              HNS3_UC_MACADDR_NUM);
7416                 ret = -ENOMEM;
7417                 goto err_rte_zmalloc;
7418         }
7419
7420         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7421         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7422                 rte_eth_random_addr(hw->mac.mac_addr);
7423                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7424                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7425                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7426                           "unicast address, using random MAC address %s",
7427                           mac_str);
7428         }
7429         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7430                             &eth_dev->data->mac_addrs[0]);
7431
7432         hw->adapter_state = HNS3_NIC_INITIALIZED;
7433
7434         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7435                             SCHEDULE_PENDING) {
7436                 hns3_err(hw, "Reschedule reset service after dev_init");
7437                 hns3_schedule_reset(hns);
7438         } else {
7439                 /* IMP will wait ready flag before reset */
7440                 hns3_notify_reset_ready(hw, false);
7441         }
7442
7443         hns3_info(hw, "hns3 dev initialization successful!");
7444         return 0;
7445
7446 err_rte_zmalloc:
7447         hns3_uninit_pf(eth_dev);
7448
7449 err_init_pf:
7450         rte_free(hw->reset.wait_data);
7451
7452 err_init_reset:
7453         hns3_mp_uninit_primary();
7454
7455 err_mp_init_primary:
7456 err_mp_init_secondary:
7457         eth_dev->dev_ops = NULL;
7458         eth_dev->rx_pkt_burst = NULL;
7459         eth_dev->rx_descriptor_status = NULL;
7460         eth_dev->tx_pkt_burst = NULL;
7461         eth_dev->tx_pkt_prepare = NULL;
7462         eth_dev->tx_descriptor_status = NULL;
7463         rte_free(eth_dev->process_private);
7464         eth_dev->process_private = NULL;
7465         return ret;
7466 }
7467
7468 static int
7469 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7470 {
7471         struct hns3_adapter *hns = eth_dev->data->dev_private;
7472         struct hns3_hw *hw = &hns->hw;
7473
7474         PMD_INIT_FUNC_TRACE();
7475
7476         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7477                 rte_free(eth_dev->process_private);
7478                 eth_dev->process_private = NULL;
7479                 return 0;
7480         }
7481
7482         if (hw->adapter_state < HNS3_NIC_CLOSING)
7483                 hns3_dev_close(eth_dev);
7484
7485         hw->adapter_state = HNS3_NIC_REMOVED;
7486         return 0;
7487 }
7488
7489 static int
7490 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7491                    struct rte_pci_device *pci_dev)
7492 {
7493         return rte_eth_dev_pci_generic_probe(pci_dev,
7494                                              sizeof(struct hns3_adapter),
7495                                              hns3_dev_init);
7496 }
7497
7498 static int
7499 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7500 {
7501         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7502 }
7503
7504 static const struct rte_pci_id pci_id_hns3_map[] = {
7505         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7506         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7507         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7508         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7509         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7510         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7511         { .vendor_id = 0, }, /* sentinel */
7512 };
7513
7514 static struct rte_pci_driver rte_hns3_pmd = {
7515         .id_table = pci_id_hns3_map,
7516         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7517         .probe = eth_hns3_pci_probe,
7518         .remove = eth_hns3_pci_remove,
7519 };
7520
7521 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7522 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7523 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7524 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7525                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7526                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7527                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7528 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7529 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);