drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32
  33 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  34 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  35
  36 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  37 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  38 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  39 #define HNS3_INVLID_PVID                0xFFFF
  40
  41 #define HNS3_FILTER_TYPE_VF             0
  42 #define HNS3_FILTER_TYPE_PORT           1
  43 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  44 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  45 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  46 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  47 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  48 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  49                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  50 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  51                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  52
  53 /* Reset related Registers */
  54 #define HNS3_GLOBAL_RESET_BIT           0
  55 #define HNS3_CORE_RESET_BIT             1
  56 #define HNS3_IMP_RESET_BIT              2
  57 #define HNS3_FUN_RST_ING_B              0
  58
  59 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  60
  61 #define HNS3_RESET_WAIT_MS      100
  62 #define HNS3_RESET_WAIT_CNT     200
  63
  64 int hns3_logtype_init;
  65 int hns3_logtype_driver;
  66
  67 enum hns3_evt_cause {
  68         HNS3_VECTOR0_EVENT_RST,
  69         HNS3_VECTOR0_EVENT_MBX,
  70         HNS3_VECTOR0_EVENT_ERR,
  71         HNS3_VECTOR0_EVENT_OTHER,
  72 };
  73
  74 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  75                                                  uint64_t *levels);
  76 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  77 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  78                                     int on);
  79
  80 static void
  81 hns3_pf_disable_irq0(struct hns3_hw *hw)
  82 {
  83         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  84 }
  85
  86 static void
  87 hns3_pf_enable_irq0(struct hns3_hw *hw)
  88 {
  89         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  90 }
  91
  92 static enum hns3_evt_cause
  93 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  94 {
  95         struct hns3_hw *hw = &hns->hw;
  96         uint32_t vector0_int_stats;
  97         uint32_t cmdq_src_val;
  98         uint32_t val;
  99         enum hns3_evt_cause ret;
 100
 101         /* fetch the events from their corresponding regs */
 102         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 103         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 104
 105         /*
 106          * Assumption: If by any chance reset and mailbox events are reported
 107          * together then we will only process reset event and defer the
 108          * processing of the mailbox events. Since, we would have not cleared
 109          * RX CMDQ event this time we would receive again another interrupt
 110          * from H/W just for the mailbox.
 111          */
 112         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 113                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 114                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 115                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 116                 if (clearval) {
 117                         hw->reset.stats.imp_cnt++;
 118                         hns3_warn(hw, "IMP reset detected, clear reset status");
 119                 } else {
 120                         hns3_schedule_delayed_reset(hns);
 121                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 122                 }
 123
 124                 ret = HNS3_VECTOR0_EVENT_RST;
 125                 goto out;
 126         }
 127
 128         /* Global reset */
 129         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 130                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 131                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 132                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 133                 if (clearval) {
 134                         hw->reset.stats.global_cnt++;
 135                         hns3_warn(hw, "Global reset detected, clear reset status");
 136                 } else {
 137                         hns3_schedule_delayed_reset(hns);
 138                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 139                 }
 140
 141                 ret = HNS3_VECTOR0_EVENT_RST;
 142                 goto out;
 143         }
 144
 145         /* check for vector0 msix event source */
 146         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 147                 val = vector0_int_stats;
 148                 ret = HNS3_VECTOR0_EVENT_ERR;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 mailbox(=CMDQ RX) event source */
 153         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 154                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 155                 val = cmdq_src_val;
 156                 ret = HNS3_VECTOR0_EVENT_MBX;
 157                 goto out;
 158         }
 159
 160         if (clearval && (vector0_int_stats || cmdq_src_val))
 161                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 162                           vector0_int_stats, cmdq_src_val);
 163         val = vector0_int_stats;
 164         ret = HNS3_VECTOR0_EVENT_OTHER;
 165 out:
 166
 167         if (clearval)
 168                 *clearval = val;
 169         return ret;
 170 }
 171
 172 static void
 173 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 174 {
 175         if (event_type == HNS3_VECTOR0_EVENT_RST)
 176                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 177         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 178                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 179 }
 180
 181 static void
 182 hns3_clear_all_event_cause(struct hns3_hw *hw)
 183 {
 184         uint32_t vector0_int_stats;
 185         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 186
 187         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 188                 hns3_warn(hw, "Probe during IMP reset interrupt");
 189
 190         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 191                 hns3_warn(hw, "Probe during Global reset interrupt");
 192
 193         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 194                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 195                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 196                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 197         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 198 }
 199
 200 static void
 201 hns3_interrupt_handler(void *param)
 202 {
 203         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 204         struct hns3_adapter *hns = dev->data->dev_private;
 205         struct hns3_hw *hw = &hns->hw;
 206         enum hns3_evt_cause event_cause;
 207         uint32_t clearval = 0;
 208
 209         /* Disable interrupt */
 210         hns3_pf_disable_irq0(hw);
 211
 212         event_cause = hns3_check_event_cause(hns, &clearval);
 213
 214         /* vector 0 interrupt is shared with reset and mailbox source events. */
 215         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 216                 hns3_handle_msix_error(hns, &hw->reset.request);
 217                 hns3_schedule_reset(hns);
 218         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 219                 hns3_schedule_reset(hns);
 220         else
 221                 hns3_err(hw, "Received unknown event");
 222
 223         hns3_clear_event_cause(hw, event_cause, clearval);
 224         /* Enable interrupt if it is not cause by reset */
 225         hns3_pf_enable_irq0(hw);
 226 }
 227
 228 static int
 229 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 230 {
 231 #define HNS3_VLAN_OFFSET_160            160
 232         struct hns3_vlan_filter_pf_cfg_cmd *req;
 233         struct hns3_hw *hw = &hns->hw;
 234         uint8_t vlan_offset_byte_val;
 235         struct hns3_cmd_desc desc;
 236         uint8_t vlan_offset_byte;
 237         uint8_t vlan_offset_160;
 238         int ret;
 239
 240         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 241
 242         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 243         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 244         vlan_offset_byte_val = 1 << (vlan_id % 8);
 245
 246         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 247         req->vlan_offset = vlan_offset_160;
 248         req->vlan_cfg = on ? 0 : 1;
 249         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 250
 251         ret = hns3_cmd_send(hw, &desc, 1);
 252         if (ret)
 253                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 254                          vlan_id, ret);
 255
 256         return ret;
 257 }
 258
 259 static void
 260 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 261 {
 262         struct hns3_user_vlan_table *vlan_entry;
 263         struct hns3_pf *pf = &hns->pf;
 264
 265         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 266                 if (vlan_entry->vlan_id == vlan_id) {
 267                         if (vlan_entry->hd_tbl_status)
 268                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 269                         LIST_REMOVE(vlan_entry, next);
 270                         rte_free(vlan_entry);
 271                         break;
 272                 }
 273         }
 274 }
 275
 276 static void
 277 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 278                         bool writen_to_tbl)
 279 {
 280         struct hns3_user_vlan_table *vlan_entry;
 281         struct hns3_hw *hw = &hns->hw;
 282         struct hns3_pf *pf = &hns->pf;
 283
 284         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 285         if (vlan_entry == NULL) {
 286                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 287                 return;
 288         }
 289
 290         vlan_entry->hd_tbl_status = writen_to_tbl;
 291         vlan_entry->vlan_id = vlan_id;
 292
 293         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 294 }
 295
 296 static int
 297 hns3_restore_vlan_table(struct hns3_adapter *hns)
 298 {
 299         struct hns3_user_vlan_table *vlan_entry;
 300         struct hns3_pf *pf = &hns->pf;
 301         uint16_t vlan_id;
 302         int ret = 0;
 303
 304         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 305                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 306                                                1);
 307                 return ret;
 308         }
 309
 310         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 311                 if (vlan_entry->hd_tbl_status) {
 312                         vlan_id = vlan_entry->vlan_id;
 313                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 314                         if (ret)
 315                                 break;
 316                 }
 317         }
 318
 319         return ret;
 320 }
 321
 322 static int
 323 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 324 {
 325         struct hns3_pf *pf = &hns->pf;
 326         bool writen_to_tbl = false;
 327         int ret = 0;
 328
 329         /*
 330          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 331          * for normal packet, deleting vlan id 0 is not allowed.
 332          */
 333         if (on == 0 && vlan_id == 0)
 334                 return 0;
 335
 336         /*
 337          * When port base vlan enabled, we use port base vlan as the vlan
 338          * filter condition. In this case, we don't update vlan filter table
 339          * when user add new vlan or remove exist vlan, just update the
 340          * vlan list. The vlan id in vlan list will be writen in vlan filter
 341          * table until port base vlan disabled
 342          */
 343         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 344                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 345                 writen_to_tbl = true;
 346         }
 347
 348         if (ret == 0 && vlan_id) {
 349                 if (on)
 350                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 351                 else
 352                         hns3_rm_dev_vlan_table(hns, vlan_id);
 353         }
 354         return ret;
 355 }
 356
 357 static int
 358 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 359 {
 360         struct hns3_adapter *hns = dev->data->dev_private;
 361         struct hns3_hw *hw = &hns->hw;
 362         int ret;
 363
 364         rte_spinlock_lock(&hw->lock);
 365         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 366         rte_spinlock_unlock(&hw->lock);
 367         return ret;
 368 }
 369
 370 static int
 371 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 372                          uint16_t tpid)
 373 {
 374         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 375         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 376         struct hns3_hw *hw = &hns->hw;
 377         struct hns3_cmd_desc desc;
 378         int ret;
 379
 380         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 381              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 382                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 383                 return -EINVAL;
 384         }
 385
 386         if (tpid != RTE_ETHER_TYPE_VLAN) {
 387                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 388                 return -EINVAL;
 389         }
 390
 391         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 392         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 393
 394         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 395                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 396                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 397         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 398                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 399                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 400                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 401                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 402         }
 403
 404         ret = hns3_cmd_send(hw, &desc, 1);
 405         if (ret) {
 406                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 407                          ret);
 408                 return ret;
 409         }
 410
 411         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 412
 413         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 414         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 415         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 416
 417         ret = hns3_cmd_send(hw, &desc, 1);
 418         if (ret)
 419                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 420                          ret);
 421         return ret;
 422 }
 423
 424 static int
 425 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 426                    uint16_t tpid)
 427 {
 428         struct hns3_adapter *hns = dev->data->dev_private;
 429         struct hns3_hw *hw = &hns->hw;
 430         int ret;
 431
 432         rte_spinlock_lock(&hw->lock);
 433         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 434         rte_spinlock_unlock(&hw->lock);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 440                              struct hns3_rx_vtag_cfg *vcfg)
 441 {
 442         struct hns3_vport_vtag_rx_cfg_cmd *req;
 443         struct hns3_hw *hw = &hns->hw;
 444         struct hns3_cmd_desc desc;
 445         uint16_t vport_id;
 446         uint8_t bitmap;
 447         int ret;
 448
 449         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 450
 451         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 452         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 453                      vcfg->strip_tag1_en ? 1 : 0);
 454         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 455                      vcfg->strip_tag2_en ? 1 : 0);
 456         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 457                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 458         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 459                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 460
 461         /*
 462          * In current version VF is not supported when PF is driven by DPDK
 463          * driver, the PF-related vf_id is 0, just need to configure parameters
 464          * for vport_id 0.
 465          */
 466         vport_id = 0;
 467         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 468         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 469         req->vf_bitmap[req->vf_offset] = bitmap;
 470
 471         ret = hns3_cmd_send(hw, &desc, 1);
 472         if (ret)
 473                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 474         return ret;
 475 }
 476
 477 static void
 478 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 479                            struct hns3_rx_vtag_cfg *vcfg)
 480 {
 481         struct hns3_pf *pf = &hns->pf;
 482         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 483 }
 484
 485 static void
 486 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 487                            struct hns3_tx_vtag_cfg *vcfg)
 488 {
 489         struct hns3_pf *pf = &hns->pf;
 490         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 491 }
 492
 493 static int
 494 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 495 {
 496         struct hns3_rx_vtag_cfg rxvlan_cfg;
 497         struct hns3_pf *pf = &hns->pf;
 498         struct hns3_hw *hw = &hns->hw;
 499         int ret;
 500
 501         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 502                 rxvlan_cfg.strip_tag1_en = false;
 503                 rxvlan_cfg.strip_tag2_en = enable;
 504         } else {
 505                 rxvlan_cfg.strip_tag1_en = enable;
 506                 rxvlan_cfg.strip_tag2_en = true;
 507         }
 508
 509         rxvlan_cfg.vlan1_vlan_prionly = false;
 510         rxvlan_cfg.vlan2_vlan_prionly = false;
 511         rxvlan_cfg.rx_vlan_offload_en = enable;
 512
 513         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 514         if (ret) {
 515                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 516                 return ret;
 517         }
 518
 519         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 520
 521         return ret;
 522 }
 523
 524 static int
 525 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 526                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 527 {
 528         struct hns3_vlan_filter_ctrl_cmd *req;
 529         struct hns3_cmd_desc desc;
 530         int ret;
 531
 532         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 533
 534         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 535         req->vlan_type = vlan_type;
 536         req->vlan_fe = filter_en ? fe_type : 0;
 537         req->vf_id = vf_id;
 538
 539         ret = hns3_cmd_send(hw, &desc, 1);
 540         if (ret)
 541                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 542
 543         return ret;
 544 }
 545
 546 static int
 547 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 548 {
 549         struct hns3_hw *hw = &hns->hw;
 550         int ret;
 551
 552         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 553                                         HNS3_FILTER_FE_EGRESS, false, 0);
 554         if (ret) {
 555                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 556                 return ret;
 557         }
 558
 559         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 560                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 561         if (ret)
 562                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 563
 564         return ret;
 565 }
 566
 567 static int
 568 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 569 {
 570         struct hns3_adapter *hns = dev->data->dev_private;
 571         struct hns3_hw *hw = &hns->hw;
 572         struct rte_eth_rxmode *rxmode;
 573         unsigned int tmp_mask;
 574         bool enable;
 575         int ret = 0;
 576
 577         rte_spinlock_lock(&hw->lock);
 578         rxmode = &dev->data->dev_conf.rxmode;
 579         tmp_mask = (unsigned int)mask;
 580         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 581                 /* Enable or disable VLAN stripping */
 582                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 583                     true : false;
 584
 585                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 586                 if (ret) {
 587                         rte_spinlock_unlock(&hw->lock);
 588                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 589                         return ret;
 590                 }
 591         }
 592
 593         rte_spinlock_unlock(&hw->lock);
 594
 595         return ret;
 596 }
 597
 598 static int
 599 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 600                              struct hns3_tx_vtag_cfg *vcfg)
 601 {
 602         struct hns3_vport_vtag_tx_cfg_cmd *req;
 603         struct hns3_cmd_desc desc;
 604         struct hns3_hw *hw = &hns->hw;
 605         uint16_t vport_id;
 606         uint8_t bitmap;
 607         int ret;
 608
 609         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 610
 611         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 612         req->def_vlan_tag1 = vcfg->default_tag1;
 613         req->def_vlan_tag2 = vcfg->default_tag2;
 614         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 615                      vcfg->accept_tag1 ? 1 : 0);
 616         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 617                      vcfg->accept_untag1 ? 1 : 0);
 618         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 619                      vcfg->accept_tag2 ? 1 : 0);
 620         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 621                      vcfg->accept_untag2 ? 1 : 0);
 622         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 623                      vcfg->insert_tag1_en ? 1 : 0);
 624         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 625                      vcfg->insert_tag2_en ? 1 : 0);
 626         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 627
 628         /*
 629          * In current version VF is not supported when PF is driven by DPDK
 630          * driver, the PF-related vf_id is 0, just need to configure parameters
 631          * for vport_id 0.
 632          */
 633         vport_id = 0;
 634         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 635         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 636         req->vf_bitmap[req->vf_offset] = bitmap;
 637
 638         ret = hns3_cmd_send(hw, &desc, 1);
 639         if (ret)
 640                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 647                      uint16_t pvid)
 648 {
 649         struct hns3_hw *hw = &hns->hw;
 650         struct hns3_tx_vtag_cfg txvlan_cfg;
 651         int ret;
 652
 653         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 654                 txvlan_cfg.accept_tag1 = true;
 655                 txvlan_cfg.insert_tag1_en = false;
 656                 txvlan_cfg.default_tag1 = 0;
 657         } else {
 658                 txvlan_cfg.accept_tag1 = false;
 659                 txvlan_cfg.insert_tag1_en = true;
 660                 txvlan_cfg.default_tag1 = pvid;
 661         }
 662
 663         txvlan_cfg.accept_untag1 = true;
 664         txvlan_cfg.accept_tag2 = true;
 665         txvlan_cfg.accept_untag2 = true;
 666         txvlan_cfg.insert_tag2_en = false;
 667         txvlan_cfg.default_tag2 = 0;
 668
 669         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 670         if (ret) {
 671                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 672                          ret);
 673                 return ret;
 674         }
 675
 676         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 677         return ret;
 678 }
 679
 680 static void
 681 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 682 {
 683         struct hns3_pf *pf = &hns->pf;
 684
 685         pf->port_base_vlan_cfg.state = on ?
 686             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 687
 688         pf->port_base_vlan_cfg.pvid = pvid;
 689 }
 690
 691 static void
 692 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 693 {
 694         struct hns3_user_vlan_table *vlan_entry;
 695         struct hns3_pf *pf = &hns->pf;
 696
 697         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 698                 if (vlan_entry->hd_tbl_status)
 699                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 700
 701                 vlan_entry->hd_tbl_status = false;
 702         }
 703
 704         if (is_del_list) {
 705                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 706                 while (vlan_entry) {
 707                         LIST_REMOVE(vlan_entry, next);
 708                         rte_free(vlan_entry);
 709                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 710                 }
 711         }
 712 }
 713
 714 static void
 715 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 716 {
 717         struct hns3_user_vlan_table *vlan_entry;
 718         struct hns3_pf *pf = &hns->pf;
 719
 720         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 721                 if (!vlan_entry->hd_tbl_status)
 722                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 723
 724                 vlan_entry->hd_tbl_status = true;
 725         }
 726 }
 727
 728 static void
 729 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 730 {
 731         struct hns3_hw *hw = &hns->hw;
 732         struct hns3_pf *pf = &hns->pf;
 733         int ret;
 734
 735         hns3_rm_all_vlan_table(hns, true);
 736         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 737                 ret = hns3_set_port_vlan_filter(hns,
 738                                                 pf->port_base_vlan_cfg.pvid, 0);
 739                 if (ret) {
 740                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 741                                  ret);
 742                         return;
 743                 }
 744         }
 745 }
 746
 747 static int
 748 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 749                                 uint16_t port_base_vlan_state,
 750                                 uint16_t new_pvid, uint16_t old_pvid)
 751 {
 752         struct hns3_pf *pf = &hns->pf;
 753         struct hns3_hw *hw = &hns->hw;
 754         int ret = 0;
 755
 756         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 757                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 758                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 759                         if (ret) {
 760                                 hns3_err(hw,
 761                                          "Failed to clear clear old pvid filter, ret =%d",
 762                                          ret);
 763                                 return ret;
 764                         }
 765                 }
 766
 767                 hns3_rm_all_vlan_table(hns, false);
 768                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 769         }
 770
 771         if (new_pvid != 0) {
 772                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 773                 if (ret) {
 774                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 775                                  ret);
 776                         return ret;
 777                 }
 778         }
 779
 780         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 781                 hns3_add_all_vlan_table(hns);
 782
 783         return ret;
 784 }
 785
 786 static int
 787 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 788 {
 789         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 790         struct hns3_hw *hw = &hns->hw;
 791         bool rx_strip_en;
 792         int ret;
 793
 794         rx_strip_en = on ? true : false;
 795         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 796         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 797         rx_vlan_cfg.vlan1_vlan_prionly = false;
 798         rx_vlan_cfg.vlan2_vlan_prionly = false;
 799         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 800
 801         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 802         if (ret) {
 803                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 804                 return ret;
 805         }
 806
 807         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 808         return ret;
 809 }
 810
 811 static int
 812 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 813 {
 814         struct hns3_pf *pf = &hns->pf;
 815         struct hns3_hw *hw = &hns->hw;
 816         uint16_t port_base_vlan_state;
 817         uint16_t old_pvid;
 818         int ret;
 819
 820         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 821                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 822                         hns3_warn(hw, "Invalid operation! As current pvid set "
 823                                   "is %u, disable pvid %u is invalid",
 824                                   pf->port_base_vlan_cfg.pvid, pvid);
 825                 return 0;
 826         }
 827
 828         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 829                                     HNS3_PORT_BASE_VLAN_DISABLE;
 830         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 831         if (ret) {
 832                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 833                 return ret;
 834         }
 835
 836         ret = hns3_en_rx_strip_all(hns, on);
 837         if (ret) {
 838                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 839                 return ret;
 840         }
 841
 842         if (pvid == HNS3_INVLID_PVID)
 843                 goto out;
 844         old_pvid = pf->port_base_vlan_cfg.pvid;
 845         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 846                                               old_pvid);
 847         if (ret) {
 848                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 849                          ret);
 850                 return ret;
 851         }
 852
 853 out:
 854         hns3_store_port_base_vlan_info(hns, pvid, on);
 855         return ret;
 856 }
 857
 858 static int
 859 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 860 {
 861         struct hns3_adapter *hns = dev->data->dev_private;
 862         struct hns3_hw *hw = &hns->hw;
 863         int ret;
 864
 865         rte_spinlock_lock(&hw->lock);
 866         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 867         rte_spinlock_unlock(&hw->lock);
 868         return ret;
 869 }
 870
 871 static void
 872 init_port_base_vlan_info(struct hns3_hw *hw)
 873 {
 874         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 875         struct hns3_pf *pf = &hns->pf;
 876
 877         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 878         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 879 }
 880
 881 static int
 882 hns3_default_vlan_config(struct hns3_adapter *hns)
 883 {
 884         struct hns3_hw *hw = &hns->hw;
 885         int ret;
 886
 887         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 888         if (ret)
 889                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 890         return ret;
 891 }
 892
 893 static int
 894 hns3_init_vlan_config(struct hns3_adapter *hns)
 895 {
 896         struct hns3_hw *hw = &hns->hw;
 897         int ret;
 898
 899         /*
 900          * This function can be called in the initialization and reset process,
 901          * when in reset process, it means that hardware had been reseted
 902          * successfully and we need to restore the hardware configuration to
 903          * ensure that the hardware configuration remains unchanged before and
 904          * after reset.
 905          */
 906         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 907                 init_port_base_vlan_info(hw);
 908
 909         ret = hns3_enable_vlan_filter(hns, true);
 910         if (ret) {
 911                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 912                 return ret;
 913         }
 914
 915         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 916                                        RTE_ETHER_TYPE_VLAN);
 917         if (ret) {
 918                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 919                 return ret;
 920         }
 921
 922         /*
 923          * When in the reinit dev stage of the reset process, the following
 924          * vlan-related configurations may differ from those at initialization,
 925          * we will restore configurations to hardware in hns3_restore_vlan_table
 926          * and hns3_restore_vlan_conf later.
 927          */
 928         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 929                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 930                 if (ret) {
 931                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 932                         return ret;
 933                 }
 934
 935                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 936                 if (ret) {
 937                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 938                                  ret);
 939                         return ret;
 940                 }
 941         }
 942
 943         return hns3_default_vlan_config(hns);
 944 }
 945
 946 static int
 947 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 948 {
 949         struct hns3_pf *pf = &hns->pf;
 950         struct hns3_hw *hw = &hns->hw;
 951         int ret;
 952
 953         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 954         if (ret) {
 955                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 956                 return ret;
 957         }
 958
 959         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 960         if (ret)
 961                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 962
 963         return ret;
 964 }
 965
 966 static int
 967 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 968 {
 969         struct hns3_adapter *hns = dev->data->dev_private;
 970         struct rte_eth_dev_data *data = dev->data;
 971         struct rte_eth_txmode *txmode;
 972         struct hns3_hw *hw = &hns->hw;
 973         int ret;
 974
 975         txmode = &data->dev_conf.txmode;
 976         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 977                 hns3_warn(hw,
 978                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 979                           "configuration is not supported! Ignore these two "
 980                           "parameters: hw_vlan_reject_tagged(%d), "
 981                           "hw_vlan_reject_untagged(%d)",
 982                           txmode->hw_vlan_reject_tagged,
 983                           txmode->hw_vlan_reject_untagged);
 984
 985         /* Apply vlan offload setting */
 986         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 987         if (ret) {
 988                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 989                 return ret;
 990         }
 991
 992         /* Apply pvid setting */
 993         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
 994                                  txmode->hw_vlan_insert_pvid);
 995         if (ret)
 996                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
 997                          txmode->pvid, ret);
 998
 999         return ret;
1000 }
1001
1002 static int
1003 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1004                 unsigned int tso_mss_max)
1005 {
1006         struct hns3_cfg_tso_status_cmd *req;
1007         struct hns3_cmd_desc desc;
1008         uint16_t tso_mss;
1009
1010         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1011
1012         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1013
1014         tso_mss = 0;
1015         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1016                        tso_mss_min);
1017         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1018
1019         tso_mss = 0;
1020         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1021                        tso_mss_max);
1022         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1023
1024         return hns3_cmd_send(hw, &desc, 1);
1025 }
1026
1027 int
1028 hns3_config_gro(struct hns3_hw *hw, bool en)
1029 {
1030         struct hns3_cfg_gro_status_cmd *req;
1031         struct hns3_cmd_desc desc;
1032         int ret;
1033
1034         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1035         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1036
1037         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1038
1039         ret = hns3_cmd_send(hw, &desc, 1);
1040         if (ret)
1041                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1042
1043         return ret;
1044 }
1045
1046 static int
1047 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1048                    uint16_t *allocated_size, bool is_alloc)
1049 {
1050         struct hns3_umv_spc_alc_cmd *req;
1051         struct hns3_cmd_desc desc;
1052         int ret;
1053
1054         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1055         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1056         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1057         req->space_size = rte_cpu_to_le_32(space_size);
1058
1059         ret = hns3_cmd_send(hw, &desc, 1);
1060         if (ret) {
1061                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1062                              is_alloc ? "allocate" : "free", ret);
1063                 return ret;
1064         }
1065
1066         if (is_alloc && allocated_size)
1067                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1068
1069         return 0;
1070 }
1071
1072 static int
1073 hns3_init_umv_space(struct hns3_hw *hw)
1074 {
1075         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1076         struct hns3_pf *pf = &hns->pf;
1077         uint16_t allocated_size = 0;
1078         int ret;
1079
1080         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1081                                  true);
1082         if (ret)
1083                 return ret;
1084
1085         if (allocated_size < pf->wanted_umv_size)
1086                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1087                              pf->wanted_umv_size, allocated_size);
1088
1089         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1090                                                 pf->wanted_umv_size;
1091         pf->used_umv_size = 0;
1092         return 0;
1093 }
1094
1095 static int
1096 hns3_uninit_umv_space(struct hns3_hw *hw)
1097 {
1098         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1099         struct hns3_pf *pf = &hns->pf;
1100         int ret;
1101
1102         if (pf->max_umv_size == 0)
1103                 return 0;
1104
1105         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1106         if (ret)
1107                 return ret;
1108
1109         pf->max_umv_size = 0;
1110
1111         return 0;
1112 }
1113
1114 static bool
1115 hns3_is_umv_space_full(struct hns3_hw *hw)
1116 {
1117         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1118         struct hns3_pf *pf = &hns->pf;
1119         bool is_full;
1120
1121         is_full = (pf->used_umv_size >= pf->max_umv_size);
1122
1123         return is_full;
1124 }
1125
1126 static void
1127 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1128 {
1129         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1130         struct hns3_pf *pf = &hns->pf;
1131
1132         if (is_free) {
1133                 if (pf->used_umv_size > 0)
1134                         pf->used_umv_size--;
1135         } else
1136                 pf->used_umv_size++;
1137 }
1138
1139 static void
1140 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1141                       const uint8_t *addr, bool is_mc)
1142 {
1143         const unsigned char *mac_addr = addr;
1144         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1145                             ((uint32_t)mac_addr[2] << 16) |
1146                             ((uint32_t)mac_addr[1] << 8) |
1147                             (uint32_t)mac_addr[0];
1148         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1149
1150         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1151         if (is_mc) {
1152                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1153                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1154                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1155         }
1156
1157         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1158         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1159 }
1160
1161 static int
1162 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1163                              uint8_t resp_code,
1164                              enum hns3_mac_vlan_tbl_opcode op)
1165 {
1166         if (cmdq_resp) {
1167                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1168                          cmdq_resp);
1169                 return -EIO;
1170         }
1171
1172         if (op == HNS3_MAC_VLAN_ADD) {
1173                 if (resp_code == 0 || resp_code == 1) {
1174                         return 0;
1175                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1176                         hns3_err(hw, "add mac addr failed for uc_overflow");
1177                         return -ENOSPC;
1178                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1179                         hns3_err(hw, "add mac addr failed for mc_overflow");
1180                         return -ENOSPC;
1181                 }
1182
1183                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1184                          resp_code);
1185                 return -EIO;
1186         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1187                 if (resp_code == 0) {
1188                         return 0;
1189                 } else if (resp_code == 1) {
1190                         hns3_dbg(hw, "remove mac addr failed for miss");
1191                         return -ENOENT;
1192                 }
1193
1194                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1195                          resp_code);
1196                 return -EIO;
1197         } else if (op == HNS3_MAC_VLAN_LKUP) {
1198                 if (resp_code == 0) {
1199                         return 0;
1200                 } else if (resp_code == 1) {
1201                         hns3_dbg(hw, "lookup mac addr failed for miss");
1202                         return -ENOENT;
1203                 }
1204
1205                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1206                          resp_code);
1207                 return -EIO;
1208         }
1209
1210         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1211                  op);
1212
1213         return -EINVAL;
1214 }
1215
1216 static int
1217 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1218                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1219                          struct hns3_cmd_desc *desc, bool is_mc)
1220 {
1221         uint8_t resp_code;
1222         uint16_t retval;
1223         int ret;
1224
1225         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1226         if (is_mc) {
1227                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1228                 memcpy(desc[0].data, req,
1229                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1230                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1231                                           true);
1232                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1233                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1234                                           true);
1235                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1236         } else {
1237                 memcpy(desc[0].data, req,
1238                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239                 ret = hns3_cmd_send(hw, desc, 1);
1240         }
1241         if (ret) {
1242                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1243                          ret);
1244                 return ret;
1245         }
1246         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1247         retval = rte_le_to_cpu_16(desc[0].retval);
1248
1249         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1250                                             HNS3_MAC_VLAN_LKUP);
1251 }
1252
1253 static int
1254 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1255                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1256                       struct hns3_cmd_desc *mc_desc)
1257 {
1258         uint8_t resp_code;
1259         uint16_t retval;
1260         int cfg_status;
1261         int ret;
1262
1263         if (mc_desc == NULL) {
1264                 struct hns3_cmd_desc desc;
1265
1266                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1267                 memcpy(desc.data, req,
1268                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1269                 ret = hns3_cmd_send(hw, &desc, 1);
1270                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1271                 retval = rte_le_to_cpu_16(desc.retval);
1272
1273                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1274                                                           HNS3_MAC_VLAN_ADD);
1275         } else {
1276                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1277                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1278                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1279                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1280                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1281                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1282                 memcpy(mc_desc[0].data, req,
1283                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1284                 mc_desc[0].retval = 0;
1285                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1286                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1287                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1288
1289                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1290                                                           HNS3_MAC_VLAN_ADD);
1291         }
1292
1293         if (ret) {
1294                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1295                 return ret;
1296         }
1297
1298         return cfg_status;
1299 }
1300
1301 static int
1302 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1303                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1304 {
1305         struct hns3_cmd_desc desc;
1306         uint8_t resp_code;
1307         uint16_t retval;
1308         int ret;
1309
1310         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1311
1312         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1313
1314         ret = hns3_cmd_send(hw, &desc, 1);
1315         if (ret) {
1316                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1317                 return ret;
1318         }
1319         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1320         retval = rte_le_to_cpu_16(desc.retval);
1321
1322         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1323                                             HNS3_MAC_VLAN_REMOVE);
1324 }
1325
1326 static int
1327 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1328 {
1329         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1330         struct hns3_mac_vlan_tbl_entry_cmd req;
1331         struct hns3_pf *pf = &hns->pf;
1332         struct hns3_cmd_desc desc;
1333         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1334         uint16_t egress_port = 0;
1335         uint8_t vf_id;
1336         int ret;
1337
1338         /* check if mac addr is valid */
1339         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1340                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1341                                       mac_addr);
1342                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1343                          mac_str);
1344                 return -EINVAL;
1345         }
1346
1347         memset(&req, 0, sizeof(req));
1348
1349         /*
1350          * In current version VF is not supported when PF is driven by DPDK
1351          * driver, the PF-related vf_id is 0, just need to configure parameters
1352          * for vf_id 0.
1353          */
1354         vf_id = 0;
1355         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1356                        HNS3_MAC_EPORT_VFID_S, vf_id);
1357
1358         req.egress_port = rte_cpu_to_le_16(egress_port);
1359
1360         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1361
1362         /*
1363          * Lookup the mac address in the mac_vlan table, and add
1364          * it if the entry is inexistent. Repeated unicast entry
1365          * is not allowed in the mac vlan table.
1366          */
1367         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1368         if (ret == -ENOENT) {
1369                 if (!hns3_is_umv_space_full(hw)) {
1370                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1371                         if (!ret)
1372                                 hns3_update_umv_space(hw, false);
1373                         return ret;
1374                 }
1375
1376                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1377
1378                 return -ENOSPC;
1379         }
1380
1381         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1382
1383         /* check if we just hit the duplicate */
1384         if (ret == 0) {
1385                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1386                 return 0;
1387         }
1388
1389         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1390                  mac_str);
1391
1392         return ret;
1393 }
1394
1395 static int
1396 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1397                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1398 {
1399         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1400         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1401         int ret;
1402
1403         rte_spinlock_lock(&hw->lock);
1404         ret = hns3_add_uc_addr_common(hw, mac_addr);
1405         if (ret) {
1406                 rte_spinlock_unlock(&hw->lock);
1407                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1408                                       mac_addr);
1409                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1410                 return ret;
1411         }
1412
1413         if (idx == 0)
1414                 hw->mac.default_addr_setted = true;
1415         rte_spinlock_unlock(&hw->lock);
1416
1417         return ret;
1418 }
1419
1420 static int
1421 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1422 {
1423         struct hns3_mac_vlan_tbl_entry_cmd req;
1424         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1425         int ret;
1426
1427         /* check if mac addr is valid */
1428         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1429                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1430                                       mac_addr);
1431                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1432                          mac_str);
1433                 return -EINVAL;
1434         }
1435
1436         memset(&req, 0, sizeof(req));
1437         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1438         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1439         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1440         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1441                 return 0;
1442         else if (ret == 0)
1443                 hns3_update_umv_space(hw, true);
1444
1445         return ret;
1446 }
1447
1448 static void
1449 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1450 {
1451         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1452         /* index will be checked by upper level rte interface */
1453         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1454         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1455         int ret;
1456
1457         rte_spinlock_lock(&hw->lock);
1458         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1459         if (ret) {
1460                 rte_spinlock_unlock(&hw->lock);
1461                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1462                                       mac_addr);
1463                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1464                 return;
1465         }
1466
1467         if (idx == 0)
1468                 hw->mac.default_addr_setted = false;
1469         rte_spinlock_unlock(&hw->lock);
1470 }
1471
1472 static int
1473 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1474                           struct rte_ether_addr *mac_addr)
1475 {
1476         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         struct rte_ether_addr *oaddr;
1478         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1479         bool default_addr_setted;
1480         bool rm_succes = false;
1481         int ret, ret_val;
1482
1483         /* check if mac addr is valid */
1484         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1485                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1486                                       mac_addr);
1487                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1488                          mac_str);
1489                 return -EINVAL;
1490         }
1491
1492         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1493         default_addr_setted = hw->mac.default_addr_setted;
1494         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1495                 return 0;
1496
1497         rte_spinlock_lock(&hw->lock);
1498         if (default_addr_setted) {
1499                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1500                 if (ret) {
1501                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1502                                               oaddr);
1503                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1504                                   mac_str, ret);
1505                         rm_succes = false;
1506                 } else
1507                         rm_succes = true;
1508         }
1509
1510         ret = hns3_add_uc_addr_common(hw, mac_addr);
1511         if (ret) {
1512                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1513                                       mac_addr);
1514                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1515                 goto err_add_uc_addr;
1516         }
1517
1518         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1519         if (ret) {
1520                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1521                 goto err_pause_addr_cfg;
1522         }
1523
1524         rte_ether_addr_copy(mac_addr,
1525                             (struct rte_ether_addr *)hw->mac.mac_addr);
1526         hw->mac.default_addr_setted = true;
1527         rte_spinlock_unlock(&hw->lock);
1528
1529         return 0;
1530
1531 err_pause_addr_cfg:
1532         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1533         if (ret_val) {
1534                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1535                                       mac_addr);
1536                 hns3_warn(hw,
1537                           "Failed to roll back to del setted mac addr(%s): %d",
1538                           mac_str, ret_val);
1539         }
1540
1541 err_add_uc_addr:
1542         if (rm_succes) {
1543                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1544                 if (ret_val) {
1545                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1546                                               oaddr);
1547                         hns3_warn(hw,
1548                                   "Failed to restore old uc mac addr(%s): %d",
1549                                   mac_str, ret_val);
1550                         hw->mac.default_addr_setted = false;
1551                 }
1552         }
1553         rte_spinlock_unlock(&hw->lock);
1554
1555         return ret;
1556 }
1557
1558 static int
1559 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1560 {
1561         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1562         struct hns3_hw *hw = &hns->hw;
1563         struct rte_ether_addr *addr;
1564         int err = 0;
1565         int ret;
1566         int i;
1567
1568         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1569                 addr = &hw->data->mac_addrs[i];
1570                 if (!rte_is_valid_assigned_ether_addr(addr))
1571                         continue;
1572                 if (del)
1573                         ret = hns3_remove_uc_addr_common(hw, addr);
1574                 else
1575                         ret = hns3_add_uc_addr_common(hw, addr);
1576                 if (ret) {
1577                         err = ret;
1578                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1579                                               addr);
1580                         hns3_dbg(hw,
1581                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1582                                  del ? "remove" : "restore", mac_str, ret, i);
1583                 }
1584         }
1585         return err;
1586 }
1587
1588 static void
1589 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1590 {
1591 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1592         uint8_t word_num;
1593         uint8_t bit_num;
1594
1595         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1596                 word_num = vfid / 32;
1597                 bit_num = vfid % 32;
1598                 if (clr)
1599                         desc[1].data[word_num] &=
1600                             rte_cpu_to_le_32(~(1UL << bit_num));
1601                 else
1602                         desc[1].data[word_num] |=
1603                             rte_cpu_to_le_32(1UL << bit_num);
1604         } else {
1605                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1606                 bit_num = vfid % 32;
1607                 if (clr)
1608                         desc[2].data[word_num] &=
1609                             rte_cpu_to_le_32(~(1UL << bit_num));
1610                 else
1611                         desc[2].data[word_num] |=
1612                             rte_cpu_to_le_32(1UL << bit_num);
1613         }
1614 }
1615
1616 static int
1617 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1618 {
1619         struct hns3_mac_vlan_tbl_entry_cmd req;
1620         struct hns3_cmd_desc desc[3];
1621         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1622         uint8_t vf_id;
1623         int ret;
1624
1625         /* Check if mac addr is valid */
1626         if (!rte_is_multicast_ether_addr(mac_addr)) {
1627                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1628                                       mac_addr);
1629                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1630                          mac_str);
1631                 return -EINVAL;
1632         }
1633
1634         memset(&req, 0, sizeof(req));
1635         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1636         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1637         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1638         if (ret) {
1639                 /* This mac addr do not exist, add new entry for it */
1640                 memset(desc[0].data, 0, sizeof(desc[0].data));
1641                 memset(desc[1].data, 0, sizeof(desc[0].data));
1642                 memset(desc[2].data, 0, sizeof(desc[0].data));
1643         }
1644
1645         /*
1646          * In current version VF is not supported when PF is driven by DPDK
1647          * driver, the PF-related vf_id is 0, just need to configure parameters
1648          * for vf_id 0.
1649          */
1650         vf_id = 0;
1651         hns3_update_desc_vfid(desc, vf_id, false);
1652         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1653         if (ret) {
1654                 if (ret == -ENOSPC)
1655                         hns3_err(hw, "mc mac vlan table is full");
1656                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1657                                       mac_addr);
1658                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1659         }
1660
1661         return ret;
1662 }
1663
1664 static int
1665 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1666 {
1667         struct hns3_mac_vlan_tbl_entry_cmd req;
1668         struct hns3_cmd_desc desc[3];
1669         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1670         uint8_t vf_id;
1671         int ret;
1672
1673         /* Check if mac addr is valid */
1674         if (!rte_is_multicast_ether_addr(mac_addr)) {
1675                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1676                                       mac_addr);
1677                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1678                          mac_str);
1679                 return -EINVAL;
1680         }
1681
1682         memset(&req, 0, sizeof(req));
1683         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1684         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1685         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1686         if (ret == 0) {
1687                 /*
1688                  * This mac addr exist, remove this handle's VFID for it.
1689                  * In current version VF is not supported when PF is driven by
1690                  * DPDK driver, the PF-related vf_id is 0, just need to
1691                  * configure parameters for vf_id 0.
1692                  */
1693                 vf_id = 0;
1694                 hns3_update_desc_vfid(desc, vf_id, true);
1695
1696                 /* All the vfid is zero, so need to delete this entry */
1697                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1698         } else if (ret == -ENOENT) {
1699                 /* This mac addr doesn't exist. */
1700                 return 0;
1701         }
1702
1703         if (ret) {
1704                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1705                                       mac_addr);
1706                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1707         }
1708
1709         return ret;
1710 }
1711
1712 static int
1713 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1714                            struct rte_ether_addr *mc_addr_set,
1715                            uint32_t nb_mc_addr)
1716 {
1717         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1718         struct rte_ether_addr *addr;
1719         uint32_t i;
1720         uint32_t j;
1721
1722         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1723                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1724                          "invalid. valid range: 0~%d",
1725                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1726                 return -EINVAL;
1727         }
1728
1729         /* Check if input mac addresses are valid */
1730         for (i = 0; i < nb_mc_addr; i++) {
1731                 addr = &mc_addr_set[i];
1732                 if (!rte_is_multicast_ether_addr(addr)) {
1733                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1734                                               addr);
1735                         hns3_err(hw,
1736                                  "Failed to set mc mac addr, addr(%s) invalid.",
1737                                  mac_str);
1738                         return -EINVAL;
1739                 }
1740
1741                 /* Check if there are duplicate addresses */
1742                 for (j = i + 1; j < nb_mc_addr; j++) {
1743                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1744                                 rte_ether_format_addr(mac_str,
1745                                                       RTE_ETHER_ADDR_FMT_SIZE,
1746                                                       addr);
1747                                 hns3_err(hw, "Failed to set mc mac addr, "
1748                                          "addrs invalid. two same addrs(%s).",
1749                                          mac_str);
1750                                 return -EINVAL;
1751                         }
1752                 }
1753         }
1754
1755         return 0;
1756 }
1757
1758 static void
1759 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1760                            struct rte_ether_addr *mc_addr_set,
1761                            int mc_addr_num,
1762                            struct rte_ether_addr *reserved_addr_list,
1763                            int *reserved_addr_num,
1764                            struct rte_ether_addr *add_addr_list,
1765                            int *add_addr_num,
1766                            struct rte_ether_addr *rm_addr_list,
1767                            int *rm_addr_num)
1768 {
1769         struct rte_ether_addr *addr;
1770         int current_addr_num;
1771         int reserved_num = 0;
1772         int add_num = 0;
1773         int rm_num = 0;
1774         int num;
1775         int i;
1776         int j;
1777         bool same_addr;
1778
1779         /* Calculate the mc mac address list that should be removed */
1780         current_addr_num = hw->mc_addrs_num;
1781         for (i = 0; i < current_addr_num; i++) {
1782                 addr = &hw->mc_addrs[i];
1783                 same_addr = false;
1784                 for (j = 0; j < mc_addr_num; j++) {
1785                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1786                                 same_addr = true;
1787                                 break;
1788                         }
1789                 }
1790
1791                 if (!same_addr) {
1792                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1793                         rm_num++;
1794                 } else {
1795                         rte_ether_addr_copy(addr,
1796                                             &reserved_addr_list[reserved_num]);
1797                         reserved_num++;
1798                 }
1799         }
1800
1801         /* Calculate the mc mac address list that should be added */
1802         for (i = 0; i < mc_addr_num; i++) {
1803                 addr = &mc_addr_set[i];
1804                 same_addr = false;
1805                 for (j = 0; j < current_addr_num; j++) {
1806                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1807                                 same_addr = true;
1808                                 break;
1809                         }
1810                 }
1811
1812                 if (!same_addr) {
1813                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1814                         add_num++;
1815                 }
1816         }
1817
1818         /* Reorder the mc mac address list maintained by driver */
1819         for (i = 0; i < reserved_num; i++)
1820                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1821
1822         for (i = 0; i < rm_num; i++) {
1823                 num = reserved_num + i;
1824                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1825         }
1826
1827         *reserved_addr_num = reserved_num;
1828         *add_addr_num = add_num;
1829         *rm_addr_num = rm_num;
1830 }
1831
1832 static int
1833 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1834                           struct rte_ether_addr *mc_addr_set,
1835                           uint32_t nb_mc_addr)
1836 {
1837         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1838         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1839         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1840         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1841         struct rte_ether_addr *addr;
1842         int reserved_addr_num;
1843         int add_addr_num;
1844         int rm_addr_num;
1845         int mc_addr_num;
1846         int num;
1847         int ret;
1848         int i;
1849
1850         /* Check if input parameters are valid */
1851         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1852         if (ret)
1853                 return ret;
1854
1855         rte_spinlock_lock(&hw->lock);
1856
1857         /*
1858          * Calculate the mc mac address lists those should be removed and be
1859          * added, Reorder the mc mac address list maintained by driver.
1860          */
1861         mc_addr_num = (int)nb_mc_addr;
1862         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1863                                    reserved_addr_list, &reserved_addr_num,
1864                                    add_addr_list, &add_addr_num,
1865                                    rm_addr_list, &rm_addr_num);
1866
1867         /* Remove mc mac addresses */
1868         for (i = 0; i < rm_addr_num; i++) {
1869                 num = rm_addr_num - i - 1;
1870                 addr = &rm_addr_list[num];
1871                 ret = hns3_remove_mc_addr(hw, addr);
1872                 if (ret) {
1873                         rte_spinlock_unlock(&hw->lock);
1874                         return ret;
1875                 }
1876                 hw->mc_addrs_num--;
1877         }
1878
1879         /* Add mc mac addresses */
1880         for (i = 0; i < add_addr_num; i++) {
1881                 addr = &add_addr_list[i];
1882                 ret = hns3_add_mc_addr(hw, addr);
1883                 if (ret) {
1884                         rte_spinlock_unlock(&hw->lock);
1885                         return ret;
1886                 }
1887
1888                 num = reserved_addr_num + i;
1889                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1890                 hw->mc_addrs_num++;
1891         }
1892         rte_spinlock_unlock(&hw->lock);
1893
1894         return 0;
1895 }
1896
1897 static int
1898 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1899 {
1900         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1901         struct hns3_hw *hw = &hns->hw;
1902         struct rte_ether_addr *addr;
1903         int err = 0;
1904         int ret;
1905         int i;
1906
1907         for (i = 0; i < hw->mc_addrs_num; i++) {
1908                 addr = &hw->mc_addrs[i];
1909                 if (!rte_is_multicast_ether_addr(addr))
1910                         continue;
1911                 if (del)
1912                         ret = hns3_remove_mc_addr(hw, addr);
1913                 else
1914                         ret = hns3_add_mc_addr(hw, addr);
1915                 if (ret) {
1916                         err = ret;
1917                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1918                                               addr);
1919                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1920                                  del ? "Remove" : "Restore", mac_str);
1921                 }
1922         }
1923         return err;
1924 }
1925
1926 static int
1927 hns3_check_mq_mode(struct rte_eth_dev *dev)
1928 {
1929         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1930         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1931         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1934         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1935         uint8_t num_tc;
1936         int max_tc = 0;
1937         int i;
1938
1939         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1940         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1941
1942         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1943                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1944                          "rx_mq_mode = %d", rx_mq_mode);
1945                 return -EINVAL;
1946         }
1947
1948         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1949             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1950                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1951                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1952                          rx_mq_mode, tx_mq_mode);
1953                 return -EINVAL;
1954         }
1955
1956         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1957                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1958                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1959                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1960                         return -EINVAL;
1961                 }
1962
1963                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1964                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1965                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1966                                  "nb_tcs(%d) != %d or %d in rx direction.",
1967                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1968                         return -EINVAL;
1969                 }
1970
1971                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1972                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1973                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1974                         return -EINVAL;
1975                 }
1976
1977                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1978                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1979                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1980                                          "is not equal to one in tx direction.",
1981                                          i, dcb_rx_conf->dcb_tc[i]);
1982                                 return -EINVAL;
1983                         }
1984                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1985                                 max_tc = dcb_rx_conf->dcb_tc[i];
1986                 }
1987
1988                 num_tc = max_tc + 1;
1989                 if (num_tc > dcb_rx_conf->nb_tcs) {
1990                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1991                                  num_tc, dcb_rx_conf->nb_tcs);
1992                         return -EINVAL;
1993                 }
1994         }
1995
1996         return 0;
1997 }
1998
1999 static int
2000 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2001 {
2002         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003
2004         if (!hns3_dev_dcb_supported(hw)) {
2005                 hns3_err(hw, "this port does not support dcb configurations.");
2006                 return -EOPNOTSUPP;
2007         }
2008
2009         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2010                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2011                 return -EOPNOTSUPP;
2012         }
2013
2014         /* Check multiple queue mode */
2015         return hns3_check_mq_mode(dev);
2016 }
2017
2018 static int
2019 hns3_dev_configure(struct rte_eth_dev *dev)
2020 {
2021         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2023         struct rte_eth_conf *conf = &dev->data->dev_conf;
2024         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2025         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2026         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2027         struct rte_eth_rss_conf rss_conf;
2028         uint16_t mtu;
2029         int ret;
2030
2031         /*
2032          * Hardware does not support where the number of rx and tx queues is
2033          * not equal in hip08.
2034          */
2035         if (nb_rx_q != nb_tx_q) {
2036                 hns3_err(hw,
2037                          "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! "
2038                          "Hardware does not support this configuration!",
2039                          nb_rx_q, nb_tx_q);
2040                 return -EINVAL;
2041         }
2042
2043         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2044                 hns3_err(hw, "setting link speed/duplex not supported");
2045                 return -EINVAL;
2046         }
2047
2048         hw->adapter_state = HNS3_NIC_CONFIGURING;
2049         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2050                 ret = hns3_check_dcb_cfg(dev);
2051                 if (ret)
2052                         goto cfg_err;
2053         }
2054
2055         /* When RSS is not configured, redirect the packet queue 0 */
2056         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2057                 rss_conf = conf->rx_adv_conf.rss_conf;
2058                 if (rss_conf.rss_key == NULL) {
2059                         rss_conf.rss_key = rss_cfg->key;
2060                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2061                 }
2062
2063                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2064                 if (ret)
2065                         goto cfg_err;
2066         }
2067
2068         /*
2069          * If jumbo frames are enabled, MTU needs to be refreshed
2070          * according to the maximum RX packet length.
2071          */
2072         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2073                 /*
2074                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2075                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2076                  * can safely assign to "uint16_t" type variable.
2077                  */
2078                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2079                 ret = hns3_dev_mtu_set(dev, mtu);
2080                 if (ret)
2081                         goto cfg_err;
2082                 dev->data->mtu = mtu;
2083         }
2084
2085         ret = hns3_dev_configure_vlan(dev);
2086         if (ret)
2087                 goto cfg_err;
2088
2089         hw->adapter_state = HNS3_NIC_CONFIGURED;
2090
2091         return 0;
2092
2093 cfg_err:
2094         hw->adapter_state = HNS3_NIC_INITIALIZED;
2095         return ret;
2096 }
2097
2098 static int
2099 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2100 {
2101         struct hns3_config_max_frm_size_cmd *req;
2102         struct hns3_cmd_desc desc;
2103
2104         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2105
2106         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2107         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2108         req->min_frm_size = HNS3_MIN_FRAME_LEN;
2109
2110         return hns3_cmd_send(hw, &desc, 1);
2111 }
2112
2113 static int
2114 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2115 {
2116         int ret;
2117
2118         ret = hns3_set_mac_mtu(hw, mps);
2119         if (ret) {
2120                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2121                 return ret;
2122         }
2123
2124         ret = hns3_buffer_alloc(hw);
2125         if (ret) {
2126                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2127                 return ret;
2128         }
2129
2130         return 0;
2131 }
2132
2133 static int
2134 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2135 {
2136         struct hns3_adapter *hns = dev->data->dev_private;
2137         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2138         struct hns3_hw *hw = &hns->hw;
2139         bool is_jumbo_frame;
2140         int ret;
2141
2142         if (dev->data->dev_started) {
2143                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2144                          "before configuration", dev->data->port_id);
2145                 return -EBUSY;
2146         }
2147
2148         rte_spinlock_lock(&hw->lock);
2149         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2150         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2151
2152         /*
2153          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2154          * assign to "uint16_t" type variable.
2155          */
2156         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2157         if (ret) {
2158                 rte_spinlock_unlock(&hw->lock);
2159                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2160                          dev->data->port_id, mtu, ret);
2161                 return ret;
2162         }
2163         hns->pf.mps = (uint16_t)frame_size;
2164         if (is_jumbo_frame)
2165                 dev->data->dev_conf.rxmode.offloads |=
2166                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2167         else
2168                 dev->data->dev_conf.rxmode.offloads &=
2169                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2170         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2171         rte_spinlock_unlock(&hw->lock);
2172
2173         return 0;
2174 }
2175
2176 static int
2177 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2178 {
2179         struct hns3_adapter *hns = eth_dev->data->dev_private;
2180         struct hns3_hw *hw = &hns->hw;
2181
2182         info->max_rx_queues = hw->tqps_num;
2183         info->max_tx_queues = hw->tqps_num;
2184         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2185         info->min_rx_bufsize = hw->rx_buf_len;
2186         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2187         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2188         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2189                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2190                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2191                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2192                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2193                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2194                                  DEV_RX_OFFLOAD_KEEP_CRC |
2195                                  DEV_RX_OFFLOAD_SCATTER |
2196                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2197                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2198                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2199                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2200                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2201         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2202         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2203                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2204                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2205                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2206                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2207                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2208                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2209                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2210                                  info->tx_queue_offload_capa);
2211
2212         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2213                 .nb_max = HNS3_MAX_RING_DESC,
2214                 .nb_min = HNS3_MIN_RING_DESC,
2215                 .nb_align = HNS3_ALIGN_RING_DESC,
2216         };
2217
2218         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2219                 .nb_max = HNS3_MAX_RING_DESC,
2220                 .nb_min = HNS3_MIN_RING_DESC,
2221                 .nb_align = HNS3_ALIGN_RING_DESC,
2222         };
2223
2224         info->vmdq_queue_num = 0;
2225
2226         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2227         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2228         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2229
2230         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2231         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2232         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2233         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2234         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2235         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2236
2237         return 0;
2238 }
2239
2240 static int
2241 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2242                     size_t fw_size)
2243 {
2244         struct hns3_adapter *hns = eth_dev->data->dev_private;
2245         struct hns3_hw *hw = &hns->hw;
2246         int ret;
2247
2248         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2249         ret += 1; /* add the size of '\0' */
2250         if (fw_size < (uint32_t)ret)
2251                 return ret;
2252         else
2253                 return 0;
2254 }
2255
2256 static int
2257 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2258                      __rte_unused int wait_to_complete)
2259 {
2260         struct hns3_adapter *hns = eth_dev->data->dev_private;
2261         struct hns3_hw *hw = &hns->hw;
2262         struct hns3_mac *mac = &hw->mac;
2263         struct rte_eth_link new_link;
2264
2265         memset(&new_link, 0, sizeof(new_link));
2266         switch (mac->link_speed) {
2267         case ETH_SPEED_NUM_10M:
2268         case ETH_SPEED_NUM_100M:
2269         case ETH_SPEED_NUM_1G:
2270         case ETH_SPEED_NUM_10G:
2271         case ETH_SPEED_NUM_25G:
2272         case ETH_SPEED_NUM_40G:
2273         case ETH_SPEED_NUM_50G:
2274         case ETH_SPEED_NUM_100G:
2275                 new_link.link_speed = mac->link_speed;
2276                 break;
2277         default:
2278                 new_link.link_speed = ETH_SPEED_NUM_100M;
2279                 break;
2280         }
2281
2282         new_link.link_duplex = mac->link_duplex;
2283         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2284         new_link.link_autoneg =
2285             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2286
2287         return rte_eth_linkstatus_set(eth_dev, &new_link);
2288 }
2289
2290 static int
2291 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2292 {
2293         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2294         struct hns3_pf *pf = &hns->pf;
2295
2296         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2297                 return -EINVAL;
2298
2299         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2300
2301         return 0;
2302 }
2303
2304 static int
2305 hns3_query_function_status(struct hns3_hw *hw)
2306 {
2307 #define HNS3_QUERY_MAX_CNT              10
2308 #define HNS3_QUERY_SLEEP_MSCOEND        1
2309         struct hns3_func_status_cmd *req;
2310         struct hns3_cmd_desc desc;
2311         int timeout = 0;
2312         int ret;
2313
2314         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2315         req = (struct hns3_func_status_cmd *)desc.data;
2316
2317         do {
2318                 ret = hns3_cmd_send(hw, &desc, 1);
2319                 if (ret) {
2320                         PMD_INIT_LOG(ERR, "query function status failed %d",
2321                                      ret);
2322                         return ret;
2323                 }
2324
2325                 /* Check pf reset is done */
2326                 if (req->pf_state)
2327                         break;
2328
2329                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2330         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2331
2332         return hns3_parse_func_status(hw, req);
2333 }
2334
2335 static int
2336 hns3_query_pf_resource(struct hns3_hw *hw)
2337 {
2338         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2339         struct hns3_pf *pf = &hns->pf;
2340         struct hns3_pf_res_cmd *req;
2341         struct hns3_cmd_desc desc;
2342         int ret;
2343
2344         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2345         ret = hns3_cmd_send(hw, &desc, 1);
2346         if (ret) {
2347                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2348                 return ret;
2349         }
2350
2351         req = (struct hns3_pf_res_cmd *)desc.data;
2352         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2353         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2354         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2355
2356         if (req->tx_buf_size)
2357                 pf->tx_buf_size =
2358                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2359         else
2360                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2361
2362         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2363
2364         if (req->dv_buf_size)
2365                 pf->dv_buf_size =
2366                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2367         else
2368                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2369
2370         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2371
2372         hw->num_msi =
2373             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2374                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2375
2376         return 0;
2377 }
2378
2379 static void
2380 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2381 {
2382         struct hns3_cfg_param_cmd *req;
2383         uint64_t mac_addr_tmp_high;
2384         uint64_t mac_addr_tmp;
2385         uint32_t i;
2386
2387         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2388
2389         /* get the configuration */
2390         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2391                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2392         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2393                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2394         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2395                                            HNS3_CFG_TQP_DESC_N_M,
2396                                            HNS3_CFG_TQP_DESC_N_S);
2397
2398         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2399                                        HNS3_CFG_PHY_ADDR_M,
2400                                        HNS3_CFG_PHY_ADDR_S);
2401         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2402                                          HNS3_CFG_MEDIA_TP_M,
2403                                          HNS3_CFG_MEDIA_TP_S);
2404         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2405                                          HNS3_CFG_RX_BUF_LEN_M,
2406                                          HNS3_CFG_RX_BUF_LEN_S);
2407         /* get mac address */
2408         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2409         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2410                                            HNS3_CFG_MAC_ADDR_H_M,
2411                                            HNS3_CFG_MAC_ADDR_H_S);
2412
2413         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2414
2415         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2416                                             HNS3_CFG_DEFAULT_SPEED_M,
2417                                             HNS3_CFG_DEFAULT_SPEED_S);
2418         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2419                                            HNS3_CFG_RSS_SIZE_M,
2420                                            HNS3_CFG_RSS_SIZE_S);
2421
2422         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2423                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2424
2425         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2426         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2427
2428         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2429                                             HNS3_CFG_SPEED_ABILITY_M,
2430                                             HNS3_CFG_SPEED_ABILITY_S);
2431         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2432                                         HNS3_CFG_UMV_TBL_SPACE_M,
2433                                         HNS3_CFG_UMV_TBL_SPACE_S);
2434         if (!cfg->umv_space)
2435                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2436 }
2437
2438 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2439  * @hw: pointer to struct hns3_hw
2440  * @hcfg: the config structure to be getted
2441  */
2442 static int
2443 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2444 {
2445         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2446         struct hns3_cfg_param_cmd *req;
2447         uint32_t offset;
2448         uint32_t i;
2449         int ret;
2450
2451         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2452                 offset = 0;
2453                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2454                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2455                                           true);
2456                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2457                                i * HNS3_CFG_RD_LEN_BYTES);
2458                 /* Len should be divided by 4 when send to hardware */
2459                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2460                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2461                 req->offset = rte_cpu_to_le_32(offset);
2462         }
2463
2464         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2465         if (ret) {
2466                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2467                 return ret;
2468         }
2469
2470         hns3_parse_cfg(hcfg, desc);
2471
2472         return 0;
2473 }
2474
2475 static int
2476 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2477 {
2478         switch (speed_cmd) {
2479         case HNS3_CFG_SPEED_10M:
2480                 *speed = ETH_SPEED_NUM_10M;
2481                 break;
2482         case HNS3_CFG_SPEED_100M:
2483                 *speed = ETH_SPEED_NUM_100M;
2484                 break;
2485         case HNS3_CFG_SPEED_1G:
2486                 *speed = ETH_SPEED_NUM_1G;
2487                 break;
2488         case HNS3_CFG_SPEED_10G:
2489                 *speed = ETH_SPEED_NUM_10G;
2490                 break;
2491         case HNS3_CFG_SPEED_25G:
2492                 *speed = ETH_SPEED_NUM_25G;
2493                 break;
2494         case HNS3_CFG_SPEED_40G:
2495                 *speed = ETH_SPEED_NUM_40G;
2496                 break;
2497         case HNS3_CFG_SPEED_50G:
2498                 *speed = ETH_SPEED_NUM_50G;
2499                 break;
2500         case HNS3_CFG_SPEED_100G:
2501                 *speed = ETH_SPEED_NUM_100G;
2502                 break;
2503         default:
2504                 return -EINVAL;
2505         }
2506
2507         return 0;
2508 }
2509
2510 static int
2511 hns3_get_board_configuration(struct hns3_hw *hw)
2512 {
2513         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2514         struct hns3_pf *pf = &hns->pf;
2515         struct hns3_cfg cfg;
2516         int ret;
2517
2518         ret = hns3_get_board_cfg(hw, &cfg);
2519         if (ret) {
2520                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2521                 return ret;
2522         }
2523
2524         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2525                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2526                 return -EOPNOTSUPP;
2527         }
2528
2529         hw->mac.media_type = cfg.media_type;
2530         hw->rss_size_max = cfg.rss_size_max;
2531         hw->rx_buf_len = cfg.rx_buf_len;
2532         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2533         hw->mac.phy_addr = cfg.phy_addr;
2534         hw->mac.default_addr_setted = false;
2535         hw->num_tx_desc = cfg.tqp_desc_num;
2536         hw->num_rx_desc = cfg.tqp_desc_num;
2537         hw->dcb_info.num_pg = 1;
2538         hw->dcb_info.hw_pfc_map = 0;
2539
2540         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2541         if (ret) {
2542                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2543                              cfg.default_speed, ret);
2544                 return ret;
2545         }
2546
2547         pf->tc_max = cfg.tc_num;
2548         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2549                 PMD_INIT_LOG(WARNING,
2550                              "Get TC num(%u) from flash, set TC num to 1",
2551                              pf->tc_max);
2552                 pf->tc_max = 1;
2553         }
2554
2555         /* Dev does not support DCB */
2556         if (!hns3_dev_dcb_supported(hw)) {
2557                 pf->tc_max = 1;
2558                 pf->pfc_max = 0;
2559         } else
2560                 pf->pfc_max = pf->tc_max;
2561
2562         hw->dcb_info.num_tc = 1;
2563         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2564                                      hw->tqps_num / hw->dcb_info.num_tc);
2565         hns3_set_bit(hw->hw_tc_map, 0, 1);
2566         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2567
2568         pf->wanted_umv_size = cfg.umv_space;
2569
2570         return ret;
2571 }
2572
2573 static int
2574 hns3_get_configuration(struct hns3_hw *hw)
2575 {
2576         int ret;
2577
2578         ret = hns3_query_function_status(hw);
2579         if (ret) {
2580                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2581                 return ret;
2582         }
2583
2584         /* Get pf resource */
2585         ret = hns3_query_pf_resource(hw);
2586         if (ret) {
2587                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2588                 return ret;
2589         }
2590
2591         ret = hns3_get_board_configuration(hw);
2592         if (ret) {
2593                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2594                 return ret;
2595         }
2596
2597         return 0;
2598 }
2599
2600 static int
2601 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2602                       uint16_t tqp_vid, bool is_pf)
2603 {
2604         struct hns3_tqp_map_cmd *req;
2605         struct hns3_cmd_desc desc;
2606         int ret;
2607
2608         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2609
2610         req = (struct hns3_tqp_map_cmd *)desc.data;
2611         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2612         req->tqp_vf = func_id;
2613         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2614         if (!is_pf)
2615                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2616         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2617
2618         ret = hns3_cmd_send(hw, &desc, 1);
2619         if (ret)
2620                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2621
2622         return ret;
2623 }
2624
2625 static int
2626 hns3_map_tqp(struct hns3_hw *hw)
2627 {
2628         uint16_t tqps_num = hw->total_tqps_num;
2629         uint16_t func_id;
2630         uint16_t tqp_id;
2631         int num;
2632         int ret;
2633         int i;
2634
2635         /*
2636          * In current version VF is not supported when PF is driven by DPDK
2637          * driver, so we allocate tqps to PF as much as possible.
2638          */
2639         tqp_id = 0;
2640         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2641         for (func_id = 0; func_id < num; func_id++) {
2642                 for (i = 0;
2643                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2644                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2645                                                     true);
2646                         if (ret)
2647                                 return ret;
2648                 }
2649         }
2650
2651         return 0;
2652 }
2653
2654 static int
2655 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2656 {
2657         struct hns3_config_mac_speed_dup_cmd *req;
2658         struct hns3_cmd_desc desc;
2659         int ret;
2660
2661         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2662
2663         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2664
2665         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2666
2667         switch (speed) {
2668         case ETH_SPEED_NUM_10M:
2669                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2670                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2671                 break;
2672         case ETH_SPEED_NUM_100M:
2673                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2674                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2675                 break;
2676         case ETH_SPEED_NUM_1G:
2677                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2678                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2679                 break;
2680         case ETH_SPEED_NUM_10G:
2681                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2682                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2683                 break;
2684         case ETH_SPEED_NUM_25G:
2685                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2686                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2687                 break;
2688         case ETH_SPEED_NUM_40G:
2689                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2690                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2691                 break;
2692         case ETH_SPEED_NUM_50G:
2693                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2694                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2695                 break;
2696         case ETH_SPEED_NUM_100G:
2697                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2698                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2699                 break;
2700         default:
2701                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2702                 return -EINVAL;
2703         }
2704
2705         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2706
2707         ret = hns3_cmd_send(hw, &desc, 1);
2708         if (ret)
2709                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2710
2711         return ret;
2712 }
2713
2714 static int
2715 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2716 {
2717         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2718         struct hns3_pf *pf = &hns->pf;
2719         struct hns3_priv_buf *priv;
2720         uint32_t i, total_size;
2721
2722         total_size = pf->pkt_buf_size;
2723
2724         /* alloc tx buffer for all enabled tc */
2725         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2726                 priv = &buf_alloc->priv_buf[i];
2727
2728                 if (hw->hw_tc_map & BIT(i)) {
2729                         if (total_size < pf->tx_buf_size)
2730                                 return -ENOMEM;
2731
2732                         priv->tx_buf_size = pf->tx_buf_size;
2733                 } else
2734                         priv->tx_buf_size = 0;
2735
2736                 total_size -= priv->tx_buf_size;
2737         }
2738
2739         return 0;
2740 }
2741
2742 static int
2743 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2744 {
2745 /* TX buffer size is unit by 128 byte */
2746 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2747 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2748         struct hns3_tx_buff_alloc_cmd *req;
2749         struct hns3_cmd_desc desc;
2750         uint32_t buf_size;
2751         uint32_t i;
2752         int ret;
2753
2754         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2755
2756         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2757         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2758                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2759
2760                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2761                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2762                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2763         }
2764
2765         ret = hns3_cmd_send(hw, &desc, 1);
2766         if (ret)
2767                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2768
2769         return ret;
2770 }
2771
2772 static int
2773 hns3_get_tc_num(struct hns3_hw *hw)
2774 {
2775         int cnt = 0;
2776         uint8_t i;
2777
2778         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2779                 if (hw->hw_tc_map & BIT(i))
2780                         cnt++;
2781         return cnt;
2782 }
2783
2784 static uint32_t
2785 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2786 {
2787         struct hns3_priv_buf *priv;
2788         uint32_t rx_priv = 0;
2789         int i;
2790
2791         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2792                 priv = &buf_alloc->priv_buf[i];
2793                 if (priv->enable)
2794                         rx_priv += priv->buf_size;
2795         }
2796         return rx_priv;
2797 }
2798
2799 static uint32_t
2800 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2801 {
2802         uint32_t total_tx_size = 0;
2803         uint32_t i;
2804
2805         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2806                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2807
2808         return total_tx_size;
2809 }
2810
2811 /* Get the number of pfc enabled TCs, which have private buffer */
2812 static int
2813 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2814 {
2815         struct hns3_priv_buf *priv;
2816         int cnt = 0;
2817         uint8_t i;
2818
2819         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2820                 priv = &buf_alloc->priv_buf[i];
2821                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2822                         cnt++;
2823         }
2824
2825         return cnt;
2826 }
2827
2828 /* Get the number of pfc disabled TCs, which have private buffer */
2829 static int
2830 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2831                          struct hns3_pkt_buf_alloc *buf_alloc)
2832 {
2833         struct hns3_priv_buf *priv;
2834         int cnt = 0;
2835         uint8_t i;
2836
2837         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2838                 priv = &buf_alloc->priv_buf[i];
2839                 if (hw->hw_tc_map & BIT(i) &&
2840                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2841                         cnt++;
2842         }
2843
2844         return cnt;
2845 }
2846
2847 static bool
2848 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2849                   uint32_t rx_all)
2850 {
2851         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2852         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2853         struct hns3_pf *pf = &hns->pf;
2854         uint32_t shared_buf, aligned_mps;
2855         uint32_t rx_priv;
2856         uint8_t tc_num;
2857         uint8_t i;
2858
2859         tc_num = hns3_get_tc_num(hw);
2860         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2861
2862         if (hns3_dev_dcb_supported(hw))
2863                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2864                                         pf->dv_buf_size;
2865         else
2866                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2867                                         + pf->dv_buf_size;
2868
2869         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2870         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2871                              HNS3_BUF_SIZE_UNIT);
2872
2873         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2874         if (rx_all < rx_priv + shared_std)
2875                 return false;
2876
2877         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2878         buf_alloc->s_buf.buf_size = shared_buf;
2879         if (hns3_dev_dcb_supported(hw)) {
2880                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2881                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2882                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2883                                   HNS3_BUF_SIZE_UNIT);
2884         } else {
2885                 buf_alloc->s_buf.self.high =
2886                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2887                 buf_alloc->s_buf.self.low = aligned_mps;
2888         }
2889
2890         if (hns3_dev_dcb_supported(hw)) {
2891                 hi_thrd = shared_buf - pf->dv_buf_size;
2892
2893                 if (tc_num <= NEED_RESERVE_TC_NUM)
2894                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2895                                         / BUF_MAX_PERCENT;
2896
2897                 if (tc_num)
2898                         hi_thrd = hi_thrd / tc_num;
2899
2900                 hi_thrd = max_t(uint32_t, hi_thrd,
2901                                 HNS3_BUF_MUL_BY * aligned_mps);
2902                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2903                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2904         } else {
2905                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2906                 lo_thrd = aligned_mps;
2907         }
2908
2909         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2910                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2911                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2912         }
2913
2914         return true;
2915 }
2916
2917 static bool
2918 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2919                      struct hns3_pkt_buf_alloc *buf_alloc)
2920 {
2921         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2922         struct hns3_pf *pf = &hns->pf;
2923         struct hns3_priv_buf *priv;
2924         uint32_t aligned_mps;
2925         uint32_t rx_all;
2926         uint8_t i;
2927
2928         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2929         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2930
2931         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2932                 priv = &buf_alloc->priv_buf[i];
2933
2934                 priv->enable = 0;
2935                 priv->wl.low = 0;
2936                 priv->wl.high = 0;
2937                 priv->buf_size = 0;
2938
2939                 if (!(hw->hw_tc_map & BIT(i)))
2940                         continue;
2941
2942                 priv->enable = 1;
2943                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
2944                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
2945                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2946                                                 HNS3_BUF_SIZE_UNIT);
2947                 } else {
2948                         priv->wl.low = 0;
2949                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
2950                                         aligned_mps;
2951                 }
2952
2953                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
2954         }
2955
2956         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2957 }
2958
2959 static bool
2960 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
2961                              struct hns3_pkt_buf_alloc *buf_alloc)
2962 {
2963         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2964         struct hns3_pf *pf = &hns->pf;
2965         struct hns3_priv_buf *priv;
2966         int no_pfc_priv_num;
2967         uint32_t rx_all;
2968         uint8_t mask;
2969         int i;
2970
2971         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2972         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
2973
2974         /* let the last to be cleared first */
2975         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
2976                 priv = &buf_alloc->priv_buf[i];
2977                 mask = BIT((uint8_t)i);
2978
2979                 if (hw->hw_tc_map & mask &&
2980                     !(hw->dcb_info.hw_pfc_map & mask)) {
2981                         /* Clear the no pfc TC private buffer */
2982                         priv->wl.low = 0;
2983                         priv->wl.high = 0;
2984                         priv->buf_size = 0;
2985                         priv->enable = 0;
2986                         no_pfc_priv_num--;
2987                 }
2988
2989                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
2990                     no_pfc_priv_num == 0)
2991                         break;
2992         }
2993
2994         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2995 }
2996
2997 static bool
2998 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
2999                            struct hns3_pkt_buf_alloc *buf_alloc)
3000 {
3001         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3002         struct hns3_pf *pf = &hns->pf;
3003         struct hns3_priv_buf *priv;
3004         uint32_t rx_all;
3005         int pfc_priv_num;
3006         uint8_t mask;
3007         int i;
3008
3009         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3010         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3011
3012         /* let the last to be cleared first */
3013         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3014                 priv = &buf_alloc->priv_buf[i];
3015                 mask = BIT((uint8_t)i);
3016
3017                 if (hw->hw_tc_map & mask &&
3018                     hw->dcb_info.hw_pfc_map & mask) {
3019                         /* Reduce the number of pfc TC with private buffer */
3020                         priv->wl.low = 0;
3021                         priv->enable = 0;
3022                         priv->wl.high = 0;
3023                         priv->buf_size = 0;
3024                         pfc_priv_num--;
3025                 }
3026                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3027                     pfc_priv_num == 0)
3028                         break;
3029         }
3030
3031         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3032 }
3033
3034 static bool
3035 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3036                           struct hns3_pkt_buf_alloc *buf_alloc)
3037 {
3038 #define COMPENSATE_BUFFER       0x3C00
3039 #define COMPENSATE_HALF_MPS_NUM 5
3040 #define PRIV_WL_GAP             0x1800
3041         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3042         struct hns3_pf *pf = &hns->pf;
3043         uint32_t tc_num = hns3_get_tc_num(hw);
3044         uint32_t half_mps = pf->mps >> 1;
3045         struct hns3_priv_buf *priv;
3046         uint32_t min_rx_priv;
3047         uint32_t rx_priv;
3048         uint8_t i;
3049
3050         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3051         if (tc_num)
3052                 rx_priv = rx_priv / tc_num;
3053
3054         if (tc_num <= NEED_RESERVE_TC_NUM)
3055                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3056
3057         /*
3058          * Minimum value of private buffer in rx direction (min_rx_priv) is
3059          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3060          * buffer if rx_priv is greater than min_rx_priv.
3061          */
3062         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3063                         COMPENSATE_HALF_MPS_NUM * half_mps;
3064         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3065         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3066
3067         if (rx_priv < min_rx_priv)
3068                 return false;
3069
3070         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3071                 priv = &buf_alloc->priv_buf[i];
3072
3073                 priv->enable = 0;
3074                 priv->wl.low = 0;
3075                 priv->wl.high = 0;
3076                 priv->buf_size = 0;
3077
3078                 if (!(hw->hw_tc_map & BIT(i)))
3079                         continue;
3080
3081                 priv->enable = 1;
3082                 priv->buf_size = rx_priv;
3083                 priv->wl.high = rx_priv - pf->dv_buf_size;
3084                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3085         }
3086
3087         buf_alloc->s_buf.buf_size = 0;
3088
3089         return true;
3090 }
3091
3092 /*
3093  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3094  * @hw: pointer to struct hns3_hw
3095  * @buf_alloc: pointer to buffer calculation data
3096  * @return: 0: calculate sucessful, negative: fail
3097  */
3098 static int
3099 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3100 {
3101         /* When DCB is not supported, rx private buffer is not allocated. */
3102         if (!hns3_dev_dcb_supported(hw)) {
3103                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3104                 struct hns3_pf *pf = &hns->pf;
3105                 uint32_t rx_all = pf->pkt_buf_size;
3106
3107                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3108                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3109                         return -ENOMEM;
3110
3111                 return 0;
3112         }
3113
3114         /*
3115          * Try to allocate privated packet buffer for all TCs without share
3116          * buffer.
3117          */
3118         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3119                 return 0;
3120
3121         /*
3122          * Try to allocate privated packet buffer for all TCs with share
3123          * buffer.
3124          */
3125         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3126                 return 0;
3127
3128         /*
3129          * For different application scenes, the enabled port number, TC number
3130          * and no_drop TC number are different. In order to obtain the better
3131          * performance, software could allocate the buffer size and configure
3132          * the waterline by tring to decrease the private buffer size according
3133          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3134          * enabled tc.
3135          */
3136         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3137                 return 0;
3138
3139         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3140                 return 0;
3141
3142         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3143                 return 0;
3144
3145         return -ENOMEM;
3146 }
3147
3148 static int
3149 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3150 {
3151         struct hns3_rx_priv_buff_cmd *req;
3152         struct hns3_cmd_desc desc;
3153         uint32_t buf_size;
3154         int ret;
3155         int i;
3156
3157         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3158         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3159
3160         /* Alloc private buffer TCs */
3161         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3162                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3163
3164                 req->buf_num[i] =
3165                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3166                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3167         }
3168
3169         buf_size = buf_alloc->s_buf.buf_size;
3170         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3171                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3172
3173         ret = hns3_cmd_send(hw, &desc, 1);
3174         if (ret)
3175                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3176
3177         return ret;
3178 }
3179
3180 static int
3181 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3182 {
3183 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3184         struct hns3_rx_priv_wl_buf *req;
3185         struct hns3_priv_buf *priv;
3186         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3187         int i, j;
3188         int ret;
3189
3190         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3191                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3192                                           false);
3193                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3194
3195                 /* The first descriptor set the NEXT bit to 1 */
3196                 if (i == 0)
3197                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3198                 else
3199                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3200
3201                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3202                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3203
3204                         priv = &buf_alloc->priv_buf[idx];
3205                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3206                                                         HNS3_BUF_UNIT_S);
3207                         req->tc_wl[j].high |=
3208                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3209                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3210                                                         HNS3_BUF_UNIT_S);
3211                         req->tc_wl[j].low |=
3212                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3213                 }
3214         }
3215
3216         /* Send 2 descriptor at one time */
3217         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3218         if (ret)
3219                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3220                              ret);
3221         return ret;
3222 }
3223
3224 static int
3225 hns3_common_thrd_config(struct hns3_hw *hw,
3226                         struct hns3_pkt_buf_alloc *buf_alloc)
3227 {
3228 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3229         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3230         struct hns3_rx_com_thrd *req;
3231         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3232         struct hns3_tc_thrd *tc;
3233         int tc_idx;
3234         int i, j;
3235         int ret;
3236
3237         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3238                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3239                                           false);
3240                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3241
3242                 /* The first descriptor set the NEXT bit to 1 */
3243                 if (i == 0)
3244                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3245                 else
3246                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3247
3248                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3249                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3250                         tc = &s_buf->tc_thrd[tc_idx];
3251
3252                         req->com_thrd[j].high =
3253                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3254                         req->com_thrd[j].high |=
3255                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3256                         req->com_thrd[j].low =
3257                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3258                         req->com_thrd[j].low |=
3259                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3260                 }
3261         }
3262
3263         /* Send 2 descriptors at one time */
3264         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3265         if (ret)
3266                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3267
3268         return ret;
3269 }
3270
3271 static int
3272 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3273 {
3274         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3275         struct hns3_rx_com_wl *req;
3276         struct hns3_cmd_desc desc;
3277         int ret;
3278
3279         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3280
3281         req = (struct hns3_rx_com_wl *)desc.data;
3282         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3283         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3284
3285         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3286         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3287
3288         ret = hns3_cmd_send(hw, &desc, 1);
3289         if (ret)
3290                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3291
3292         return ret;
3293 }
3294
3295 int
3296 hns3_buffer_alloc(struct hns3_hw *hw)
3297 {
3298         struct hns3_pkt_buf_alloc pkt_buf;
3299         int ret;
3300
3301         memset(&pkt_buf, 0, sizeof(pkt_buf));
3302         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3303         if (ret) {
3304                 PMD_INIT_LOG(ERR,
3305                              "could not calc tx buffer size for all TCs %d",
3306                              ret);
3307                 return ret;
3308         }
3309
3310         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3311         if (ret) {
3312                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3313                 return ret;
3314         }
3315
3316         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3317         if (ret) {
3318                 PMD_INIT_LOG(ERR,
3319                              "could not calc rx priv buffer size for all TCs %d",
3320                              ret);
3321                 return ret;
3322         }
3323
3324         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3325         if (ret) {
3326                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3327                 return ret;
3328         }
3329
3330         if (hns3_dev_dcb_supported(hw)) {
3331                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3332                 if (ret) {
3333                         PMD_INIT_LOG(ERR,
3334                                      "could not configure rx private waterline %d",
3335                                      ret);
3336                         return ret;
3337                 }
3338
3339                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3340                 if (ret) {
3341                         PMD_INIT_LOG(ERR,
3342                                      "could not configure common threshold %d",
3343                                      ret);
3344                         return ret;
3345                 }
3346         }
3347
3348         ret = hns3_common_wl_config(hw, &pkt_buf);
3349         if (ret)
3350                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3351                              ret);
3352
3353         return ret;
3354 }
3355
3356 static int
3357 hns3_mac_init(struct hns3_hw *hw)
3358 {
3359         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3360         struct hns3_mac *mac = &hw->mac;
3361         struct hns3_pf *pf = &hns->pf;
3362         int ret;
3363
3364         pf->support_sfp_query = true;
3365         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3366         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3367         if (ret) {
3368                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3369                 return ret;
3370         }
3371
3372         mac->link_status = ETH_LINK_DOWN;
3373
3374         return hns3_config_mtu(hw, pf->mps);
3375 }
3376
3377 static int
3378 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3379 {
3380 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3381 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3382 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3383 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3384         int return_status;
3385
3386         if (cmdq_resp) {
3387                 PMD_INIT_LOG(ERR,
3388                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3389                              cmdq_resp);
3390                 return -EIO;
3391         }
3392
3393         switch (resp_code) {
3394         case HNS3_ETHERTYPE_SUCCESS_ADD:
3395         case HNS3_ETHERTYPE_ALREADY_ADD:
3396                 return_status = 0;
3397                 break;
3398         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3399                 PMD_INIT_LOG(ERR,
3400                              "add mac ethertype failed for manager table overflow.");
3401                 return_status = -EIO;
3402                 break;
3403         case HNS3_ETHERTYPE_KEY_CONFLICT:
3404                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3405                 return_status = -EIO;
3406                 break;
3407         default:
3408                 PMD_INIT_LOG(ERR,
3409                              "add mac ethertype failed for undefined, code=%d.",
3410                              resp_code);
3411                 return_status = -EIO;
3412         }
3413
3414         return return_status;
3415 }
3416
3417 static int
3418 hns3_add_mgr_tbl(struct hns3_hw *hw,
3419                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3420 {
3421         struct hns3_cmd_desc desc;
3422         uint8_t resp_code;
3423         uint16_t retval;
3424         int ret;
3425
3426         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3427         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3428
3429         ret = hns3_cmd_send(hw, &desc, 1);
3430         if (ret) {
3431                 PMD_INIT_LOG(ERR,
3432                              "add mac ethertype failed for cmd_send, ret =%d.",
3433                              ret);
3434                 return ret;
3435         }
3436
3437         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3438         retval = rte_le_to_cpu_16(desc.retval);
3439
3440         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3441 }
3442
3443 static void
3444 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3445                      int *table_item_num)
3446 {
3447         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3448
3449         /*
3450          * In current version, we add one item in management table as below:
3451          * 0x0180C200000E -- LLDP MC address
3452          */
3453         tbl = mgr_table;
3454         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3455         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3456         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3457         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3458         tbl->i_port_bitmap = 0x1;
3459         *table_item_num = 1;
3460 }
3461
3462 static int
3463 hns3_init_mgr_tbl(struct hns3_hw *hw)
3464 {
3465 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3466         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3467         int table_item_num;
3468         int ret;
3469         int i;
3470
3471         memset(mgr_table, 0, sizeof(mgr_table));
3472         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3473         for (i = 0; i < table_item_num; i++) {
3474                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3475                 if (ret) {
3476                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3477                                      ret);
3478                         return ret;
3479                 }
3480         }
3481
3482         return 0;
3483 }
3484
3485 static void
3486 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3487                         bool en_mc, bool en_bc, int vport_id)
3488 {
3489         if (!param)
3490                 return;
3491
3492         memset(param, 0, sizeof(struct hns3_promisc_param));
3493         if (en_uc)
3494                 param->enable = HNS3_PROMISC_EN_UC;
3495         if (en_mc)
3496                 param->enable |= HNS3_PROMISC_EN_MC;
3497         if (en_bc)
3498                 param->enable |= HNS3_PROMISC_EN_BC;
3499         param->vf_id = vport_id;
3500 }
3501
3502 static int
3503 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3504 {
3505         struct hns3_promisc_cfg_cmd *req;
3506         struct hns3_cmd_desc desc;
3507         int ret;
3508
3509         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3510
3511         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3512         req->vf_id = param->vf_id;
3513         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3514             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3515
3516         ret = hns3_cmd_send(hw, &desc, 1);
3517         if (ret)
3518                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3519
3520         return ret;
3521 }
3522
3523 static int
3524 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3525 {
3526         struct hns3_promisc_param param;
3527         bool en_bc_pmc = true;
3528         uint8_t vf_id;
3529         int ret;
3530
3531         /*
3532          * In current version VF is not supported when PF is driven by DPDK
3533          * driver, the PF-related vf_id is 0, just need to configure parameters
3534          * for vf_id 0.
3535          */
3536         vf_id = 0;
3537
3538         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3539         ret = hns3_cmd_set_promisc_mode(hw, &param);
3540         if (ret)
3541                 return ret;
3542
3543         return 0;
3544 }
3545
3546 static int
3547 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3548 {
3549         struct hns3_adapter *hns = dev->data->dev_private;
3550         struct hns3_hw *hw = &hns->hw;
3551         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3552         int ret = 0;
3553
3554         rte_spinlock_lock(&hw->lock);
3555         ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3556         rte_spinlock_unlock(&hw->lock);
3557         if (ret)
3558                 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3559
3560         return ret;
3561 }
3562
3563 static int
3564 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3565 {
3566         struct hns3_adapter *hns = dev->data->dev_private;
3567         struct hns3_hw *hw = &hns->hw;
3568         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3569         int ret = 0;
3570
3571         /* If now in all_multicast mode, must remain in all_multicast mode. */
3572         rte_spinlock_lock(&hw->lock);
3573         ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3574         rte_spinlock_unlock(&hw->lock);
3575         if (ret)
3576                 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3577
3578         return ret;
3579 }
3580
3581 static int
3582 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3583 {
3584         struct hns3_adapter *hns = dev->data->dev_private;
3585         struct hns3_hw *hw = &hns->hw;
3586         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3587         int ret = 0;
3588
3589         rte_spinlock_lock(&hw->lock);
3590         ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3591         rte_spinlock_unlock(&hw->lock);
3592         if (ret)
3593                 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3594
3595         return ret;
3596 }
3597
3598 static int
3599 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3600 {
3601         struct hns3_adapter *hns = dev->data->dev_private;
3602         struct hns3_hw *hw = &hns->hw;
3603         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3604         int ret = 0;
3605
3606         /* If now in promiscuous mode, must remain in all_multicast mode. */
3607         if (dev->data->promiscuous == 1)
3608                 return 0;
3609
3610         rte_spinlock_lock(&hw->lock);
3611         ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3612         rte_spinlock_unlock(&hw->lock);
3613         if (ret)
3614                 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3615
3616         return ret;
3617 }
3618
3619 static int
3620 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3621 {
3622         struct hns3_hw *hw = &hns->hw;
3623         bool en_mc_pmc;
3624         bool en_uc_pmc;
3625
3626         en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3627         en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3628
3629         return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3630 }
3631
3632 static int
3633 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3634 {
3635         struct hns3_sfp_speed_cmd *resp;
3636         struct hns3_cmd_desc desc;
3637         int ret;
3638
3639         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3640         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3641         ret = hns3_cmd_send(hw, &desc, 1);
3642         if (ret == -EOPNOTSUPP) {
3643                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3644                 return ret;
3645         } else if (ret) {
3646                 hns3_err(hw, "get sfp speed failed %d", ret);
3647                 return ret;
3648         }
3649
3650         *speed = resp->sfp_speed;
3651
3652         return 0;
3653 }
3654
3655 static uint8_t
3656 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3657 {
3658         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3659                 duplex = ETH_LINK_FULL_DUPLEX;
3660
3661         return duplex;
3662 }
3663
3664 static int
3665 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3666 {
3667         struct hns3_mac *mac = &hw->mac;
3668         int ret;
3669
3670         duplex = hns3_check_speed_dup(duplex, speed);
3671         if (mac->link_speed == speed && mac->link_duplex == duplex)
3672                 return 0;
3673
3674         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3675         if (ret)
3676                 return ret;
3677
3678         mac->link_speed = speed;
3679         mac->link_duplex = duplex;
3680
3681         return 0;
3682 }
3683
3684 static int
3685 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3686 {
3687         struct hns3_adapter *hns = eth_dev->data->dev_private;
3688         struct hns3_hw *hw = &hns->hw;
3689         struct hns3_pf *pf = &hns->pf;
3690         uint32_t speed;
3691         int ret;
3692
3693         /* If IMP do not support get SFP/qSFP speed, return directly */
3694         if (!pf->support_sfp_query)
3695                 return 0;
3696
3697         ret = hns3_get_sfp_speed(hw, &speed);
3698         if (ret == -EOPNOTSUPP) {
3699                 pf->support_sfp_query = false;
3700                 return ret;
3701         } else if (ret)
3702                 return ret;
3703
3704         if (speed == ETH_SPEED_NUM_NONE)
3705                 return 0; /* do nothing if no SFP */
3706
3707         /* Config full duplex for SFP */
3708         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3709 }
3710
3711 static int
3712 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3713 {
3714         struct hns3_config_mac_mode_cmd *req;
3715         struct hns3_cmd_desc desc;
3716         uint32_t loop_en = 0;
3717         uint8_t val = 0;
3718         int ret;
3719
3720         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3721
3722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3723         if (enable)
3724                 val = 1;
3725         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3726         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3727         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3728         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3729         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3730         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3731         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3732         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3733         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3734         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3735         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3736         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3737         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3738         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3739         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3740
3741         ret = hns3_cmd_send(hw, &desc, 1);
3742         if (ret)
3743                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3744
3745         return ret;
3746 }
3747
3748 static int
3749 hns3_get_mac_link_status(struct hns3_hw *hw)
3750 {
3751         struct hns3_link_status_cmd *req;
3752         struct hns3_cmd_desc desc;
3753         int link_status;
3754         int ret;
3755
3756         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3757         ret = hns3_cmd_send(hw, &desc, 1);
3758         if (ret) {
3759                 hns3_err(hw, "get link status cmd failed %d", ret);
3760                 return ret;
3761         }
3762
3763         req = (struct hns3_link_status_cmd *)desc.data;
3764         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3765
3766         return !!link_status;
3767 }
3768
3769 static void
3770 hns3_update_link_status(struct hns3_hw *hw)
3771 {
3772         int state;
3773
3774         state = hns3_get_mac_link_status(hw);
3775         if (state != hw->mac.link_status)
3776                 hw->mac.link_status = state;
3777 }
3778
3779 static void
3780 hns3_service_handler(void *param)
3781 {
3782         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3783         struct hns3_adapter *hns = eth_dev->data->dev_private;
3784         struct hns3_hw *hw = &hns->hw;
3785
3786         if (!hns3_is_reset_pending(hns)) {
3787                 hns3_update_speed_duplex(eth_dev);
3788                 hns3_update_link_status(hw);
3789         } else
3790                 hns3_warn(hw, "Cancel the query when reset is pending");
3791
3792         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3793 }
3794
3795 static int
3796 hns3_init_hardware(struct hns3_adapter *hns)
3797 {
3798         struct hns3_hw *hw = &hns->hw;
3799         int ret;
3800
3801         ret = hns3_map_tqp(hw);
3802         if (ret) {
3803                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3804                 return ret;
3805         }
3806
3807         ret = hns3_init_umv_space(hw);
3808         if (ret) {
3809                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3810                 return ret;
3811         }
3812
3813         ret = hns3_mac_init(hw);
3814         if (ret) {
3815                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3816                 goto err_mac_init;
3817         }
3818
3819         ret = hns3_init_mgr_tbl(hw);
3820         if (ret) {
3821                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3822                 goto err_mac_init;
3823         }
3824
3825         ret = hns3_set_promisc_mode(hw, false, false);
3826         if (ret) {
3827                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3828                 goto err_mac_init;
3829         }
3830
3831         ret = hns3_init_vlan_config(hns);
3832         if (ret) {
3833                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3834                 goto err_mac_init;
3835         }
3836
3837         ret = hns3_dcb_init(hw);
3838         if (ret) {
3839                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3840                 goto err_mac_init;
3841         }
3842
3843         ret = hns3_init_fd_config(hns);
3844         if (ret) {
3845                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3846                 goto err_mac_init;
3847         }
3848
3849         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3850         if (ret) {
3851                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3852                 goto err_mac_init;
3853         }
3854
3855         ret = hns3_config_gro(hw, false);
3856         if (ret) {
3857                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3858                 goto err_mac_init;
3859         }
3860         return 0;
3861
3862 err_mac_init:
3863         hns3_uninit_umv_space(hw);
3864         return ret;
3865 }
3866
3867 static int
3868 hns3_init_pf(struct rte_eth_dev *eth_dev)
3869 {
3870         struct rte_device *dev = eth_dev->device;
3871         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3872         struct hns3_adapter *hns = eth_dev->data->dev_private;
3873         struct hns3_hw *hw = &hns->hw;
3874         int ret;
3875
3876         PMD_INIT_FUNC_TRACE();
3877
3878         /* Get hardware io base address from pcie BAR2 IO space */
3879         hw->io_base = pci_dev->mem_resource[2].addr;
3880
3881         /* Firmware command queue initialize */
3882         ret = hns3_cmd_init_queue(hw);
3883         if (ret) {
3884                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3885                 goto err_cmd_init_queue;
3886         }
3887
3888         hns3_clear_all_event_cause(hw);
3889
3890         /* Firmware command initialize */
3891         ret = hns3_cmd_init(hw);
3892         if (ret) {
3893                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3894                 goto err_cmd_init;
3895         }
3896
3897         ret = rte_intr_callback_register(&pci_dev->intr_handle,
3898                                          hns3_interrupt_handler,
3899                                          eth_dev);
3900         if (ret) {
3901                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3902                 goto err_intr_callback_register;
3903         }
3904
3905         /* Enable interrupt */
3906         rte_intr_enable(&pci_dev->intr_handle);
3907         hns3_pf_enable_irq0(hw);
3908
3909         /* Get configuration */
3910         ret = hns3_get_configuration(hw);
3911         if (ret) {
3912                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3913                 goto err_get_config;
3914         }
3915
3916         ret = hns3_init_hardware(hns);
3917         if (ret) {
3918                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
3919                 goto err_get_config;
3920         }
3921
3922         /* Initialize flow director filter list & hash */
3923         ret = hns3_fdir_filter_init(hns);
3924         if (ret) {
3925                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
3926                 goto err_hw_init;
3927         }
3928
3929         hns3_set_default_rss_args(hw);
3930
3931         ret = hns3_enable_hw_error_intr(hns, true);
3932         if (ret) {
3933                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
3934                              ret);
3935                 goto err_fdir;
3936         }
3937
3938         return 0;
3939
3940 err_fdir:
3941         hns3_fdir_filter_uninit(hns);
3942 err_hw_init:
3943         hns3_uninit_umv_space(hw);
3944
3945 err_get_config:
3946         hns3_pf_disable_irq0(hw);
3947         rte_intr_disable(&pci_dev->intr_handle);
3948         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
3949                              eth_dev);
3950
3951 err_intr_callback_register:
3952         hns3_cmd_uninit(hw);
3953
3954 err_cmd_init:
3955         hns3_cmd_destroy_queue(hw);
3956
3957 err_cmd_init_queue:
3958         hw->io_base = NULL;
3959
3960         return ret;
3961 }
3962
3963 static void
3964 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
3965 {
3966         struct hns3_adapter *hns = eth_dev->data->dev_private;
3967         struct rte_device *dev = eth_dev->device;
3968         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3969         struct hns3_hw *hw = &hns->hw;
3970
3971         PMD_INIT_FUNC_TRACE();
3972
3973         hns3_enable_hw_error_intr(hns, false);
3974         hns3_rss_uninit(hns);
3975         hns3_fdir_filter_uninit(hns);
3976         hns3_uninit_umv_space(hw);
3977         hns3_pf_disable_irq0(hw);
3978         rte_intr_disable(&pci_dev->intr_handle);
3979         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
3980                              eth_dev);
3981         hns3_cmd_uninit(hw);
3982         hns3_cmd_destroy_queue(hw);
3983         hw->io_base = NULL;
3984 }
3985
3986 static int
3987 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
3988 {
3989         struct hns3_hw *hw = &hns->hw;
3990         int ret;
3991
3992         ret = hns3_dcb_cfg_update(hns);
3993         if (ret)
3994                 return ret;
3995
3996         /* Enable queues */
3997         ret = hns3_start_queues(hns, reset_queue);
3998         if (ret) {
3999                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4000                 return ret;
4001         }
4002
4003         /* Enable MAC */
4004         ret = hns3_cfg_mac_mode(hw, true);
4005         if (ret) {
4006                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4007                 goto err_config_mac_mode;
4008         }
4009         return 0;
4010
4011 err_config_mac_mode:
4012         hns3_stop_queues(hns, true);
4013         return ret;
4014 }
4015
4016 static int
4017 hns3_dev_start(struct rte_eth_dev *eth_dev)
4018 {
4019         struct hns3_adapter *hns = eth_dev->data->dev_private;
4020         struct hns3_hw *hw = &hns->hw;
4021         int ret;
4022
4023         PMD_INIT_FUNC_TRACE();
4024         if (rte_atomic16_read(&hw->reset.resetting))
4025                 return -EBUSY;
4026         rte_spinlock_lock(&hw->lock);
4027         hw->adapter_state = HNS3_NIC_STARTING;
4028
4029         ret = hns3_do_start(hns, true);
4030         if (ret) {
4031                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4032                 rte_spinlock_unlock(&hw->lock);
4033                 return ret;
4034         }
4035
4036         hw->adapter_state = HNS3_NIC_STARTED;
4037         rte_spinlock_unlock(&hw->lock);
4038         hns3_set_rxtx_function(eth_dev);
4039
4040         hns3_info(hw, "hns3 dev start successful!");
4041         return 0;
4042 }
4043
4044 static int
4045 hns3_do_stop(struct hns3_adapter *hns)
4046 {
4047         struct hns3_hw *hw = &hns->hw;
4048         bool reset_queue;
4049         int ret;
4050
4051         ret = hns3_cfg_mac_mode(hw, false);
4052         if (ret)
4053                 return ret;
4054         hw->mac.link_status = ETH_LINK_DOWN;
4055
4056         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4057                 hns3_configure_all_mac_addr(hns, true);
4058                 reset_queue = true;
4059         } else
4060                 reset_queue = false;
4061         hw->mac.default_addr_setted = false;
4062         return hns3_stop_queues(hns, reset_queue);
4063 }
4064
4065 static void
4066 hns3_dev_stop(struct rte_eth_dev *eth_dev)
4067 {
4068         struct hns3_adapter *hns = eth_dev->data->dev_private;
4069         struct hns3_hw *hw = &hns->hw;
4070
4071         PMD_INIT_FUNC_TRACE();
4072
4073         hw->adapter_state = HNS3_NIC_STOPPING;
4074         hns3_set_rxtx_function(eth_dev);
4075
4076         rte_spinlock_lock(&hw->lock);
4077         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4078                 hns3_do_stop(hns);
4079                 hns3_dev_release_mbufs(hns);
4080                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4081         }
4082         rte_spinlock_unlock(&hw->lock);
4083 }
4084
4085 static void
4086 hns3_dev_close(struct rte_eth_dev *eth_dev)
4087 {
4088         struct hns3_adapter *hns = eth_dev->data->dev_private;
4089         struct hns3_hw *hw = &hns->hw;
4090
4091         if (hw->adapter_state == HNS3_NIC_STARTED)
4092                 hns3_dev_stop(eth_dev);
4093
4094         hw->adapter_state = HNS3_NIC_CLOSING;
4095         hns3_reset_abort(hns);
4096         hw->adapter_state = HNS3_NIC_CLOSED;
4097         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4098
4099         hns3_configure_all_mc_mac_addr(hns, true);
4100         hns3_remove_all_vlan_table(hns);
4101         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4102         hns3_uninit_pf(eth_dev);
4103         hns3_free_all_queues(eth_dev);
4104         rte_free(hw->reset.wait_data);
4105         rte_free(eth_dev->process_private);
4106         eth_dev->process_private = NULL;
4107         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4108 }
4109
4110 static int
4111 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4112 {
4113         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4115
4116         fc_conf->pause_time = pf->pause_time;
4117
4118         /* return fc current mode */
4119         switch (hw->current_mode) {
4120         case HNS3_FC_FULL:
4121                 fc_conf->mode = RTE_FC_FULL;
4122                 break;
4123         case HNS3_FC_TX_PAUSE:
4124                 fc_conf->mode = RTE_FC_TX_PAUSE;
4125                 break;
4126         case HNS3_FC_RX_PAUSE:
4127                 fc_conf->mode = RTE_FC_RX_PAUSE;
4128                 break;
4129         case HNS3_FC_NONE:
4130         default:
4131                 fc_conf->mode = RTE_FC_NONE;
4132                 break;
4133         }
4134
4135         return 0;
4136 }
4137
4138 static void
4139 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4140 {
4141         switch (mode) {
4142         case RTE_FC_NONE:
4143                 hw->requested_mode = HNS3_FC_NONE;
4144                 break;
4145         case RTE_FC_RX_PAUSE:
4146                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4147                 break;
4148         case RTE_FC_TX_PAUSE:
4149                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4150                 break;
4151         case RTE_FC_FULL:
4152                 hw->requested_mode = HNS3_FC_FULL;
4153                 break;
4154         default:
4155                 hw->requested_mode = HNS3_FC_NONE;
4156                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4157                           "configured to RTE_FC_NONE", mode);
4158                 break;
4159         }
4160 }
4161
4162 static int
4163 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4164 {
4165         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4166         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4167         int ret;
4168
4169         if (fc_conf->high_water || fc_conf->low_water ||
4170             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4171                 hns3_err(hw, "Unsupported flow control settings specified, "
4172                          "high_water(%u), low_water(%u), send_xon(%u) and "
4173                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4174                          fc_conf->high_water, fc_conf->low_water,
4175                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4176                 return -EINVAL;
4177         }
4178         if (fc_conf->autoneg) {
4179                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4180                 return -EINVAL;
4181         }
4182         if (!fc_conf->pause_time) {
4183                 hns3_err(hw, "Invalid pause time %d setting.",
4184                          fc_conf->pause_time);
4185                 return -EINVAL;
4186         }
4187
4188         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4189             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4190                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4191                          "current_fc_status = %d", hw->current_fc_status);
4192                 return -EOPNOTSUPP;
4193         }
4194
4195         hns3_get_fc_mode(hw, fc_conf->mode);
4196         if (hw->requested_mode == hw->current_mode &&
4197             pf->pause_time == fc_conf->pause_time)
4198                 return 0;
4199
4200         rte_spinlock_lock(&hw->lock);
4201         ret = hns3_fc_enable(dev, fc_conf);
4202         rte_spinlock_unlock(&hw->lock);
4203
4204         return ret;
4205 }
4206
4207 static int
4208 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4209                             struct rte_eth_pfc_conf *pfc_conf)
4210 {
4211         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4213         uint8_t priority;
4214         int ret;
4215
4216         if (!hns3_dev_dcb_supported(hw)) {
4217                 hns3_err(hw, "This port does not support dcb configurations.");
4218                 return -EOPNOTSUPP;
4219         }
4220
4221         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4222             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4223                 hns3_err(hw, "Unsupported flow control settings specified, "
4224                          "high_water(%u), low_water(%u), send_xon(%u) and "
4225                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4226                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4227                          pfc_conf->fc.send_xon,
4228                          pfc_conf->fc.mac_ctrl_frame_fwd);
4229                 return -EINVAL;
4230         }
4231         if (pfc_conf->fc.autoneg) {
4232                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4233                 return -EINVAL;
4234         }
4235         if (pfc_conf->fc.pause_time == 0) {
4236                 hns3_err(hw, "Invalid pause time %d setting.",
4237                          pfc_conf->fc.pause_time);
4238                 return -EINVAL;
4239         }
4240
4241         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4242             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4243                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4244                              "current_fc_status = %d", hw->current_fc_status);
4245                 return -EOPNOTSUPP;
4246         }
4247
4248         priority = pfc_conf->priority;
4249         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4250         if (hw->dcb_info.pfc_en & BIT(priority) &&
4251             hw->requested_mode == hw->current_mode &&
4252             pfc_conf->fc.pause_time == pf->pause_time)
4253                 return 0;
4254
4255         rte_spinlock_lock(&hw->lock);
4256         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4257         rte_spinlock_unlock(&hw->lock);
4258
4259         return ret;
4260 }
4261
4262 static int
4263 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4264 {
4265         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4266         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4267         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4268         int i;
4269
4270         rte_spinlock_lock(&hw->lock);
4271         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4272                 dcb_info->nb_tcs = pf->local_max_tc;
4273         else
4274                 dcb_info->nb_tcs = 1;
4275
4276         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4277                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4278         for (i = 0; i < dcb_info->nb_tcs; i++)
4279                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4280
4281         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4282                 dcb_info->tc_queue.tc_rxq[0][i].base =
4283                                         hw->tc_queue[i].tqp_offset;
4284                 dcb_info->tc_queue.tc_txq[0][i].base =
4285                                         hw->tc_queue[i].tqp_offset;
4286                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
4287                                         hw->tc_queue[i].tqp_count;
4288                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4289                                         hw->tc_queue[i].tqp_count;
4290         }
4291         rte_spinlock_unlock(&hw->lock);
4292
4293         return 0;
4294 }
4295
4296 static int
4297 hns3_reinit_dev(struct hns3_adapter *hns)
4298 {
4299         struct hns3_hw *hw = &hns->hw;
4300         int ret;
4301
4302         ret = hns3_cmd_init(hw);
4303         if (ret) {
4304                 hns3_err(hw, "Failed to init cmd: %d", ret);
4305                 return ret;
4306         }
4307
4308         ret = hns3_reset_all_queues(hns);
4309         if (ret) {
4310                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4311                 goto err_init;
4312         }
4313
4314         ret = hns3_init_hardware(hns);
4315         if (ret) {
4316                 hns3_err(hw, "Failed to init hardware: %d", ret);
4317                 goto err_init;
4318         }
4319
4320         ret = hns3_enable_hw_error_intr(hns, true);
4321         if (ret) {
4322                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4323                              ret);
4324                 goto err_mac_init;
4325         }
4326         hns3_info(hw, "Reset done, driver initialization finished.");
4327
4328         return 0;
4329
4330 err_mac_init:
4331         hns3_uninit_umv_space(hw);
4332 err_init:
4333         hns3_cmd_uninit(hw);
4334
4335         return ret;
4336 }
4337
4338 static bool
4339 is_pf_reset_done(struct hns3_hw *hw)
4340 {
4341         uint32_t val, reg, reg_bit;
4342
4343         switch (hw->reset.level) {
4344         case HNS3_IMP_RESET:
4345                 reg = HNS3_GLOBAL_RESET_REG;
4346                 reg_bit = HNS3_IMP_RESET_BIT;
4347                 break;
4348         case HNS3_GLOBAL_RESET:
4349                 reg = HNS3_GLOBAL_RESET_REG;
4350                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4351                 break;
4352         case HNS3_FUNC_RESET:
4353                 reg = HNS3_FUN_RST_ING;
4354                 reg_bit = HNS3_FUN_RST_ING_B;
4355                 break;
4356         case HNS3_FLR_RESET:
4357         default:
4358                 hns3_err(hw, "Wait for unsupported reset level: %d",
4359                          hw->reset.level);
4360                 return true;
4361         }
4362         val = hns3_read_dev(hw, reg);
4363         if (hns3_get_bit(val, reg_bit))
4364                 return false;
4365         else
4366                 return true;
4367 }
4368
4369 bool
4370 hns3_is_reset_pending(struct hns3_adapter *hns)
4371 {
4372         struct hns3_hw *hw = &hns->hw;
4373         enum hns3_reset_level reset;
4374
4375         hns3_check_event_cause(hns, NULL);
4376         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4377         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4378                 hns3_warn(hw, "High level reset %d is pending", reset);
4379                 return true;
4380         }
4381         reset = hns3_get_reset_level(hns, &hw->reset.request);
4382         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4383                 hns3_warn(hw, "High level reset %d is request", reset);
4384                 return true;
4385         }
4386         return false;
4387 }
4388
4389 static int
4390 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4391 {
4392         struct hns3_hw *hw = &hns->hw;
4393         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4394         struct timeval tv;
4395
4396         if (wait_data->result == HNS3_WAIT_SUCCESS)
4397                 return 0;
4398         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4399                 gettimeofday(&tv, NULL);
4400                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4401                           tv.tv_sec, tv.tv_usec);
4402                 return -ETIME;
4403         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4404                 return -EAGAIN;
4405
4406         wait_data->hns = hns;
4407         wait_data->check_completion = is_pf_reset_done;
4408         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4409                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4410         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4411         wait_data->count = HNS3_RESET_WAIT_CNT;
4412         wait_data->result = HNS3_WAIT_REQUEST;
4413         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4414         return -EAGAIN;
4415 }
4416
4417 static int
4418 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4419 {
4420         struct hns3_cmd_desc desc;
4421         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4422
4423         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4424         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4425         req->fun_reset_vfid = func_id;
4426
4427         return hns3_cmd_send(hw, &desc, 1);
4428 }
4429
4430 static int
4431 hns3_imp_reset_cmd(struct hns3_hw *hw)
4432 {
4433         struct hns3_cmd_desc desc;
4434
4435         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4436         desc.data[0] = 0xeedd;
4437
4438         return hns3_cmd_send(hw, &desc, 1);
4439 }
4440
4441 static void
4442 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4443 {
4444         struct hns3_hw *hw = &hns->hw;
4445         struct timeval tv;
4446         uint32_t val;
4447
4448         gettimeofday(&tv, NULL);
4449         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4450             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4451                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4452                           tv.tv_sec, tv.tv_usec);
4453                 return;
4454         }
4455
4456         switch (reset_level) {
4457         case HNS3_IMP_RESET:
4458                 hns3_imp_reset_cmd(hw);
4459                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4460                           tv.tv_sec, tv.tv_usec);
4461                 break;
4462         case HNS3_GLOBAL_RESET:
4463                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4464                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4465                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4466                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4467                           tv.tv_sec, tv.tv_usec);
4468                 break;
4469         case HNS3_FUNC_RESET:
4470                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4471                           tv.tv_sec, tv.tv_usec);
4472                 /* schedule again to check later */
4473                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4474                 hns3_schedule_reset(hns);
4475                 break;
4476         default:
4477                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4478                 return;
4479         }
4480         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4481 }
4482
4483 static enum hns3_reset_level
4484 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4485 {
4486         struct hns3_hw *hw = &hns->hw;
4487         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4488
4489         /* Return the highest priority reset level amongst all */
4490         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4491                 reset_level = HNS3_IMP_RESET;
4492         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4493                 reset_level = HNS3_GLOBAL_RESET;
4494         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4495                 reset_level = HNS3_FUNC_RESET;
4496         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4497                 reset_level = HNS3_FLR_RESET;
4498
4499         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4500                 return HNS3_NONE_RESET;
4501
4502         return reset_level;
4503 }
4504
4505 static int
4506 hns3_prepare_reset(struct hns3_adapter *hns)
4507 {
4508         struct hns3_hw *hw = &hns->hw;
4509         uint32_t reg_val;
4510         int ret;
4511
4512         switch (hw->reset.level) {
4513         case HNS3_FUNC_RESET:
4514                 ret = hns3_func_reset_cmd(hw, 0);
4515                 if (ret)
4516                         return ret;
4517
4518                 /*
4519                  * After performaning pf reset, it is not necessary to do the
4520                  * mailbox handling or send any command to firmware, because
4521                  * any mailbox handling or command to firmware is only valid
4522                  * after hns3_cmd_init is called.
4523                  */
4524                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4525                 hw->reset.stats.request_cnt++;
4526                 break;
4527         case HNS3_IMP_RESET:
4528                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4529                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4530                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4531                 break;
4532         default:
4533                 break;
4534         }
4535         return 0;
4536 }
4537
4538 static int
4539 hns3_set_rst_done(struct hns3_hw *hw)
4540 {
4541         struct hns3_pf_rst_done_cmd *req;
4542         struct hns3_cmd_desc desc;
4543
4544         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4545         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4546         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4547         return hns3_cmd_send(hw, &desc, 1);
4548 }
4549
4550 static int
4551 hns3_stop_service(struct hns3_adapter *hns)
4552 {
4553         struct hns3_hw *hw = &hns->hw;
4554         struct rte_eth_dev *eth_dev;
4555
4556         eth_dev = &rte_eth_devices[hw->data->port_id];
4557         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4558         hw->mac.link_status = ETH_LINK_DOWN;
4559
4560         hns3_set_rxtx_function(eth_dev);
4561
4562         rte_spinlock_lock(&hw->lock);
4563         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4564             hw->adapter_state == HNS3_NIC_STOPPING) {
4565                 hns3_do_stop(hns);
4566                 hw->reset.mbuf_deferred_free = true;
4567         } else
4568                 hw->reset.mbuf_deferred_free = false;
4569
4570         /*
4571          * It is cumbersome for hardware to pick-and-choose entries for deletion
4572          * from table space. Hence, for function reset software intervention is
4573          * required to delete the entries
4574          */
4575         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4576                 hns3_configure_all_mc_mac_addr(hns, true);
4577         rte_spinlock_unlock(&hw->lock);
4578
4579         return 0;
4580 }
4581
4582 static int
4583 hns3_start_service(struct hns3_adapter *hns)
4584 {
4585         struct hns3_hw *hw = &hns->hw;
4586         struct rte_eth_dev *eth_dev;
4587
4588         if (hw->reset.level == HNS3_IMP_RESET ||
4589             hw->reset.level == HNS3_GLOBAL_RESET)
4590                 hns3_set_rst_done(hw);
4591         eth_dev = &rte_eth_devices[hw->data->port_id];
4592         hns3_set_rxtx_function(eth_dev);
4593         hns3_service_handler(eth_dev);
4594         return 0;
4595 }
4596
4597 static int
4598 hns3_restore_conf(struct hns3_adapter *hns)
4599 {
4600         struct hns3_hw *hw = &hns->hw;
4601         int ret;
4602
4603         ret = hns3_configure_all_mac_addr(hns, false);
4604         if (ret)
4605                 return ret;
4606
4607         ret = hns3_configure_all_mc_mac_addr(hns, false);
4608         if (ret)
4609                 goto err_mc_mac;
4610
4611         ret = hns3_dev_promisc_restore(hns);
4612         if (ret)
4613                 goto err_promisc;
4614
4615         ret = hns3_restore_vlan_table(hns);
4616         if (ret)
4617                 goto err_promisc;
4618
4619         ret = hns3_restore_vlan_conf(hns);
4620         if (ret)
4621                 goto err_promisc;
4622
4623         ret = hns3_restore_all_fdir_filter(hns);
4624         if (ret)
4625                 goto err_promisc;
4626
4627         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4628                 ret = hns3_do_start(hns, false);
4629                 if (ret)
4630                         goto err_promisc;
4631                 hns3_info(hw, "hns3 dev restart successful!");
4632         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4633                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4634         return 0;
4635
4636 err_promisc:
4637         hns3_configure_all_mc_mac_addr(hns, true);
4638 err_mc_mac:
4639         hns3_configure_all_mac_addr(hns, true);
4640         return ret;
4641 }
4642
4643 static void
4644 hns3_reset_service(void *param)
4645 {
4646         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4647         struct hns3_hw *hw = &hns->hw;
4648         enum hns3_reset_level reset_level;
4649         struct timeval tv_delta;
4650         struct timeval tv_start;
4651         struct timeval tv;
4652         uint64_t msec;
4653         int ret;
4654
4655         /*
4656          * The interrupt is not triggered within the delay time.
4657          * The interrupt may have been lost. It is necessary to handle
4658          * the interrupt to recover from the error.
4659          */
4660         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4661                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4662                 hns3_err(hw, "Handling interrupts in delayed tasks");
4663                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4664         }
4665         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4666
4667         /*
4668          * Check if there is any ongoing reset in the hardware. This status can
4669          * be checked from reset_pending. If there is then, we need to wait for
4670          * hardware to complete reset.
4671          *    a. If we are able to figure out in reasonable time that hardware
4672          *       has fully resetted then, we can proceed with driver, client
4673          *       reset.
4674          *    b. else, we can come back later to check this status so re-sched
4675          *       now.
4676          */
4677         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4678         if (reset_level != HNS3_NONE_RESET) {
4679                 gettimeofday(&tv_start, NULL);
4680                 ret = hns3_reset_process(hns, reset_level);
4681                 gettimeofday(&tv, NULL);
4682                 timersub(&tv, &tv_start, &tv_delta);
4683                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4684                        tv_delta.tv_usec / USEC_PER_MSEC;
4685                 if (msec > HNS3_RESET_PROCESS_MS)
4686                         hns3_err(hw, "%d handle long time delta %" PRIx64
4687                                      " ms time=%ld.%.6ld",
4688                                  hw->reset.level, msec,
4689                                  tv.tv_sec, tv.tv_usec);
4690                 if (ret == -EAGAIN)
4691                         return;
4692         }
4693
4694         /* Check if we got any *new* reset requests to be honored */
4695         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4696         if (reset_level != HNS3_NONE_RESET)
4697                 hns3_msix_process(hns, reset_level);
4698 }
4699
4700 static const struct eth_dev_ops hns3_eth_dev_ops = {
4701         .dev_start          = hns3_dev_start,
4702         .dev_stop           = hns3_dev_stop,
4703         .dev_close          = hns3_dev_close,
4704         .promiscuous_enable = hns3_dev_promiscuous_enable,
4705         .promiscuous_disable = hns3_dev_promiscuous_disable,
4706         .allmulticast_enable  = hns3_dev_allmulticast_enable,
4707         .allmulticast_disable = hns3_dev_allmulticast_disable,
4708         .mtu_set            = hns3_dev_mtu_set,
4709         .stats_get          = hns3_stats_get,
4710         .stats_reset        = hns3_stats_reset,
4711         .xstats_get         = hns3_dev_xstats_get,
4712         .xstats_get_names   = hns3_dev_xstats_get_names,
4713         .xstats_reset       = hns3_dev_xstats_reset,
4714         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
4715         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4716         .dev_infos_get          = hns3_dev_infos_get,
4717         .fw_version_get         = hns3_fw_version_get,
4718         .rx_queue_setup         = hns3_rx_queue_setup,
4719         .tx_queue_setup         = hns3_tx_queue_setup,
4720         .rx_queue_release       = hns3_dev_rx_queue_release,
4721         .tx_queue_release       = hns3_dev_tx_queue_release,
4722         .dev_configure          = hns3_dev_configure,
4723         .flow_ctrl_get          = hns3_flow_ctrl_get,
4724         .flow_ctrl_set          = hns3_flow_ctrl_set,
4725         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4726         .mac_addr_add           = hns3_add_mac_addr,
4727         .mac_addr_remove        = hns3_remove_mac_addr,
4728         .mac_addr_set           = hns3_set_default_mac_addr,
4729         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
4730         .link_update            = hns3_dev_link_update,
4731         .rss_hash_update        = hns3_dev_rss_hash_update,
4732         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
4733         .reta_update            = hns3_dev_rss_reta_update,
4734         .reta_query             = hns3_dev_rss_reta_query,
4735         .filter_ctrl            = hns3_dev_filter_ctrl,
4736         .vlan_filter_set        = hns3_vlan_filter_set,
4737         .vlan_tpid_set          = hns3_vlan_tpid_set,
4738         .vlan_offload_set       = hns3_vlan_offload_set,
4739         .vlan_pvid_set          = hns3_vlan_pvid_set,
4740         .get_reg                = hns3_get_regs,
4741         .get_dcb_info           = hns3_get_dcb_info,
4742         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4743 };
4744
4745 static const struct hns3_reset_ops hns3_reset_ops = {
4746         .reset_service       = hns3_reset_service,
4747         .stop_service        = hns3_stop_service,
4748         .prepare_reset       = hns3_prepare_reset,
4749         .wait_hardware_ready = hns3_wait_hardware_ready,
4750         .reinit_dev          = hns3_reinit_dev,
4751         .restore_conf        = hns3_restore_conf,
4752         .start_service       = hns3_start_service,
4753 };
4754
4755 static int
4756 hns3_dev_init(struct rte_eth_dev *eth_dev)
4757 {
4758         struct rte_device *dev = eth_dev->device;
4759         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4760         struct hns3_adapter *hns = eth_dev->data->dev_private;
4761         struct hns3_hw *hw = &hns->hw;
4762         uint16_t device_id = pci_dev->id.device_id;
4763         int ret;
4764
4765         PMD_INIT_FUNC_TRACE();
4766         eth_dev->process_private = (struct hns3_process_private *)
4767             rte_zmalloc_socket("hns3_filter_list",
4768                                sizeof(struct hns3_process_private),
4769                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4770         if (eth_dev->process_private == NULL) {
4771                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4772                 return -ENOMEM;
4773         }
4774         /* initialize flow filter lists */
4775         hns3_filterlist_init(eth_dev);
4776
4777         hns3_set_rxtx_function(eth_dev);
4778         eth_dev->dev_ops = &hns3_eth_dev_ops;
4779         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4780                 return 0;
4781
4782         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
4783
4784         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
4785             device_id == HNS3_DEV_ID_50GE_RDMA ||
4786             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
4787                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
4788
4789         hns->is_vf = false;
4790         hw->data = eth_dev->data;
4791
4792         /*
4793          * Set default max packet size according to the mtu
4794          * default vale in DPDK frame.
4795          */
4796         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
4797
4798         ret = hns3_reset_init(hw);
4799         if (ret)
4800                 goto err_init_reset;
4801         hw->reset.ops = &hns3_reset_ops;
4802
4803         ret = hns3_init_pf(eth_dev);
4804         if (ret) {
4805                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
4806                 goto err_init_pf;
4807         }
4808
4809         /* Allocate memory for storing MAC addresses */
4810         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
4811                                                sizeof(struct rte_ether_addr) *
4812                                                HNS3_UC_MACADDR_NUM, 0);
4813         if (eth_dev->data->mac_addrs == NULL) {
4814                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
4815                              "to store MAC addresses",
4816                              sizeof(struct rte_ether_addr) *
4817                              HNS3_UC_MACADDR_NUM);
4818                 ret = -ENOMEM;
4819                 goto err_rte_zmalloc;
4820         }
4821
4822         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
4823                             &eth_dev->data->mac_addrs[0]);
4824
4825         hw->adapter_state = HNS3_NIC_INITIALIZED;
4826         /*
4827          * Pass the information to the rte_eth_dev_close() that it should also
4828          * release the private port resources.
4829          */
4830         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4831
4832         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
4833                 hns3_err(hw, "Reschedule reset service after dev_init");
4834                 hns3_schedule_reset(hns);
4835         } else {
4836                 /* IMP will wait ready flag before reset */
4837                 hns3_notify_reset_ready(hw, false);
4838         }
4839
4840         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4841         hns3_info(hw, "hns3 dev initialization successful!");
4842         return 0;
4843
4844 err_rte_zmalloc:
4845         hns3_uninit_pf(eth_dev);
4846
4847 err_init_pf:
4848         rte_free(hw->reset.wait_data);
4849 err_init_reset:
4850         eth_dev->dev_ops = NULL;
4851         eth_dev->rx_pkt_burst = NULL;
4852         eth_dev->tx_pkt_burst = NULL;
4853         eth_dev->tx_pkt_prepare = NULL;
4854         rte_free(eth_dev->process_private);
4855         eth_dev->process_private = NULL;
4856         return ret;
4857 }
4858
4859 static int
4860 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
4861 {
4862         struct hns3_adapter *hns = eth_dev->data->dev_private;
4863         struct hns3_hw *hw = &hns->hw;
4864
4865         PMD_INIT_FUNC_TRACE();
4866
4867         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4868                 return -EPERM;
4869
4870         eth_dev->dev_ops = NULL;
4871         eth_dev->rx_pkt_burst = NULL;
4872         eth_dev->tx_pkt_burst = NULL;
4873         eth_dev->tx_pkt_prepare = NULL;
4874         if (hw->adapter_state < HNS3_NIC_CLOSING)
4875                 hns3_dev_close(eth_dev);
4876
4877         hw->adapter_state = HNS3_NIC_REMOVED;
4878         return 0;
4879 }
4880
4881 static int
4882 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4883                    struct rte_pci_device *pci_dev)
4884 {
4885         return rte_eth_dev_pci_generic_probe(pci_dev,
4886                                              sizeof(struct hns3_adapter),
4887                                              hns3_dev_init);
4888 }
4889
4890 static int
4891 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
4892 {
4893         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
4894 }
4895
4896 static const struct rte_pci_id pci_id_hns3_map[] = {
4897         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
4898         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
4899         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
4900         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
4901         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
4902         { .vendor_id = 0, /* sentinel */ },
4903 };
4904
4905 static struct rte_pci_driver rte_hns3_pmd = {
4906         .id_table = pci_id_hns3_map,
4907         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
4908         .probe = eth_hns3_pci_probe,
4909         .remove = eth_hns3_pci_remove,
4910 };
4911
4912 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
4913 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
4914 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
4915
4916 RTE_INIT(hns3_init_log)
4917 {
4918         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
4919         if (hns3_logtype_init >= 0)
4920                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
4921         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
4922         if (hns3_logtype_driver >= 0)
4923                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
4924 }