drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <rte_alarm.h>
   6 #include <rte_bus_pci.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_pci.h>
   9 #include <rte_kvargs.h>
  10
  11 #include "hns3_ethdev.h"
  12 #include "hns3_logs.h"
  13 #include "hns3_rxtx.h"
  14 #include "hns3_intr.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_dcb.h"
  17 #include "hns3_mp.h"
  18
  19 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  20 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  21
  22 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  23 #define HNS3_SERVICE_QUICK_INTERVAL     10
  24 #define HNS3_INVALID_PVID               0xFFFF
  25
  26 #define HNS3_FILTER_TYPE_VF             0
  27 #define HNS3_FILTER_TYPE_PORT           1
  28 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  29 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  30 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  31 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  32 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  33 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  34                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  35 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  36                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  37
  38 /* Reset related Registers */
  39 #define HNS3_GLOBAL_RESET_BIT           0
  40 #define HNS3_CORE_RESET_BIT             1
  41 #define HNS3_IMP_RESET_BIT              2
  42 #define HNS3_FUN_RST_ING_B              0
  43
  44 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  45 #define HNS3_VECTOR0_IMP_CMDQ_ERR_B     4U
  46 #define HNS3_VECTOR0_IMP_RD_POISON_B    5U
  47 #define HNS3_VECTOR0_ALL_MSIX_ERR_B     6U
  48
  49 #define HNS3_RESET_WAIT_MS      100
  50 #define HNS3_RESET_WAIT_CNT     200
  51
  52 /* FEC mode order defined in HNS3 hardware */
  53 #define HNS3_HW_FEC_MODE_NOFEC  0
  54 #define HNS3_HW_FEC_MODE_BASER  1
  55 #define HNS3_HW_FEC_MODE_RS     2
  56
  57 enum hns3_evt_cause {
  58         HNS3_VECTOR0_EVENT_RST,
  59         HNS3_VECTOR0_EVENT_MBX,
  60         HNS3_VECTOR0_EVENT_ERR,
  61         HNS3_VECTOR0_EVENT_PTP,
  62         HNS3_VECTOR0_EVENT_OTHER,
  63 };
  64
  65 static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
  66         { ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  67                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  68                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  69
  70         { ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  71                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  72                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  73                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  74
  75         { ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  76                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  77                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
  78
  79         { ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  80                              RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  81                              RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
  82                              RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  83
  84         { ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  85                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  86                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
  87
  88         { ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
  89                               RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
  90                               RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
  91 };
  92
  93 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  94                                                  uint64_t *levels);
  95 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  96 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  97                                     int on);
  98 static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
  99 static bool hns3_update_link_status(struct hns3_hw *hw);
 100
 101 static int hns3_add_mc_addr(struct hns3_hw *hw,
 102                             struct rte_ether_addr *mac_addr);
 103 static int hns3_remove_mc_addr(struct hns3_hw *hw,
 104                             struct rte_ether_addr *mac_addr);
 105 static int hns3_restore_fec(struct hns3_hw *hw);
 106 static int hns3_query_dev_fec_info(struct hns3_hw *hw);
 107 static int hns3_do_stop(struct hns3_adapter *hns);
 108 static int hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds);
 109
 110 void hns3_ether_format_addr(char *buf, uint16_t size,
 111                             const struct rte_ether_addr *ether_addr)
 112 {
 113         snprintf(buf, size, "%02X:**:**:**:%02X:%02X",
 114                 ether_addr->addr_bytes[0],
 115                 ether_addr->addr_bytes[4],
 116                 ether_addr->addr_bytes[5]);
 117 }
 118
 119 static void
 120 hns3_pf_disable_irq0(struct hns3_hw *hw)
 121 {
 122         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 123 }
 124
 125 static void
 126 hns3_pf_enable_irq0(struct hns3_hw *hw)
 127 {
 128         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 129 }
 130
 131 static enum hns3_evt_cause
 132 hns3_proc_imp_reset_event(struct hns3_adapter *hns, bool is_delay,
 133                           uint32_t *vec_val)
 134 {
 135         struct hns3_hw *hw = &hns->hw;
 136
 137         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 138         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 139         *vec_val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 140         if (!is_delay) {
 141                 hw->reset.stats.imp_cnt++;
 142                 hns3_warn(hw, "IMP reset detected, clear reset status");
 143         } else {
 144                 hns3_schedule_delayed_reset(hns);
 145                 hns3_warn(hw, "IMP reset detected, don't clear reset status");
 146         }
 147
 148         return HNS3_VECTOR0_EVENT_RST;
 149 }
 150
 151 static enum hns3_evt_cause
 152 hns3_proc_global_reset_event(struct hns3_adapter *hns, bool is_delay,
 153                              uint32_t *vec_val)
 154 {
 155         struct hns3_hw *hw = &hns->hw;
 156
 157         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
 158         hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 159         *vec_val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 160         if (!is_delay) {
 161                 hw->reset.stats.global_cnt++;
 162                 hns3_warn(hw, "Global reset detected, clear reset status");
 163         } else {
 164                 hns3_schedule_delayed_reset(hns);
 165                 hns3_warn(hw,
 166                           "Global reset detected, don't clear reset status");
 167         }
 168
 169         return HNS3_VECTOR0_EVENT_RST;
 170 }
 171
 172 static enum hns3_evt_cause
 173 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 174 {
 175         struct hns3_hw *hw = &hns->hw;
 176         uint32_t vector0_int_stats;
 177         uint32_t cmdq_src_val;
 178         uint32_t hw_err_src_reg;
 179         uint32_t val;
 180         enum hns3_evt_cause ret;
 181         bool is_delay;
 182
 183         /* fetch the events from their corresponding regs */
 184         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 185         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 186         hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 187
 188         is_delay = clearval == NULL ? true : false;
 189         /*
 190          * Assumption: If by any chance reset and mailbox events are reported
 191          * together then we will only process reset event and defer the
 192          * processing of the mailbox events. Since, we would have not cleared
 193          * RX CMDQ event this time we would receive again another interrupt
 194          * from H/W just for the mailbox.
 195          */
 196         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 197                 ret = hns3_proc_imp_reset_event(hns, is_delay, &val);
 198                 goto out;
 199         }
 200
 201         /* Global reset */
 202         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 203                 ret = hns3_proc_global_reset_event(hns, is_delay, &val);
 204                 goto out;
 205         }
 206
 207         /* Check for vector0 1588 event source */
 208         if (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {
 209                 val = BIT(HNS3_VECTOR0_1588_INT_B);
 210                 ret = HNS3_VECTOR0_EVENT_PTP;
 211                 goto out;
 212         }
 213
 214         /* check for vector0 msix event source */
 215         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
 216             hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
 217                 val = vector0_int_stats | hw_err_src_reg;
 218                 ret = HNS3_VECTOR0_EVENT_ERR;
 219                 goto out;
 220         }
 221
 222         /* check for vector0 mailbox(=CMDQ RX) event source */
 223         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 224                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 225                 val = cmdq_src_val;
 226                 ret = HNS3_VECTOR0_EVENT_MBX;
 227                 goto out;
 228         }
 229
 230         val = vector0_int_stats;
 231         ret = HNS3_VECTOR0_EVENT_OTHER;
 232 out:
 233
 234         if (clearval)
 235                 *clearval = val;
 236         return ret;
 237 }
 238
 239 static bool
 240 hns3_is_1588_event_type(uint32_t event_type)
 241 {
 242         return (event_type == HNS3_VECTOR0_EVENT_PTP);
 243 }
 244
 245 static void
 246 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 247 {
 248         if (event_type == HNS3_VECTOR0_EVENT_RST ||
 249             hns3_is_1588_event_type(event_type))
 250                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 251         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 252                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 253 }
 254
 255 static void
 256 hns3_clear_all_event_cause(struct hns3_hw *hw)
 257 {
 258         uint32_t vector0_int_stats;
 259         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 260
 261         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 262                 hns3_warn(hw, "Probe during IMP reset interrupt");
 263
 264         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 265                 hns3_warn(hw, "Probe during Global reset interrupt");
 266
 267         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 268                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 269                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 270                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 271         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 272         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,
 273                                 BIT(HNS3_VECTOR0_1588_INT_B));
 274 }
 275
 276 static void
 277 hns3_handle_mac_tnl(struct hns3_hw *hw)
 278 {
 279         struct hns3_cmd_desc desc;
 280         uint32_t status;
 281         int ret;
 282
 283         /* query and clear mac tnl interruptions */
 284         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_MAC_TNL_INT, true);
 285         ret = hns3_cmd_send(hw, &desc, 1);
 286         if (ret) {
 287                 hns3_err(hw, "failed to query mac tnl int, ret = %d.", ret);
 288                 return;
 289         }
 290
 291         status = rte_le_to_cpu_32(desc.data[0]);
 292         if (status) {
 293                 hns3_warn(hw, "mac tnl int occurs, status = 0x%x.", status);
 294                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_MAC_TNL_INT,
 295                                           false);
 296                 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_CLR);
 297                 ret = hns3_cmd_send(hw, &desc, 1);
 298                 if (ret)
 299                         hns3_err(hw, "failed to clear mac tnl int, ret = %d.",
 300                                  ret);
 301         }
 302 }
 303
 304 static void
 305 hns3_interrupt_handler(void *param)
 306 {
 307         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 308         struct hns3_adapter *hns = dev->data->dev_private;
 309         struct hns3_hw *hw = &hns->hw;
 310         enum hns3_evt_cause event_cause;
 311         uint32_t clearval = 0;
 312         uint32_t vector0_int;
 313         uint32_t ras_int;
 314         uint32_t cmdq_int;
 315
 316         /* Disable interrupt */
 317         hns3_pf_disable_irq0(hw);
 318
 319         event_cause = hns3_check_event_cause(hns, &clearval);
 320         vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 321         ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
 322         cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 323         /* vector 0 interrupt is shared with reset and mailbox source events. */
 324         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 325                 hns3_warn(hw, "received interrupt: vector0_int_stat:0x%x "
 326                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 327                           vector0_int, ras_int, cmdq_int);
 328                 hns3_handle_mac_tnl(hw);
 329                 hns3_handle_error(hns);
 330         } else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
 331                 hns3_warn(hw, "received reset interrupt");
 332                 hns3_schedule_reset(hns);
 333         } else if (event_cause == HNS3_VECTOR0_EVENT_MBX) {
 334                 hns3_dev_handle_mbx_msg(hw);
 335         } else {
 336                 hns3_warn(hw, "received unknown event: vector0_int_stat:0x%x "
 337                           "ras_int_stat:0x%x cmdq_int_stat:0x%x",
 338                           vector0_int, ras_int, cmdq_int);
 339         }
 340
 341         hns3_clear_event_cause(hw, event_cause, clearval);
 342         /* Enable interrupt if it is not cause by reset */
 343         hns3_pf_enable_irq0(hw);
 344 }
 345
 346 static int
 347 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 348 {
 349 #define HNS3_VLAN_ID_OFFSET_STEP        160
 350 #define HNS3_VLAN_BYTE_SIZE             8
 351         struct hns3_vlan_filter_pf_cfg_cmd *req;
 352         struct hns3_hw *hw = &hns->hw;
 353         uint8_t vlan_offset_byte_val;
 354         struct hns3_cmd_desc desc;
 355         uint8_t vlan_offset_byte;
 356         uint8_t vlan_offset_base;
 357         int ret;
 358
 359         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 360
 361         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 362         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 363                            HNS3_VLAN_BYTE_SIZE;
 364         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 365
 366         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 367         req->vlan_offset = vlan_offset_base;
 368         req->vlan_cfg = on ? 0 : 1;
 369         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 370
 371         ret = hns3_cmd_send(hw, &desc, 1);
 372         if (ret)
 373                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 374                          vlan_id, ret);
 375
 376         return ret;
 377 }
 378
 379 static void
 380 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 381 {
 382         struct hns3_user_vlan_table *vlan_entry;
 383         struct hns3_pf *pf = &hns->pf;
 384
 385         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 386                 if (vlan_entry->vlan_id == vlan_id) {
 387                         if (vlan_entry->hd_tbl_status)
 388                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 389                         LIST_REMOVE(vlan_entry, next);
 390                         rte_free(vlan_entry);
 391                         break;
 392                 }
 393         }
 394 }
 395
 396 static void
 397 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 398                         bool writen_to_tbl)
 399 {
 400         struct hns3_user_vlan_table *vlan_entry;
 401         struct hns3_hw *hw = &hns->hw;
 402         struct hns3_pf *pf = &hns->pf;
 403
 404         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 405                 if (vlan_entry->vlan_id == vlan_id)
 406                         return;
 407         }
 408
 409         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 410         if (vlan_entry == NULL) {
 411                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 412                 return;
 413         }
 414
 415         vlan_entry->hd_tbl_status = writen_to_tbl;
 416         vlan_entry->vlan_id = vlan_id;
 417
 418         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 419 }
 420
 421 static int
 422 hns3_restore_vlan_table(struct hns3_adapter *hns)
 423 {
 424         struct hns3_user_vlan_table *vlan_entry;
 425         struct hns3_hw *hw = &hns->hw;
 426         struct hns3_pf *pf = &hns->pf;
 427         uint16_t vlan_id;
 428         int ret = 0;
 429
 430         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 431                 return hns3_vlan_pvid_configure(hns,
 432                                                 hw->port_base_vlan_cfg.pvid, 1);
 433
 434         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 435                 if (vlan_entry->hd_tbl_status) {
 436                         vlan_id = vlan_entry->vlan_id;
 437                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 438                         if (ret)
 439                                 break;
 440                 }
 441         }
 442
 443         return ret;
 444 }
 445
 446 static int
 447 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 448 {
 449         struct hns3_hw *hw = &hns->hw;
 450         bool writen_to_tbl = false;
 451         int ret = 0;
 452
 453         /*
 454          * When vlan filter is enabled, hardware regards packets without vlan
 455          * as packets with vlan 0. So, to receive packets without vlan, vlan id
 456          * 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
 457          */
 458         if (on == 0 && vlan_id == 0)
 459                 return 0;
 460
 461         /*
 462          * When port base vlan enabled, we use port base vlan as the vlan
 463          * filter condition. In this case, we don't update vlan filter table
 464          * when user add new vlan or remove exist vlan, just update the
 465          * vlan list. The vlan id in vlan list will be writen in vlan filter
 466          * table until port base vlan disabled
 467          */
 468         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 469                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 470                 writen_to_tbl = true;
 471         }
 472
 473         if (ret == 0) {
 474                 if (on)
 475                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 476                 else
 477                         hns3_rm_dev_vlan_table(hns, vlan_id);
 478         }
 479         return ret;
 480 }
 481
 482 static int
 483 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 484 {
 485         struct hns3_adapter *hns = dev->data->dev_private;
 486         struct hns3_hw *hw = &hns->hw;
 487         int ret;
 488
 489         rte_spinlock_lock(&hw->lock);
 490         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 491         rte_spinlock_unlock(&hw->lock);
 492         return ret;
 493 }
 494
 495 static int
 496 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 497                          uint16_t tpid)
 498 {
 499         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 500         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 501         struct hns3_hw *hw = &hns->hw;
 502         struct hns3_cmd_desc desc;
 503         int ret;
 504
 505         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 506              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 507                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 508                 return -EINVAL;
 509         }
 510
 511         if (tpid != RTE_ETHER_TYPE_VLAN) {
 512                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 513                 return -EINVAL;
 514         }
 515
 516         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 517         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 518
 519         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 520                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 521                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 522         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 523                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 524                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 525                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 526                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 527         }
 528
 529         ret = hns3_cmd_send(hw, &desc, 1);
 530         if (ret) {
 531                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 532                          ret);
 533                 return ret;
 534         }
 535
 536         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 537
 538         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 539         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 540         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 541
 542         ret = hns3_cmd_send(hw, &desc, 1);
 543         if (ret)
 544                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 545                          ret);
 546         return ret;
 547 }
 548
 549 static int
 550 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 551                    uint16_t tpid)
 552 {
 553         struct hns3_adapter *hns = dev->data->dev_private;
 554         struct hns3_hw *hw = &hns->hw;
 555         int ret;
 556
 557         rte_spinlock_lock(&hw->lock);
 558         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 559         rte_spinlock_unlock(&hw->lock);
 560         return ret;
 561 }
 562
 563 static int
 564 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 565                              struct hns3_rx_vtag_cfg *vcfg)
 566 {
 567         struct hns3_vport_vtag_rx_cfg_cmd *req;
 568         struct hns3_hw *hw = &hns->hw;
 569         struct hns3_cmd_desc desc;
 570         uint16_t vport_id;
 571         uint8_t bitmap;
 572         int ret;
 573
 574         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 575
 576         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 577         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 578                      vcfg->strip_tag1_en ? 1 : 0);
 579         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 580                      vcfg->strip_tag2_en ? 1 : 0);
 581         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 582                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 583         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 584                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 585
 586         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 587         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
 588                      vcfg->strip_tag1_discard_en ? 1 : 0);
 589         hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
 590                      vcfg->strip_tag2_discard_en ? 1 : 0);
 591         /*
 592          * In current version VF is not supported when PF is driven by DPDK
 593          * driver, just need to configure parameters for PF vport.
 594          */
 595         vport_id = HNS3_PF_FUNC_ID;
 596         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 597         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 598         req->vf_bitmap[req->vf_offset] = bitmap;
 599
 600         ret = hns3_cmd_send(hw, &desc, 1);
 601         if (ret)
 602                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 603         return ret;
 604 }
 605
 606 static void
 607 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 608                            struct hns3_rx_vtag_cfg *vcfg)
 609 {
 610         struct hns3_pf *pf = &hns->pf;
 611         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 612 }
 613
 614 static void
 615 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 616                            struct hns3_tx_vtag_cfg *vcfg)
 617 {
 618         struct hns3_pf *pf = &hns->pf;
 619         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 620 }
 621
 622 static int
 623 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 624 {
 625         struct hns3_rx_vtag_cfg rxvlan_cfg;
 626         struct hns3_hw *hw = &hns->hw;
 627         int ret;
 628
 629         if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 630                 rxvlan_cfg.strip_tag1_en = false;
 631                 rxvlan_cfg.strip_tag2_en = enable;
 632                 rxvlan_cfg.strip_tag2_discard_en = false;
 633         } else {
 634                 rxvlan_cfg.strip_tag1_en = enable;
 635                 rxvlan_cfg.strip_tag2_en = true;
 636                 rxvlan_cfg.strip_tag2_discard_en = true;
 637         }
 638
 639         rxvlan_cfg.strip_tag1_discard_en = false;
 640         rxvlan_cfg.vlan1_vlan_prionly = false;
 641         rxvlan_cfg.vlan2_vlan_prionly = false;
 642         rxvlan_cfg.rx_vlan_offload_en = enable;
 643
 644         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 645         if (ret) {
 646                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 647                 return ret;
 648         }
 649
 650         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 651
 652         return ret;
 653 }
 654
 655 static int
 656 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 657                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 658 {
 659         struct hns3_vlan_filter_ctrl_cmd *req;
 660         struct hns3_cmd_desc desc;
 661         int ret;
 662
 663         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 664
 665         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 666         req->vlan_type = vlan_type;
 667         req->vlan_fe = filter_en ? fe_type : 0;
 668         req->vf_id = vf_id;
 669
 670         ret = hns3_cmd_send(hw, &desc, 1);
 671         if (ret)
 672                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 673
 674         return ret;
 675 }
 676
 677 static int
 678 hns3_vlan_filter_init(struct hns3_adapter *hns)
 679 {
 680         struct hns3_hw *hw = &hns->hw;
 681         int ret;
 682
 683         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 684                                         HNS3_FILTER_FE_EGRESS, false,
 685                                         HNS3_PF_FUNC_ID);
 686         if (ret) {
 687                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 688                 return ret;
 689         }
 690
 691         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 692                                         HNS3_FILTER_FE_INGRESS, false,
 693                                         HNS3_PF_FUNC_ID);
 694         if (ret)
 695                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 696
 697         return ret;
 698 }
 699
 700 static int
 701 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 702 {
 703         struct hns3_hw *hw = &hns->hw;
 704         int ret;
 705
 706         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 707                                         HNS3_FILTER_FE_INGRESS, enable,
 708                                         HNS3_PF_FUNC_ID);
 709         if (ret)
 710                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 711                          enable ? "enable" : "disable", ret);
 712
 713         return ret;
 714 }
 715
 716 static int
 717 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 718 {
 719         struct hns3_adapter *hns = dev->data->dev_private;
 720         struct hns3_hw *hw = &hns->hw;
 721         struct rte_eth_rxmode *rxmode;
 722         unsigned int tmp_mask;
 723         bool enable;
 724         int ret = 0;
 725
 726         rte_spinlock_lock(&hw->lock);
 727         rxmode = &dev->data->dev_conf.rxmode;
 728         tmp_mask = (unsigned int)mask;
 729         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 730                 /* ignore vlan filter configuration during promiscuous mode */
 731                 if (!dev->data->promiscuous) {
 732                         /* Enable or disable VLAN filter */
 733                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 734                                  true : false;
 735
 736                         ret = hns3_enable_vlan_filter(hns, enable);
 737                         if (ret) {
 738                                 rte_spinlock_unlock(&hw->lock);
 739                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 740                                          enable ? "enable" : "disable", ret);
 741                                 return ret;
 742                         }
 743                 }
 744         }
 745
 746         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 747                 /* Enable or disable VLAN stripping */
 748                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 749                     true : false;
 750
 751                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 752                 if (ret) {
 753                         rte_spinlock_unlock(&hw->lock);
 754                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 755                                  enable ? "enable" : "disable", ret);
 756                         return ret;
 757                 }
 758         }
 759
 760         rte_spinlock_unlock(&hw->lock);
 761
 762         return ret;
 763 }
 764
 765 static int
 766 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 767                              struct hns3_tx_vtag_cfg *vcfg)
 768 {
 769         struct hns3_vport_vtag_tx_cfg_cmd *req;
 770         struct hns3_cmd_desc desc;
 771         struct hns3_hw *hw = &hns->hw;
 772         uint16_t vport_id;
 773         uint8_t bitmap;
 774         int ret;
 775
 776         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 777
 778         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 779         req->def_vlan_tag1 = vcfg->default_tag1;
 780         req->def_vlan_tag2 = vcfg->default_tag2;
 781         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 782                      vcfg->accept_tag1 ? 1 : 0);
 783         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 784                      vcfg->accept_untag1 ? 1 : 0);
 785         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 786                      vcfg->accept_tag2 ? 1 : 0);
 787         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 788                      vcfg->accept_untag2 ? 1 : 0);
 789         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 790                      vcfg->insert_tag1_en ? 1 : 0);
 791         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 792                      vcfg->insert_tag2_en ? 1 : 0);
 793         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 794
 795         /* firmwall will ignore this configuration for PCI_REVISION_ID_HIP08 */
 796         hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
 797                      vcfg->tag_shift_mode_en ? 1 : 0);
 798
 799         /*
 800          * In current version VF is not supported when PF is driven by DPDK
 801          * driver, just need to configure parameters for PF vport.
 802          */
 803         vport_id = HNS3_PF_FUNC_ID;
 804         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 805         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 806         req->vf_bitmap[req->vf_offset] = bitmap;
 807
 808         ret = hns3_cmd_send(hw, &desc, 1);
 809         if (ret)
 810                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 811
 812         return ret;
 813 }
 814
 815 static int
 816 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 817                      uint16_t pvid)
 818 {
 819         struct hns3_hw *hw = &hns->hw;
 820         struct hns3_tx_vtag_cfg txvlan_cfg;
 821         int ret;
 822
 823         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 824                 txvlan_cfg.accept_tag1 = true;
 825                 txvlan_cfg.insert_tag1_en = false;
 826                 txvlan_cfg.default_tag1 = 0;
 827         } else {
 828                 txvlan_cfg.accept_tag1 =
 829                         hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
 830                 txvlan_cfg.insert_tag1_en = true;
 831                 txvlan_cfg.default_tag1 = pvid;
 832         }
 833
 834         txvlan_cfg.accept_untag1 = true;
 835         txvlan_cfg.accept_tag2 = true;
 836         txvlan_cfg.accept_untag2 = true;
 837         txvlan_cfg.insert_tag2_en = false;
 838         txvlan_cfg.default_tag2 = 0;
 839         txvlan_cfg.tag_shift_mode_en = true;
 840
 841         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 842         if (ret) {
 843                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 844                          ret);
 845                 return ret;
 846         }
 847
 848         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 849         return ret;
 850 }
 851
 852
 853 static void
 854 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 855 {
 856         struct hns3_user_vlan_table *vlan_entry;
 857         struct hns3_pf *pf = &hns->pf;
 858
 859         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 860                 if (vlan_entry->hd_tbl_status) {
 861                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 862                         vlan_entry->hd_tbl_status = false;
 863                 }
 864         }
 865
 866         if (is_del_list) {
 867                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 868                 while (vlan_entry) {
 869                         LIST_REMOVE(vlan_entry, next);
 870                         rte_free(vlan_entry);
 871                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 872                 }
 873         }
 874 }
 875
 876 static void
 877 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 878 {
 879         struct hns3_user_vlan_table *vlan_entry;
 880         struct hns3_pf *pf = &hns->pf;
 881
 882         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 883                 if (!vlan_entry->hd_tbl_status) {
 884                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 885                         vlan_entry->hd_tbl_status = true;
 886                 }
 887         }
 888 }
 889
 890 static void
 891 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         hns3_rm_all_vlan_table(hns, true);
 897         if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
 898                 ret = hns3_set_port_vlan_filter(hns,
 899                                                 hw->port_base_vlan_cfg.pvid, 0);
 900                 if (ret) {
 901                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 902                                  ret);
 903                         return;
 904                 }
 905         }
 906 }
 907
 908 static int
 909 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 910                         uint16_t port_base_vlan_state, uint16_t new_pvid)
 911 {
 912         struct hns3_hw *hw = &hns->hw;
 913         uint16_t old_pvid;
 914         int ret;
 915
 916         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 917                 old_pvid = hw->port_base_vlan_cfg.pvid;
 918                 if (old_pvid != HNS3_INVALID_PVID) {
 919                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 920                         if (ret) {
 921                                 hns3_err(hw, "failed to remove old pvid %u, "
 922                                                 "ret = %d", old_pvid, ret);
 923                                 return ret;
 924                         }
 925                 }
 926
 927                 hns3_rm_all_vlan_table(hns, false);
 928                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
 929                 if (ret) {
 930                         hns3_err(hw, "failed to add new pvid %u, ret = %d",
 931                                         new_pvid, ret);
 932                         return ret;
 933                 }
 934         } else {
 935                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 936                 if (ret) {
 937                         hns3_err(hw, "failed to remove pvid %u, ret = %d",
 938                                         new_pvid, ret);
 939                         return ret;
 940                 }
 941
 942                 hns3_add_all_vlan_table(hns);
 943         }
 944         return 0;
 945 }
 946
 947 static int
 948 hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
 949 {
 950         struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
 951         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 952         bool rx_strip_en;
 953         int ret;
 954
 955         rx_strip_en = old_cfg->rx_vlan_offload_en;
 956         if (on) {
 957                 rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 958                 rx_vlan_cfg.strip_tag2_en = true;
 959                 rx_vlan_cfg.strip_tag2_discard_en = true;
 960         } else {
 961                 rx_vlan_cfg.strip_tag1_en = false;
 962                 rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 963                 rx_vlan_cfg.strip_tag2_discard_en = false;
 964         }
 965         rx_vlan_cfg.strip_tag1_discard_en = false;
 966         rx_vlan_cfg.vlan1_vlan_prionly = false;
 967         rx_vlan_cfg.vlan2_vlan_prionly = false;
 968         rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
 969
 970         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 971         if (ret)
 972                 return ret;
 973
 974         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 975         return ret;
 976 }
 977
 978 static int
 979 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 980 {
 981         struct hns3_hw *hw = &hns->hw;
 982         uint16_t port_base_vlan_state;
 983         int ret, err;
 984
 985         if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
 986                 if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
 987                         hns3_warn(hw, "Invalid operation! As current pvid set "
 988                                   "is %u, disable pvid %u is invalid",
 989                                   hw->port_base_vlan_cfg.pvid, pvid);
 990                 return 0;
 991         }
 992
 993         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 994                                     HNS3_PORT_BASE_VLAN_DISABLE;
 995         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 996         if (ret) {
 997                 hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
 998                          ret);
 999                 return ret;
1000         }
1001
1002         ret = hns3_en_pvid_strip(hns, on);
1003         if (ret) {
1004                 hns3_err(hw, "failed to config rx vlan strip for pvid, "
1005                          "ret = %d", ret);
1006                 goto pvid_vlan_strip_fail;
1007         }
1008
1009         if (pvid == HNS3_INVALID_PVID)
1010                 goto out;
1011         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
1012         if (ret) {
1013                 hns3_err(hw, "failed to update vlan filter entries, ret = %d",
1014                          ret);
1015                 goto vlan_filter_set_fail;
1016         }
1017
1018 out:
1019         hw->port_base_vlan_cfg.state = port_base_vlan_state;
1020         hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
1021         return ret;
1022
1023 vlan_filter_set_fail:
1024         err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
1025                                         HNS3_PORT_BASE_VLAN_ENABLE);
1026         if (err)
1027                 hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
1028
1029 pvid_vlan_strip_fail:
1030         err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
1031                                         hw->port_base_vlan_cfg.pvid);
1032         if (err)
1033                 hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
1034
1035         return ret;
1036 }
1037
1038 static int
1039 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1040 {
1041         struct hns3_adapter *hns = dev->data->dev_private;
1042         struct hns3_hw *hw = &hns->hw;
1043         bool pvid_en_state_change;
1044         uint16_t pvid_state;
1045         int ret;
1046
1047         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
1048                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
1049                          RTE_ETHER_MAX_VLAN_ID);
1050                 return -EINVAL;
1051         }
1052
1053         /*
1054          * If PVID configuration state change, should refresh the PVID
1055          * configuration state in struct hns3_tx_queue/hns3_rx_queue.
1056          */
1057         pvid_state = hw->port_base_vlan_cfg.state;
1058         if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
1059             (!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
1060                 pvid_en_state_change = false;
1061         else
1062                 pvid_en_state_change = true;
1063
1064         rte_spinlock_lock(&hw->lock);
1065         ret = hns3_vlan_pvid_configure(hns, pvid, on);
1066         rte_spinlock_unlock(&hw->lock);
1067         if (ret)
1068                 return ret;
1069         /*
1070          * Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
1071          * need be processed by PMD driver.
1072          */
1073         if (pvid_en_state_change &&
1074             hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
1075                 hns3_update_all_queues_pvid_proc_en(hw);
1076
1077         return 0;
1078 }
1079
1080 static int
1081 hns3_default_vlan_config(struct hns3_adapter *hns)
1082 {
1083         struct hns3_hw *hw = &hns->hw;
1084         int ret;
1085
1086         /*
1087          * When vlan filter is enabled, hardware regards packets without vlan
1088          * as packets with vlan 0. Therefore, if vlan 0 is not in the vlan
1089          * table, packets without vlan won't be received. So, add vlan 0 as
1090          * the default vlan.
1091          */
1092         ret = hns3_vlan_filter_configure(hns, 0, 1);
1093         if (ret)
1094                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
1095         return ret;
1096 }
1097
1098 static int
1099 hns3_init_vlan_config(struct hns3_adapter *hns)
1100 {
1101         struct hns3_hw *hw = &hns->hw;
1102         int ret;
1103
1104         /*
1105          * This function can be called in the initialization and reset process,
1106          * when in reset process, it means that hardware had been reseted
1107          * successfully and we need to restore the hardware configuration to
1108          * ensure that the hardware configuration remains unchanged before and
1109          * after reset.
1110          */
1111         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1112                 hw->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
1113                 hw->port_base_vlan_cfg.pvid = HNS3_INVALID_PVID;
1114         }
1115
1116         ret = hns3_vlan_filter_init(hns);
1117         if (ret) {
1118                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
1119                 return ret;
1120         }
1121
1122         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
1123                                        RTE_ETHER_TYPE_VLAN);
1124         if (ret) {
1125                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
1126                 return ret;
1127         }
1128
1129         /*
1130          * When in the reinit dev stage of the reset process, the following
1131          * vlan-related configurations may differ from those at initialization,
1132          * we will restore configurations to hardware in hns3_restore_vlan_table
1133          * and hns3_restore_vlan_conf later.
1134          */
1135         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
1136                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVALID_PVID, 0);
1137                 if (ret) {
1138                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
1139                         return ret;
1140                 }
1141
1142                 ret = hns3_en_hw_strip_rxvtag(hns, false);
1143                 if (ret) {
1144                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
1145                                  ret);
1146                         return ret;
1147                 }
1148         }
1149
1150         return hns3_default_vlan_config(hns);
1151 }
1152
1153 static int
1154 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1155 {
1156         struct hns3_pf *pf = &hns->pf;
1157         struct hns3_hw *hw = &hns->hw;
1158         uint64_t offloads;
1159         bool enable;
1160         int ret;
1161
1162         if (!hw->data->promiscuous) {
1163                 /* restore vlan filter states */
1164                 offloads = hw->data->dev_conf.rxmode.offloads;
1165                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1166                 ret = hns3_enable_vlan_filter(hns, enable);
1167                 if (ret) {
1168                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1169                                  "ret = %d", ret);
1170                         return ret;
1171                 }
1172         }
1173
1174         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1175         if (ret) {
1176                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1177                 return ret;
1178         }
1179
1180         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1181         if (ret)
1182                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1183
1184         return ret;
1185 }
1186
1187 static int
1188 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1189 {
1190         struct hns3_adapter *hns = dev->data->dev_private;
1191         struct rte_eth_dev_data *data = dev->data;
1192         struct rte_eth_txmode *txmode;
1193         struct hns3_hw *hw = &hns->hw;
1194         int mask;
1195         int ret;
1196
1197         txmode = &data->dev_conf.txmode;
1198         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1199                 hns3_warn(hw,
1200                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1201                           "configuration is not supported! Ignore these two "
1202                           "parameters: hw_vlan_reject_tagged(%u), "
1203                           "hw_vlan_reject_untagged(%u)",
1204                           txmode->hw_vlan_reject_tagged,
1205                           txmode->hw_vlan_reject_untagged);
1206
1207         /* Apply vlan offload setting */
1208         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1209         ret = hns3_vlan_offload_set(dev, mask);
1210         if (ret) {
1211                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1212                          ret);
1213                 return ret;
1214         }
1215
1216         /*
1217          * If pvid config is not set in rte_eth_conf, driver needn't to set
1218          * VLAN pvid related configuration to hardware.
1219          */
1220         if (txmode->pvid == 0 && txmode->hw_vlan_insert_pvid == 0)
1221                 return 0;
1222
1223         /* Apply pvid setting */
1224         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1225                                  txmode->hw_vlan_insert_pvid);
1226         if (ret)
1227                 hns3_err(hw, "dev config vlan pvid(%u) failed, ret = %d",
1228                          txmode->pvid, ret);
1229
1230         return ret;
1231 }
1232
1233 static int
1234 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1235                 unsigned int tso_mss_max)
1236 {
1237         struct hns3_cfg_tso_status_cmd *req;
1238         struct hns3_cmd_desc desc;
1239         uint16_t tso_mss;
1240
1241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1242
1243         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1244
1245         tso_mss = 0;
1246         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1247                        tso_mss_min);
1248         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1249
1250         tso_mss = 0;
1251         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1252                        tso_mss_max);
1253         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1254
1255         return hns3_cmd_send(hw, &desc, 1);
1256 }
1257
1258 static int
1259 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1260                    uint16_t *allocated_size, bool is_alloc)
1261 {
1262         struct hns3_umv_spc_alc_cmd *req;
1263         struct hns3_cmd_desc desc;
1264         int ret;
1265
1266         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1267         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1268         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1269         req->space_size = rte_cpu_to_le_32(space_size);
1270
1271         ret = hns3_cmd_send(hw, &desc, 1);
1272         if (ret) {
1273                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1274                              is_alloc ? "allocate" : "free", ret);
1275                 return ret;
1276         }
1277
1278         if (is_alloc && allocated_size)
1279                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 hns3_init_umv_space(struct hns3_hw *hw)
1286 {
1287         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1288         struct hns3_pf *pf = &hns->pf;
1289         uint16_t allocated_size = 0;
1290         int ret;
1291
1292         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1293                                  true);
1294         if (ret)
1295                 return ret;
1296
1297         if (allocated_size < pf->wanted_umv_size)
1298                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1299                              pf->wanted_umv_size, allocated_size);
1300
1301         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1302                                                 pf->wanted_umv_size;
1303         pf->used_umv_size = 0;
1304         return 0;
1305 }
1306
1307 static int
1308 hns3_uninit_umv_space(struct hns3_hw *hw)
1309 {
1310         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1311         struct hns3_pf *pf = &hns->pf;
1312         int ret;
1313
1314         if (pf->max_umv_size == 0)
1315                 return 0;
1316
1317         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1318         if (ret)
1319                 return ret;
1320
1321         pf->max_umv_size = 0;
1322
1323         return 0;
1324 }
1325
1326 static bool
1327 hns3_is_umv_space_full(struct hns3_hw *hw)
1328 {
1329         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1330         struct hns3_pf *pf = &hns->pf;
1331         bool is_full;
1332
1333         is_full = (pf->used_umv_size >= pf->max_umv_size);
1334
1335         return is_full;
1336 }
1337
1338 static void
1339 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1340 {
1341         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1342         struct hns3_pf *pf = &hns->pf;
1343
1344         if (is_free) {
1345                 if (pf->used_umv_size > 0)
1346                         pf->used_umv_size--;
1347         } else
1348                 pf->used_umv_size++;
1349 }
1350
1351 static void
1352 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1353                       const uint8_t *addr, bool is_mc)
1354 {
1355         const unsigned char *mac_addr = addr;
1356         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1357                             ((uint32_t)mac_addr[2] << 16) |
1358                             ((uint32_t)mac_addr[1] << 8) |
1359                             (uint32_t)mac_addr[0];
1360         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1361
1362         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1363         if (is_mc) {
1364                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1365                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1366                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1367         }
1368
1369         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1370         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1371 }
1372
1373 static int
1374 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1375                              uint8_t resp_code,
1376                              enum hns3_mac_vlan_tbl_opcode op)
1377 {
1378         if (cmdq_resp) {
1379                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1380                          cmdq_resp);
1381                 return -EIO;
1382         }
1383
1384         if (op == HNS3_MAC_VLAN_ADD) {
1385                 if (resp_code == 0 || resp_code == 1) {
1386                         return 0;
1387                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1388                         hns3_err(hw, "add mac addr failed for uc_overflow");
1389                         return -ENOSPC;
1390                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1391                         hns3_err(hw, "add mac addr failed for mc_overflow");
1392                         return -ENOSPC;
1393                 }
1394
1395                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1396                          resp_code);
1397                 return -EIO;
1398         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1399                 if (resp_code == 0) {
1400                         return 0;
1401                 } else if (resp_code == 1) {
1402                         hns3_dbg(hw, "remove mac addr failed for miss");
1403                         return -ENOENT;
1404                 }
1405
1406                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1407                          resp_code);
1408                 return -EIO;
1409         } else if (op == HNS3_MAC_VLAN_LKUP) {
1410                 if (resp_code == 0) {
1411                         return 0;
1412                 } else if (resp_code == 1) {
1413                         hns3_dbg(hw, "lookup mac addr failed for miss");
1414                         return -ENOENT;
1415                 }
1416
1417                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1418                          resp_code);
1419                 return -EIO;
1420         }
1421
1422         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1423                  op);
1424
1425         return -EINVAL;
1426 }
1427
1428 static int
1429 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1430                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1431                          struct hns3_cmd_desc *desc, bool is_mc)
1432 {
1433         uint8_t resp_code;
1434         uint16_t retval;
1435         int ret;
1436
1437         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1438         if (is_mc) {
1439                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1440                 memcpy(desc[0].data, req,
1441                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1442                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1443                                           true);
1444                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1445                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1446                                           true);
1447                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1448         } else {
1449                 memcpy(desc[0].data, req,
1450                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1451                 ret = hns3_cmd_send(hw, desc, 1);
1452         }
1453         if (ret) {
1454                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1455                          ret);
1456                 return ret;
1457         }
1458         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1459         retval = rte_le_to_cpu_16(desc[0].retval);
1460
1461         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1462                                             HNS3_MAC_VLAN_LKUP);
1463 }
1464
1465 static int
1466 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1467                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1468                       struct hns3_cmd_desc *mc_desc)
1469 {
1470         uint8_t resp_code;
1471         uint16_t retval;
1472         int cfg_status;
1473         int ret;
1474
1475         if (mc_desc == NULL) {
1476                 struct hns3_cmd_desc desc;
1477
1478                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1479                 memcpy(desc.data, req,
1480                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1481                 ret = hns3_cmd_send(hw, &desc, 1);
1482                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1483                 retval = rte_le_to_cpu_16(desc.retval);
1484
1485                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1486                                                           HNS3_MAC_VLAN_ADD);
1487         } else {
1488                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1489                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1490                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1491                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1492                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1493                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1494                 memcpy(mc_desc[0].data, req,
1495                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1496                 mc_desc[0].retval = 0;
1497                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1498                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1499                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1500
1501                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1502                                                           HNS3_MAC_VLAN_ADD);
1503         }
1504
1505         if (ret) {
1506                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1507                 return ret;
1508         }
1509
1510         return cfg_status;
1511 }
1512
1513 static int
1514 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1515                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1516 {
1517         struct hns3_cmd_desc desc;
1518         uint8_t resp_code;
1519         uint16_t retval;
1520         int ret;
1521
1522         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1523
1524         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1525
1526         ret = hns3_cmd_send(hw, &desc, 1);
1527         if (ret) {
1528                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1529                 return ret;
1530         }
1531         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1532         retval = rte_le_to_cpu_16(desc.retval);
1533
1534         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1535                                             HNS3_MAC_VLAN_REMOVE);
1536 }
1537
1538 static int
1539 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1540 {
1541         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1542         struct hns3_mac_vlan_tbl_entry_cmd req;
1543         struct hns3_pf *pf = &hns->pf;
1544         struct hns3_cmd_desc desc[3];
1545         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1546         uint16_t egress_port = 0;
1547         uint8_t vf_id;
1548         int ret;
1549
1550         /* check if mac addr is valid */
1551         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1552                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1553                                       mac_addr);
1554                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1555                          mac_str);
1556                 return -EINVAL;
1557         }
1558
1559         memset(&req, 0, sizeof(req));
1560
1561         /*
1562          * In current version VF is not supported when PF is driven by DPDK
1563          * driver, just need to configure parameters for PF vport.
1564          */
1565         vf_id = HNS3_PF_FUNC_ID;
1566         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1567                        HNS3_MAC_EPORT_VFID_S, vf_id);
1568
1569         req.egress_port = rte_cpu_to_le_16(egress_port);
1570
1571         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1572
1573         /*
1574          * Lookup the mac address in the mac_vlan table, and add
1575          * it if the entry is inexistent. Repeated unicast entry
1576          * is not allowed in the mac vlan table.
1577          */
1578         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, false);
1579         if (ret == -ENOENT) {
1580                 if (!hns3_is_umv_space_full(hw)) {
1581                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1582                         if (!ret)
1583                                 hns3_update_umv_space(hw, false);
1584                         return ret;
1585                 }
1586
1587                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1588
1589                 return -ENOSPC;
1590         }
1591
1592         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1593
1594         /* check if we just hit the duplicate */
1595         if (ret == 0) {
1596                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1597                 return 0;
1598         }
1599
1600         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1601                  mac_str);
1602
1603         return ret;
1604 }
1605
1606 static int
1607 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1608 {
1609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1610         struct rte_ether_addr *addr;
1611         int ret;
1612         int i;
1613
1614         for (i = 0; i < hw->mc_addrs_num; i++) {
1615                 addr = &hw->mc_addrs[i];
1616                 /* Check if there are duplicate addresses */
1617                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1618                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1619                                               addr);
1620                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1621                                  "(%s) is added by the set_mc_mac_addr_list "
1622                                  "API", mac_str);
1623                         return -EINVAL;
1624                 }
1625         }
1626
1627         ret = hns3_add_mc_addr(hw, mac_addr);
1628         if (ret) {
1629                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1630                                       mac_addr);
1631                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1632                          mac_str, ret);
1633         }
1634         return ret;
1635 }
1636
1637 static int
1638 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1639 {
1640         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1641         int ret;
1642
1643         ret = hns3_remove_mc_addr(hw, mac_addr);
1644         if (ret) {
1645                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1646                                       mac_addr);
1647                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1648                          mac_str, ret);
1649         }
1650         return ret;
1651 }
1652
1653 static int
1654 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1655                   uint32_t idx, __rte_unused uint32_t pool)
1656 {
1657         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1659         int ret;
1660
1661         rte_spinlock_lock(&hw->lock);
1662
1663         /*
1664          * In hns3 network engine adding UC and MC mac address with different
1665          * commands with firmware. We need to determine whether the input
1666          * address is a UC or a MC address to call different commands.
1667          * By the way, it is recommended calling the API function named
1668          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1669          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1670          * may affect the specifications of UC mac addresses.
1671          */
1672         if (rte_is_multicast_ether_addr(mac_addr))
1673                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1674         else
1675                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1676
1677         if (ret) {
1678                 rte_spinlock_unlock(&hw->lock);
1679                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1680                                       mac_addr);
1681                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1682                          ret);
1683                 return ret;
1684         }
1685
1686         if (idx == 0)
1687                 hw->mac.default_addr_setted = true;
1688         rte_spinlock_unlock(&hw->lock);
1689
1690         return ret;
1691 }
1692
1693 static int
1694 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1695 {
1696         struct hns3_mac_vlan_tbl_entry_cmd req;
1697         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1698         int ret;
1699
1700         /* check if mac addr is valid */
1701         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1702                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1703                                       mac_addr);
1704                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1705                          mac_str);
1706                 return -EINVAL;
1707         }
1708
1709         memset(&req, 0, sizeof(req));
1710         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1711         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1712         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1713         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1714                 return 0;
1715         else if (ret == 0)
1716                 hns3_update_umv_space(hw, true);
1717
1718         return ret;
1719 }
1720
1721 static void
1722 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1723 {
1724         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1725         /* index will be checked by upper level rte interface */
1726         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1727         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1728         int ret;
1729
1730         rte_spinlock_lock(&hw->lock);
1731
1732         if (rte_is_multicast_ether_addr(mac_addr))
1733                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1734         else
1735                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1736         rte_spinlock_unlock(&hw->lock);
1737         if (ret) {
1738                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1739                                       mac_addr);
1740                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1741                          ret);
1742         }
1743 }
1744
1745 static int
1746 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1747                           struct rte_ether_addr *mac_addr)
1748 {
1749         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750         struct rte_ether_addr *oaddr;
1751         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1752         bool default_addr_setted;
1753         bool rm_succes = false;
1754         int ret, ret_val;
1755
1756         /*
1757          * It has been guaranteed that input parameter named mac_addr is valid
1758          * address in the rte layer of DPDK framework.
1759          */
1760         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1761         default_addr_setted = hw->mac.default_addr_setted;
1762         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1763                 return 0;
1764
1765         rte_spinlock_lock(&hw->lock);
1766         if (default_addr_setted) {
1767                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1768                 if (ret) {
1769                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1770                                               oaddr);
1771                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1772                                   mac_str, ret);
1773                         rm_succes = false;
1774                 } else
1775                         rm_succes = true;
1776         }
1777
1778         ret = hns3_add_uc_addr_common(hw, mac_addr);
1779         if (ret) {
1780                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1781                                       mac_addr);
1782                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1783                 goto err_add_uc_addr;
1784         }
1785
1786         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1787         if (ret) {
1788                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1789                 goto err_pause_addr_cfg;
1790         }
1791
1792         rte_ether_addr_copy(mac_addr,
1793                             (struct rte_ether_addr *)hw->mac.mac_addr);
1794         hw->mac.default_addr_setted = true;
1795         rte_spinlock_unlock(&hw->lock);
1796
1797         return 0;
1798
1799 err_pause_addr_cfg:
1800         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1801         if (ret_val) {
1802                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1803                                       mac_addr);
1804                 hns3_warn(hw,
1805                           "Failed to roll back to del setted mac addr(%s): %d",
1806                           mac_str, ret_val);
1807         }
1808
1809 err_add_uc_addr:
1810         if (rm_succes) {
1811                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1812                 if (ret_val) {
1813                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1814                                               oaddr);
1815                         hns3_warn(hw,
1816                                   "Failed to restore old uc mac addr(%s): %d",
1817                                   mac_str, ret_val);
1818                         hw->mac.default_addr_setted = false;
1819                 }
1820         }
1821         rte_spinlock_unlock(&hw->lock);
1822
1823         return ret;
1824 }
1825
1826 static int
1827 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1828 {
1829         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1830         struct hns3_hw *hw = &hns->hw;
1831         struct rte_ether_addr *addr;
1832         int err = 0;
1833         int ret;
1834         int i;
1835
1836         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1837                 addr = &hw->data->mac_addrs[i];
1838                 if (rte_is_zero_ether_addr(addr))
1839                         continue;
1840                 if (rte_is_multicast_ether_addr(addr))
1841                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1842                               hns3_add_mc_addr(hw, addr);
1843                 else
1844                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1845                               hns3_add_uc_addr_common(hw, addr);
1846
1847                 if (ret) {
1848                         err = ret;
1849                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1850                                               addr);
1851                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1852                                  "ret = %d.", del ? "remove" : "restore",
1853                                  mac_str, i, ret);
1854                 }
1855         }
1856         return err;
1857 }
1858
1859 static void
1860 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1861 {
1862 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1863         uint8_t word_num;
1864         uint8_t bit_num;
1865
1866         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1867                 word_num = vfid / 32;
1868                 bit_num = vfid % 32;
1869                 if (clr)
1870                         desc[1].data[word_num] &=
1871                             rte_cpu_to_le_32(~(1UL << bit_num));
1872                 else
1873                         desc[1].data[word_num] |=
1874                             rte_cpu_to_le_32(1UL << bit_num);
1875         } else {
1876                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1877                 bit_num = vfid % 32;
1878                 if (clr)
1879                         desc[2].data[word_num] &=
1880                             rte_cpu_to_le_32(~(1UL << bit_num));
1881                 else
1882                         desc[2].data[word_num] |=
1883                             rte_cpu_to_le_32(1UL << bit_num);
1884         }
1885 }
1886
1887 static int
1888 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1889 {
1890         struct hns3_mac_vlan_tbl_entry_cmd req;
1891         struct hns3_cmd_desc desc[3];
1892         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1893         uint8_t vf_id;
1894         int ret;
1895
1896         /* Check if mac addr is valid */
1897         if (!rte_is_multicast_ether_addr(mac_addr)) {
1898                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1899                                       mac_addr);
1900                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1901                          mac_str);
1902                 return -EINVAL;
1903         }
1904
1905         memset(&req, 0, sizeof(req));
1906         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1907         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1908         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1909         if (ret) {
1910                 /* This mac addr do not exist, add new entry for it */
1911                 memset(desc[0].data, 0, sizeof(desc[0].data));
1912                 memset(desc[1].data, 0, sizeof(desc[0].data));
1913                 memset(desc[2].data, 0, sizeof(desc[0].data));
1914         }
1915
1916         /*
1917          * In current version VF is not supported when PF is driven by DPDK
1918          * driver, just need to configure parameters for PF vport.
1919          */
1920         vf_id = HNS3_PF_FUNC_ID;
1921         hns3_update_desc_vfid(desc, vf_id, false);
1922         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1923         if (ret) {
1924                 if (ret == -ENOSPC)
1925                         hns3_err(hw, "mc mac vlan table is full");
1926                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1927                                       mac_addr);
1928                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1929         }
1930
1931         return ret;
1932 }
1933
1934 static int
1935 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1936 {
1937         struct hns3_mac_vlan_tbl_entry_cmd req;
1938         struct hns3_cmd_desc desc[3];
1939         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1940         uint8_t vf_id;
1941         int ret;
1942
1943         /* Check if mac addr is valid */
1944         if (!rte_is_multicast_ether_addr(mac_addr)) {
1945                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1946                                       mac_addr);
1947                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1948                          mac_str);
1949                 return -EINVAL;
1950         }
1951
1952         memset(&req, 0, sizeof(req));
1953         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1954         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1955         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1956         if (ret == 0) {
1957                 /*
1958                  * This mac addr exist, remove this handle's VFID for it.
1959                  * In current version VF is not supported when PF is driven by
1960                  * DPDK driver, just need to configure parameters for PF vport.
1961                  */
1962                 vf_id = HNS3_PF_FUNC_ID;
1963                 hns3_update_desc_vfid(desc, vf_id, true);
1964
1965                 /* All the vfid is zero, so need to delete this entry */
1966                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1967         } else if (ret == -ENOENT) {
1968                 /* This mac addr doesn't exist. */
1969                 return 0;
1970         }
1971
1972         if (ret) {
1973                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1974                                       mac_addr);
1975                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1976         }
1977
1978         return ret;
1979 }
1980
1981 static int
1982 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1983                            struct rte_ether_addr *mc_addr_set,
1984                            uint32_t nb_mc_addr)
1985 {
1986         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1987         struct rte_ether_addr *addr;
1988         uint32_t i;
1989         uint32_t j;
1990
1991         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1992                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
1993                          "invalid. valid range: 0~%d",
1994                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1995                 return -EINVAL;
1996         }
1997
1998         /* Check if input mac addresses are valid */
1999         for (i = 0; i < nb_mc_addr; i++) {
2000                 addr = &mc_addr_set[i];
2001                 if (!rte_is_multicast_ether_addr(addr)) {
2002                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2003                                               addr);
2004                         hns3_err(hw,
2005                                  "failed to set mc mac addr, addr(%s) invalid.",
2006                                  mac_str);
2007                         return -EINVAL;
2008                 }
2009
2010                 /* Check if there are duplicate addresses */
2011                 for (j = i + 1; j < nb_mc_addr; j++) {
2012                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2013                                 hns3_ether_format_addr(mac_str,
2014                                                       RTE_ETHER_ADDR_FMT_SIZE,
2015                                                       addr);
2016                                 hns3_err(hw, "failed to set mc mac addr, "
2017                                          "addrs invalid. two same addrs(%s).",
2018                                          mac_str);
2019                                 return -EINVAL;
2020                         }
2021                 }
2022
2023                 /*
2024                  * Check if there are duplicate addresses between mac_addrs
2025                  * and mc_addr_set
2026                  */
2027                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
2028                         if (rte_is_same_ether_addr(addr,
2029                                                    &hw->data->mac_addrs[j])) {
2030                                 hns3_ether_format_addr(mac_str,
2031                                                       RTE_ETHER_ADDR_FMT_SIZE,
2032                                                       addr);
2033                                 hns3_err(hw, "failed to set mc mac addr, "
2034                                          "addrs invalid. addrs(%s) has already "
2035                                          "configured in mac_addr add API",
2036                                          mac_str);
2037                                 return -EINVAL;
2038                         }
2039                 }
2040         }
2041
2042         return 0;
2043 }
2044
2045 static void
2046 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
2047                            struct rte_ether_addr *mc_addr_set,
2048                            int mc_addr_num,
2049                            struct rte_ether_addr *reserved_addr_list,
2050                            int *reserved_addr_num,
2051                            struct rte_ether_addr *add_addr_list,
2052                            int *add_addr_num,
2053                            struct rte_ether_addr *rm_addr_list,
2054                            int *rm_addr_num)
2055 {
2056         struct rte_ether_addr *addr;
2057         int current_addr_num;
2058         int reserved_num = 0;
2059         int add_num = 0;
2060         int rm_num = 0;
2061         int num;
2062         int i;
2063         int j;
2064         bool same_addr;
2065
2066         /* Calculate the mc mac address list that should be removed */
2067         current_addr_num = hw->mc_addrs_num;
2068         for (i = 0; i < current_addr_num; i++) {
2069                 addr = &hw->mc_addrs[i];
2070                 same_addr = false;
2071                 for (j = 0; j < mc_addr_num; j++) {
2072                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
2073                                 same_addr = true;
2074                                 break;
2075                         }
2076                 }
2077
2078                 if (!same_addr) {
2079                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
2080                         rm_num++;
2081                 } else {
2082                         rte_ether_addr_copy(addr,
2083                                             &reserved_addr_list[reserved_num]);
2084                         reserved_num++;
2085                 }
2086         }
2087
2088         /* Calculate the mc mac address list that should be added */
2089         for (i = 0; i < mc_addr_num; i++) {
2090                 addr = &mc_addr_set[i];
2091                 same_addr = false;
2092                 for (j = 0; j < current_addr_num; j++) {
2093                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
2094                                 same_addr = true;
2095                                 break;
2096                         }
2097                 }
2098
2099                 if (!same_addr) {
2100                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
2101                         add_num++;
2102                 }
2103         }
2104
2105         /* Reorder the mc mac address list maintained by driver */
2106         for (i = 0; i < reserved_num; i++)
2107                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
2108
2109         for (i = 0; i < rm_num; i++) {
2110                 num = reserved_num + i;
2111                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
2112         }
2113
2114         *reserved_addr_num = reserved_num;
2115         *add_addr_num = add_num;
2116         *rm_addr_num = rm_num;
2117 }
2118
2119 static int
2120 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
2121                           struct rte_ether_addr *mc_addr_set,
2122                           uint32_t nb_mc_addr)
2123 {
2124         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
2126         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
2127         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
2128         struct rte_ether_addr *addr;
2129         int reserved_addr_num;
2130         int add_addr_num;
2131         int rm_addr_num;
2132         int mc_addr_num;
2133         int num;
2134         int ret;
2135         int i;
2136
2137         /* Check if input parameters are valid */
2138         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2139         if (ret)
2140                 return ret;
2141
2142         rte_spinlock_lock(&hw->lock);
2143
2144         /*
2145          * Calculate the mc mac address lists those should be removed and be
2146          * added, Reorder the mc mac address list maintained by driver.
2147          */
2148         mc_addr_num = (int)nb_mc_addr;
2149         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2150                                    reserved_addr_list, &reserved_addr_num,
2151                                    add_addr_list, &add_addr_num,
2152                                    rm_addr_list, &rm_addr_num);
2153
2154         /* Remove mc mac addresses */
2155         for (i = 0; i < rm_addr_num; i++) {
2156                 num = rm_addr_num - i - 1;
2157                 addr = &rm_addr_list[num];
2158                 ret = hns3_remove_mc_addr(hw, addr);
2159                 if (ret) {
2160                         rte_spinlock_unlock(&hw->lock);
2161                         return ret;
2162                 }
2163                 hw->mc_addrs_num--;
2164         }
2165
2166         /* Add mc mac addresses */
2167         for (i = 0; i < add_addr_num; i++) {
2168                 addr = &add_addr_list[i];
2169                 ret = hns3_add_mc_addr(hw, addr);
2170                 if (ret) {
2171                         rte_spinlock_unlock(&hw->lock);
2172                         return ret;
2173                 }
2174
2175                 num = reserved_addr_num + i;
2176                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2177                 hw->mc_addrs_num++;
2178         }
2179         rte_spinlock_unlock(&hw->lock);
2180
2181         return 0;
2182 }
2183
2184 static int
2185 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2186 {
2187         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2188         struct hns3_hw *hw = &hns->hw;
2189         struct rte_ether_addr *addr;
2190         int err = 0;
2191         int ret;
2192         int i;
2193
2194         for (i = 0; i < hw->mc_addrs_num; i++) {
2195                 addr = &hw->mc_addrs[i];
2196                 if (!rte_is_multicast_ether_addr(addr))
2197                         continue;
2198                 if (del)
2199                         ret = hns3_remove_mc_addr(hw, addr);
2200                 else
2201                         ret = hns3_add_mc_addr(hw, addr);
2202                 if (ret) {
2203                         err = ret;
2204                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2205                                               addr);
2206                         hns3_dbg(hw, "%s mc mac addr: %s failed for pf: ret = %d",
2207                                  del ? "Remove" : "Restore", mac_str, ret);
2208                 }
2209         }
2210         return err;
2211 }
2212
2213 static int
2214 hns3_check_mq_mode(struct rte_eth_dev *dev)
2215 {
2216         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2217         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2218         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2221         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2222         uint8_t num_tc;
2223         int max_tc = 0;
2224         int i;
2225
2226         if ((rx_mq_mode & ETH_MQ_RX_VMDQ_FLAG) ||
2227             (tx_mq_mode == ETH_MQ_TX_VMDQ_DCB ||
2228              tx_mq_mode == ETH_MQ_TX_VMDQ_ONLY)) {
2229                 hns3_err(hw, "VMDQ is not supported, rx_mq_mode = %d, tx_mq_mode = %d.",
2230                          rx_mq_mode, tx_mq_mode);
2231                 return -EOPNOTSUPP;
2232         }
2233
2234         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2235         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2236         if (rx_mq_mode & ETH_MQ_RX_DCB_FLAG) {
2237                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2238                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2239                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2240                         return -EINVAL;
2241                 }
2242
2243                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2244                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2245                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2246                                  "nb_tcs(%d) != %d or %d in rx direction.",
2247                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2248                         return -EINVAL;
2249                 }
2250
2251                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2252                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2253                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2254                         return -EINVAL;
2255                 }
2256
2257                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2258                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2259                                 hns3_err(hw, "dcb_tc[%d] = %u in rx direction, "
2260                                          "is not equal to one in tx direction.",
2261                                          i, dcb_rx_conf->dcb_tc[i]);
2262                                 return -EINVAL;
2263                         }
2264                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2265                                 max_tc = dcb_rx_conf->dcb_tc[i];
2266                 }
2267
2268                 num_tc = max_tc + 1;
2269                 if (num_tc > dcb_rx_conf->nb_tcs) {
2270                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2271                                  num_tc, dcb_rx_conf->nb_tcs);
2272                         return -EINVAL;
2273                 }
2274         }
2275
2276         return 0;
2277 }
2278
2279 static int
2280 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2281 {
2282         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283
2284         if (!hns3_dev_dcb_supported(hw)) {
2285                 hns3_err(hw, "this port does not support dcb configurations.");
2286                 return -EOPNOTSUPP;
2287         }
2288
2289         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2290                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2291                 return -EOPNOTSUPP;
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int
2298 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint16_t vector_id, bool en,
2299                            enum hns3_ring_type queue_type, uint16_t queue_id)
2300 {
2301         struct hns3_cmd_desc desc;
2302         struct hns3_ctrl_vector_chain_cmd *req =
2303                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2304         enum hns3_opcode_type op;
2305         uint16_t tqp_type_and_id = 0;
2306         uint16_t type;
2307         uint16_t gl;
2308         int ret;
2309
2310         op = en ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2311         hns3_cmd_setup_basic_desc(&desc, op, false);
2312         req->int_vector_id = hns3_get_field(vector_id, HNS3_TQP_INT_ID_L_M,
2313                                               HNS3_TQP_INT_ID_L_S);
2314         req->int_vector_id_h = hns3_get_field(vector_id, HNS3_TQP_INT_ID_H_M,
2315                                               HNS3_TQP_INT_ID_H_S);
2316
2317         if (queue_type == HNS3_RING_TYPE_RX)
2318                 gl = HNS3_RING_GL_RX;
2319         else
2320                 gl = HNS3_RING_GL_TX;
2321
2322         type = queue_type;
2323
2324         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2325                        type);
2326         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2327         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2328                        gl);
2329         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2330         req->int_cause_num = 1;
2331         ret = hns3_cmd_send(hw, &desc, 1);
2332         if (ret) {
2333                 hns3_err(hw, "%s TQP %u fail, vector_id = %u, ret = %d.",
2334                          en ? "Map" : "Unmap", queue_id, vector_id, ret);
2335                 return ret;
2336         }
2337
2338         return 0;
2339 }
2340
2341 static int
2342 hns3_init_ring_with_vector(struct hns3_hw *hw)
2343 {
2344         uint16_t vec;
2345         int ret;
2346         int i;
2347
2348         /*
2349          * In hns3 network engine, vector 0 is always the misc interrupt of this
2350          * function, vector 1~N can be used respectively for the queues of the
2351          * function. Tx and Rx queues with the same number share the interrupt
2352          * vector. In the initialization clearing the all hardware mapping
2353          * relationship configurations between queues and interrupt vectors is
2354          * needed, so some error caused by the residual configurations, such as
2355          * the unexpected Tx interrupt, can be avoid.
2356          */
2357         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2358         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
2359                 vec = vec - 1; /* the last interrupt is reserved */
2360         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
2361         for (i = 0; i < hw->intr_tqps_num; i++) {
2362                 /*
2363                  * Set gap limiter/rate limiter/quanity limiter algorithm
2364                  * configuration for interrupt coalesce of queue's interrupt.
2365                  */
2366                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2367                                        HNS3_TQP_INTR_GL_DEFAULT);
2368                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2369                                        HNS3_TQP_INTR_GL_DEFAULT);
2370                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2371                 /*
2372                  * QL(quantity limiter) is not used currently, just set 0 to
2373                  * close it.
2374                  */
2375                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
2376
2377                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2378                                                  HNS3_RING_TYPE_TX, i);
2379                 if (ret) {
2380                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2381                                           "vector: %u, ret=%d", i, vec, ret);
2382                         return ret;
2383                 }
2384
2385                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2386                                                  HNS3_RING_TYPE_RX, i);
2387                 if (ret) {
2388                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2389                                           "vector: %u, ret=%d", i, vec, ret);
2390                         return ret;
2391                 }
2392         }
2393
2394         return 0;
2395 }
2396
2397 static int
2398 hns3_refresh_mtu(struct rte_eth_dev *dev, struct rte_eth_conf *conf)
2399 {
2400         struct hns3_adapter *hns = dev->data->dev_private;
2401         struct hns3_hw *hw = &hns->hw;
2402         uint32_t max_rx_pkt_len;
2403         uint16_t mtu;
2404         int ret;
2405
2406         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME))
2407                 return 0;
2408
2409         /*
2410          * If jumbo frames are enabled, MTU needs to be refreshed
2411          * according to the maximum RX packet length.
2412          */
2413         max_rx_pkt_len = conf->rxmode.max_rx_pkt_len;
2414         if (max_rx_pkt_len > HNS3_MAX_FRAME_LEN ||
2415             max_rx_pkt_len <= HNS3_DEFAULT_FRAME_LEN) {
2416                 hns3_err(hw, "maximum Rx packet length must be greater than %u "
2417                          "and no more than %u when jumbo frame enabled.",
2418                          (uint16_t)HNS3_DEFAULT_FRAME_LEN,
2419                          (uint16_t)HNS3_MAX_FRAME_LEN);
2420                 return -EINVAL;
2421         }
2422
2423         mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(max_rx_pkt_len);
2424         ret = hns3_dev_mtu_set(dev, mtu);
2425         if (ret)
2426                 return ret;
2427         dev->data->mtu = mtu;
2428
2429         return 0;
2430 }
2431
2432 static int
2433 hns3_check_link_speed(struct hns3_hw *hw, uint32_t link_speeds)
2434 {
2435         int ret;
2436
2437         /*
2438          * Some hardware doesn't support auto-negotiation, but users may not
2439          * configure link_speeds (default 0), which means auto-negotiation.
2440          * In this case, a warning message need to be printed, instead of
2441          * an error.
2442          */
2443         if (link_speeds == ETH_LINK_SPEED_AUTONEG &&
2444             hw->mac.support_autoneg == 0) {
2445                 hns3_warn(hw, "auto-negotiation is not supported, use default fixed speed!");
2446                 return 0;
2447         }
2448
2449         if (link_speeds != ETH_LINK_SPEED_AUTONEG) {
2450                 ret = hns3_check_port_speed(hw, link_speeds);
2451                 if (ret)
2452                         return ret;
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int
2459 hns3_check_dev_conf(struct rte_eth_dev *dev)
2460 {
2461         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         struct rte_eth_conf *conf = &dev->data->dev_conf;
2463         int ret;
2464
2465         ret = hns3_check_mq_mode(dev);
2466         if (ret)
2467                 return ret;
2468
2469         return hns3_check_link_speed(hw, conf->link_speeds);
2470 }
2471
2472 static int
2473 hns3_dev_configure(struct rte_eth_dev *dev)
2474 {
2475         struct hns3_adapter *hns = dev->data->dev_private;
2476         struct rte_eth_conf *conf = &dev->data->dev_conf;
2477         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2478         struct hns3_hw *hw = &hns->hw;
2479         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2480         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2481         struct rte_eth_rss_conf rss_conf;
2482         bool gro_en;
2483         int ret;
2484
2485         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
2486
2487         /*
2488          * Some versions of hardware network engine does not support
2489          * individually enable/disable/reset the Tx or Rx queue. These devices
2490          * must enable/disable/reset Tx and Rx queues at the same time. When the
2491          * numbers of Tx queues allocated by upper applications are not equal to
2492          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
2493          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
2494          * work as usual. But these fake queues are imperceptible, and can not
2495          * be used by upper applications.
2496          */
2497         if (!hns3_dev_indep_txrx_supported(hw)) {
2498                 ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2499                 if (ret) {
2500                         hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.",
2501                                  ret);
2502                         return ret;
2503                 }
2504         }
2505
2506         hw->adapter_state = HNS3_NIC_CONFIGURING;
2507         ret = hns3_check_dev_conf(dev);
2508         if (ret)
2509                 goto cfg_err;
2510
2511         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2512                 ret = hns3_check_dcb_cfg(dev);
2513                 if (ret)
2514                         goto cfg_err;
2515         }
2516
2517         /* When RSS is not configured, redirect the packet queue 0 */
2518         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2519                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2520                 rss_conf = conf->rx_adv_conf.rss_conf;
2521                 hw->rss_dis_flag = false;
2522                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2523                 if (ret)
2524                         goto cfg_err;
2525         }
2526
2527         ret = hns3_refresh_mtu(dev, conf);
2528         if (ret)
2529                 goto cfg_err;
2530
2531         ret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);
2532         if (ret)
2533                 goto cfg_err;
2534
2535         ret = hns3_dev_configure_vlan(dev);
2536         if (ret)
2537                 goto cfg_err;
2538
2539         /* config hardware GRO */
2540         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
2541         ret = hns3_config_gro(hw, gro_en);
2542         if (ret)
2543                 goto cfg_err;
2544
2545         hns3_init_rx_ptype_tble(dev);
2546         hw->adapter_state = HNS3_NIC_CONFIGURED;
2547
2548         return 0;
2549
2550 cfg_err:
2551         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2552         hw->adapter_state = HNS3_NIC_INITIALIZED;
2553
2554         return ret;
2555 }
2556
2557 static int
2558 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2559 {
2560         struct hns3_config_max_frm_size_cmd *req;
2561         struct hns3_cmd_desc desc;
2562
2563         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2564
2565         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2566         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2567         req->min_frm_size = RTE_ETHER_MIN_LEN;
2568
2569         return hns3_cmd_send(hw, &desc, 1);
2570 }
2571
2572 static int
2573 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2574 {
2575         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2576         uint16_t original_mps = hns->pf.mps;
2577         int err;
2578         int ret;
2579
2580         ret = hns3_set_mac_mtu(hw, mps);
2581         if (ret) {
2582                 hns3_err(hw, "failed to set mtu, ret = %d", ret);
2583                 return ret;
2584         }
2585
2586         hns->pf.mps = mps;
2587         ret = hns3_buffer_alloc(hw);
2588         if (ret) {
2589                 hns3_err(hw, "failed to allocate buffer, ret = %d", ret);
2590                 goto rollback;
2591         }
2592
2593         return 0;
2594
2595 rollback:
2596         err = hns3_set_mac_mtu(hw, original_mps);
2597         if (err) {
2598                 hns3_err(hw, "fail to rollback MTU, err = %d", err);
2599                 return ret;
2600         }
2601         hns->pf.mps = original_mps;
2602
2603         return ret;
2604 }
2605
2606 static int
2607 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2608 {
2609         struct hns3_adapter *hns = dev->data->dev_private;
2610         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2611         struct hns3_hw *hw = &hns->hw;
2612         bool is_jumbo_frame;
2613         int ret;
2614
2615         if (dev->data->dev_started) {
2616                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2617                          "before configuration", dev->data->port_id);
2618                 return -EBUSY;
2619         }
2620
2621         rte_spinlock_lock(&hw->lock);
2622         is_jumbo_frame = frame_size > HNS3_DEFAULT_FRAME_LEN ? true : false;
2623         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2624
2625         /*
2626          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2627          * assign to "uint16_t" type variable.
2628          */
2629         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2630         if (ret) {
2631                 rte_spinlock_unlock(&hw->lock);
2632                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2633                          dev->data->port_id, mtu, ret);
2634                 return ret;
2635         }
2636
2637         if (is_jumbo_frame)
2638                 dev->data->dev_conf.rxmode.offloads |=
2639                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2640         else
2641                 dev->data->dev_conf.rxmode.offloads &=
2642                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2643         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2644         rte_spinlock_unlock(&hw->lock);
2645
2646         return 0;
2647 }
2648
2649 static uint32_t
2650 hns3_get_copper_port_speed_capa(uint32_t supported_speed)
2651 {
2652         uint32_t speed_capa = 0;
2653
2654         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_HD_BIT)
2655                 speed_capa |= ETH_LINK_SPEED_10M_HD;
2656         if (supported_speed & HNS3_PHY_LINK_SPEED_10M_BIT)
2657                 speed_capa |= ETH_LINK_SPEED_10M;
2658         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_HD_BIT)
2659                 speed_capa |= ETH_LINK_SPEED_100M_HD;
2660         if (supported_speed & HNS3_PHY_LINK_SPEED_100M_BIT)
2661                 speed_capa |= ETH_LINK_SPEED_100M;
2662         if (supported_speed & HNS3_PHY_LINK_SPEED_1000M_BIT)
2663                 speed_capa |= ETH_LINK_SPEED_1G;
2664
2665         return speed_capa;
2666 }
2667
2668 static uint32_t
2669 hns3_get_firber_port_speed_capa(uint32_t supported_speed)
2670 {
2671         uint32_t speed_capa = 0;
2672
2673         if (supported_speed & HNS3_FIBER_LINK_SPEED_1G_BIT)
2674                 speed_capa |= ETH_LINK_SPEED_1G;
2675         if (supported_speed & HNS3_FIBER_LINK_SPEED_10G_BIT)
2676                 speed_capa |= ETH_LINK_SPEED_10G;
2677         if (supported_speed & HNS3_FIBER_LINK_SPEED_25G_BIT)
2678                 speed_capa |= ETH_LINK_SPEED_25G;
2679         if (supported_speed & HNS3_FIBER_LINK_SPEED_40G_BIT)
2680                 speed_capa |= ETH_LINK_SPEED_40G;
2681         if (supported_speed & HNS3_FIBER_LINK_SPEED_50G_BIT)
2682                 speed_capa |= ETH_LINK_SPEED_50G;
2683         if (supported_speed & HNS3_FIBER_LINK_SPEED_100G_BIT)
2684                 speed_capa |= ETH_LINK_SPEED_100G;
2685         if (supported_speed & HNS3_FIBER_LINK_SPEED_200G_BIT)
2686                 speed_capa |= ETH_LINK_SPEED_200G;
2687
2688         return speed_capa;
2689 }
2690
2691 static uint32_t
2692 hns3_get_speed_capa(struct hns3_hw *hw)
2693 {
2694         struct hns3_mac *mac = &hw->mac;
2695         uint32_t speed_capa;
2696
2697         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
2698                 speed_capa =
2699                         hns3_get_copper_port_speed_capa(mac->supported_speed);
2700         else
2701                 speed_capa =
2702                         hns3_get_firber_port_speed_capa(mac->supported_speed);
2703
2704         if (mac->support_autoneg == 0)
2705                 speed_capa |= ETH_LINK_SPEED_FIXED;
2706
2707         return speed_capa;
2708 }
2709
2710 int
2711 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2712 {
2713         struct hns3_adapter *hns = eth_dev->data->dev_private;
2714         struct hns3_hw *hw = &hns->hw;
2715         uint16_t queue_num = hw->tqps_num;
2716
2717         /*
2718          * In interrupt mode, 'max_rx_queues' is set based on the number of
2719          * MSI-X interrupt resources of the hardware.
2720          */
2721         if (hw->data->dev_conf.intr_conf.rxq == 1)
2722                 queue_num = hw->intr_tqps_num;
2723
2724         info->max_rx_queues = queue_num;
2725         info->max_tx_queues = hw->tqps_num;
2726         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2727         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
2728         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2729         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2730         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
2731         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2732                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2733                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2734                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2735                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2736                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2737                                  DEV_RX_OFFLOAD_KEEP_CRC |
2738                                  DEV_RX_OFFLOAD_SCATTER |
2739                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2740                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2741                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2742                                  DEV_RX_OFFLOAD_RSS_HASH |
2743                                  DEV_RX_OFFLOAD_TCP_LRO);
2744         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2745                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2746                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2747                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2748                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2749                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2750                                  DEV_TX_OFFLOAD_TCP_TSO |
2751                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2752                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2753                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2754                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
2755                                  hns3_txvlan_cap_get(hw));
2756
2757         if (hns3_dev_outer_udp_cksum_supported(hw))
2758                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2759
2760         if (hns3_dev_indep_txrx_supported(hw))
2761                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
2762                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
2763
2764         if (hns3_dev_ptp_supported(hw))
2765                 info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
2766
2767         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2768                 .nb_max = HNS3_MAX_RING_DESC,
2769                 .nb_min = HNS3_MIN_RING_DESC,
2770                 .nb_align = HNS3_ALIGN_RING_DESC,
2771         };
2772
2773         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2774                 .nb_max = HNS3_MAX_RING_DESC,
2775                 .nb_min = HNS3_MIN_RING_DESC,
2776                 .nb_align = HNS3_ALIGN_RING_DESC,
2777                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
2778                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
2779         };
2780
2781         info->speed_capa = hns3_get_speed_capa(hw);
2782         info->default_rxconf = (struct rte_eth_rxconf) {
2783                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
2784                 /*
2785                  * If there are no available Rx buffer descriptors, incoming
2786                  * packets are always dropped by hardware based on hns3 network
2787                  * engine.
2788                  */
2789                 .rx_drop_en = 1,
2790                 .offloads = 0,
2791         };
2792         info->default_txconf = (struct rte_eth_txconf) {
2793                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
2794                 .offloads = 0,
2795         };
2796
2797         info->vmdq_queue_num = 0;
2798
2799         info->reta_size = hw->rss_ind_tbl_size;
2800         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2801         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2802
2803         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2804         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2805         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2806         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2807         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2808         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2809
2810         return 0;
2811 }
2812
2813 static int
2814 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2815                     size_t fw_size)
2816 {
2817         struct hns3_adapter *hns = eth_dev->data->dev_private;
2818         struct hns3_hw *hw = &hns->hw;
2819         uint32_t version = hw->fw_version;
2820         int ret;
2821
2822         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2823                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2824                                       HNS3_FW_VERSION_BYTE3_S),
2825                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2826                                       HNS3_FW_VERSION_BYTE2_S),
2827                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2828                                       HNS3_FW_VERSION_BYTE1_S),
2829                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2830                                       HNS3_FW_VERSION_BYTE0_S));
2831         ret += 1; /* add the size of '\0' */
2832         if (fw_size < (uint32_t)ret)
2833                 return ret;
2834         else
2835                 return 0;
2836 }
2837
2838 static int
2839 hns3_update_port_link_info(struct rte_eth_dev *eth_dev)
2840 {
2841         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2842         int ret;
2843
2844         (void)hns3_update_link_status(hw);
2845
2846         ret = hns3_update_link_info(eth_dev);
2847         if (ret)
2848                 hw->mac.link_status = ETH_LINK_DOWN;
2849
2850         return ret;
2851 }
2852
2853 static void
2854 hns3_setup_linkstatus(struct rte_eth_dev *eth_dev,
2855                       struct rte_eth_link *new_link)
2856 {
2857         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2858         struct hns3_mac *mac = &hw->mac;
2859
2860         switch (mac->link_speed) {
2861         case ETH_SPEED_NUM_10M:
2862         case ETH_SPEED_NUM_100M:
2863         case ETH_SPEED_NUM_1G:
2864         case ETH_SPEED_NUM_10G:
2865         case ETH_SPEED_NUM_25G:
2866         case ETH_SPEED_NUM_40G:
2867         case ETH_SPEED_NUM_50G:
2868         case ETH_SPEED_NUM_100G:
2869         case ETH_SPEED_NUM_200G:
2870                 new_link->link_speed = mac->link_speed;
2871                 break;
2872         default:
2873                 if (mac->link_status)
2874                         new_link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2875                 else
2876                         new_link->link_speed = ETH_SPEED_NUM_NONE;
2877                 break;
2878         }
2879
2880         new_link->link_duplex = mac->link_duplex;
2881         new_link->link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2882         new_link->link_autoneg = mac->link_autoneg;
2883 }
2884
2885 static int
2886 hns3_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)
2887 {
2888 #define HNS3_LINK_CHECK_INTERVAL 100  /* 100ms */
2889 #define HNS3_MAX_LINK_CHECK_TIMES 20  /* 2s (100 * 20ms) in total */
2890
2891         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
2892         uint32_t retry_cnt = HNS3_MAX_LINK_CHECK_TIMES;
2893         struct hns3_mac *mac = &hw->mac;
2894         struct rte_eth_link new_link;
2895         int ret;
2896
2897         do {
2898                 ret = hns3_update_port_link_info(eth_dev);
2899                 if (ret) {
2900                         hns3_err(hw, "failed to get port link info, ret = %d.",
2901                                  ret);
2902                         break;
2903                 }
2904
2905                 if (!wait_to_complete || mac->link_status == ETH_LINK_UP)
2906                         break;
2907
2908                 rte_delay_ms(HNS3_LINK_CHECK_INTERVAL);
2909         } while (retry_cnt--);
2910
2911         memset(&new_link, 0, sizeof(new_link));
2912         hns3_setup_linkstatus(eth_dev, &new_link);
2913
2914         return rte_eth_linkstatus_set(eth_dev, &new_link);
2915 }
2916
2917 static int
2918 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2919 {
2920         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2921         struct hns3_pf *pf = &hns->pf;
2922
2923         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2924                 return -EINVAL;
2925
2926         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2927
2928         return 0;
2929 }
2930
2931 static int
2932 hns3_query_function_status(struct hns3_hw *hw)
2933 {
2934 #define HNS3_QUERY_MAX_CNT              10
2935 #define HNS3_QUERY_SLEEP_MSCOEND        1
2936         struct hns3_func_status_cmd *req;
2937         struct hns3_cmd_desc desc;
2938         int timeout = 0;
2939         int ret;
2940
2941         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2942         req = (struct hns3_func_status_cmd *)desc.data;
2943
2944         do {
2945                 ret = hns3_cmd_send(hw, &desc, 1);
2946                 if (ret) {
2947                         PMD_INIT_LOG(ERR, "query function status failed %d",
2948                                      ret);
2949                         return ret;
2950                 }
2951
2952                 /* Check pf reset is done */
2953                 if (req->pf_state)
2954                         break;
2955
2956                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2957         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2958
2959         return hns3_parse_func_status(hw, req);
2960 }
2961
2962 static int
2963 hns3_get_pf_max_tqp_num(struct hns3_hw *hw)
2964 {
2965         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2966         struct hns3_pf *pf = &hns->pf;
2967
2968         if (pf->tqp_config_mode == HNS3_FLEX_MAX_TQP_NUM_MODE) {
2969                 /*
2970                  * The total_tqps_num obtained from firmware is maximum tqp
2971                  * numbers of this port, which should be used for PF and VFs.
2972                  * There is no need for pf to have so many tqp numbers in
2973                  * most cases. RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2974                  * coming from config file, is assigned to maximum queue number
2975                  * for the PF of this port by user. So users can modify the
2976                  * maximum queue number of PF according to their own application
2977                  * scenarios, which is more flexible to use. In addition, many
2978                  * memories can be saved due to allocating queue statistics
2979                  * room according to the actual number of queues required. The
2980                  * maximum queue number of PF for network engine with
2981                  * revision_id greater than 0x30 is assigned by config file.
2982                  */
2983                 if (RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF <= 0) {
2984                         hns3_err(hw, "RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF(%d) "
2985                                  "must be greater than 0.",
2986                                  RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF);
2987                         return -EINVAL;
2988                 }
2989
2990                 hw->tqps_num = RTE_MIN(RTE_LIBRTE_HNS3_MAX_TQP_NUM_PER_PF,
2991                                        hw->total_tqps_num);
2992         } else {
2993                 /*
2994                  * Due to the limitation on the number of PF interrupts
2995                  * available, the maximum queue number assigned to PF on
2996                  * the network engine with revision_id 0x21 is 64.
2997                  */
2998                 hw->tqps_num = RTE_MIN(hw->total_tqps_num,
2999                                        HNS3_MAX_TQP_NUM_HIP08_PF);
3000         }
3001
3002         return 0;
3003 }
3004
3005 static int
3006 hns3_query_pf_resource(struct hns3_hw *hw)
3007 {
3008         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3009         struct hns3_pf *pf = &hns->pf;
3010         struct hns3_pf_res_cmd *req;
3011         struct hns3_cmd_desc desc;
3012         int ret;
3013
3014         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
3015         ret = hns3_cmd_send(hw, &desc, 1);
3016         if (ret) {
3017                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
3018                 return ret;
3019         }
3020
3021         req = (struct hns3_pf_res_cmd *)desc.data;
3022         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num) +
3023                              rte_le_to_cpu_16(req->ext_tqp_num);
3024         ret = hns3_get_pf_max_tqp_num(hw);
3025         if (ret)
3026                 return ret;
3027
3028         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
3029         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
3030
3031         if (req->tx_buf_size)
3032                 pf->tx_buf_size =
3033                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
3034         else
3035                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
3036
3037         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
3038
3039         if (req->dv_buf_size)
3040                 pf->dv_buf_size =
3041                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
3042         else
3043                 pf->dv_buf_size = HNS3_DEFAULT_DV;
3044
3045         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
3046
3047         hw->num_msi =
3048                 hns3_get_field(rte_le_to_cpu_16(req->nic_pf_intr_vector_number),
3049                                HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
3050
3051         return 0;
3052 }
3053
3054 static void
3055 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
3056 {
3057         struct hns3_cfg_param_cmd *req;
3058         uint64_t mac_addr_tmp_high;
3059         uint8_t ext_rss_size_max;
3060         uint64_t mac_addr_tmp;
3061         uint32_t i;
3062
3063         req = (struct hns3_cfg_param_cmd *)desc[0].data;
3064
3065         /* get the configuration */
3066         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3067                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
3068         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3069                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
3070         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
3071                                            HNS3_CFG_TQP_DESC_N_M,
3072                                            HNS3_CFG_TQP_DESC_N_S);
3073
3074         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3075                                        HNS3_CFG_PHY_ADDR_M,
3076                                        HNS3_CFG_PHY_ADDR_S);
3077         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3078                                          HNS3_CFG_MEDIA_TP_M,
3079                                          HNS3_CFG_MEDIA_TP_S);
3080         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3081                                          HNS3_CFG_RX_BUF_LEN_M,
3082                                          HNS3_CFG_RX_BUF_LEN_S);
3083         /* get mac address */
3084         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
3085         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3086                                            HNS3_CFG_MAC_ADDR_H_M,
3087                                            HNS3_CFG_MAC_ADDR_H_S);
3088
3089         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
3090
3091         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3092                                             HNS3_CFG_DEFAULT_SPEED_M,
3093                                             HNS3_CFG_DEFAULT_SPEED_S);
3094         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
3095                                            HNS3_CFG_RSS_SIZE_M,
3096                                            HNS3_CFG_RSS_SIZE_S);
3097
3098         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3099                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
3100
3101         req = (struct hns3_cfg_param_cmd *)desc[1].data;
3102         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
3103
3104         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3105                                             HNS3_CFG_SPEED_ABILITY_M,
3106                                             HNS3_CFG_SPEED_ABILITY_S);
3107         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
3108                                         HNS3_CFG_UMV_TBL_SPACE_M,
3109                                         HNS3_CFG_UMV_TBL_SPACE_S);
3110         if (!cfg->umv_space)
3111                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
3112
3113         ext_rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[2]),
3114                                                HNS3_CFG_EXT_RSS_SIZE_M,
3115                                                HNS3_CFG_EXT_RSS_SIZE_S);
3116
3117         /*
3118          * Field ext_rss_size_max obtained from firmware will be more flexible
3119          * for future changes and expansions, which is an exponent of 2, instead
3120          * of reading out directly. If this field is not zero, hns3 PF PMD
3121          * driver uses it as rss_size_max under one TC. Device, whose revision
3122          * id is greater than or equal to PCI_REVISION_ID_HIP09_A, obtains the
3123          * maximum number of queues supported under a TC through this field.
3124          */
3125         if (ext_rss_size_max)
3126                 cfg->rss_size_max = 1U << ext_rss_size_max;
3127 }
3128
3129 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
3130  * @hw: pointer to struct hns3_hw
3131  * @hcfg: the config structure to be getted
3132  */
3133 static int
3134 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
3135 {
3136         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
3137         struct hns3_cfg_param_cmd *req;
3138         uint32_t offset;
3139         uint32_t i;
3140         int ret;
3141
3142         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
3143                 offset = 0;
3144                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
3145                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
3146                                           true);
3147                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
3148                                i * HNS3_CFG_RD_LEN_BYTES);
3149                 /* Len should be divided by 4 when send to hardware */
3150                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
3151                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
3152                 req->offset = rte_cpu_to_le_32(offset);
3153         }
3154
3155         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
3156         if (ret) {
3157                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
3158                 return ret;
3159         }
3160
3161         hns3_parse_cfg(hcfg, desc);
3162
3163         return 0;
3164 }
3165
3166 static int
3167 hns3_parse_speed(int speed_cmd, uint32_t *speed)
3168 {
3169         switch (speed_cmd) {
3170         case HNS3_CFG_SPEED_10M:
3171                 *speed = ETH_SPEED_NUM_10M;
3172                 break;
3173         case HNS3_CFG_SPEED_100M:
3174                 *speed = ETH_SPEED_NUM_100M;
3175                 break;
3176         case HNS3_CFG_SPEED_1G:
3177                 *speed = ETH_SPEED_NUM_1G;
3178                 break;
3179         case HNS3_CFG_SPEED_10G:
3180                 *speed = ETH_SPEED_NUM_10G;
3181                 break;
3182         case HNS3_CFG_SPEED_25G:
3183                 *speed = ETH_SPEED_NUM_25G;
3184                 break;
3185         case HNS3_CFG_SPEED_40G:
3186                 *speed = ETH_SPEED_NUM_40G;
3187                 break;
3188         case HNS3_CFG_SPEED_50G:
3189                 *speed = ETH_SPEED_NUM_50G;
3190                 break;
3191         case HNS3_CFG_SPEED_100G:
3192                 *speed = ETH_SPEED_NUM_100G;
3193                 break;
3194         case HNS3_CFG_SPEED_200G:
3195                 *speed = ETH_SPEED_NUM_200G;
3196                 break;
3197         default:
3198                 return -EINVAL;
3199         }
3200
3201         return 0;
3202 }
3203
3204 static void
3205 hns3_set_default_dev_specifications(struct hns3_hw *hw)
3206 {
3207         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
3208         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
3209         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
3210         hw->max_tm_rate = HNS3_ETHER_MAX_RATE;
3211         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
3212 }
3213
3214 static void
3215 hns3_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
3216 {
3217         struct hns3_dev_specs_0_cmd *req0;
3218
3219         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
3220
3221         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
3222         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
3223         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
3224         hw->max_tm_rate = rte_le_to_cpu_32(req0->max_tm_rate);
3225         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
3226 }
3227
3228 static int
3229 hns3_check_dev_specifications(struct hns3_hw *hw)
3230 {
3231         if (hw->rss_ind_tbl_size == 0 ||
3232             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
3233                 hns3_err(hw, "the size of hash lookup table configured (%u)"
3234                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
3235                               HNS3_RSS_IND_TBL_SIZE_MAX);
3236                 return -EINVAL;
3237         }
3238
3239         return 0;
3240 }
3241
3242 static int
3243 hns3_query_dev_specifications(struct hns3_hw *hw)
3244 {
3245         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
3246         int ret;
3247         int i;
3248
3249         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
3250                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
3251                                           true);
3252                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3253         }
3254         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
3255
3256         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
3257         if (ret)
3258                 return ret;
3259
3260         hns3_parse_dev_specifications(hw, desc);
3261
3262         return hns3_check_dev_specifications(hw);
3263 }
3264
3265 static int
3266 hns3_get_capability(struct hns3_hw *hw)
3267 {
3268         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3269         struct rte_pci_device *pci_dev;
3270         struct hns3_pf *pf = &hns->pf;
3271         struct rte_eth_dev *eth_dev;
3272         uint16_t device_id;
3273         uint8_t revision;
3274         int ret;
3275
3276         eth_dev = &rte_eth_devices[hw->data->port_id];
3277         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3278         device_id = pci_dev->id.device_id;
3279
3280         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
3281             device_id == HNS3_DEV_ID_50GE_RDMA ||
3282             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC ||
3283             device_id == HNS3_DEV_ID_200G_RDMA)
3284                 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1);
3285
3286         /* Get PCI revision id */
3287         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
3288                                   HNS3_PCI_REVISION_ID);
3289         if (ret != HNS3_PCI_REVISION_ID_LEN) {
3290                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
3291                              ret);
3292                 return -EIO;
3293         }
3294         hw->revision = revision;
3295
3296         if (revision < PCI_REVISION_ID_HIP09_A) {
3297                 hns3_set_default_dev_specifications(hw);
3298                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
3299                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
3300                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
3301                 hw->vlan_mode = HNS3_SW_SHIFT_AND_DISCARD_MODE;
3302                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
3303                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
3304                 pf->tqp_config_mode = HNS3_FIXED_MAX_TQP_NUM_MODE;
3305                 hw->rss_info.ipv6_sctp_offload_supported = false;
3306                 hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE;
3307                 return 0;
3308         }
3309
3310         ret = hns3_query_dev_specifications(hw);
3311         if (ret) {
3312                 PMD_INIT_LOG(ERR,
3313                              "failed to query dev specifications, ret = %d",
3314                              ret);
3315                 return ret;
3316         }
3317
3318         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
3319         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
3320         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
3321         hw->vlan_mode = HNS3_HW_SHIFT_AND_DISCARD_MODE;
3322         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
3323         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
3324         pf->tqp_config_mode = HNS3_FLEX_MAX_TQP_NUM_MODE;
3325         hw->rss_info.ipv6_sctp_offload_supported = true;
3326         hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE;
3327
3328         return 0;
3329 }
3330
3331 static int
3332 hns3_check_media_type(struct hns3_hw *hw, uint8_t media_type)
3333 {
3334         int ret;
3335
3336         switch (media_type) {
3337         case HNS3_MEDIA_TYPE_COPPER:
3338                 if (!hns3_dev_copper_supported(hw)) {
3339                         PMD_INIT_LOG(ERR,
3340                                      "Media type is copper, not supported.");
3341                         ret = -EOPNOTSUPP;
3342                 } else {
3343                         ret = 0;
3344                 }
3345                 break;
3346         case HNS3_MEDIA_TYPE_FIBER:
3347                 ret = 0;
3348                 break;
3349         case HNS3_MEDIA_TYPE_BACKPLANE:
3350                 PMD_INIT_LOG(ERR, "Media type is Backplane, not supported.");
3351                 ret = -EOPNOTSUPP;
3352                 break;
3353         default:
3354                 PMD_INIT_LOG(ERR, "Unknown media type = %u!", media_type);
3355                 ret = -EINVAL;
3356                 break;
3357         }
3358
3359         return ret;
3360 }
3361
3362 static int
3363 hns3_get_board_configuration(struct hns3_hw *hw)
3364 {
3365         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3366         struct hns3_pf *pf = &hns->pf;
3367         struct hns3_cfg cfg;
3368         int ret;
3369
3370         ret = hns3_get_board_cfg(hw, &cfg);
3371         if (ret) {
3372                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
3373                 return ret;
3374         }
3375
3376         ret = hns3_check_media_type(hw, cfg.media_type);
3377         if (ret)
3378                 return ret;
3379
3380         hw->mac.media_type = cfg.media_type;
3381         hw->rss_size_max = cfg.rss_size_max;
3382         hw->rss_dis_flag = false;
3383         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
3384         hw->mac.phy_addr = cfg.phy_addr;
3385         hw->mac.default_addr_setted = false;
3386         hw->num_tx_desc = cfg.tqp_desc_num;
3387         hw->num_rx_desc = cfg.tqp_desc_num;
3388         hw->dcb_info.num_pg = 1;
3389         hw->dcb_info.hw_pfc_map = 0;
3390
3391         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
3392         if (ret) {
3393                 PMD_INIT_LOG(ERR, "Get wrong speed %u, ret = %d",
3394                              cfg.default_speed, ret);
3395                 return ret;
3396         }
3397
3398         pf->tc_max = cfg.tc_num;
3399         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
3400                 PMD_INIT_LOG(WARNING,
3401                              "Get TC num(%u) from flash, set TC num to 1",
3402                              pf->tc_max);
3403                 pf->tc_max = 1;
3404         }
3405
3406         /* Dev does not support DCB */
3407         if (!hns3_dev_dcb_supported(hw)) {
3408                 pf->tc_max = 1;
3409                 pf->pfc_max = 0;
3410         } else
3411                 pf->pfc_max = pf->tc_max;
3412
3413         hw->dcb_info.num_tc = 1;
3414         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
3415                                      hw->tqps_num / hw->dcb_info.num_tc);
3416         hns3_set_bit(hw->hw_tc_map, 0, 1);
3417         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
3418
3419         pf->wanted_umv_size = cfg.umv_space;
3420
3421         return ret;
3422 }
3423
3424 static int
3425 hns3_get_configuration(struct hns3_hw *hw)
3426 {
3427         int ret;
3428
3429         ret = hns3_query_function_status(hw);
3430         if (ret) {
3431                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
3432                 return ret;
3433         }
3434
3435         /* Get device capability */
3436         ret = hns3_get_capability(hw);
3437         if (ret) {
3438                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
3439                 return ret;
3440         }
3441
3442         /* Get pf resource */
3443         ret = hns3_query_pf_resource(hw);
3444         if (ret) {
3445                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
3446                 return ret;
3447         }
3448
3449         ret = hns3_get_board_configuration(hw);
3450         if (ret) {
3451                 PMD_INIT_LOG(ERR, "failed to get board configuration: %d", ret);
3452                 return ret;
3453         }
3454
3455         ret = hns3_query_dev_fec_info(hw);
3456         if (ret)
3457                 PMD_INIT_LOG(ERR,
3458                              "failed to query FEC information, ret = %d", ret);
3459
3460         return ret;
3461 }
3462
3463 static int
3464 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
3465                       uint16_t tqp_vid, bool is_pf)
3466 {
3467         struct hns3_tqp_map_cmd *req;
3468         struct hns3_cmd_desc desc;
3469         int ret;
3470
3471         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
3472
3473         req = (struct hns3_tqp_map_cmd *)desc.data;
3474         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
3475         req->tqp_vf = func_id;
3476         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
3477         if (!is_pf)
3478                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
3479         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
3480
3481         ret = hns3_cmd_send(hw, &desc, 1);
3482         if (ret)
3483                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
3484
3485         return ret;
3486 }
3487
3488 static int
3489 hns3_map_tqp(struct hns3_hw *hw)
3490 {
3491         int ret;
3492         int i;
3493
3494         /*
3495          * In current version, VF is not supported when PF is driven by DPDK
3496          * driver, so we assign total tqps_num tqps allocated to this port
3497          * to PF.
3498          */
3499         for (i = 0; i < hw->total_tqps_num; i++) {
3500                 ret = hns3_map_tqps_to_func(hw, HNS3_PF_FUNC_ID, i, i, true);
3501                 if (ret)
3502                         return ret;
3503         }
3504
3505         return 0;
3506 }
3507
3508 static int
3509 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3510 {
3511         struct hns3_config_mac_speed_dup_cmd *req;
3512         struct hns3_cmd_desc desc;
3513         int ret;
3514
3515         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
3516
3517         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
3518
3519         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
3520
3521         switch (speed) {
3522         case ETH_SPEED_NUM_10M:
3523                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3524                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
3525                 break;
3526         case ETH_SPEED_NUM_100M:
3527                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3528                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
3529                 break;
3530         case ETH_SPEED_NUM_1G:
3531                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3532                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
3533                 break;
3534         case ETH_SPEED_NUM_10G:
3535                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3536                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
3537                 break;
3538         case ETH_SPEED_NUM_25G:
3539                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3540                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
3541                 break;
3542         case ETH_SPEED_NUM_40G:
3543                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3544                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
3545                 break;
3546         case ETH_SPEED_NUM_50G:
3547                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3548                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
3549                 break;
3550         case ETH_SPEED_NUM_100G:
3551                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3552                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
3553                 break;
3554         case ETH_SPEED_NUM_200G:
3555                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
3556                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_200G);
3557                 break;
3558         default:
3559                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
3560                 return -EINVAL;
3561         }
3562
3563         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
3564
3565         ret = hns3_cmd_send(hw, &desc, 1);
3566         if (ret)
3567                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
3568
3569         return ret;
3570 }
3571
3572 static int
3573 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3574 {
3575         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3576         struct hns3_pf *pf = &hns->pf;
3577         struct hns3_priv_buf *priv;
3578         uint32_t i, total_size;
3579
3580         total_size = pf->pkt_buf_size;
3581
3582         /* alloc tx buffer for all enabled tc */
3583         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3584                 priv = &buf_alloc->priv_buf[i];
3585
3586                 if (hw->hw_tc_map & BIT(i)) {
3587                         if (total_size < pf->tx_buf_size)
3588                                 return -ENOMEM;
3589
3590                         priv->tx_buf_size = pf->tx_buf_size;
3591                 } else
3592                         priv->tx_buf_size = 0;
3593
3594                 total_size -= priv->tx_buf_size;
3595         }
3596
3597         return 0;
3598 }
3599
3600 static int
3601 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3602 {
3603 /* TX buffer size is unit by 128 byte */
3604 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3605 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3606         struct hns3_tx_buff_alloc_cmd *req;
3607         struct hns3_cmd_desc desc;
3608         uint32_t buf_size;
3609         uint32_t i;
3610         int ret;
3611
3612         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3613
3614         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3615         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3616                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3617
3618                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3619                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3620                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3621         }
3622
3623         ret = hns3_cmd_send(hw, &desc, 1);
3624         if (ret)
3625                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3626
3627         return ret;
3628 }
3629
3630 static int
3631 hns3_get_tc_num(struct hns3_hw *hw)
3632 {
3633         int cnt = 0;
3634         uint8_t i;
3635
3636         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3637                 if (hw->hw_tc_map & BIT(i))
3638                         cnt++;
3639         return cnt;
3640 }
3641
3642 static uint32_t
3643 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3644 {
3645         struct hns3_priv_buf *priv;
3646         uint32_t rx_priv = 0;
3647         int i;
3648
3649         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3650                 priv = &buf_alloc->priv_buf[i];
3651                 if (priv->enable)
3652                         rx_priv += priv->buf_size;
3653         }
3654         return rx_priv;
3655 }
3656
3657 static uint32_t
3658 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3659 {
3660         uint32_t total_tx_size = 0;
3661         uint32_t i;
3662
3663         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3664                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3665
3666         return total_tx_size;
3667 }
3668
3669 /* Get the number of pfc enabled TCs, which have private buffer */
3670 static int
3671 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3672 {
3673         struct hns3_priv_buf *priv;
3674         int cnt = 0;
3675         uint8_t i;
3676
3677         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3678                 priv = &buf_alloc->priv_buf[i];
3679                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3680                         cnt++;
3681         }
3682
3683         return cnt;
3684 }
3685
3686 /* Get the number of pfc disabled TCs, which have private buffer */
3687 static int
3688 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3689                          struct hns3_pkt_buf_alloc *buf_alloc)
3690 {
3691         struct hns3_priv_buf *priv;
3692         int cnt = 0;
3693         uint8_t i;
3694
3695         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3696                 priv = &buf_alloc->priv_buf[i];
3697                 if (hw->hw_tc_map & BIT(i) &&
3698                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3699                         cnt++;
3700         }
3701
3702         return cnt;
3703 }
3704
3705 static bool
3706 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3707                   uint32_t rx_all)
3708 {
3709         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3710         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3711         struct hns3_pf *pf = &hns->pf;
3712         uint32_t shared_buf, aligned_mps;
3713         uint32_t rx_priv;
3714         uint8_t tc_num;
3715         uint8_t i;
3716
3717         tc_num = hns3_get_tc_num(hw);
3718         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3719
3720         if (hns3_dev_dcb_supported(hw))
3721                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3722                                         pf->dv_buf_size;
3723         else
3724                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3725                                         + pf->dv_buf_size;
3726
3727         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3728         shared_std = roundup(RTE_MAX(shared_buf_min, shared_buf_tc),
3729                              HNS3_BUF_SIZE_UNIT);
3730
3731         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3732         if (rx_all < rx_priv + shared_std)
3733                 return false;
3734
3735         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3736         buf_alloc->s_buf.buf_size = shared_buf;
3737         if (hns3_dev_dcb_supported(hw)) {
3738                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3739                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3740                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3741                                   HNS3_BUF_SIZE_UNIT);
3742         } else {
3743                 buf_alloc->s_buf.self.high =
3744                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3745                 buf_alloc->s_buf.self.low = aligned_mps;
3746         }
3747
3748         if (hns3_dev_dcb_supported(hw)) {
3749                 hi_thrd = shared_buf - pf->dv_buf_size;
3750
3751                 if (tc_num <= NEED_RESERVE_TC_NUM)
3752                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT /
3753                                   BUF_MAX_PERCENT;
3754
3755                 if (tc_num)
3756                         hi_thrd = hi_thrd / tc_num;
3757
3758                 hi_thrd = RTE_MAX(hi_thrd, HNS3_BUF_MUL_BY * aligned_mps);
3759                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3760                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3761         } else {
3762                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3763                 lo_thrd = aligned_mps;
3764         }
3765
3766         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3767                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3768                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3769         }
3770
3771         return true;
3772 }
3773
3774 static bool
3775 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3776                      struct hns3_pkt_buf_alloc *buf_alloc)
3777 {
3778         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3779         struct hns3_pf *pf = &hns->pf;
3780         struct hns3_priv_buf *priv;
3781         uint32_t aligned_mps;
3782         uint32_t rx_all;
3783         uint8_t i;
3784
3785         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3786         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3787
3788         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3789                 priv = &buf_alloc->priv_buf[i];
3790
3791                 priv->enable = 0;
3792                 priv->wl.low = 0;
3793                 priv->wl.high = 0;
3794                 priv->buf_size = 0;
3795
3796                 if (!(hw->hw_tc_map & BIT(i)))
3797                         continue;
3798
3799                 priv->enable = 1;
3800                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3801                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3802                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3803                                                 HNS3_BUF_SIZE_UNIT);
3804                 } else {
3805                         priv->wl.low = 0;
3806                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3807                                         aligned_mps;
3808                 }
3809
3810                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3811         }
3812
3813         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3814 }
3815
3816 static bool
3817 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3818                              struct hns3_pkt_buf_alloc *buf_alloc)
3819 {
3820         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3821         struct hns3_pf *pf = &hns->pf;
3822         struct hns3_priv_buf *priv;
3823         int no_pfc_priv_num;
3824         uint32_t rx_all;
3825         uint8_t mask;
3826         int i;
3827
3828         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3829         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3830
3831         /* let the last to be cleared first */
3832         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3833                 priv = &buf_alloc->priv_buf[i];
3834                 mask = BIT((uint8_t)i);
3835
3836                 if (hw->hw_tc_map & mask &&
3837                     !(hw->dcb_info.hw_pfc_map & mask)) {
3838                         /* Clear the no pfc TC private buffer */
3839                         priv->wl.low = 0;
3840                         priv->wl.high = 0;
3841                         priv->buf_size = 0;
3842                         priv->enable = 0;
3843                         no_pfc_priv_num--;
3844                 }
3845
3846                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3847                     no_pfc_priv_num == 0)
3848                         break;
3849         }
3850
3851         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3852 }
3853
3854 static bool
3855 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3856                            struct hns3_pkt_buf_alloc *buf_alloc)
3857 {
3858         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3859         struct hns3_pf *pf = &hns->pf;
3860         struct hns3_priv_buf *priv;
3861         uint32_t rx_all;
3862         int pfc_priv_num;
3863         uint8_t mask;
3864         int i;
3865
3866         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3867         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3868
3869         /* let the last to be cleared first */
3870         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3871                 priv = &buf_alloc->priv_buf[i];
3872                 mask = BIT((uint8_t)i);
3873                 if (hw->hw_tc_map & mask && hw->dcb_info.hw_pfc_map & mask) {
3874                         /* Reduce the number of pfc TC with private buffer */
3875                         priv->wl.low = 0;
3876                         priv->enable = 0;
3877                         priv->wl.high = 0;
3878                         priv->buf_size = 0;
3879                         pfc_priv_num--;
3880                 }
3881                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3882                     pfc_priv_num == 0)
3883                         break;
3884         }
3885
3886         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3887 }
3888
3889 static bool
3890 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3891                           struct hns3_pkt_buf_alloc *buf_alloc)
3892 {
3893 #define COMPENSATE_BUFFER       0x3C00
3894 #define COMPENSATE_HALF_MPS_NUM 5
3895 #define PRIV_WL_GAP             0x1800
3896         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3897         struct hns3_pf *pf = &hns->pf;
3898         uint32_t tc_num = hns3_get_tc_num(hw);
3899         uint32_t half_mps = pf->mps >> 1;
3900         struct hns3_priv_buf *priv;
3901         uint32_t min_rx_priv;
3902         uint32_t rx_priv;
3903         uint8_t i;
3904
3905         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3906         if (tc_num)
3907                 rx_priv = rx_priv / tc_num;
3908
3909         if (tc_num <= NEED_RESERVE_TC_NUM)
3910                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3911
3912         /*
3913          * Minimum value of private buffer in rx direction (min_rx_priv) is
3914          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3915          * buffer if rx_priv is greater than min_rx_priv.
3916          */
3917         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3918                         COMPENSATE_HALF_MPS_NUM * half_mps;
3919         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3920         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3921
3922         if (rx_priv < min_rx_priv)
3923                 return false;
3924
3925         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3926                 priv = &buf_alloc->priv_buf[i];
3927                 priv->enable = 0;
3928                 priv->wl.low = 0;
3929                 priv->wl.high = 0;
3930                 priv->buf_size = 0;
3931
3932                 if (!(hw->hw_tc_map & BIT(i)))
3933                         continue;
3934
3935                 priv->enable = 1;
3936                 priv->buf_size = rx_priv;
3937                 priv->wl.high = rx_priv - pf->dv_buf_size;
3938                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3939         }
3940
3941         buf_alloc->s_buf.buf_size = 0;
3942
3943         return true;
3944 }
3945
3946 /*
3947  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3948  * @hw: pointer to struct hns3_hw
3949  * @buf_alloc: pointer to buffer calculation data
3950  * @return: 0: calculate sucessful, negative: fail
3951  */
3952 static int
3953 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3954 {
3955         /* When DCB is not supported, rx private buffer is not allocated. */
3956         if (!hns3_dev_dcb_supported(hw)) {
3957                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3958                 struct hns3_pf *pf = &hns->pf;
3959                 uint32_t rx_all = pf->pkt_buf_size;
3960
3961                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3962                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3963                         return -ENOMEM;
3964
3965                 return 0;
3966         }
3967
3968         /*
3969          * Try to allocate privated packet buffer for all TCs without share
3970          * buffer.
3971          */
3972         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3973                 return 0;
3974
3975         /*
3976          * Try to allocate privated packet buffer for all TCs with share
3977          * buffer.
3978          */
3979         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3980                 return 0;
3981
3982         /*
3983          * For different application scenes, the enabled port number, TC number
3984          * and no_drop TC number are different. In order to obtain the better
3985          * performance, software could allocate the buffer size and configure
3986          * the waterline by tring to decrease the private buffer size according
3987          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3988          * enabled tc.
3989          */
3990         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3991                 return 0;
3992
3993         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3994                 return 0;
3995
3996         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3997                 return 0;
3998
3999         return -ENOMEM;
4000 }
4001
4002 static int
4003 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4004 {
4005         struct hns3_rx_priv_buff_cmd *req;
4006         struct hns3_cmd_desc desc;
4007         uint32_t buf_size;
4008         int ret;
4009         int i;
4010
4011         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
4012         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
4013
4014         /* Alloc private buffer TCs */
4015         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4016                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
4017
4018                 req->buf_num[i] =
4019                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
4020                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
4021         }
4022
4023         buf_size = buf_alloc->s_buf.buf_size;
4024         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
4025                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
4026
4027         ret = hns3_cmd_send(hw, &desc, 1);
4028         if (ret)
4029                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
4030
4031         return ret;
4032 }
4033
4034 static int
4035 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4036 {
4037 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
4038         struct hns3_rx_priv_wl_buf *req;
4039         struct hns3_priv_buf *priv;
4040         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
4041         int i, j;
4042         int ret;
4043
4044         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
4045                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
4046                                           false);
4047                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
4048
4049                 /* The first descriptor set the NEXT bit to 1 */
4050                 if (i == 0)
4051                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4052                 else
4053                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4054
4055                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4056                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
4057
4058                         priv = &buf_alloc->priv_buf[idx];
4059                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
4060                                                         HNS3_BUF_UNIT_S);
4061                         req->tc_wl[j].high |=
4062                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4063                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
4064                                                         HNS3_BUF_UNIT_S);
4065                         req->tc_wl[j].low |=
4066                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4067                 }
4068         }
4069
4070         /* Send 2 descriptor at one time */
4071         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
4072         if (ret)
4073                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
4074                              ret);
4075         return ret;
4076 }
4077
4078 static int
4079 hns3_common_thrd_config(struct hns3_hw *hw,
4080                         struct hns3_pkt_buf_alloc *buf_alloc)
4081 {
4082 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
4083         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
4084         struct hns3_rx_com_thrd *req;
4085         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
4086         struct hns3_tc_thrd *tc;
4087         int tc_idx;
4088         int i, j;
4089         int ret;
4090
4091         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
4092                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
4093                                           false);
4094                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
4095
4096                 /* The first descriptor set the NEXT bit to 1 */
4097                 if (i == 0)
4098                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4099                 else
4100                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4101
4102                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
4103                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
4104                         tc = &s_buf->tc_thrd[tc_idx];
4105
4106                         req->com_thrd[j].high =
4107                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
4108                         req->com_thrd[j].high |=
4109                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4110                         req->com_thrd[j].low =
4111                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
4112                         req->com_thrd[j].low |=
4113                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4114                 }
4115         }
4116
4117         /* Send 2 descriptors at one time */
4118         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
4119         if (ret)
4120                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
4121
4122         return ret;
4123 }
4124
4125 static int
4126 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
4127 {
4128         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
4129         struct hns3_rx_com_wl *req;
4130         struct hns3_cmd_desc desc;
4131         int ret;
4132
4133         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
4134
4135         req = (struct hns3_rx_com_wl *)desc.data;
4136         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
4137         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4138
4139         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
4140         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
4141
4142         ret = hns3_cmd_send(hw, &desc, 1);
4143         if (ret)
4144                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
4145
4146         return ret;
4147 }
4148
4149 int
4150 hns3_buffer_alloc(struct hns3_hw *hw)
4151 {
4152         struct hns3_pkt_buf_alloc pkt_buf;
4153         int ret;
4154
4155         memset(&pkt_buf, 0, sizeof(pkt_buf));
4156         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
4157         if (ret) {
4158                 PMD_INIT_LOG(ERR,
4159                              "could not calc tx buffer size for all TCs %d",
4160                              ret);
4161                 return ret;
4162         }
4163
4164         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
4165         if (ret) {
4166                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
4167                 return ret;
4168         }
4169
4170         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
4171         if (ret) {
4172                 PMD_INIT_LOG(ERR,
4173                              "could not calc rx priv buffer size for all TCs %d",
4174                              ret);
4175                 return ret;
4176         }
4177
4178         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
4179         if (ret) {
4180                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
4181                 return ret;
4182         }
4183
4184         if (hns3_dev_dcb_supported(hw)) {
4185                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
4186                 if (ret) {
4187                         PMD_INIT_LOG(ERR,
4188                                      "could not configure rx private waterline %d",
4189                                      ret);
4190                         return ret;
4191                 }
4192
4193                 ret = hns3_common_thrd_config(hw, &pkt_buf);
4194                 if (ret) {
4195                         PMD_INIT_LOG(ERR,
4196                                      "could not configure common threshold %d",
4197                                      ret);
4198                         return ret;
4199                 }
4200         }
4201
4202         ret = hns3_common_wl_config(hw, &pkt_buf);
4203         if (ret)
4204                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
4205                              ret);
4206
4207         return ret;
4208 }
4209
4210 static int
4211 hns3_mac_init(struct hns3_hw *hw)
4212 {
4213         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4214         struct hns3_mac *mac = &hw->mac;
4215         struct hns3_pf *pf = &hns->pf;
4216         int ret;
4217
4218         pf->support_sfp_query = true;
4219         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
4220         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
4221         if (ret) {
4222                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
4223                 return ret;
4224         }
4225
4226         mac->link_status = ETH_LINK_DOWN;
4227
4228         return hns3_config_mtu(hw, pf->mps);
4229 }
4230
4231 static int
4232 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
4233 {
4234 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
4235 #define HNS3_ETHERTYPE_ALREADY_ADD              1
4236 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
4237 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
4238         int return_status;
4239
4240         if (cmdq_resp) {
4241                 PMD_INIT_LOG(ERR,
4242                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%u.\n",
4243                              cmdq_resp);
4244                 return -EIO;
4245         }
4246
4247         switch (resp_code) {
4248         case HNS3_ETHERTYPE_SUCCESS_ADD:
4249         case HNS3_ETHERTYPE_ALREADY_ADD:
4250                 return_status = 0;
4251                 break;
4252         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
4253                 PMD_INIT_LOG(ERR,
4254                              "add mac ethertype failed for manager table overflow.");
4255                 return_status = -EIO;
4256                 break;
4257         case HNS3_ETHERTYPE_KEY_CONFLICT:
4258                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
4259                 return_status = -EIO;
4260                 break;
4261         default:
4262                 PMD_INIT_LOG(ERR,
4263                              "add mac ethertype failed for undefined, code=%u.",
4264                              resp_code);
4265                 return_status = -EIO;
4266                 break;
4267         }
4268
4269         return return_status;
4270 }
4271
4272 static int
4273 hns3_add_mgr_tbl(struct hns3_hw *hw,
4274                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
4275 {
4276         struct hns3_cmd_desc desc;
4277         uint8_t resp_code;
4278         uint16_t retval;
4279         int ret;
4280
4281         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
4282         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
4283
4284         ret = hns3_cmd_send(hw, &desc, 1);
4285         if (ret) {
4286                 PMD_INIT_LOG(ERR,
4287                              "add mac ethertype failed for cmd_send, ret =%d.",
4288                              ret);
4289                 return ret;
4290         }
4291
4292         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
4293         retval = rte_le_to_cpu_16(desc.retval);
4294
4295         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
4296 }
4297
4298 static void
4299 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
4300                      int *table_item_num)
4301 {
4302         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
4303
4304         /*
4305          * In current version, we add one item in management table as below:
4306          * 0x0180C200000E -- LLDP MC address
4307          */
4308         tbl = mgr_table;
4309         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
4310         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
4311         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
4312         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
4313         tbl->i_port_bitmap = 0x1;
4314         *table_item_num = 1;
4315 }
4316
4317 static int
4318 hns3_init_mgr_tbl(struct hns3_hw *hw)
4319 {
4320 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
4321         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
4322         int table_item_num;
4323         int ret;
4324         int i;
4325
4326         memset(mgr_table, 0, sizeof(mgr_table));
4327         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
4328         for (i = 0; i < table_item_num; i++) {
4329                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
4330                 if (ret) {
4331                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
4332                                      ret);
4333                         return ret;
4334                 }
4335         }
4336
4337         return 0;
4338 }
4339
4340 static void
4341 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
4342                         bool en_mc, bool en_bc, int vport_id)
4343 {
4344         if (!param)
4345                 return;
4346
4347         memset(param, 0, sizeof(struct hns3_promisc_param));
4348         if (en_uc)
4349                 param->enable = HNS3_PROMISC_EN_UC;
4350         if (en_mc)
4351                 param->enable |= HNS3_PROMISC_EN_MC;
4352         if (en_bc)
4353                 param->enable |= HNS3_PROMISC_EN_BC;
4354         param->vf_id = vport_id;
4355 }
4356
4357 static int
4358 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
4359 {
4360         struct hns3_promisc_cfg_cmd *req;
4361         struct hns3_cmd_desc desc;
4362         int ret;
4363
4364         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
4365
4366         req = (struct hns3_promisc_cfg_cmd *)desc.data;
4367         req->vf_id = param->vf_id;
4368         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
4369             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
4370
4371         ret = hns3_cmd_send(hw, &desc, 1);
4372         if (ret)
4373                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
4374
4375         return ret;
4376 }
4377
4378 static int
4379 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
4380 {
4381         struct hns3_promisc_param param;
4382         bool en_bc_pmc = true;
4383         uint8_t vf_id;
4384
4385         /*
4386          * In current version VF is not supported when PF is driven by DPDK
4387          * driver, just need to configure parameters for PF vport.
4388          */
4389         vf_id = HNS3_PF_FUNC_ID;
4390
4391         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
4392         return hns3_cmd_set_promisc_mode(hw, &param);
4393 }
4394
4395 static int
4396 hns3_promisc_init(struct hns3_hw *hw)
4397 {
4398         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
4399         struct hns3_pf *pf = &hns->pf;
4400         struct hns3_promisc_param param;
4401         uint16_t func_id;
4402         int ret;
4403
4404         ret = hns3_set_promisc_mode(hw, false, false);
4405         if (ret) {
4406                 PMD_INIT_LOG(ERR, "failed to set promisc mode, ret = %d", ret);
4407                 return ret;
4408         }
4409
4410         /*
4411          * In current version VFs are not supported when PF is driven by DPDK
4412          * driver. After PF has been taken over by DPDK, the original VF will
4413          * be invalid. So, there is a possibility of entry residues. It should
4414          * clear VFs's promisc mode to avoid unnecessary bandwidth usage
4415          * during init.
4416          */
4417         for (func_id = HNS3_1ST_VF_FUNC_ID; func_id < pf->func_num; func_id++) {
4418                 hns3_promisc_param_init(&param, false, false, false, func_id);
4419                 ret = hns3_cmd_set_promisc_mode(hw, &param);
4420                 if (ret) {
4421                         PMD_INIT_LOG(ERR, "failed to clear vf:%u promisc mode,"
4422                                         " ret = %d", func_id, ret);
4423                         return ret;
4424                 }
4425         }
4426
4427         return 0;
4428 }
4429
4430 static void
4431 hns3_promisc_uninit(struct hns3_hw *hw)
4432 {
4433         struct hns3_promisc_param param;
4434         uint16_t func_id;
4435         int ret;
4436
4437         func_id = HNS3_PF_FUNC_ID;
4438
4439         /*
4440          * In current version VFs are not supported when PF is driven by
4441          * DPDK driver, and VFs' promisc mode status has been cleared during
4442          * init and their status will not change. So just clear PF's promisc
4443          * mode status during uninit.
4444          */
4445         hns3_promisc_param_init(&param, false, false, false, func_id);
4446         ret = hns3_cmd_set_promisc_mode(hw, &param);
4447         if (ret)
4448                 PMD_INIT_LOG(ERR, "failed to clear promisc status during"
4449                                 " uninit, ret = %d", ret);
4450 }
4451
4452 static int
4453 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
4454 {
4455         bool allmulti = dev->data->all_multicast ? true : false;
4456         struct hns3_adapter *hns = dev->data->dev_private;
4457         struct hns3_hw *hw = &hns->hw;
4458         uint64_t offloads;
4459         int err;
4460         int ret;
4461
4462         rte_spinlock_lock(&hw->lock);
4463         ret = hns3_set_promisc_mode(hw, true, true);
4464         if (ret) {
4465                 rte_spinlock_unlock(&hw->lock);
4466                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
4467                          ret);
4468                 return ret;
4469         }
4470
4471         /*
4472          * When promiscuous mode was enabled, disable the vlan filter to let
4473          * all packets coming in in the receiving direction.
4474          */
4475         offloads = dev->data->dev_conf.rxmode.offloads;
4476         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4477                 ret = hns3_enable_vlan_filter(hns, false);
4478                 if (ret) {
4479                         hns3_err(hw, "failed to enable promiscuous mode due to "
4480                                      "failure to disable vlan filter, ret = %d",
4481                                  ret);
4482                         err = hns3_set_promisc_mode(hw, false, allmulti);
4483                         if (err)
4484                                 hns3_err(hw, "failed to restore promiscuous "
4485                                          "status after disable vlan filter "
4486                                          "failed during enabling promiscuous "
4487                                          "mode, ret = %d", ret);
4488                 }
4489         }
4490
4491         rte_spinlock_unlock(&hw->lock);
4492
4493         return ret;
4494 }
4495
4496 static int
4497 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
4498 {
4499         bool allmulti = dev->data->all_multicast ? true : false;
4500         struct hns3_adapter *hns = dev->data->dev_private;
4501         struct hns3_hw *hw = &hns->hw;
4502         uint64_t offloads;
4503         int err;
4504         int ret;
4505
4506         /* If now in all_multicast mode, must remain in all_multicast mode. */
4507         rte_spinlock_lock(&hw->lock);
4508         ret = hns3_set_promisc_mode(hw, false, allmulti);
4509         if (ret) {
4510                 rte_spinlock_unlock(&hw->lock);
4511                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
4512                          ret);
4513                 return ret;
4514         }
4515         /* when promiscuous mode was disabled, restore the vlan filter status */
4516         offloads = dev->data->dev_conf.rxmode.offloads;
4517         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
4518                 ret = hns3_enable_vlan_filter(hns, true);
4519                 if (ret) {
4520                         hns3_err(hw, "failed to disable promiscuous mode due to"
4521                                  " failure to restore vlan filter, ret = %d",
4522                                  ret);
4523                         err = hns3_set_promisc_mode(hw, true, true);
4524                         if (err)
4525                                 hns3_err(hw, "failed to restore promiscuous "
4526                                          "status after enabling vlan filter "
4527                                          "failed during disabling promiscuous "
4528                                          "mode, ret = %d", ret);
4529                 }
4530         }
4531         rte_spinlock_unlock(&hw->lock);
4532
4533         return ret;
4534 }
4535
4536 static int
4537 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
4538 {
4539         struct hns3_adapter *hns = dev->data->dev_private;
4540         struct hns3_hw *hw = &hns->hw;
4541         int ret;
4542
4543         if (dev->data->promiscuous)
4544                 return 0;
4545
4546         rte_spinlock_lock(&hw->lock);
4547         ret = hns3_set_promisc_mode(hw, false, true);
4548         rte_spinlock_unlock(&hw->lock);
4549         if (ret)
4550                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
4551                          ret);
4552
4553         return ret;
4554 }
4555
4556 static int
4557 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
4558 {
4559         struct hns3_adapter *hns = dev->data->dev_private;
4560         struct hns3_hw *hw = &hns->hw;
4561         int ret;
4562
4563         /* If now in promiscuous mode, must remain in all_multicast mode. */
4564         if (dev->data->promiscuous)
4565                 return 0;
4566
4567         rte_spinlock_lock(&hw->lock);
4568         ret = hns3_set_promisc_mode(hw, false, false);
4569         rte_spinlock_unlock(&hw->lock);
4570         if (ret)
4571                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
4572                          ret);
4573
4574         return ret;
4575 }
4576
4577 static int
4578 hns3_dev_promisc_restore(struct hns3_adapter *hns)
4579 {
4580         struct hns3_hw *hw = &hns->hw;
4581         bool allmulti = hw->data->all_multicast ? true : false;
4582         int ret;
4583
4584         if (hw->data->promiscuous) {
4585                 ret = hns3_set_promisc_mode(hw, true, true);
4586                 if (ret)
4587                         hns3_err(hw, "failed to restore promiscuous mode, "
4588                                  "ret = %d", ret);
4589                 return ret;
4590         }
4591
4592         ret = hns3_set_promisc_mode(hw, false, allmulti);
4593         if (ret)
4594                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
4595                          ret);
4596         return ret;
4597 }
4598
4599 static int
4600 hns3_get_sfp_info(struct hns3_hw *hw, struct hns3_mac *mac_info)
4601 {
4602         struct hns3_sfp_info_cmd *resp;
4603         struct hns3_cmd_desc desc;
4604         int ret;
4605
4606         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
4607         resp = (struct hns3_sfp_info_cmd *)desc.data;
4608         resp->query_type = HNS3_ACTIVE_QUERY;
4609
4610         ret = hns3_cmd_send(hw, &desc, 1);
4611         if (ret == -EOPNOTSUPP) {
4612                 hns3_warn(hw, "firmware does not support get SFP info,"
4613                           " ret = %d.", ret);
4614                 return ret;
4615         } else if (ret) {
4616                 hns3_err(hw, "get sfp info failed, ret = %d.", ret);
4617                 return ret;
4618         }
4619
4620         /*
4621          * In some case, the speed of MAC obtained from firmware may be 0, it
4622          * shouldn't be set to mac->speed.
4623          */
4624         if (!rte_le_to_cpu_32(resp->sfp_speed))
4625                 return 0;
4626
4627         mac_info->link_speed = rte_le_to_cpu_32(resp->sfp_speed);
4628         /*
4629          * if resp->supported_speed is 0, it means it's an old version
4630          * firmware, do not update these params.
4631          */
4632         if (resp->supported_speed) {
4633                 mac_info->query_type = HNS3_ACTIVE_QUERY;
4634                 mac_info->supported_speed =
4635                                         rte_le_to_cpu_32(resp->supported_speed);
4636                 mac_info->support_autoneg = resp->autoneg_ability;
4637                 mac_info->link_autoneg = (resp->autoneg == 0) ? ETH_LINK_FIXED
4638                                         : ETH_LINK_AUTONEG;
4639         } else {
4640                 mac_info->query_type = HNS3_DEFAULT_QUERY;
4641         }
4642
4643         return 0;
4644 }
4645
4646 static uint8_t
4647 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4648 {
4649         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4650                 duplex = ETH_LINK_FULL_DUPLEX;
4651
4652         return duplex;
4653 }
4654
4655 static int
4656 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4657 {
4658         struct hns3_mac *mac = &hw->mac;
4659         int ret;
4660
4661         duplex = hns3_check_speed_dup(duplex, speed);
4662         if (mac->link_speed == speed && mac->link_duplex == duplex)
4663                 return 0;
4664
4665         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4666         if (ret)
4667                 return ret;
4668
4669         ret = hns3_port_shaper_update(hw, speed);
4670         if (ret)
4671                 return ret;
4672
4673         mac->link_speed = speed;
4674         mac->link_duplex = duplex;
4675
4676         return 0;
4677 }
4678
4679 static int
4680 hns3_update_fiber_link_info(struct hns3_hw *hw)
4681 {
4682         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
4683         struct hns3_mac *mac = &hw->mac;
4684         struct hns3_mac mac_info;
4685         int ret;
4686
4687         /* If firmware do not support get SFP/qSFP speed, return directly */
4688         if (!pf->support_sfp_query)
4689                 return 0;
4690
4691         memset(&mac_info, 0, sizeof(struct hns3_mac));
4692         ret = hns3_get_sfp_info(hw, &mac_info);
4693         if (ret == -EOPNOTSUPP) {
4694                 pf->support_sfp_query = false;
4695                 return ret;
4696         } else if (ret)
4697                 return ret;
4698
4699         /* Do nothing if no SFP */
4700         if (mac_info.link_speed == ETH_SPEED_NUM_NONE)
4701                 return 0;
4702
4703         /*
4704          * If query_type is HNS3_ACTIVE_QUERY, it is no need
4705          * to reconfigure the speed of MAC. Otherwise, it indicates
4706          * that the current firmware only supports to obtain the
4707          * speed of the SFP, and the speed of MAC needs to reconfigure.
4708          */
4709         mac->query_type = mac_info.query_type;
4710         if (mac->query_type == HNS3_ACTIVE_QUERY) {
4711                 if (mac_info.link_speed != mac->link_speed) {
4712                         ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4713                         if (ret)
4714                                 return ret;
4715                 }
4716
4717                 mac->link_speed = mac_info.link_speed;
4718                 mac->supported_speed = mac_info.supported_speed;
4719                 mac->support_autoneg = mac_info.support_autoneg;
4720                 mac->link_autoneg = mac_info.link_autoneg;
4721
4722                 return 0;
4723         }
4724
4725         /* Config full duplex for SFP */
4726         return hns3_cfg_mac_speed_dup(hw, mac_info.link_speed,
4727                                       ETH_LINK_FULL_DUPLEX);
4728 }
4729
4730 static void
4731 hns3_parse_copper_phy_params(struct hns3_cmd_desc *desc, struct hns3_mac *mac)
4732 {
4733 #define HNS3_PHY_SUPPORTED_SPEED_MASK   0x2f
4734
4735         struct hns3_phy_params_bd0_cmd *req;
4736         uint32_t supported;
4737
4738         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
4739         mac->link_speed = rte_le_to_cpu_32(req->speed);
4740         mac->link_duplex = hns3_get_bit(req->duplex,
4741                                            HNS3_PHY_DUPLEX_CFG_B);
4742         mac->link_autoneg = hns3_get_bit(req->autoneg,
4743                                            HNS3_PHY_AUTONEG_CFG_B);
4744         mac->advertising = rte_le_to_cpu_32(req->advertising);
4745         mac->lp_advertising = rte_le_to_cpu_32(req->lp_advertising);
4746         supported = rte_le_to_cpu_32(req->supported);
4747         mac->supported_speed = supported & HNS3_PHY_SUPPORTED_SPEED_MASK;
4748         mac->support_autoneg = !!(supported & HNS3_PHY_LINK_MODE_AUTONEG_BIT);
4749 }
4750
4751 static int
4752 hns3_get_copper_phy_params(struct hns3_hw *hw, struct hns3_mac *mac)
4753 {
4754         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
4755         uint16_t i;
4756         int ret;
4757
4758         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
4759                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
4760                                           true);
4761                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
4762         }
4763         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, true);
4764
4765         ret = hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
4766         if (ret) {
4767                 hns3_err(hw, "get phy parameters failed, ret = %d.", ret);
4768                 return ret;
4769         }
4770
4771         hns3_parse_copper_phy_params(desc, mac);
4772
4773         return 0;
4774 }
4775
4776 static int
4777 hns3_update_copper_link_info(struct hns3_hw *hw)
4778 {
4779         struct hns3_mac *mac = &hw->mac;
4780         struct hns3_mac mac_info;
4781         int ret;
4782
4783         memset(&mac_info, 0, sizeof(struct hns3_mac));
4784         ret = hns3_get_copper_phy_params(hw, &mac_info);
4785         if (ret)
4786                 return ret;
4787
4788         if (mac_info.link_speed != mac->link_speed) {
4789                 ret = hns3_port_shaper_update(hw, mac_info.link_speed);
4790                 if (ret)
4791                         return ret;
4792         }
4793
4794         mac->link_speed = mac_info.link_speed;
4795         mac->link_duplex = mac_info.link_duplex;
4796         mac->link_autoneg = mac_info.link_autoneg;
4797         mac->supported_speed = mac_info.supported_speed;
4798         mac->advertising = mac_info.advertising;
4799         mac->lp_advertising = mac_info.lp_advertising;
4800         mac->support_autoneg = mac_info.support_autoneg;
4801
4802         return 0;
4803 }
4804
4805 static int
4806 hns3_update_link_info(struct rte_eth_dev *eth_dev)
4807 {
4808         struct hns3_adapter *hns = eth_dev->data->dev_private;
4809         struct hns3_hw *hw = &hns->hw;
4810         int ret = 0;
4811
4812         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER)
4813                 ret = hns3_update_copper_link_info(hw);
4814         else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER)
4815                 ret = hns3_update_fiber_link_info(hw);
4816
4817         return ret;
4818 }
4819
4820 static int
4821 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4822 {
4823         struct hns3_config_mac_mode_cmd *req;
4824         struct hns3_cmd_desc desc;
4825         uint32_t loop_en = 0;
4826         uint8_t val = 0;
4827         int ret;
4828
4829         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4830
4831         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4832         if (enable)
4833                 val = 1;
4834         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4835         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4836         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4837         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4838         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4839         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4840         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4841         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4842         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4843         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4844
4845         /*
4846          * If DEV_RX_OFFLOAD_KEEP_CRC offload is set, MAC will not strip CRC
4847          * when receiving frames. Otherwise, CRC will be stripped.
4848          */
4849         if (hw->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
4850                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, 0);
4851         else
4852                 hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4853         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4854         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4855         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4856         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4857
4858         ret = hns3_cmd_send(hw, &desc, 1);
4859         if (ret)
4860                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4861
4862         return ret;
4863 }
4864
4865 static int
4866 hns3_get_mac_link_status(struct hns3_hw *hw)
4867 {
4868         struct hns3_link_status_cmd *req;
4869         struct hns3_cmd_desc desc;
4870         int link_status;
4871         int ret;
4872
4873         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4874         ret = hns3_cmd_send(hw, &desc, 1);
4875         if (ret) {
4876                 hns3_err(hw, "get link status cmd failed %d", ret);
4877                 return ETH_LINK_DOWN;
4878         }
4879
4880         req = (struct hns3_link_status_cmd *)desc.data;
4881         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4882
4883         return !!link_status;
4884 }
4885
4886 static bool
4887 hns3_update_link_status(struct hns3_hw *hw)
4888 {
4889         int state;
4890
4891         state = hns3_get_mac_link_status(hw);
4892         if (state != hw->mac.link_status) {
4893                 hw->mac.link_status = state;
4894                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4895                 hns3_config_mac_tnl_int(hw,
4896                                         state == ETH_LINK_UP ? true : false);
4897                 return true;
4898         }
4899
4900         return false;
4901 }
4902
4903 void
4904 hns3_update_linkstatus_and_event(struct hns3_hw *hw, bool query)
4905 {
4906         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4907         struct rte_eth_link new_link;
4908         int ret;
4909
4910         if (query)
4911                 hns3_update_port_link_info(dev);
4912
4913         memset(&new_link, 0, sizeof(new_link));
4914         hns3_setup_linkstatus(dev, &new_link);
4915
4916         ret = rte_eth_linkstatus_set(dev, &new_link);
4917         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
4918                 hns3_start_report_lse(dev);
4919 }
4920
4921 static void
4922 hns3_service_handler(void *param)
4923 {
4924         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4925         struct hns3_adapter *hns = eth_dev->data->dev_private;
4926         struct hns3_hw *hw = &hns->hw;
4927
4928         if (!hns3_is_reset_pending(hns))
4929                 hns3_update_linkstatus_and_event(hw, true);
4930         else
4931                 hns3_warn(hw, "Cancel the query when reset is pending");
4932
4933         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4934 }
4935
4936 static int
4937 hns3_init_hardware(struct hns3_adapter *hns)
4938 {
4939         struct hns3_hw *hw = &hns->hw;
4940         int ret;
4941
4942         ret = hns3_map_tqp(hw);
4943         if (ret) {
4944                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4945                 return ret;
4946         }
4947
4948         ret = hns3_init_umv_space(hw);
4949         if (ret) {
4950                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4951                 return ret;
4952         }
4953
4954         ret = hns3_mac_init(hw);
4955         if (ret) {
4956                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4957                 goto err_mac_init;
4958         }
4959
4960         ret = hns3_init_mgr_tbl(hw);
4961         if (ret) {
4962                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4963                 goto err_mac_init;
4964         }
4965
4966         ret = hns3_promisc_init(hw);
4967         if (ret) {
4968                 PMD_INIT_LOG(ERR, "Failed to init promisc: %d",
4969                              ret);
4970                 goto err_mac_init;
4971         }
4972
4973         ret = hns3_init_vlan_config(hns);
4974         if (ret) {
4975                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4976                 goto err_mac_init;
4977         }
4978
4979         ret = hns3_dcb_init(hw);
4980         if (ret) {
4981                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4982                 goto err_mac_init;
4983         }
4984
4985         ret = hns3_init_fd_config(hns);
4986         if (ret) {
4987                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4988                 goto err_mac_init;
4989         }
4990
4991         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4992         if (ret) {
4993                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4994                 goto err_mac_init;
4995         }
4996
4997         ret = hns3_config_gro(hw, false);
4998         if (ret) {
4999                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
5000                 goto err_mac_init;
5001         }
5002
5003         /*
5004          * In the initialization clearing the all hardware mapping relationship
5005          * configurations between queues and interrupt vectors is needed, so
5006          * some error caused by the residual configurations, such as the
5007          * unexpected interrupt, can be avoid.
5008          */
5009         ret = hns3_init_ring_with_vector(hw);
5010         if (ret) {
5011                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
5012                 goto err_mac_init;
5013         }
5014
5015         return 0;
5016
5017 err_mac_init:
5018         hns3_uninit_umv_space(hw);
5019         return ret;
5020 }
5021
5022 static int
5023 hns3_clear_hw(struct hns3_hw *hw)
5024 {
5025         struct hns3_cmd_desc desc;
5026         int ret;
5027
5028         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CLEAR_HW_STATE, false);
5029
5030         ret = hns3_cmd_send(hw, &desc, 1);
5031         if (ret && ret != -EOPNOTSUPP)
5032                 return ret;
5033
5034         return 0;
5035 }
5036
5037 static void
5038 hns3_config_all_msix_error(struct hns3_hw *hw, bool enable)
5039 {
5040         uint32_t val;
5041
5042         /*
5043          * The new firmware support report more hardware error types by
5044          * msix mode. These errors are defined as RAS errors in hardware
5045          * and belong to a different type from the MSI-x errors processed
5046          * by the network driver.
5047          *
5048          * Network driver should open the new error report on initialition
5049          */
5050         val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5051         hns3_set_bit(val, HNS3_VECTOR0_ALL_MSIX_ERR_B, enable ? 1 : 0);
5052         hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, val);
5053 }
5054
5055 static uint32_t
5056 hns3_set_firber_default_support_speed(struct hns3_hw *hw)
5057 {
5058         struct hns3_mac *mac = &hw->mac;
5059
5060         switch (mac->link_speed) {
5061         case ETH_SPEED_NUM_1G:
5062                 return HNS3_FIBER_LINK_SPEED_1G_BIT;
5063         case ETH_SPEED_NUM_10G:
5064                 return HNS3_FIBER_LINK_SPEED_10G_BIT;
5065         case ETH_SPEED_NUM_25G:
5066                 return HNS3_FIBER_LINK_SPEED_25G_BIT;
5067         case ETH_SPEED_NUM_40G:
5068                 return HNS3_FIBER_LINK_SPEED_40G_BIT;
5069         case ETH_SPEED_NUM_50G:
5070                 return HNS3_FIBER_LINK_SPEED_50G_BIT;
5071         case ETH_SPEED_NUM_100G:
5072                 return HNS3_FIBER_LINK_SPEED_100G_BIT;
5073         case ETH_SPEED_NUM_200G:
5074                 return HNS3_FIBER_LINK_SPEED_200G_BIT;
5075         default:
5076                 hns3_warn(hw, "invalid speed %u Mbps.", mac->link_speed);
5077                 return 0;
5078         }
5079 }
5080
5081 /*
5082  * Validity of supported_speed for firber and copper media type can be
5083  * guaranteed by the following policy:
5084  * Copper:
5085  *       Although the initialization of the phy in the firmware may not be
5086  *       completed, the firmware can guarantees that the supported_speed is
5087  *       an valid value.
5088  * Firber:
5089  *       If the version of firmware supports the acitive query way of the
5090  *       HNS3_OPC_GET_SFP_INFO opcode, the supported_speed can be obtained
5091  *       through it. If unsupported, use the SFP's speed as the value of the
5092  *       supported_speed.
5093  */
5094 static int
5095 hns3_get_port_supported_speed(struct rte_eth_dev *eth_dev)
5096 {
5097         struct hns3_adapter *hns = eth_dev->data->dev_private;
5098         struct hns3_hw *hw = &hns->hw;
5099         struct hns3_mac *mac = &hw->mac;
5100         int ret;
5101
5102         ret = hns3_update_link_info(eth_dev);
5103         if (ret)
5104                 return ret;
5105
5106         if (mac->media_type == HNS3_MEDIA_TYPE_FIBER) {
5107                 /*
5108                  * Some firmware does not support the report of supported_speed,
5109                  * and only report the effective speed of SFP. In this case, it
5110                  * is necessary to use the SFP's speed as the supported_speed.
5111                  */
5112                 if (mac->supported_speed == 0)
5113                         mac->supported_speed =
5114                                 hns3_set_firber_default_support_speed(hw);
5115         }
5116
5117         return 0;
5118 }
5119
5120 static void
5121 hns3_get_fc_autoneg_capability(struct hns3_adapter *hns)
5122 {
5123         struct hns3_mac *mac = &hns->hw.mac;
5124
5125         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER) {
5126                 hns->pf.support_fc_autoneg = true;
5127                 return;
5128         }
5129
5130         /*
5131          * Flow control auto-negotiation requires the cooperation of the driver
5132          * and firmware. Currently, the optical port does not support flow
5133          * control auto-negotiation.
5134          */
5135         hns->pf.support_fc_autoneg = false;
5136 }
5137
5138 static int
5139 hns3_init_pf(struct rte_eth_dev *eth_dev)
5140 {
5141         struct rte_device *dev = eth_dev->device;
5142         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5143         struct hns3_adapter *hns = eth_dev->data->dev_private;
5144         struct hns3_hw *hw = &hns->hw;
5145         int ret;
5146
5147         PMD_INIT_FUNC_TRACE();
5148
5149         /* Get hardware io base address from pcie BAR2 IO space */
5150         hw->io_base = pci_dev->mem_resource[2].addr;
5151
5152         /* Firmware command queue initialize */
5153         ret = hns3_cmd_init_queue(hw);
5154         if (ret) {
5155                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
5156                 goto err_cmd_init_queue;
5157         }
5158
5159         hns3_clear_all_event_cause(hw);
5160
5161         /* Firmware command initialize */
5162         ret = hns3_cmd_init(hw);
5163         if (ret) {
5164                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
5165                 goto err_cmd_init;
5166         }
5167
5168         /*
5169          * To ensure that the hardware environment is clean during
5170          * initialization, the driver actively clear the hardware environment
5171          * during initialization, including PF and corresponding VFs' vlan, mac,
5172          * flow table configurations, etc.
5173          */
5174         ret = hns3_clear_hw(hw);
5175         if (ret) {
5176                 PMD_INIT_LOG(ERR, "failed to clear hardware: %d", ret);
5177                 goto err_cmd_init;
5178         }
5179
5180         /* Hardware statistics of imissed registers cleared. */
5181         ret = hns3_update_imissed_stats(hw, true);
5182         if (ret) {
5183                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
5184                 goto err_cmd_init;
5185         }
5186
5187         hns3_config_all_msix_error(hw, true);
5188
5189         ret = rte_intr_callback_register(&pci_dev->intr_handle,
5190                                          hns3_interrupt_handler,
5191                                          eth_dev);
5192         if (ret) {
5193                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
5194                 goto err_intr_callback_register;
5195         }
5196
5197         ret = hns3_ptp_init(hw);
5198         if (ret)
5199                 goto err_get_config;
5200
5201         /* Enable interrupt */
5202         rte_intr_enable(&pci_dev->intr_handle);
5203         hns3_pf_enable_irq0(hw);
5204
5205         /* Get configuration */
5206         ret = hns3_get_configuration(hw);
5207         if (ret) {
5208                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
5209                 goto err_get_config;
5210         }
5211
5212         ret = hns3_tqp_stats_init(hw);
5213         if (ret)
5214                 goto err_get_config;
5215
5216         ret = hns3_init_hardware(hns);
5217         if (ret) {
5218                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
5219                 goto err_init_hw;
5220         }
5221
5222         /* Initialize flow director filter list & hash */
5223         ret = hns3_fdir_filter_init(hns);
5224         if (ret) {
5225                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
5226                 goto err_fdir;
5227         }
5228
5229         hns3_rss_set_default_args(hw);
5230
5231         ret = hns3_enable_hw_error_intr(hns, true);
5232         if (ret) {
5233                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
5234                              ret);
5235                 goto err_enable_intr;
5236         }
5237
5238         ret = hns3_get_port_supported_speed(eth_dev);
5239         if (ret) {
5240                 PMD_INIT_LOG(ERR, "failed to get speed capabilities supported "
5241                              "by device, ret = %d.", ret);
5242                 goto err_supported_speed;
5243         }
5244
5245         hns3_get_fc_autoneg_capability(hns);
5246
5247         hns3_tm_conf_init(eth_dev);
5248
5249         return 0;
5250
5251 err_supported_speed:
5252         (void)hns3_enable_hw_error_intr(hns, false);
5253 err_enable_intr:
5254         hns3_fdir_filter_uninit(hns);
5255 err_fdir:
5256         hns3_uninit_umv_space(hw);
5257 err_init_hw:
5258         hns3_tqp_stats_uninit(hw);
5259 err_get_config:
5260         hns3_pf_disable_irq0(hw);
5261         rte_intr_disable(&pci_dev->intr_handle);
5262         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5263                              eth_dev);
5264 err_intr_callback_register:
5265 err_cmd_init:
5266         hns3_cmd_uninit(hw);
5267         hns3_cmd_destroy_queue(hw);
5268 err_cmd_init_queue:
5269         hw->io_base = NULL;
5270
5271         return ret;
5272 }
5273
5274 static void
5275 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
5276 {
5277         struct hns3_adapter *hns = eth_dev->data->dev_private;
5278         struct rte_device *dev = eth_dev->device;
5279         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5280         struct hns3_hw *hw = &hns->hw;
5281
5282         PMD_INIT_FUNC_TRACE();
5283
5284         hns3_tm_conf_uninit(eth_dev);
5285         hns3_enable_hw_error_intr(hns, false);
5286         hns3_rss_uninit(hns);
5287         (void)hns3_config_gro(hw, false);
5288         hns3_promisc_uninit(hw);
5289         hns3_fdir_filter_uninit(hns);
5290         hns3_uninit_umv_space(hw);
5291         hns3_tqp_stats_uninit(hw);
5292         hns3_config_mac_tnl_int(hw, false);
5293         hns3_pf_disable_irq0(hw);
5294         rte_intr_disable(&pci_dev->intr_handle);
5295         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
5296                              eth_dev);
5297         hns3_config_all_msix_error(hw, false);
5298         hns3_cmd_uninit(hw);
5299         hns3_cmd_destroy_queue(hw);
5300         hw->io_base = NULL;
5301 }
5302
5303 static uint32_t
5304 hns3_convert_link_speeds2bitmap_copper(uint32_t link_speeds)
5305 {
5306         uint32_t speed_bit;
5307
5308         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5309         case ETH_LINK_SPEED_10M:
5310                 speed_bit = HNS3_PHY_LINK_SPEED_10M_BIT;
5311                 break;
5312         case ETH_LINK_SPEED_10M_HD:
5313                 speed_bit = HNS3_PHY_LINK_SPEED_10M_HD_BIT;
5314                 break;
5315         case ETH_LINK_SPEED_100M:
5316                 speed_bit = HNS3_PHY_LINK_SPEED_100M_BIT;
5317                 break;
5318         case ETH_LINK_SPEED_100M_HD:
5319                 speed_bit = HNS3_PHY_LINK_SPEED_100M_HD_BIT;
5320                 break;
5321         case ETH_LINK_SPEED_1G:
5322                 speed_bit = HNS3_PHY_LINK_SPEED_1000M_BIT;
5323                 break;
5324         default:
5325                 speed_bit = 0;
5326                 break;
5327         }
5328
5329         return speed_bit;
5330 }
5331
5332 static uint32_t
5333 hns3_convert_link_speeds2bitmap_fiber(uint32_t link_speeds)
5334 {
5335         uint32_t speed_bit;
5336
5337         switch (link_speeds & ~ETH_LINK_SPEED_FIXED) {
5338         case ETH_LINK_SPEED_1G:
5339                 speed_bit = HNS3_FIBER_LINK_SPEED_1G_BIT;
5340                 break;
5341         case ETH_LINK_SPEED_10G:
5342                 speed_bit = HNS3_FIBER_LINK_SPEED_10G_BIT;
5343                 break;
5344         case ETH_LINK_SPEED_25G:
5345                 speed_bit = HNS3_FIBER_LINK_SPEED_25G_BIT;
5346                 break;
5347         case ETH_LINK_SPEED_40G:
5348                 speed_bit = HNS3_FIBER_LINK_SPEED_40G_BIT;
5349                 break;
5350         case ETH_LINK_SPEED_50G:
5351                 speed_bit = HNS3_FIBER_LINK_SPEED_50G_BIT;
5352                 break;
5353         case ETH_LINK_SPEED_100G:
5354                 speed_bit = HNS3_FIBER_LINK_SPEED_100G_BIT;
5355                 break;
5356         case ETH_LINK_SPEED_200G:
5357                 speed_bit = HNS3_FIBER_LINK_SPEED_200G_BIT;
5358                 break;
5359         default:
5360                 speed_bit = 0;
5361                 break;
5362         }
5363
5364         return speed_bit;
5365 }
5366
5367 static int
5368 hns3_check_port_speed(struct hns3_hw *hw, uint32_t link_speeds)
5369 {
5370         struct hns3_mac *mac = &hw->mac;
5371         uint32_t supported_speed = mac->supported_speed;
5372         uint32_t speed_bit = 0;
5373
5374         if (mac->media_type == HNS3_MEDIA_TYPE_COPPER)
5375                 speed_bit = hns3_convert_link_speeds2bitmap_copper(link_speeds);
5376         else if (mac->media_type == HNS3_MEDIA_TYPE_FIBER)
5377                 speed_bit = hns3_convert_link_speeds2bitmap_fiber(link_speeds);
5378
5379         if (!(speed_bit & supported_speed)) {
5380                 hns3_err(hw, "link_speeds(0x%x) exceeds the supported speed capability or is incorrect.",
5381                          link_speeds);
5382                 return -EINVAL;
5383         }
5384
5385         return 0;
5386 }
5387
5388 static inline uint32_t
5389 hns3_get_link_speed(uint32_t link_speeds)
5390 {
5391         uint32_t speed = ETH_SPEED_NUM_NONE;
5392
5393         if (link_speeds & ETH_LINK_SPEED_10M ||
5394             link_speeds & ETH_LINK_SPEED_10M_HD)
5395                 speed = ETH_SPEED_NUM_10M;
5396         if (link_speeds & ETH_LINK_SPEED_100M ||
5397             link_speeds & ETH_LINK_SPEED_100M_HD)
5398                 speed = ETH_SPEED_NUM_100M;
5399         if (link_speeds & ETH_LINK_SPEED_1G)
5400                 speed = ETH_SPEED_NUM_1G;
5401         if (link_speeds & ETH_LINK_SPEED_10G)
5402                 speed = ETH_SPEED_NUM_10G;
5403         if (link_speeds & ETH_LINK_SPEED_25G)
5404                 speed = ETH_SPEED_NUM_25G;
5405         if (link_speeds & ETH_LINK_SPEED_40G)
5406                 speed = ETH_SPEED_NUM_40G;
5407         if (link_speeds & ETH_LINK_SPEED_50G)
5408                 speed = ETH_SPEED_NUM_50G;
5409         if (link_speeds & ETH_LINK_SPEED_100G)
5410                 speed = ETH_SPEED_NUM_100G;
5411         if (link_speeds & ETH_LINK_SPEED_200G)
5412                 speed = ETH_SPEED_NUM_200G;
5413
5414         return speed;
5415 }
5416
5417 static uint8_t
5418 hns3_get_link_duplex(uint32_t link_speeds)
5419 {
5420         if ((link_speeds & ETH_LINK_SPEED_10M_HD) ||
5421             (link_speeds & ETH_LINK_SPEED_100M_HD))
5422                 return ETH_LINK_HALF_DUPLEX;
5423         else
5424                 return ETH_LINK_FULL_DUPLEX;
5425 }
5426
5427 static int
5428 hns3_set_copper_port_link_speed(struct hns3_hw *hw,
5429                                 struct hns3_set_link_speed_cfg *cfg)
5430 {
5431         struct hns3_cmd_desc desc[HNS3_PHY_PARAM_CFG_BD_NUM];
5432         struct hns3_phy_params_bd0_cmd *req;
5433         uint16_t i;
5434
5435         for (i = 0; i < HNS3_PHY_PARAM_CFG_BD_NUM - 1; i++) {
5436                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG,
5437                                           false);
5438                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
5439         }
5440         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_PHY_PARAM_CFG, false);
5441         req = (struct hns3_phy_params_bd0_cmd *)desc[0].data;
5442         req->autoneg = cfg->autoneg;
5443
5444         /*
5445          * The full speed capability is used to negotiate when
5446          * auto-negotiation is enabled.
5447          */
5448         if (cfg->autoneg) {
5449                 req->advertising = HNS3_PHY_LINK_SPEED_10M_BIT |
5450                                     HNS3_PHY_LINK_SPEED_10M_HD_BIT |
5451                                     HNS3_PHY_LINK_SPEED_100M_BIT |
5452                                     HNS3_PHY_LINK_SPEED_100M_HD_BIT |
5453                                     HNS3_PHY_LINK_SPEED_1000M_BIT;
5454         } else {
5455                 req->speed = cfg->speed;
5456                 req->duplex = cfg->duplex;
5457         }
5458
5459         return hns3_cmd_send(hw, desc, HNS3_PHY_PARAM_CFG_BD_NUM);
5460 }
5461
5462 static int
5463 hns3_set_autoneg(struct hns3_hw *hw, bool enable)
5464 {
5465         struct hns3_config_auto_neg_cmd *req;
5466         struct hns3_cmd_desc desc;
5467         uint32_t flag = 0;
5468         int ret;
5469
5470         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_AN_MODE, false);
5471
5472         req = (struct hns3_config_auto_neg_cmd *)desc.data;
5473         if (enable)
5474                 hns3_set_bit(flag, HNS3_MAC_CFG_AN_EN_B, 1);
5475         req->cfg_an_cmd_flag = rte_cpu_to_le_32(flag);
5476
5477         ret = hns3_cmd_send(hw, &desc, 1);
5478         if (ret)
5479                 hns3_err(hw, "autoneg set cmd failed, ret = %d.", ret);
5480
5481         return ret;
5482 }
5483
5484 static int
5485 hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
5486                                struct hns3_set_link_speed_cfg *cfg)
5487 {
5488         int ret;
5489
5490         if (hw->mac.support_autoneg) {
5491                 ret = hns3_set_autoneg(hw, cfg->autoneg);
5492                 if (ret) {
5493                         hns3_err(hw, "failed to configure auto-negotiation.");
5494                         return ret;
5495                 }
5496
5497                 /*
5498                  * To enable auto-negotiation, we only need to open the switch
5499                  * of auto-negotiation, then firmware sets all speed
5500                  * capabilities.
5501                  */
5502                 if (cfg->autoneg)
5503                         return 0;
5504         }
5505
5506         /*
5507          * Some hardware doesn't support auto-negotiation, but users may not
5508          * configure link_speeds (default 0), which means auto-negotiation.
5509          * In this case, it should return success.
5510          */
5511         if (cfg->autoneg)
5512                 return 0;
5513
5514         return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
5515 }
5516
5517 static int
5518 hns3_set_port_link_speed(struct hns3_hw *hw,
5519                          struct hns3_set_link_speed_cfg *cfg)
5520 {
5521         int ret;
5522
5523         if (hw->mac.media_type == HNS3_MEDIA_TYPE_COPPER) {
5524 #if defined(RTE_HNS3_ONLY_1630_FPGA)
5525                 struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
5526                 if (pf->is_tmp_phy)
5527                         return 0;
5528 #endif
5529
5530                 ret = hns3_set_copper_port_link_speed(hw, cfg);
5531                 if (ret) {
5532                         hns3_err(hw, "failed to set copper port link speed,"
5533                                  "ret = %d.", ret);
5534                         return ret;
5535                 }
5536         } else if (hw->mac.media_type == HNS3_MEDIA_TYPE_FIBER) {
5537                 ret = hns3_set_fiber_port_link_speed(hw, cfg);
5538                 if (ret) {
5539                         hns3_err(hw, "failed to set fiber port link speed,"
5540                                  "ret = %d.", ret);
5541                         return ret;
5542                 }
5543         }
5544
5545         return 0;
5546 }
5547
5548 static int
5549 hns3_apply_link_speed(struct hns3_hw *hw)
5550 {
5551         struct rte_eth_conf *conf = &hw->data->dev_conf;
5552         struct hns3_set_link_speed_cfg cfg;
5553
5554         memset(&cfg, 0, sizeof(struct hns3_set_link_speed_cfg));
5555         cfg.autoneg = (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) ?
5556                         ETH_LINK_AUTONEG : ETH_LINK_FIXED;
5557         if (cfg.autoneg != ETH_LINK_AUTONEG) {
5558                 cfg.speed = hns3_get_link_speed(conf->link_speeds);
5559                 cfg.duplex = hns3_get_link_duplex(conf->link_speeds);
5560         }
5561
5562         return hns3_set_port_link_speed(hw, &cfg);
5563 }
5564
5565 static int
5566 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
5567 {
5568         struct hns3_hw *hw = &hns->hw;
5569         int ret;
5570
5571         ret = hns3_dcb_cfg_update(hns);
5572         if (ret)
5573                 return ret;
5574
5575         /*
5576          * The hns3_dcb_cfg_update may configure TM module, so
5577          * hns3_tm_conf_update must called later.
5578          */
5579         ret = hns3_tm_conf_update(hw);
5580         if (ret) {
5581                 PMD_INIT_LOG(ERR, "failed to update tm conf, ret = %d.", ret);
5582                 return ret;
5583         }
5584
5585         hns3_enable_rxd_adv_layout(hw);
5586
5587         ret = hns3_init_queues(hns, reset_queue);
5588         if (ret) {
5589                 PMD_INIT_LOG(ERR, "failed to init queues, ret = %d.", ret);
5590                 return ret;
5591         }
5592
5593         ret = hns3_cfg_mac_mode(hw, true);
5594         if (ret) {
5595                 PMD_INIT_LOG(ERR, "failed to enable MAC, ret = %d", ret);
5596                 goto err_config_mac_mode;
5597         }
5598
5599         ret = hns3_apply_link_speed(hw);
5600         if (ret)
5601                 goto err_config_mac_mode;
5602
5603         return 0;
5604
5605 err_config_mac_mode:
5606         (void)hns3_cfg_mac_mode(hw, false);
5607         hns3_dev_release_mbufs(hns);
5608         /*
5609          * Here is exception handling, hns3_reset_all_tqps will have the
5610          * corresponding error message if it is handled incorrectly, so it is
5611          * not necessary to check hns3_reset_all_tqps return value, here keep
5612          * ret as the error code causing the exception.
5613          */
5614         (void)hns3_reset_all_tqps(hns);
5615         return ret;
5616 }
5617
5618 static int
5619 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
5620 {
5621         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5622         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5623         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5624         uint16_t base = RTE_INTR_VEC_ZERO_OFFSET;
5625         uint16_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5626         uint32_t intr_vector;
5627         uint16_t q_id;
5628         int ret;
5629
5630         /*
5631          * hns3 needs a separate interrupt to be used as event interrupt which
5632          * could not be shared with task queue pair, so KERNEL drivers need
5633          * support multiple interrupt vectors.
5634          */
5635         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
5636             !rte_intr_cap_multiple(intr_handle))
5637                 return 0;
5638
5639         rte_intr_disable(intr_handle);
5640         intr_vector = hw->used_rx_queues;
5641         /* creates event fd for each intr vector when MSIX is used */
5642         if (rte_intr_efd_enable(intr_handle, intr_vector))
5643                 return -EINVAL;
5644
5645         if (intr_handle->intr_vec == NULL) {
5646                 intr_handle->intr_vec =
5647                         rte_zmalloc("intr_vec",
5648                                     hw->used_rx_queues * sizeof(int), 0);
5649                 if (intr_handle->intr_vec == NULL) {
5650                         hns3_err(hw, "failed to allocate %u rx_queues intr_vec",
5651                                         hw->used_rx_queues);
5652                         ret = -ENOMEM;
5653                         goto alloc_intr_vec_error;
5654                 }
5655         }
5656
5657         if (rte_intr_allow_others(intr_handle)) {
5658                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5659                 base = RTE_INTR_VEC_RXTX_OFFSET;
5660         }
5661
5662         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5663                 ret = hns3_bind_ring_with_vector(hw, vec, true,
5664                                                  HNS3_RING_TYPE_RX, q_id);
5665                 if (ret)
5666                         goto bind_vector_error;
5667                 intr_handle->intr_vec[q_id] = vec;
5668                 /*
5669                  * If there are not enough efds (e.g. not enough interrupt),
5670                  * remaining queues will be bond to the last interrupt.
5671                  */
5672                 if (vec < base + intr_handle->nb_efd - 1)
5673                         vec++;
5674         }
5675         rte_intr_enable(intr_handle);
5676         return 0;
5677
5678 bind_vector_error:
5679         rte_free(intr_handle->intr_vec);
5680         intr_handle->intr_vec = NULL;
5681 alloc_intr_vec_error:
5682         rte_intr_efd_disable(intr_handle);
5683         return ret;
5684 }
5685
5686 static int
5687 hns3_restore_rx_interrupt(struct hns3_hw *hw)
5688 {
5689         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
5690         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5691         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5692         uint16_t q_id;
5693         int ret;
5694
5695         if (dev->data->dev_conf.intr_conf.rxq == 0)
5696                 return 0;
5697
5698         if (rte_intr_dp_is_en(intr_handle)) {
5699                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5700                         ret = hns3_bind_ring_with_vector(hw,
5701                                         intr_handle->intr_vec[q_id], true,
5702                                         HNS3_RING_TYPE_RX, q_id);
5703                         if (ret)
5704                                 return ret;
5705                 }
5706         }
5707
5708         return 0;
5709 }
5710
5711 static void
5712 hns3_restore_filter(struct rte_eth_dev *dev)
5713 {
5714         hns3_restore_rss_filter(dev);
5715 }
5716
5717 static int
5718 hns3_dev_start(struct rte_eth_dev *dev)
5719 {
5720         struct hns3_adapter *hns = dev->data->dev_private;
5721         struct hns3_hw *hw = &hns->hw;
5722         int ret;
5723
5724         PMD_INIT_FUNC_TRACE();
5725         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
5726                 return -EBUSY;
5727
5728         rte_spinlock_lock(&hw->lock);
5729         hw->adapter_state = HNS3_NIC_STARTING;
5730
5731         ret = hns3_do_start(hns, true);
5732         if (ret) {
5733                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5734                 rte_spinlock_unlock(&hw->lock);
5735                 return ret;
5736         }
5737         ret = hns3_map_rx_interrupt(dev);
5738         if (ret)
5739                 goto map_rx_inter_err;
5740
5741         /*
5742          * There are three register used to control the status of a TQP
5743          * (contains a pair of Tx queue and Rx queue) in the new version network
5744          * engine. One is used to control the enabling of Tx queue, the other is
5745          * used to control the enabling of Rx queue, and the last is the master
5746          * switch used to control the enabling of the tqp. The Tx register and
5747          * TQP register must be enabled at the same time to enable a Tx queue.
5748          * The same applies to the Rx queue. For the older network engine, this
5749          * function only refresh the enabled flag, and it is used to update the
5750          * status of queue in the dpdk framework.
5751          */
5752         ret = hns3_start_all_txqs(dev);
5753         if (ret)
5754                 goto map_rx_inter_err;
5755
5756         ret = hns3_start_all_rxqs(dev);
5757         if (ret)
5758                 goto start_all_rxqs_fail;
5759
5760         hw->adapter_state = HNS3_NIC_STARTED;
5761         rte_spinlock_unlock(&hw->lock);
5762
5763         hns3_rx_scattered_calc(dev);
5764         hns3_set_rxtx_function(dev);
5765         hns3_mp_req_start_rxtx(dev);
5766
5767         hns3_restore_filter(dev);
5768
5769         /* Enable interrupt of all rx queues before enabling queues */
5770         hns3_dev_all_rx_queue_intr_enable(hw, true);
5771
5772         /*
5773          * After finished the initialization, enable tqps to receive/transmit
5774          * packets and refresh all queue status.
5775          */
5776         hns3_start_tqps(hw);
5777
5778         hns3_tm_dev_start_proc(hw);
5779
5780         if (dev->data->dev_conf.intr_conf.lsc != 0)
5781                 hns3_dev_link_update(dev, 0);
5782         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
5783
5784         hns3_info(hw, "hns3 dev start successful!");
5785
5786         return 0;
5787
5788 start_all_rxqs_fail:
5789         hns3_stop_all_txqs(dev);
5790 map_rx_inter_err:
5791         (void)hns3_do_stop(hns);
5792         hw->adapter_state = HNS3_NIC_CONFIGURED;
5793         rte_spinlock_unlock(&hw->lock);
5794
5795         return ret;
5796 }
5797
5798 static int
5799 hns3_do_stop(struct hns3_adapter *hns)
5800 {
5801         struct hns3_hw *hw = &hns->hw;
5802         int ret;
5803
5804         /*
5805          * The "hns3_do_stop" function will also be called by .stop_service to
5806          * prepare reset. At the time of global or IMP reset, the command cannot
5807          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
5808          * accessed during the reset process. So the mbuf can not be released
5809          * during reset and is required to be released after the reset is
5810          * completed.
5811          */
5812         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
5813                 hns3_dev_release_mbufs(hns);
5814
5815         ret = hns3_cfg_mac_mode(hw, false);
5816         if (ret)
5817                 return ret;
5818         hw->mac.link_status = ETH_LINK_DOWN;
5819
5820         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
5821                 hns3_configure_all_mac_addr(hns, true);
5822                 ret = hns3_reset_all_tqps(hns);
5823                 if (ret) {
5824                         hns3_err(hw, "failed to reset all queues ret = %d.",
5825                                  ret);
5826                         return ret;
5827                 }
5828         }
5829         hw->mac.default_addr_setted = false;
5830         return 0;
5831 }
5832
5833 static void
5834 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
5835 {
5836         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5837         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5838         struct hns3_adapter *hns = dev->data->dev_private;
5839         struct hns3_hw *hw = &hns->hw;
5840         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
5841         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
5842         uint16_t q_id;
5843
5844         if (dev->data->dev_conf.intr_conf.rxq == 0)
5845                 return;
5846
5847         /* unmap the ring with vector */
5848         if (rte_intr_allow_others(intr_handle)) {
5849                 vec = RTE_INTR_VEC_RXTX_OFFSET;
5850                 base = RTE_INTR_VEC_RXTX_OFFSET;
5851         }
5852         if (rte_intr_dp_is_en(intr_handle)) {
5853                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
5854                         (void)hns3_bind_ring_with_vector(hw, vec, false,
5855                                                          HNS3_RING_TYPE_RX,
5856                                                          q_id);
5857                         if (vec < base + intr_handle->nb_efd - 1)
5858                                 vec++;
5859                 }
5860         }
5861         /* Clean datapath event and queue/vec mapping */
5862         rte_intr_efd_disable(intr_handle);
5863         if (intr_handle->intr_vec) {
5864                 rte_free(intr_handle->intr_vec);
5865                 intr_handle->intr_vec = NULL;
5866         }
5867 }
5868
5869 static int
5870 hns3_dev_stop(struct rte_eth_dev *dev)
5871 {
5872         struct hns3_adapter *hns = dev->data->dev_private;
5873         struct hns3_hw *hw = &hns->hw;
5874
5875         PMD_INIT_FUNC_TRACE();
5876         dev->data->dev_started = 0;
5877
5878         hw->adapter_state = HNS3_NIC_STOPPING;
5879         hns3_set_rxtx_function(dev);
5880         rte_wmb();
5881         /* Disable datapath on secondary process. */
5882         hns3_mp_req_stop_rxtx(dev);
5883         /* Prevent crashes when queues are still in use. */
5884         rte_delay_ms(hw->tqps_num);
5885
5886         rte_spinlock_lock(&hw->lock);
5887         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
5888                 hns3_tm_dev_stop_proc(hw);
5889                 hns3_config_mac_tnl_int(hw, false);
5890                 hns3_stop_tqps(hw);
5891                 hns3_do_stop(hns);
5892                 hns3_unmap_rx_interrupt(dev);
5893                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5894         }
5895         hns3_rx_scattered_reset(dev);
5896         rte_eal_alarm_cancel(hns3_service_handler, dev);
5897         hns3_stop_report_lse(dev);
5898         rte_spinlock_unlock(&hw->lock);
5899
5900         return 0;
5901 }
5902
5903 static int
5904 hns3_dev_close(struct rte_eth_dev *eth_dev)
5905 {
5906         struct hns3_adapter *hns = eth_dev->data->dev_private;
5907         struct hns3_hw *hw = &hns->hw;
5908         int ret = 0;
5909
5910         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5911                 rte_free(eth_dev->process_private);
5912                 eth_dev->process_private = NULL;
5913                 return 0;
5914         }
5915
5916         if (hw->adapter_state == HNS3_NIC_STARTED)
5917                 ret = hns3_dev_stop(eth_dev);
5918
5919         hw->adapter_state = HNS3_NIC_CLOSING;
5920         hns3_reset_abort(hns);
5921         hw->adapter_state = HNS3_NIC_CLOSED;
5922
5923         hns3_configure_all_mc_mac_addr(hns, true);
5924         hns3_remove_all_vlan_table(hns);
5925         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
5926         hns3_uninit_pf(eth_dev);
5927         hns3_free_all_queues(eth_dev);
5928         rte_free(hw->reset.wait_data);
5929         rte_free(eth_dev->process_private);
5930         eth_dev->process_private = NULL;
5931         hns3_mp_uninit_primary();
5932         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
5933
5934         return ret;
5935 }
5936
5937 static void
5938 hns3_get_autoneg_rxtx_pause_copper(struct hns3_hw *hw, bool *rx_pause,
5939                                    bool *tx_pause)
5940 {
5941         struct hns3_mac *mac = &hw->mac;
5942         uint32_t advertising = mac->advertising;
5943         uint32_t lp_advertising = mac->lp_advertising;
5944         *rx_pause = false;
5945         *tx_pause = false;
5946
5947         if (advertising & lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT) {
5948                 *rx_pause = true;
5949                 *tx_pause = true;
5950         } else if (advertising & lp_advertising &
5951                    HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT) {
5952                 if (advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5953                         *rx_pause = true;
5954                 else if (lp_advertising & HNS3_PHY_LINK_MODE_PAUSE_BIT)
5955                         *tx_pause = true;
5956         }
5957 }
5958
5959 static enum hns3_fc_mode
5960 hns3_get_autoneg_fc_mode(struct hns3_hw *hw)
5961 {
5962         enum hns3_fc_mode current_mode;
5963         bool rx_pause = false;
5964         bool tx_pause = false;
5965
5966         switch (hw->mac.media_type) {
5967         case HNS3_MEDIA_TYPE_COPPER:
5968                 hns3_get_autoneg_rxtx_pause_copper(hw, &rx_pause, &tx_pause);
5969                 break;
5970
5971         /*
5972          * Flow control auto-negotiation is not supported for fiber and
5973          * backpalne media type.
5974          */
5975         case HNS3_MEDIA_TYPE_FIBER:
5976         case HNS3_MEDIA_TYPE_BACKPLANE:
5977                 hns3_err(hw, "autoneg FC mode can't be obtained, but flow control auto-negotiation is enabled.");
5978                 current_mode = hw->requested_fc_mode;
5979                 goto out;
5980         default:
5981                 hns3_err(hw, "autoneg FC mode can't be obtained for unknown media type(%u).",
5982                          hw->mac.media_type);
5983                 current_mode = HNS3_FC_NONE;
5984                 goto out;
5985         }
5986
5987         if (rx_pause && tx_pause)
5988                 current_mode = HNS3_FC_FULL;
5989         else if (rx_pause)
5990                 current_mode = HNS3_FC_RX_PAUSE;
5991         else if (tx_pause)
5992                 current_mode = HNS3_FC_TX_PAUSE;
5993         else
5994                 current_mode = HNS3_FC_NONE;
5995
5996 out:
5997         return current_mode;
5998 }
5999
6000 static enum hns3_fc_mode
6001 hns3_get_current_fc_mode(struct rte_eth_dev *dev)
6002 {
6003         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6004         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6005         struct hns3_mac *mac = &hw->mac;
6006
6007         /*
6008          * When the flow control mode is obtained, the device may not complete
6009          * auto-negotiation. It is necessary to wait for link establishment.
6010          */
6011         (void)hns3_dev_link_update(dev, 1);
6012
6013         /*
6014          * If the link auto-negotiation of the nic is disabled, or the flow
6015          * control auto-negotiation is not supported, the forced flow control
6016          * mode is used.
6017          */
6018         if (mac->link_autoneg == 0 || !pf->support_fc_autoneg)
6019                 return hw->requested_fc_mode;
6020
6021         return hns3_get_autoneg_fc_mode(hw);
6022 }
6023
6024 static int
6025 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6026 {
6027         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6028         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6029         enum hns3_fc_mode current_mode;
6030
6031         current_mode = hns3_get_current_fc_mode(dev);
6032         switch (current_mode) {
6033         case HNS3_FC_FULL:
6034                 fc_conf->mode = RTE_FC_FULL;
6035                 break;
6036         case HNS3_FC_TX_PAUSE:
6037                 fc_conf->mode = RTE_FC_TX_PAUSE;
6038                 break;
6039         case HNS3_FC_RX_PAUSE:
6040                 fc_conf->mode = RTE_FC_RX_PAUSE;
6041                 break;
6042         case HNS3_FC_NONE:
6043         default:
6044                 fc_conf->mode = RTE_FC_NONE;
6045                 break;
6046         }
6047
6048         fc_conf->pause_time = pf->pause_time;
6049         fc_conf->autoneg = pf->support_fc_autoneg ? hw->mac.link_autoneg : 0;
6050
6051         return 0;
6052 }
6053
6054 static void
6055 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
6056 {
6057         switch (mode) {
6058         case RTE_FC_NONE:
6059                 hw->requested_fc_mode = HNS3_FC_NONE;
6060                 break;
6061         case RTE_FC_RX_PAUSE:
6062                 hw->requested_fc_mode = HNS3_FC_RX_PAUSE;
6063                 break;
6064         case RTE_FC_TX_PAUSE:
6065                 hw->requested_fc_mode = HNS3_FC_TX_PAUSE;
6066                 break;
6067         case RTE_FC_FULL:
6068                 hw->requested_fc_mode = HNS3_FC_FULL;
6069                 break;
6070         default:
6071                 hw->requested_fc_mode = HNS3_FC_NONE;
6072                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
6073                           "configured to RTE_FC_NONE", mode);
6074                 break;
6075         }
6076 }
6077
6078 static int
6079 hns3_check_fc_autoneg_valid(struct hns3_hw *hw, uint8_t autoneg)
6080 {
6081         struct hns3_pf *pf = HNS3_DEV_HW_TO_PF(hw);
6082
6083         if (!pf->support_fc_autoneg) {
6084                 if (autoneg != 0) {
6085                         hns3_err(hw, "unsupported fc auto-negotiation setting.");
6086                         return -EOPNOTSUPP;
6087                 }
6088
6089                 /*
6090                  * Flow control auto-negotiation of the NIC is not supported,
6091                  * but other auto-negotiation features may be supported.
6092                  */
6093                 if (autoneg != hw->mac.link_autoneg) {
6094                         hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to disable autoneg!");
6095                         return -EOPNOTSUPP;
6096                 }
6097
6098                 return 0;
6099         }
6100
6101         /*
6102          * If flow control auto-negotiation of the NIC is supported, all
6103          * auto-negotiation features are supported.
6104          */
6105         if (autoneg != hw->mac.link_autoneg) {
6106                 hns3_err(hw, "please use 'link_speeds' in struct rte_eth_conf to change autoneg!");
6107                 return -EOPNOTSUPP;
6108         }
6109
6110         return 0;
6111 }
6112
6113 static int
6114 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
6115 {
6116         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6117         int ret;
6118
6119         if (fc_conf->high_water || fc_conf->low_water ||
6120             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
6121                 hns3_err(hw, "Unsupported flow control settings specified, "
6122                          "high_water(%u), low_water(%u), send_xon(%u) and "
6123                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6124                          fc_conf->high_water, fc_conf->low_water,
6125                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
6126                 return -EINVAL;
6127         }
6128
6129         ret = hns3_check_fc_autoneg_valid(hw, fc_conf->autoneg);
6130         if (ret)
6131                 return ret;
6132
6133         if (!fc_conf->pause_time) {
6134                 hns3_err(hw, "Invalid pause time %u setting.",
6135                          fc_conf->pause_time);
6136                 return -EINVAL;
6137         }
6138
6139         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6140             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
6141                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
6142                          "current_fc_status = %d", hw->current_fc_status);
6143                 return -EOPNOTSUPP;
6144         }
6145
6146         if (hw->num_tc > 1) {
6147                 hns3_err(hw, "in multi-TC scenarios, MAC pause is not supported.");
6148                 return -EOPNOTSUPP;
6149         }
6150
6151         hns3_get_fc_mode(hw, fc_conf->mode);
6152
6153         rte_spinlock_lock(&hw->lock);
6154         ret = hns3_fc_enable(dev, fc_conf);
6155         rte_spinlock_unlock(&hw->lock);
6156
6157         return ret;
6158 }
6159
6160 static int
6161 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
6162                             struct rte_eth_pfc_conf *pfc_conf)
6163 {
6164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6165         int ret;
6166
6167         if (!hns3_dev_dcb_supported(hw)) {
6168                 hns3_err(hw, "This port does not support dcb configurations.");
6169                 return -EOPNOTSUPP;
6170         }
6171
6172         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
6173             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
6174                 hns3_err(hw, "Unsupported flow control settings specified, "
6175                          "high_water(%u), low_water(%u), send_xon(%u) and "
6176                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
6177                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
6178                          pfc_conf->fc.send_xon,
6179                          pfc_conf->fc.mac_ctrl_frame_fwd);
6180                 return -EINVAL;
6181         }
6182         if (pfc_conf->fc.autoneg) {
6183                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
6184                 return -EINVAL;
6185         }
6186         if (pfc_conf->fc.pause_time == 0) {
6187                 hns3_err(hw, "Invalid pause time %u setting.",
6188                          pfc_conf->fc.pause_time);
6189                 return -EINVAL;
6190         }
6191
6192         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
6193             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
6194                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
6195                              "current_fc_status = %d", hw->current_fc_status);
6196                 return -EOPNOTSUPP;
6197         }
6198
6199         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
6200
6201         rte_spinlock_lock(&hw->lock);
6202         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
6203         rte_spinlock_unlock(&hw->lock);
6204
6205         return ret;
6206 }
6207
6208 static int
6209 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
6210 {
6211         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6212         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6213         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
6214         int i;
6215
6216         rte_spinlock_lock(&hw->lock);
6217         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
6218                 dcb_info->nb_tcs = pf->local_max_tc;
6219         else
6220                 dcb_info->nb_tcs = 1;
6221
6222         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
6223                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
6224         for (i = 0; i < dcb_info->nb_tcs; i++)
6225                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
6226
6227         for (i = 0; i < hw->num_tc; i++) {
6228                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
6229                 dcb_info->tc_queue.tc_txq[0][i].base =
6230                                                 hw->tc_queue[i].tqp_offset;
6231                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
6232                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
6233                                                 hw->tc_queue[i].tqp_count;
6234         }
6235         rte_spinlock_unlock(&hw->lock);
6236
6237         return 0;
6238 }
6239
6240 static int
6241 hns3_reinit_dev(struct hns3_adapter *hns)
6242 {
6243         struct hns3_hw *hw = &hns->hw;
6244         int ret;
6245
6246         ret = hns3_cmd_init(hw);
6247         if (ret) {
6248                 hns3_err(hw, "Failed to init cmd: %d", ret);
6249                 return ret;
6250         }
6251
6252         ret = hns3_reset_all_tqps(hns);
6253         if (ret) {
6254                 hns3_err(hw, "Failed to reset all queues: %d", ret);
6255                 return ret;
6256         }
6257
6258         ret = hns3_init_hardware(hns);
6259         if (ret) {
6260                 hns3_err(hw, "Failed to init hardware: %d", ret);
6261                 return ret;
6262         }
6263
6264         ret = hns3_enable_hw_error_intr(hns, true);
6265         if (ret) {
6266                 hns3_err(hw, "fail to enable hw error interrupts: %d",
6267                              ret);
6268                 return ret;
6269         }
6270         hns3_info(hw, "Reset done, driver initialization finished.");
6271
6272         return 0;
6273 }
6274
6275 static bool
6276 is_pf_reset_done(struct hns3_hw *hw)
6277 {
6278         uint32_t val, reg, reg_bit;
6279
6280         switch (hw->reset.level) {
6281         case HNS3_IMP_RESET:
6282                 reg = HNS3_GLOBAL_RESET_REG;
6283                 reg_bit = HNS3_IMP_RESET_BIT;
6284                 break;
6285         case HNS3_GLOBAL_RESET:
6286                 reg = HNS3_GLOBAL_RESET_REG;
6287                 reg_bit = HNS3_GLOBAL_RESET_BIT;
6288                 break;
6289         case HNS3_FUNC_RESET:
6290                 reg = HNS3_FUN_RST_ING;
6291                 reg_bit = HNS3_FUN_RST_ING_B;
6292                 break;
6293         case HNS3_FLR_RESET:
6294         default:
6295                 hns3_err(hw, "Wait for unsupported reset level: %d",
6296                          hw->reset.level);
6297                 return true;
6298         }
6299         val = hns3_read_dev(hw, reg);
6300         if (hns3_get_bit(val, reg_bit))
6301                 return false;
6302         else
6303                 return true;
6304 }
6305
6306 bool
6307 hns3_is_reset_pending(struct hns3_adapter *hns)
6308 {
6309         struct hns3_hw *hw = &hns->hw;
6310         enum hns3_reset_level reset;
6311
6312         hns3_check_event_cause(hns, NULL);
6313         reset = hns3_get_reset_level(hns, &hw->reset.pending);
6314
6315         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6316             hw->reset.level < reset) {
6317                 hns3_warn(hw, "High level reset %d is pending", reset);
6318                 return true;
6319         }
6320         reset = hns3_get_reset_level(hns, &hw->reset.request);
6321         if (reset != HNS3_NONE_RESET && hw->reset.level != HNS3_NONE_RESET &&
6322             hw->reset.level < reset) {
6323                 hns3_warn(hw, "High level reset %d is request", reset);
6324                 return true;
6325         }
6326         return false;
6327 }
6328
6329 static int
6330 hns3_wait_hardware_ready(struct hns3_adapter *hns)
6331 {
6332         struct hns3_hw *hw = &hns->hw;
6333         struct hns3_wait_data *wait_data = hw->reset.wait_data;
6334         struct timeval tv;
6335
6336         if (wait_data->result == HNS3_WAIT_SUCCESS)
6337                 return 0;
6338         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
6339                 gettimeofday(&tv, NULL);
6340                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
6341                           tv.tv_sec, tv.tv_usec);
6342                 return -ETIME;
6343         } else if (wait_data->result == HNS3_WAIT_REQUEST)
6344                 return -EAGAIN;
6345
6346         wait_data->hns = hns;
6347         wait_data->check_completion = is_pf_reset_done;
6348         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
6349                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
6350         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
6351         wait_data->count = HNS3_RESET_WAIT_CNT;
6352         wait_data->result = HNS3_WAIT_REQUEST;
6353         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
6354         return -EAGAIN;
6355 }
6356
6357 static int
6358 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
6359 {
6360         struct hns3_cmd_desc desc;
6361         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
6362
6363         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
6364         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
6365         req->fun_reset_vfid = func_id;
6366
6367         return hns3_cmd_send(hw, &desc, 1);
6368 }
6369
6370 static int
6371 hns3_imp_reset_cmd(struct hns3_hw *hw)
6372 {
6373         struct hns3_cmd_desc desc;
6374
6375         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
6376         desc.data[0] = 0xeedd;
6377
6378         return hns3_cmd_send(hw, &desc, 1);
6379 }
6380
6381 static void
6382 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
6383 {
6384         struct hns3_hw *hw = &hns->hw;
6385         struct timeval tv;
6386         uint32_t val;
6387
6388         gettimeofday(&tv, NULL);
6389         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
6390             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
6391                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
6392                           tv.tv_sec, tv.tv_usec);
6393                 return;
6394         }
6395
6396         switch (reset_level) {
6397         case HNS3_IMP_RESET:
6398                 hns3_imp_reset_cmd(hw);
6399                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
6400                           tv.tv_sec, tv.tv_usec);
6401                 break;
6402         case HNS3_GLOBAL_RESET:
6403                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
6404                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
6405                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
6406                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
6407                           tv.tv_sec, tv.tv_usec);
6408                 break;
6409         case HNS3_FUNC_RESET:
6410                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
6411                           tv.tv_sec, tv.tv_usec);
6412                 /* schedule again to check later */
6413                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
6414                 hns3_schedule_reset(hns);
6415                 break;
6416         default:
6417                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
6418                 return;
6419         }
6420         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
6421 }
6422
6423 static enum hns3_reset_level
6424 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
6425 {
6426         struct hns3_hw *hw = &hns->hw;
6427         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
6428
6429         /* Return the highest priority reset level amongst all */
6430         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
6431                 reset_level = HNS3_IMP_RESET;
6432         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
6433                 reset_level = HNS3_GLOBAL_RESET;
6434         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
6435                 reset_level = HNS3_FUNC_RESET;
6436         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
6437                 reset_level = HNS3_FLR_RESET;
6438
6439         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
6440                 return HNS3_NONE_RESET;
6441
6442         return reset_level;
6443 }
6444
6445 static void
6446 hns3_record_imp_error(struct hns3_adapter *hns)
6447 {
6448         struct hns3_hw *hw = &hns->hw;
6449         uint32_t reg_val;
6450
6451         reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6452         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B)) {
6453                 hns3_warn(hw, "Detected IMP RD poison!");
6454                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_RD_POISON_B, 0);
6455                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6456         }
6457
6458         if (hns3_get_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B)) {
6459                 hns3_warn(hw, "Detected IMP CMDQ error!");
6460                 hns3_set_bit(reg_val, HNS3_VECTOR0_IMP_CMDQ_ERR_B, 0);
6461                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val);
6462         }
6463 }
6464
6465 static int
6466 hns3_prepare_reset(struct hns3_adapter *hns)
6467 {
6468         struct hns3_hw *hw = &hns->hw;
6469         uint32_t reg_val;
6470         int ret;
6471
6472         switch (hw->reset.level) {
6473         case HNS3_FUNC_RESET:
6474                 ret = hns3_func_reset_cmd(hw, HNS3_PF_FUNC_ID);
6475                 if (ret)
6476                         return ret;
6477
6478                 /*
6479                  * After performaning pf reset, it is not necessary to do the
6480                  * mailbox handling or send any command to firmware, because
6481                  * any mailbox handling or command to firmware is only valid
6482                  * after hns3_cmd_init is called.
6483                  */
6484                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
6485                 hw->reset.stats.request_cnt++;
6486                 break;
6487         case HNS3_IMP_RESET:
6488                 hns3_record_imp_error(hns);
6489                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
6490                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
6491                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
6492                 break;
6493         default:
6494                 break;
6495         }
6496         return 0;
6497 }
6498
6499 static int
6500 hns3_set_rst_done(struct hns3_hw *hw)
6501 {
6502         struct hns3_pf_rst_done_cmd *req;
6503         struct hns3_cmd_desc desc;
6504
6505         req = (struct hns3_pf_rst_done_cmd *)desc.data;
6506         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
6507         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
6508         return hns3_cmd_send(hw, &desc, 1);
6509 }
6510
6511 static int
6512 hns3_stop_service(struct hns3_adapter *hns)
6513 {
6514         struct hns3_hw *hw = &hns->hw;
6515         struct rte_eth_dev *eth_dev;
6516
6517         eth_dev = &rte_eth_devices[hw->data->port_id];
6518         hw->mac.link_status = ETH_LINK_DOWN;
6519         if (hw->adapter_state == HNS3_NIC_STARTED) {
6520                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
6521                 hns3_update_linkstatus_and_event(hw, false);
6522         }
6523
6524         hns3_set_rxtx_function(eth_dev);
6525         rte_wmb();
6526         /* Disable datapath on secondary process. */
6527         hns3_mp_req_stop_rxtx(eth_dev);
6528         rte_delay_ms(hw->tqps_num);
6529
6530         rte_spinlock_lock(&hw->lock);
6531         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
6532             hw->adapter_state == HNS3_NIC_STOPPING) {
6533                 hns3_enable_all_queues(hw, false);
6534                 hns3_do_stop(hns);
6535                 hw->reset.mbuf_deferred_free = true;
6536         } else
6537                 hw->reset.mbuf_deferred_free = false;
6538
6539         /*
6540          * It is cumbersome for hardware to pick-and-choose entries for deletion
6541          * from table space. Hence, for function reset software intervention is
6542          * required to delete the entries
6543          */
6544         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
6545                 hns3_configure_all_mc_mac_addr(hns, true);
6546         rte_spinlock_unlock(&hw->lock);
6547
6548         return 0;
6549 }
6550
6551 static int
6552 hns3_start_service(struct hns3_adapter *hns)
6553 {
6554         struct hns3_hw *hw = &hns->hw;
6555         struct rte_eth_dev *eth_dev;
6556
6557         if (hw->reset.level == HNS3_IMP_RESET ||
6558             hw->reset.level == HNS3_GLOBAL_RESET)
6559                 hns3_set_rst_done(hw);
6560         eth_dev = &rte_eth_devices[hw->data->port_id];
6561         hns3_set_rxtx_function(eth_dev);
6562         hns3_mp_req_start_rxtx(eth_dev);
6563         if (hw->adapter_state == HNS3_NIC_STARTED) {
6564                 /*
6565                  * This API parent function already hold the hns3_hw.lock, the
6566                  * hns3_service_handler may report lse, in bonding application
6567                  * it will call driver's ops which may acquire the hns3_hw.lock
6568                  * again, thus lead to deadlock.
6569                  * We defer calls hns3_service_handler to avoid the deadlock.
6570                  */
6571                 rte_eal_alarm_set(HNS3_SERVICE_QUICK_INTERVAL,
6572                                   hns3_service_handler, eth_dev);
6573
6574                 /* Enable interrupt of all rx queues before enabling queues */
6575                 hns3_dev_all_rx_queue_intr_enable(hw, true);
6576                 /*
6577                  * Enable state of each rxq and txq will be recovered after
6578                  * reset, so we need to restore them before enable all tqps;
6579                  */
6580                 hns3_restore_tqp_enable_state(hw);
6581                 /*
6582                  * When finished the initialization, enable queues to receive
6583                  * and transmit packets.
6584                  */
6585                 hns3_enable_all_queues(hw, true);
6586         }
6587
6588         return 0;
6589 }
6590
6591 static int
6592 hns3_restore_conf(struct hns3_adapter *hns)
6593 {
6594         struct hns3_hw *hw = &hns->hw;
6595         int ret;
6596
6597         ret = hns3_configure_all_mac_addr(hns, false);
6598         if (ret)
6599                 return ret;
6600
6601         ret = hns3_configure_all_mc_mac_addr(hns, false);
6602         if (ret)
6603                 goto err_mc_mac;
6604
6605         ret = hns3_dev_promisc_restore(hns);
6606         if (ret)
6607                 goto err_promisc;
6608
6609         ret = hns3_restore_vlan_table(hns);
6610         if (ret)
6611                 goto err_promisc;
6612
6613         ret = hns3_restore_vlan_conf(hns);
6614         if (ret)
6615                 goto err_promisc;
6616
6617         ret = hns3_restore_all_fdir_filter(hns);
6618         if (ret)
6619                 goto err_promisc;
6620
6621         ret = hns3_restore_ptp(hns);
6622         if (ret)
6623                 goto err_promisc;
6624
6625         ret = hns3_restore_rx_interrupt(hw);
6626         if (ret)
6627                 goto err_promisc;
6628
6629         ret = hns3_restore_gro_conf(hw);
6630         if (ret)
6631                 goto err_promisc;
6632
6633         ret = hns3_restore_fec(hw);
6634         if (ret)
6635                 goto err_promisc;
6636
6637         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
6638                 ret = hns3_do_start(hns, false);
6639                 if (ret)
6640                         goto err_promisc;
6641                 hns3_info(hw, "hns3 dev restart successful!");
6642         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
6643                 hw->adapter_state = HNS3_NIC_CONFIGURED;
6644         return 0;
6645
6646 err_promisc:
6647         hns3_configure_all_mc_mac_addr(hns, true);
6648 err_mc_mac:
6649         hns3_configure_all_mac_addr(hns, true);
6650         return ret;
6651 }
6652
6653 static void
6654 hns3_reset_service(void *param)
6655 {
6656         struct hns3_adapter *hns = (struct hns3_adapter *)param;
6657         struct hns3_hw *hw = &hns->hw;
6658         enum hns3_reset_level reset_level;
6659         struct timeval tv_delta;
6660         struct timeval tv_start;
6661         struct timeval tv;
6662         uint64_t msec;
6663         int ret;
6664
6665         /*
6666          * The interrupt is not triggered within the delay time.
6667          * The interrupt may have been lost. It is necessary to handle
6668          * the interrupt to recover from the error.
6669          */
6670         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
6671                             SCHEDULE_DEFERRED) {
6672                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
6673                                   __ATOMIC_RELAXED);
6674                 hns3_err(hw, "Handling interrupts in delayed tasks");
6675                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
6676                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6677                 if (reset_level == HNS3_NONE_RESET) {
6678                         hns3_err(hw, "No reset level is set, try IMP reset");
6679                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
6680                 }
6681         }
6682         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
6683
6684         /*
6685          * Check if there is any ongoing reset in the hardware. This status can
6686          * be checked from reset_pending. If there is then, we need to wait for
6687          * hardware to complete reset.
6688          *    a. If we are able to figure out in reasonable time that hardware
6689          *       has fully resetted then, we can proceed with driver, client
6690          *       reset.
6691          *    b. else, we can come back later to check this status so re-sched
6692          *       now.
6693          */
6694         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
6695         if (reset_level != HNS3_NONE_RESET) {
6696                 gettimeofday(&tv_start, NULL);
6697                 ret = hns3_reset_process(hns, reset_level);
6698                 gettimeofday(&tv, NULL);
6699                 timersub(&tv, &tv_start, &tv_delta);
6700                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
6701                        tv_delta.tv_usec / USEC_PER_MSEC;
6702                 if (msec > HNS3_RESET_PROCESS_MS)
6703                         hns3_err(hw, "%d handle long time delta %" PRIx64
6704                                      " ms time=%ld.%.6ld",
6705                                  hw->reset.level, msec,
6706                                  tv.tv_sec, tv.tv_usec);
6707                 if (ret == -EAGAIN)
6708                         return;
6709         }
6710
6711         /* Check if we got any *new* reset requests to be honored */
6712         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
6713         if (reset_level != HNS3_NONE_RESET)
6714                 hns3_msix_process(hns, reset_level);
6715 }
6716
6717 static unsigned int
6718 hns3_get_speed_capa_num(uint16_t device_id)
6719 {
6720         unsigned int num;
6721
6722         switch (device_id) {
6723         case HNS3_DEV_ID_25GE:
6724         case HNS3_DEV_ID_25GE_RDMA:
6725                 num = 2;
6726                 break;
6727         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6728         case HNS3_DEV_ID_200G_RDMA:
6729                 num = 1;
6730                 break;
6731         default:
6732                 num = 0;
6733                 break;
6734         }
6735
6736         return num;
6737 }
6738
6739 static int
6740 hns3_get_speed_fec_capa(struct rte_eth_fec_capa *speed_fec_capa,
6741                         uint16_t device_id)
6742 {
6743         switch (device_id) {
6744         case HNS3_DEV_ID_25GE:
6745         /* fallthrough */
6746         case HNS3_DEV_ID_25GE_RDMA:
6747                 speed_fec_capa[0].speed = speed_fec_capa_tbl[1].speed;
6748                 speed_fec_capa[0].capa = speed_fec_capa_tbl[1].capa;
6749
6750                 /* In HNS3 device, the 25G NIC is compatible with 10G rate */
6751                 speed_fec_capa[1].speed = speed_fec_capa_tbl[0].speed;
6752                 speed_fec_capa[1].capa = speed_fec_capa_tbl[0].capa;
6753                 break;
6754         case HNS3_DEV_ID_100G_RDMA_MACSEC:
6755                 speed_fec_capa[0].speed = speed_fec_capa_tbl[4].speed;
6756                 speed_fec_capa[0].capa = speed_fec_capa_tbl[4].capa;
6757                 break;
6758         case HNS3_DEV_ID_200G_RDMA:
6759                 speed_fec_capa[0].speed = speed_fec_capa_tbl[5].speed;
6760                 speed_fec_capa[0].capa = speed_fec_capa_tbl[5].capa;
6761                 break;
6762         default:
6763                 return -ENOTSUP;
6764         }
6765
6766         return 0;
6767 }
6768
6769 static int
6770 hns3_fec_get_capability(struct rte_eth_dev *dev,
6771                         struct rte_eth_fec_capa *speed_fec_capa,
6772                         unsigned int num)
6773 {
6774         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6775         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6776         uint16_t device_id = pci_dev->id.device_id;
6777         unsigned int capa_num;
6778         int ret;
6779
6780         capa_num = hns3_get_speed_capa_num(device_id);
6781         if (capa_num == 0) {
6782                 hns3_err(hw, "device(0x%x) is not supported by hns3 PMD",
6783                          device_id);
6784                 return -ENOTSUP;
6785         }
6786
6787         if (speed_fec_capa == NULL || num < capa_num)
6788                 return capa_num;
6789
6790         ret = hns3_get_speed_fec_capa(speed_fec_capa, device_id);
6791         if (ret)
6792                 return -ENOTSUP;
6793
6794         return capa_num;
6795 }
6796
6797 static int
6798 get_current_fec_auto_state(struct hns3_hw *hw, uint8_t *state)
6799 {
6800         struct hns3_config_fec_cmd *req;
6801         struct hns3_cmd_desc desc;
6802         int ret;
6803
6804         /*
6805          * CMD(HNS3_OPC_CONFIG_FEC_MODE) read is not supported
6806          * in device of link speed
6807          * below 10 Gbps.
6808          */
6809         if (hw->mac.link_speed < ETH_SPEED_NUM_10G) {
6810                 *state = 0;
6811                 return 0;
6812         }
6813
6814         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, true);
6815         req = (struct hns3_config_fec_cmd *)desc.data;
6816         ret = hns3_cmd_send(hw, &desc, 1);
6817         if (ret) {
6818                 hns3_err(hw, "get current fec auto state failed, ret = %d",
6819                          ret);
6820                 return ret;
6821         }
6822
6823         *state = req->fec_mode & (1U << HNS3_MAC_CFG_FEC_AUTO_EN_B);
6824         return 0;
6825 }
6826
6827 static int
6828 hns3_fec_get_internal(struct hns3_hw *hw, uint32_t *fec_capa)
6829 {
6830         struct hns3_sfp_info_cmd *resp;
6831         uint32_t tmp_fec_capa;
6832         uint8_t auto_state;
6833         struct hns3_cmd_desc desc;
6834         int ret;
6835
6836         /*
6837          * If link is down and AUTO is enabled, AUTO is returned, otherwise,
6838          * configured FEC mode is returned.
6839          * If link is up, current FEC mode is returned.
6840          */
6841         if (hw->mac.link_status == ETH_LINK_DOWN) {
6842                 ret = get_current_fec_auto_state(hw, &auto_state);
6843                 if (ret)
6844                         return ret;
6845
6846                 if (auto_state == 0x1) {
6847                         *fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);
6848                         return 0;
6849                 }
6850         }
6851
6852         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_INFO, true);
6853         resp = (struct hns3_sfp_info_cmd *)desc.data;
6854         resp->query_type = HNS3_ACTIVE_QUERY;
6855
6856         ret = hns3_cmd_send(hw, &desc, 1);
6857         if (ret == -EOPNOTSUPP) {
6858                 hns3_err(hw, "IMP do not support get FEC, ret = %d", ret);
6859                 return ret;
6860         } else if (ret) {
6861                 hns3_err(hw, "get FEC failed, ret = %d", ret);
6862                 return ret;
6863         }
6864
6865         /*
6866          * FEC mode order defined in hns3 hardware is inconsistend with
6867          * that defined in the ethdev library. So the sequence needs
6868          * to be converted.
6869          */
6870         switch (resp->active_fec) {
6871         case HNS3_HW_FEC_MODE_NOFEC:
6872                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6873                 break;
6874         case HNS3_HW_FEC_MODE_BASER:
6875                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);
6876                 break;
6877         case HNS3_HW_FEC_MODE_RS:
6878                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(RS);
6879                 break;
6880         default:
6881                 tmp_fec_capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);
6882                 break;
6883         }
6884
6885         *fec_capa = tmp_fec_capa;
6886         return 0;
6887 }
6888
6889 static int
6890 hns3_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)
6891 {
6892         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6893
6894         return hns3_fec_get_internal(hw, fec_capa);
6895 }
6896
6897 static int
6898 hns3_set_fec_hw(struct hns3_hw *hw, uint32_t mode)
6899 {
6900         struct hns3_config_fec_cmd *req;
6901         struct hns3_cmd_desc desc;
6902         int ret;
6903
6904         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_FEC_MODE, false);
6905
6906         req = (struct hns3_config_fec_cmd *)desc.data;
6907         switch (mode) {
6908         case RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC):
6909                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6910                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_OFF);
6911                 break;
6912         case RTE_ETH_FEC_MODE_CAPA_MASK(BASER):
6913                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6914                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_BASER);
6915                 break;
6916         case RTE_ETH_FEC_MODE_CAPA_MASK(RS):
6917                 hns3_set_field(req->fec_mode, HNS3_MAC_CFG_FEC_MODE_M,
6918                                 HNS3_MAC_CFG_FEC_MODE_S, HNS3_MAC_FEC_RS);
6919                 break;
6920         case RTE_ETH_FEC_MODE_CAPA_MASK(AUTO):
6921                 hns3_set_bit(req->fec_mode, HNS3_MAC_CFG_FEC_AUTO_EN_B, 1);
6922                 break;
6923         default:
6924                 return 0;
6925         }
6926         ret = hns3_cmd_send(hw, &desc, 1);
6927         if (ret)
6928                 hns3_err(hw, "set fec mode failed, ret = %d", ret);
6929
6930         return ret;
6931 }
6932
6933 static uint32_t
6934 get_current_speed_fec_cap(struct hns3_hw *hw, struct rte_eth_fec_capa *fec_capa)
6935 {
6936         struct hns3_mac *mac = &hw->mac;
6937         uint32_t cur_capa;
6938
6939         switch (mac->link_speed) {
6940         case ETH_SPEED_NUM_10G:
6941                 cur_capa = fec_capa[1].capa;
6942                 break;
6943         case ETH_SPEED_NUM_25G:
6944         case ETH_SPEED_NUM_100G:
6945         case ETH_SPEED_NUM_200G:
6946                 cur_capa = fec_capa[0].capa;
6947                 break;
6948         default:
6949                 cur_capa = 0;
6950                 break;
6951         }
6952
6953         return cur_capa;
6954 }
6955
6956 static bool
6957 is_fec_mode_one_bit_set(uint32_t mode)
6958 {
6959         int cnt = 0;
6960         uint8_t i;
6961
6962         for (i = 0; i < sizeof(mode); i++)
6963                 if (mode >> i & 0x1)
6964                         cnt++;
6965
6966         return cnt == 1 ? true : false;
6967 }
6968
6969 static int
6970 hns3_fec_set(struct rte_eth_dev *dev, uint32_t mode)
6971 {
6972 #define FEC_CAPA_NUM 2
6973         struct hns3_adapter *hns = dev->data->dev_private;
6974         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
6975         struct hns3_pf *pf = &hns->pf;
6976
6977         struct rte_eth_fec_capa fec_capa[FEC_CAPA_NUM];
6978         uint32_t cur_capa;
6979         uint32_t num = FEC_CAPA_NUM;
6980         int ret;
6981
6982         ret = hns3_fec_get_capability(dev, fec_capa, num);
6983         if (ret < 0)
6984                 return ret;
6985
6986         /* HNS3 PMD driver only support one bit set mode, e.g. 0x1, 0x4 */
6987         if (!is_fec_mode_one_bit_set(mode))
6988                 hns3_err(hw, "FEC mode(0x%x) not supported in HNS3 PMD,"
6989                              "FEC mode should be only one bit set", mode);
6990
6991         /*
6992          * Check whether the configured mode is within the FEC capability.
6993          * If not, the configured mode will not be supported.
6994          */
6995         cur_capa = get_current_speed_fec_cap(hw, fec_capa);
6996         if (!(cur_capa & mode)) {
6997                 hns3_err(hw, "unsupported FEC mode = 0x%x", mode);
6998                 return -EINVAL;
6999         }
7000
7001         rte_spinlock_lock(&hw->lock);
7002         ret = hns3_set_fec_hw(hw, mode);
7003         if (ret) {
7004                 rte_spinlock_unlock(&hw->lock);
7005                 return ret;
7006         }
7007
7008         pf->fec_mode = mode;
7009         rte_spinlock_unlock(&hw->lock);
7010
7011         return 0;
7012 }
7013
7014 static int
7015 hns3_restore_fec(struct hns3_hw *hw)
7016 {
7017         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7018         struct hns3_pf *pf = &hns->pf;
7019         uint32_t mode = pf->fec_mode;
7020         int ret;
7021
7022         ret = hns3_set_fec_hw(hw, mode);
7023         if (ret)
7024                 hns3_err(hw, "restore fec mode(0x%x) failed, ret = %d",
7025                          mode, ret);
7026
7027         return ret;
7028 }
7029
7030 static int
7031 hns3_query_dev_fec_info(struct hns3_hw *hw)
7032 {
7033         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
7034         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(hns);
7035         int ret;
7036
7037         ret = hns3_fec_get_internal(hw, &pf->fec_mode);
7038         if (ret)
7039                 hns3_err(hw, "query device FEC info failed, ret = %d", ret);
7040
7041         return ret;
7042 }
7043
7044 static bool
7045 hns3_optical_module_existed(struct hns3_hw *hw)
7046 {
7047         struct hns3_cmd_desc desc;
7048         bool existed;
7049         int ret;
7050
7051         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GET_SFP_EXIST, true);
7052         ret = hns3_cmd_send(hw, &desc, 1);
7053         if (ret) {
7054                 hns3_err(hw,
7055                          "fail to get optical module exist state, ret = %d.\n",
7056                          ret);
7057                 return false;
7058         }
7059         existed = !!desc.data[0];
7060
7061         return existed;
7062 }
7063
7064 static int
7065 hns3_get_module_eeprom_data(struct hns3_hw *hw, uint32_t offset,
7066                                 uint32_t len, uint8_t *data)
7067 {
7068 #define HNS3_SFP_INFO_CMD_NUM 6
7069 #define HNS3_SFP_INFO_MAX_LEN \
7070         (HNS3_SFP_INFO_BD0_LEN + \
7071         (HNS3_SFP_INFO_CMD_NUM - 1) * HNS3_SFP_INFO_BDX_LEN)
7072         struct hns3_cmd_desc desc[HNS3_SFP_INFO_CMD_NUM];
7073         struct hns3_sfp_info_bd0_cmd *sfp_info_bd0;
7074         uint16_t read_len;
7075         uint16_t copy_len;
7076         int ret;
7077         int i;
7078
7079         for (i = 0; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7080                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_SFP_EEPROM,
7081                                           true);
7082                 if (i < HNS3_SFP_INFO_CMD_NUM - 1)
7083                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
7084         }
7085
7086         sfp_info_bd0 = (struct hns3_sfp_info_bd0_cmd *)desc[0].data;
7087         sfp_info_bd0->offset = rte_cpu_to_le_16((uint16_t)offset);
7088         read_len = RTE_MIN(len, HNS3_SFP_INFO_MAX_LEN);
7089         sfp_info_bd0->read_len = rte_cpu_to_le_16((uint16_t)read_len);
7090
7091         ret = hns3_cmd_send(hw, desc, HNS3_SFP_INFO_CMD_NUM);
7092         if (ret) {
7093                 hns3_err(hw, "fail to get module EEPROM info, ret = %d.\n",
7094                                 ret);
7095                 return ret;
7096         }
7097
7098         /* The data format in BD0 is different with the others. */
7099         copy_len = RTE_MIN(len, HNS3_SFP_INFO_BD0_LEN);
7100         memcpy(data, sfp_info_bd0->data, copy_len);
7101         read_len = copy_len;
7102
7103         for (i = 1; i < HNS3_SFP_INFO_CMD_NUM; i++) {
7104                 if (read_len >= len)
7105                         break;
7106
7107                 copy_len = RTE_MIN(len - read_len, HNS3_SFP_INFO_BDX_LEN);
7108                 memcpy(data + read_len, desc[i].data, copy_len);
7109                 read_len += copy_len;
7110         }
7111
7112         return (int)read_len;
7113 }
7114
7115 static int
7116 hns3_get_module_eeprom(struct rte_eth_dev *dev,
7117                        struct rte_dev_eeprom_info *info)
7118 {
7119         struct hns3_adapter *hns = dev->data->dev_private;
7120         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7121         uint32_t offset = info->offset;
7122         uint32_t len = info->length;
7123         uint8_t *data = info->data;
7124         uint32_t read_len = 0;
7125
7126         if (hw->mac.media_type != HNS3_MEDIA_TYPE_FIBER)
7127                 return -ENOTSUP;
7128
7129         if (!hns3_optical_module_existed(hw)) {
7130                 hns3_err(hw, "fail to read module EEPROM: no module is connected.\n");
7131                 return -EIO;
7132         }
7133
7134         while (read_len < len) {
7135                 int ret;
7136                 ret = hns3_get_module_eeprom_data(hw, offset + read_len,
7137                                                   len - read_len,
7138                                                   data + read_len);
7139                 if (ret < 0)
7140                         return -EIO;
7141                 read_len += ret;
7142         }
7143
7144         return 0;
7145 }
7146
7147 static int
7148 hns3_get_module_info(struct rte_eth_dev *dev,
7149                      struct rte_eth_dev_module_info *modinfo)
7150 {
7151 #define HNS3_SFF8024_ID_SFP             0x03
7152 #define HNS3_SFF8024_ID_QSFP_8438       0x0c
7153 #define HNS3_SFF8024_ID_QSFP_8436_8636  0x0d
7154 #define HNS3_SFF8024_ID_QSFP28_8636     0x11
7155 #define HNS3_SFF_8636_V1_3              0x03
7156         struct hns3_adapter *hns = dev->data->dev_private;
7157         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(hns);
7158         struct rte_dev_eeprom_info info;
7159         struct hns3_sfp_type sfp_type;
7160         int ret;
7161
7162         memset(&sfp_type, 0, sizeof(sfp_type));
7163         memset(&info, 0, sizeof(info));
7164         info.data = (uint8_t *)&sfp_type;
7165         info.length = sizeof(sfp_type);
7166         ret = hns3_get_module_eeprom(dev, &info);
7167         if (ret)
7168                 return ret;
7169
7170         switch (sfp_type.type) {
7171         case HNS3_SFF8024_ID_SFP:
7172                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7173                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7174                 break;
7175         case HNS3_SFF8024_ID_QSFP_8438:
7176                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
7177                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7178                 break;
7179         case HNS3_SFF8024_ID_QSFP_8436_8636:
7180                 if (sfp_type.ext_type < HNS3_SFF_8636_V1_3) {
7181                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
7182                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_MAX_LEN;
7183                 } else {
7184                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
7185                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7186                 }
7187                 break;
7188         case HNS3_SFF8024_ID_QSFP28_8636:
7189                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
7190                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
7191                 break;
7192         default:
7193                 hns3_err(hw, "unknown module, type = %u, extra_type = %u.\n",
7194                          sfp_type.type, sfp_type.ext_type);
7195                 return -EINVAL;
7196         }
7197
7198         return 0;
7199 }
7200
7201 static int
7202 hns3_parse_io_hint_func(const char *key, const char *value, void *extra_args)
7203 {
7204         uint32_t hint = HNS3_IO_FUNC_HINT_NONE;
7205
7206         RTE_SET_USED(key);
7207
7208         if (strcmp(value, "vec") == 0)
7209                 hint = HNS3_IO_FUNC_HINT_VEC;
7210         else if (strcmp(value, "sve") == 0)
7211                 hint = HNS3_IO_FUNC_HINT_SVE;
7212         else if (strcmp(value, "simple") == 0)
7213                 hint = HNS3_IO_FUNC_HINT_SIMPLE;
7214         else if (strcmp(value, "common") == 0)
7215                 hint = HNS3_IO_FUNC_HINT_COMMON;
7216
7217         /* If the hint is valid then update output parameters */
7218         if (hint != HNS3_IO_FUNC_HINT_NONE)
7219                 *(uint32_t *)extra_args = hint;
7220
7221         return 0;
7222 }
7223
7224 static const char *
7225 hns3_get_io_hint_func_name(uint32_t hint)
7226 {
7227         switch (hint) {
7228         case HNS3_IO_FUNC_HINT_VEC:
7229                 return "vec";
7230         case HNS3_IO_FUNC_HINT_SVE:
7231                 return "sve";
7232         case HNS3_IO_FUNC_HINT_SIMPLE:
7233                 return "simple";
7234         case HNS3_IO_FUNC_HINT_COMMON:
7235                 return "common";
7236         default:
7237                 return "none";
7238         }
7239 }
7240
7241 static int
7242 hns3_parse_dev_caps_mask(const char *key, const char *value, void *extra_args)
7243 {
7244         uint64_t val;
7245
7246         RTE_SET_USED(key);
7247
7248         val = strtoull(value, NULL, 16);
7249         *(uint64_t *)extra_args = val;
7250
7251         return 0;
7252 }
7253
7254 void
7255 hns3_parse_devargs(struct rte_eth_dev *dev)
7256 {
7257         struct hns3_adapter *hns = dev->data->dev_private;
7258         uint32_t rx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7259         uint32_t tx_func_hint = HNS3_IO_FUNC_HINT_NONE;
7260         struct hns3_hw *hw = &hns->hw;
7261         uint64_t dev_caps_mask = 0;
7262         struct rte_kvargs *kvlist;
7263
7264         if (dev->device->devargs == NULL)
7265                 return;
7266
7267         kvlist = rte_kvargs_parse(dev->device->devargs->args, NULL);
7268         if (!kvlist)
7269                 return;
7270
7271         rte_kvargs_process(kvlist, HNS3_DEVARG_RX_FUNC_HINT,
7272                            &hns3_parse_io_hint_func, &rx_func_hint);
7273         rte_kvargs_process(kvlist, HNS3_DEVARG_TX_FUNC_HINT,
7274                            &hns3_parse_io_hint_func, &tx_func_hint);
7275         rte_kvargs_process(kvlist, HNS3_DEVARG_DEV_CAPS_MASK,
7276                            &hns3_parse_dev_caps_mask, &dev_caps_mask);
7277         rte_kvargs_free(kvlist);
7278
7279         if (rx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7280                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_RX_FUNC_HINT,
7281                           hns3_get_io_hint_func_name(rx_func_hint));
7282         hns->rx_func_hint = rx_func_hint;
7283         if (tx_func_hint != HNS3_IO_FUNC_HINT_NONE)
7284                 hns3_warn(hw, "parsed %s = %s.", HNS3_DEVARG_TX_FUNC_HINT,
7285                           hns3_get_io_hint_func_name(tx_func_hint));
7286         hns->tx_func_hint = tx_func_hint;
7287
7288         if (dev_caps_mask != 0)
7289                 hns3_warn(hw, "parsed %s = 0x%" PRIx64 ".",
7290                           HNS3_DEVARG_DEV_CAPS_MASK, dev_caps_mask);
7291         hns->dev_caps_mask = dev_caps_mask;
7292 }
7293
7294 static const struct eth_dev_ops hns3_eth_dev_ops = {
7295         .dev_configure      = hns3_dev_configure,
7296         .dev_start          = hns3_dev_start,
7297         .dev_stop           = hns3_dev_stop,
7298         .dev_close          = hns3_dev_close,
7299         .promiscuous_enable = hns3_dev_promiscuous_enable,
7300         .promiscuous_disable = hns3_dev_promiscuous_disable,
7301         .allmulticast_enable  = hns3_dev_allmulticast_enable,
7302         .allmulticast_disable = hns3_dev_allmulticast_disable,
7303         .mtu_set            = hns3_dev_mtu_set,
7304         .stats_get          = hns3_stats_get,
7305         .stats_reset        = hns3_stats_reset,
7306         .xstats_get         = hns3_dev_xstats_get,
7307         .xstats_get_names   = hns3_dev_xstats_get_names,
7308         .xstats_reset       = hns3_dev_xstats_reset,
7309         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
7310         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
7311         .dev_infos_get          = hns3_dev_infos_get,
7312         .fw_version_get         = hns3_fw_version_get,
7313         .rx_queue_setup         = hns3_rx_queue_setup,
7314         .tx_queue_setup         = hns3_tx_queue_setup,
7315         .rx_queue_release       = hns3_dev_rx_queue_release,
7316         .tx_queue_release       = hns3_dev_tx_queue_release,
7317         .rx_queue_start         = hns3_dev_rx_queue_start,
7318         .rx_queue_stop          = hns3_dev_rx_queue_stop,
7319         .tx_queue_start         = hns3_dev_tx_queue_start,
7320         .tx_queue_stop          = hns3_dev_tx_queue_stop,
7321         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
7322         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
7323         .rxq_info_get           = hns3_rxq_info_get,
7324         .txq_info_get           = hns3_txq_info_get,
7325         .rx_burst_mode_get      = hns3_rx_burst_mode_get,
7326         .tx_burst_mode_get      = hns3_tx_burst_mode_get,
7327         .flow_ctrl_get          = hns3_flow_ctrl_get,
7328         .flow_ctrl_set          = hns3_flow_ctrl_set,
7329         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
7330         .mac_addr_add           = hns3_add_mac_addr,
7331         .mac_addr_remove        = hns3_remove_mac_addr,
7332         .mac_addr_set           = hns3_set_default_mac_addr,
7333         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
7334         .link_update            = hns3_dev_link_update,
7335         .rss_hash_update        = hns3_dev_rss_hash_update,
7336         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
7337         .reta_update            = hns3_dev_rss_reta_update,
7338         .reta_query             = hns3_dev_rss_reta_query,
7339         .flow_ops_get           = hns3_dev_flow_ops_get,
7340         .vlan_filter_set        = hns3_vlan_filter_set,
7341         .vlan_tpid_set          = hns3_vlan_tpid_set,
7342         .vlan_offload_set       = hns3_vlan_offload_set,
7343         .vlan_pvid_set          = hns3_vlan_pvid_set,
7344         .get_reg                = hns3_get_regs,
7345         .get_module_info        = hns3_get_module_info,
7346         .get_module_eeprom      = hns3_get_module_eeprom,
7347         .get_dcb_info           = hns3_get_dcb_info,
7348         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
7349         .fec_get_capability     = hns3_fec_get_capability,
7350         .fec_get                = hns3_fec_get,
7351         .fec_set                = hns3_fec_set,
7352         .tm_ops_get             = hns3_tm_ops_get,
7353         .tx_done_cleanup        = hns3_tx_done_cleanup,
7354         .timesync_enable            = hns3_timesync_enable,
7355         .timesync_disable           = hns3_timesync_disable,
7356         .timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,
7357         .timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,
7358         .timesync_adjust_time       = hns3_timesync_adjust_time,
7359         .timesync_read_time         = hns3_timesync_read_time,
7360         .timesync_write_time        = hns3_timesync_write_time,
7361 };
7362
7363 static const struct hns3_reset_ops hns3_reset_ops = {
7364         .reset_service       = hns3_reset_service,
7365         .stop_service        = hns3_stop_service,
7366         .prepare_reset       = hns3_prepare_reset,
7367         .wait_hardware_ready = hns3_wait_hardware_ready,
7368         .reinit_dev          = hns3_reinit_dev,
7369         .restore_conf        = hns3_restore_conf,
7370         .start_service       = hns3_start_service,
7371 };
7372
7373 static int
7374 hns3_dev_init(struct rte_eth_dev *eth_dev)
7375 {
7376         struct hns3_adapter *hns = eth_dev->data->dev_private;
7377         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
7378         struct rte_ether_addr *eth_addr;
7379         struct hns3_hw *hw = &hns->hw;
7380         int ret;
7381
7382         PMD_INIT_FUNC_TRACE();
7383
7384         eth_dev->process_private = (struct hns3_process_private *)
7385             rte_zmalloc_socket("hns3_filter_list",
7386                                sizeof(struct hns3_process_private),
7387                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
7388         if (eth_dev->process_private == NULL) {
7389                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
7390                 return -ENOMEM;
7391         }
7392
7393         hns3_flow_init(eth_dev);
7394
7395         hns3_set_rxtx_function(eth_dev);
7396         eth_dev->dev_ops = &hns3_eth_dev_ops;
7397         eth_dev->rx_queue_count = hns3_rx_queue_count;
7398         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7399                 ret = hns3_mp_init_secondary();
7400                 if (ret) {
7401                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
7402                                      "process, ret = %d", ret);
7403                         goto err_mp_init_secondary;
7404                 }
7405
7406                 hw->secondary_cnt++;
7407                 return 0;
7408         }
7409
7410         ret = hns3_mp_init_primary();
7411         if (ret) {
7412                 PMD_INIT_LOG(ERR,
7413                              "Failed to init for primary process, ret = %d",
7414                              ret);
7415                 goto err_mp_init_primary;
7416         }
7417
7418         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
7419         hns->is_vf = false;
7420         hw->data = eth_dev->data;
7421         hns3_parse_devargs(eth_dev);
7422
7423         /*
7424          * Set default max packet size according to the mtu
7425          * default vale in DPDK frame.
7426          */
7427         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
7428
7429         ret = hns3_reset_init(hw);
7430         if (ret)
7431                 goto err_init_reset;
7432         hw->reset.ops = &hns3_reset_ops;
7433
7434         ret = hns3_init_pf(eth_dev);
7435         if (ret) {
7436                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
7437                 goto err_init_pf;
7438         }
7439
7440         /* Allocate memory for storing MAC addresses */
7441         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
7442                                                sizeof(struct rte_ether_addr) *
7443                                                HNS3_UC_MACADDR_NUM, 0);
7444         if (eth_dev->data->mac_addrs == NULL) {
7445                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
7446                              "to store MAC addresses",
7447                              sizeof(struct rte_ether_addr) *
7448                              HNS3_UC_MACADDR_NUM);
7449                 ret = -ENOMEM;
7450                 goto err_rte_zmalloc;
7451         }
7452
7453         eth_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
7454         if (!rte_is_valid_assigned_ether_addr(eth_addr)) {
7455                 rte_eth_random_addr(hw->mac.mac_addr);
7456                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
7457                                 (struct rte_ether_addr *)hw->mac.mac_addr);
7458                 hns3_warn(hw, "default mac_addr from firmware is an invalid "
7459                           "unicast address, using random MAC address %s",
7460                           mac_str);
7461         }
7462         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
7463                             &eth_dev->data->mac_addrs[0]);
7464
7465         hw->adapter_state = HNS3_NIC_INITIALIZED;
7466
7467         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
7468                             SCHEDULE_PENDING) {
7469                 hns3_err(hw, "Reschedule reset service after dev_init");
7470                 hns3_schedule_reset(hns);
7471         } else {
7472                 /* IMP will wait ready flag before reset */
7473                 hns3_notify_reset_ready(hw, false);
7474         }
7475
7476         hns3_info(hw, "hns3 dev initialization successful!");
7477         return 0;
7478
7479 err_rte_zmalloc:
7480         hns3_uninit_pf(eth_dev);
7481
7482 err_init_pf:
7483         rte_free(hw->reset.wait_data);
7484
7485 err_init_reset:
7486         hns3_mp_uninit_primary();
7487
7488 err_mp_init_primary:
7489 err_mp_init_secondary:
7490         eth_dev->dev_ops = NULL;
7491         eth_dev->rx_pkt_burst = NULL;
7492         eth_dev->rx_descriptor_status = NULL;
7493         eth_dev->tx_pkt_burst = NULL;
7494         eth_dev->tx_pkt_prepare = NULL;
7495         eth_dev->tx_descriptor_status = NULL;
7496         rte_free(eth_dev->process_private);
7497         eth_dev->process_private = NULL;
7498         return ret;
7499 }
7500
7501 static int
7502 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
7503 {
7504         struct hns3_adapter *hns = eth_dev->data->dev_private;
7505         struct hns3_hw *hw = &hns->hw;
7506
7507         PMD_INIT_FUNC_TRACE();
7508
7509         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
7510                 rte_free(eth_dev->process_private);
7511                 eth_dev->process_private = NULL;
7512                 return 0;
7513         }
7514
7515         if (hw->adapter_state < HNS3_NIC_CLOSING)
7516                 hns3_dev_close(eth_dev);
7517
7518         hw->adapter_state = HNS3_NIC_REMOVED;
7519         return 0;
7520 }
7521
7522 static int
7523 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
7524                    struct rte_pci_device *pci_dev)
7525 {
7526         return rte_eth_dev_pci_generic_probe(pci_dev,
7527                                              sizeof(struct hns3_adapter),
7528                                              hns3_dev_init);
7529 }
7530
7531 static int
7532 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
7533 {
7534         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
7535 }
7536
7537 static const struct rte_pci_id pci_id_hns3_map[] = {
7538         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
7539         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
7540         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
7541         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
7542         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
7543         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_200G_RDMA) },
7544         { .vendor_id = 0, }, /* sentinel */
7545 };
7546
7547 static struct rte_pci_driver rte_hns3_pmd = {
7548         .id_table = pci_id_hns3_map,
7549         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
7550         .probe = eth_hns3_pci_probe,
7551         .remove = eth_hns3_pci_remove,
7552 };
7553
7554 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
7555 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
7556 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
7557 RTE_PMD_REGISTER_PARAM_STRING(net_hns3,
7558                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
7559                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
7560                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");
7561 RTE_LOG_REGISTER(hns3_logtype_init, pmd.net.hns3.init, NOTICE);
7562 RTE_LOG_REGISTER(hns3_logtype_driver, pmd.net.hns3.driver, NOTICE);