drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_bus_pci.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_ethdev_driver.h>
  19 #include <rte_ethdev_pci.h>
  20 #include <rte_io.h>
  21 #include <rte_log.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_regs.h"
  27
  28 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  29 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  30
  31 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  32
  33 int hns3_logtype_init;
  34 int hns3_logtype_driver;
  35
  36 static int
  37 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
  38                 unsigned int tso_mss_max)
  39 {
  40         struct hns3_cfg_tso_status_cmd *req;
  41         struct hns3_cmd_desc desc;
  42         uint16_t tso_mss;
  43
  44         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
  45
  46         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
  47
  48         tso_mss = 0;
  49         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  50                        tso_mss_min);
  51         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
  52
  53         tso_mss = 0;
  54         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
  55                        tso_mss_max);
  56         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
  57
  58         return hns3_cmd_send(hw, &desc, 1);
  59 }
  60
  61 int
  62 hns3_config_gro(struct hns3_hw *hw, bool en)
  63 {
  64         struct hns3_cfg_gro_status_cmd *req;
  65         struct hns3_cmd_desc desc;
  66         int ret;
  67
  68         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
  69         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
  70
  71         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
  72
  73         ret = hns3_cmd_send(hw, &desc, 1);
  74         if (ret)
  75                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
  76
  77         return ret;
  78 }
  79
  80 static int
  81 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
  82                    uint16_t *allocated_size, bool is_alloc)
  83 {
  84         struct hns3_umv_spc_alc_cmd *req;
  85         struct hns3_cmd_desc desc;
  86         int ret;
  87
  88         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
  89         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
  90         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
  91         req->space_size = rte_cpu_to_le_32(space_size);
  92
  93         ret = hns3_cmd_send(hw, &desc, 1);
  94         if (ret) {
  95                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
  96                              is_alloc ? "allocate" : "free", ret);
  97                 return ret;
  98         }
  99
 100         if (is_alloc && allocated_size)
 101                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
 102
 103         return 0;
 104 }
 105
 106 static int
 107 hns3_init_umv_space(struct hns3_hw *hw)
 108 {
 109         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 110         struct hns3_pf *pf = &hns->pf;
 111         uint16_t allocated_size = 0;
 112         int ret;
 113
 114         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
 115                                  true);
 116         if (ret)
 117                 return ret;
 118
 119         if (allocated_size < pf->wanted_umv_size)
 120                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
 121                              pf->wanted_umv_size, allocated_size);
 122
 123         pf->max_umv_size = (!!allocated_size) ? allocated_size :
 124                                                 pf->wanted_umv_size;
 125         pf->used_umv_size = 0;
 126         return 0;
 127 }
 128
 129 static int
 130 hns3_uninit_umv_space(struct hns3_hw *hw)
 131 {
 132         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 133         struct hns3_pf *pf = &hns->pf;
 134         int ret;
 135
 136         if (pf->max_umv_size == 0)
 137                 return 0;
 138
 139         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
 140         if (ret)
 141                 return ret;
 142
 143         pf->max_umv_size = 0;
 144
 145         return 0;
 146 }
 147
 148 static bool
 149 hns3_is_umv_space_full(struct hns3_hw *hw)
 150 {
 151         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 152         struct hns3_pf *pf = &hns->pf;
 153         bool is_full;
 154
 155         is_full = (pf->used_umv_size >= pf->max_umv_size);
 156
 157         return is_full;
 158 }
 159
 160 static void
 161 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
 162 {
 163         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 164         struct hns3_pf *pf = &hns->pf;
 165
 166         if (is_free) {
 167                 if (pf->used_umv_size > 0)
 168                         pf->used_umv_size--;
 169         } else
 170                 pf->used_umv_size++;
 171 }
 172
 173 static void
 174 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
 175                       const uint8_t *addr, bool is_mc)
 176 {
 177         const unsigned char *mac_addr = addr;
 178         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
 179                             ((uint32_t)mac_addr[2] << 16) |
 180                             ((uint32_t)mac_addr[1] << 8) |
 181                             (uint32_t)mac_addr[0];
 182         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
 183
 184         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 185         if (is_mc) {
 186                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 187                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
 188                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
 189         }
 190
 191         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
 192         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
 193 }
 194
 195 static int
 196 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
 197                              uint8_t resp_code,
 198                              enum hns3_mac_vlan_tbl_opcode op)
 199 {
 200         if (cmdq_resp) {
 201                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
 202                          cmdq_resp);
 203                 return -EIO;
 204         }
 205
 206         if (op == HNS3_MAC_VLAN_ADD) {
 207                 if (resp_code == 0 || resp_code == 1) {
 208                         return 0;
 209                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
 210                         hns3_err(hw, "add mac addr failed for uc_overflow");
 211                         return -ENOSPC;
 212                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
 213                         hns3_err(hw, "add mac addr failed for mc_overflow");
 214                         return -ENOSPC;
 215                 }
 216
 217                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
 218                          resp_code);
 219                 return -EIO;
 220         } else if (op == HNS3_MAC_VLAN_REMOVE) {
 221                 if (resp_code == 0) {
 222                         return 0;
 223                 } else if (resp_code == 1) {
 224                         hns3_dbg(hw, "remove mac addr failed for miss");
 225                         return -ENOENT;
 226                 }
 227
 228                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
 229                          resp_code);
 230                 return -EIO;
 231         } else if (op == HNS3_MAC_VLAN_LKUP) {
 232                 if (resp_code == 0) {
 233                         return 0;
 234                 } else if (resp_code == 1) {
 235                         hns3_dbg(hw, "lookup mac addr failed for miss");
 236                         return -ENOENT;
 237                 }
 238
 239                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
 240                          resp_code);
 241                 return -EIO;
 242         }
 243
 244         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
 245                  op);
 246
 247         return -EINVAL;
 248 }
 249
 250 static int
 251 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
 252                          struct hns3_mac_vlan_tbl_entry_cmd *req,
 253                          struct hns3_cmd_desc *desc, bool is_mc)
 254 {
 255         uint8_t resp_code;
 256         uint16_t retval;
 257         int ret;
 258
 259         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
 260         if (is_mc) {
 261                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 262                 memcpy(desc[0].data, req,
 263                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 264                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
 265                                           true);
 266                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 267                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
 268                                           true);
 269                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 270         } else {
 271                 memcpy(desc[0].data, req,
 272                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 273                 ret = hns3_cmd_send(hw, desc, 1);
 274         }
 275         if (ret) {
 276                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
 277                          ret);
 278                 return ret;
 279         }
 280         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
 281         retval = rte_le_to_cpu_16(desc[0].retval);
 282
 283         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 284                                             HNS3_MAC_VLAN_LKUP);
 285 }
 286
 287 static int
 288 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
 289                       struct hns3_mac_vlan_tbl_entry_cmd *req,
 290                       struct hns3_cmd_desc *mc_desc)
 291 {
 292         uint8_t resp_code;
 293         uint16_t retval;
 294         int cfg_status;
 295         int ret;
 296
 297         if (mc_desc == NULL) {
 298                 struct hns3_cmd_desc desc;
 299
 300                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
 301                 memcpy(desc.data, req,
 302                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 303                 ret = hns3_cmd_send(hw, &desc, 1);
 304                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 305                 retval = rte_le_to_cpu_16(desc.retval);
 306
 307                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 308                                                           HNS3_MAC_VLAN_ADD);
 309         } else {
 310                 hns3_cmd_reuse_desc(&mc_desc[0], false);
 311                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 312                 hns3_cmd_reuse_desc(&mc_desc[1], false);
 313                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
 314                 hns3_cmd_reuse_desc(&mc_desc[2], false);
 315                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
 316                 memcpy(mc_desc[0].data, req,
 317                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 318                 mc_desc[0].retval = 0;
 319                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
 320                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
 321                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
 322
 323                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 324                                                           HNS3_MAC_VLAN_ADD);
 325         }
 326
 327         if (ret) {
 328                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
 329                 return ret;
 330         }
 331
 332         return cfg_status;
 333 }
 334
 335 static int
 336 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
 337                          struct hns3_mac_vlan_tbl_entry_cmd *req)
 338 {
 339         struct hns3_cmd_desc desc;
 340         uint8_t resp_code;
 341         uint16_t retval;
 342         int ret;
 343
 344         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
 345
 346         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
 347
 348         ret = hns3_cmd_send(hw, &desc, 1);
 349         if (ret) {
 350                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
 351                 return ret;
 352         }
 353         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
 354         retval = rte_le_to_cpu_16(desc.retval);
 355
 356         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
 357                                             HNS3_MAC_VLAN_REMOVE);
 358 }
 359
 360 static int
 361 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 362 {
 363         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 364         struct hns3_mac_vlan_tbl_entry_cmd req;
 365         struct hns3_pf *pf = &hns->pf;
 366         struct hns3_cmd_desc desc;
 367         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 368         uint16_t egress_port = 0;
 369         uint8_t vf_id;
 370         int ret;
 371
 372         /* check if mac addr is valid */
 373         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 374                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 375                                       mac_addr);
 376                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
 377                          mac_str);
 378                 return -EINVAL;
 379         }
 380
 381         memset(&req, 0, sizeof(req));
 382
 383         /*
 384          * In current version VF is not supported when PF is driven by DPDK
 385          * driver, the PF-related vf_id is 0, just need to configure parameters
 386          * for vf_id 0.
 387          */
 388         vf_id = 0;
 389         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
 390                        HNS3_MAC_EPORT_VFID_S, vf_id);
 391
 392         req.egress_port = rte_cpu_to_le_16(egress_port);
 393
 394         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 395
 396         /*
 397          * Lookup the mac address in the mac_vlan table, and add
 398          * it if the entry is inexistent. Repeated unicast entry
 399          * is not allowed in the mac vlan table.
 400          */
 401         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
 402         if (ret == -ENOENT) {
 403                 if (!hns3_is_umv_space_full(hw)) {
 404                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
 405                         if (!ret)
 406                                 hns3_update_umv_space(hw, false);
 407                         return ret;
 408                 }
 409
 410                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
 411
 412                 return -ENOSPC;
 413         }
 414
 415         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
 416
 417         /* check if we just hit the duplicate */
 418         if (ret == 0) {
 419                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
 420                 return 0;
 421         }
 422
 423         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
 424                  mac_str);
 425
 426         return ret;
 427 }
 428
 429 static int
 430 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 431                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
 432 {
 433         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 434         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 435         int ret;
 436
 437         rte_spinlock_lock(&hw->lock);
 438         ret = hns3_add_uc_addr_common(hw, mac_addr);
 439         if (ret) {
 440                 rte_spinlock_unlock(&hw->lock);
 441                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 442                                       mac_addr);
 443                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
 444                 return ret;
 445         }
 446
 447         if (idx == 0)
 448                 hw->mac.default_addr_setted = true;
 449         rte_spinlock_unlock(&hw->lock);
 450
 451         return ret;
 452 }
 453
 454 static int
 455 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 456 {
 457         struct hns3_mac_vlan_tbl_entry_cmd req;
 458         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 459         int ret;
 460
 461         /* check if mac addr is valid */
 462         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 463                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 464                                       mac_addr);
 465                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
 466                          mac_str);
 467                 return -EINVAL;
 468         }
 469
 470         memset(&req, 0, sizeof(req));
 471         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 472         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
 473         ret = hns3_remove_mac_vlan_tbl(hw, &req);
 474         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
 475                 return 0;
 476         else if (ret == 0)
 477                 hns3_update_umv_space(hw, true);
 478
 479         return ret;
 480 }
 481
 482 static void
 483 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 484 {
 485         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 486         /* index will be checked by upper level rte interface */
 487         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 488         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 489         int ret;
 490
 491         rte_spinlock_lock(&hw->lock);
 492         ret = hns3_remove_uc_addr_common(hw, mac_addr);
 493         if (ret) {
 494                 rte_spinlock_unlock(&hw->lock);
 495                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 496                                       mac_addr);
 497                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
 498                 return;
 499         }
 500
 501         if (idx == 0)
 502                 hw->mac.default_addr_setted = false;
 503         rte_spinlock_unlock(&hw->lock);
 504 }
 505
 506 static int
 507 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
 508                           struct rte_ether_addr *mac_addr)
 509 {
 510         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511         struct rte_ether_addr *oaddr;
 512         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 513         bool default_addr_setted;
 514         bool rm_succes = false;
 515         int ret, ret_val;
 516
 517         /* check if mac addr is valid */
 518         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 519                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 520                                       mac_addr);
 521                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
 522                          mac_str);
 523                 return -EINVAL;
 524         }
 525
 526         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
 527         default_addr_setted = hw->mac.default_addr_setted;
 528         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
 529                 return 0;
 530
 531         rte_spinlock_lock(&hw->lock);
 532         if (default_addr_setted) {
 533                 ret = hns3_remove_uc_addr_common(hw, oaddr);
 534                 if (ret) {
 535                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 536                                               oaddr);
 537                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
 538                                   mac_str, ret);
 539                         rm_succes = false;
 540                 } else
 541                         rm_succes = true;
 542         }
 543
 544         ret = hns3_add_uc_addr_common(hw, mac_addr);
 545         if (ret) {
 546                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 547                                       mac_addr);
 548                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
 549                 goto err_add_uc_addr;
 550         }
 551
 552         rte_ether_addr_copy(mac_addr,
 553                             (struct rte_ether_addr *)hw->mac.mac_addr);
 554         hw->mac.default_addr_setted = true;
 555         rte_spinlock_unlock(&hw->lock);
 556
 557         return 0;
 558
 559 err_add_uc_addr:
 560         if (rm_succes) {
 561                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
 562                 if (ret_val) {
 563                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 564                                               oaddr);
 565                         hns3_warn(hw,
 566                                   "Failed to restore old uc mac addr(%s): %d",
 567                                   mac_str, ret_val);
 568                         hw->mac.default_addr_setted = false;
 569                 }
 570         }
 571         rte_spinlock_unlock(&hw->lock);
 572
 573         return ret;
 574 }
 575
 576 static void
 577 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
 578 {
 579 #define HNS3_VF_NUM_IN_FIRST_DESC 192
 580         uint8_t word_num;
 581         uint8_t bit_num;
 582
 583         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
 584                 word_num = vfid / 32;
 585                 bit_num = vfid % 32;
 586                 if (clr)
 587                         desc[1].data[word_num] &=
 588                             rte_cpu_to_le_32(~(1UL << bit_num));
 589                 else
 590                         desc[1].data[word_num] |=
 591                             rte_cpu_to_le_32(1UL << bit_num);
 592         } else {
 593                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
 594                 bit_num = vfid % 32;
 595                 if (clr)
 596                         desc[2].data[word_num] &=
 597                             rte_cpu_to_le_32(~(1UL << bit_num));
 598                 else
 599                         desc[2].data[word_num] |=
 600                             rte_cpu_to_le_32(1UL << bit_num);
 601         }
 602 }
 603
 604 static int
 605 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 606 {
 607         struct hns3_mac_vlan_tbl_entry_cmd req;
 608         struct hns3_cmd_desc desc[3];
 609         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 610         uint8_t vf_id;
 611         int ret;
 612
 613         /* Check if mac addr is valid */
 614         if (!rte_is_multicast_ether_addr(mac_addr)) {
 615                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 616                                       mac_addr);
 617                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
 618                          mac_str);
 619                 return -EINVAL;
 620         }
 621
 622         memset(&req, 0, sizeof(req));
 623         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 624         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 625         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 626         if (ret) {
 627                 /* This mac addr do not exist, add new entry for it */
 628                 memset(desc[0].data, 0, sizeof(desc[0].data));
 629                 memset(desc[1].data, 0, sizeof(desc[0].data));
 630                 memset(desc[2].data, 0, sizeof(desc[0].data));
 631         }
 632
 633         /*
 634          * In current version VF is not supported when PF is driven by DPDK
 635          * driver, the PF-related vf_id is 0, just need to configure parameters
 636          * for vf_id 0.
 637          */
 638         vf_id = 0;
 639         hns3_update_desc_vfid(desc, vf_id, false);
 640         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
 641         if (ret) {
 642                 if (ret == -ENOSPC)
 643                         hns3_err(hw, "mc mac vlan table is full");
 644                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 645                                       mac_addr);
 646                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
 647         }
 648
 649         return ret;
 650 }
 651
 652 static int
 653 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 654 {
 655         struct hns3_mac_vlan_tbl_entry_cmd req;
 656         struct hns3_cmd_desc desc[3];
 657         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 658         uint8_t vf_id;
 659         int ret;
 660
 661         /* Check if mac addr is valid */
 662         if (!rte_is_multicast_ether_addr(mac_addr)) {
 663                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 664                                       mac_addr);
 665                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
 666                          mac_str);
 667                 return -EINVAL;
 668         }
 669
 670         memset(&req, 0, sizeof(req));
 671         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
 672         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
 673         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
 674         if (ret == 0) {
 675                 /*
 676                  * This mac addr exist, remove this handle's VFID for it.
 677                  * In current version VF is not supported when PF is driven by
 678                  * DPDK driver, the PF-related vf_id is 0, just need to
 679                  * configure parameters for vf_id 0.
 680                  */
 681                 vf_id = 0;
 682                 hns3_update_desc_vfid(desc, vf_id, true);
 683
 684                 /* All the vfid is zero, so need to delete this entry */
 685                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
 686         } else if (ret == -ENOENT) {
 687                 /* This mac addr doesn't exist. */
 688                 return 0;
 689         }
 690
 691         if (ret) {
 692                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 693                                       mac_addr);
 694                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
 695         }
 696
 697         return ret;
 698 }
 699
 700 static int
 701 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
 702                            struct rte_ether_addr *mc_addr_set,
 703                            uint32_t nb_mc_addr)
 704 {
 705         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 706         struct rte_ether_addr *addr;
 707         uint32_t i;
 708         uint32_t j;
 709
 710         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 711                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 712                          "invalid. valid range: 0~%d",
 713                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 714                 return -EINVAL;
 715         }
 716
 717         /* Check if input mac addresses are valid */
 718         for (i = 0; i < nb_mc_addr; i++) {
 719                 addr = &mc_addr_set[i];
 720                 if (!rte_is_multicast_ether_addr(addr)) {
 721                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 722                                               addr);
 723                         hns3_err(hw,
 724                                  "Failed to set mc mac addr, addr(%s) invalid.",
 725                                  mac_str);
 726                         return -EINVAL;
 727                 }
 728
 729                 /* Check if there are duplicate addresses */
 730                 for (j = i + 1; j < nb_mc_addr; j++) {
 731                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 732                                 rte_ether_format_addr(mac_str,
 733                                                       RTE_ETHER_ADDR_FMT_SIZE,
 734                                                       addr);
 735                                 hns3_err(hw, "Failed to set mc mac addr, "
 736                                          "addrs invalid. two same addrs(%s).",
 737                                          mac_str);
 738                                 return -EINVAL;
 739                         }
 740                 }
 741         }
 742
 743         return 0;
 744 }
 745
 746 static void
 747 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
 748                            struct rte_ether_addr *mc_addr_set,
 749                            int mc_addr_num,
 750                            struct rte_ether_addr *reserved_addr_list,
 751                            int *reserved_addr_num,
 752                            struct rte_ether_addr *add_addr_list,
 753                            int *add_addr_num,
 754                            struct rte_ether_addr *rm_addr_list,
 755                            int *rm_addr_num)
 756 {
 757         struct rte_ether_addr *addr;
 758         int current_addr_num;
 759         int reserved_num = 0;
 760         int add_num = 0;
 761         int rm_num = 0;
 762         int num;
 763         int i;
 764         int j;
 765         bool same_addr;
 766
 767         /* Calculate the mc mac address list that should be removed */
 768         current_addr_num = hw->mc_addrs_num;
 769         for (i = 0; i < current_addr_num; i++) {
 770                 addr = &hw->mc_addrs[i];
 771                 same_addr = false;
 772                 for (j = 0; j < mc_addr_num; j++) {
 773                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 774                                 same_addr = true;
 775                                 break;
 776                         }
 777                 }
 778
 779                 if (!same_addr) {
 780                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
 781                         rm_num++;
 782                 } else {
 783                         rte_ether_addr_copy(addr,
 784                                             &reserved_addr_list[reserved_num]);
 785                         reserved_num++;
 786                 }
 787         }
 788
 789         /* Calculate the mc mac address list that should be added */
 790         for (i = 0; i < mc_addr_num; i++) {
 791                 addr = &mc_addr_set[i];
 792                 same_addr = false;
 793                 for (j = 0; j < current_addr_num; j++) {
 794                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
 795                                 same_addr = true;
 796                                 break;
 797                         }
 798                 }
 799
 800                 if (!same_addr) {
 801                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
 802                         add_num++;
 803                 }
 804         }
 805
 806         /* Reorder the mc mac address list maintained by driver */
 807         for (i = 0; i < reserved_num; i++)
 808                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
 809
 810         for (i = 0; i < rm_num; i++) {
 811                 num = reserved_num + i;
 812                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
 813         }
 814
 815         *reserved_addr_num = reserved_num;
 816         *add_addr_num = add_num;
 817         *rm_addr_num = rm_num;
 818 }
 819
 820 static int
 821 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 822                           struct rte_ether_addr *mc_addr_set,
 823                           uint32_t nb_mc_addr)
 824 {
 825         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 826         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
 827         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
 828         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
 829         struct rte_ether_addr *addr;
 830         int reserved_addr_num;
 831         int add_addr_num;
 832         int rm_addr_num;
 833         int mc_addr_num;
 834         int num;
 835         int ret;
 836         int i;
 837
 838         /* Check if input parameters are valid */
 839         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 840         if (ret)
 841                 return ret;
 842
 843         rte_spinlock_lock(&hw->lock);
 844
 845         /*
 846          * Calculate the mc mac address lists those should be removed and be
 847          * added, Reorder the mc mac address list maintained by driver.
 848          */
 849         mc_addr_num = (int)nb_mc_addr;
 850         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
 851                                    reserved_addr_list, &reserved_addr_num,
 852                                    add_addr_list, &add_addr_num,
 853                                    rm_addr_list, &rm_addr_num);
 854
 855         /* Remove mc mac addresses */
 856         for (i = 0; i < rm_addr_num; i++) {
 857                 num = rm_addr_num - i - 1;
 858                 addr = &rm_addr_list[num];
 859                 ret = hns3_remove_mc_addr(hw, addr);
 860                 if (ret) {
 861                         rte_spinlock_unlock(&hw->lock);
 862                         return ret;
 863                 }
 864                 hw->mc_addrs_num--;
 865         }
 866
 867         /* Add mc mac addresses */
 868         for (i = 0; i < add_addr_num; i++) {
 869                 addr = &add_addr_list[i];
 870                 ret = hns3_add_mc_addr(hw, addr);
 871                 if (ret) {
 872                         rte_spinlock_unlock(&hw->lock);
 873                         return ret;
 874                 }
 875
 876                 num = reserved_addr_num + i;
 877                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
 878                 hw->mc_addrs_num++;
 879         }
 880         rte_spinlock_unlock(&hw->lock);
 881
 882         return 0;
 883 }
 884
 885 static int
 886 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 887 {
 888         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 889         struct hns3_hw *hw = &hns->hw;
 890         struct rte_ether_addr *addr;
 891         int err = 0;
 892         int ret;
 893         int i;
 894
 895         for (i = 0; i < hw->mc_addrs_num; i++) {
 896                 addr = &hw->mc_addrs[i];
 897                 if (!rte_is_multicast_ether_addr(addr))
 898                         continue;
 899                 if (del)
 900                         ret = hns3_remove_mc_addr(hw, addr);
 901                 else
 902                         ret = hns3_add_mc_addr(hw, addr);
 903                 if (ret) {
 904                         err = ret;
 905                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 906                                               addr);
 907                         hns3_dbg(hw, "%s mc mac addr: %s failed",
 908                                  del ? "Remove" : "Restore", mac_str);
 909                 }
 910         }
 911         return err;
 912 }
 913
 914 static int
 915 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
 916 {
 917         struct hns3_config_max_frm_size_cmd *req;
 918         struct hns3_cmd_desc desc;
 919
 920         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
 921
 922         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
 923         req->max_frm_size = rte_cpu_to_le_16(new_mps);
 924         req->min_frm_size = HNS3_MIN_FRAME_LEN;
 925
 926         return hns3_cmd_send(hw, &desc, 1);
 927 }
 928
 929 static int
 930 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
 931 {
 932         int ret;
 933
 934         ret = hns3_set_mac_mtu(hw, mps);
 935         if (ret) {
 936                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
 937                 return ret;
 938         }
 939
 940         ret = hns3_buffer_alloc(hw);
 941         if (ret) {
 942                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
 943                 return ret;
 944         }
 945
 946         return 0;
 947 }
 948
 949 static int
 950 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 951 {
 952         struct hns3_adapter *hns = dev->data->dev_private;
 953         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 954         struct hns3_hw *hw = &hns->hw;
 955         bool is_jumbo_frame;
 956         int ret;
 957
 958         if (dev->data->dev_started) {
 959                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
 960                          "before configuration", dev->data->port_id);
 961                 return -EBUSY;
 962         }
 963
 964         rte_spinlock_lock(&hw->lock);
 965         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
 966         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
 967
 968         /*
 969          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
 970          * assign to "uint16_t" type variable.
 971          */
 972         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
 973         if (ret) {
 974                 rte_spinlock_unlock(&hw->lock);
 975                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
 976                          dev->data->port_id, mtu, ret);
 977                 return ret;
 978         }
 979         hns->pf.mps = (uint16_t)frame_size;
 980         if (is_jumbo_frame)
 981                 dev->data->dev_conf.rxmode.offloads |=
 982                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 983         else
 984                 dev->data->dev_conf.rxmode.offloads &=
 985                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 986         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 987         rte_spinlock_unlock(&hw->lock);
 988
 989         return 0;
 990 }
 991
 992 static int
 993 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 994 {
 995         struct hns3_adapter *hns = eth_dev->data->dev_private;
 996         struct hns3_hw *hw = &hns->hw;
 997
 998         info->max_rx_queues = hw->tqps_num;
 999         info->max_tx_queues = hw->tqps_num;
1000         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
1001         info->min_rx_bufsize = hw->rx_buf_len;
1002         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
1003         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
1004         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
1005                                  DEV_RX_OFFLOAD_TCP_CKSUM |
1006                                  DEV_RX_OFFLOAD_UDP_CKSUM |
1007                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
1008                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1009                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1010                                  DEV_RX_OFFLOAD_KEEP_CRC |
1011                                  DEV_RX_OFFLOAD_SCATTER |
1012                                  DEV_RX_OFFLOAD_VLAN_STRIP |
1013                                  DEV_RX_OFFLOAD_QINQ_STRIP |
1014                                  DEV_RX_OFFLOAD_VLAN_FILTER |
1015                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
1016                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
1017         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1018         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1019                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
1020                                  DEV_TX_OFFLOAD_TCP_CKSUM |
1021                                  DEV_TX_OFFLOAD_UDP_CKSUM |
1022                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
1023                                  DEV_TX_OFFLOAD_VLAN_INSERT |
1024                                  DEV_TX_OFFLOAD_QINQ_INSERT |
1025                                  DEV_TX_OFFLOAD_MULTI_SEGS |
1026                                  info->tx_queue_offload_capa);
1027
1028         info->vmdq_queue_num = 0;
1029
1030         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1031         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1032         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1033         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1034
1035         return 0;
1036 }
1037
1038 static int
1039 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1040                     size_t fw_size)
1041 {
1042         struct hns3_adapter *hns = eth_dev->data->dev_private;
1043         struct hns3_hw *hw = &hns->hw;
1044         int ret;
1045
1046         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
1047         ret += 1; /* add the size of '\0' */
1048         if (fw_size < (uint32_t)ret)
1049                 return ret;
1050         else
1051                 return 0;
1052 }
1053
1054 static int
1055 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
1056                      __rte_unused int wait_to_complete)
1057 {
1058         struct hns3_adapter *hns = eth_dev->data->dev_private;
1059         struct hns3_hw *hw = &hns->hw;
1060         struct hns3_mac *mac = &hw->mac;
1061         struct rte_eth_link new_link;
1062
1063         memset(&new_link, 0, sizeof(new_link));
1064         switch (mac->link_speed) {
1065         case ETH_SPEED_NUM_10M:
1066         case ETH_SPEED_NUM_100M:
1067         case ETH_SPEED_NUM_1G:
1068         case ETH_SPEED_NUM_10G:
1069         case ETH_SPEED_NUM_25G:
1070         case ETH_SPEED_NUM_40G:
1071         case ETH_SPEED_NUM_50G:
1072         case ETH_SPEED_NUM_100G:
1073                 new_link.link_speed = mac->link_speed;
1074                 break;
1075         default:
1076                 new_link.link_speed = ETH_SPEED_NUM_100M;
1077                 break;
1078         }
1079
1080         new_link.link_duplex = mac->link_duplex;
1081         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1082         new_link.link_autoneg =
1083             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1084
1085         return rte_eth_linkstatus_set(eth_dev, &new_link);
1086 }
1087
1088 static int
1089 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
1090 {
1091         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1092         struct hns3_pf *pf = &hns->pf;
1093
1094         if (!(status->pf_state & HNS3_PF_STATE_DONE))
1095                 return -EINVAL;
1096
1097         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
1098
1099         return 0;
1100 }
1101
1102 static int
1103 hns3_query_function_status(struct hns3_hw *hw)
1104 {
1105 #define HNS3_QUERY_MAX_CNT              10
1106 #define HNS3_QUERY_SLEEP_MSCOEND        1
1107         struct hns3_func_status_cmd *req;
1108         struct hns3_cmd_desc desc;
1109         int timeout = 0;
1110         int ret;
1111
1112         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
1113         req = (struct hns3_func_status_cmd *)desc.data;
1114
1115         do {
1116                 ret = hns3_cmd_send(hw, &desc, 1);
1117                 if (ret) {
1118                         PMD_INIT_LOG(ERR, "query function status failed %d",
1119                                      ret);
1120                         return ret;
1121                 }
1122
1123                 /* Check pf reset is done */
1124                 if (req->pf_state)
1125                         break;
1126
1127                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
1128         } while (timeout++ < HNS3_QUERY_MAX_CNT);
1129
1130         return hns3_parse_func_status(hw, req);
1131 }
1132
1133 static int
1134 hns3_query_pf_resource(struct hns3_hw *hw)
1135 {
1136         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1137         struct hns3_pf *pf = &hns->pf;
1138         struct hns3_pf_res_cmd *req;
1139         struct hns3_cmd_desc desc;
1140         int ret;
1141
1142         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
1143         ret = hns3_cmd_send(hw, &desc, 1);
1144         if (ret) {
1145                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
1146                 return ret;
1147         }
1148
1149         req = (struct hns3_pf_res_cmd *)desc.data;
1150         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
1151         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
1152         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1153
1154         if (req->tx_buf_size)
1155                 pf->tx_buf_size =
1156                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
1157         else
1158                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
1159
1160         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
1161
1162         if (req->dv_buf_size)
1163                 pf->dv_buf_size =
1164                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
1165         else
1166                 pf->dv_buf_size = HNS3_DEFAULT_DV;
1167
1168         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
1169
1170         hw->num_msi =
1171             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
1172                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
1173
1174         return 0;
1175 }
1176
1177 static void
1178 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
1179 {
1180         struct hns3_cfg_param_cmd *req;
1181         uint64_t mac_addr_tmp_high;
1182         uint64_t mac_addr_tmp;
1183         uint32_t i;
1184
1185         req = (struct hns3_cfg_param_cmd *)desc[0].data;
1186
1187         /* get the configuration */
1188         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1189                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
1190         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1191                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
1192         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
1193                                            HNS3_CFG_TQP_DESC_N_M,
1194                                            HNS3_CFG_TQP_DESC_N_S);
1195
1196         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1197                                        HNS3_CFG_PHY_ADDR_M,
1198                                        HNS3_CFG_PHY_ADDR_S);
1199         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1200                                          HNS3_CFG_MEDIA_TP_M,
1201                                          HNS3_CFG_MEDIA_TP_S);
1202         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1203                                          HNS3_CFG_RX_BUF_LEN_M,
1204                                          HNS3_CFG_RX_BUF_LEN_S);
1205         /* get mac address */
1206         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
1207         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1208                                            HNS3_CFG_MAC_ADDR_H_M,
1209                                            HNS3_CFG_MAC_ADDR_H_S);
1210
1211         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1212
1213         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1214                                             HNS3_CFG_DEFAULT_SPEED_M,
1215                                             HNS3_CFG_DEFAULT_SPEED_S);
1216         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
1217                                            HNS3_CFG_RSS_SIZE_M,
1218                                            HNS3_CFG_RSS_SIZE_S);
1219
1220         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
1221                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1222
1223         req = (struct hns3_cfg_param_cmd *)desc[1].data;
1224         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
1225
1226         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1227                                             HNS3_CFG_SPEED_ABILITY_M,
1228                                             HNS3_CFG_SPEED_ABILITY_S);
1229         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
1230                                         HNS3_CFG_UMV_TBL_SPACE_M,
1231                                         HNS3_CFG_UMV_TBL_SPACE_S);
1232         if (!cfg->umv_space)
1233                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
1234 }
1235
1236 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
1237  * @hw: pointer to struct hns3_hw
1238  * @hcfg: the config structure to be getted
1239  */
1240 static int
1241 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
1242 {
1243         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
1244         struct hns3_cfg_param_cmd *req;
1245         uint32_t offset;
1246         uint32_t i;
1247         int ret;
1248
1249         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
1250                 offset = 0;
1251                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
1252                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
1253                                           true);
1254                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
1255                                i * HNS3_CFG_RD_LEN_BYTES);
1256                 /* Len should be divided by 4 when send to hardware */
1257                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
1258                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
1259                 req->offset = rte_cpu_to_le_32(offset);
1260         }
1261
1262         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
1263         if (ret) {
1264                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
1265                 return ret;
1266         }
1267
1268         hns3_parse_cfg(hcfg, desc);
1269
1270         return 0;
1271 }
1272
1273 static int
1274 hns3_parse_speed(int speed_cmd, uint32_t *speed)
1275 {
1276         switch (speed_cmd) {
1277         case HNS3_CFG_SPEED_10M:
1278                 *speed = ETH_SPEED_NUM_10M;
1279                 break;
1280         case HNS3_CFG_SPEED_100M:
1281                 *speed = ETH_SPEED_NUM_100M;
1282                 break;
1283         case HNS3_CFG_SPEED_1G:
1284                 *speed = ETH_SPEED_NUM_1G;
1285                 break;
1286         case HNS3_CFG_SPEED_10G:
1287                 *speed = ETH_SPEED_NUM_10G;
1288                 break;
1289         case HNS3_CFG_SPEED_25G:
1290                 *speed = ETH_SPEED_NUM_25G;
1291                 break;
1292         case HNS3_CFG_SPEED_40G:
1293                 *speed = ETH_SPEED_NUM_40G;
1294                 break;
1295         case HNS3_CFG_SPEED_50G:
1296                 *speed = ETH_SPEED_NUM_50G;
1297                 break;
1298         case HNS3_CFG_SPEED_100G:
1299                 *speed = ETH_SPEED_NUM_100G;
1300                 break;
1301         default:
1302                 return -EINVAL;
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int
1309 hns3_get_board_configuration(struct hns3_hw *hw)
1310 {
1311         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1312         struct hns3_pf *pf = &hns->pf;
1313         struct hns3_cfg cfg;
1314         int ret;
1315
1316         ret = hns3_get_board_cfg(hw, &cfg);
1317         if (ret) {
1318                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
1319                 return ret;
1320         }
1321
1322         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
1323                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
1324                 return -EOPNOTSUPP;
1325         }
1326
1327         hw->mac.media_type = cfg.media_type;
1328         hw->rss_size_max = cfg.rss_size_max;
1329         hw->rx_buf_len = cfg.rx_buf_len;
1330         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
1331         hw->mac.phy_addr = cfg.phy_addr;
1332         hw->mac.default_addr_setted = false;
1333         hw->num_tx_desc = cfg.tqp_desc_num;
1334         hw->num_rx_desc = cfg.tqp_desc_num;
1335         hw->dcb_info.num_pg = 1;
1336         hw->dcb_info.hw_pfc_map = 0;
1337
1338         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
1339         if (ret) {
1340                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
1341                              cfg.default_speed, ret);
1342                 return ret;
1343         }
1344
1345         pf->tc_max = cfg.tc_num;
1346         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
1347                 PMD_INIT_LOG(WARNING,
1348                              "Get TC num(%u) from flash, set TC num to 1",
1349                              pf->tc_max);
1350                 pf->tc_max = 1;
1351         }
1352
1353         /* Dev does not support DCB */
1354         if (!hns3_dev_dcb_supported(hw)) {
1355                 pf->tc_max = 1;
1356                 pf->pfc_max = 0;
1357         } else
1358                 pf->pfc_max = pf->tc_max;
1359
1360         hw->dcb_info.num_tc = 1;
1361         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
1362                                      hw->tqps_num / hw->dcb_info.num_tc);
1363         hns3_set_bit(hw->hw_tc_map, 0, 1);
1364         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
1365
1366         pf->wanted_umv_size = cfg.umv_space;
1367
1368         return ret;
1369 }
1370
1371 static int
1372 hns3_get_configuration(struct hns3_hw *hw)
1373 {
1374         int ret;
1375
1376         ret = hns3_query_function_status(hw);
1377         if (ret) {
1378                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
1379                 return ret;
1380         }
1381
1382         /* Get pf resource */
1383         ret = hns3_query_pf_resource(hw);
1384         if (ret) {
1385                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
1386                 return ret;
1387         }
1388
1389         ret = hns3_get_board_configuration(hw);
1390         if (ret) {
1391                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
1392                 return ret;
1393         }
1394
1395         return 0;
1396 }
1397
1398 static int
1399 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
1400                       uint16_t tqp_vid, bool is_pf)
1401 {
1402         struct hns3_tqp_map_cmd *req;
1403         struct hns3_cmd_desc desc;
1404         int ret;
1405
1406         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
1407
1408         req = (struct hns3_tqp_map_cmd *)desc.data;
1409         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
1410         req->tqp_vf = func_id;
1411         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
1412         if (!is_pf)
1413                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
1414         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
1415
1416         ret = hns3_cmd_send(hw, &desc, 1);
1417         if (ret)
1418                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
1419
1420         return ret;
1421 }
1422
1423 static int
1424 hns3_map_tqp(struct hns3_hw *hw)
1425 {
1426         uint16_t tqps_num = hw->total_tqps_num;
1427         uint16_t func_id;
1428         uint16_t tqp_id;
1429         int num;
1430         int ret;
1431         int i;
1432
1433         /*
1434          * In current version VF is not supported when PF is driven by DPDK
1435          * driver, so we allocate tqps to PF as much as possible.
1436          */
1437         tqp_id = 0;
1438         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1439         for (func_id = 0; func_id < num; func_id++) {
1440                 for (i = 0;
1441                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
1442                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
1443                                                     true);
1444                         if (ret)
1445                                 return ret;
1446                 }
1447         }
1448
1449         return 0;
1450 }
1451
1452 static int
1453 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
1454 {
1455         struct hns3_config_mac_speed_dup_cmd *req;
1456         struct hns3_cmd_desc desc;
1457         int ret;
1458
1459         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
1460
1461         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
1462
1463         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
1464
1465         switch (speed) {
1466         case ETH_SPEED_NUM_10M:
1467                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1468                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
1469                 break;
1470         case ETH_SPEED_NUM_100M:
1471                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1472                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
1473                 break;
1474         case ETH_SPEED_NUM_1G:
1475                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1476                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
1477                 break;
1478         case ETH_SPEED_NUM_10G:
1479                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1480                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
1481                 break;
1482         case ETH_SPEED_NUM_25G:
1483                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1484                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
1485                 break;
1486         case ETH_SPEED_NUM_40G:
1487                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1488                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
1489                 break;
1490         case ETH_SPEED_NUM_50G:
1491                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1492                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
1493                 break;
1494         case ETH_SPEED_NUM_100G:
1495                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
1496                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
1497                 break;
1498         default:
1499                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
1500                 return -EINVAL;
1501         }
1502
1503         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
1504
1505         ret = hns3_cmd_send(hw, &desc, 1);
1506         if (ret)
1507                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
1508
1509         return ret;
1510 }
1511
1512 static int
1513 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1514 {
1515         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1516         struct hns3_pf *pf = &hns->pf;
1517         struct hns3_priv_buf *priv;
1518         uint32_t i, total_size;
1519
1520         total_size = pf->pkt_buf_size;
1521
1522         /* alloc tx buffer for all enabled tc */
1523         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1524                 priv = &buf_alloc->priv_buf[i];
1525
1526                 if (hw->hw_tc_map & BIT(i)) {
1527                         if (total_size < pf->tx_buf_size)
1528                                 return -ENOMEM;
1529
1530                         priv->tx_buf_size = pf->tx_buf_size;
1531                 } else
1532                         priv->tx_buf_size = 0;
1533
1534                 total_size -= priv->tx_buf_size;
1535         }
1536
1537         return 0;
1538 }
1539
1540 static int
1541 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1542 {
1543 /* TX buffer size is unit by 128 byte */
1544 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
1545 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
1546         struct hns3_tx_buff_alloc_cmd *req;
1547         struct hns3_cmd_desc desc;
1548         uint32_t buf_size;
1549         uint32_t i;
1550         int ret;
1551
1552         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
1553
1554         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
1555         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1556                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1557
1558                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
1559                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
1560                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
1561         }
1562
1563         ret = hns3_cmd_send(hw, &desc, 1);
1564         if (ret)
1565                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
1566
1567         return ret;
1568 }
1569
1570 static int
1571 hns3_get_tc_num(struct hns3_hw *hw)
1572 {
1573         int cnt = 0;
1574         uint8_t i;
1575
1576         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1577                 if (hw->hw_tc_map & BIT(i))
1578                         cnt++;
1579         return cnt;
1580 }
1581
1582 static uint32_t
1583 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1584 {
1585         struct hns3_priv_buf *priv;
1586         uint32_t rx_priv = 0;
1587         int i;
1588
1589         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1590                 priv = &buf_alloc->priv_buf[i];
1591                 if (priv->enable)
1592                         rx_priv += priv->buf_size;
1593         }
1594         return rx_priv;
1595 }
1596
1597 static uint32_t
1598 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
1599 {
1600         uint32_t total_tx_size = 0;
1601         uint32_t i;
1602
1603         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1604                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1605
1606         return total_tx_size;
1607 }
1608
1609 /* Get the number of pfc enabled TCs, which have private buffer */
1610 static int
1611 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1612 {
1613         struct hns3_priv_buf *priv;
1614         int cnt = 0;
1615         uint8_t i;
1616
1617         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1618                 priv = &buf_alloc->priv_buf[i];
1619                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1620                         cnt++;
1621         }
1622
1623         return cnt;
1624 }
1625
1626 /* Get the number of pfc disabled TCs, which have private buffer */
1627 static int
1628 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
1629                          struct hns3_pkt_buf_alloc *buf_alloc)
1630 {
1631         struct hns3_priv_buf *priv;
1632         int cnt = 0;
1633         uint8_t i;
1634
1635         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1636                 priv = &buf_alloc->priv_buf[i];
1637                 if (hw->hw_tc_map & BIT(i) &&
1638                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
1639                         cnt++;
1640         }
1641
1642         return cnt;
1643 }
1644
1645 static bool
1646 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
1647                   uint32_t rx_all)
1648 {
1649         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
1650         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1651         struct hns3_pf *pf = &hns->pf;
1652         uint32_t shared_buf, aligned_mps;
1653         uint32_t rx_priv;
1654         uint8_t tc_num;
1655         uint8_t i;
1656
1657         tc_num = hns3_get_tc_num(hw);
1658         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1659
1660         if (hns3_dev_dcb_supported(hw))
1661                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
1662                                         pf->dv_buf_size;
1663         else
1664                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
1665                                         + pf->dv_buf_size;
1666
1667         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
1668         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
1669                              HNS3_BUF_SIZE_UNIT);
1670
1671         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
1672         if (rx_all < rx_priv + shared_std)
1673                 return false;
1674
1675         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
1676         buf_alloc->s_buf.buf_size = shared_buf;
1677         if (hns3_dev_dcb_supported(hw)) {
1678                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
1679                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
1680                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
1681                                   HNS3_BUF_SIZE_UNIT);
1682         } else {
1683                 buf_alloc->s_buf.self.high =
1684                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1685                 buf_alloc->s_buf.self.low = aligned_mps;
1686         }
1687
1688         if (hns3_dev_dcb_supported(hw)) {
1689                 hi_thrd = shared_buf - pf->dv_buf_size;
1690
1691                 if (tc_num <= NEED_RESERVE_TC_NUM)
1692                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
1693                                         / BUF_MAX_PERCENT;
1694
1695                 if (tc_num)
1696                         hi_thrd = hi_thrd / tc_num;
1697
1698                 hi_thrd = max_t(uint32_t, hi_thrd,
1699                                 HNS3_BUF_MUL_BY * aligned_mps);
1700                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
1701                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
1702         } else {
1703                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
1704                 lo_thrd = aligned_mps;
1705         }
1706
1707         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1708                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
1709                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
1710         }
1711
1712         return true;
1713 }
1714
1715 static bool
1716 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
1717                      struct hns3_pkt_buf_alloc *buf_alloc)
1718 {
1719         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1720         struct hns3_pf *pf = &hns->pf;
1721         struct hns3_priv_buf *priv;
1722         uint32_t aligned_mps;
1723         uint32_t rx_all;
1724         uint8_t i;
1725
1726         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1727         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
1728
1729         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1730                 priv = &buf_alloc->priv_buf[i];
1731
1732                 priv->enable = 0;
1733                 priv->wl.low = 0;
1734                 priv->wl.high = 0;
1735                 priv->buf_size = 0;
1736
1737                 if (!(hw->hw_tc_map & BIT(i)))
1738                         continue;
1739
1740                 priv->enable = 1;
1741                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
1742                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
1743                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
1744                                                 HNS3_BUF_SIZE_UNIT);
1745                 } else {
1746                         priv->wl.low = 0;
1747                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
1748                                         aligned_mps;
1749                 }
1750
1751                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
1752         }
1753
1754         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1755 }
1756
1757 static bool
1758 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
1759                              struct hns3_pkt_buf_alloc *buf_alloc)
1760 {
1761         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1762         struct hns3_pf *pf = &hns->pf;
1763         struct hns3_priv_buf *priv;
1764         int no_pfc_priv_num;
1765         uint32_t rx_all;
1766         uint8_t mask;
1767         int i;
1768
1769         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1770         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
1771
1772         /* let the last to be cleared first */
1773         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1774                 priv = &buf_alloc->priv_buf[i];
1775                 mask = BIT((uint8_t)i);
1776
1777                 if (hw->hw_tc_map & mask &&
1778                     !(hw->dcb_info.hw_pfc_map & mask)) {
1779                         /* Clear the no pfc TC private buffer */
1780                         priv->wl.low = 0;
1781                         priv->wl.high = 0;
1782                         priv->buf_size = 0;
1783                         priv->enable = 0;
1784                         no_pfc_priv_num--;
1785                 }
1786
1787                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1788                     no_pfc_priv_num == 0)
1789                         break;
1790         }
1791
1792         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1793 }
1794
1795 static bool
1796 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
1797                            struct hns3_pkt_buf_alloc *buf_alloc)
1798 {
1799         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1800         struct hns3_pf *pf = &hns->pf;
1801         struct hns3_priv_buf *priv;
1802         uint32_t rx_all;
1803         int pfc_priv_num;
1804         uint8_t mask;
1805         int i;
1806
1807         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1808         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
1809
1810         /* let the last to be cleared first */
1811         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
1812                 priv = &buf_alloc->priv_buf[i];
1813                 mask = BIT((uint8_t)i);
1814
1815                 if (hw->hw_tc_map & mask &&
1816                     hw->dcb_info.hw_pfc_map & mask) {
1817                         /* Reduce the number of pfc TC with private buffer */
1818                         priv->wl.low = 0;
1819                         priv->enable = 0;
1820                         priv->wl.high = 0;
1821                         priv->buf_size = 0;
1822                         pfc_priv_num--;
1823                 }
1824                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
1825                     pfc_priv_num == 0)
1826                         break;
1827         }
1828
1829         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
1830 }
1831
1832 static bool
1833 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
1834                           struct hns3_pkt_buf_alloc *buf_alloc)
1835 {
1836 #define COMPENSATE_BUFFER       0x3C00
1837 #define COMPENSATE_HALF_MPS_NUM 5
1838 #define PRIV_WL_GAP             0x1800
1839         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1840         struct hns3_pf *pf = &hns->pf;
1841         uint32_t tc_num = hns3_get_tc_num(hw);
1842         uint32_t half_mps = pf->mps >> 1;
1843         struct hns3_priv_buf *priv;
1844         uint32_t min_rx_priv;
1845         uint32_t rx_priv;
1846         uint8_t i;
1847
1848         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
1849         if (tc_num)
1850                 rx_priv = rx_priv / tc_num;
1851
1852         if (tc_num <= NEED_RESERVE_TC_NUM)
1853                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
1854
1855         /*
1856          * Minimum value of private buffer in rx direction (min_rx_priv) is
1857          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
1858          * buffer if rx_priv is greater than min_rx_priv.
1859          */
1860         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
1861                         COMPENSATE_HALF_MPS_NUM * half_mps;
1862         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
1863         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
1864
1865         if (rx_priv < min_rx_priv)
1866                 return false;
1867
1868         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1869                 priv = &buf_alloc->priv_buf[i];
1870
1871                 priv->enable = 0;
1872                 priv->wl.low = 0;
1873                 priv->wl.high = 0;
1874                 priv->buf_size = 0;
1875
1876                 if (!(hw->hw_tc_map & BIT(i)))
1877                         continue;
1878
1879                 priv->enable = 1;
1880                 priv->buf_size = rx_priv;
1881                 priv->wl.high = rx_priv - pf->dv_buf_size;
1882                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
1883         }
1884
1885         buf_alloc->s_buf.buf_size = 0;
1886
1887         return true;
1888 }
1889
1890 /*
1891  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
1892  * @hw: pointer to struct hns3_hw
1893  * @buf_alloc: pointer to buffer calculation data
1894  * @return: 0: calculate sucessful, negative: fail
1895  */
1896 static int
1897 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1898 {
1899         /* When DCB is not supported, rx private buffer is not allocated. */
1900         if (!hns3_dev_dcb_supported(hw)) {
1901                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1902                 struct hns3_pf *pf = &hns->pf;
1903                 uint32_t rx_all = pf->pkt_buf_size;
1904
1905                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
1906                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
1907                         return -ENOMEM;
1908
1909                 return 0;
1910         }
1911
1912         /*
1913          * Try to allocate privated packet buffer for all TCs without share
1914          * buffer.
1915          */
1916         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
1917                 return 0;
1918
1919         /*
1920          * Try to allocate privated packet buffer for all TCs with share
1921          * buffer.
1922          */
1923         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
1924                 return 0;
1925
1926         /*
1927          * For different application scenes, the enabled port number, TC number
1928          * and no_drop TC number are different. In order to obtain the better
1929          * performance, software could allocate the buffer size and configure
1930          * the waterline by tring to decrease the private buffer size according
1931          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
1932          * enabled tc.
1933          */
1934         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
1935                 return 0;
1936
1937         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
1938                 return 0;
1939
1940         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
1941                 return 0;
1942
1943         return -ENOMEM;
1944 }
1945
1946 static int
1947 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1948 {
1949         struct hns3_rx_priv_buff_cmd *req;
1950         struct hns3_cmd_desc desc;
1951         uint32_t buf_size;
1952         int ret;
1953         int i;
1954
1955         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
1956         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
1957
1958         /* Alloc private buffer TCs */
1959         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1960                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
1961
1962                 req->buf_num[i] =
1963                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
1964                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
1965         }
1966
1967         buf_size = buf_alloc->s_buf.buf_size;
1968         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
1969                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
1970
1971         ret = hns3_cmd_send(hw, &desc, 1);
1972         if (ret)
1973                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
1974
1975         return ret;
1976 }
1977
1978 static int
1979 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
1980 {
1981 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
1982         struct hns3_rx_priv_wl_buf *req;
1983         struct hns3_priv_buf *priv;
1984         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
1985         int i, j;
1986         int ret;
1987
1988         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
1989                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
1990                                           false);
1991                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
1992
1993                 /* The first descriptor set the NEXT bit to 1 */
1994                 if (i == 0)
1995                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1996                 else
1997                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1998
1999                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2000                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
2001
2002                         priv = &buf_alloc->priv_buf[idx];
2003                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
2004                                                         HNS3_BUF_UNIT_S);
2005                         req->tc_wl[j].high |=
2006                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2007                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
2008                                                         HNS3_BUF_UNIT_S);
2009                         req->tc_wl[j].low |=
2010                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2011                 }
2012         }
2013
2014         /* Send 2 descriptor at one time */
2015         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
2016         if (ret)
2017                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
2018                              ret);
2019         return ret;
2020 }
2021
2022 static int
2023 hns3_common_thrd_config(struct hns3_hw *hw,
2024                         struct hns3_pkt_buf_alloc *buf_alloc)
2025 {
2026 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
2027         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
2028         struct hns3_rx_com_thrd *req;
2029         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
2030         struct hns3_tc_thrd *tc;
2031         int tc_idx;
2032         int i, j;
2033         int ret;
2034
2035         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
2036                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
2037                                           false);
2038                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
2039
2040                 /* The first descriptor set the NEXT bit to 1 */
2041                 if (i == 0)
2042                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2043                 else
2044                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
2045
2046                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
2047                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
2048                         tc = &s_buf->tc_thrd[tc_idx];
2049
2050                         req->com_thrd[j].high =
2051                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
2052                         req->com_thrd[j].high |=
2053                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2054                         req->com_thrd[j].low =
2055                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
2056                         req->com_thrd[j].low |=
2057                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2058                 }
2059         }
2060
2061         /* Send 2 descriptors at one time */
2062         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
2063         if (ret)
2064                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
2065
2066         return ret;
2067 }
2068
2069 static int
2070 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2071 {
2072         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
2073         struct hns3_rx_com_wl *req;
2074         struct hns3_cmd_desc desc;
2075         int ret;
2076
2077         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
2078
2079         req = (struct hns3_rx_com_wl *)desc.data;
2080         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
2081         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2082
2083         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
2084         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
2085
2086         ret = hns3_cmd_send(hw, &desc, 1);
2087         if (ret)
2088                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
2089
2090         return ret;
2091 }
2092
2093 int
2094 hns3_buffer_alloc(struct hns3_hw *hw)
2095 {
2096         struct hns3_pkt_buf_alloc pkt_buf;
2097         int ret;
2098
2099         memset(&pkt_buf, 0, sizeof(pkt_buf));
2100         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
2101         if (ret) {
2102                 PMD_INIT_LOG(ERR,
2103                              "could not calc tx buffer size for all TCs %d",
2104                              ret);
2105                 return ret;
2106         }
2107
2108         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
2109         if (ret) {
2110                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
2111                 return ret;
2112         }
2113
2114         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
2115         if (ret) {
2116                 PMD_INIT_LOG(ERR,
2117                              "could not calc rx priv buffer size for all TCs %d",
2118                              ret);
2119                 return ret;
2120         }
2121
2122         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
2123         if (ret) {
2124                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
2125                 return ret;
2126         }
2127
2128         if (hns3_dev_dcb_supported(hw)) {
2129                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
2130                 if (ret) {
2131                         PMD_INIT_LOG(ERR,
2132                                      "could not configure rx private waterline %d",
2133                                      ret);
2134                         return ret;
2135                 }
2136
2137                 ret = hns3_common_thrd_config(hw, &pkt_buf);
2138                 if (ret) {
2139                         PMD_INIT_LOG(ERR,
2140                                      "could not configure common threshold %d",
2141                                      ret);
2142                         return ret;
2143                 }
2144         }
2145
2146         ret = hns3_common_wl_config(hw, &pkt_buf);
2147         if (ret)
2148                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
2149                              ret);
2150
2151         return ret;
2152 }
2153
2154 static int
2155 hns3_mac_init(struct hns3_hw *hw)
2156 {
2157         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2158         struct hns3_mac *mac = &hw->mac;
2159         struct hns3_pf *pf = &hns->pf;
2160         int ret;
2161
2162         pf->support_sfp_query = true;
2163         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
2164         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
2165         if (ret) {
2166                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
2167                 return ret;
2168         }
2169
2170         mac->link_status = ETH_LINK_DOWN;
2171
2172         return hns3_config_mtu(hw, pf->mps);
2173 }
2174
2175 static int
2176 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
2177 {
2178 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
2179 #define HNS3_ETHERTYPE_ALREADY_ADD              1
2180 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
2181 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
2182         int return_status;
2183
2184         if (cmdq_resp) {
2185                 PMD_INIT_LOG(ERR,
2186                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
2187                              cmdq_resp);
2188                 return -EIO;
2189         }
2190
2191         switch (resp_code) {
2192         case HNS3_ETHERTYPE_SUCCESS_ADD:
2193         case HNS3_ETHERTYPE_ALREADY_ADD:
2194                 return_status = 0;
2195                 break;
2196         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
2197                 PMD_INIT_LOG(ERR,
2198                              "add mac ethertype failed for manager table overflow.");
2199                 return_status = -EIO;
2200                 break;
2201         case HNS3_ETHERTYPE_KEY_CONFLICT:
2202                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
2203                 return_status = -EIO;
2204                 break;
2205         default:
2206                 PMD_INIT_LOG(ERR,
2207                              "add mac ethertype failed for undefined, code=%d.",
2208                              resp_code);
2209                 return_status = -EIO;
2210         }
2211
2212         return return_status;
2213 }
2214
2215 static int
2216 hns3_add_mgr_tbl(struct hns3_hw *hw,
2217                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
2218 {
2219         struct hns3_cmd_desc desc;
2220         uint8_t resp_code;
2221         uint16_t retval;
2222         int ret;
2223
2224         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
2225         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
2226
2227         ret = hns3_cmd_send(hw, &desc, 1);
2228         if (ret) {
2229                 PMD_INIT_LOG(ERR,
2230                              "add mac ethertype failed for cmd_send, ret =%d.",
2231                              ret);
2232                 return ret;
2233         }
2234
2235         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
2236         retval = rte_le_to_cpu_16(desc.retval);
2237
2238         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
2239 }
2240
2241 static void
2242 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
2243                      int *table_item_num)
2244 {
2245         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
2246
2247         /*
2248          * In current version, we add one item in management table as below:
2249          * 0x0180C200000E -- LLDP MC address
2250          */
2251         tbl = mgr_table;
2252         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
2253         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
2254         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
2255         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
2256         tbl->i_port_bitmap = 0x1;
2257         *table_item_num = 1;
2258 }
2259
2260 static int
2261 hns3_init_mgr_tbl(struct hns3_hw *hw)
2262 {
2263 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
2264         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
2265         int table_item_num;
2266         int ret;
2267         int i;
2268
2269         memset(mgr_table, 0, sizeof(mgr_table));
2270         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
2271         for (i = 0; i < table_item_num; i++) {
2272                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
2273                 if (ret) {
2274                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
2275                                      ret);
2276                         return ret;
2277                 }
2278         }
2279
2280         return 0;
2281 }
2282
2283 static void
2284 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
2285                         bool en_mc, bool en_bc, int vport_id)
2286 {
2287         if (!param)
2288                 return;
2289
2290         memset(param, 0, sizeof(struct hns3_promisc_param));
2291         if (en_uc)
2292                 param->enable = HNS3_PROMISC_EN_UC;
2293         if (en_mc)
2294                 param->enable |= HNS3_PROMISC_EN_MC;
2295         if (en_bc)
2296                 param->enable |= HNS3_PROMISC_EN_BC;
2297         param->vf_id = vport_id;
2298 }
2299
2300 static int
2301 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
2302 {
2303         struct hns3_promisc_cfg_cmd *req;
2304         struct hns3_cmd_desc desc;
2305         int ret;
2306
2307         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
2308
2309         req = (struct hns3_promisc_cfg_cmd *)desc.data;
2310         req->vf_id = param->vf_id;
2311         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
2312             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
2313
2314         ret = hns3_cmd_send(hw, &desc, 1);
2315         if (ret)
2316                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
2317
2318         return ret;
2319 }
2320
2321 static int
2322 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
2323 {
2324         struct hns3_promisc_param param;
2325         bool en_bc_pmc = true;
2326         uint8_t vf_id;
2327         int ret;
2328
2329         /*
2330          * In current version VF is not supported when PF is driven by DPDK
2331          * driver, the PF-related vf_id is 0, just need to configure parameters
2332          * for vf_id 0.
2333          */
2334         vf_id = 0;
2335
2336         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
2337         ret = hns3_cmd_set_promisc_mode(hw, &param);
2338         if (ret)
2339                 return ret;
2340
2341         return 0;
2342 }
2343
2344 static int
2345 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
2346 {
2347         struct hns3_sfp_speed_cmd *resp;
2348         struct hns3_cmd_desc desc;
2349         int ret;
2350
2351         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
2352         resp = (struct hns3_sfp_speed_cmd *)desc.data;
2353         ret = hns3_cmd_send(hw, &desc, 1);
2354         if (ret == -EOPNOTSUPP) {
2355                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
2356                 return ret;
2357         } else if (ret) {
2358                 hns3_err(hw, "get sfp speed failed %d", ret);
2359                 return ret;
2360         }
2361
2362         *speed = resp->sfp_speed;
2363
2364         return 0;
2365 }
2366
2367 static uint8_t
2368 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
2369 {
2370         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
2371                 duplex = ETH_LINK_FULL_DUPLEX;
2372
2373         return duplex;
2374 }
2375
2376 static int
2377 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2378 {
2379         struct hns3_mac *mac = &hw->mac;
2380         int ret;
2381
2382         duplex = hns3_check_speed_dup(duplex, speed);
2383         if (mac->link_speed == speed && mac->link_duplex == duplex)
2384                 return 0;
2385
2386         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
2387         if (ret)
2388                 return ret;
2389
2390         mac->link_speed = speed;
2391         mac->link_duplex = duplex;
2392
2393         return 0;
2394 }
2395
2396 static int
2397 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
2398 {
2399         struct hns3_adapter *hns = eth_dev->data->dev_private;
2400         struct hns3_hw *hw = &hns->hw;
2401         struct hns3_pf *pf = &hns->pf;
2402         uint32_t speed;
2403         int ret;
2404
2405         /* If IMP do not support get SFP/qSFP speed, return directly */
2406         if (!pf->support_sfp_query)
2407                 return 0;
2408
2409         ret = hns3_get_sfp_speed(hw, &speed);
2410         if (ret == -EOPNOTSUPP) {
2411                 pf->support_sfp_query = false;
2412                 return ret;
2413         } else if (ret)
2414                 return ret;
2415
2416         if (speed == ETH_SPEED_NUM_NONE)
2417                 return 0; /* do nothing if no SFP */
2418
2419         /* Config full duplex for SFP */
2420         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
2421 }
2422
2423 static int
2424 hns3_get_mac_link_status(struct hns3_hw *hw)
2425 {
2426         struct hns3_link_status_cmd *req;
2427         struct hns3_cmd_desc desc;
2428         int link_status;
2429         int ret;
2430
2431         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
2432         ret = hns3_cmd_send(hw, &desc, 1);
2433         if (ret) {
2434                 hns3_err(hw, "get link status cmd failed %d", ret);
2435                 return ret;
2436         }
2437
2438         req = (struct hns3_link_status_cmd *)desc.data;
2439         link_status = req->status & HNS3_LINK_STATUS_UP_M;
2440
2441         return !!link_status;
2442 }
2443
2444 static void
2445 hns3_update_link_status(struct hns3_hw *hw)
2446 {
2447         int state;
2448
2449         state = hns3_get_mac_link_status(hw);
2450         if (state != hw->mac.link_status)
2451                 hw->mac.link_status = state;
2452 }
2453
2454 static void
2455 hns3_service_handler(void *param)
2456 {
2457         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
2458         struct hns3_adapter *hns = eth_dev->data->dev_private;
2459         struct hns3_hw *hw = &hns->hw;
2460
2461         hns3_update_speed_duplex(eth_dev);
2462         hns3_update_link_status(hw);
2463
2464         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2465 }
2466
2467 static int
2468 hns3_init_hardware(struct hns3_adapter *hns)
2469 {
2470         struct hns3_hw *hw = &hns->hw;
2471         int ret;
2472
2473         ret = hns3_map_tqp(hw);
2474         if (ret) {
2475                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
2476                 return ret;
2477         }
2478
2479         ret = hns3_init_umv_space(hw);
2480         if (ret) {
2481                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
2482                 return ret;
2483         }
2484
2485         ret = hns3_mac_init(hw);
2486         if (ret) {
2487                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
2488                 goto err_mac_init;
2489         }
2490
2491         ret = hns3_init_mgr_tbl(hw);
2492         if (ret) {
2493                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
2494                 goto err_mac_init;
2495         }
2496
2497         ret = hns3_set_promisc_mode(hw, false, false);
2498         if (ret) {
2499                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
2500                 goto err_mac_init;
2501         }
2502
2503         ret = hns3_init_fd_config(hns);
2504         if (ret) {
2505                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
2506                 goto err_mac_init;
2507         }
2508
2509         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
2510         if (ret) {
2511                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
2512                 goto err_mac_init;
2513         }
2514
2515         ret = hns3_config_gro(hw, false);
2516         if (ret) {
2517                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
2518                 goto err_mac_init;
2519         }
2520         return 0;
2521
2522 err_mac_init:
2523         hns3_uninit_umv_space(hw);
2524         return ret;
2525 }
2526
2527 static int
2528 hns3_init_pf(struct rte_eth_dev *eth_dev)
2529 {
2530         struct rte_device *dev = eth_dev->device;
2531         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2532         struct hns3_adapter *hns = eth_dev->data->dev_private;
2533         struct hns3_hw *hw = &hns->hw;
2534         int ret;
2535
2536         PMD_INIT_FUNC_TRACE();
2537
2538         /* Get hardware io base address from pcie BAR2 IO space */
2539         hw->io_base = pci_dev->mem_resource[2].addr;
2540
2541         /* Firmware command queue initialize */
2542         ret = hns3_cmd_init_queue(hw);
2543         if (ret) {
2544                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
2545                 goto err_cmd_init_queue;
2546         }
2547
2548         /* Firmware command initialize */
2549         ret = hns3_cmd_init(hw);
2550         if (ret) {
2551                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
2552                 goto err_cmd_init;
2553         }
2554
2555         /* Get configuration */
2556         ret = hns3_get_configuration(hw);
2557         if (ret) {
2558                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
2559                 goto err_get_config;
2560         }
2561
2562         ret = hns3_init_hardware(hns);
2563         if (ret) {
2564                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
2565                 goto err_get_config;
2566         }
2567
2568         /* Initialize flow director filter list & hash */
2569         ret = hns3_fdir_filter_init(hns);
2570         if (ret) {
2571                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
2572                 goto err_hw_init;
2573         }
2574
2575         return 0;
2576
2577 err_hw_init:
2578         hns3_uninit_umv_space(hw);
2579
2580 err_get_config:
2581         hns3_cmd_uninit(hw);
2582
2583 err_cmd_init:
2584         hns3_cmd_destroy_queue(hw);
2585
2586 err_cmd_init_queue:
2587         hw->io_base = NULL;
2588
2589         return ret;
2590 }
2591
2592 static void
2593 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
2594 {
2595         struct hns3_adapter *hns = eth_dev->data->dev_private;
2596         struct hns3_hw *hw = &hns->hw;
2597
2598         PMD_INIT_FUNC_TRACE();
2599
2600         hns3_fdir_filter_uninit(hns);
2601         hns3_uninit_umv_space(hw);
2602         hns3_cmd_uninit(hw);
2603         hns3_cmd_destroy_queue(hw);
2604         hw->io_base = NULL;
2605 }
2606
2607 static void
2608 hns3_dev_close(struct rte_eth_dev *eth_dev)
2609 {
2610         struct hns3_adapter *hns = eth_dev->data->dev_private;
2611         struct hns3_hw *hw = &hns->hw;
2612
2613         hw->adapter_state = HNS3_NIC_CLOSING;
2614         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
2615
2616         hns3_configure_all_mc_mac_addr(hns, true);
2617         hns3_uninit_pf(eth_dev);
2618         rte_free(eth_dev->process_private);
2619         eth_dev->process_private = NULL;
2620         hw->adapter_state = HNS3_NIC_CLOSED;
2621 }
2622
2623 static const struct eth_dev_ops hns3_eth_dev_ops = {
2624         .dev_close          = hns3_dev_close,
2625         .mtu_set            = hns3_dev_mtu_set,
2626         .dev_infos_get          = hns3_dev_infos_get,
2627         .fw_version_get         = hns3_fw_version_get,
2628         .mac_addr_add           = hns3_add_mac_addr,
2629         .mac_addr_remove        = hns3_remove_mac_addr,
2630         .mac_addr_set           = hns3_set_default_mac_addr,
2631         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
2632         .link_update            = hns3_dev_link_update,
2633         .filter_ctrl            = hns3_dev_filter_ctrl,
2634 };
2635
2636 static int
2637 hns3_dev_init(struct rte_eth_dev *eth_dev)
2638 {
2639         struct hns3_adapter *hns = eth_dev->data->dev_private;
2640         struct hns3_hw *hw = &hns->hw;
2641         int ret;
2642
2643         PMD_INIT_FUNC_TRACE();
2644         eth_dev->process_private = (struct hns3_process_private *)
2645             rte_zmalloc_socket("hns3_filter_list",
2646                                sizeof(struct hns3_process_private),
2647                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2648         if (eth_dev->process_private == NULL) {
2649                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2650                 return -ENOMEM;
2651         }
2652         /* initialize flow filter lists */
2653         hns3_filterlist_init(eth_dev);
2654
2655         eth_dev->dev_ops = &hns3_eth_dev_ops;
2656         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2657                 return 0;
2658
2659         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2660         hns->is_vf = false;
2661         hw->data = eth_dev->data;
2662
2663         /*
2664          * Set default max packet size according to the mtu
2665          * default vale in DPDK frame.
2666          */
2667         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
2668
2669         ret = hns3_init_pf(eth_dev);
2670         if (ret) {
2671                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
2672                 goto err_init_pf;
2673         }
2674
2675         /* Allocate memory for storing MAC addresses */
2676         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
2677                                                sizeof(struct rte_ether_addr) *
2678                                                HNS3_UC_MACADDR_NUM, 0);
2679         if (eth_dev->data->mac_addrs == NULL) {
2680                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2681                              "to store MAC addresses",
2682                              sizeof(struct rte_ether_addr) *
2683                              HNS3_UC_MACADDR_NUM);
2684                 ret = -ENOMEM;
2685                 goto err_rte_zmalloc;
2686         }
2687
2688         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2689                             &eth_dev->data->mac_addrs[0]);
2690
2691         hw->adapter_state = HNS3_NIC_INITIALIZED;
2692         /*
2693          * Pass the information to the rte_eth_dev_close() that it should also
2694          * release the private port resources.
2695          */
2696         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2697
2698         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
2699         hns3_info(hw, "hns3 dev initialization successful!");
2700         return 0;
2701
2702 err_rte_zmalloc:
2703         hns3_uninit_pf(eth_dev);
2704
2705 err_init_pf:
2706         eth_dev->dev_ops = NULL;
2707         eth_dev->rx_pkt_burst = NULL;
2708         eth_dev->tx_pkt_burst = NULL;
2709         eth_dev->tx_pkt_prepare = NULL;
2710         rte_free(eth_dev->process_private);
2711         eth_dev->process_private = NULL;
2712         return ret;
2713 }
2714
2715 static int
2716 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
2717 {
2718         struct hns3_adapter *hns = eth_dev->data->dev_private;
2719         struct hns3_hw *hw = &hns->hw;
2720
2721         PMD_INIT_FUNC_TRACE();
2722
2723         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2724                 return -EPERM;
2725
2726         eth_dev->dev_ops = NULL;
2727         eth_dev->rx_pkt_burst = NULL;
2728         eth_dev->tx_pkt_burst = NULL;
2729         eth_dev->tx_pkt_prepare = NULL;
2730         if (hw->adapter_state < HNS3_NIC_CLOSING)
2731                 hns3_dev_close(eth_dev);
2732
2733         hw->adapter_state = HNS3_NIC_REMOVED;
2734         return 0;
2735 }
2736
2737 static int
2738 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2739                    struct rte_pci_device *pci_dev)
2740 {
2741         return rte_eth_dev_pci_generic_probe(pci_dev,
2742                                              sizeof(struct hns3_adapter),
2743                                              hns3_dev_init);
2744 }
2745
2746 static int
2747 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
2748 {
2749         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
2750 }
2751
2752 static const struct rte_pci_id pci_id_hns3_map[] = {
2753         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
2754         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
2755         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
2756         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
2757         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
2758         { .vendor_id = 0, /* sentinel */ },
2759 };
2760
2761 static struct rte_pci_driver rte_hns3_pmd = {
2762         .id_table = pci_id_hns3_map,
2763         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2764         .probe = eth_hns3_pci_probe,
2765         .remove = eth_hns3_pci_remove,
2766 };
2767
2768 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
2769 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
2770 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
2771
2772 RTE_INIT(hns3_init_log)
2773 {
2774         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
2775         if (hns3_logtype_init >= 0)
2776                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
2777         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
2778         if (hns3_logtype_driver >= 0)
2779                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
2780 }