drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static int hns3_add_mc_addr(struct hns3_hw *hw,
  83                             struct rte_ether_addr *mac_addr);
  84 static int hns3_remove_mc_addr(struct hns3_hw *hw,
  85                             struct rte_ether_addr *mac_addr);
  86
  87 static void
  88 hns3_pf_disable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  91 }
  92
  93 static void
  94 hns3_pf_enable_irq0(struct hns3_hw *hw)
  95 {
  96         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  97 }
  98
  99 static enum hns3_evt_cause
 100 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 101 {
 102         struct hns3_hw *hw = &hns->hw;
 103         uint32_t vector0_int_stats;
 104         uint32_t cmdq_src_val;
 105         uint32_t val;
 106         enum hns3_evt_cause ret;
 107
 108         /* fetch the events from their corresponding regs */
 109         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 110         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 111
 112         /*
 113          * Assumption: If by any chance reset and mailbox events are reported
 114          * together then we will only process reset event and defer the
 115          * processing of the mailbox events. Since, we would have not cleared
 116          * RX CMDQ event this time we would receive again another interrupt
 117          * from H/W just for the mailbox.
 118          */
 119         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 120                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 121                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 122                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 123                 if (clearval) {
 124                         hw->reset.stats.imp_cnt++;
 125                         hns3_warn(hw, "IMP reset detected, clear reset status");
 126                 } else {
 127                         hns3_schedule_delayed_reset(hns);
 128                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 129                 }
 130
 131                 ret = HNS3_VECTOR0_EVENT_RST;
 132                 goto out;
 133         }
 134
 135         /* Global reset */
 136         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 137                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 138                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 139                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 140                 if (clearval) {
 141                         hw->reset.stats.global_cnt++;
 142                         hns3_warn(hw, "Global reset detected, clear reset status");
 143                 } else {
 144                         hns3_schedule_delayed_reset(hns);
 145                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 146                 }
 147
 148                 ret = HNS3_VECTOR0_EVENT_RST;
 149                 goto out;
 150         }
 151
 152         /* check for vector0 msix event source */
 153         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 154                 val = vector0_int_stats;
 155                 ret = HNS3_VECTOR0_EVENT_ERR;
 156                 goto out;
 157         }
 158
 159         /* check for vector0 mailbox(=CMDQ RX) event source */
 160         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 161                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 162                 val = cmdq_src_val;
 163                 ret = HNS3_VECTOR0_EVENT_MBX;
 164                 goto out;
 165         }
 166
 167         if (clearval && (vector0_int_stats || cmdq_src_val))
 168                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 169                           vector0_int_stats, cmdq_src_val);
 170         val = vector0_int_stats;
 171         ret = HNS3_VECTOR0_EVENT_OTHER;
 172 out:
 173
 174         if (clearval)
 175                 *clearval = val;
 176         return ret;
 177 }
 178
 179 static void
 180 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 181 {
 182         if (event_type == HNS3_VECTOR0_EVENT_RST)
 183                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 184         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 185                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 186 }
 187
 188 static void
 189 hns3_clear_all_event_cause(struct hns3_hw *hw)
 190 {
 191         uint32_t vector0_int_stats;
 192         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 193
 194         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 195                 hns3_warn(hw, "Probe during IMP reset interrupt");
 196
 197         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 198                 hns3_warn(hw, "Probe during Global reset interrupt");
 199
 200         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 201                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 202                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 203                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 204         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 205 }
 206
 207 static void
 208 hns3_interrupt_handler(void *param)
 209 {
 210         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 211         struct hns3_adapter *hns = dev->data->dev_private;
 212         struct hns3_hw *hw = &hns->hw;
 213         enum hns3_evt_cause event_cause;
 214         uint32_t clearval = 0;
 215
 216         /* Disable interrupt */
 217         hns3_pf_disable_irq0(hw);
 218
 219         event_cause = hns3_check_event_cause(hns, &clearval);
 220
 221         /* vector 0 interrupt is shared with reset and mailbox source events. */
 222         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 223                 hns3_handle_msix_error(hns, &hw->reset.request);
 224                 hns3_schedule_reset(hns);
 225         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 226                 hns3_schedule_reset(hns);
 227         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 228                 hns3_dev_handle_mbx_msg(hw);
 229         else
 230                 hns3_err(hw, "Received unknown event");
 231
 232         hns3_clear_event_cause(hw, event_cause, clearval);
 233         /* Enable interrupt if it is not cause by reset */
 234         hns3_pf_enable_irq0(hw);
 235 }
 236
 237 static int
 238 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 239 {
 240 #define HNS3_VLAN_ID_OFFSET_STEP        160
 241 #define HNS3_VLAN_BYTE_SIZE             8
 242         struct hns3_vlan_filter_pf_cfg_cmd *req;
 243         struct hns3_hw *hw = &hns->hw;
 244         uint8_t vlan_offset_byte_val;
 245         struct hns3_cmd_desc desc;
 246         uint8_t vlan_offset_byte;
 247         uint8_t vlan_offset_base;
 248         int ret;
 249
 250         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 251
 252         vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
 253         vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
 254                            HNS3_VLAN_BYTE_SIZE;
 255         vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
 256
 257         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 258         req->vlan_offset = vlan_offset_base;
 259         req->vlan_cfg = on ? 0 : 1;
 260         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 261
 262         ret = hns3_cmd_send(hw, &desc, 1);
 263         if (ret)
 264                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 265                          vlan_id, ret);
 266
 267         return ret;
 268 }
 269
 270 static void
 271 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 272 {
 273         struct hns3_user_vlan_table *vlan_entry;
 274         struct hns3_pf *pf = &hns->pf;
 275
 276         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 277                 if (vlan_entry->vlan_id == vlan_id) {
 278                         if (vlan_entry->hd_tbl_status)
 279                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 280                         LIST_REMOVE(vlan_entry, next);
 281                         rte_free(vlan_entry);
 282                         break;
 283                 }
 284         }
 285 }
 286
 287 static void
 288 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 289                         bool writen_to_tbl)
 290 {
 291         struct hns3_user_vlan_table *vlan_entry;
 292         struct hns3_hw *hw = &hns->hw;
 293         struct hns3_pf *pf = &hns->pf;
 294
 295         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 296                 if (vlan_entry->vlan_id == vlan_id)
 297                         return;
 298         }
 299
 300         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 301         if (vlan_entry == NULL) {
 302                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 303                 return;
 304         }
 305
 306         vlan_entry->hd_tbl_status = writen_to_tbl;
 307         vlan_entry->vlan_id = vlan_id;
 308
 309         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 310 }
 311
 312 static int
 313 hns3_restore_vlan_table(struct hns3_adapter *hns)
 314 {
 315         struct hns3_user_vlan_table *vlan_entry;
 316         struct hns3_pf *pf = &hns->pf;
 317         uint16_t vlan_id;
 318         int ret = 0;
 319
 320         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
 321                 return hns3_vlan_pvid_configure(hns,
 322                                                 pf->port_base_vlan_cfg.pvid, 1);
 323
 324         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 325                 if (vlan_entry->hd_tbl_status) {
 326                         vlan_id = vlan_entry->vlan_id;
 327                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332
 333         return ret;
 334 }
 335
 336 static int
 337 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 338 {
 339         struct hns3_pf *pf = &hns->pf;
 340         bool writen_to_tbl = false;
 341         int ret = 0;
 342
 343         /*
 344          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 345          * for normal packet, deleting vlan id 0 is not allowed.
 346          */
 347         if (on == 0 && vlan_id == 0)
 348                 return 0;
 349
 350         /*
 351          * When port base vlan enabled, we use port base vlan as the vlan
 352          * filter condition. In this case, we don't update vlan filter table
 353          * when user add new vlan or remove exist vlan, just update the
 354          * vlan list. The vlan id in vlan list will be writen in vlan filter
 355          * table until port base vlan disabled
 356          */
 357         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 358                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 359                 writen_to_tbl = true;
 360         }
 361
 362         if (ret == 0 && vlan_id) {
 363                 if (on)
 364                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 365                 else
 366                         hns3_rm_dev_vlan_table(hns, vlan_id);
 367         }
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 373 {
 374         struct hns3_adapter *hns = dev->data->dev_private;
 375         struct hns3_hw *hw = &hns->hw;
 376         int ret;
 377
 378         rte_spinlock_lock(&hw->lock);
 379         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 380         rte_spinlock_unlock(&hw->lock);
 381         return ret;
 382 }
 383
 384 static int
 385 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 386                          uint16_t tpid)
 387 {
 388         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 389         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 390         struct hns3_hw *hw = &hns->hw;
 391         struct hns3_cmd_desc desc;
 392         int ret;
 393
 394         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 395              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 396                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         if (tpid != RTE_ETHER_TYPE_VLAN) {
 401                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 402                 return -EINVAL;
 403         }
 404
 405         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 406         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 407
 408         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 409                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 412                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 413                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 414                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 415                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 416         }
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret) {
 420                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 421                          ret);
 422                 return ret;
 423         }
 424
 425         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 426
 427         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 428         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 429         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 430
 431         ret = hns3_cmd_send(hw, &desc, 1);
 432         if (ret)
 433                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 434                          ret);
 435         return ret;
 436 }
 437
 438 static int
 439 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 440                    uint16_t tpid)
 441 {
 442         struct hns3_adapter *hns = dev->data->dev_private;
 443         struct hns3_hw *hw = &hns->hw;
 444         int ret;
 445
 446         rte_spinlock_lock(&hw->lock);
 447         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 448         rte_spinlock_unlock(&hw->lock);
 449         return ret;
 450 }
 451
 452 static int
 453 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 454                              struct hns3_rx_vtag_cfg *vcfg)
 455 {
 456         struct hns3_vport_vtag_rx_cfg_cmd *req;
 457         struct hns3_hw *hw = &hns->hw;
 458         struct hns3_cmd_desc desc;
 459         uint16_t vport_id;
 460         uint8_t bitmap;
 461         int ret;
 462
 463         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 464
 465         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 466         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 467                      vcfg->strip_tag1_en ? 1 : 0);
 468         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 469                      vcfg->strip_tag2_en ? 1 : 0);
 470         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 471                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 472         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 473                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 474
 475         /*
 476          * In current version VF is not supported when PF is driven by DPDK
 477          * driver, the PF-related vf_id is 0, just need to configure parameters
 478          * for vport_id 0.
 479          */
 480         vport_id = 0;
 481         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 482         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 483         req->vf_bitmap[req->vf_offset] = bitmap;
 484
 485         ret = hns3_cmd_send(hw, &desc, 1);
 486         if (ret)
 487                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 488         return ret;
 489 }
 490
 491 static void
 492 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 493                            struct hns3_rx_vtag_cfg *vcfg)
 494 {
 495         struct hns3_pf *pf = &hns->pf;
 496         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 497 }
 498
 499 static void
 500 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 501                            struct hns3_tx_vtag_cfg *vcfg)
 502 {
 503         struct hns3_pf *pf = &hns->pf;
 504         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 505 }
 506
 507 static int
 508 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 509 {
 510         struct hns3_rx_vtag_cfg rxvlan_cfg;
 511         struct hns3_pf *pf = &hns->pf;
 512         struct hns3_hw *hw = &hns->hw;
 513         int ret;
 514
 515         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 516                 rxvlan_cfg.strip_tag1_en = false;
 517                 rxvlan_cfg.strip_tag2_en = enable;
 518         } else {
 519                 rxvlan_cfg.strip_tag1_en = enable;
 520                 rxvlan_cfg.strip_tag2_en = true;
 521         }
 522
 523         rxvlan_cfg.vlan1_vlan_prionly = false;
 524         rxvlan_cfg.vlan2_vlan_prionly = false;
 525         rxvlan_cfg.rx_vlan_offload_en = enable;
 526
 527         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 528         if (ret) {
 529                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 530                 return ret;
 531         }
 532
 533         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 534
 535         return ret;
 536 }
 537
 538 static int
 539 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 540                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 541 {
 542         struct hns3_vlan_filter_ctrl_cmd *req;
 543         struct hns3_cmd_desc desc;
 544         int ret;
 545
 546         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 547
 548         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 549         req->vlan_type = vlan_type;
 550         req->vlan_fe = filter_en ? fe_type : 0;
 551         req->vf_id = vf_id;
 552
 553         ret = hns3_cmd_send(hw, &desc, 1);
 554         if (ret)
 555                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 556
 557         return ret;
 558 }
 559
 560 static int
 561 hns3_vlan_filter_init(struct hns3_adapter *hns)
 562 {
 563         struct hns3_hw *hw = &hns->hw;
 564         int ret;
 565
 566         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 567                                         HNS3_FILTER_FE_EGRESS, false, 0);
 568         if (ret) {
 569                 hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
 570                 return ret;
 571         }
 572
 573         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 574                                         HNS3_FILTER_FE_INGRESS, false, 0);
 575         if (ret)
 576                 hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
 577
 578         return ret;
 579 }
 580
 581 static int
 582 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 583 {
 584         struct hns3_hw *hw = &hns->hw;
 585         int ret;
 586
 587         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 588                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 589         if (ret)
 590                 hns3_err(hw, "failed to %s port vlan filter, ret = %d",
 591                          enable ? "enable" : "disable", ret);
 592
 593         return ret;
 594 }
 595
 596 static int
 597 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 598 {
 599         struct hns3_adapter *hns = dev->data->dev_private;
 600         struct hns3_hw *hw = &hns->hw;
 601         struct rte_eth_rxmode *rxmode;
 602         unsigned int tmp_mask;
 603         bool enable;
 604         int ret = 0;
 605
 606         rte_spinlock_lock(&hw->lock);
 607         rxmode = &dev->data->dev_conf.rxmode;
 608         tmp_mask = (unsigned int)mask;
 609         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
 610                 /* ignore vlan filter configuration during promiscuous mode */
 611                 if (!dev->data->promiscuous) {
 612                         /* Enable or disable VLAN filter */
 613                         enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
 614                                  true : false;
 615
 616                         ret = hns3_enable_vlan_filter(hns, enable);
 617                         if (ret) {
 618                                 rte_spinlock_unlock(&hw->lock);
 619                                 hns3_err(hw, "failed to %s rx filter, ret = %d",
 620                                          enable ? "enable" : "disable", ret);
 621                                 return ret;
 622                         }
 623                 }
 624         }
 625
 626         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 627                 /* Enable or disable VLAN stripping */
 628                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 629                     true : false;
 630
 631                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 632                 if (ret) {
 633                         rte_spinlock_unlock(&hw->lock);
 634                         hns3_err(hw, "failed to %s rx strip, ret = %d",
 635                                  enable ? "enable" : "disable", ret);
 636                         return ret;
 637                 }
 638         }
 639
 640         rte_spinlock_unlock(&hw->lock);
 641
 642         return ret;
 643 }
 644
 645 static int
 646 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 647                              struct hns3_tx_vtag_cfg *vcfg)
 648 {
 649         struct hns3_vport_vtag_tx_cfg_cmd *req;
 650         struct hns3_cmd_desc desc;
 651         struct hns3_hw *hw = &hns->hw;
 652         uint16_t vport_id;
 653         uint8_t bitmap;
 654         int ret;
 655
 656         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 657
 658         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 659         req->def_vlan_tag1 = vcfg->default_tag1;
 660         req->def_vlan_tag2 = vcfg->default_tag2;
 661         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 662                      vcfg->accept_tag1 ? 1 : 0);
 663         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 664                      vcfg->accept_untag1 ? 1 : 0);
 665         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 666                      vcfg->accept_tag2 ? 1 : 0);
 667         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 668                      vcfg->accept_untag2 ? 1 : 0);
 669         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 670                      vcfg->insert_tag1_en ? 1 : 0);
 671         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 672                      vcfg->insert_tag2_en ? 1 : 0);
 673         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 674
 675         /*
 676          * In current version VF is not supported when PF is driven by DPDK
 677          * driver, the PF-related vf_id is 0, just need to configure parameters
 678          * for vport_id 0.
 679          */
 680         vport_id = 0;
 681         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 682         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 683         req->vf_bitmap[req->vf_offset] = bitmap;
 684
 685         ret = hns3_cmd_send(hw, &desc, 1);
 686         if (ret)
 687                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 688
 689         return ret;
 690 }
 691
 692 static int
 693 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 694                      uint16_t pvid)
 695 {
 696         struct hns3_hw *hw = &hns->hw;
 697         struct hns3_tx_vtag_cfg txvlan_cfg;
 698         int ret;
 699
 700         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 701                 txvlan_cfg.accept_tag1 = true;
 702                 txvlan_cfg.insert_tag1_en = false;
 703                 txvlan_cfg.default_tag1 = 0;
 704         } else {
 705                 txvlan_cfg.accept_tag1 = false;
 706                 txvlan_cfg.insert_tag1_en = true;
 707                 txvlan_cfg.default_tag1 = pvid;
 708         }
 709
 710         txvlan_cfg.accept_untag1 = true;
 711         txvlan_cfg.accept_tag2 = true;
 712         txvlan_cfg.accept_untag2 = true;
 713         txvlan_cfg.insert_tag2_en = false;
 714         txvlan_cfg.default_tag2 = 0;
 715
 716         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 717         if (ret) {
 718                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 719                          ret);
 720                 return ret;
 721         }
 722
 723         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 724         return ret;
 725 }
 726
 727 static void
 728 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 729 {
 730         struct hns3_pf *pf = &hns->pf;
 731
 732         pf->port_base_vlan_cfg.state = on ?
 733             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 734
 735         pf->port_base_vlan_cfg.pvid = pvid;
 736 }
 737
 738 static void
 739 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 740 {
 741         struct hns3_user_vlan_table *vlan_entry;
 742         struct hns3_pf *pf = &hns->pf;
 743
 744         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 745                 if (vlan_entry->hd_tbl_status)
 746                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 747
 748                 vlan_entry->hd_tbl_status = false;
 749         }
 750
 751         if (is_del_list) {
 752                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 753                 while (vlan_entry) {
 754                         LIST_REMOVE(vlan_entry, next);
 755                         rte_free(vlan_entry);
 756                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 757                 }
 758         }
 759 }
 760
 761 static void
 762 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 763 {
 764         struct hns3_user_vlan_table *vlan_entry;
 765         struct hns3_pf *pf = &hns->pf;
 766
 767         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 768                 if (!vlan_entry->hd_tbl_status)
 769                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 770
 771                 vlan_entry->hd_tbl_status = true;
 772         }
 773 }
 774
 775 static void
 776 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 777 {
 778         struct hns3_hw *hw = &hns->hw;
 779         struct hns3_pf *pf = &hns->pf;
 780         int ret;
 781
 782         hns3_rm_all_vlan_table(hns, true);
 783         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 784                 ret = hns3_set_port_vlan_filter(hns,
 785                                                 pf->port_base_vlan_cfg.pvid, 0);
 786                 if (ret) {
 787                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 788                                  ret);
 789                         return;
 790                 }
 791         }
 792 }
 793
 794 static int
 795 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 796                                 uint16_t port_base_vlan_state,
 797                                 uint16_t new_pvid, uint16_t old_pvid)
 798 {
 799         struct hns3_pf *pf = &hns->pf;
 800         struct hns3_hw *hw = &hns->hw;
 801         int ret = 0;
 802
 803         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 804                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 805                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 806                         if (ret) {
 807                                 hns3_err(hw,
 808                                          "Failed to clear clear old pvid filter, ret =%d",
 809                                          ret);
 810                                 return ret;
 811                         }
 812                 }
 813
 814                 hns3_rm_all_vlan_table(hns, false);
 815                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 816         }
 817
 818         if (new_pvid != 0) {
 819                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 820                 if (ret) {
 821                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 822                                  ret);
 823                         return ret;
 824                 }
 825         }
 826
 827         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 828                 hns3_add_all_vlan_table(hns);
 829
 830         return ret;
 831 }
 832
 833 static int
 834 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 835 {
 836         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 837         struct hns3_hw *hw = &hns->hw;
 838         bool rx_strip_en;
 839         int ret;
 840
 841         rx_strip_en = on ? true : false;
 842         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 843         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 844         rx_vlan_cfg.vlan1_vlan_prionly = false;
 845         rx_vlan_cfg.vlan2_vlan_prionly = false;
 846         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 847
 848         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 849         if (ret) {
 850                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 851                 return ret;
 852         }
 853
 854         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 855         return ret;
 856 }
 857
 858 static int
 859 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 860 {
 861         struct hns3_pf *pf = &hns->pf;
 862         struct hns3_hw *hw = &hns->hw;
 863         uint16_t port_base_vlan_state;
 864         uint16_t old_pvid;
 865         int ret;
 866
 867         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 868                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 869                         hns3_warn(hw, "Invalid operation! As current pvid set "
 870                                   "is %u, disable pvid %u is invalid",
 871                                   pf->port_base_vlan_cfg.pvid, pvid);
 872                 return 0;
 873         }
 874
 875         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 876                                     HNS3_PORT_BASE_VLAN_DISABLE;
 877         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 878         if (ret) {
 879                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 880                 return ret;
 881         }
 882
 883         ret = hns3_en_rx_strip_all(hns, on);
 884         if (ret) {
 885                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 886                 return ret;
 887         }
 888
 889         if (pvid == HNS3_INVLID_PVID)
 890                 goto out;
 891         old_pvid = pf->port_base_vlan_cfg.pvid;
 892         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 893                                               old_pvid);
 894         if (ret) {
 895                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 896                          ret);
 897                 return ret;
 898         }
 899
 900 out:
 901         hns3_store_port_base_vlan_info(hns, pvid, on);
 902         return ret;
 903 }
 904
 905 static int
 906 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 907 {
 908         struct hns3_adapter *hns = dev->data->dev_private;
 909         struct hns3_hw *hw = &hns->hw;
 910         int ret;
 911
 912         if (pvid > RTE_ETHER_MAX_VLAN_ID) {
 913                 hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
 914                          RTE_ETHER_MAX_VLAN_ID);
 915                 return -EINVAL;
 916         }
 917
 918         rte_spinlock_lock(&hw->lock);
 919         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 920         rte_spinlock_unlock(&hw->lock);
 921         return ret;
 922 }
 923
 924 static void
 925 init_port_base_vlan_info(struct hns3_hw *hw)
 926 {
 927         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 928         struct hns3_pf *pf = &hns->pf;
 929
 930         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 931         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 932 }
 933
 934 static int
 935 hns3_default_vlan_config(struct hns3_adapter *hns)
 936 {
 937         struct hns3_hw *hw = &hns->hw;
 938         int ret;
 939
 940         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 941         if (ret)
 942                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 943         return ret;
 944 }
 945
 946 static int
 947 hns3_init_vlan_config(struct hns3_adapter *hns)
 948 {
 949         struct hns3_hw *hw = &hns->hw;
 950         int ret;
 951
 952         /*
 953          * This function can be called in the initialization and reset process,
 954          * when in reset process, it means that hardware had been reseted
 955          * successfully and we need to restore the hardware configuration to
 956          * ensure that the hardware configuration remains unchanged before and
 957          * after reset.
 958          */
 959         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 960                 init_port_base_vlan_info(hw);
 961
 962         ret = hns3_vlan_filter_init(hns);
 963         if (ret) {
 964                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 969                                        RTE_ETHER_TYPE_VLAN);
 970         if (ret) {
 971                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 972                 return ret;
 973         }
 974
 975         /*
 976          * When in the reinit dev stage of the reset process, the following
 977          * vlan-related configurations may differ from those at initialization,
 978          * we will restore configurations to hardware in hns3_restore_vlan_table
 979          * and hns3_restore_vlan_conf later.
 980          */
 981         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 982                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 983                 if (ret) {
 984                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 985                         return ret;
 986                 }
 987
 988                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 989                 if (ret) {
 990                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 991                                  ret);
 992                         return ret;
 993                 }
 994         }
 995
 996         return hns3_default_vlan_config(hns);
 997 }
 998
 999 static int
1000 hns3_restore_vlan_conf(struct hns3_adapter *hns)
1001 {
1002         struct hns3_pf *pf = &hns->pf;
1003         struct hns3_hw *hw = &hns->hw;
1004         uint64_t offloads;
1005         bool enable;
1006         int ret;
1007
1008         if (!hw->data->promiscuous) {
1009                 /* restore vlan filter states */
1010                 offloads = hw->data->dev_conf.rxmode.offloads;
1011                 enable = offloads & DEV_RX_OFFLOAD_VLAN_FILTER ? true : false;
1012                 ret = hns3_enable_vlan_filter(hns, enable);
1013                 if (ret) {
1014                         hns3_err(hw, "failed to restore vlan rx filter conf, "
1015                                  "ret = %d", ret);
1016                         return ret;
1017                 }
1018         }
1019
1020         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
1021         if (ret) {
1022                 hns3_err(hw, "failed to restore vlan rx conf, ret = %d", ret);
1023                 return ret;
1024         }
1025
1026         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
1027         if (ret)
1028                 hns3_err(hw, "failed to restore vlan tx conf, ret = %d", ret);
1029
1030         return ret;
1031 }
1032
1033 static int
1034 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
1035 {
1036         struct hns3_adapter *hns = dev->data->dev_private;
1037         struct rte_eth_dev_data *data = dev->data;
1038         struct rte_eth_txmode *txmode;
1039         struct hns3_hw *hw = &hns->hw;
1040         int mask;
1041         int ret;
1042
1043         txmode = &data->dev_conf.txmode;
1044         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
1045                 hns3_warn(hw,
1046                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
1047                           "configuration is not supported! Ignore these two "
1048                           "parameters: hw_vlan_reject_tagged(%d), "
1049                           "hw_vlan_reject_untagged(%d)",
1050                           txmode->hw_vlan_reject_tagged,
1051                           txmode->hw_vlan_reject_untagged);
1052
1053         /* Apply vlan offload setting */
1054         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
1055         ret = hns3_vlan_offload_set(dev, mask);
1056         if (ret) {
1057                 hns3_err(hw, "dev config rx vlan offload failed, ret = %d",
1058                          ret);
1059                 return ret;
1060         }
1061
1062         /* Apply pvid setting */
1063         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1064                                  txmode->hw_vlan_insert_pvid);
1065         if (ret)
1066                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret = %d",
1067                          txmode->pvid, ret);
1068
1069         return ret;
1070 }
1071
1072 static int
1073 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1074                 unsigned int tso_mss_max)
1075 {
1076         struct hns3_cfg_tso_status_cmd *req;
1077         struct hns3_cmd_desc desc;
1078         uint16_t tso_mss;
1079
1080         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1081
1082         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1083
1084         tso_mss = 0;
1085         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1086                        tso_mss_min);
1087         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1088
1089         tso_mss = 0;
1090         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1091                        tso_mss_max);
1092         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1093
1094         return hns3_cmd_send(hw, &desc, 1);
1095 }
1096
1097 int
1098 hns3_config_gro(struct hns3_hw *hw, bool en)
1099 {
1100         struct hns3_cfg_gro_status_cmd *req;
1101         struct hns3_cmd_desc desc;
1102         int ret;
1103
1104         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1105         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1106
1107         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1108
1109         ret = hns3_cmd_send(hw, &desc, 1);
1110         if (ret)
1111                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1112
1113         return ret;
1114 }
1115
1116 static int
1117 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1118                    uint16_t *allocated_size, bool is_alloc)
1119 {
1120         struct hns3_umv_spc_alc_cmd *req;
1121         struct hns3_cmd_desc desc;
1122         int ret;
1123
1124         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1125         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1126         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1127         req->space_size = rte_cpu_to_le_32(space_size);
1128
1129         ret = hns3_cmd_send(hw, &desc, 1);
1130         if (ret) {
1131                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1132                              is_alloc ? "allocate" : "free", ret);
1133                 return ret;
1134         }
1135
1136         if (is_alloc && allocated_size)
1137                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1138
1139         return 0;
1140 }
1141
1142 static int
1143 hns3_init_umv_space(struct hns3_hw *hw)
1144 {
1145         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1146         struct hns3_pf *pf = &hns->pf;
1147         uint16_t allocated_size = 0;
1148         int ret;
1149
1150         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1151                                  true);
1152         if (ret)
1153                 return ret;
1154
1155         if (allocated_size < pf->wanted_umv_size)
1156                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1157                              pf->wanted_umv_size, allocated_size);
1158
1159         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1160                                                 pf->wanted_umv_size;
1161         pf->used_umv_size = 0;
1162         return 0;
1163 }
1164
1165 static int
1166 hns3_uninit_umv_space(struct hns3_hw *hw)
1167 {
1168         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1169         struct hns3_pf *pf = &hns->pf;
1170         int ret;
1171
1172         if (pf->max_umv_size == 0)
1173                 return 0;
1174
1175         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1176         if (ret)
1177                 return ret;
1178
1179         pf->max_umv_size = 0;
1180
1181         return 0;
1182 }
1183
1184 static bool
1185 hns3_is_umv_space_full(struct hns3_hw *hw)
1186 {
1187         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1188         struct hns3_pf *pf = &hns->pf;
1189         bool is_full;
1190
1191         is_full = (pf->used_umv_size >= pf->max_umv_size);
1192
1193         return is_full;
1194 }
1195
1196 static void
1197 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1198 {
1199         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1200         struct hns3_pf *pf = &hns->pf;
1201
1202         if (is_free) {
1203                 if (pf->used_umv_size > 0)
1204                         pf->used_umv_size--;
1205         } else
1206                 pf->used_umv_size++;
1207 }
1208
1209 static void
1210 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1211                       const uint8_t *addr, bool is_mc)
1212 {
1213         const unsigned char *mac_addr = addr;
1214         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1215                             ((uint32_t)mac_addr[2] << 16) |
1216                             ((uint32_t)mac_addr[1] << 8) |
1217                             (uint32_t)mac_addr[0];
1218         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1219
1220         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1221         if (is_mc) {
1222                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1223                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1224                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1225         }
1226
1227         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1228         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1229 }
1230
1231 static int
1232 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1233                              uint8_t resp_code,
1234                              enum hns3_mac_vlan_tbl_opcode op)
1235 {
1236         if (cmdq_resp) {
1237                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1238                          cmdq_resp);
1239                 return -EIO;
1240         }
1241
1242         if (op == HNS3_MAC_VLAN_ADD) {
1243                 if (resp_code == 0 || resp_code == 1) {
1244                         return 0;
1245                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1246                         hns3_err(hw, "add mac addr failed for uc_overflow");
1247                         return -ENOSPC;
1248                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1249                         hns3_err(hw, "add mac addr failed for mc_overflow");
1250                         return -ENOSPC;
1251                 }
1252
1253                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1254                          resp_code);
1255                 return -EIO;
1256         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1257                 if (resp_code == 0) {
1258                         return 0;
1259                 } else if (resp_code == 1) {
1260                         hns3_dbg(hw, "remove mac addr failed for miss");
1261                         return -ENOENT;
1262                 }
1263
1264                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1265                          resp_code);
1266                 return -EIO;
1267         } else if (op == HNS3_MAC_VLAN_LKUP) {
1268                 if (resp_code == 0) {
1269                         return 0;
1270                 } else if (resp_code == 1) {
1271                         hns3_dbg(hw, "lookup mac addr failed for miss");
1272                         return -ENOENT;
1273                 }
1274
1275                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1276                          resp_code);
1277                 return -EIO;
1278         }
1279
1280         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1281                  op);
1282
1283         return -EINVAL;
1284 }
1285
1286 static int
1287 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1288                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1289                          struct hns3_cmd_desc *desc, bool is_mc)
1290 {
1291         uint8_t resp_code;
1292         uint16_t retval;
1293         int ret;
1294
1295         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1296         if (is_mc) {
1297                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1298                 memcpy(desc[0].data, req,
1299                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1300                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1301                                           true);
1302                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1303                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1304                                           true);
1305                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1306         } else {
1307                 memcpy(desc[0].data, req,
1308                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1309                 ret = hns3_cmd_send(hw, desc, 1);
1310         }
1311         if (ret) {
1312                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1313                          ret);
1314                 return ret;
1315         }
1316         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1317         retval = rte_le_to_cpu_16(desc[0].retval);
1318
1319         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1320                                             HNS3_MAC_VLAN_LKUP);
1321 }
1322
1323 static int
1324 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1325                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1326                       struct hns3_cmd_desc *mc_desc)
1327 {
1328         uint8_t resp_code;
1329         uint16_t retval;
1330         int cfg_status;
1331         int ret;
1332
1333         if (mc_desc == NULL) {
1334                 struct hns3_cmd_desc desc;
1335
1336                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1337                 memcpy(desc.data, req,
1338                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1339                 ret = hns3_cmd_send(hw, &desc, 1);
1340                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1341                 retval = rte_le_to_cpu_16(desc.retval);
1342
1343                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1344                                                           HNS3_MAC_VLAN_ADD);
1345         } else {
1346                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1347                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1348                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1349                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1350                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1351                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1352                 memcpy(mc_desc[0].data, req,
1353                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1354                 mc_desc[0].retval = 0;
1355                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1356                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1357                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1358
1359                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1360                                                           HNS3_MAC_VLAN_ADD);
1361         }
1362
1363         if (ret) {
1364                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1365                 return ret;
1366         }
1367
1368         return cfg_status;
1369 }
1370
1371 static int
1372 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1373                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1374 {
1375         struct hns3_cmd_desc desc;
1376         uint8_t resp_code;
1377         uint16_t retval;
1378         int ret;
1379
1380         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1381
1382         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1383
1384         ret = hns3_cmd_send(hw, &desc, 1);
1385         if (ret) {
1386                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1387                 return ret;
1388         }
1389         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1390         retval = rte_le_to_cpu_16(desc.retval);
1391
1392         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1393                                             HNS3_MAC_VLAN_REMOVE);
1394 }
1395
1396 static int
1397 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1398 {
1399         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1400         struct hns3_mac_vlan_tbl_entry_cmd req;
1401         struct hns3_pf *pf = &hns->pf;
1402         struct hns3_cmd_desc desc;
1403         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1404         uint16_t egress_port = 0;
1405         uint8_t vf_id;
1406         int ret;
1407
1408         /* check if mac addr is valid */
1409         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1410                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1411                                       mac_addr);
1412                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1413                          mac_str);
1414                 return -EINVAL;
1415         }
1416
1417         memset(&req, 0, sizeof(req));
1418
1419         /*
1420          * In current version VF is not supported when PF is driven by DPDK
1421          * driver, the PF-related vf_id is 0, just need to configure parameters
1422          * for vf_id 0.
1423          */
1424         vf_id = 0;
1425         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1426                        HNS3_MAC_EPORT_VFID_S, vf_id);
1427
1428         req.egress_port = rte_cpu_to_le_16(egress_port);
1429
1430         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1431
1432         /*
1433          * Lookup the mac address in the mac_vlan table, and add
1434          * it if the entry is inexistent. Repeated unicast entry
1435          * is not allowed in the mac vlan table.
1436          */
1437         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1438         if (ret == -ENOENT) {
1439                 if (!hns3_is_umv_space_full(hw)) {
1440                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1441                         if (!ret)
1442                                 hns3_update_umv_space(hw, false);
1443                         return ret;
1444                 }
1445
1446                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1447
1448                 return -ENOSPC;
1449         }
1450
1451         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1452
1453         /* check if we just hit the duplicate */
1454         if (ret == 0) {
1455                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1456                 return 0;
1457         }
1458
1459         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1460                  mac_str);
1461
1462         return ret;
1463 }
1464
1465 static int
1466 hns3_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1467 {
1468         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1469         struct rte_ether_addr *addr;
1470         int ret;
1471         int i;
1472
1473         for (i = 0; i < hw->mc_addrs_num; i++) {
1474                 addr = &hw->mc_addrs[i];
1475                 /* Check if there are duplicate addresses */
1476                 if (rte_is_same_ether_addr(addr, mac_addr)) {
1477                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1478                                               addr);
1479                         hns3_err(hw, "failed to add mc mac addr, same addrs"
1480                                  "(%s) is added by the set_mc_mac_addr_list "
1481                                  "API", mac_str);
1482                         return -EINVAL;
1483                 }
1484         }
1485
1486         ret = hns3_add_mc_addr(hw, mac_addr);
1487         if (ret) {
1488                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1489                                       mac_addr);
1490                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
1491                          mac_str, ret);
1492         }
1493         return ret;
1494 }
1495
1496 static int
1497 hns3_remove_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1498 {
1499         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1500         int ret;
1501
1502         ret = hns3_remove_mc_addr(hw, mac_addr);
1503         if (ret) {
1504                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1505                                       mac_addr);
1506                 hns3_err(hw, "failed to remove mc mac addr(%s), ret = %d",
1507                          mac_str, ret);
1508         }
1509         return ret;
1510 }
1511
1512 static int
1513 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1514                   uint32_t idx, __rte_unused uint32_t pool)
1515 {
1516         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1518         int ret;
1519
1520         rte_spinlock_lock(&hw->lock);
1521
1522         /*
1523          * In hns3 network engine adding UC and MC mac address with different
1524          * commands with firmware. We need to determine whether the input
1525          * address is a UC or a MC address to call different commands.
1526          * By the way, it is recommended calling the API function named
1527          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
1528          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
1529          * may affect the specifications of UC mac addresses.
1530          */
1531         if (rte_is_multicast_ether_addr(mac_addr))
1532                 ret = hns3_add_mc_addr_common(hw, mac_addr);
1533         else
1534                 ret = hns3_add_uc_addr_common(hw, mac_addr);
1535
1536         if (ret) {
1537                 rte_spinlock_unlock(&hw->lock);
1538                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1539                                       mac_addr);
1540                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
1541                          ret);
1542                 return ret;
1543         }
1544
1545         if (idx == 0)
1546                 hw->mac.default_addr_setted = true;
1547         rte_spinlock_unlock(&hw->lock);
1548
1549         return ret;
1550 }
1551
1552 static int
1553 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1554 {
1555         struct hns3_mac_vlan_tbl_entry_cmd req;
1556         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1557         int ret;
1558
1559         /* check if mac addr is valid */
1560         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1561                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1562                                       mac_addr);
1563                 hns3_err(hw, "remove unicast mac addr err! addr(%s) invalid",
1564                          mac_str);
1565                 return -EINVAL;
1566         }
1567
1568         memset(&req, 0, sizeof(req));
1569         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1570         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1571         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1572         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1573                 return 0;
1574         else if (ret == 0)
1575                 hns3_update_umv_space(hw, true);
1576
1577         return ret;
1578 }
1579
1580 static void
1581 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1582 {
1583         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1584         /* index will be checked by upper level rte interface */
1585         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1586         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1587         int ret;
1588
1589         rte_spinlock_lock(&hw->lock);
1590
1591         if (rte_is_multicast_ether_addr(mac_addr))
1592                 ret = hns3_remove_mc_addr_common(hw, mac_addr);
1593         else
1594                 ret = hns3_remove_uc_addr_common(hw, mac_addr);
1595         rte_spinlock_unlock(&hw->lock);
1596         if (ret) {
1597                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1598                                       mac_addr);
1599                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d", mac_str,
1600                          ret);
1601         }
1602 }
1603
1604 static int
1605 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1606                           struct rte_ether_addr *mac_addr)
1607 {
1608         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1609         struct rte_ether_addr *oaddr;
1610         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1611         bool default_addr_setted;
1612         bool rm_succes = false;
1613         int ret, ret_val;
1614
1615         /*
1616          * It has been guaranteed that input parameter named mac_addr is valid
1617          * address in the rte layer of DPDK framework.
1618          */
1619         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1620         default_addr_setted = hw->mac.default_addr_setted;
1621         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1622                 return 0;
1623
1624         rte_spinlock_lock(&hw->lock);
1625         if (default_addr_setted) {
1626                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1627                 if (ret) {
1628                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                               oaddr);
1630                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1631                                   mac_str, ret);
1632                         rm_succes = false;
1633                 } else
1634                         rm_succes = true;
1635         }
1636
1637         ret = hns3_add_uc_addr_common(hw, mac_addr);
1638         if (ret) {
1639                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1640                                       mac_addr);
1641                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1642                 goto err_add_uc_addr;
1643         }
1644
1645         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1646         if (ret) {
1647                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1648                 goto err_pause_addr_cfg;
1649         }
1650
1651         rte_ether_addr_copy(mac_addr,
1652                             (struct rte_ether_addr *)hw->mac.mac_addr);
1653         hw->mac.default_addr_setted = true;
1654         rte_spinlock_unlock(&hw->lock);
1655
1656         return 0;
1657
1658 err_pause_addr_cfg:
1659         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1660         if (ret_val) {
1661                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1662                                       mac_addr);
1663                 hns3_warn(hw,
1664                           "Failed to roll back to del setted mac addr(%s): %d",
1665                           mac_str, ret_val);
1666         }
1667
1668 err_add_uc_addr:
1669         if (rm_succes) {
1670                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1671                 if (ret_val) {
1672                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1673                                               oaddr);
1674                         hns3_warn(hw,
1675                                   "Failed to restore old uc mac addr(%s): %d",
1676                                   mac_str, ret_val);
1677                         hw->mac.default_addr_setted = false;
1678                 }
1679         }
1680         rte_spinlock_unlock(&hw->lock);
1681
1682         return ret;
1683 }
1684
1685 static int
1686 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1687 {
1688         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1689         struct hns3_hw *hw = &hns->hw;
1690         struct rte_ether_addr *addr;
1691         int err = 0;
1692         int ret;
1693         int i;
1694
1695         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1696                 addr = &hw->data->mac_addrs[i];
1697                 if (rte_is_zero_ether_addr(addr))
1698                         continue;
1699                 if (rte_is_multicast_ether_addr(addr))
1700                         ret = del ? hns3_remove_mc_addr(hw, addr) :
1701                               hns3_add_mc_addr(hw, addr);
1702                 else
1703                         ret = del ? hns3_remove_uc_addr_common(hw, addr) :
1704                               hns3_add_uc_addr_common(hw, addr);
1705
1706                 if (ret) {
1707                         err = ret;
1708                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1709                                               addr);
1710                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
1711                                  "ret = %d.", del ? "remove" : "restore",
1712                                  mac_str, i, ret);
1713                 }
1714         }
1715         return err;
1716 }
1717
1718 static void
1719 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1720 {
1721 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1722         uint8_t word_num;
1723         uint8_t bit_num;
1724
1725         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1726                 word_num = vfid / 32;
1727                 bit_num = vfid % 32;
1728                 if (clr)
1729                         desc[1].data[word_num] &=
1730                             rte_cpu_to_le_32(~(1UL << bit_num));
1731                 else
1732                         desc[1].data[word_num] |=
1733                             rte_cpu_to_le_32(1UL << bit_num);
1734         } else {
1735                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1736                 bit_num = vfid % 32;
1737                 if (clr)
1738                         desc[2].data[word_num] &=
1739                             rte_cpu_to_le_32(~(1UL << bit_num));
1740                 else
1741                         desc[2].data[word_num] |=
1742                             rte_cpu_to_le_32(1UL << bit_num);
1743         }
1744 }
1745
1746 static int
1747 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1748 {
1749         struct hns3_mac_vlan_tbl_entry_cmd req;
1750         struct hns3_cmd_desc desc[3];
1751         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1752         uint8_t vf_id;
1753         int ret;
1754
1755         /* Check if mac addr is valid */
1756         if (!rte_is_multicast_ether_addr(mac_addr)) {
1757                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1758                                       mac_addr);
1759                 hns3_err(hw, "failed to add mc mac addr, addr(%s) invalid",
1760                          mac_str);
1761                 return -EINVAL;
1762         }
1763
1764         memset(&req, 0, sizeof(req));
1765         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1766         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1767         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1768         if (ret) {
1769                 /* This mac addr do not exist, add new entry for it */
1770                 memset(desc[0].data, 0, sizeof(desc[0].data));
1771                 memset(desc[1].data, 0, sizeof(desc[0].data));
1772                 memset(desc[2].data, 0, sizeof(desc[0].data));
1773         }
1774
1775         /*
1776          * In current version VF is not supported when PF is driven by DPDK
1777          * driver, the PF-related vf_id is 0, just need to configure parameters
1778          * for vf_id 0.
1779          */
1780         vf_id = 0;
1781         hns3_update_desc_vfid(desc, vf_id, false);
1782         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1783         if (ret) {
1784                 if (ret == -ENOSPC)
1785                         hns3_err(hw, "mc mac vlan table is full");
1786                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1787                                       mac_addr);
1788                 hns3_err(hw, "failed to add mc mac addr(%s): %d", mac_str, ret);
1789         }
1790
1791         return ret;
1792 }
1793
1794 static int
1795 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1796 {
1797         struct hns3_mac_vlan_tbl_entry_cmd req;
1798         struct hns3_cmd_desc desc[3];
1799         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1800         uint8_t vf_id;
1801         int ret;
1802
1803         /* Check if mac addr is valid */
1804         if (!rte_is_multicast_ether_addr(mac_addr)) {
1805                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1806                                       mac_addr);
1807                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1808                          mac_str);
1809                 return -EINVAL;
1810         }
1811
1812         memset(&req, 0, sizeof(req));
1813         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1814         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1815         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1816         if (ret == 0) {
1817                 /*
1818                  * This mac addr exist, remove this handle's VFID for it.
1819                  * In current version VF is not supported when PF is driven by
1820                  * DPDK driver, the PF-related vf_id is 0, just need to
1821                  * configure parameters for vf_id 0.
1822                  */
1823                 vf_id = 0;
1824                 hns3_update_desc_vfid(desc, vf_id, true);
1825
1826                 /* All the vfid is zero, so need to delete this entry */
1827                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1828         } else if (ret == -ENOENT) {
1829                 /* This mac addr doesn't exist. */
1830                 return 0;
1831         }
1832
1833         if (ret) {
1834                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1835                                       mac_addr);
1836                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1837         }
1838
1839         return ret;
1840 }
1841
1842 static int
1843 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1844                            struct rte_ether_addr *mc_addr_set,
1845                            uint32_t nb_mc_addr)
1846 {
1847         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1848         struct rte_ether_addr *addr;
1849         uint32_t i;
1850         uint32_t j;
1851
1852         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1853                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
1854                          "invalid. valid range: 0~%d",
1855                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1856                 return -EINVAL;
1857         }
1858
1859         /* Check if input mac addresses are valid */
1860         for (i = 0; i < nb_mc_addr; i++) {
1861                 addr = &mc_addr_set[i];
1862                 if (!rte_is_multicast_ether_addr(addr)) {
1863                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1864                                               addr);
1865                         hns3_err(hw,
1866                                  "failed to set mc mac addr, addr(%s) invalid.",
1867                                  mac_str);
1868                         return -EINVAL;
1869                 }
1870
1871                 /* Check if there are duplicate addresses */
1872                 for (j = i + 1; j < nb_mc_addr; j++) {
1873                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1874                                 rte_ether_format_addr(mac_str,
1875                                                       RTE_ETHER_ADDR_FMT_SIZE,
1876                                                       addr);
1877                                 hns3_err(hw, "failed to set mc mac addr, "
1878                                          "addrs invalid. two same addrs(%s).",
1879                                          mac_str);
1880                                 return -EINVAL;
1881                         }
1882                 }
1883
1884                 /*
1885                  * Check if there are duplicate addresses between mac_addrs
1886                  * and mc_addr_set
1887                  */
1888                 for (j = 0; j < HNS3_UC_MACADDR_NUM; j++) {
1889                         if (rte_is_same_ether_addr(addr,
1890                                                    &hw->data->mac_addrs[j])) {
1891                                 rte_ether_format_addr(mac_str,
1892                                                       RTE_ETHER_ADDR_FMT_SIZE,
1893                                                       addr);
1894                                 hns3_err(hw, "failed to set mc mac addr, "
1895                                          "addrs invalid. addrs(%s) has already "
1896                                          "configured in mac_addr add API",
1897                                          mac_str);
1898                                 return -EINVAL;
1899                         }
1900                 }
1901         }
1902
1903         return 0;
1904 }
1905
1906 static void
1907 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1908                            struct rte_ether_addr *mc_addr_set,
1909                            int mc_addr_num,
1910                            struct rte_ether_addr *reserved_addr_list,
1911                            int *reserved_addr_num,
1912                            struct rte_ether_addr *add_addr_list,
1913                            int *add_addr_num,
1914                            struct rte_ether_addr *rm_addr_list,
1915                            int *rm_addr_num)
1916 {
1917         struct rte_ether_addr *addr;
1918         int current_addr_num;
1919         int reserved_num = 0;
1920         int add_num = 0;
1921         int rm_num = 0;
1922         int num;
1923         int i;
1924         int j;
1925         bool same_addr;
1926
1927         /* Calculate the mc mac address list that should be removed */
1928         current_addr_num = hw->mc_addrs_num;
1929         for (i = 0; i < current_addr_num; i++) {
1930                 addr = &hw->mc_addrs[i];
1931                 same_addr = false;
1932                 for (j = 0; j < mc_addr_num; j++) {
1933                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1934                                 same_addr = true;
1935                                 break;
1936                         }
1937                 }
1938
1939                 if (!same_addr) {
1940                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1941                         rm_num++;
1942                 } else {
1943                         rte_ether_addr_copy(addr,
1944                                             &reserved_addr_list[reserved_num]);
1945                         reserved_num++;
1946                 }
1947         }
1948
1949         /* Calculate the mc mac address list that should be added */
1950         for (i = 0; i < mc_addr_num; i++) {
1951                 addr = &mc_addr_set[i];
1952                 same_addr = false;
1953                 for (j = 0; j < current_addr_num; j++) {
1954                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1955                                 same_addr = true;
1956                                 break;
1957                         }
1958                 }
1959
1960                 if (!same_addr) {
1961                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1962                         add_num++;
1963                 }
1964         }
1965
1966         /* Reorder the mc mac address list maintained by driver */
1967         for (i = 0; i < reserved_num; i++)
1968                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1969
1970         for (i = 0; i < rm_num; i++) {
1971                 num = reserved_num + i;
1972                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1973         }
1974
1975         *reserved_addr_num = reserved_num;
1976         *add_addr_num = add_num;
1977         *rm_addr_num = rm_num;
1978 }
1979
1980 static int
1981 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1982                           struct rte_ether_addr *mc_addr_set,
1983                           uint32_t nb_mc_addr)
1984 {
1985         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1986         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1987         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1988         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1989         struct rte_ether_addr *addr;
1990         int reserved_addr_num;
1991         int add_addr_num;
1992         int rm_addr_num;
1993         int mc_addr_num;
1994         int num;
1995         int ret;
1996         int i;
1997
1998         /* Check if input parameters are valid */
1999         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
2000         if (ret)
2001                 return ret;
2002
2003         rte_spinlock_lock(&hw->lock);
2004
2005         /*
2006          * Calculate the mc mac address lists those should be removed and be
2007          * added, Reorder the mc mac address list maintained by driver.
2008          */
2009         mc_addr_num = (int)nb_mc_addr;
2010         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
2011                                    reserved_addr_list, &reserved_addr_num,
2012                                    add_addr_list, &add_addr_num,
2013                                    rm_addr_list, &rm_addr_num);
2014
2015         /* Remove mc mac addresses */
2016         for (i = 0; i < rm_addr_num; i++) {
2017                 num = rm_addr_num - i - 1;
2018                 addr = &rm_addr_list[num];
2019                 ret = hns3_remove_mc_addr(hw, addr);
2020                 if (ret) {
2021                         rte_spinlock_unlock(&hw->lock);
2022                         return ret;
2023                 }
2024                 hw->mc_addrs_num--;
2025         }
2026
2027         /* Add mc mac addresses */
2028         for (i = 0; i < add_addr_num; i++) {
2029                 addr = &add_addr_list[i];
2030                 ret = hns3_add_mc_addr(hw, addr);
2031                 if (ret) {
2032                         rte_spinlock_unlock(&hw->lock);
2033                         return ret;
2034                 }
2035
2036                 num = reserved_addr_num + i;
2037                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
2038                 hw->mc_addrs_num++;
2039         }
2040         rte_spinlock_unlock(&hw->lock);
2041
2042         return 0;
2043 }
2044
2045 static int
2046 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
2047 {
2048         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2049         struct hns3_hw *hw = &hns->hw;
2050         struct rte_ether_addr *addr;
2051         int err = 0;
2052         int ret;
2053         int i;
2054
2055         for (i = 0; i < hw->mc_addrs_num; i++) {
2056                 addr = &hw->mc_addrs[i];
2057                 if (!rte_is_multicast_ether_addr(addr))
2058                         continue;
2059                 if (del)
2060                         ret = hns3_remove_mc_addr(hw, addr);
2061                 else
2062                         ret = hns3_add_mc_addr(hw, addr);
2063                 if (ret) {
2064                         err = ret;
2065                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2066                                               addr);
2067                         hns3_dbg(hw, "%s mc mac addr: %s failed",
2068                                  del ? "Remove" : "Restore", mac_str);
2069                 }
2070         }
2071         return err;
2072 }
2073
2074 static int
2075 hns3_check_mq_mode(struct rte_eth_dev *dev)
2076 {
2077         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
2078         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
2079         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2081         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
2082         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
2083         uint8_t num_tc;
2084         int max_tc = 0;
2085         int i;
2086
2087         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2088         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2089
2090         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2091                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
2092                          "rx_mq_mode = %d", rx_mq_mode);
2093                 return -EINVAL;
2094         }
2095
2096         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
2097             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2098                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
2099                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
2100                          rx_mq_mode, tx_mq_mode);
2101                 return -EINVAL;
2102         }
2103
2104         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
2105                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
2106                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
2107                                  dcb_rx_conf->nb_tcs, pf->tc_max);
2108                         return -EINVAL;
2109                 }
2110
2111                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
2112                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
2113                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
2114                                  "nb_tcs(%d) != %d or %d in rx direction.",
2115                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
2116                         return -EINVAL;
2117                 }
2118
2119                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
2120                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
2121                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
2122                         return -EINVAL;
2123                 }
2124
2125                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
2126                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
2127                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
2128                                          "is not equal to one in tx direction.",
2129                                          i, dcb_rx_conf->dcb_tc[i]);
2130                                 return -EINVAL;
2131                         }
2132                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
2133                                 max_tc = dcb_rx_conf->dcb_tc[i];
2134                 }
2135
2136                 num_tc = max_tc + 1;
2137                 if (num_tc > dcb_rx_conf->nb_tcs) {
2138                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
2139                                  num_tc, dcb_rx_conf->nb_tcs);
2140                         return -EINVAL;
2141                 }
2142         }
2143
2144         return 0;
2145 }
2146
2147 static int
2148 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2149 {
2150         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151
2152         if (!hns3_dev_dcb_supported(hw)) {
2153                 hns3_err(hw, "this port does not support dcb configurations.");
2154                 return -EOPNOTSUPP;
2155         }
2156
2157         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2158                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2159                 return -EOPNOTSUPP;
2160         }
2161
2162         /* Check multiple queue mode */
2163         return hns3_check_mq_mode(dev);
2164 }
2165
2166 static int
2167 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2168                            enum hns3_ring_type queue_type, uint16_t queue_id)
2169 {
2170         struct hns3_cmd_desc desc;
2171         struct hns3_ctrl_vector_chain_cmd *req =
2172                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2173         enum hns3_cmd_status status;
2174         enum hns3_opcode_type op;
2175         uint16_t tqp_type_and_id = 0;
2176         const char *op_str;
2177         uint16_t type;
2178         uint16_t gl;
2179
2180         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2181         hns3_cmd_setup_basic_desc(&desc, op, false);
2182         req->int_vector_id = vector_id;
2183
2184         if (queue_type == HNS3_RING_TYPE_RX)
2185                 gl = HNS3_RING_GL_RX;
2186         else
2187                 gl = HNS3_RING_GL_TX;
2188
2189         type = queue_type;
2190
2191         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2192                        type);
2193         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2194         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2195                        gl);
2196         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2197         req->int_cause_num = 1;
2198         op_str = mmap ? "Map" : "Unmap";
2199         status = hns3_cmd_send(hw, &desc, 1);
2200         if (status) {
2201                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2202                          op_str, queue_id, req->int_vector_id, status);
2203                 return status;
2204         }
2205
2206         return 0;
2207 }
2208
2209 static int
2210 hns3_init_ring_with_vector(struct hns3_hw *hw)
2211 {
2212         uint8_t vec;
2213         int ret;
2214         int i;
2215
2216         /*
2217          * In hns3 network engine, vector 0 is always the misc interrupt of this
2218          * function, vector 1~N can be used respectively for the queues of the
2219          * function. Tx and Rx queues with the same number share the interrupt
2220          * vector. In the initialization clearing the all hardware mapping
2221          * relationship configurations between queues and interrupt vectors is
2222          * needed, so some error caused by the residual configurations, such as
2223          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2224          * constraints in hns3 hardware engine, we have to implement clearing
2225          * the mapping relationship configurations by binding all queues to the
2226          * last interrupt vector and reserving the last interrupt vector. This
2227          * method results in a decrease of the maximum queues when upper
2228          * applications call the rte_eth_dev_configure API function to enable
2229          * Rx interrupt.
2230          */
2231         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2232         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2233         for (i = 0; i < hw->intr_tqps_num; i++) {
2234                 /*
2235                  * Set gap limiter and rate limiter configuration of queue's
2236                  * interrupt.
2237                  */
2238                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2239                                        HNS3_TQP_INTR_GL_DEFAULT);
2240                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2241                                        HNS3_TQP_INTR_GL_DEFAULT);
2242                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2243
2244                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2245                                                  HNS3_RING_TYPE_TX, i);
2246                 if (ret) {
2247                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2248                                           "vector: %d, ret=%d", i, vec, ret);
2249                         return ret;
2250                 }
2251
2252                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2253                                                  HNS3_RING_TYPE_RX, i);
2254                 if (ret) {
2255                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2256                                           "vector: %d, ret=%d", i, vec, ret);
2257                         return ret;
2258                 }
2259         }
2260
2261         return 0;
2262 }
2263
2264 static int
2265 hns3_dev_configure(struct rte_eth_dev *dev)
2266 {
2267         struct hns3_adapter *hns = dev->data->dev_private;
2268         struct rte_eth_conf *conf = &dev->data->dev_conf;
2269         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2270         struct hns3_hw *hw = &hns->hw;
2271         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2272         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2273         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2274         struct rte_eth_rss_conf rss_conf;
2275         uint16_t mtu;
2276         int ret;
2277
2278         /*
2279          * Hardware does not support individually enable/disable/reset the Tx or
2280          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2281          * and Rx queues at the same time. When the numbers of Tx queues
2282          * allocated by upper applications are not equal to the numbers of Rx
2283          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2284          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2285          * these fake queues are imperceptible, and can not be used by upper
2286          * applications.
2287          */
2288         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2289         if (ret) {
2290                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2291                 return ret;
2292         }
2293
2294         hw->adapter_state = HNS3_NIC_CONFIGURING;
2295         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2296                 hns3_err(hw, "setting link speed/duplex not supported");
2297                 ret = -EINVAL;
2298                 goto cfg_err;
2299         }
2300
2301         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2302                 ret = hns3_check_dcb_cfg(dev);
2303                 if (ret)
2304                         goto cfg_err;
2305         }
2306
2307         /* When RSS is not configured, redirect the packet queue 0 */
2308         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2309                 rss_conf = conf->rx_adv_conf.rss_conf;
2310                 if (rss_conf.rss_key == NULL) {
2311                         rss_conf.rss_key = rss_cfg->key;
2312                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2313                 }
2314
2315                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2316                 if (ret)
2317                         goto cfg_err;
2318         }
2319
2320         /*
2321          * If jumbo frames are enabled, MTU needs to be refreshed
2322          * according to the maximum RX packet length.
2323          */
2324         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2325                 /*
2326                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2327                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2328                  * can safely assign to "uint16_t" type variable.
2329                  */
2330                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2331                 ret = hns3_dev_mtu_set(dev, mtu);
2332                 if (ret)
2333                         goto cfg_err;
2334                 dev->data->mtu = mtu;
2335         }
2336
2337         ret = hns3_dev_configure_vlan(dev);
2338         if (ret)
2339                 goto cfg_err;
2340
2341         hw->adapter_state = HNS3_NIC_CONFIGURED;
2342
2343         return 0;
2344
2345 cfg_err:
2346         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2347         hw->adapter_state = HNS3_NIC_INITIALIZED;
2348
2349         return ret;
2350 }
2351
2352 static int
2353 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2354 {
2355         struct hns3_config_max_frm_size_cmd *req;
2356         struct hns3_cmd_desc desc;
2357
2358         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2359
2360         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2361         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2362         req->min_frm_size = RTE_ETHER_MIN_LEN;
2363
2364         return hns3_cmd_send(hw, &desc, 1);
2365 }
2366
2367 static int
2368 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2369 {
2370         int ret;
2371
2372         ret = hns3_set_mac_mtu(hw, mps);
2373         if (ret) {
2374                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2375                 return ret;
2376         }
2377
2378         ret = hns3_buffer_alloc(hw);
2379         if (ret)
2380                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2381
2382         return ret;
2383 }
2384
2385 static int
2386 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2387 {
2388         struct hns3_adapter *hns = dev->data->dev_private;
2389         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2390         struct hns3_hw *hw = &hns->hw;
2391         bool is_jumbo_frame;
2392         int ret;
2393
2394         if (dev->data->dev_started) {
2395                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2396                          "before configuration", dev->data->port_id);
2397                 return -EBUSY;
2398         }
2399
2400         rte_spinlock_lock(&hw->lock);
2401         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2402         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2403
2404         /*
2405          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2406          * assign to "uint16_t" type variable.
2407          */
2408         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2409         if (ret) {
2410                 rte_spinlock_unlock(&hw->lock);
2411                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2412                          dev->data->port_id, mtu, ret);
2413                 return ret;
2414         }
2415         hns->pf.mps = (uint16_t)frame_size;
2416         if (is_jumbo_frame)
2417                 dev->data->dev_conf.rxmode.offloads |=
2418                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2419         else
2420                 dev->data->dev_conf.rxmode.offloads &=
2421                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2422         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2423         rte_spinlock_unlock(&hw->lock);
2424
2425         return 0;
2426 }
2427
2428 static int
2429 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2430 {
2431         struct hns3_adapter *hns = eth_dev->data->dev_private;
2432         struct hns3_hw *hw = &hns->hw;
2433         uint16_t queue_num = hw->tqps_num;
2434
2435         /*
2436          * In interrupt mode, 'max_rx_queues' is set based on the number of
2437          * MSI-X interrupt resources of the hardware.
2438          */
2439         if (hw->data->dev_conf.intr_conf.rxq == 1)
2440                 queue_num = hw->intr_tqps_num;
2441
2442         info->max_rx_queues = queue_num;
2443         info->max_tx_queues = hw->tqps_num;
2444         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2445         info->min_rx_bufsize = hw->rx_buf_len;
2446         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2447         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2448         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2449                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2450                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2451                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2452                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2453                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2454                                  DEV_RX_OFFLOAD_KEEP_CRC |
2455                                  DEV_RX_OFFLOAD_SCATTER |
2456                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2457                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2458                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2459                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2460                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
2461                                  DEV_RX_OFFLOAD_RSS_HASH);
2462         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2463         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2464                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2465                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2466                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2467                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2468                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2469                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2470                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2471                                  DEV_TX_OFFLOAD_TCP_TSO |
2472                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2473                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2474                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2475                                  info->tx_queue_offload_capa);
2476
2477         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2478                 .nb_max = HNS3_MAX_RING_DESC,
2479                 .nb_min = HNS3_MIN_RING_DESC,
2480                 .nb_align = HNS3_ALIGN_RING_DESC,
2481         };
2482
2483         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2484                 .nb_max = HNS3_MAX_RING_DESC,
2485                 .nb_min = HNS3_MIN_RING_DESC,
2486                 .nb_align = HNS3_ALIGN_RING_DESC,
2487         };
2488
2489         info->vmdq_queue_num = 0;
2490
2491         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2492         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2493         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2494
2495         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2496         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2497         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2498         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2499         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2500         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2501
2502         return 0;
2503 }
2504
2505 static int
2506 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2507                     size_t fw_size)
2508 {
2509         struct hns3_adapter *hns = eth_dev->data->dev_private;
2510         struct hns3_hw *hw = &hns->hw;
2511         uint32_t version = hw->fw_version;
2512         int ret;
2513
2514         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2515                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2516                                       HNS3_FW_VERSION_BYTE3_S),
2517                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2518                                       HNS3_FW_VERSION_BYTE2_S),
2519                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2520                                       HNS3_FW_VERSION_BYTE1_S),
2521                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2522                                       HNS3_FW_VERSION_BYTE0_S));
2523         ret += 1; /* add the size of '\0' */
2524         if (fw_size < (uint32_t)ret)
2525                 return ret;
2526         else
2527                 return 0;
2528 }
2529
2530 static int
2531 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2532                      __rte_unused int wait_to_complete)
2533 {
2534         struct hns3_adapter *hns = eth_dev->data->dev_private;
2535         struct hns3_hw *hw = &hns->hw;
2536         struct hns3_mac *mac = &hw->mac;
2537         struct rte_eth_link new_link;
2538
2539         if (!hns3_is_reset_pending(hns)) {
2540                 hns3_update_speed_duplex(eth_dev);
2541                 hns3_update_link_status(hw);
2542         }
2543
2544         memset(&new_link, 0, sizeof(new_link));
2545         switch (mac->link_speed) {
2546         case ETH_SPEED_NUM_10M:
2547         case ETH_SPEED_NUM_100M:
2548         case ETH_SPEED_NUM_1G:
2549         case ETH_SPEED_NUM_10G:
2550         case ETH_SPEED_NUM_25G:
2551         case ETH_SPEED_NUM_40G:
2552         case ETH_SPEED_NUM_50G:
2553         case ETH_SPEED_NUM_100G:
2554                 new_link.link_speed = mac->link_speed;
2555                 break;
2556         default:
2557                 new_link.link_speed = ETH_SPEED_NUM_100M;
2558                 break;
2559         }
2560
2561         new_link.link_duplex = mac->link_duplex;
2562         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2563         new_link.link_autoneg =
2564             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2565
2566         return rte_eth_linkstatus_set(eth_dev, &new_link);
2567 }
2568
2569 static int
2570 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2571 {
2572         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2573         struct hns3_pf *pf = &hns->pf;
2574
2575         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2576                 return -EINVAL;
2577
2578         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2579
2580         return 0;
2581 }
2582
2583 static int
2584 hns3_query_function_status(struct hns3_hw *hw)
2585 {
2586 #define HNS3_QUERY_MAX_CNT              10
2587 #define HNS3_QUERY_SLEEP_MSCOEND        1
2588         struct hns3_func_status_cmd *req;
2589         struct hns3_cmd_desc desc;
2590         int timeout = 0;
2591         int ret;
2592
2593         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2594         req = (struct hns3_func_status_cmd *)desc.data;
2595
2596         do {
2597                 ret = hns3_cmd_send(hw, &desc, 1);
2598                 if (ret) {
2599                         PMD_INIT_LOG(ERR, "query function status failed %d",
2600                                      ret);
2601                         return ret;
2602                 }
2603
2604                 /* Check pf reset is done */
2605                 if (req->pf_state)
2606                         break;
2607
2608                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2609         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2610
2611         return hns3_parse_func_status(hw, req);
2612 }
2613
2614 static int
2615 hns3_query_pf_resource(struct hns3_hw *hw)
2616 {
2617         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2618         struct hns3_pf *pf = &hns->pf;
2619         struct hns3_pf_res_cmd *req;
2620         struct hns3_cmd_desc desc;
2621         uint16_t num_msi;
2622         int ret;
2623
2624         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2625         ret = hns3_cmd_send(hw, &desc, 1);
2626         if (ret) {
2627                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2628                 return ret;
2629         }
2630
2631         req = (struct hns3_pf_res_cmd *)desc.data;
2632         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2633         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2634         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2635         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2636
2637         if (req->tx_buf_size)
2638                 pf->tx_buf_size =
2639                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2640         else
2641                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2642
2643         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2644
2645         if (req->dv_buf_size)
2646                 pf->dv_buf_size =
2647                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2648         else
2649                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2650
2651         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2652
2653         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2654                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2655         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2656
2657         return 0;
2658 }
2659
2660 static void
2661 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2662 {
2663         struct hns3_cfg_param_cmd *req;
2664         uint64_t mac_addr_tmp_high;
2665         uint64_t mac_addr_tmp;
2666         uint32_t i;
2667
2668         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2669
2670         /* get the configuration */
2671         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2672                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2673         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2674                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2675         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2676                                            HNS3_CFG_TQP_DESC_N_M,
2677                                            HNS3_CFG_TQP_DESC_N_S);
2678
2679         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2680                                        HNS3_CFG_PHY_ADDR_M,
2681                                        HNS3_CFG_PHY_ADDR_S);
2682         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2683                                          HNS3_CFG_MEDIA_TP_M,
2684                                          HNS3_CFG_MEDIA_TP_S);
2685         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2686                                          HNS3_CFG_RX_BUF_LEN_M,
2687                                          HNS3_CFG_RX_BUF_LEN_S);
2688         /* get mac address */
2689         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2690         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2691                                            HNS3_CFG_MAC_ADDR_H_M,
2692                                            HNS3_CFG_MAC_ADDR_H_S);
2693
2694         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2695
2696         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2697                                             HNS3_CFG_DEFAULT_SPEED_M,
2698                                             HNS3_CFG_DEFAULT_SPEED_S);
2699         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2700                                            HNS3_CFG_RSS_SIZE_M,
2701                                            HNS3_CFG_RSS_SIZE_S);
2702
2703         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2704                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2705
2706         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2707         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2708
2709         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2710                                             HNS3_CFG_SPEED_ABILITY_M,
2711                                             HNS3_CFG_SPEED_ABILITY_S);
2712         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2713                                         HNS3_CFG_UMV_TBL_SPACE_M,
2714                                         HNS3_CFG_UMV_TBL_SPACE_S);
2715         if (!cfg->umv_space)
2716                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2717 }
2718
2719 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2720  * @hw: pointer to struct hns3_hw
2721  * @hcfg: the config structure to be getted
2722  */
2723 static int
2724 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2725 {
2726         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2727         struct hns3_cfg_param_cmd *req;
2728         uint32_t offset;
2729         uint32_t i;
2730         int ret;
2731
2732         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2733                 offset = 0;
2734                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2735                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2736                                           true);
2737                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2738                                i * HNS3_CFG_RD_LEN_BYTES);
2739                 /* Len should be divided by 4 when send to hardware */
2740                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2741                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2742                 req->offset = rte_cpu_to_le_32(offset);
2743         }
2744
2745         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2746         if (ret) {
2747                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2748                 return ret;
2749         }
2750
2751         hns3_parse_cfg(hcfg, desc);
2752
2753         return 0;
2754 }
2755
2756 static int
2757 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2758 {
2759         switch (speed_cmd) {
2760         case HNS3_CFG_SPEED_10M:
2761                 *speed = ETH_SPEED_NUM_10M;
2762                 break;
2763         case HNS3_CFG_SPEED_100M:
2764                 *speed = ETH_SPEED_NUM_100M;
2765                 break;
2766         case HNS3_CFG_SPEED_1G:
2767                 *speed = ETH_SPEED_NUM_1G;
2768                 break;
2769         case HNS3_CFG_SPEED_10G:
2770                 *speed = ETH_SPEED_NUM_10G;
2771                 break;
2772         case HNS3_CFG_SPEED_25G:
2773                 *speed = ETH_SPEED_NUM_25G;
2774                 break;
2775         case HNS3_CFG_SPEED_40G:
2776                 *speed = ETH_SPEED_NUM_40G;
2777                 break;
2778         case HNS3_CFG_SPEED_50G:
2779                 *speed = ETH_SPEED_NUM_50G;
2780                 break;
2781         case HNS3_CFG_SPEED_100G:
2782                 *speed = ETH_SPEED_NUM_100G;
2783                 break;
2784         default:
2785                 return -EINVAL;
2786         }
2787
2788         return 0;
2789 }
2790
2791 static int
2792 hns3_get_board_configuration(struct hns3_hw *hw)
2793 {
2794         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2795         struct hns3_pf *pf = &hns->pf;
2796         struct hns3_cfg cfg;
2797         int ret;
2798
2799         ret = hns3_get_board_cfg(hw, &cfg);
2800         if (ret) {
2801                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2802                 return ret;
2803         }
2804
2805         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2806                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2807                 return -EOPNOTSUPP;
2808         }
2809
2810         hw->mac.media_type = cfg.media_type;
2811         hw->rss_size_max = cfg.rss_size_max;
2812         hw->rss_dis_flag = false;
2813         hw->rx_buf_len = cfg.rx_buf_len;
2814         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2815         hw->mac.phy_addr = cfg.phy_addr;
2816         hw->mac.default_addr_setted = false;
2817         hw->num_tx_desc = cfg.tqp_desc_num;
2818         hw->num_rx_desc = cfg.tqp_desc_num;
2819         hw->dcb_info.num_pg = 1;
2820         hw->dcb_info.hw_pfc_map = 0;
2821
2822         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2823         if (ret) {
2824                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2825                              cfg.default_speed, ret);
2826                 return ret;
2827         }
2828
2829         pf->tc_max = cfg.tc_num;
2830         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2831                 PMD_INIT_LOG(WARNING,
2832                              "Get TC num(%u) from flash, set TC num to 1",
2833                              pf->tc_max);
2834                 pf->tc_max = 1;
2835         }
2836
2837         /* Dev does not support DCB */
2838         if (!hns3_dev_dcb_supported(hw)) {
2839                 pf->tc_max = 1;
2840                 pf->pfc_max = 0;
2841         } else
2842                 pf->pfc_max = pf->tc_max;
2843
2844         hw->dcb_info.num_tc = 1;
2845         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2846                                      hw->tqps_num / hw->dcb_info.num_tc);
2847         hns3_set_bit(hw->hw_tc_map, 0, 1);
2848         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2849
2850         pf->wanted_umv_size = cfg.umv_space;
2851
2852         return ret;
2853 }
2854
2855 static int
2856 hns3_get_configuration(struct hns3_hw *hw)
2857 {
2858         int ret;
2859
2860         ret = hns3_query_function_status(hw);
2861         if (ret) {
2862                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2863                 return ret;
2864         }
2865
2866         /* Get pf resource */
2867         ret = hns3_query_pf_resource(hw);
2868         if (ret) {
2869                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2870                 return ret;
2871         }
2872
2873         ret = hns3_get_board_configuration(hw);
2874         if (ret)
2875                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2876
2877         return ret;
2878 }
2879
2880 static int
2881 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2882                       uint16_t tqp_vid, bool is_pf)
2883 {
2884         struct hns3_tqp_map_cmd *req;
2885         struct hns3_cmd_desc desc;
2886         int ret;
2887
2888         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2889
2890         req = (struct hns3_tqp_map_cmd *)desc.data;
2891         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2892         req->tqp_vf = func_id;
2893         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2894         if (!is_pf)
2895                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2896         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2897
2898         ret = hns3_cmd_send(hw, &desc, 1);
2899         if (ret)
2900                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2901
2902         return ret;
2903 }
2904
2905 static int
2906 hns3_map_tqp(struct hns3_hw *hw)
2907 {
2908         uint16_t tqps_num = hw->total_tqps_num;
2909         uint16_t func_id;
2910         uint16_t tqp_id;
2911         bool is_pf;
2912         int num;
2913         int ret;
2914         int i;
2915
2916         /*
2917          * In current version VF is not supported when PF is driven by DPDK
2918          * driver, so we allocate tqps to PF as much as possible.
2919          */
2920         tqp_id = 0;
2921         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2922         for (func_id = 0; func_id < num; func_id++) {
2923                 is_pf = func_id == 0 ? true : false;
2924                 for (i = 0;
2925                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2926                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2927                                                     is_pf);
2928                         if (ret)
2929                                 return ret;
2930                 }
2931         }
2932
2933         return 0;
2934 }
2935
2936 static int
2937 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2938 {
2939         struct hns3_config_mac_speed_dup_cmd *req;
2940         struct hns3_cmd_desc desc;
2941         int ret;
2942
2943         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2944
2945         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2946
2947         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2948
2949         switch (speed) {
2950         case ETH_SPEED_NUM_10M:
2951                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2952                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2953                 break;
2954         case ETH_SPEED_NUM_100M:
2955                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2956                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2957                 break;
2958         case ETH_SPEED_NUM_1G:
2959                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2960                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2961                 break;
2962         case ETH_SPEED_NUM_10G:
2963                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2964                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2965                 break;
2966         case ETH_SPEED_NUM_25G:
2967                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2968                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2969                 break;
2970         case ETH_SPEED_NUM_40G:
2971                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2972                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2973                 break;
2974         case ETH_SPEED_NUM_50G:
2975                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2976                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2977                 break;
2978         case ETH_SPEED_NUM_100G:
2979                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2980                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2981                 break;
2982         default:
2983                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2984                 return -EINVAL;
2985         }
2986
2987         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2988
2989         ret = hns3_cmd_send(hw, &desc, 1);
2990         if (ret)
2991                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2992
2993         return ret;
2994 }
2995
2996 static int
2997 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2998 {
2999         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3000         struct hns3_pf *pf = &hns->pf;
3001         struct hns3_priv_buf *priv;
3002         uint32_t i, total_size;
3003
3004         total_size = pf->pkt_buf_size;
3005
3006         /* alloc tx buffer for all enabled tc */
3007         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3008                 priv = &buf_alloc->priv_buf[i];
3009
3010                 if (hw->hw_tc_map & BIT(i)) {
3011                         if (total_size < pf->tx_buf_size)
3012                                 return -ENOMEM;
3013
3014                         priv->tx_buf_size = pf->tx_buf_size;
3015                 } else
3016                         priv->tx_buf_size = 0;
3017
3018                 total_size -= priv->tx_buf_size;
3019         }
3020
3021         return 0;
3022 }
3023
3024 static int
3025 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3026 {
3027 /* TX buffer size is unit by 128 byte */
3028 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
3029 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
3030         struct hns3_tx_buff_alloc_cmd *req;
3031         struct hns3_cmd_desc desc;
3032         uint32_t buf_size;
3033         uint32_t i;
3034         int ret;
3035
3036         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
3037
3038         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
3039         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3040                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
3041
3042                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
3043                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
3044                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
3045         }
3046
3047         ret = hns3_cmd_send(hw, &desc, 1);
3048         if (ret)
3049                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
3050
3051         return ret;
3052 }
3053
3054 static int
3055 hns3_get_tc_num(struct hns3_hw *hw)
3056 {
3057         int cnt = 0;
3058         uint8_t i;
3059
3060         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3061                 if (hw->hw_tc_map & BIT(i))
3062                         cnt++;
3063         return cnt;
3064 }
3065
3066 static uint32_t
3067 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3068 {
3069         struct hns3_priv_buf *priv;
3070         uint32_t rx_priv = 0;
3071         int i;
3072
3073         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3074                 priv = &buf_alloc->priv_buf[i];
3075                 if (priv->enable)
3076                         rx_priv += priv->buf_size;
3077         }
3078         return rx_priv;
3079 }
3080
3081 static uint32_t
3082 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
3083 {
3084         uint32_t total_tx_size = 0;
3085         uint32_t i;
3086
3087         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
3088                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
3089
3090         return total_tx_size;
3091 }
3092
3093 /* Get the number of pfc enabled TCs, which have private buffer */
3094 static int
3095 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3096 {
3097         struct hns3_priv_buf *priv;
3098         int cnt = 0;
3099         uint8_t i;
3100
3101         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3102                 priv = &buf_alloc->priv_buf[i];
3103                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3104                         cnt++;
3105         }
3106
3107         return cnt;
3108 }
3109
3110 /* Get the number of pfc disabled TCs, which have private buffer */
3111 static int
3112 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
3113                          struct hns3_pkt_buf_alloc *buf_alloc)
3114 {
3115         struct hns3_priv_buf *priv;
3116         int cnt = 0;
3117         uint8_t i;
3118
3119         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3120                 priv = &buf_alloc->priv_buf[i];
3121                 if (hw->hw_tc_map & BIT(i) &&
3122                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
3123                         cnt++;
3124         }
3125
3126         return cnt;
3127 }
3128
3129 static bool
3130 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
3131                   uint32_t rx_all)
3132 {
3133         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
3134         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3135         struct hns3_pf *pf = &hns->pf;
3136         uint32_t shared_buf, aligned_mps;
3137         uint32_t rx_priv;
3138         uint8_t tc_num;
3139         uint8_t i;
3140
3141         tc_num = hns3_get_tc_num(hw);
3142         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3143
3144         if (hns3_dev_dcb_supported(hw))
3145                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
3146                                         pf->dv_buf_size;
3147         else
3148                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3149                                         + pf->dv_buf_size;
3150
3151         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3152         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3153                              HNS3_BUF_SIZE_UNIT);
3154
3155         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3156         if (rx_all < rx_priv + shared_std)
3157                 return false;
3158
3159         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3160         buf_alloc->s_buf.buf_size = shared_buf;
3161         if (hns3_dev_dcb_supported(hw)) {
3162                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3163                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3164                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3165                                   HNS3_BUF_SIZE_UNIT);
3166         } else {
3167                 buf_alloc->s_buf.self.high =
3168                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3169                 buf_alloc->s_buf.self.low = aligned_mps;
3170         }
3171
3172         if (hns3_dev_dcb_supported(hw)) {
3173                 hi_thrd = shared_buf - pf->dv_buf_size;
3174
3175                 if (tc_num <= NEED_RESERVE_TC_NUM)
3176                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3177                                         / BUF_MAX_PERCENT;
3178
3179                 if (tc_num)
3180                         hi_thrd = hi_thrd / tc_num;
3181
3182                 hi_thrd = max_t(uint32_t, hi_thrd,
3183                                 HNS3_BUF_MUL_BY * aligned_mps);
3184                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3185                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3186         } else {
3187                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3188                 lo_thrd = aligned_mps;
3189         }
3190
3191         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3192                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3193                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3194         }
3195
3196         return true;
3197 }
3198
3199 static bool
3200 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3201                      struct hns3_pkt_buf_alloc *buf_alloc)
3202 {
3203         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3204         struct hns3_pf *pf = &hns->pf;
3205         struct hns3_priv_buf *priv;
3206         uint32_t aligned_mps;
3207         uint32_t rx_all;
3208         uint8_t i;
3209
3210         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3211         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3212
3213         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3214                 priv = &buf_alloc->priv_buf[i];
3215
3216                 priv->enable = 0;
3217                 priv->wl.low = 0;
3218                 priv->wl.high = 0;
3219                 priv->buf_size = 0;
3220
3221                 if (!(hw->hw_tc_map & BIT(i)))
3222                         continue;
3223
3224                 priv->enable = 1;
3225                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3226                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3227                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3228                                                 HNS3_BUF_SIZE_UNIT);
3229                 } else {
3230                         priv->wl.low = 0;
3231                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3232                                         aligned_mps;
3233                 }
3234
3235                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3236         }
3237
3238         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3239 }
3240
3241 static bool
3242 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3243                              struct hns3_pkt_buf_alloc *buf_alloc)
3244 {
3245         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3246         struct hns3_pf *pf = &hns->pf;
3247         struct hns3_priv_buf *priv;
3248         int no_pfc_priv_num;
3249         uint32_t rx_all;
3250         uint8_t mask;
3251         int i;
3252
3253         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3254         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3255
3256         /* let the last to be cleared first */
3257         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3258                 priv = &buf_alloc->priv_buf[i];
3259                 mask = BIT((uint8_t)i);
3260
3261                 if (hw->hw_tc_map & mask &&
3262                     !(hw->dcb_info.hw_pfc_map & mask)) {
3263                         /* Clear the no pfc TC private buffer */
3264                         priv->wl.low = 0;
3265                         priv->wl.high = 0;
3266                         priv->buf_size = 0;
3267                         priv->enable = 0;
3268                         no_pfc_priv_num--;
3269                 }
3270
3271                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3272                     no_pfc_priv_num == 0)
3273                         break;
3274         }
3275
3276         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3277 }
3278
3279 static bool
3280 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3281                            struct hns3_pkt_buf_alloc *buf_alloc)
3282 {
3283         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3284         struct hns3_pf *pf = &hns->pf;
3285         struct hns3_priv_buf *priv;
3286         uint32_t rx_all;
3287         int pfc_priv_num;
3288         uint8_t mask;
3289         int i;
3290
3291         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3292         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3293
3294         /* let the last to be cleared first */
3295         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3296                 priv = &buf_alloc->priv_buf[i];
3297                 mask = BIT((uint8_t)i);
3298
3299                 if (hw->hw_tc_map & mask &&
3300                     hw->dcb_info.hw_pfc_map & mask) {
3301                         /* Reduce the number of pfc TC with private buffer */
3302                         priv->wl.low = 0;
3303                         priv->enable = 0;
3304                         priv->wl.high = 0;
3305                         priv->buf_size = 0;
3306                         pfc_priv_num--;
3307                 }
3308                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3309                     pfc_priv_num == 0)
3310                         break;
3311         }
3312
3313         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3314 }
3315
3316 static bool
3317 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3318                           struct hns3_pkt_buf_alloc *buf_alloc)
3319 {
3320 #define COMPENSATE_BUFFER       0x3C00
3321 #define COMPENSATE_HALF_MPS_NUM 5
3322 #define PRIV_WL_GAP             0x1800
3323         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3324         struct hns3_pf *pf = &hns->pf;
3325         uint32_t tc_num = hns3_get_tc_num(hw);
3326         uint32_t half_mps = pf->mps >> 1;
3327         struct hns3_priv_buf *priv;
3328         uint32_t min_rx_priv;
3329         uint32_t rx_priv;
3330         uint8_t i;
3331
3332         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3333         if (tc_num)
3334                 rx_priv = rx_priv / tc_num;
3335
3336         if (tc_num <= NEED_RESERVE_TC_NUM)
3337                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3338
3339         /*
3340          * Minimum value of private buffer in rx direction (min_rx_priv) is
3341          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3342          * buffer if rx_priv is greater than min_rx_priv.
3343          */
3344         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3345                         COMPENSATE_HALF_MPS_NUM * half_mps;
3346         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3347         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3348
3349         if (rx_priv < min_rx_priv)
3350                 return false;
3351
3352         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3353                 priv = &buf_alloc->priv_buf[i];
3354
3355                 priv->enable = 0;
3356                 priv->wl.low = 0;
3357                 priv->wl.high = 0;
3358                 priv->buf_size = 0;
3359
3360                 if (!(hw->hw_tc_map & BIT(i)))
3361                         continue;
3362
3363                 priv->enable = 1;
3364                 priv->buf_size = rx_priv;
3365                 priv->wl.high = rx_priv - pf->dv_buf_size;
3366                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3367         }
3368
3369         buf_alloc->s_buf.buf_size = 0;
3370
3371         return true;
3372 }
3373
3374 /*
3375  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3376  * @hw: pointer to struct hns3_hw
3377  * @buf_alloc: pointer to buffer calculation data
3378  * @return: 0: calculate sucessful, negative: fail
3379  */
3380 static int
3381 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3382 {
3383         /* When DCB is not supported, rx private buffer is not allocated. */
3384         if (!hns3_dev_dcb_supported(hw)) {
3385                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3386                 struct hns3_pf *pf = &hns->pf;
3387                 uint32_t rx_all = pf->pkt_buf_size;
3388
3389                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3390                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3391                         return -ENOMEM;
3392
3393                 return 0;
3394         }
3395
3396         /*
3397          * Try to allocate privated packet buffer for all TCs without share
3398          * buffer.
3399          */
3400         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3401                 return 0;
3402
3403         /*
3404          * Try to allocate privated packet buffer for all TCs with share
3405          * buffer.
3406          */
3407         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3408                 return 0;
3409
3410         /*
3411          * For different application scenes, the enabled port number, TC number
3412          * and no_drop TC number are different. In order to obtain the better
3413          * performance, software could allocate the buffer size and configure
3414          * the waterline by tring to decrease the private buffer size according
3415          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3416          * enabled tc.
3417          */
3418         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3419                 return 0;
3420
3421         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3422                 return 0;
3423
3424         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3425                 return 0;
3426
3427         return -ENOMEM;
3428 }
3429
3430 static int
3431 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3432 {
3433         struct hns3_rx_priv_buff_cmd *req;
3434         struct hns3_cmd_desc desc;
3435         uint32_t buf_size;
3436         int ret;
3437         int i;
3438
3439         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3440         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3441
3442         /* Alloc private buffer TCs */
3443         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3444                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3445
3446                 req->buf_num[i] =
3447                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3448                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3449         }
3450
3451         buf_size = buf_alloc->s_buf.buf_size;
3452         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3453                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3454
3455         ret = hns3_cmd_send(hw, &desc, 1);
3456         if (ret)
3457                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3458
3459         return ret;
3460 }
3461
3462 static int
3463 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3464 {
3465 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3466         struct hns3_rx_priv_wl_buf *req;
3467         struct hns3_priv_buf *priv;
3468         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3469         int i, j;
3470         int ret;
3471
3472         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3473                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3474                                           false);
3475                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3476
3477                 /* The first descriptor set the NEXT bit to 1 */
3478                 if (i == 0)
3479                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3480                 else
3481                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3482
3483                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3484                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3485
3486                         priv = &buf_alloc->priv_buf[idx];
3487                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3488                                                         HNS3_BUF_UNIT_S);
3489                         req->tc_wl[j].high |=
3490                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3491                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3492                                                         HNS3_BUF_UNIT_S);
3493                         req->tc_wl[j].low |=
3494                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3495                 }
3496         }
3497
3498         /* Send 2 descriptor at one time */
3499         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3500         if (ret)
3501                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3502                              ret);
3503         return ret;
3504 }
3505
3506 static int
3507 hns3_common_thrd_config(struct hns3_hw *hw,
3508                         struct hns3_pkt_buf_alloc *buf_alloc)
3509 {
3510 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3511         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3512         struct hns3_rx_com_thrd *req;
3513         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3514         struct hns3_tc_thrd *tc;
3515         int tc_idx;
3516         int i, j;
3517         int ret;
3518
3519         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3520                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3521                                           false);
3522                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3523
3524                 /* The first descriptor set the NEXT bit to 1 */
3525                 if (i == 0)
3526                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3527                 else
3528                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3529
3530                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3531                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3532                         tc = &s_buf->tc_thrd[tc_idx];
3533
3534                         req->com_thrd[j].high =
3535                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3536                         req->com_thrd[j].high |=
3537                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3538                         req->com_thrd[j].low =
3539                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3540                         req->com_thrd[j].low |=
3541                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3542                 }
3543         }
3544
3545         /* Send 2 descriptors at one time */
3546         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3547         if (ret)
3548                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3549
3550         return ret;
3551 }
3552
3553 static int
3554 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3555 {
3556         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3557         struct hns3_rx_com_wl *req;
3558         struct hns3_cmd_desc desc;
3559         int ret;
3560
3561         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3562
3563         req = (struct hns3_rx_com_wl *)desc.data;
3564         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3565         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3566
3567         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3568         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3569
3570         ret = hns3_cmd_send(hw, &desc, 1);
3571         if (ret)
3572                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3573
3574         return ret;
3575 }
3576
3577 int
3578 hns3_buffer_alloc(struct hns3_hw *hw)
3579 {
3580         struct hns3_pkt_buf_alloc pkt_buf;
3581         int ret;
3582
3583         memset(&pkt_buf, 0, sizeof(pkt_buf));
3584         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3585         if (ret) {
3586                 PMD_INIT_LOG(ERR,
3587                              "could not calc tx buffer size for all TCs %d",
3588                              ret);
3589                 return ret;
3590         }
3591
3592         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3593         if (ret) {
3594                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3595                 return ret;
3596         }
3597
3598         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3599         if (ret) {
3600                 PMD_INIT_LOG(ERR,
3601                              "could not calc rx priv buffer size for all TCs %d",
3602                              ret);
3603                 return ret;
3604         }
3605
3606         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3607         if (ret) {
3608                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3609                 return ret;
3610         }
3611
3612         if (hns3_dev_dcb_supported(hw)) {
3613                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3614                 if (ret) {
3615                         PMD_INIT_LOG(ERR,
3616                                      "could not configure rx private waterline %d",
3617                                      ret);
3618                         return ret;
3619                 }
3620
3621                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3622                 if (ret) {
3623                         PMD_INIT_LOG(ERR,
3624                                      "could not configure common threshold %d",
3625                                      ret);
3626                         return ret;
3627                 }
3628         }
3629
3630         ret = hns3_common_wl_config(hw, &pkt_buf);
3631         if (ret)
3632                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3633                              ret);
3634
3635         return ret;
3636 }
3637
3638 static int
3639 hns3_mac_init(struct hns3_hw *hw)
3640 {
3641         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3642         struct hns3_mac *mac = &hw->mac;
3643         struct hns3_pf *pf = &hns->pf;
3644         int ret;
3645
3646         pf->support_sfp_query = true;
3647         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3648         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3649         if (ret) {
3650                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3651                 return ret;
3652         }
3653
3654         mac->link_status = ETH_LINK_DOWN;
3655
3656         return hns3_config_mtu(hw, pf->mps);
3657 }
3658
3659 static int
3660 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3661 {
3662 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3663 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3664 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3665 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3666         int return_status;
3667
3668         if (cmdq_resp) {
3669                 PMD_INIT_LOG(ERR,
3670                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3671                              cmdq_resp);
3672                 return -EIO;
3673         }
3674
3675         switch (resp_code) {
3676         case HNS3_ETHERTYPE_SUCCESS_ADD:
3677         case HNS3_ETHERTYPE_ALREADY_ADD:
3678                 return_status = 0;
3679                 break;
3680         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3681                 PMD_INIT_LOG(ERR,
3682                              "add mac ethertype failed for manager table overflow.");
3683                 return_status = -EIO;
3684                 break;
3685         case HNS3_ETHERTYPE_KEY_CONFLICT:
3686                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3687                 return_status = -EIO;
3688                 break;
3689         default:
3690                 PMD_INIT_LOG(ERR,
3691                              "add mac ethertype failed for undefined, code=%d.",
3692                              resp_code);
3693                 return_status = -EIO;
3694                 break;
3695         }
3696
3697         return return_status;
3698 }
3699
3700 static int
3701 hns3_add_mgr_tbl(struct hns3_hw *hw,
3702                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3703 {
3704         struct hns3_cmd_desc desc;
3705         uint8_t resp_code;
3706         uint16_t retval;
3707         int ret;
3708
3709         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3710         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3711
3712         ret = hns3_cmd_send(hw, &desc, 1);
3713         if (ret) {
3714                 PMD_INIT_LOG(ERR,
3715                              "add mac ethertype failed for cmd_send, ret =%d.",
3716                              ret);
3717                 return ret;
3718         }
3719
3720         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3721         retval = rte_le_to_cpu_16(desc.retval);
3722
3723         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3724 }
3725
3726 static void
3727 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3728                      int *table_item_num)
3729 {
3730         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3731
3732         /*
3733          * In current version, we add one item in management table as below:
3734          * 0x0180C200000E -- LLDP MC address
3735          */
3736         tbl = mgr_table;
3737         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3738         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3739         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3740         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3741         tbl->i_port_bitmap = 0x1;
3742         *table_item_num = 1;
3743 }
3744
3745 static int
3746 hns3_init_mgr_tbl(struct hns3_hw *hw)
3747 {
3748 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3749         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3750         int table_item_num;
3751         int ret;
3752         int i;
3753
3754         memset(mgr_table, 0, sizeof(mgr_table));
3755         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3756         for (i = 0; i < table_item_num; i++) {
3757                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3758                 if (ret) {
3759                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3760                                      ret);
3761                         return ret;
3762                 }
3763         }
3764
3765         return 0;
3766 }
3767
3768 static void
3769 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3770                         bool en_mc, bool en_bc, int vport_id)
3771 {
3772         if (!param)
3773                 return;
3774
3775         memset(param, 0, sizeof(struct hns3_promisc_param));
3776         if (en_uc)
3777                 param->enable = HNS3_PROMISC_EN_UC;
3778         if (en_mc)
3779                 param->enable |= HNS3_PROMISC_EN_MC;
3780         if (en_bc)
3781                 param->enable |= HNS3_PROMISC_EN_BC;
3782         param->vf_id = vport_id;
3783 }
3784
3785 static int
3786 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3787 {
3788         struct hns3_promisc_cfg_cmd *req;
3789         struct hns3_cmd_desc desc;
3790         int ret;
3791
3792         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3793
3794         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3795         req->vf_id = param->vf_id;
3796         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3797             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3798
3799         ret = hns3_cmd_send(hw, &desc, 1);
3800         if (ret)
3801                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3802
3803         return ret;
3804 }
3805
3806 static int
3807 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3808 {
3809         struct hns3_promisc_param param;
3810         bool en_bc_pmc = true;
3811         uint8_t vf_id;
3812
3813         /*
3814          * In current version VF is not supported when PF is driven by DPDK
3815          * driver, the PF-related vf_id is 0, just need to configure parameters
3816          * for vf_id 0.
3817          */
3818         vf_id = 0;
3819
3820         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3821         return hns3_cmd_set_promisc_mode(hw, &param);
3822 }
3823
3824 static int
3825 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3826 {
3827         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3828         struct hns3_pf *pf = &hns->pf;
3829         struct hns3_promisc_param param;
3830         uint16_t func_id;
3831         int ret;
3832
3833         /* func_id 0 is denoted PF, the VFs start from 1 */
3834         for (func_id = 1; func_id < pf->func_num; func_id++) {
3835                 hns3_promisc_param_init(&param, false, false, false, func_id);
3836                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3837                 if (ret)
3838                         return ret;
3839         }
3840
3841         return 0;
3842 }
3843
3844 static int
3845 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3846 {
3847         bool allmulti = dev->data->all_multicast ? true : false;
3848         struct hns3_adapter *hns = dev->data->dev_private;
3849         struct hns3_hw *hw = &hns->hw;
3850         uint64_t offloads;
3851         int err;
3852         int ret;
3853
3854         rte_spinlock_lock(&hw->lock);
3855         ret = hns3_set_promisc_mode(hw, true, true);
3856         if (ret) {
3857                 rte_spinlock_unlock(&hw->lock);
3858                 hns3_err(hw, "failed to enable promiscuous mode, ret = %d",
3859                          ret);
3860                 return ret;
3861         }
3862
3863         /*
3864          * When promiscuous mode was enabled, disable the vlan filter to let
3865          * all packets coming in in the receiving direction.
3866          */
3867         offloads = dev->data->dev_conf.rxmode.offloads;
3868         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3869                 ret = hns3_enable_vlan_filter(hns, false);
3870                 if (ret) {
3871                         hns3_err(hw, "failed to enable promiscuous mode due to "
3872                                      "failure to disable vlan filter, ret = %d",
3873                                  ret);
3874                         err = hns3_set_promisc_mode(hw, false, allmulti);
3875                         if (err)
3876                                 hns3_err(hw, "failed to restore promiscuous "
3877                                          "status after disable vlan filter "
3878                                          "failed during enabling promiscuous "
3879                                          "mode, ret = %d", ret);
3880                 }
3881         }
3882
3883         rte_spinlock_unlock(&hw->lock);
3884
3885         return ret;
3886 }
3887
3888 static int
3889 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3890 {
3891         bool allmulti = dev->data->all_multicast ? true : false;
3892         struct hns3_adapter *hns = dev->data->dev_private;
3893         struct hns3_hw *hw = &hns->hw;
3894         uint64_t offloads;
3895         int err;
3896         int ret;
3897
3898         /* If now in all_multicast mode, must remain in all_multicast mode. */
3899         rte_spinlock_lock(&hw->lock);
3900         ret = hns3_set_promisc_mode(hw, false, allmulti);
3901         if (ret) {
3902                 rte_spinlock_unlock(&hw->lock);
3903                 hns3_err(hw, "failed to disable promiscuous mode, ret = %d",
3904                          ret);
3905                 return ret;
3906         }
3907         /* when promiscuous mode was disabled, restore the vlan filter status */
3908         offloads = dev->data->dev_conf.rxmode.offloads;
3909         if (offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
3910                 ret = hns3_enable_vlan_filter(hns, true);
3911                 if (ret) {
3912                         hns3_err(hw, "failed to disable promiscuous mode due to"
3913                                  " failure to restore vlan filter, ret = %d",
3914                                  ret);
3915                         err = hns3_set_promisc_mode(hw, true, true);
3916                         if (err)
3917                                 hns3_err(hw, "failed to restore promiscuous "
3918                                          "status after enabling vlan filter "
3919                                          "failed during disabling promiscuous "
3920                                          "mode, ret = %d", ret);
3921                 }
3922         }
3923         rte_spinlock_unlock(&hw->lock);
3924
3925         return ret;
3926 }
3927
3928 static int
3929 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3930 {
3931         struct hns3_adapter *hns = dev->data->dev_private;
3932         struct hns3_hw *hw = &hns->hw;
3933         int ret;
3934
3935         if (dev->data->promiscuous)
3936                 return 0;
3937
3938         rte_spinlock_lock(&hw->lock);
3939         ret = hns3_set_promisc_mode(hw, false, true);
3940         rte_spinlock_unlock(&hw->lock);
3941         if (ret)
3942                 hns3_err(hw, "failed to enable allmulticast mode, ret = %d",
3943                          ret);
3944
3945         return ret;
3946 }
3947
3948 static int
3949 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3950 {
3951         struct hns3_adapter *hns = dev->data->dev_private;
3952         struct hns3_hw *hw = &hns->hw;
3953         int ret;
3954
3955         /* If now in promiscuous mode, must remain in all_multicast mode. */
3956         if (dev->data->promiscuous)
3957                 return 0;
3958
3959         rte_spinlock_lock(&hw->lock);
3960         ret = hns3_set_promisc_mode(hw, false, false);
3961         rte_spinlock_unlock(&hw->lock);
3962         if (ret)
3963                 hns3_err(hw, "failed to disable allmulticast mode, ret = %d",
3964                          ret);
3965
3966         return ret;
3967 }
3968
3969 static int
3970 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3971 {
3972         struct hns3_hw *hw = &hns->hw;
3973         bool allmulti = hw->data->all_multicast ? true : false;
3974         int ret;
3975
3976         if (hw->data->promiscuous) {
3977                 ret = hns3_set_promisc_mode(hw, true, true);
3978                 if (ret)
3979                         hns3_err(hw, "failed to restore promiscuous mode, "
3980                                  "ret = %d", ret);
3981                 return ret;
3982         }
3983
3984         ret = hns3_set_promisc_mode(hw, false, allmulti);
3985         if (ret)
3986                 hns3_err(hw, "failed to restore allmulticast mode, ret = %d",
3987                          ret);
3988         return ret;
3989 }
3990
3991 static int
3992 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3993 {
3994         struct hns3_sfp_speed_cmd *resp;
3995         struct hns3_cmd_desc desc;
3996         int ret;
3997
3998         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3999         resp = (struct hns3_sfp_speed_cmd *)desc.data;
4000         ret = hns3_cmd_send(hw, &desc, 1);
4001         if (ret == -EOPNOTSUPP) {
4002                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
4003                 return ret;
4004         } else if (ret) {
4005                 hns3_err(hw, "get sfp speed failed %d", ret);
4006                 return ret;
4007         }
4008
4009         *speed = resp->sfp_speed;
4010
4011         return 0;
4012 }
4013
4014 static uint8_t
4015 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
4016 {
4017         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
4018                 duplex = ETH_LINK_FULL_DUPLEX;
4019
4020         return duplex;
4021 }
4022
4023 static int
4024 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
4025 {
4026         struct hns3_mac *mac = &hw->mac;
4027         int ret;
4028
4029         duplex = hns3_check_speed_dup(duplex, speed);
4030         if (mac->link_speed == speed && mac->link_duplex == duplex)
4031                 return 0;
4032
4033         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
4034         if (ret)
4035                 return ret;
4036
4037         mac->link_speed = speed;
4038         mac->link_duplex = duplex;
4039
4040         return 0;
4041 }
4042
4043 static int
4044 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
4045 {
4046         struct hns3_adapter *hns = eth_dev->data->dev_private;
4047         struct hns3_hw *hw = &hns->hw;
4048         struct hns3_pf *pf = &hns->pf;
4049         uint32_t speed;
4050         int ret;
4051
4052         /* If IMP do not support get SFP/qSFP speed, return directly */
4053         if (!pf->support_sfp_query)
4054                 return 0;
4055
4056         ret = hns3_get_sfp_speed(hw, &speed);
4057         if (ret == -EOPNOTSUPP) {
4058                 pf->support_sfp_query = false;
4059                 return ret;
4060         } else if (ret)
4061                 return ret;
4062
4063         if (speed == ETH_SPEED_NUM_NONE)
4064                 return 0; /* do nothing if no SFP */
4065
4066         /* Config full duplex for SFP */
4067         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
4068 }
4069
4070 static int
4071 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
4072 {
4073         struct hns3_config_mac_mode_cmd *req;
4074         struct hns3_cmd_desc desc;
4075         uint32_t loop_en = 0;
4076         uint8_t val = 0;
4077         int ret;
4078
4079         req = (struct hns3_config_mac_mode_cmd *)desc.data;
4080
4081         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
4082         if (enable)
4083                 val = 1;
4084         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
4085         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
4086         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
4087         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
4088         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
4089         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
4090         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
4091         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
4092         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
4093         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
4094         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
4095         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
4096         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
4097         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
4098         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
4099
4100         ret = hns3_cmd_send(hw, &desc, 1);
4101         if (ret)
4102                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
4103
4104         return ret;
4105 }
4106
4107 static int
4108 hns3_get_mac_link_status(struct hns3_hw *hw)
4109 {
4110         struct hns3_link_status_cmd *req;
4111         struct hns3_cmd_desc desc;
4112         int link_status;
4113         int ret;
4114
4115         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
4116         ret = hns3_cmd_send(hw, &desc, 1);
4117         if (ret) {
4118                 hns3_err(hw, "get link status cmd failed %d", ret);
4119                 return ETH_LINK_DOWN;
4120         }
4121
4122         req = (struct hns3_link_status_cmd *)desc.data;
4123         link_status = req->status & HNS3_LINK_STATUS_UP_M;
4124
4125         return !!link_status;
4126 }
4127
4128 void
4129 hns3_update_link_status(struct hns3_hw *hw)
4130 {
4131         int state;
4132
4133         state = hns3_get_mac_link_status(hw);
4134         if (state != hw->mac.link_status) {
4135                 hw->mac.link_status = state;
4136                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
4137         }
4138 }
4139
4140 static void
4141 hns3_service_handler(void *param)
4142 {
4143         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
4144         struct hns3_adapter *hns = eth_dev->data->dev_private;
4145         struct hns3_hw *hw = &hns->hw;
4146
4147         if (!hns3_is_reset_pending(hns)) {
4148                 hns3_update_speed_duplex(eth_dev);
4149                 hns3_update_link_status(hw);
4150         } else
4151                 hns3_warn(hw, "Cancel the query when reset is pending");
4152
4153         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4154 }
4155
4156 static int
4157 hns3_init_hardware(struct hns3_adapter *hns)
4158 {
4159         struct hns3_hw *hw = &hns->hw;
4160         int ret;
4161
4162         ret = hns3_map_tqp(hw);
4163         if (ret) {
4164                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
4165                 return ret;
4166         }
4167
4168         ret = hns3_init_umv_space(hw);
4169         if (ret) {
4170                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
4171                 return ret;
4172         }
4173
4174         ret = hns3_mac_init(hw);
4175         if (ret) {
4176                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
4177                 goto err_mac_init;
4178         }
4179
4180         ret = hns3_init_mgr_tbl(hw);
4181         if (ret) {
4182                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
4183                 goto err_mac_init;
4184         }
4185
4186         ret = hns3_set_promisc_mode(hw, false, false);
4187         if (ret) {
4188                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
4189                 goto err_mac_init;
4190         }
4191
4192         ret = hns3_clear_all_vfs_promisc_mode(hw);
4193         if (ret) {
4194                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
4195                              ret);
4196                 goto err_mac_init;
4197         }
4198
4199         ret = hns3_init_vlan_config(hns);
4200         if (ret) {
4201                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4202                 goto err_mac_init;
4203         }
4204
4205         ret = hns3_dcb_init(hw);
4206         if (ret) {
4207                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4208                 goto err_mac_init;
4209         }
4210
4211         ret = hns3_init_fd_config(hns);
4212         if (ret) {
4213                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4214                 goto err_mac_init;
4215         }
4216
4217         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4218         if (ret) {
4219                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4220                 goto err_mac_init;
4221         }
4222
4223         ret = hns3_config_gro(hw, false);
4224         if (ret) {
4225                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4226                 goto err_mac_init;
4227         }
4228
4229         /*
4230          * In the initialization clearing the all hardware mapping relationship
4231          * configurations between queues and interrupt vectors is needed, so
4232          * some error caused by the residual configurations, such as the
4233          * unexpected interrupt, can be avoid.
4234          */
4235         ret = hns3_init_ring_with_vector(hw);
4236         if (ret) {
4237                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
4238                 goto err_mac_init;
4239         }
4240
4241         return 0;
4242
4243 err_mac_init:
4244         hns3_uninit_umv_space(hw);
4245         return ret;
4246 }
4247
4248 static int
4249 hns3_init_pf(struct rte_eth_dev *eth_dev)
4250 {
4251         struct rte_device *dev = eth_dev->device;
4252         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4253         struct hns3_adapter *hns = eth_dev->data->dev_private;
4254         struct hns3_hw *hw = &hns->hw;
4255         int ret;
4256
4257         PMD_INIT_FUNC_TRACE();
4258
4259         /* Get hardware io base address from pcie BAR2 IO space */
4260         hw->io_base = pci_dev->mem_resource[2].addr;
4261
4262         /* Firmware command queue initialize */
4263         ret = hns3_cmd_init_queue(hw);
4264         if (ret) {
4265                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4266                 goto err_cmd_init_queue;
4267         }
4268
4269         hns3_clear_all_event_cause(hw);
4270
4271         /* Firmware command initialize */
4272         ret = hns3_cmd_init(hw);
4273         if (ret) {
4274                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4275                 goto err_cmd_init;
4276         }
4277
4278         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4279                                          hns3_interrupt_handler,
4280                                          eth_dev);
4281         if (ret) {
4282                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4283                 goto err_intr_callback_register;
4284         }
4285
4286         /* Enable interrupt */
4287         rte_intr_enable(&pci_dev->intr_handle);
4288         hns3_pf_enable_irq0(hw);
4289
4290         /* Get configuration */
4291         ret = hns3_get_configuration(hw);
4292         if (ret) {
4293                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4294                 goto err_get_config;
4295         }
4296
4297         ret = hns3_init_hardware(hns);
4298         if (ret) {
4299                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4300                 goto err_get_config;
4301         }
4302
4303         /* Initialize flow director filter list & hash */
4304         ret = hns3_fdir_filter_init(hns);
4305         if (ret) {
4306                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4307                 goto err_hw_init;
4308         }
4309
4310         hns3_set_default_rss_args(hw);
4311
4312         ret = hns3_enable_hw_error_intr(hns, true);
4313         if (ret) {
4314                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4315                              ret);
4316                 goto err_fdir;
4317         }
4318
4319         return 0;
4320
4321 err_fdir:
4322         hns3_fdir_filter_uninit(hns);
4323 err_hw_init:
4324         hns3_uninit_umv_space(hw);
4325
4326 err_get_config:
4327         hns3_pf_disable_irq0(hw);
4328         rte_intr_disable(&pci_dev->intr_handle);
4329         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4330                              eth_dev);
4331 err_intr_callback_register:
4332 err_cmd_init:
4333         hns3_cmd_uninit(hw);
4334         hns3_cmd_destroy_queue(hw);
4335 err_cmd_init_queue:
4336         hw->io_base = NULL;
4337
4338         return ret;
4339 }
4340
4341 static void
4342 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4343 {
4344         struct hns3_adapter *hns = eth_dev->data->dev_private;
4345         struct rte_device *dev = eth_dev->device;
4346         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4347         struct hns3_hw *hw = &hns->hw;
4348
4349         PMD_INIT_FUNC_TRACE();
4350
4351         hns3_enable_hw_error_intr(hns, false);
4352         hns3_rss_uninit(hns);
4353         hns3_fdir_filter_uninit(hns);
4354         hns3_uninit_umv_space(hw);
4355         hns3_pf_disable_irq0(hw);
4356         rte_intr_disable(&pci_dev->intr_handle);
4357         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4358                              eth_dev);
4359         hns3_cmd_uninit(hw);
4360         hns3_cmd_destroy_queue(hw);
4361         hw->io_base = NULL;
4362 }
4363
4364 static int
4365 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4366 {
4367         struct hns3_hw *hw = &hns->hw;
4368         int ret;
4369
4370         ret = hns3_dcb_cfg_update(hns);
4371         if (ret)
4372                 return ret;
4373
4374         /* Enable queues */
4375         ret = hns3_start_queues(hns, reset_queue);
4376         if (ret) {
4377                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4378                 return ret;
4379         }
4380
4381         /* Enable MAC */
4382         ret = hns3_cfg_mac_mode(hw, true);
4383         if (ret) {
4384                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4385                 goto err_config_mac_mode;
4386         }
4387         return 0;
4388
4389 err_config_mac_mode:
4390         hns3_stop_queues(hns, true);
4391         return ret;
4392 }
4393
4394 static int
4395 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4396 {
4397         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4398         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4399         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4400         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4401         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4402         uint32_t intr_vector;
4403         uint16_t q_id;
4404         int ret;
4405
4406         if (dev->data->dev_conf.intr_conf.rxq == 0)
4407                 return 0;
4408
4409         /* disable uio/vfio intr/eventfd mapping */
4410         rte_intr_disable(intr_handle);
4411
4412         /* check and configure queue intr-vector mapping */
4413         if (rte_intr_cap_multiple(intr_handle) ||
4414             !RTE_ETH_DEV_SRIOV(dev).active) {
4415                 intr_vector = hw->used_rx_queues;
4416                 /* creates event fd for each intr vector when MSIX is used */
4417                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4418                         return -EINVAL;
4419         }
4420         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4421                 intr_handle->intr_vec =
4422                         rte_zmalloc("intr_vec",
4423                                     hw->used_rx_queues * sizeof(int), 0);
4424                 if (intr_handle->intr_vec == NULL) {
4425                         hns3_err(hw, "Failed to allocate %d rx_queues"
4426                                      " intr_vec", hw->used_rx_queues);
4427                         ret = -ENOMEM;
4428                         goto alloc_intr_vec_error;
4429                 }
4430         }
4431
4432         if (rte_intr_allow_others(intr_handle)) {
4433                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4434                 base = RTE_INTR_VEC_RXTX_OFFSET;
4435         }
4436         if (rte_intr_dp_is_en(intr_handle)) {
4437                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4438                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4439                                                          HNS3_RING_TYPE_RX,
4440                                                          q_id);
4441                         if (ret)
4442                                 goto bind_vector_error;
4443                         intr_handle->intr_vec[q_id] = vec;
4444                         if (vec < base + intr_handle->nb_efd - 1)
4445                                 vec++;
4446                 }
4447         }
4448         rte_intr_enable(intr_handle);
4449         return 0;
4450
4451 bind_vector_error:
4452         rte_intr_efd_disable(intr_handle);
4453         if (intr_handle->intr_vec) {
4454                 free(intr_handle->intr_vec);
4455                 intr_handle->intr_vec = NULL;
4456         }
4457         return ret;
4458 alloc_intr_vec_error:
4459         rte_intr_efd_disable(intr_handle);
4460         return ret;
4461 }
4462
4463 static int
4464 hns3_restore_rx_interrupt(struct hns3_hw *hw)
4465 {
4466         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
4467         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4468         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4469         uint16_t q_id;
4470         int ret;
4471
4472         if (dev->data->dev_conf.intr_conf.rxq == 0)
4473                 return 0;
4474
4475         if (rte_intr_dp_is_en(intr_handle)) {
4476                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4477                         ret = hns3_bind_ring_with_vector(hw,
4478                                         intr_handle->intr_vec[q_id], true,
4479                                         HNS3_RING_TYPE_RX, q_id);
4480                         if (ret)
4481                                 return ret;
4482                 }
4483         }
4484
4485         return 0;
4486 }
4487
4488 static void
4489 hns3_restore_filter(struct rte_eth_dev *dev)
4490 {
4491         hns3_restore_rss_filter(dev);
4492 }
4493
4494 static int
4495 hns3_dev_start(struct rte_eth_dev *dev)
4496 {
4497         struct hns3_adapter *hns = dev->data->dev_private;
4498         struct hns3_hw *hw = &hns->hw;
4499         int ret;
4500
4501         PMD_INIT_FUNC_TRACE();
4502         if (rte_atomic16_read(&hw->reset.resetting))
4503                 return -EBUSY;
4504
4505         rte_spinlock_lock(&hw->lock);
4506         hw->adapter_state = HNS3_NIC_STARTING;
4507
4508         ret = hns3_do_start(hns, true);
4509         if (ret) {
4510                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4511                 rte_spinlock_unlock(&hw->lock);
4512                 return ret;
4513         }
4514         ret = hns3_map_rx_interrupt(dev);
4515         if (ret) {
4516                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4517                 rte_spinlock_unlock(&hw->lock);
4518                 return ret;
4519         }
4520
4521         hw->adapter_state = HNS3_NIC_STARTED;
4522         rte_spinlock_unlock(&hw->lock);
4523
4524         hns3_set_rxtx_function(dev);
4525         hns3_mp_req_start_rxtx(dev);
4526         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4527
4528         hns3_restore_filter(dev);
4529
4530         /* Enable interrupt of all rx queues before enabling queues */
4531         hns3_dev_all_rx_queue_intr_enable(hw, true);
4532         /*
4533          * When finished the initialization, enable queues to receive/transmit
4534          * packets.
4535          */
4536         hns3_enable_all_queues(hw, true);
4537
4538         hns3_info(hw, "hns3 dev start successful!");
4539         return 0;
4540 }
4541
4542 static int
4543 hns3_do_stop(struct hns3_adapter *hns)
4544 {
4545         struct hns3_hw *hw = &hns->hw;
4546         bool reset_queue;
4547         int ret;
4548
4549         ret = hns3_cfg_mac_mode(hw, false);
4550         if (ret)
4551                 return ret;
4552         hw->mac.link_status = ETH_LINK_DOWN;
4553
4554         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4555                 hns3_configure_all_mac_addr(hns, true);
4556                 reset_queue = true;
4557         } else
4558                 reset_queue = false;
4559         hw->mac.default_addr_setted = false;
4560         return hns3_stop_queues(hns, reset_queue);
4561 }
4562
4563 static void
4564 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4565 {
4566         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4567         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4568         struct hns3_adapter *hns = dev->data->dev_private;
4569         struct hns3_hw *hw = &hns->hw;
4570         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
4571         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
4572         uint16_t q_id;
4573
4574         if (dev->data->dev_conf.intr_conf.rxq == 0)
4575                 return;
4576
4577         /* unmap the ring with vector */
4578         if (rte_intr_allow_others(intr_handle)) {
4579                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4580                 base = RTE_INTR_VEC_RXTX_OFFSET;
4581         }
4582         if (rte_intr_dp_is_en(intr_handle)) {
4583                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4584                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4585                                                          HNS3_RING_TYPE_RX,
4586                                                          q_id);
4587                         if (vec < base + intr_handle->nb_efd - 1)
4588                                 vec++;
4589                 }
4590         }
4591         /* Clean datapath event and queue/vec mapping */
4592         rte_intr_efd_disable(intr_handle);
4593         if (intr_handle->intr_vec) {
4594                 rte_free(intr_handle->intr_vec);
4595                 intr_handle->intr_vec = NULL;
4596         }
4597 }
4598
4599 static void
4600 hns3_dev_stop(struct rte_eth_dev *dev)
4601 {
4602         struct hns3_adapter *hns = dev->data->dev_private;
4603         struct hns3_hw *hw = &hns->hw;
4604
4605         PMD_INIT_FUNC_TRACE();
4606
4607         hw->adapter_state = HNS3_NIC_STOPPING;
4608         hns3_set_rxtx_function(dev);
4609         rte_wmb();
4610         /* Disable datapath on secondary process. */
4611         hns3_mp_req_stop_rxtx(dev);
4612         /* Prevent crashes when queues are still in use. */
4613         rte_delay_ms(hw->tqps_num);
4614
4615         rte_spinlock_lock(&hw->lock);
4616         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4617                 hns3_do_stop(hns);
4618                 hns3_unmap_rx_interrupt(dev);
4619                 hns3_dev_release_mbufs(hns);
4620                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4621         }
4622         rte_eal_alarm_cancel(hns3_service_handler, dev);
4623         rte_spinlock_unlock(&hw->lock);
4624 }
4625
4626 static void
4627 hns3_dev_close(struct rte_eth_dev *eth_dev)
4628 {
4629         struct hns3_adapter *hns = eth_dev->data->dev_private;
4630         struct hns3_hw *hw = &hns->hw;
4631
4632         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4633                 rte_free(eth_dev->process_private);
4634                 eth_dev->process_private = NULL;
4635                 return;
4636         }
4637
4638         if (hw->adapter_state == HNS3_NIC_STARTED)
4639                 hns3_dev_stop(eth_dev);
4640
4641         hw->adapter_state = HNS3_NIC_CLOSING;
4642         hns3_reset_abort(hns);
4643         hw->adapter_state = HNS3_NIC_CLOSED;
4644
4645         hns3_configure_all_mc_mac_addr(hns, true);
4646         hns3_remove_all_vlan_table(hns);
4647         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4648         hns3_uninit_pf(eth_dev);
4649         hns3_free_all_queues(eth_dev);
4650         rte_free(hw->reset.wait_data);
4651         rte_free(eth_dev->process_private);
4652         eth_dev->process_private = NULL;
4653         hns3_mp_uninit_primary();
4654         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4655 }
4656
4657 static int
4658 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4659 {
4660         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4661         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4662
4663         fc_conf->pause_time = pf->pause_time;
4664
4665         /* return fc current mode */
4666         switch (hw->current_mode) {
4667         case HNS3_FC_FULL:
4668                 fc_conf->mode = RTE_FC_FULL;
4669                 break;
4670         case HNS3_FC_TX_PAUSE:
4671                 fc_conf->mode = RTE_FC_TX_PAUSE;
4672                 break;
4673         case HNS3_FC_RX_PAUSE:
4674                 fc_conf->mode = RTE_FC_RX_PAUSE;
4675                 break;
4676         case HNS3_FC_NONE:
4677         default:
4678                 fc_conf->mode = RTE_FC_NONE;
4679                 break;
4680         }
4681
4682         return 0;
4683 }
4684
4685 static void
4686 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4687 {
4688         switch (mode) {
4689         case RTE_FC_NONE:
4690                 hw->requested_mode = HNS3_FC_NONE;
4691                 break;
4692         case RTE_FC_RX_PAUSE:
4693                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4694                 break;
4695         case RTE_FC_TX_PAUSE:
4696                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4697                 break;
4698         case RTE_FC_FULL:
4699                 hw->requested_mode = HNS3_FC_FULL;
4700                 break;
4701         default:
4702                 hw->requested_mode = HNS3_FC_NONE;
4703                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4704                           "configured to RTE_FC_NONE", mode);
4705                 break;
4706         }
4707 }
4708
4709 static int
4710 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4711 {
4712         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4714         int ret;
4715
4716         if (fc_conf->high_water || fc_conf->low_water ||
4717             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4718                 hns3_err(hw, "Unsupported flow control settings specified, "
4719                          "high_water(%u), low_water(%u), send_xon(%u) and "
4720                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4721                          fc_conf->high_water, fc_conf->low_water,
4722                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4723                 return -EINVAL;
4724         }
4725         if (fc_conf->autoneg) {
4726                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4727                 return -EINVAL;
4728         }
4729         if (!fc_conf->pause_time) {
4730                 hns3_err(hw, "Invalid pause time %d setting.",
4731                          fc_conf->pause_time);
4732                 return -EINVAL;
4733         }
4734
4735         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4736             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4737                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4738                          "current_fc_status = %d", hw->current_fc_status);
4739                 return -EOPNOTSUPP;
4740         }
4741
4742         hns3_get_fc_mode(hw, fc_conf->mode);
4743         if (hw->requested_mode == hw->current_mode &&
4744             pf->pause_time == fc_conf->pause_time)
4745                 return 0;
4746
4747         rte_spinlock_lock(&hw->lock);
4748         ret = hns3_fc_enable(dev, fc_conf);
4749         rte_spinlock_unlock(&hw->lock);
4750
4751         return ret;
4752 }
4753
4754 static int
4755 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4756                             struct rte_eth_pfc_conf *pfc_conf)
4757 {
4758         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4759         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4760         uint8_t priority;
4761         int ret;
4762
4763         if (!hns3_dev_dcb_supported(hw)) {
4764                 hns3_err(hw, "This port does not support dcb configurations.");
4765                 return -EOPNOTSUPP;
4766         }
4767
4768         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4769             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4770                 hns3_err(hw, "Unsupported flow control settings specified, "
4771                          "high_water(%u), low_water(%u), send_xon(%u) and "
4772                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4773                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4774                          pfc_conf->fc.send_xon,
4775                          pfc_conf->fc.mac_ctrl_frame_fwd);
4776                 return -EINVAL;
4777         }
4778         if (pfc_conf->fc.autoneg) {
4779                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4780                 return -EINVAL;
4781         }
4782         if (pfc_conf->fc.pause_time == 0) {
4783                 hns3_err(hw, "Invalid pause time %d setting.",
4784                          pfc_conf->fc.pause_time);
4785                 return -EINVAL;
4786         }
4787
4788         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4789             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4790                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4791                              "current_fc_status = %d", hw->current_fc_status);
4792                 return -EOPNOTSUPP;
4793         }
4794
4795         priority = pfc_conf->priority;
4796         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4797         if (hw->dcb_info.pfc_en & BIT(priority) &&
4798             hw->requested_mode == hw->current_mode &&
4799             pfc_conf->fc.pause_time == pf->pause_time)
4800                 return 0;
4801
4802         rte_spinlock_lock(&hw->lock);
4803         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4804         rte_spinlock_unlock(&hw->lock);
4805
4806         return ret;
4807 }
4808
4809 static int
4810 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4811 {
4812         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4813         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4814         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4815         int i;
4816
4817         rte_spinlock_lock(&hw->lock);
4818         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4819                 dcb_info->nb_tcs = pf->local_max_tc;
4820         else
4821                 dcb_info->nb_tcs = 1;
4822
4823         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4824                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4825         for (i = 0; i < dcb_info->nb_tcs; i++)
4826                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4827
4828         for (i = 0; i < hw->num_tc; i++) {
4829                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4830                 dcb_info->tc_queue.tc_txq[0][i].base =
4831                                                 hw->tc_queue[i].tqp_offset;
4832                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4833                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4834                                                 hw->tc_queue[i].tqp_count;
4835         }
4836         rte_spinlock_unlock(&hw->lock);
4837
4838         return 0;
4839 }
4840
4841 static int
4842 hns3_reinit_dev(struct hns3_adapter *hns)
4843 {
4844         struct hns3_hw *hw = &hns->hw;
4845         int ret;
4846
4847         ret = hns3_cmd_init(hw);
4848         if (ret) {
4849                 hns3_err(hw, "Failed to init cmd: %d", ret);
4850                 return ret;
4851         }
4852
4853         ret = hns3_reset_all_queues(hns);
4854         if (ret) {
4855                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4856                 return ret;
4857         }
4858
4859         ret = hns3_init_hardware(hns);
4860         if (ret) {
4861                 hns3_err(hw, "Failed to init hardware: %d", ret);
4862                 return ret;
4863         }
4864
4865         ret = hns3_enable_hw_error_intr(hns, true);
4866         if (ret) {
4867                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4868                              ret);
4869                 return ret;
4870         }
4871         hns3_info(hw, "Reset done, driver initialization finished.");
4872
4873         return 0;
4874 }
4875
4876 static bool
4877 is_pf_reset_done(struct hns3_hw *hw)
4878 {
4879         uint32_t val, reg, reg_bit;
4880
4881         switch (hw->reset.level) {
4882         case HNS3_IMP_RESET:
4883                 reg = HNS3_GLOBAL_RESET_REG;
4884                 reg_bit = HNS3_IMP_RESET_BIT;
4885                 break;
4886         case HNS3_GLOBAL_RESET:
4887                 reg = HNS3_GLOBAL_RESET_REG;
4888                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4889                 break;
4890         case HNS3_FUNC_RESET:
4891                 reg = HNS3_FUN_RST_ING;
4892                 reg_bit = HNS3_FUN_RST_ING_B;
4893                 break;
4894         case HNS3_FLR_RESET:
4895         default:
4896                 hns3_err(hw, "Wait for unsupported reset level: %d",
4897                          hw->reset.level);
4898                 return true;
4899         }
4900         val = hns3_read_dev(hw, reg);
4901         if (hns3_get_bit(val, reg_bit))
4902                 return false;
4903         else
4904                 return true;
4905 }
4906
4907 bool
4908 hns3_is_reset_pending(struct hns3_adapter *hns)
4909 {
4910         struct hns3_hw *hw = &hns->hw;
4911         enum hns3_reset_level reset;
4912
4913         hns3_check_event_cause(hns, NULL);
4914         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4915         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4916                 hns3_warn(hw, "High level reset %d is pending", reset);
4917                 return true;
4918         }
4919         reset = hns3_get_reset_level(hns, &hw->reset.request);
4920         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4921                 hns3_warn(hw, "High level reset %d is request", reset);
4922                 return true;
4923         }
4924         return false;
4925 }
4926
4927 static int
4928 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4929 {
4930         struct hns3_hw *hw = &hns->hw;
4931         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4932         struct timeval tv;
4933
4934         if (wait_data->result == HNS3_WAIT_SUCCESS)
4935                 return 0;
4936         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4937                 gettimeofday(&tv, NULL);
4938                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4939                           tv.tv_sec, tv.tv_usec);
4940                 return -ETIME;
4941         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4942                 return -EAGAIN;
4943
4944         wait_data->hns = hns;
4945         wait_data->check_completion = is_pf_reset_done;
4946         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4947                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4948         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4949         wait_data->count = HNS3_RESET_WAIT_CNT;
4950         wait_data->result = HNS3_WAIT_REQUEST;
4951         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4952         return -EAGAIN;
4953 }
4954
4955 static int
4956 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4957 {
4958         struct hns3_cmd_desc desc;
4959         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4960
4961         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4962         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4963         req->fun_reset_vfid = func_id;
4964
4965         return hns3_cmd_send(hw, &desc, 1);
4966 }
4967
4968 static int
4969 hns3_imp_reset_cmd(struct hns3_hw *hw)
4970 {
4971         struct hns3_cmd_desc desc;
4972
4973         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4974         desc.data[0] = 0xeedd;
4975
4976         return hns3_cmd_send(hw, &desc, 1);
4977 }
4978
4979 static void
4980 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4981 {
4982         struct hns3_hw *hw = &hns->hw;
4983         struct timeval tv;
4984         uint32_t val;
4985
4986         gettimeofday(&tv, NULL);
4987         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4988             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4989                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4990                           tv.tv_sec, tv.tv_usec);
4991                 return;
4992         }
4993
4994         switch (reset_level) {
4995         case HNS3_IMP_RESET:
4996                 hns3_imp_reset_cmd(hw);
4997                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4998                           tv.tv_sec, tv.tv_usec);
4999                 break;
5000         case HNS3_GLOBAL_RESET:
5001                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
5002                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
5003                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
5004                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
5005                           tv.tv_sec, tv.tv_usec);
5006                 break;
5007         case HNS3_FUNC_RESET:
5008                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
5009                           tv.tv_sec, tv.tv_usec);
5010                 /* schedule again to check later */
5011                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
5012                 hns3_schedule_reset(hns);
5013                 break;
5014         default:
5015                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
5016                 return;
5017         }
5018         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
5019 }
5020
5021 static enum hns3_reset_level
5022 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
5023 {
5024         struct hns3_hw *hw = &hns->hw;
5025         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
5026
5027         /* Return the highest priority reset level amongst all */
5028         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
5029                 reset_level = HNS3_IMP_RESET;
5030         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
5031                 reset_level = HNS3_GLOBAL_RESET;
5032         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
5033                 reset_level = HNS3_FUNC_RESET;
5034         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
5035                 reset_level = HNS3_FLR_RESET;
5036
5037         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
5038                 return HNS3_NONE_RESET;
5039
5040         return reset_level;
5041 }
5042
5043 static int
5044 hns3_prepare_reset(struct hns3_adapter *hns)
5045 {
5046         struct hns3_hw *hw = &hns->hw;
5047         uint32_t reg_val;
5048         int ret;
5049
5050         switch (hw->reset.level) {
5051         case HNS3_FUNC_RESET:
5052                 ret = hns3_func_reset_cmd(hw, 0);
5053                 if (ret)
5054                         return ret;
5055
5056                 /*
5057                  * After performaning pf reset, it is not necessary to do the
5058                  * mailbox handling or send any command to firmware, because
5059                  * any mailbox handling or command to firmware is only valid
5060                  * after hns3_cmd_init is called.
5061                  */
5062                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
5063                 hw->reset.stats.request_cnt++;
5064                 break;
5065         case HNS3_IMP_RESET:
5066                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
5067                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
5068                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
5069                 break;
5070         default:
5071                 break;
5072         }
5073         return 0;
5074 }
5075
5076 static int
5077 hns3_set_rst_done(struct hns3_hw *hw)
5078 {
5079         struct hns3_pf_rst_done_cmd *req;
5080         struct hns3_cmd_desc desc;
5081
5082         req = (struct hns3_pf_rst_done_cmd *)desc.data;
5083         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
5084         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
5085         return hns3_cmd_send(hw, &desc, 1);
5086 }
5087
5088 static int
5089 hns3_stop_service(struct hns3_adapter *hns)
5090 {
5091         struct hns3_hw *hw = &hns->hw;
5092         struct rte_eth_dev *eth_dev;
5093
5094         eth_dev = &rte_eth_devices[hw->data->port_id];
5095         if (hw->adapter_state == HNS3_NIC_STARTED)
5096                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
5097         hw->mac.link_status = ETH_LINK_DOWN;
5098
5099         hns3_set_rxtx_function(eth_dev);
5100         rte_wmb();
5101         /* Disable datapath on secondary process. */
5102         hns3_mp_req_stop_rxtx(eth_dev);
5103         rte_delay_ms(hw->tqps_num);
5104
5105         rte_spinlock_lock(&hw->lock);
5106         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
5107             hw->adapter_state == HNS3_NIC_STOPPING) {
5108                 hns3_do_stop(hns);
5109                 hw->reset.mbuf_deferred_free = true;
5110         } else
5111                 hw->reset.mbuf_deferred_free = false;
5112
5113         /*
5114          * It is cumbersome for hardware to pick-and-choose entries for deletion
5115          * from table space. Hence, for function reset software intervention is
5116          * required to delete the entries
5117          */
5118         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
5119                 hns3_configure_all_mc_mac_addr(hns, true);
5120         rte_spinlock_unlock(&hw->lock);
5121
5122         return 0;
5123 }
5124
5125 static int
5126 hns3_start_service(struct hns3_adapter *hns)
5127 {
5128         struct hns3_hw *hw = &hns->hw;
5129         struct rte_eth_dev *eth_dev;
5130
5131         if (hw->reset.level == HNS3_IMP_RESET ||
5132             hw->reset.level == HNS3_GLOBAL_RESET)
5133                 hns3_set_rst_done(hw);
5134         eth_dev = &rte_eth_devices[hw->data->port_id];
5135         hns3_set_rxtx_function(eth_dev);
5136         hns3_mp_req_start_rxtx(eth_dev);
5137         if (hw->adapter_state == HNS3_NIC_STARTED) {
5138                 hns3_service_handler(eth_dev);
5139
5140                 /* Enable interrupt of all rx queues before enabling queues */
5141                 hns3_dev_all_rx_queue_intr_enable(hw, true);
5142                 /*
5143                  * When finished the initialization, enable queues to receive
5144                  * and transmit packets.
5145                  */
5146                 hns3_enable_all_queues(hw, true);
5147         }
5148
5149         return 0;
5150 }
5151
5152 static int
5153 hns3_restore_conf(struct hns3_adapter *hns)
5154 {
5155         struct hns3_hw *hw = &hns->hw;
5156         int ret;
5157
5158         ret = hns3_configure_all_mac_addr(hns, false);
5159         if (ret)
5160                 return ret;
5161
5162         ret = hns3_configure_all_mc_mac_addr(hns, false);
5163         if (ret)
5164                 goto err_mc_mac;
5165
5166         ret = hns3_dev_promisc_restore(hns);
5167         if (ret)
5168                 goto err_promisc;
5169
5170         ret = hns3_restore_vlan_table(hns);
5171         if (ret)
5172                 goto err_promisc;
5173
5174         ret = hns3_restore_vlan_conf(hns);
5175         if (ret)
5176                 goto err_promisc;
5177
5178         ret = hns3_restore_all_fdir_filter(hns);
5179         if (ret)
5180                 goto err_promisc;
5181
5182         ret = hns3_restore_rx_interrupt(hw);
5183         if (ret)
5184                 goto err_promisc;
5185
5186         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
5187                 ret = hns3_do_start(hns, false);
5188                 if (ret)
5189                         goto err_promisc;
5190                 hns3_info(hw, "hns3 dev restart successful!");
5191         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
5192                 hw->adapter_state = HNS3_NIC_CONFIGURED;
5193         return 0;
5194
5195 err_promisc:
5196         hns3_configure_all_mc_mac_addr(hns, true);
5197 err_mc_mac:
5198         hns3_configure_all_mac_addr(hns, true);
5199         return ret;
5200 }
5201
5202 static void
5203 hns3_reset_service(void *param)
5204 {
5205         struct hns3_adapter *hns = (struct hns3_adapter *)param;
5206         struct hns3_hw *hw = &hns->hw;
5207         enum hns3_reset_level reset_level;
5208         struct timeval tv_delta;
5209         struct timeval tv_start;
5210         struct timeval tv;
5211         uint64_t msec;
5212         int ret;
5213
5214         /*
5215          * The interrupt is not triggered within the delay time.
5216          * The interrupt may have been lost. It is necessary to handle
5217          * the interrupt to recover from the error.
5218          */
5219         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
5220                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
5221                 hns3_err(hw, "Handling interrupts in delayed tasks");
5222                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
5223                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5224                 if (reset_level == HNS3_NONE_RESET) {
5225                         hns3_err(hw, "No reset level is set, try IMP reset");
5226                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
5227                 }
5228         }
5229         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
5230
5231         /*
5232          * Check if there is any ongoing reset in the hardware. This status can
5233          * be checked from reset_pending. If there is then, we need to wait for
5234          * hardware to complete reset.
5235          *    a. If we are able to figure out in reasonable time that hardware
5236          *       has fully resetted then, we can proceed with driver, client
5237          *       reset.
5238          *    b. else, we can come back later to check this status so re-sched
5239          *       now.
5240          */
5241         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
5242         if (reset_level != HNS3_NONE_RESET) {
5243                 gettimeofday(&tv_start, NULL);
5244                 ret = hns3_reset_process(hns, reset_level);
5245                 gettimeofday(&tv, NULL);
5246                 timersub(&tv, &tv_start, &tv_delta);
5247                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
5248                        tv_delta.tv_usec / USEC_PER_MSEC;
5249                 if (msec > HNS3_RESET_PROCESS_MS)
5250                         hns3_err(hw, "%d handle long time delta %" PRIx64
5251                                      " ms time=%ld.%.6ld",
5252                                  hw->reset.level, msec,
5253                                  tv.tv_sec, tv.tv_usec);
5254                 if (ret == -EAGAIN)
5255                         return;
5256         }
5257
5258         /* Check if we got any *new* reset requests to be honored */
5259         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5260         if (reset_level != HNS3_NONE_RESET)
5261                 hns3_msix_process(hns, reset_level);
5262 }
5263
5264 static const struct eth_dev_ops hns3_eth_dev_ops = {
5265         .dev_start          = hns3_dev_start,
5266         .dev_stop           = hns3_dev_stop,
5267         .dev_close          = hns3_dev_close,
5268         .promiscuous_enable = hns3_dev_promiscuous_enable,
5269         .promiscuous_disable = hns3_dev_promiscuous_disable,
5270         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5271         .allmulticast_disable = hns3_dev_allmulticast_disable,
5272         .mtu_set            = hns3_dev_mtu_set,
5273         .stats_get          = hns3_stats_get,
5274         .stats_reset        = hns3_stats_reset,
5275         .xstats_get         = hns3_dev_xstats_get,
5276         .xstats_get_names   = hns3_dev_xstats_get_names,
5277         .xstats_reset       = hns3_dev_xstats_reset,
5278         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5279         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5280         .dev_infos_get          = hns3_dev_infos_get,
5281         .fw_version_get         = hns3_fw_version_get,
5282         .rx_queue_setup         = hns3_rx_queue_setup,
5283         .tx_queue_setup         = hns3_tx_queue_setup,
5284         .rx_queue_release       = hns3_dev_rx_queue_release,
5285         .tx_queue_release       = hns3_dev_tx_queue_release,
5286         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5287         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5288         .dev_configure          = hns3_dev_configure,
5289         .flow_ctrl_get          = hns3_flow_ctrl_get,
5290         .flow_ctrl_set          = hns3_flow_ctrl_set,
5291         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5292         .mac_addr_add           = hns3_add_mac_addr,
5293         .mac_addr_remove        = hns3_remove_mac_addr,
5294         .mac_addr_set           = hns3_set_default_mac_addr,
5295         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5296         .link_update            = hns3_dev_link_update,
5297         .rss_hash_update        = hns3_dev_rss_hash_update,
5298         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5299         .reta_update            = hns3_dev_rss_reta_update,
5300         .reta_query             = hns3_dev_rss_reta_query,
5301         .filter_ctrl            = hns3_dev_filter_ctrl,
5302         .vlan_filter_set        = hns3_vlan_filter_set,
5303         .vlan_tpid_set          = hns3_vlan_tpid_set,
5304         .vlan_offload_set       = hns3_vlan_offload_set,
5305         .vlan_pvid_set          = hns3_vlan_pvid_set,
5306         .get_reg                = hns3_get_regs,
5307         .get_dcb_info           = hns3_get_dcb_info,
5308         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5309 };
5310
5311 static const struct hns3_reset_ops hns3_reset_ops = {
5312         .reset_service       = hns3_reset_service,
5313         .stop_service        = hns3_stop_service,
5314         .prepare_reset       = hns3_prepare_reset,
5315         .wait_hardware_ready = hns3_wait_hardware_ready,
5316         .reinit_dev          = hns3_reinit_dev,
5317         .restore_conf        = hns3_restore_conf,
5318         .start_service       = hns3_start_service,
5319 };
5320
5321 static int
5322 hns3_dev_init(struct rte_eth_dev *eth_dev)
5323 {
5324         struct rte_device *dev = eth_dev->device;
5325         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5326         struct hns3_adapter *hns = eth_dev->data->dev_private;
5327         struct hns3_hw *hw = &hns->hw;
5328         uint16_t device_id = pci_dev->id.device_id;
5329         int ret;
5330
5331         PMD_INIT_FUNC_TRACE();
5332         eth_dev->process_private = (struct hns3_process_private *)
5333             rte_zmalloc_socket("hns3_filter_list",
5334                                sizeof(struct hns3_process_private),
5335                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5336         if (eth_dev->process_private == NULL) {
5337                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5338                 return -ENOMEM;
5339         }
5340         /* initialize flow filter lists */
5341         hns3_filterlist_init(eth_dev);
5342
5343         hns3_set_rxtx_function(eth_dev);
5344         eth_dev->dev_ops = &hns3_eth_dev_ops;
5345         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5346                 hns3_mp_init_secondary();
5347                 hw->secondary_cnt++;
5348                 return 0;
5349         }
5350
5351         hns3_mp_init_primary();
5352         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5353
5354         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5355             device_id == HNS3_DEV_ID_50GE_RDMA ||
5356             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5357                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5358
5359         hns->is_vf = false;
5360         hw->data = eth_dev->data;
5361
5362         /*
5363          * Set default max packet size according to the mtu
5364          * default vale in DPDK frame.
5365          */
5366         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5367
5368         ret = hns3_reset_init(hw);
5369         if (ret)
5370                 goto err_init_reset;
5371         hw->reset.ops = &hns3_reset_ops;
5372
5373         ret = hns3_init_pf(eth_dev);
5374         if (ret) {
5375                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5376                 goto err_init_pf;
5377         }
5378
5379         /* Allocate memory for storing MAC addresses */
5380         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5381                                                sizeof(struct rte_ether_addr) *
5382                                                HNS3_UC_MACADDR_NUM, 0);
5383         if (eth_dev->data->mac_addrs == NULL) {
5384                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5385                              "to store MAC addresses",
5386                              sizeof(struct rte_ether_addr) *
5387                              HNS3_UC_MACADDR_NUM);
5388                 ret = -ENOMEM;
5389                 goto err_rte_zmalloc;
5390         }
5391
5392         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5393                             &eth_dev->data->mac_addrs[0]);
5394
5395         hw->adapter_state = HNS3_NIC_INITIALIZED;
5396         /*
5397          * Pass the information to the rte_eth_dev_close() that it should also
5398          * release the private port resources.
5399          */
5400         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5401
5402         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5403                 hns3_err(hw, "Reschedule reset service after dev_init");
5404                 hns3_schedule_reset(hns);
5405         } else {
5406                 /* IMP will wait ready flag before reset */
5407                 hns3_notify_reset_ready(hw, false);
5408         }
5409
5410         hns3_info(hw, "hns3 dev initialization successful!");
5411         return 0;
5412
5413 err_rte_zmalloc:
5414         hns3_uninit_pf(eth_dev);
5415
5416 err_init_pf:
5417         rte_free(hw->reset.wait_data);
5418 err_init_reset:
5419         eth_dev->dev_ops = NULL;
5420         eth_dev->rx_pkt_burst = NULL;
5421         eth_dev->tx_pkt_burst = NULL;
5422         eth_dev->tx_pkt_prepare = NULL;
5423         rte_free(eth_dev->process_private);
5424         eth_dev->process_private = NULL;
5425         return ret;
5426 }
5427
5428 static int
5429 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5430 {
5431         struct hns3_adapter *hns = eth_dev->data->dev_private;
5432         struct hns3_hw *hw = &hns->hw;
5433
5434         PMD_INIT_FUNC_TRACE();
5435
5436         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5437                 return -EPERM;
5438
5439         eth_dev->dev_ops = NULL;
5440         eth_dev->rx_pkt_burst = NULL;
5441         eth_dev->tx_pkt_burst = NULL;
5442         eth_dev->tx_pkt_prepare = NULL;
5443         if (hw->adapter_state < HNS3_NIC_CLOSING)
5444                 hns3_dev_close(eth_dev);
5445
5446         hw->adapter_state = HNS3_NIC_REMOVED;
5447         return 0;
5448 }
5449
5450 static int
5451 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5452                    struct rte_pci_device *pci_dev)
5453 {
5454         return rte_eth_dev_pci_generic_probe(pci_dev,
5455                                              sizeof(struct hns3_adapter),
5456                                              hns3_dev_init);
5457 }
5458
5459 static int
5460 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5461 {
5462         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5463 }
5464
5465 static const struct rte_pci_id pci_id_hns3_map[] = {
5466         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5467         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5468         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5469         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5470         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5471         { .vendor_id = 0, /* sentinel */ },
5472 };
5473
5474 static struct rte_pci_driver rte_hns3_pmd = {
5475         .id_table = pci_id_hns3_map,
5476         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5477         .probe = eth_hns3_pci_probe,
5478         .remove = eth_hns3_pci_remove,
5479 };
5480
5481 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5482 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5483 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5484
5485 RTE_INIT(hns3_init_log)
5486 {
5487         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5488         if (hns3_logtype_init >= 0)
5489                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5490         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5491         if (hns3_logtype_driver >= 0)
5492                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5493 }