drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_OFFSET_160            160
 236         struct hns3_vlan_filter_pf_cfg_cmd *req;
 237         struct hns3_hw *hw = &hns->hw;
 238         uint8_t vlan_offset_byte_val;
 239         struct hns3_cmd_desc desc;
 240         uint8_t vlan_offset_byte;
 241         uint8_t vlan_offset_160;
 242         int ret;
 243
 244         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 245
 246         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 247         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 248         vlan_offset_byte_val = 1 << (vlan_id % 8);
 249
 250         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 251         req->vlan_offset = vlan_offset_160;
 252         req->vlan_cfg = on ? 0 : 1;
 253         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 254
 255         ret = hns3_cmd_send(hw, &desc, 1);
 256         if (ret)
 257                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 258                          vlan_id, ret);
 259
 260         return ret;
 261 }
 262
 263 static void
 264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 265 {
 266         struct hns3_user_vlan_table *vlan_entry;
 267         struct hns3_pf *pf = &hns->pf;
 268
 269         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 270                 if (vlan_entry->vlan_id == vlan_id) {
 271                         if (vlan_entry->hd_tbl_status)
 272                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 273                         LIST_REMOVE(vlan_entry, next);
 274                         rte_free(vlan_entry);
 275                         break;
 276                 }
 277         }
 278 }
 279
 280 static void
 281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 282                         bool writen_to_tbl)
 283 {
 284         struct hns3_user_vlan_table *vlan_entry;
 285         struct hns3_hw *hw = &hns->hw;
 286         struct hns3_pf *pf = &hns->pf;
 287
 288         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 289                 if (vlan_entry->vlan_id == vlan_id)
 290                         return;
 291         }
 292
 293         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 294         if (vlan_entry == NULL) {
 295                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 296                 return;
 297         }
 298
 299         vlan_entry->hd_tbl_status = writen_to_tbl;
 300         vlan_entry->vlan_id = vlan_id;
 301
 302         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 303 }
 304
 305 static int
 306 hns3_restore_vlan_table(struct hns3_adapter *hns)
 307 {
 308         struct hns3_user_vlan_table *vlan_entry;
 309         struct hns3_pf *pf = &hns->pf;
 310         uint16_t vlan_id;
 311         int ret = 0;
 312
 313         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 314                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 315                                                1);
 316                 return ret;
 317         }
 318
 319         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 320                 if (vlan_entry->hd_tbl_status) {
 321                         vlan_id = vlan_entry->vlan_id;
 322                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 323                         if (ret)
 324                                 break;
 325                 }
 326         }
 327
 328         return ret;
 329 }
 330
 331 static int
 332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 333 {
 334         struct hns3_pf *pf = &hns->pf;
 335         bool writen_to_tbl = false;
 336         int ret = 0;
 337
 338         /*
 339          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 340          * for normal packet, deleting vlan id 0 is not allowed.
 341          */
 342         if (on == 0 && vlan_id == 0)
 343                 return 0;
 344
 345         /*
 346          * When port base vlan enabled, we use port base vlan as the vlan
 347          * filter condition. In this case, we don't update vlan filter table
 348          * when user add new vlan or remove exist vlan, just update the
 349          * vlan list. The vlan id in vlan list will be writen in vlan filter
 350          * table until port base vlan disabled
 351          */
 352         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 353                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 354                 writen_to_tbl = true;
 355         }
 356
 357         if (ret == 0 && vlan_id) {
 358                 if (on)
 359                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 360                 else
 361                         hns3_rm_dev_vlan_table(hns, vlan_id);
 362         }
 363         return ret;
 364 }
 365
 366 static int
 367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 368 {
 369         struct hns3_adapter *hns = dev->data->dev_private;
 370         struct hns3_hw *hw = &hns->hw;
 371         int ret;
 372
 373         rte_spinlock_lock(&hw->lock);
 374         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 375         rte_spinlock_unlock(&hw->lock);
 376         return ret;
 377 }
 378
 379 static int
 380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 381                          uint16_t tpid)
 382 {
 383         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 384         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_cmd_desc desc;
 387         int ret;
 388
 389         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 390              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 391                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 392                 return -EINVAL;
 393         }
 394
 395         if (tpid != RTE_ETHER_TYPE_VLAN) {
 396                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 401         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 402
 403         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 407                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 408                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         }
 412
 413         ret = hns3_cmd_send(hw, &desc, 1);
 414         if (ret) {
 415                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 416                          ret);
 417                 return ret;
 418         }
 419
 420         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 421
 422         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 423         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 424         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 425
 426         ret = hns3_cmd_send(hw, &desc, 1);
 427         if (ret)
 428                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 429                          ret);
 430         return ret;
 431 }
 432
 433 static int
 434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 435                    uint16_t tpid)
 436 {
 437         struct hns3_adapter *hns = dev->data->dev_private;
 438         struct hns3_hw *hw = &hns->hw;
 439         int ret;
 440
 441         rte_spinlock_lock(&hw->lock);
 442         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 443         rte_spinlock_unlock(&hw->lock);
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 449                              struct hns3_rx_vtag_cfg *vcfg)
 450 {
 451         struct hns3_vport_vtag_rx_cfg_cmd *req;
 452         struct hns3_hw *hw = &hns->hw;
 453         struct hns3_cmd_desc desc;
 454         uint16_t vport_id;
 455         uint8_t bitmap;
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 459
 460         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 461         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 462                      vcfg->strip_tag1_en ? 1 : 0);
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 464                      vcfg->strip_tag2_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 466                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 468                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 469
 470         /*
 471          * In current version VF is not supported when PF is driven by DPDK
 472          * driver, the PF-related vf_id is 0, just need to configure parameters
 473          * for vport_id 0.
 474          */
 475         vport_id = 0;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_pf *pf = &hns->pf;
 507         struct hns3_hw *hw = &hns->hw;
 508         int ret;
 509
 510         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 511                 rxvlan_cfg.strip_tag1_en = false;
 512                 rxvlan_cfg.strip_tag2_en = enable;
 513         } else {
 514                 rxvlan_cfg.strip_tag1_en = enable;
 515                 rxvlan_cfg.strip_tag2_en = true;
 516         }
 517
 518         rxvlan_cfg.vlan1_vlan_prionly = false;
 519         rxvlan_cfg.vlan2_vlan_prionly = false;
 520         rxvlan_cfg.rx_vlan_offload_en = enable;
 521
 522         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 523         if (ret) {
 524                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 525                 return ret;
 526         }
 527
 528         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 535                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 536 {
 537         struct hns3_vlan_filter_ctrl_cmd *req;
 538         struct hns3_cmd_desc desc;
 539         int ret;
 540
 541         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 542
 543         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 544         req->vlan_type = vlan_type;
 545         req->vlan_fe = filter_en ? fe_type : 0;
 546         req->vf_id = vf_id;
 547
 548         ret = hns3_cmd_send(hw, &desc, 1);
 549         if (ret)
 550                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 551
 552         return ret;
 553 }
 554
 555 static int
 556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 557 {
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 562                                         HNS3_FILTER_FE_EGRESS, false, 0);
 563         if (ret) {
 564                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 570         if (ret)
 571                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 572
 573         return ret;
 574 }
 575
 576 static int
 577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 578 {
 579         struct hns3_adapter *hns = dev->data->dev_private;
 580         struct hns3_hw *hw = &hns->hw;
 581         struct rte_eth_rxmode *rxmode;
 582         unsigned int tmp_mask;
 583         bool enable;
 584         int ret = 0;
 585
 586         rte_spinlock_lock(&hw->lock);
 587         rxmode = &dev->data->dev_conf.rxmode;
 588         tmp_mask = (unsigned int)mask;
 589         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 590                 /* Enable or disable VLAN stripping */
 591                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 592                     true : false;
 593
 594                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 595                 if (ret) {
 596                         rte_spinlock_unlock(&hw->lock);
 597                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 598                         return ret;
 599                 }
 600         }
 601
 602         rte_spinlock_unlock(&hw->lock);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 609                              struct hns3_tx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_vport_vtag_tx_cfg_cmd *req;
 612         struct hns3_cmd_desc desc;
 613         struct hns3_hw *hw = &hns->hw;
 614         uint16_t vport_id;
 615         uint8_t bitmap;
 616         int ret;
 617
 618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 619
 620         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 621         req->def_vlan_tag1 = vcfg->default_tag1;
 622         req->def_vlan_tag2 = vcfg->default_tag2;
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 624                      vcfg->accept_tag1 ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 626                      vcfg->accept_untag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 628                      vcfg->accept_tag2 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 630                      vcfg->accept_untag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 632                      vcfg->insert_tag1_en ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 634                      vcfg->insert_tag2_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 636
 637         /*
 638          * In current version VF is not supported when PF is driven by DPDK
 639          * driver, the PF-related vf_id is 0, just need to configure parameters
 640          * for vport_id 0.
 641          */
 642         vport_id = 0;
 643         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 644         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 645         req->vf_bitmap[req->vf_offset] = bitmap;
 646
 647         ret = hns3_cmd_send(hw, &desc, 1);
 648         if (ret)
 649                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 656                      uint16_t pvid)
 657 {
 658         struct hns3_hw *hw = &hns->hw;
 659         struct hns3_tx_vtag_cfg txvlan_cfg;
 660         int ret;
 661
 662         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 663                 txvlan_cfg.accept_tag1 = true;
 664                 txvlan_cfg.insert_tag1_en = false;
 665                 txvlan_cfg.default_tag1 = 0;
 666         } else {
 667                 txvlan_cfg.accept_tag1 = false;
 668                 txvlan_cfg.insert_tag1_en = true;
 669                 txvlan_cfg.default_tag1 = pvid;
 670         }
 671
 672         txvlan_cfg.accept_untag1 = true;
 673         txvlan_cfg.accept_tag2 = true;
 674         txvlan_cfg.accept_untag2 = true;
 675         txvlan_cfg.insert_tag2_en = false;
 676         txvlan_cfg.default_tag2 = 0;
 677
 678         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 679         if (ret) {
 680                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 681                          ret);
 682                 return ret;
 683         }
 684
 685         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 686         return ret;
 687 }
 688
 689 static void
 690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 691 {
 692         struct hns3_pf *pf = &hns->pf;
 693
 694         pf->port_base_vlan_cfg.state = on ?
 695             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 696
 697         pf->port_base_vlan_cfg.pvid = pvid;
 698 }
 699
 700 static void
 701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 702 {
 703         struct hns3_user_vlan_table *vlan_entry;
 704         struct hns3_pf *pf = &hns->pf;
 705
 706         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 707                 if (vlan_entry->hd_tbl_status)
 708                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 709
 710                 vlan_entry->hd_tbl_status = false;
 711         }
 712
 713         if (is_del_list) {
 714                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 715                 while (vlan_entry) {
 716                         LIST_REMOVE(vlan_entry, next);
 717                         rte_free(vlan_entry);
 718                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 719                 }
 720         }
 721 }
 722
 723 static void
 724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 725 {
 726         struct hns3_user_vlan_table *vlan_entry;
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 730                 if (!vlan_entry->hd_tbl_status)
 731                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 732
 733                 vlan_entry->hd_tbl_status = true;
 734         }
 735 }
 736
 737 static void
 738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         struct hns3_pf *pf = &hns->pf;
 742         int ret;
 743
 744         hns3_rm_all_vlan_table(hns, true);
 745         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 746                 ret = hns3_set_port_vlan_filter(hns,
 747                                                 pf->port_base_vlan_cfg.pvid, 0);
 748                 if (ret) {
 749                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 750                                  ret);
 751                         return;
 752                 }
 753         }
 754 }
 755
 756 static int
 757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 758                                 uint16_t port_base_vlan_state,
 759                                 uint16_t new_pvid, uint16_t old_pvid)
 760 {
 761         struct hns3_pf *pf = &hns->pf;
 762         struct hns3_hw *hw = &hns->hw;
 763         int ret = 0;
 764
 765         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 766                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 767                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 768                         if (ret) {
 769                                 hns3_err(hw,
 770                                          "Failed to clear clear old pvid filter, ret =%d",
 771                                          ret);
 772                                 return ret;
 773                         }
 774                 }
 775
 776                 hns3_rm_all_vlan_table(hns, false);
 777                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 778         }
 779
 780         if (new_pvid != 0) {
 781                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 782                 if (ret) {
 783                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 784                                  ret);
 785                         return ret;
 786                 }
 787         }
 788
 789         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 790                 hns3_add_all_vlan_table(hns);
 791
 792         return ret;
 793 }
 794
 795 static int
 796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 797 {
 798         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 799         struct hns3_hw *hw = &hns->hw;
 800         bool rx_strip_en;
 801         int ret;
 802
 803         rx_strip_en = on ? true : false;
 804         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 805         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 806         rx_vlan_cfg.vlan1_vlan_prionly = false;
 807         rx_vlan_cfg.vlan2_vlan_prionly = false;
 808         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 809
 810         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 811         if (ret) {
 812                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 813                 return ret;
 814         }
 815
 816         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 817         return ret;
 818 }
 819
 820 static int
 821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 822 {
 823         struct hns3_pf *pf = &hns->pf;
 824         struct hns3_hw *hw = &hns->hw;
 825         uint16_t port_base_vlan_state;
 826         uint16_t old_pvid;
 827         int ret;
 828
 829         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 830                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 831                         hns3_warn(hw, "Invalid operation! As current pvid set "
 832                                   "is %u, disable pvid %u is invalid",
 833                                   pf->port_base_vlan_cfg.pvid, pvid);
 834                 return 0;
 835         }
 836
 837         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 838                                     HNS3_PORT_BASE_VLAN_DISABLE;
 839         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 840         if (ret) {
 841                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_en_rx_strip_all(hns, on);
 846         if (ret) {
 847                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         if (pvid == HNS3_INVLID_PVID)
 852                 goto out;
 853         old_pvid = pf->port_base_vlan_cfg.pvid;
 854         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 855                                               old_pvid);
 856         if (ret) {
 857                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 858                          ret);
 859                 return ret;
 860         }
 861
 862 out:
 863         hns3_store_port_base_vlan_info(hns, pvid, on);
 864         return ret;
 865 }
 866
 867 static int
 868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 869 {
 870         struct hns3_adapter *hns = dev->data->dev_private;
 871         struct hns3_hw *hw = &hns->hw;
 872         int ret;
 873
 874         rte_spinlock_lock(&hw->lock);
 875         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 876         rte_spinlock_unlock(&hw->lock);
 877         return ret;
 878 }
 879
 880 static void
 881 init_port_base_vlan_info(struct hns3_hw *hw)
 882 {
 883         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 884         struct hns3_pf *pf = &hns->pf;
 885
 886         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 887         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 888 }
 889
 890 static int
 891 hns3_default_vlan_config(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 897         if (ret)
 898                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 899         return ret;
 900 }
 901
 902 static int
 903 hns3_init_vlan_config(struct hns3_adapter *hns)
 904 {
 905         struct hns3_hw *hw = &hns->hw;
 906         int ret;
 907
 908         /*
 909          * This function can be called in the initialization and reset process,
 910          * when in reset process, it means that hardware had been reseted
 911          * successfully and we need to restore the hardware configuration to
 912          * ensure that the hardware configuration remains unchanged before and
 913          * after reset.
 914          */
 915         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 916                 init_port_base_vlan_info(hw);
 917
 918         ret = hns3_enable_vlan_filter(hns, true);
 919         if (ret) {
 920                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 921                 return ret;
 922         }
 923
 924         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 925                                        RTE_ETHER_TYPE_VLAN);
 926         if (ret) {
 927                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 928                 return ret;
 929         }
 930
 931         /*
 932          * When in the reinit dev stage of the reset process, the following
 933          * vlan-related configurations may differ from those at initialization,
 934          * we will restore configurations to hardware in hns3_restore_vlan_table
 935          * and hns3_restore_vlan_conf later.
 936          */
 937         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 938                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 939                 if (ret) {
 940                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 941                         return ret;
 942                 }
 943
 944                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 945                 if (ret) {
 946                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 947                                  ret);
 948                         return ret;
 949                 }
 950         }
 951
 952         return hns3_default_vlan_config(hns);
 953 }
 954
 955 static int
 956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 957 {
 958         struct hns3_pf *pf = &hns->pf;
 959         struct hns3_hw *hw = &hns->hw;
 960         int ret;
 961
 962         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 963         if (ret) {
 964                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 969         if (ret)
 970                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 977 {
 978         struct hns3_adapter *hns = dev->data->dev_private;
 979         struct rte_eth_dev_data *data = dev->data;
 980         struct rte_eth_txmode *txmode;
 981         struct hns3_hw *hw = &hns->hw;
 982         int ret;
 983
 984         txmode = &data->dev_conf.txmode;
 985         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 986                 hns3_warn(hw,
 987                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 988                           "configuration is not supported! Ignore these two "
 989                           "parameters: hw_vlan_reject_tagged(%d), "
 990                           "hw_vlan_reject_untagged(%d)",
 991                           txmode->hw_vlan_reject_tagged,
 992                           txmode->hw_vlan_reject_untagged);
 993
 994         /* Apply vlan offload setting */
 995         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 996         if (ret) {
 997                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 998                 return ret;
 999         }
1000
1001         /* Apply pvid setting */
1002         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003                                  txmode->hw_vlan_insert_pvid);
1004         if (ret)
1005                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1006                          txmode->pvid, ret);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013                 unsigned int tso_mss_max)
1014 {
1015         struct hns3_cfg_tso_status_cmd *req;
1016         struct hns3_cmd_desc desc;
1017         uint16_t tso_mss;
1018
1019         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1020
1021         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1022
1023         tso_mss = 0;
1024         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1025                        tso_mss_min);
1026         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1027
1028         tso_mss = 0;
1029         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1030                        tso_mss_max);
1031         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1032
1033         return hns3_cmd_send(hw, &desc, 1);
1034 }
1035
1036 int
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1038 {
1039         struct hns3_cfg_gro_status_cmd *req;
1040         struct hns3_cmd_desc desc;
1041         int ret;
1042
1043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1045
1046         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1047
1048         ret = hns3_cmd_send(hw, &desc, 1);
1049         if (ret)
1050                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057                    uint16_t *allocated_size, bool is_alloc)
1058 {
1059         struct hns3_umv_spc_alc_cmd *req;
1060         struct hns3_cmd_desc desc;
1061         int ret;
1062
1063         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066         req->space_size = rte_cpu_to_le_32(space_size);
1067
1068         ret = hns3_cmd_send(hw, &desc, 1);
1069         if (ret) {
1070                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071                              is_alloc ? "allocate" : "free", ret);
1072                 return ret;
1073         }
1074
1075         if (is_alloc && allocated_size)
1076                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_init_umv_space(struct hns3_hw *hw)
1083 {
1084         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085         struct hns3_pf *pf = &hns->pf;
1086         uint16_t allocated_size = 0;
1087         int ret;
1088
1089         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1090                                  true);
1091         if (ret)
1092                 return ret;
1093
1094         if (allocated_size < pf->wanted_umv_size)
1095                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096                              pf->wanted_umv_size, allocated_size);
1097
1098         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099                                                 pf->wanted_umv_size;
1100         pf->used_umv_size = 0;
1101         return 0;
1102 }
1103
1104 static int
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1106 {
1107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108         struct hns3_pf *pf = &hns->pf;
1109         int ret;
1110
1111         if (pf->max_umv_size == 0)
1112                 return 0;
1113
1114         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1115         if (ret)
1116                 return ret;
1117
1118         pf->max_umv_size = 0;
1119
1120         return 0;
1121 }
1122
1123 static bool
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1125 {
1126         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127         struct hns3_pf *pf = &hns->pf;
1128         bool is_full;
1129
1130         is_full = (pf->used_umv_size >= pf->max_umv_size);
1131
1132         return is_full;
1133 }
1134
1135 static void
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1137 {
1138         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139         struct hns3_pf *pf = &hns->pf;
1140
1141         if (is_free) {
1142                 if (pf->used_umv_size > 0)
1143                         pf->used_umv_size--;
1144         } else
1145                 pf->used_umv_size++;
1146 }
1147
1148 static void
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150                       const uint8_t *addr, bool is_mc)
1151 {
1152         const unsigned char *mac_addr = addr;
1153         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154                             ((uint32_t)mac_addr[2] << 16) |
1155                             ((uint32_t)mac_addr[1] << 8) |
1156                             (uint32_t)mac_addr[0];
1157         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1158
1159         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1160         if (is_mc) {
1161                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1164         }
1165
1166         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1168 }
1169
1170 static int
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1172                              uint8_t resp_code,
1173                              enum hns3_mac_vlan_tbl_opcode op)
1174 {
1175         if (cmdq_resp) {
1176                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1177                          cmdq_resp);
1178                 return -EIO;
1179         }
1180
1181         if (op == HNS3_MAC_VLAN_ADD) {
1182                 if (resp_code == 0 || resp_code == 1) {
1183                         return 0;
1184                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185                         hns3_err(hw, "add mac addr failed for uc_overflow");
1186                         return -ENOSPC;
1187                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188                         hns3_err(hw, "add mac addr failed for mc_overflow");
1189                         return -ENOSPC;
1190                 }
1191
1192                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1193                          resp_code);
1194                 return -EIO;
1195         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196                 if (resp_code == 0) {
1197                         return 0;
1198                 } else if (resp_code == 1) {
1199                         hns3_dbg(hw, "remove mac addr failed for miss");
1200                         return -ENOENT;
1201                 }
1202
1203                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_LKUP) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "lookup mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         }
1218
1219         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1220                  op);
1221
1222         return -EINVAL;
1223 }
1224
1225 static int
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1228                          struct hns3_cmd_desc *desc, bool is_mc)
1229 {
1230         uint8_t resp_code;
1231         uint16_t retval;
1232         int ret;
1233
1234         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1235         if (is_mc) {
1236                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237                 memcpy(desc[0].data, req,
1238                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1240                                           true);
1241                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1243                                           true);
1244                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1245         } else {
1246                 memcpy(desc[0].data, req,
1247                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248                 ret = hns3_cmd_send(hw, desc, 1);
1249         }
1250         if (ret) {
1251                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1252                          ret);
1253                 return ret;
1254         }
1255         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256         retval = rte_le_to_cpu_16(desc[0].retval);
1257
1258         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259                                             HNS3_MAC_VLAN_LKUP);
1260 }
1261
1262 static int
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1265                       struct hns3_cmd_desc *mc_desc)
1266 {
1267         uint8_t resp_code;
1268         uint16_t retval;
1269         int cfg_status;
1270         int ret;
1271
1272         if (mc_desc == NULL) {
1273                 struct hns3_cmd_desc desc;
1274
1275                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276                 memcpy(desc.data, req,
1277                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278                 ret = hns3_cmd_send(hw, &desc, 1);
1279                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280                 retval = rte_le_to_cpu_16(desc.retval);
1281
1282                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1283                                                           HNS3_MAC_VLAN_ADD);
1284         } else {
1285                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291                 memcpy(mc_desc[0].data, req,
1292                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293                 mc_desc[0].retval = 0;
1294                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1297
1298                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1299                                                           HNS3_MAC_VLAN_ADD);
1300         }
1301
1302         if (ret) {
1303                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1304                 return ret;
1305         }
1306
1307         return cfg_status;
1308 }
1309
1310 static int
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1313 {
1314         struct hns3_cmd_desc desc;
1315         uint8_t resp_code;
1316         uint16_t retval;
1317         int ret;
1318
1319         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1320
1321         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322
1323         ret = hns3_cmd_send(hw, &desc, 1);
1324         if (ret) {
1325                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1326                 return ret;
1327         }
1328         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329         retval = rte_le_to_cpu_16(desc.retval);
1330
1331         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332                                             HNS3_MAC_VLAN_REMOVE);
1333 }
1334
1335 static int
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1337 {
1338         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339         struct hns3_mac_vlan_tbl_entry_cmd req;
1340         struct hns3_pf *pf = &hns->pf;
1341         struct hns3_cmd_desc desc;
1342         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343         uint16_t egress_port = 0;
1344         uint8_t vf_id;
1345         int ret;
1346
1347         /* check if mac addr is valid */
1348         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1350                                       mac_addr);
1351                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1352                          mac_str);
1353                 return -EINVAL;
1354         }
1355
1356         memset(&req, 0, sizeof(req));
1357
1358         /*
1359          * In current version VF is not supported when PF is driven by DPDK
1360          * driver, the PF-related vf_id is 0, just need to configure parameters
1361          * for vf_id 0.
1362          */
1363         vf_id = 0;
1364         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365                        HNS3_MAC_EPORT_VFID_S, vf_id);
1366
1367         req.egress_port = rte_cpu_to_le_16(egress_port);
1368
1369         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1370
1371         /*
1372          * Lookup the mac address in the mac_vlan table, and add
1373          * it if the entry is inexistent. Repeated unicast entry
1374          * is not allowed in the mac vlan table.
1375          */
1376         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377         if (ret == -ENOENT) {
1378                 if (!hns3_is_umv_space_full(hw)) {
1379                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1380                         if (!ret)
1381                                 hns3_update_umv_space(hw, false);
1382                         return ret;
1383                 }
1384
1385                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1386
1387                 return -ENOSPC;
1388         }
1389
1390         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1391
1392         /* check if we just hit the duplicate */
1393         if (ret == 0) {
1394                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1395                 return 0;
1396         }
1397
1398         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1399                  mac_str);
1400
1401         return ret;
1402 }
1403
1404 static int
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1407 {
1408         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1410         int ret;
1411
1412         rte_spinlock_lock(&hw->lock);
1413         ret = hns3_add_uc_addr_common(hw, mac_addr);
1414         if (ret) {
1415                 rte_spinlock_unlock(&hw->lock);
1416                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1417                                       mac_addr);
1418                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1419                 return ret;
1420         }
1421
1422         if (idx == 0)
1423                 hw->mac.default_addr_setted = true;
1424         rte_spinlock_unlock(&hw->lock);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1431 {
1432         struct hns3_mac_vlan_tbl_entry_cmd req;
1433         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1434         int ret;
1435
1436         /* check if mac addr is valid */
1437         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1441                          mac_str);
1442                 return -EINVAL;
1443         }
1444
1445         memset(&req, 0, sizeof(req));
1446         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1450                 return 0;
1451         else if (ret == 0)
1452                 hns3_update_umv_space(hw, true);
1453
1454         return ret;
1455 }
1456
1457 static void
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1459 {
1460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         /* index will be checked by upper level rte interface */
1462         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464         int ret;
1465
1466         rte_spinlock_lock(&hw->lock);
1467         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1468         if (ret) {
1469                 rte_spinlock_unlock(&hw->lock);
1470                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1471                                       mac_addr);
1472                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1473                 return;
1474         }
1475
1476         rte_spinlock_unlock(&hw->lock);
1477 }
1478
1479 static int
1480 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1481                           struct rte_ether_addr *mac_addr)
1482 {
1483         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         struct rte_ether_addr *oaddr;
1485         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1486         bool default_addr_setted;
1487         bool rm_succes = false;
1488         int ret, ret_val;
1489
1490         /* check if mac addr is valid */
1491         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1492                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1493                                       mac_addr);
1494                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1495                          mac_str);
1496                 return -EINVAL;
1497         }
1498
1499         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1500         default_addr_setted = hw->mac.default_addr_setted;
1501         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1502                 return 0;
1503
1504         rte_spinlock_lock(&hw->lock);
1505         if (default_addr_setted) {
1506                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1507                 if (ret) {
1508                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1509                                               oaddr);
1510                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1511                                   mac_str, ret);
1512                         rm_succes = false;
1513                 } else
1514                         rm_succes = true;
1515         }
1516
1517         ret = hns3_add_uc_addr_common(hw, mac_addr);
1518         if (ret) {
1519                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1520                                       mac_addr);
1521                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1522                 goto err_add_uc_addr;
1523         }
1524
1525         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1526         if (ret) {
1527                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1528                 goto err_pause_addr_cfg;
1529         }
1530
1531         rte_ether_addr_copy(mac_addr,
1532                             (struct rte_ether_addr *)hw->mac.mac_addr);
1533         hw->mac.default_addr_setted = true;
1534         rte_spinlock_unlock(&hw->lock);
1535
1536         return 0;
1537
1538 err_pause_addr_cfg:
1539         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1540         if (ret_val) {
1541                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1542                                       mac_addr);
1543                 hns3_warn(hw,
1544                           "Failed to roll back to del setted mac addr(%s): %d",
1545                           mac_str, ret_val);
1546         }
1547
1548 err_add_uc_addr:
1549         if (rm_succes) {
1550                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1551                 if (ret_val) {
1552                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1553                                               oaddr);
1554                         hns3_warn(hw,
1555                                   "Failed to restore old uc mac addr(%s): %d",
1556                                   mac_str, ret_val);
1557                         hw->mac.default_addr_setted = false;
1558                 }
1559         }
1560         rte_spinlock_unlock(&hw->lock);
1561
1562         return ret;
1563 }
1564
1565 static int
1566 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1567 {
1568         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1569         struct hns3_hw *hw = &hns->hw;
1570         struct rte_ether_addr *addr;
1571         int err = 0;
1572         int ret;
1573         int i;
1574
1575         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1576                 addr = &hw->data->mac_addrs[i];
1577                 if (!rte_is_valid_assigned_ether_addr(addr))
1578                         continue;
1579                 if (del)
1580                         ret = hns3_remove_uc_addr_common(hw, addr);
1581                 else
1582                         ret = hns3_add_uc_addr_common(hw, addr);
1583                 if (ret) {
1584                         err = ret;
1585                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1586                                               addr);
1587                         hns3_dbg(hw,
1588                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1589                                  del ? "remove" : "restore", mac_str, ret, i);
1590                 }
1591         }
1592         return err;
1593 }
1594
1595 static void
1596 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1597 {
1598 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1599         uint8_t word_num;
1600         uint8_t bit_num;
1601
1602         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1603                 word_num = vfid / 32;
1604                 bit_num = vfid % 32;
1605                 if (clr)
1606                         desc[1].data[word_num] &=
1607                             rte_cpu_to_le_32(~(1UL << bit_num));
1608                 else
1609                         desc[1].data[word_num] |=
1610                             rte_cpu_to_le_32(1UL << bit_num);
1611         } else {
1612                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1613                 bit_num = vfid % 32;
1614                 if (clr)
1615                         desc[2].data[word_num] &=
1616                             rte_cpu_to_le_32(~(1UL << bit_num));
1617                 else
1618                         desc[2].data[word_num] |=
1619                             rte_cpu_to_le_32(1UL << bit_num);
1620         }
1621 }
1622
1623 static int
1624 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1625 {
1626         struct hns3_mac_vlan_tbl_entry_cmd req;
1627         struct hns3_cmd_desc desc[3];
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         uint8_t vf_id;
1630         int ret;
1631
1632         /* Check if mac addr is valid */
1633         if (!rte_is_multicast_ether_addr(mac_addr)) {
1634                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1635                                       mac_addr);
1636                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1637                          mac_str);
1638                 return -EINVAL;
1639         }
1640
1641         memset(&req, 0, sizeof(req));
1642         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1643         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1644         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1645         if (ret) {
1646                 /* This mac addr do not exist, add new entry for it */
1647                 memset(desc[0].data, 0, sizeof(desc[0].data));
1648                 memset(desc[1].data, 0, sizeof(desc[0].data));
1649                 memset(desc[2].data, 0, sizeof(desc[0].data));
1650         }
1651
1652         /*
1653          * In current version VF is not supported when PF is driven by DPDK
1654          * driver, the PF-related vf_id is 0, just need to configure parameters
1655          * for vf_id 0.
1656          */
1657         vf_id = 0;
1658         hns3_update_desc_vfid(desc, vf_id, false);
1659         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1660         if (ret) {
1661                 if (ret == -ENOSPC)
1662                         hns3_err(hw, "mc mac vlan table is full");
1663                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1664                                       mac_addr);
1665                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1666         }
1667
1668         return ret;
1669 }
1670
1671 static int
1672 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1673 {
1674         struct hns3_mac_vlan_tbl_entry_cmd req;
1675         struct hns3_cmd_desc desc[3];
1676         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1677         uint8_t vf_id;
1678         int ret;
1679
1680         /* Check if mac addr is valid */
1681         if (!rte_is_multicast_ether_addr(mac_addr)) {
1682                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1683                                       mac_addr);
1684                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1685                          mac_str);
1686                 return -EINVAL;
1687         }
1688
1689         memset(&req, 0, sizeof(req));
1690         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1691         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1692         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1693         if (ret == 0) {
1694                 /*
1695                  * This mac addr exist, remove this handle's VFID for it.
1696                  * In current version VF is not supported when PF is driven by
1697                  * DPDK driver, the PF-related vf_id is 0, just need to
1698                  * configure parameters for vf_id 0.
1699                  */
1700                 vf_id = 0;
1701                 hns3_update_desc_vfid(desc, vf_id, true);
1702
1703                 /* All the vfid is zero, so need to delete this entry */
1704                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1705         } else if (ret == -ENOENT) {
1706                 /* This mac addr doesn't exist. */
1707                 return 0;
1708         }
1709
1710         if (ret) {
1711                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1714         }
1715
1716         return ret;
1717 }
1718
1719 static int
1720 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1721                            struct rte_ether_addr *mc_addr_set,
1722                            uint32_t nb_mc_addr)
1723 {
1724         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1725         struct rte_ether_addr *addr;
1726         uint32_t i;
1727         uint32_t j;
1728
1729         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1730                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1731                          "invalid. valid range: 0~%d",
1732                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1733                 return -EINVAL;
1734         }
1735
1736         /* Check if input mac addresses are valid */
1737         for (i = 0; i < nb_mc_addr; i++) {
1738                 addr = &mc_addr_set[i];
1739                 if (!rte_is_multicast_ether_addr(addr)) {
1740                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1741                                               addr);
1742                         hns3_err(hw,
1743                                  "Failed to set mc mac addr, addr(%s) invalid.",
1744                                  mac_str);
1745                         return -EINVAL;
1746                 }
1747
1748                 /* Check if there are duplicate addresses */
1749                 for (j = i + 1; j < nb_mc_addr; j++) {
1750                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1751                                 rte_ether_format_addr(mac_str,
1752                                                       RTE_ETHER_ADDR_FMT_SIZE,
1753                                                       addr);
1754                                 hns3_err(hw, "Failed to set mc mac addr, "
1755                                          "addrs invalid. two same addrs(%s).",
1756                                          mac_str);
1757                                 return -EINVAL;
1758                         }
1759                 }
1760         }
1761
1762         return 0;
1763 }
1764
1765 static void
1766 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1767                            struct rte_ether_addr *mc_addr_set,
1768                            int mc_addr_num,
1769                            struct rte_ether_addr *reserved_addr_list,
1770                            int *reserved_addr_num,
1771                            struct rte_ether_addr *add_addr_list,
1772                            int *add_addr_num,
1773                            struct rte_ether_addr *rm_addr_list,
1774                            int *rm_addr_num)
1775 {
1776         struct rte_ether_addr *addr;
1777         int current_addr_num;
1778         int reserved_num = 0;
1779         int add_num = 0;
1780         int rm_num = 0;
1781         int num;
1782         int i;
1783         int j;
1784         bool same_addr;
1785
1786         /* Calculate the mc mac address list that should be removed */
1787         current_addr_num = hw->mc_addrs_num;
1788         for (i = 0; i < current_addr_num; i++) {
1789                 addr = &hw->mc_addrs[i];
1790                 same_addr = false;
1791                 for (j = 0; j < mc_addr_num; j++) {
1792                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1793                                 same_addr = true;
1794                                 break;
1795                         }
1796                 }
1797
1798                 if (!same_addr) {
1799                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1800                         rm_num++;
1801                 } else {
1802                         rte_ether_addr_copy(addr,
1803                                             &reserved_addr_list[reserved_num]);
1804                         reserved_num++;
1805                 }
1806         }
1807
1808         /* Calculate the mc mac address list that should be added */
1809         for (i = 0; i < mc_addr_num; i++) {
1810                 addr = &mc_addr_set[i];
1811                 same_addr = false;
1812                 for (j = 0; j < current_addr_num; j++) {
1813                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1814                                 same_addr = true;
1815                                 break;
1816                         }
1817                 }
1818
1819                 if (!same_addr) {
1820                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1821                         add_num++;
1822                 }
1823         }
1824
1825         /* Reorder the mc mac address list maintained by driver */
1826         for (i = 0; i < reserved_num; i++)
1827                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1828
1829         for (i = 0; i < rm_num; i++) {
1830                 num = reserved_num + i;
1831                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1832         }
1833
1834         *reserved_addr_num = reserved_num;
1835         *add_addr_num = add_num;
1836         *rm_addr_num = rm_num;
1837 }
1838
1839 static int
1840 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1841                           struct rte_ether_addr *mc_addr_set,
1842                           uint32_t nb_mc_addr)
1843 {
1844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1846         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1847         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1848         struct rte_ether_addr *addr;
1849         int reserved_addr_num;
1850         int add_addr_num;
1851         int rm_addr_num;
1852         int mc_addr_num;
1853         int num;
1854         int ret;
1855         int i;
1856
1857         /* Check if input parameters are valid */
1858         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1859         if (ret)
1860                 return ret;
1861
1862         rte_spinlock_lock(&hw->lock);
1863
1864         /*
1865          * Calculate the mc mac address lists those should be removed and be
1866          * added, Reorder the mc mac address list maintained by driver.
1867          */
1868         mc_addr_num = (int)nb_mc_addr;
1869         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1870                                    reserved_addr_list, &reserved_addr_num,
1871                                    add_addr_list, &add_addr_num,
1872                                    rm_addr_list, &rm_addr_num);
1873
1874         /* Remove mc mac addresses */
1875         for (i = 0; i < rm_addr_num; i++) {
1876                 num = rm_addr_num - i - 1;
1877                 addr = &rm_addr_list[num];
1878                 ret = hns3_remove_mc_addr(hw, addr);
1879                 if (ret) {
1880                         rte_spinlock_unlock(&hw->lock);
1881                         return ret;
1882                 }
1883                 hw->mc_addrs_num--;
1884         }
1885
1886         /* Add mc mac addresses */
1887         for (i = 0; i < add_addr_num; i++) {
1888                 addr = &add_addr_list[i];
1889                 ret = hns3_add_mc_addr(hw, addr);
1890                 if (ret) {
1891                         rte_spinlock_unlock(&hw->lock);
1892                         return ret;
1893                 }
1894
1895                 num = reserved_addr_num + i;
1896                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1897                 hw->mc_addrs_num++;
1898         }
1899         rte_spinlock_unlock(&hw->lock);
1900
1901         return 0;
1902 }
1903
1904 static int
1905 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1906 {
1907         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1908         struct hns3_hw *hw = &hns->hw;
1909         struct rte_ether_addr *addr;
1910         int err = 0;
1911         int ret;
1912         int i;
1913
1914         for (i = 0; i < hw->mc_addrs_num; i++) {
1915                 addr = &hw->mc_addrs[i];
1916                 if (!rte_is_multicast_ether_addr(addr))
1917                         continue;
1918                 if (del)
1919                         ret = hns3_remove_mc_addr(hw, addr);
1920                 else
1921                         ret = hns3_add_mc_addr(hw, addr);
1922                 if (ret) {
1923                         err = ret;
1924                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1925                                               addr);
1926                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1927                                  del ? "Remove" : "Restore", mac_str);
1928                 }
1929         }
1930         return err;
1931 }
1932
1933 static int
1934 hns3_check_mq_mode(struct rte_eth_dev *dev)
1935 {
1936         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1937         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1938         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1941         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1942         uint8_t num_tc;
1943         int max_tc = 0;
1944         int i;
1945
1946         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1947         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1948
1949         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1950                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1951                          "rx_mq_mode = %d", rx_mq_mode);
1952                 return -EINVAL;
1953         }
1954
1955         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1956             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1957                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1958                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1959                          rx_mq_mode, tx_mq_mode);
1960                 return -EINVAL;
1961         }
1962
1963         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1964                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1965                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1966                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1967                         return -EINVAL;
1968                 }
1969
1970                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1971                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1972                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1973                                  "nb_tcs(%d) != %d or %d in rx direction.",
1974                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1975                         return -EINVAL;
1976                 }
1977
1978                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1979                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1980                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1981                         return -EINVAL;
1982                 }
1983
1984                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1985                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1986                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1987                                          "is not equal to one in tx direction.",
1988                                          i, dcb_rx_conf->dcb_tc[i]);
1989                                 return -EINVAL;
1990                         }
1991                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1992                                 max_tc = dcb_rx_conf->dcb_tc[i];
1993                 }
1994
1995                 num_tc = max_tc + 1;
1996                 if (num_tc > dcb_rx_conf->nb_tcs) {
1997                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1998                                  num_tc, dcb_rx_conf->nb_tcs);
1999                         return -EINVAL;
2000                 }
2001         }
2002
2003         return 0;
2004 }
2005
2006 static int
2007 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2008 {
2009         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010
2011         if (!hns3_dev_dcb_supported(hw)) {
2012                 hns3_err(hw, "this port does not support dcb configurations.");
2013                 return -EOPNOTSUPP;
2014         }
2015
2016         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2017                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2018                 return -EOPNOTSUPP;
2019         }
2020
2021         /* Check multiple queue mode */
2022         return hns3_check_mq_mode(dev);
2023 }
2024
2025 static int
2026 hns3_bind_ring_with_vector(struct rte_eth_dev *dev, uint8_t vector_id,
2027                            bool mmap, uint16_t queue_id)
2028 {
2029         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         struct hns3_cmd_desc desc;
2031         struct hns3_ctrl_vector_chain_cmd *req =
2032                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2033         enum hns3_cmd_status status;
2034         enum hns3_opcode_type op;
2035         uint16_t tqp_type_and_id = 0;
2036
2037         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2038         hns3_cmd_setup_basic_desc(&desc, op, false);
2039         req->int_vector_id = vector_id;
2040
2041         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2042                        HNS3_RING_TYPE_RX);
2043         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2044         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2045                        HNS3_RING_GL_RX);
2046         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2047
2048         req->int_cause_num = 1;
2049         status = hns3_cmd_send(hw, &desc, 1);
2050         if (status) {
2051                 hns3_err(hw, "Map TQP %d fail, vector_id is %d, status is %d.",
2052                          queue_id, vector_id, status);
2053                 return -EIO;
2054         }
2055
2056         return 0;
2057 }
2058
2059 static int
2060 hns3_dev_configure(struct rte_eth_dev *dev)
2061 {
2062         struct hns3_adapter *hns = dev->data->dev_private;
2063         struct rte_eth_conf *conf = &dev->data->dev_conf;
2064         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2065         struct hns3_hw *hw = &hns->hw;
2066         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2067         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2068         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2069         struct rte_eth_rss_conf rss_conf;
2070         uint16_t mtu;
2071         int ret;
2072
2073         /*
2074          * Hardware does not support individually enable/disable/reset the Tx or
2075          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2076          * and Rx queues at the same time. When the numbers of Tx queues
2077          * allocated by upper applications are not equal to the numbers of Rx
2078          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2079          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2080          * these fake queues are imperceptible, and can not be used by upper
2081          * applications.
2082          */
2083         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2084         if (ret) {
2085                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2086                 return ret;
2087         }
2088
2089         hw->adapter_state = HNS3_NIC_CONFIGURING;
2090         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2091                 hns3_err(hw, "setting link speed/duplex not supported");
2092                 ret = -EINVAL;
2093                 goto cfg_err;
2094         }
2095
2096         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2097                 ret = hns3_check_dcb_cfg(dev);
2098                 if (ret)
2099                         goto cfg_err;
2100         }
2101
2102         /* When RSS is not configured, redirect the packet queue 0 */
2103         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2104                 rss_conf = conf->rx_adv_conf.rss_conf;
2105                 if (rss_conf.rss_key == NULL) {
2106                         rss_conf.rss_key = rss_cfg->key;
2107                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2108                 }
2109
2110                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2111                 if (ret)
2112                         goto cfg_err;
2113         }
2114
2115         /*
2116          * If jumbo frames are enabled, MTU needs to be refreshed
2117          * according to the maximum RX packet length.
2118          */
2119         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2120                 /*
2121                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2122                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2123                  * can safely assign to "uint16_t" type variable.
2124                  */
2125                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2126                 ret = hns3_dev_mtu_set(dev, mtu);
2127                 if (ret)
2128                         goto cfg_err;
2129                 dev->data->mtu = mtu;
2130         }
2131
2132         ret = hns3_dev_configure_vlan(dev);
2133         if (ret)
2134                 goto cfg_err;
2135
2136         hw->adapter_state = HNS3_NIC_CONFIGURED;
2137
2138         return 0;
2139
2140 cfg_err:
2141         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2142         hw->adapter_state = HNS3_NIC_INITIALIZED;
2143
2144         return ret;
2145 }
2146
2147 static int
2148 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2149 {
2150         struct hns3_config_max_frm_size_cmd *req;
2151         struct hns3_cmd_desc desc;
2152
2153         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2154
2155         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2156         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2157         req->min_frm_size = RTE_ETHER_MIN_LEN;
2158
2159         return hns3_cmd_send(hw, &desc, 1);
2160 }
2161
2162 static int
2163 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2164 {
2165         int ret;
2166
2167         ret = hns3_set_mac_mtu(hw, mps);
2168         if (ret) {
2169                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2170                 return ret;
2171         }
2172
2173         ret = hns3_buffer_alloc(hw);
2174         if (ret) {
2175                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2176                 return ret;
2177         }
2178
2179         return 0;
2180 }
2181
2182 static int
2183 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2184 {
2185         struct hns3_adapter *hns = dev->data->dev_private;
2186         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2187         struct hns3_hw *hw = &hns->hw;
2188         bool is_jumbo_frame;
2189         int ret;
2190
2191         if (dev->data->dev_started) {
2192                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2193                          "before configuration", dev->data->port_id);
2194                 return -EBUSY;
2195         }
2196
2197         rte_spinlock_lock(&hw->lock);
2198         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2199         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2200
2201         /*
2202          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2203          * assign to "uint16_t" type variable.
2204          */
2205         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2206         if (ret) {
2207                 rte_spinlock_unlock(&hw->lock);
2208                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2209                          dev->data->port_id, mtu, ret);
2210                 return ret;
2211         }
2212         hns->pf.mps = (uint16_t)frame_size;
2213         if (is_jumbo_frame)
2214                 dev->data->dev_conf.rxmode.offloads |=
2215                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2216         else
2217                 dev->data->dev_conf.rxmode.offloads &=
2218                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2219         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2220         rte_spinlock_unlock(&hw->lock);
2221
2222         return 0;
2223 }
2224
2225 static int
2226 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2227 {
2228         struct hns3_adapter *hns = eth_dev->data->dev_private;
2229         struct hns3_hw *hw = &hns->hw;
2230
2231         info->max_rx_queues = hw->tqps_num;
2232         info->max_tx_queues = hw->tqps_num;
2233         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2234         info->min_rx_bufsize = hw->rx_buf_len;
2235         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2236         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2237         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2238                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2239                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2240                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2241                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2242                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2243                                  DEV_RX_OFFLOAD_KEEP_CRC |
2244                                  DEV_RX_OFFLOAD_SCATTER |
2245                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2246                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2247                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2248                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2249                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2250         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2251         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2252                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2253                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2254                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2255                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2256                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2257                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2258                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2259                                  DEV_TX_OFFLOAD_TCP_TSO |
2260                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2261                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2262                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2263                                  info->tx_queue_offload_capa);
2264
2265         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2266                 .nb_max = HNS3_MAX_RING_DESC,
2267                 .nb_min = HNS3_MIN_RING_DESC,
2268                 .nb_align = HNS3_ALIGN_RING_DESC,
2269         };
2270
2271         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2272                 .nb_max = HNS3_MAX_RING_DESC,
2273                 .nb_min = HNS3_MIN_RING_DESC,
2274                 .nb_align = HNS3_ALIGN_RING_DESC,
2275         };
2276
2277         info->vmdq_queue_num = 0;
2278
2279         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2280         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2281         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2282
2283         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2284         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2285         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2286         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2287         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2288         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2289
2290         return 0;
2291 }
2292
2293 static int
2294 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2295                     size_t fw_size)
2296 {
2297         struct hns3_adapter *hns = eth_dev->data->dev_private;
2298         struct hns3_hw *hw = &hns->hw;
2299         int ret;
2300
2301         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2302         ret += 1; /* add the size of '\0' */
2303         if (fw_size < (uint32_t)ret)
2304                 return ret;
2305         else
2306                 return 0;
2307 }
2308
2309 static int
2310 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2311                      __rte_unused int wait_to_complete)
2312 {
2313         struct hns3_adapter *hns = eth_dev->data->dev_private;
2314         struct hns3_hw *hw = &hns->hw;
2315         struct hns3_mac *mac = &hw->mac;
2316         struct rte_eth_link new_link;
2317
2318         if (!hns3_is_reset_pending(hns)) {
2319                 hns3_update_speed_duplex(eth_dev);
2320                 hns3_update_link_status(hw);
2321         }
2322
2323         memset(&new_link, 0, sizeof(new_link));
2324         switch (mac->link_speed) {
2325         case ETH_SPEED_NUM_10M:
2326         case ETH_SPEED_NUM_100M:
2327         case ETH_SPEED_NUM_1G:
2328         case ETH_SPEED_NUM_10G:
2329         case ETH_SPEED_NUM_25G:
2330         case ETH_SPEED_NUM_40G:
2331         case ETH_SPEED_NUM_50G:
2332         case ETH_SPEED_NUM_100G:
2333                 new_link.link_speed = mac->link_speed;
2334                 break;
2335         default:
2336                 new_link.link_speed = ETH_SPEED_NUM_100M;
2337                 break;
2338         }
2339
2340         new_link.link_duplex = mac->link_duplex;
2341         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2342         new_link.link_autoneg =
2343             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2344
2345         return rte_eth_linkstatus_set(eth_dev, &new_link);
2346 }
2347
2348 static int
2349 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2350 {
2351         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2352         struct hns3_pf *pf = &hns->pf;
2353
2354         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2355                 return -EINVAL;
2356
2357         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2358
2359         return 0;
2360 }
2361
2362 static int
2363 hns3_query_function_status(struct hns3_hw *hw)
2364 {
2365 #define HNS3_QUERY_MAX_CNT              10
2366 #define HNS3_QUERY_SLEEP_MSCOEND        1
2367         struct hns3_func_status_cmd *req;
2368         struct hns3_cmd_desc desc;
2369         int timeout = 0;
2370         int ret;
2371
2372         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2373         req = (struct hns3_func_status_cmd *)desc.data;
2374
2375         do {
2376                 ret = hns3_cmd_send(hw, &desc, 1);
2377                 if (ret) {
2378                         PMD_INIT_LOG(ERR, "query function status failed %d",
2379                                      ret);
2380                         return ret;
2381                 }
2382
2383                 /* Check pf reset is done */
2384                 if (req->pf_state)
2385                         break;
2386
2387                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2388         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2389
2390         return hns3_parse_func_status(hw, req);
2391 }
2392
2393 static int
2394 hns3_query_pf_resource(struct hns3_hw *hw)
2395 {
2396         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2397         struct hns3_pf *pf = &hns->pf;
2398         struct hns3_pf_res_cmd *req;
2399         struct hns3_cmd_desc desc;
2400         int ret;
2401
2402         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2403         ret = hns3_cmd_send(hw, &desc, 1);
2404         if (ret) {
2405                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2406                 return ret;
2407         }
2408
2409         req = (struct hns3_pf_res_cmd *)desc.data;
2410         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2411         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2412         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2413         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2414
2415         if (req->tx_buf_size)
2416                 pf->tx_buf_size =
2417                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2418         else
2419                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2420
2421         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2422
2423         if (req->dv_buf_size)
2424                 pf->dv_buf_size =
2425                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2426         else
2427                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2428
2429         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2430
2431         hw->num_msi =
2432             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2433                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2434
2435         return 0;
2436 }
2437
2438 static void
2439 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2440 {
2441         struct hns3_cfg_param_cmd *req;
2442         uint64_t mac_addr_tmp_high;
2443         uint64_t mac_addr_tmp;
2444         uint32_t i;
2445
2446         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2447
2448         /* get the configuration */
2449         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2450                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2451         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2452                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2453         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2454                                            HNS3_CFG_TQP_DESC_N_M,
2455                                            HNS3_CFG_TQP_DESC_N_S);
2456
2457         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2458                                        HNS3_CFG_PHY_ADDR_M,
2459                                        HNS3_CFG_PHY_ADDR_S);
2460         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2461                                          HNS3_CFG_MEDIA_TP_M,
2462                                          HNS3_CFG_MEDIA_TP_S);
2463         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2464                                          HNS3_CFG_RX_BUF_LEN_M,
2465                                          HNS3_CFG_RX_BUF_LEN_S);
2466         /* get mac address */
2467         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2468         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2469                                            HNS3_CFG_MAC_ADDR_H_M,
2470                                            HNS3_CFG_MAC_ADDR_H_S);
2471
2472         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2473
2474         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2475                                             HNS3_CFG_DEFAULT_SPEED_M,
2476                                             HNS3_CFG_DEFAULT_SPEED_S);
2477         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2478                                            HNS3_CFG_RSS_SIZE_M,
2479                                            HNS3_CFG_RSS_SIZE_S);
2480
2481         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2482                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2483
2484         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2485         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2486
2487         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2488                                             HNS3_CFG_SPEED_ABILITY_M,
2489                                             HNS3_CFG_SPEED_ABILITY_S);
2490         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2491                                         HNS3_CFG_UMV_TBL_SPACE_M,
2492                                         HNS3_CFG_UMV_TBL_SPACE_S);
2493         if (!cfg->umv_space)
2494                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2495 }
2496
2497 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2498  * @hw: pointer to struct hns3_hw
2499  * @hcfg: the config structure to be getted
2500  */
2501 static int
2502 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2503 {
2504         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2505         struct hns3_cfg_param_cmd *req;
2506         uint32_t offset;
2507         uint32_t i;
2508         int ret;
2509
2510         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2511                 offset = 0;
2512                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2513                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2514                                           true);
2515                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2516                                i * HNS3_CFG_RD_LEN_BYTES);
2517                 /* Len should be divided by 4 when send to hardware */
2518                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2519                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2520                 req->offset = rte_cpu_to_le_32(offset);
2521         }
2522
2523         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2524         if (ret) {
2525                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2526                 return ret;
2527         }
2528
2529         hns3_parse_cfg(hcfg, desc);
2530
2531         return 0;
2532 }
2533
2534 static int
2535 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2536 {
2537         switch (speed_cmd) {
2538         case HNS3_CFG_SPEED_10M:
2539                 *speed = ETH_SPEED_NUM_10M;
2540                 break;
2541         case HNS3_CFG_SPEED_100M:
2542                 *speed = ETH_SPEED_NUM_100M;
2543                 break;
2544         case HNS3_CFG_SPEED_1G:
2545                 *speed = ETH_SPEED_NUM_1G;
2546                 break;
2547         case HNS3_CFG_SPEED_10G:
2548                 *speed = ETH_SPEED_NUM_10G;
2549                 break;
2550         case HNS3_CFG_SPEED_25G:
2551                 *speed = ETH_SPEED_NUM_25G;
2552                 break;
2553         case HNS3_CFG_SPEED_40G:
2554                 *speed = ETH_SPEED_NUM_40G;
2555                 break;
2556         case HNS3_CFG_SPEED_50G:
2557                 *speed = ETH_SPEED_NUM_50G;
2558                 break;
2559         case HNS3_CFG_SPEED_100G:
2560                 *speed = ETH_SPEED_NUM_100G;
2561                 break;
2562         default:
2563                 return -EINVAL;
2564         }
2565
2566         return 0;
2567 }
2568
2569 static int
2570 hns3_get_board_configuration(struct hns3_hw *hw)
2571 {
2572         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2573         struct hns3_pf *pf = &hns->pf;
2574         struct hns3_cfg cfg;
2575         int ret;
2576
2577         ret = hns3_get_board_cfg(hw, &cfg);
2578         if (ret) {
2579                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2580                 return ret;
2581         }
2582
2583         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2584                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2585                 return -EOPNOTSUPP;
2586         }
2587
2588         hw->mac.media_type = cfg.media_type;
2589         hw->rss_size_max = cfg.rss_size_max;
2590         hw->rx_buf_len = cfg.rx_buf_len;
2591         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2592         hw->mac.phy_addr = cfg.phy_addr;
2593         hw->mac.default_addr_setted = false;
2594         hw->num_tx_desc = cfg.tqp_desc_num;
2595         hw->num_rx_desc = cfg.tqp_desc_num;
2596         hw->dcb_info.num_pg = 1;
2597         hw->dcb_info.hw_pfc_map = 0;
2598
2599         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2600         if (ret) {
2601                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2602                              cfg.default_speed, ret);
2603                 return ret;
2604         }
2605
2606         pf->tc_max = cfg.tc_num;
2607         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2608                 PMD_INIT_LOG(WARNING,
2609                              "Get TC num(%u) from flash, set TC num to 1",
2610                              pf->tc_max);
2611                 pf->tc_max = 1;
2612         }
2613
2614         /* Dev does not support DCB */
2615         if (!hns3_dev_dcb_supported(hw)) {
2616                 pf->tc_max = 1;
2617                 pf->pfc_max = 0;
2618         } else
2619                 pf->pfc_max = pf->tc_max;
2620
2621         hw->dcb_info.num_tc = 1;
2622         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2623                                      hw->tqps_num / hw->dcb_info.num_tc);
2624         hns3_set_bit(hw->hw_tc_map, 0, 1);
2625         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2626
2627         pf->wanted_umv_size = cfg.umv_space;
2628
2629         return ret;
2630 }
2631
2632 static int
2633 hns3_get_configuration(struct hns3_hw *hw)
2634 {
2635         int ret;
2636
2637         ret = hns3_query_function_status(hw);
2638         if (ret) {
2639                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2640                 return ret;
2641         }
2642
2643         /* Get pf resource */
2644         ret = hns3_query_pf_resource(hw);
2645         if (ret) {
2646                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2647                 return ret;
2648         }
2649
2650         ret = hns3_get_board_configuration(hw);
2651         if (ret) {
2652                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2653                 return ret;
2654         }
2655
2656         return 0;
2657 }
2658
2659 static int
2660 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2661                       uint16_t tqp_vid, bool is_pf)
2662 {
2663         struct hns3_tqp_map_cmd *req;
2664         struct hns3_cmd_desc desc;
2665         int ret;
2666
2667         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2668
2669         req = (struct hns3_tqp_map_cmd *)desc.data;
2670         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2671         req->tqp_vf = func_id;
2672         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2673         if (!is_pf)
2674                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2675         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2676
2677         ret = hns3_cmd_send(hw, &desc, 1);
2678         if (ret)
2679                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2680
2681         return ret;
2682 }
2683
2684 static int
2685 hns3_map_tqp(struct hns3_hw *hw)
2686 {
2687         uint16_t tqps_num = hw->total_tqps_num;
2688         uint16_t func_id;
2689         uint16_t tqp_id;
2690         bool is_pf;
2691         int num;
2692         int ret;
2693         int i;
2694
2695         /*
2696          * In current version VF is not supported when PF is driven by DPDK
2697          * driver, so we allocate tqps to PF as much as possible.
2698          */
2699         tqp_id = 0;
2700         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2701         for (func_id = 0; func_id < num; func_id++) {
2702                 is_pf = func_id == 0 ? true : false;
2703                 for (i = 0;
2704                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2705                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2706                                                     is_pf);
2707                         if (ret)
2708                                 return ret;
2709                 }
2710         }
2711
2712         return 0;
2713 }
2714
2715 static int
2716 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2717 {
2718         struct hns3_config_mac_speed_dup_cmd *req;
2719         struct hns3_cmd_desc desc;
2720         int ret;
2721
2722         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2723
2724         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2725
2726         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2727
2728         switch (speed) {
2729         case ETH_SPEED_NUM_10M:
2730                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2731                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2732                 break;
2733         case ETH_SPEED_NUM_100M:
2734                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2735                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2736                 break;
2737         case ETH_SPEED_NUM_1G:
2738                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2739                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2740                 break;
2741         case ETH_SPEED_NUM_10G:
2742                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2743                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2744                 break;
2745         case ETH_SPEED_NUM_25G:
2746                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2747                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2748                 break;
2749         case ETH_SPEED_NUM_40G:
2750                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2751                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2752                 break;
2753         case ETH_SPEED_NUM_50G:
2754                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2755                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2756                 break;
2757         case ETH_SPEED_NUM_100G:
2758                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2759                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2760                 break;
2761         default:
2762                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2763                 return -EINVAL;
2764         }
2765
2766         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2767
2768         ret = hns3_cmd_send(hw, &desc, 1);
2769         if (ret)
2770                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2771
2772         return ret;
2773 }
2774
2775 static int
2776 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2777 {
2778         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2779         struct hns3_pf *pf = &hns->pf;
2780         struct hns3_priv_buf *priv;
2781         uint32_t i, total_size;
2782
2783         total_size = pf->pkt_buf_size;
2784
2785         /* alloc tx buffer for all enabled tc */
2786         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2787                 priv = &buf_alloc->priv_buf[i];
2788
2789                 if (hw->hw_tc_map & BIT(i)) {
2790                         if (total_size < pf->tx_buf_size)
2791                                 return -ENOMEM;
2792
2793                         priv->tx_buf_size = pf->tx_buf_size;
2794                 } else
2795                         priv->tx_buf_size = 0;
2796
2797                 total_size -= priv->tx_buf_size;
2798         }
2799
2800         return 0;
2801 }
2802
2803 static int
2804 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2805 {
2806 /* TX buffer size is unit by 128 byte */
2807 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2808 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2809         struct hns3_tx_buff_alloc_cmd *req;
2810         struct hns3_cmd_desc desc;
2811         uint32_t buf_size;
2812         uint32_t i;
2813         int ret;
2814
2815         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2816
2817         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2818         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2819                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2820
2821                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2822                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2823                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2824         }
2825
2826         ret = hns3_cmd_send(hw, &desc, 1);
2827         if (ret)
2828                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2829
2830         return ret;
2831 }
2832
2833 static int
2834 hns3_get_tc_num(struct hns3_hw *hw)
2835 {
2836         int cnt = 0;
2837         uint8_t i;
2838
2839         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2840                 if (hw->hw_tc_map & BIT(i))
2841                         cnt++;
2842         return cnt;
2843 }
2844
2845 static uint32_t
2846 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2847 {
2848         struct hns3_priv_buf *priv;
2849         uint32_t rx_priv = 0;
2850         int i;
2851
2852         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2853                 priv = &buf_alloc->priv_buf[i];
2854                 if (priv->enable)
2855                         rx_priv += priv->buf_size;
2856         }
2857         return rx_priv;
2858 }
2859
2860 static uint32_t
2861 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2862 {
2863         uint32_t total_tx_size = 0;
2864         uint32_t i;
2865
2866         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2867                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2868
2869         return total_tx_size;
2870 }
2871
2872 /* Get the number of pfc enabled TCs, which have private buffer */
2873 static int
2874 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2875 {
2876         struct hns3_priv_buf *priv;
2877         int cnt = 0;
2878         uint8_t i;
2879
2880         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2881                 priv = &buf_alloc->priv_buf[i];
2882                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2883                         cnt++;
2884         }
2885
2886         return cnt;
2887 }
2888
2889 /* Get the number of pfc disabled TCs, which have private buffer */
2890 static int
2891 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2892                          struct hns3_pkt_buf_alloc *buf_alloc)
2893 {
2894         struct hns3_priv_buf *priv;
2895         int cnt = 0;
2896         uint8_t i;
2897
2898         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2899                 priv = &buf_alloc->priv_buf[i];
2900                 if (hw->hw_tc_map & BIT(i) &&
2901                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2902                         cnt++;
2903         }
2904
2905         return cnt;
2906 }
2907
2908 static bool
2909 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2910                   uint32_t rx_all)
2911 {
2912         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2913         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2914         struct hns3_pf *pf = &hns->pf;
2915         uint32_t shared_buf, aligned_mps;
2916         uint32_t rx_priv;
2917         uint8_t tc_num;
2918         uint8_t i;
2919
2920         tc_num = hns3_get_tc_num(hw);
2921         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2922
2923         if (hns3_dev_dcb_supported(hw))
2924                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2925                                         pf->dv_buf_size;
2926         else
2927                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2928                                         + pf->dv_buf_size;
2929
2930         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2931         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2932                              HNS3_BUF_SIZE_UNIT);
2933
2934         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2935         if (rx_all < rx_priv + shared_std)
2936                 return false;
2937
2938         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2939         buf_alloc->s_buf.buf_size = shared_buf;
2940         if (hns3_dev_dcb_supported(hw)) {
2941                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2942                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2943                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2944                                   HNS3_BUF_SIZE_UNIT);
2945         } else {
2946                 buf_alloc->s_buf.self.high =
2947                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2948                 buf_alloc->s_buf.self.low = aligned_mps;
2949         }
2950
2951         if (hns3_dev_dcb_supported(hw)) {
2952                 hi_thrd = shared_buf - pf->dv_buf_size;
2953
2954                 if (tc_num <= NEED_RESERVE_TC_NUM)
2955                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2956                                         / BUF_MAX_PERCENT;
2957
2958                 if (tc_num)
2959                         hi_thrd = hi_thrd / tc_num;
2960
2961                 hi_thrd = max_t(uint32_t, hi_thrd,
2962                                 HNS3_BUF_MUL_BY * aligned_mps);
2963                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2964                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2965         } else {
2966                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2967                 lo_thrd = aligned_mps;
2968         }
2969
2970         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2971                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2972                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2973         }
2974
2975         return true;
2976 }
2977
2978 static bool
2979 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2980                      struct hns3_pkt_buf_alloc *buf_alloc)
2981 {
2982         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2983         struct hns3_pf *pf = &hns->pf;
2984         struct hns3_priv_buf *priv;
2985         uint32_t aligned_mps;
2986         uint32_t rx_all;
2987         uint8_t i;
2988
2989         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2990         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2991
2992         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2993                 priv = &buf_alloc->priv_buf[i];
2994
2995                 priv->enable = 0;
2996                 priv->wl.low = 0;
2997                 priv->wl.high = 0;
2998                 priv->buf_size = 0;
2999
3000                 if (!(hw->hw_tc_map & BIT(i)))
3001                         continue;
3002
3003                 priv->enable = 1;
3004                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3005                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3006                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3007                                                 HNS3_BUF_SIZE_UNIT);
3008                 } else {
3009                         priv->wl.low = 0;
3010                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3011                                         aligned_mps;
3012                 }
3013
3014                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3015         }
3016
3017         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3018 }
3019
3020 static bool
3021 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3022                              struct hns3_pkt_buf_alloc *buf_alloc)
3023 {
3024         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3025         struct hns3_pf *pf = &hns->pf;
3026         struct hns3_priv_buf *priv;
3027         int no_pfc_priv_num;
3028         uint32_t rx_all;
3029         uint8_t mask;
3030         int i;
3031
3032         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3033         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3034
3035         /* let the last to be cleared first */
3036         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3037                 priv = &buf_alloc->priv_buf[i];
3038                 mask = BIT((uint8_t)i);
3039
3040                 if (hw->hw_tc_map & mask &&
3041                     !(hw->dcb_info.hw_pfc_map & mask)) {
3042                         /* Clear the no pfc TC private buffer */
3043                         priv->wl.low = 0;
3044                         priv->wl.high = 0;
3045                         priv->buf_size = 0;
3046                         priv->enable = 0;
3047                         no_pfc_priv_num--;
3048                 }
3049
3050                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3051                     no_pfc_priv_num == 0)
3052                         break;
3053         }
3054
3055         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3056 }
3057
3058 static bool
3059 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3060                            struct hns3_pkt_buf_alloc *buf_alloc)
3061 {
3062         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3063         struct hns3_pf *pf = &hns->pf;
3064         struct hns3_priv_buf *priv;
3065         uint32_t rx_all;
3066         int pfc_priv_num;
3067         uint8_t mask;
3068         int i;
3069
3070         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3071         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3072
3073         /* let the last to be cleared first */
3074         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3075                 priv = &buf_alloc->priv_buf[i];
3076                 mask = BIT((uint8_t)i);
3077
3078                 if (hw->hw_tc_map & mask &&
3079                     hw->dcb_info.hw_pfc_map & mask) {
3080                         /* Reduce the number of pfc TC with private buffer */
3081                         priv->wl.low = 0;
3082                         priv->enable = 0;
3083                         priv->wl.high = 0;
3084                         priv->buf_size = 0;
3085                         pfc_priv_num--;
3086                 }
3087                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3088                     pfc_priv_num == 0)
3089                         break;
3090         }
3091
3092         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3093 }
3094
3095 static bool
3096 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3097                           struct hns3_pkt_buf_alloc *buf_alloc)
3098 {
3099 #define COMPENSATE_BUFFER       0x3C00
3100 #define COMPENSATE_HALF_MPS_NUM 5
3101 #define PRIV_WL_GAP             0x1800
3102         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3103         struct hns3_pf *pf = &hns->pf;
3104         uint32_t tc_num = hns3_get_tc_num(hw);
3105         uint32_t half_mps = pf->mps >> 1;
3106         struct hns3_priv_buf *priv;
3107         uint32_t min_rx_priv;
3108         uint32_t rx_priv;
3109         uint8_t i;
3110
3111         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3112         if (tc_num)
3113                 rx_priv = rx_priv / tc_num;
3114
3115         if (tc_num <= NEED_RESERVE_TC_NUM)
3116                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3117
3118         /*
3119          * Minimum value of private buffer in rx direction (min_rx_priv) is
3120          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3121          * buffer if rx_priv is greater than min_rx_priv.
3122          */
3123         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3124                         COMPENSATE_HALF_MPS_NUM * half_mps;
3125         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3126         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3127
3128         if (rx_priv < min_rx_priv)
3129                 return false;
3130
3131         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3132                 priv = &buf_alloc->priv_buf[i];
3133
3134                 priv->enable = 0;
3135                 priv->wl.low = 0;
3136                 priv->wl.high = 0;
3137                 priv->buf_size = 0;
3138
3139                 if (!(hw->hw_tc_map & BIT(i)))
3140                         continue;
3141
3142                 priv->enable = 1;
3143                 priv->buf_size = rx_priv;
3144                 priv->wl.high = rx_priv - pf->dv_buf_size;
3145                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3146         }
3147
3148         buf_alloc->s_buf.buf_size = 0;
3149
3150         return true;
3151 }
3152
3153 /*
3154  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3155  * @hw: pointer to struct hns3_hw
3156  * @buf_alloc: pointer to buffer calculation data
3157  * @return: 0: calculate sucessful, negative: fail
3158  */
3159 static int
3160 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3161 {
3162         /* When DCB is not supported, rx private buffer is not allocated. */
3163         if (!hns3_dev_dcb_supported(hw)) {
3164                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3165                 struct hns3_pf *pf = &hns->pf;
3166                 uint32_t rx_all = pf->pkt_buf_size;
3167
3168                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3169                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3170                         return -ENOMEM;
3171
3172                 return 0;
3173         }
3174
3175         /*
3176          * Try to allocate privated packet buffer for all TCs without share
3177          * buffer.
3178          */
3179         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3180                 return 0;
3181
3182         /*
3183          * Try to allocate privated packet buffer for all TCs with share
3184          * buffer.
3185          */
3186         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3187                 return 0;
3188
3189         /*
3190          * For different application scenes, the enabled port number, TC number
3191          * and no_drop TC number are different. In order to obtain the better
3192          * performance, software could allocate the buffer size and configure
3193          * the waterline by tring to decrease the private buffer size according
3194          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3195          * enabled tc.
3196          */
3197         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3198                 return 0;
3199
3200         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3201                 return 0;
3202
3203         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3204                 return 0;
3205
3206         return -ENOMEM;
3207 }
3208
3209 static int
3210 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3211 {
3212         struct hns3_rx_priv_buff_cmd *req;
3213         struct hns3_cmd_desc desc;
3214         uint32_t buf_size;
3215         int ret;
3216         int i;
3217
3218         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3219         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3220
3221         /* Alloc private buffer TCs */
3222         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3223                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3224
3225                 req->buf_num[i] =
3226                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3227                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3228         }
3229
3230         buf_size = buf_alloc->s_buf.buf_size;
3231         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3232                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3233
3234         ret = hns3_cmd_send(hw, &desc, 1);
3235         if (ret)
3236                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3237
3238         return ret;
3239 }
3240
3241 static int
3242 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3243 {
3244 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3245         struct hns3_rx_priv_wl_buf *req;
3246         struct hns3_priv_buf *priv;
3247         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3248         int i, j;
3249         int ret;
3250
3251         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3252                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3253                                           false);
3254                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3255
3256                 /* The first descriptor set the NEXT bit to 1 */
3257                 if (i == 0)
3258                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3259                 else
3260                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3261
3262                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3263                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3264
3265                         priv = &buf_alloc->priv_buf[idx];
3266                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3267                                                         HNS3_BUF_UNIT_S);
3268                         req->tc_wl[j].high |=
3269                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3270                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3271                                                         HNS3_BUF_UNIT_S);
3272                         req->tc_wl[j].low |=
3273                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3274                 }
3275         }
3276
3277         /* Send 2 descriptor at one time */
3278         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3279         if (ret)
3280                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3281                              ret);
3282         return ret;
3283 }
3284
3285 static int
3286 hns3_common_thrd_config(struct hns3_hw *hw,
3287                         struct hns3_pkt_buf_alloc *buf_alloc)
3288 {
3289 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3290         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3291         struct hns3_rx_com_thrd *req;
3292         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3293         struct hns3_tc_thrd *tc;
3294         int tc_idx;
3295         int i, j;
3296         int ret;
3297
3298         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3299                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3300                                           false);
3301                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3302
3303                 /* The first descriptor set the NEXT bit to 1 */
3304                 if (i == 0)
3305                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3306                 else
3307                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3308
3309                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3310                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3311                         tc = &s_buf->tc_thrd[tc_idx];
3312
3313                         req->com_thrd[j].high =
3314                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3315                         req->com_thrd[j].high |=
3316                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3317                         req->com_thrd[j].low =
3318                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3319                         req->com_thrd[j].low |=
3320                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3321                 }
3322         }
3323
3324         /* Send 2 descriptors at one time */
3325         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3326         if (ret)
3327                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3328
3329         return ret;
3330 }
3331
3332 static int
3333 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3334 {
3335         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3336         struct hns3_rx_com_wl *req;
3337         struct hns3_cmd_desc desc;
3338         int ret;
3339
3340         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3341
3342         req = (struct hns3_rx_com_wl *)desc.data;
3343         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3344         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3345
3346         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3347         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3348
3349         ret = hns3_cmd_send(hw, &desc, 1);
3350         if (ret)
3351                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3352
3353         return ret;
3354 }
3355
3356 int
3357 hns3_buffer_alloc(struct hns3_hw *hw)
3358 {
3359         struct hns3_pkt_buf_alloc pkt_buf;
3360         int ret;
3361
3362         memset(&pkt_buf, 0, sizeof(pkt_buf));
3363         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3364         if (ret) {
3365                 PMD_INIT_LOG(ERR,
3366                              "could not calc tx buffer size for all TCs %d",
3367                              ret);
3368                 return ret;
3369         }
3370
3371         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3372         if (ret) {
3373                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3374                 return ret;
3375         }
3376
3377         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3378         if (ret) {
3379                 PMD_INIT_LOG(ERR,
3380                              "could not calc rx priv buffer size for all TCs %d",
3381                              ret);
3382                 return ret;
3383         }
3384
3385         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3386         if (ret) {
3387                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3388                 return ret;
3389         }
3390
3391         if (hns3_dev_dcb_supported(hw)) {
3392                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3393                 if (ret) {
3394                         PMD_INIT_LOG(ERR,
3395                                      "could not configure rx private waterline %d",
3396                                      ret);
3397                         return ret;
3398                 }
3399
3400                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3401                 if (ret) {
3402                         PMD_INIT_LOG(ERR,
3403                                      "could not configure common threshold %d",
3404                                      ret);
3405                         return ret;
3406                 }
3407         }
3408
3409         ret = hns3_common_wl_config(hw, &pkt_buf);
3410         if (ret)
3411                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3412                              ret);
3413
3414         return ret;
3415 }
3416
3417 static int
3418 hns3_mac_init(struct hns3_hw *hw)
3419 {
3420         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3421         struct hns3_mac *mac = &hw->mac;
3422         struct hns3_pf *pf = &hns->pf;
3423         int ret;
3424
3425         pf->support_sfp_query = true;
3426         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3427         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3428         if (ret) {
3429                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3430                 return ret;
3431         }
3432
3433         mac->link_status = ETH_LINK_DOWN;
3434
3435         return hns3_config_mtu(hw, pf->mps);
3436 }
3437
3438 static int
3439 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3440 {
3441 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3442 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3443 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3444 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3445         int return_status;
3446
3447         if (cmdq_resp) {
3448                 PMD_INIT_LOG(ERR,
3449                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3450                              cmdq_resp);
3451                 return -EIO;
3452         }
3453
3454         switch (resp_code) {
3455         case HNS3_ETHERTYPE_SUCCESS_ADD:
3456         case HNS3_ETHERTYPE_ALREADY_ADD:
3457                 return_status = 0;
3458                 break;
3459         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3460                 PMD_INIT_LOG(ERR,
3461                              "add mac ethertype failed for manager table overflow.");
3462                 return_status = -EIO;
3463                 break;
3464         case HNS3_ETHERTYPE_KEY_CONFLICT:
3465                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3466                 return_status = -EIO;
3467                 break;
3468         default:
3469                 PMD_INIT_LOG(ERR,
3470                              "add mac ethertype failed for undefined, code=%d.",
3471                              resp_code);
3472                 return_status = -EIO;
3473         }
3474
3475         return return_status;
3476 }
3477
3478 static int
3479 hns3_add_mgr_tbl(struct hns3_hw *hw,
3480                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3481 {
3482         struct hns3_cmd_desc desc;
3483         uint8_t resp_code;
3484         uint16_t retval;
3485         int ret;
3486
3487         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3488         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3489
3490         ret = hns3_cmd_send(hw, &desc, 1);
3491         if (ret) {
3492                 PMD_INIT_LOG(ERR,
3493                              "add mac ethertype failed for cmd_send, ret =%d.",
3494                              ret);
3495                 return ret;
3496         }
3497
3498         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3499         retval = rte_le_to_cpu_16(desc.retval);
3500
3501         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3502 }
3503
3504 static void
3505 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3506                      int *table_item_num)
3507 {
3508         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3509
3510         /*
3511          * In current version, we add one item in management table as below:
3512          * 0x0180C200000E -- LLDP MC address
3513          */
3514         tbl = mgr_table;
3515         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3516         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3517         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3518         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3519         tbl->i_port_bitmap = 0x1;
3520         *table_item_num = 1;
3521 }
3522
3523 static int
3524 hns3_init_mgr_tbl(struct hns3_hw *hw)
3525 {
3526 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3527         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3528         int table_item_num;
3529         int ret;
3530         int i;
3531
3532         memset(mgr_table, 0, sizeof(mgr_table));
3533         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3534         for (i = 0; i < table_item_num; i++) {
3535                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3536                 if (ret) {
3537                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3538                                      ret);
3539                         return ret;
3540                 }
3541         }
3542
3543         return 0;
3544 }
3545
3546 static void
3547 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3548                         bool en_mc, bool en_bc, int vport_id)
3549 {
3550         if (!param)
3551                 return;
3552
3553         memset(param, 0, sizeof(struct hns3_promisc_param));
3554         if (en_uc)
3555                 param->enable = HNS3_PROMISC_EN_UC;
3556         if (en_mc)
3557                 param->enable |= HNS3_PROMISC_EN_MC;
3558         if (en_bc)
3559                 param->enable |= HNS3_PROMISC_EN_BC;
3560         param->vf_id = vport_id;
3561 }
3562
3563 static int
3564 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3565 {
3566         struct hns3_promisc_cfg_cmd *req;
3567         struct hns3_cmd_desc desc;
3568         int ret;
3569
3570         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3571
3572         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3573         req->vf_id = param->vf_id;
3574         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3575             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3576
3577         ret = hns3_cmd_send(hw, &desc, 1);
3578         if (ret)
3579                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3580
3581         return ret;
3582 }
3583
3584 static int
3585 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3586 {
3587         struct hns3_promisc_param param;
3588         bool en_bc_pmc = true;
3589         uint8_t vf_id;
3590         int ret;
3591
3592         /*
3593          * In current version VF is not supported when PF is driven by DPDK
3594          * driver, the PF-related vf_id is 0, just need to configure parameters
3595          * for vf_id 0.
3596          */
3597         vf_id = 0;
3598
3599         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3600         ret = hns3_cmd_set_promisc_mode(hw, &param);
3601         if (ret)
3602                 return ret;
3603
3604         return 0;
3605 }
3606
3607 static int
3608 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3609 {
3610         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3611         struct hns3_pf *pf = &hns->pf;
3612         struct hns3_promisc_param param;
3613         uint16_t func_id;
3614         int ret;
3615
3616         /* func_id 0 is denoted PF, the VFs start from 1 */
3617         for (func_id = 1; func_id < pf->func_num; func_id++) {
3618                 hns3_promisc_param_init(&param, false, false, false, func_id);
3619                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3620                 if (ret)
3621                         return ret;
3622         }
3623
3624         return 0;
3625 }
3626
3627 static int
3628 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3629 {
3630         struct hns3_adapter *hns = dev->data->dev_private;
3631         struct hns3_hw *hw = &hns->hw;
3632         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3633         int ret;
3634
3635         rte_spinlock_lock(&hw->lock);
3636         ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3637         rte_spinlock_unlock(&hw->lock);
3638         if (ret)
3639                 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3640
3641         return ret;
3642 }
3643
3644 static int
3645 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3646 {
3647         struct hns3_adapter *hns = dev->data->dev_private;
3648         struct hns3_hw *hw = &hns->hw;
3649         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3650         int ret;
3651
3652         /* If now in all_multicast mode, must remain in all_multicast mode. */
3653         rte_spinlock_lock(&hw->lock);
3654         ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3655         rte_spinlock_unlock(&hw->lock);
3656         if (ret)
3657                 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3658
3659         return ret;
3660 }
3661
3662 static int
3663 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3664 {
3665         struct hns3_adapter *hns = dev->data->dev_private;
3666         struct hns3_hw *hw = &hns->hw;
3667         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3668         int ret;
3669
3670         rte_spinlock_lock(&hw->lock);
3671         ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3672         rte_spinlock_unlock(&hw->lock);
3673         if (ret)
3674                 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3675
3676         return ret;
3677 }
3678
3679 static int
3680 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3681 {
3682         struct hns3_adapter *hns = dev->data->dev_private;
3683         struct hns3_hw *hw = &hns->hw;
3684         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3685         int ret;
3686
3687         /* If now in promiscuous mode, must remain in all_multicast mode. */
3688         if (dev->data->promiscuous == 1)
3689                 return 0;
3690
3691         rte_spinlock_lock(&hw->lock);
3692         ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3693         rte_spinlock_unlock(&hw->lock);
3694         if (ret)
3695                 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3696
3697         return ret;
3698 }
3699
3700 static int
3701 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3702 {
3703         struct hns3_hw *hw = &hns->hw;
3704         bool en_mc_pmc;
3705         bool en_uc_pmc;
3706
3707         en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3708         en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3709
3710         return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3711 }
3712
3713 static int
3714 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3715 {
3716         struct hns3_sfp_speed_cmd *resp;
3717         struct hns3_cmd_desc desc;
3718         int ret;
3719
3720         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3721         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3722         ret = hns3_cmd_send(hw, &desc, 1);
3723         if (ret == -EOPNOTSUPP) {
3724                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3725                 return ret;
3726         } else if (ret) {
3727                 hns3_err(hw, "get sfp speed failed %d", ret);
3728                 return ret;
3729         }
3730
3731         *speed = resp->sfp_speed;
3732
3733         return 0;
3734 }
3735
3736 static uint8_t
3737 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3738 {
3739         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3740                 duplex = ETH_LINK_FULL_DUPLEX;
3741
3742         return duplex;
3743 }
3744
3745 static int
3746 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3747 {
3748         struct hns3_mac *mac = &hw->mac;
3749         int ret;
3750
3751         duplex = hns3_check_speed_dup(duplex, speed);
3752         if (mac->link_speed == speed && mac->link_duplex == duplex)
3753                 return 0;
3754
3755         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3756         if (ret)
3757                 return ret;
3758
3759         mac->link_speed = speed;
3760         mac->link_duplex = duplex;
3761
3762         return 0;
3763 }
3764
3765 static int
3766 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3767 {
3768         struct hns3_adapter *hns = eth_dev->data->dev_private;
3769         struct hns3_hw *hw = &hns->hw;
3770         struct hns3_pf *pf = &hns->pf;
3771         uint32_t speed;
3772         int ret;
3773
3774         /* If IMP do not support get SFP/qSFP speed, return directly */
3775         if (!pf->support_sfp_query)
3776                 return 0;
3777
3778         ret = hns3_get_sfp_speed(hw, &speed);
3779         if (ret == -EOPNOTSUPP) {
3780                 pf->support_sfp_query = false;
3781                 return ret;
3782         } else if (ret)
3783                 return ret;
3784
3785         if (speed == ETH_SPEED_NUM_NONE)
3786                 return 0; /* do nothing if no SFP */
3787
3788         /* Config full duplex for SFP */
3789         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3790 }
3791
3792 static int
3793 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3794 {
3795         struct hns3_config_mac_mode_cmd *req;
3796         struct hns3_cmd_desc desc;
3797         uint32_t loop_en = 0;
3798         uint8_t val = 0;
3799         int ret;
3800
3801         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3802
3803         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3804         if (enable)
3805                 val = 1;
3806         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3807         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3808         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3809         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3810         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3811         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3812         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3813         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3814         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3815         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3816         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3817         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3818         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3819         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3820         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3821
3822         ret = hns3_cmd_send(hw, &desc, 1);
3823         if (ret)
3824                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3825
3826         return ret;
3827 }
3828
3829 static int
3830 hns3_get_mac_link_status(struct hns3_hw *hw)
3831 {
3832         struct hns3_link_status_cmd *req;
3833         struct hns3_cmd_desc desc;
3834         int link_status;
3835         int ret;
3836
3837         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3838         ret = hns3_cmd_send(hw, &desc, 1);
3839         if (ret) {
3840                 hns3_err(hw, "get link status cmd failed %d", ret);
3841                 return ETH_LINK_DOWN;
3842         }
3843
3844         req = (struct hns3_link_status_cmd *)desc.data;
3845         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3846
3847         return !!link_status;
3848 }
3849
3850 void
3851 hns3_update_link_status(struct hns3_hw *hw)
3852 {
3853         int state;
3854
3855         state = hns3_get_mac_link_status(hw);
3856         if (state != hw->mac.link_status) {
3857                 hw->mac.link_status = state;
3858                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3859         }
3860 }
3861
3862 static void
3863 hns3_service_handler(void *param)
3864 {
3865         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3866         struct hns3_adapter *hns = eth_dev->data->dev_private;
3867         struct hns3_hw *hw = &hns->hw;
3868
3869         if (!hns3_is_reset_pending(hns)) {
3870                 hns3_update_speed_duplex(eth_dev);
3871                 hns3_update_link_status(hw);
3872         } else
3873                 hns3_warn(hw, "Cancel the query when reset is pending");
3874
3875         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3876 }
3877
3878 static int
3879 hns3_init_hardware(struct hns3_adapter *hns)
3880 {
3881         struct hns3_hw *hw = &hns->hw;
3882         int ret;
3883
3884         ret = hns3_map_tqp(hw);
3885         if (ret) {
3886                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3887                 return ret;
3888         }
3889
3890         ret = hns3_init_umv_space(hw);
3891         if (ret) {
3892                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3893                 return ret;
3894         }
3895
3896         ret = hns3_mac_init(hw);
3897         if (ret) {
3898                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3899                 goto err_mac_init;
3900         }
3901
3902         ret = hns3_init_mgr_tbl(hw);
3903         if (ret) {
3904                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3905                 goto err_mac_init;
3906         }
3907
3908         ret = hns3_set_promisc_mode(hw, false, false);
3909         if (ret) {
3910                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3911                 goto err_mac_init;
3912         }
3913
3914         ret = hns3_clear_all_vfs_promisc_mode(hw);
3915         if (ret) {
3916                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3917                              ret);
3918                 goto err_mac_init;
3919         }
3920
3921         ret = hns3_init_vlan_config(hns);
3922         if (ret) {
3923                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3924                 goto err_mac_init;
3925         }
3926
3927         ret = hns3_dcb_init(hw);
3928         if (ret) {
3929                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3930                 goto err_mac_init;
3931         }
3932
3933         ret = hns3_init_fd_config(hns);
3934         if (ret) {
3935                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3936                 goto err_mac_init;
3937         }
3938
3939         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3940         if (ret) {
3941                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3942                 goto err_mac_init;
3943         }
3944
3945         ret = hns3_config_gro(hw, false);
3946         if (ret) {
3947                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3948                 goto err_mac_init;
3949         }
3950         return 0;
3951
3952 err_mac_init:
3953         hns3_uninit_umv_space(hw);
3954         return ret;
3955 }
3956
3957 static int
3958 hns3_init_pf(struct rte_eth_dev *eth_dev)
3959 {
3960         struct rte_device *dev = eth_dev->device;
3961         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3962         struct hns3_adapter *hns = eth_dev->data->dev_private;
3963         struct hns3_hw *hw = &hns->hw;
3964         int ret;
3965
3966         PMD_INIT_FUNC_TRACE();
3967
3968         /* Get hardware io base address from pcie BAR2 IO space */
3969         hw->io_base = pci_dev->mem_resource[2].addr;
3970
3971         /* Firmware command queue initialize */
3972         ret = hns3_cmd_init_queue(hw);
3973         if (ret) {
3974                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3975                 goto err_cmd_init_queue;
3976         }
3977
3978         hns3_clear_all_event_cause(hw);
3979
3980         /* Firmware command initialize */
3981         ret = hns3_cmd_init(hw);
3982         if (ret) {
3983                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3984                 goto err_cmd_init;
3985         }
3986
3987         ret = rte_intr_callback_register(&pci_dev->intr_handle,
3988                                          hns3_interrupt_handler,
3989                                          eth_dev);
3990         if (ret) {
3991                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3992                 goto err_intr_callback_register;
3993         }
3994
3995         /* Enable interrupt */
3996         rte_intr_enable(&pci_dev->intr_handle);
3997         hns3_pf_enable_irq0(hw);
3998
3999         /* Get configuration */
4000         ret = hns3_get_configuration(hw);
4001         if (ret) {
4002                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4003                 goto err_get_config;
4004         }
4005
4006         ret = hns3_init_hardware(hns);
4007         if (ret) {
4008                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4009                 goto err_get_config;
4010         }
4011
4012         /* Initialize flow director filter list & hash */
4013         ret = hns3_fdir_filter_init(hns);
4014         if (ret) {
4015                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4016                 goto err_hw_init;
4017         }
4018
4019         hns3_set_default_rss_args(hw);
4020
4021         ret = hns3_enable_hw_error_intr(hns, true);
4022         if (ret) {
4023                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4024                              ret);
4025                 goto err_fdir;
4026         }
4027
4028         return 0;
4029
4030 err_fdir:
4031         hns3_fdir_filter_uninit(hns);
4032 err_hw_init:
4033         hns3_uninit_umv_space(hw);
4034
4035 err_get_config:
4036         hns3_pf_disable_irq0(hw);
4037         rte_intr_disable(&pci_dev->intr_handle);
4038         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4039                              eth_dev);
4040
4041 err_intr_callback_register:
4042         hns3_cmd_uninit(hw);
4043
4044 err_cmd_init:
4045         hns3_cmd_destroy_queue(hw);
4046
4047 err_cmd_init_queue:
4048         hw->io_base = NULL;
4049
4050         return ret;
4051 }
4052
4053 static void
4054 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4055 {
4056         struct hns3_adapter *hns = eth_dev->data->dev_private;
4057         struct rte_device *dev = eth_dev->device;
4058         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4059         struct hns3_hw *hw = &hns->hw;
4060
4061         PMD_INIT_FUNC_TRACE();
4062
4063         hns3_enable_hw_error_intr(hns, false);
4064         hns3_rss_uninit(hns);
4065         hns3_fdir_filter_uninit(hns);
4066         hns3_uninit_umv_space(hw);
4067         hns3_pf_disable_irq0(hw);
4068         rte_intr_disable(&pci_dev->intr_handle);
4069         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4070                              eth_dev);
4071         hns3_cmd_uninit(hw);
4072         hns3_cmd_destroy_queue(hw);
4073         hw->io_base = NULL;
4074 }
4075
4076 static int
4077 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4078 {
4079         struct hns3_hw *hw = &hns->hw;
4080         int ret;
4081
4082         ret = hns3_dcb_cfg_update(hns);
4083         if (ret)
4084                 return ret;
4085
4086         /* Enable queues */
4087         ret = hns3_start_queues(hns, reset_queue);
4088         if (ret) {
4089                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4090                 return ret;
4091         }
4092
4093         /* Enable MAC */
4094         ret = hns3_cfg_mac_mode(hw, true);
4095         if (ret) {
4096                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4097                 goto err_config_mac_mode;
4098         }
4099         return 0;
4100
4101 err_config_mac_mode:
4102         hns3_stop_queues(hns, true);
4103         return ret;
4104 }
4105
4106 static int
4107 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4108 {
4109         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4110         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4111         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4112         uint32_t intr_vector;
4113         uint8_t base = 0;
4114         uint8_t vec = 0;
4115         uint16_t q_id;
4116         int ret;
4117
4118         if (dev->data->dev_conf.intr_conf.rxq == 0)
4119                 return 0;
4120
4121         /* disable uio/vfio intr/eventfd mapping */
4122         rte_intr_disable(intr_handle);
4123
4124         /* check and configure queue intr-vector mapping */
4125         if (rte_intr_cap_multiple(intr_handle) ||
4126             !RTE_ETH_DEV_SRIOV(dev).active) {
4127                 intr_vector = hw->used_rx_queues;
4128                 /* creates event fd for each intr vector when MSIX is used */
4129                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4130                         return -EINVAL;
4131         }
4132         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4133                 intr_handle->intr_vec =
4134                         rte_zmalloc("intr_vec",
4135                                     hw->used_rx_queues * sizeof(int), 0);
4136                 if (intr_handle->intr_vec == NULL) {
4137                         hns3_err(hw, "Failed to allocate %d rx_queues"
4138                                      " intr_vec", hw->used_rx_queues);
4139                         ret = -ENOMEM;
4140                         goto alloc_intr_vec_error;
4141                 }
4142         }
4143
4144         if (rte_intr_allow_others(intr_handle)) {
4145                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4146                 base = RTE_INTR_VEC_RXTX_OFFSET;
4147         }
4148         if (rte_intr_dp_is_en(intr_handle)) {
4149                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4150                         ret = hns3_bind_ring_with_vector(dev, vec, true, q_id);
4151                         if (ret)
4152                                 goto bind_vector_error;
4153                         intr_handle->intr_vec[q_id] = vec;
4154                         if (vec < base + intr_handle->nb_efd - 1)
4155                                 vec++;
4156                 }
4157         }
4158         rte_intr_enable(intr_handle);
4159         return 0;
4160
4161 bind_vector_error:
4162         rte_intr_efd_disable(intr_handle);
4163         if (intr_handle->intr_vec) {
4164                 free(intr_handle->intr_vec);
4165                 intr_handle->intr_vec = NULL;
4166         }
4167         return ret;
4168 alloc_intr_vec_error:
4169         rte_intr_efd_disable(intr_handle);
4170         return ret;
4171 }
4172
4173 static int
4174 hns3_dev_start(struct rte_eth_dev *dev)
4175 {
4176         struct hns3_adapter *hns = dev->data->dev_private;
4177         struct hns3_hw *hw = &hns->hw;
4178         int ret;
4179
4180         PMD_INIT_FUNC_TRACE();
4181         if (rte_atomic16_read(&hw->reset.resetting))
4182                 return -EBUSY;
4183
4184         rte_spinlock_lock(&hw->lock);
4185         hw->adapter_state = HNS3_NIC_STARTING;
4186
4187         ret = hns3_do_start(hns, true);
4188         if (ret) {
4189                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4190                 rte_spinlock_unlock(&hw->lock);
4191                 return ret;
4192         }
4193
4194         hw->adapter_state = HNS3_NIC_STARTED;
4195         rte_spinlock_unlock(&hw->lock);
4196
4197         ret = hns3_map_rx_interrupt(dev);
4198         if (ret)
4199                 return ret;
4200         hns3_set_rxtx_function(dev);
4201         hns3_mp_req_start_rxtx(dev);
4202         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4203
4204         hns3_info(hw, "hns3 dev start successful!");
4205         return 0;
4206 }
4207
4208 static int
4209 hns3_do_stop(struct hns3_adapter *hns)
4210 {
4211         struct hns3_hw *hw = &hns->hw;
4212         bool reset_queue;
4213         int ret;
4214
4215         ret = hns3_cfg_mac_mode(hw, false);
4216         if (ret)
4217                 return ret;
4218         hw->mac.link_status = ETH_LINK_DOWN;
4219
4220         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4221                 hns3_configure_all_mac_addr(hns, true);
4222                 reset_queue = true;
4223         } else
4224                 reset_queue = false;
4225         hw->mac.default_addr_setted = false;
4226         return hns3_stop_queues(hns, reset_queue);
4227 }
4228
4229 static void
4230 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4231 {
4232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4233         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4234         struct hns3_adapter *hns = dev->data->dev_private;
4235         struct hns3_hw *hw = &hns->hw;
4236         uint8_t base = 0;
4237         uint8_t vec = 0;
4238         uint16_t q_id;
4239
4240         if (dev->data->dev_conf.intr_conf.rxq == 0)
4241                 return;
4242
4243         /* unmap the ring with vector */
4244         if (rte_intr_allow_others(intr_handle)) {
4245                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4246                 base = RTE_INTR_VEC_RXTX_OFFSET;
4247         }
4248         if (rte_intr_dp_is_en(intr_handle)) {
4249                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4250                         (void)hns3_bind_ring_with_vector(dev, vec, false, q_id);
4251                         if (vec < base + intr_handle->nb_efd - 1)
4252                                 vec++;
4253                 }
4254         }
4255         /* Clean datapath event and queue/vec mapping */
4256         rte_intr_efd_disable(intr_handle);
4257         if (intr_handle->intr_vec) {
4258                 rte_free(intr_handle->intr_vec);
4259                 intr_handle->intr_vec = NULL;
4260         }
4261 }
4262
4263 static void
4264 hns3_dev_stop(struct rte_eth_dev *dev)
4265 {
4266         struct hns3_adapter *hns = dev->data->dev_private;
4267         struct hns3_hw *hw = &hns->hw;
4268
4269         PMD_INIT_FUNC_TRACE();
4270
4271         hw->adapter_state = HNS3_NIC_STOPPING;
4272         hns3_set_rxtx_function(dev);
4273         rte_wmb();
4274         /* Disable datapath on secondary process. */
4275         hns3_mp_req_stop_rxtx(dev);
4276         /* Prevent crashes when queues are still in use. */
4277         rte_delay_ms(hw->tqps_num);
4278
4279         rte_spinlock_lock(&hw->lock);
4280         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4281                 hns3_do_stop(hns);
4282                 hns3_dev_release_mbufs(hns);
4283                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4284         }
4285         rte_eal_alarm_cancel(hns3_service_handler, dev);
4286         rte_spinlock_unlock(&hw->lock);
4287         hns3_unmap_rx_interrupt(dev);
4288 }
4289
4290 static void
4291 hns3_dev_close(struct rte_eth_dev *eth_dev)
4292 {
4293         struct hns3_adapter *hns = eth_dev->data->dev_private;
4294         struct hns3_hw *hw = &hns->hw;
4295
4296         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4297                 rte_free(eth_dev->process_private);
4298                 eth_dev->process_private = NULL;
4299                 return;
4300         }
4301
4302         if (hw->adapter_state == HNS3_NIC_STARTED)
4303                 hns3_dev_stop(eth_dev);
4304
4305         hw->adapter_state = HNS3_NIC_CLOSING;
4306         hns3_reset_abort(hns);
4307         hw->adapter_state = HNS3_NIC_CLOSED;
4308
4309         hns3_configure_all_mc_mac_addr(hns, true);
4310         hns3_remove_all_vlan_table(hns);
4311         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4312         hns3_uninit_pf(eth_dev);
4313         hns3_free_all_queues(eth_dev);
4314         rte_free(hw->reset.wait_data);
4315         rte_free(eth_dev->process_private);
4316         eth_dev->process_private = NULL;
4317         hns3_mp_uninit_primary();
4318         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4319 }
4320
4321 static int
4322 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4323 {
4324         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4325         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4326
4327         fc_conf->pause_time = pf->pause_time;
4328
4329         /* return fc current mode */
4330         switch (hw->current_mode) {
4331         case HNS3_FC_FULL:
4332                 fc_conf->mode = RTE_FC_FULL;
4333                 break;
4334         case HNS3_FC_TX_PAUSE:
4335                 fc_conf->mode = RTE_FC_TX_PAUSE;
4336                 break;
4337         case HNS3_FC_RX_PAUSE:
4338                 fc_conf->mode = RTE_FC_RX_PAUSE;
4339                 break;
4340         case HNS3_FC_NONE:
4341         default:
4342                 fc_conf->mode = RTE_FC_NONE;
4343                 break;
4344         }
4345
4346         return 0;
4347 }
4348
4349 static void
4350 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4351 {
4352         switch (mode) {
4353         case RTE_FC_NONE:
4354                 hw->requested_mode = HNS3_FC_NONE;
4355                 break;
4356         case RTE_FC_RX_PAUSE:
4357                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4358                 break;
4359         case RTE_FC_TX_PAUSE:
4360                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4361                 break;
4362         case RTE_FC_FULL:
4363                 hw->requested_mode = HNS3_FC_FULL;
4364                 break;
4365         default:
4366                 hw->requested_mode = HNS3_FC_NONE;
4367                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4368                           "configured to RTE_FC_NONE", mode);
4369                 break;
4370         }
4371 }
4372
4373 static int
4374 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4375 {
4376         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4378         int ret;
4379
4380         if (fc_conf->high_water || fc_conf->low_water ||
4381             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4382                 hns3_err(hw, "Unsupported flow control settings specified, "
4383                          "high_water(%u), low_water(%u), send_xon(%u) and "
4384                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4385                          fc_conf->high_water, fc_conf->low_water,
4386                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4387                 return -EINVAL;
4388         }
4389         if (fc_conf->autoneg) {
4390                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4391                 return -EINVAL;
4392         }
4393         if (!fc_conf->pause_time) {
4394                 hns3_err(hw, "Invalid pause time %d setting.",
4395                          fc_conf->pause_time);
4396                 return -EINVAL;
4397         }
4398
4399         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4400             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4401                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4402                          "current_fc_status = %d", hw->current_fc_status);
4403                 return -EOPNOTSUPP;
4404         }
4405
4406         hns3_get_fc_mode(hw, fc_conf->mode);
4407         if (hw->requested_mode == hw->current_mode &&
4408             pf->pause_time == fc_conf->pause_time)
4409                 return 0;
4410
4411         rte_spinlock_lock(&hw->lock);
4412         ret = hns3_fc_enable(dev, fc_conf);
4413         rte_spinlock_unlock(&hw->lock);
4414
4415         return ret;
4416 }
4417
4418 static int
4419 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4420                             struct rte_eth_pfc_conf *pfc_conf)
4421 {
4422         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4423         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4424         uint8_t priority;
4425         int ret;
4426
4427         if (!hns3_dev_dcb_supported(hw)) {
4428                 hns3_err(hw, "This port does not support dcb configurations.");
4429                 return -EOPNOTSUPP;
4430         }
4431
4432         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4433             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4434                 hns3_err(hw, "Unsupported flow control settings specified, "
4435                          "high_water(%u), low_water(%u), send_xon(%u) and "
4436                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4437                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4438                          pfc_conf->fc.send_xon,
4439                          pfc_conf->fc.mac_ctrl_frame_fwd);
4440                 return -EINVAL;
4441         }
4442         if (pfc_conf->fc.autoneg) {
4443                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4444                 return -EINVAL;
4445         }
4446         if (pfc_conf->fc.pause_time == 0) {
4447                 hns3_err(hw, "Invalid pause time %d setting.",
4448                          pfc_conf->fc.pause_time);
4449                 return -EINVAL;
4450         }
4451
4452         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4453             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4454                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4455                              "current_fc_status = %d", hw->current_fc_status);
4456                 return -EOPNOTSUPP;
4457         }
4458
4459         priority = pfc_conf->priority;
4460         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4461         if (hw->dcb_info.pfc_en & BIT(priority) &&
4462             hw->requested_mode == hw->current_mode &&
4463             pfc_conf->fc.pause_time == pf->pause_time)
4464                 return 0;
4465
4466         rte_spinlock_lock(&hw->lock);
4467         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4468         rte_spinlock_unlock(&hw->lock);
4469
4470         return ret;
4471 }
4472
4473 static int
4474 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4475 {
4476         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4477         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4478         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4479         int i;
4480
4481         rte_spinlock_lock(&hw->lock);
4482         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4483                 dcb_info->nb_tcs = pf->local_max_tc;
4484         else
4485                 dcb_info->nb_tcs = 1;
4486
4487         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4488                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4489         for (i = 0; i < dcb_info->nb_tcs; i++)
4490                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4491
4492         for (i = 0; i < hw->num_tc; i++) {
4493                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4494                 dcb_info->tc_queue.tc_txq[0][i].base =
4495                                                 hw->tc_queue[i].tqp_offset;
4496                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4497                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4498                                                 hw->tc_queue[i].tqp_count;
4499         }
4500         rte_spinlock_unlock(&hw->lock);
4501
4502         return 0;
4503 }
4504
4505 static int
4506 hns3_reinit_dev(struct hns3_adapter *hns)
4507 {
4508         struct hns3_hw *hw = &hns->hw;
4509         int ret;
4510
4511         ret = hns3_cmd_init(hw);
4512         if (ret) {
4513                 hns3_err(hw, "Failed to init cmd: %d", ret);
4514                 return ret;
4515         }
4516
4517         ret = hns3_reset_all_queues(hns);
4518         if (ret) {
4519                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4520                 goto err_init;
4521         }
4522
4523         ret = hns3_init_hardware(hns);
4524         if (ret) {
4525                 hns3_err(hw, "Failed to init hardware: %d", ret);
4526                 goto err_init;
4527         }
4528
4529         ret = hns3_enable_hw_error_intr(hns, true);
4530         if (ret) {
4531                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4532                              ret);
4533                 goto err_mac_init;
4534         }
4535         hns3_info(hw, "Reset done, driver initialization finished.");
4536
4537         return 0;
4538
4539 err_mac_init:
4540         hns3_uninit_umv_space(hw);
4541 err_init:
4542         hns3_cmd_uninit(hw);
4543
4544         return ret;
4545 }
4546
4547 static bool
4548 is_pf_reset_done(struct hns3_hw *hw)
4549 {
4550         uint32_t val, reg, reg_bit;
4551
4552         switch (hw->reset.level) {
4553         case HNS3_IMP_RESET:
4554                 reg = HNS3_GLOBAL_RESET_REG;
4555                 reg_bit = HNS3_IMP_RESET_BIT;
4556                 break;
4557         case HNS3_GLOBAL_RESET:
4558                 reg = HNS3_GLOBAL_RESET_REG;
4559                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4560                 break;
4561         case HNS3_FUNC_RESET:
4562                 reg = HNS3_FUN_RST_ING;
4563                 reg_bit = HNS3_FUN_RST_ING_B;
4564                 break;
4565         case HNS3_FLR_RESET:
4566         default:
4567                 hns3_err(hw, "Wait for unsupported reset level: %d",
4568                          hw->reset.level);
4569                 return true;
4570         }
4571         val = hns3_read_dev(hw, reg);
4572         if (hns3_get_bit(val, reg_bit))
4573                 return false;
4574         else
4575                 return true;
4576 }
4577
4578 bool
4579 hns3_is_reset_pending(struct hns3_adapter *hns)
4580 {
4581         struct hns3_hw *hw = &hns->hw;
4582         enum hns3_reset_level reset;
4583
4584         hns3_check_event_cause(hns, NULL);
4585         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4586         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4587                 hns3_warn(hw, "High level reset %d is pending", reset);
4588                 return true;
4589         }
4590         reset = hns3_get_reset_level(hns, &hw->reset.request);
4591         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4592                 hns3_warn(hw, "High level reset %d is request", reset);
4593                 return true;
4594         }
4595         return false;
4596 }
4597
4598 static int
4599 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4600 {
4601         struct hns3_hw *hw = &hns->hw;
4602         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4603         struct timeval tv;
4604
4605         if (wait_data->result == HNS3_WAIT_SUCCESS)
4606                 return 0;
4607         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4608                 gettimeofday(&tv, NULL);
4609                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4610                           tv.tv_sec, tv.tv_usec);
4611                 return -ETIME;
4612         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4613                 return -EAGAIN;
4614
4615         wait_data->hns = hns;
4616         wait_data->check_completion = is_pf_reset_done;
4617         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4618                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4619         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4620         wait_data->count = HNS3_RESET_WAIT_CNT;
4621         wait_data->result = HNS3_WAIT_REQUEST;
4622         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4623         return -EAGAIN;
4624 }
4625
4626 static int
4627 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4628 {
4629         struct hns3_cmd_desc desc;
4630         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4631
4632         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4633         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4634         req->fun_reset_vfid = func_id;
4635
4636         return hns3_cmd_send(hw, &desc, 1);
4637 }
4638
4639 static int
4640 hns3_imp_reset_cmd(struct hns3_hw *hw)
4641 {
4642         struct hns3_cmd_desc desc;
4643
4644         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4645         desc.data[0] = 0xeedd;
4646
4647         return hns3_cmd_send(hw, &desc, 1);
4648 }
4649
4650 static void
4651 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4652 {
4653         struct hns3_hw *hw = &hns->hw;
4654         struct timeval tv;
4655         uint32_t val;
4656
4657         gettimeofday(&tv, NULL);
4658         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4659             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4660                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4661                           tv.tv_sec, tv.tv_usec);
4662                 return;
4663         }
4664
4665         switch (reset_level) {
4666         case HNS3_IMP_RESET:
4667                 hns3_imp_reset_cmd(hw);
4668                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4669                           tv.tv_sec, tv.tv_usec);
4670                 break;
4671         case HNS3_GLOBAL_RESET:
4672                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4673                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4674                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4675                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4676                           tv.tv_sec, tv.tv_usec);
4677                 break;
4678         case HNS3_FUNC_RESET:
4679                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4680                           tv.tv_sec, tv.tv_usec);
4681                 /* schedule again to check later */
4682                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4683                 hns3_schedule_reset(hns);
4684                 break;
4685         default:
4686                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4687                 return;
4688         }
4689         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4690 }
4691
4692 static enum hns3_reset_level
4693 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4694 {
4695         struct hns3_hw *hw = &hns->hw;
4696         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4697
4698         /* Return the highest priority reset level amongst all */
4699         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4700                 reset_level = HNS3_IMP_RESET;
4701         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4702                 reset_level = HNS3_GLOBAL_RESET;
4703         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4704                 reset_level = HNS3_FUNC_RESET;
4705         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4706                 reset_level = HNS3_FLR_RESET;
4707
4708         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4709                 return HNS3_NONE_RESET;
4710
4711         return reset_level;
4712 }
4713
4714 static int
4715 hns3_prepare_reset(struct hns3_adapter *hns)
4716 {
4717         struct hns3_hw *hw = &hns->hw;
4718         uint32_t reg_val;
4719         int ret;
4720
4721         switch (hw->reset.level) {
4722         case HNS3_FUNC_RESET:
4723                 ret = hns3_func_reset_cmd(hw, 0);
4724                 if (ret)
4725                         return ret;
4726
4727                 /*
4728                  * After performaning pf reset, it is not necessary to do the
4729                  * mailbox handling or send any command to firmware, because
4730                  * any mailbox handling or command to firmware is only valid
4731                  * after hns3_cmd_init is called.
4732                  */
4733                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4734                 hw->reset.stats.request_cnt++;
4735                 break;
4736         case HNS3_IMP_RESET:
4737                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4738                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4739                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4740                 break;
4741         default:
4742                 break;
4743         }
4744         return 0;
4745 }
4746
4747 static int
4748 hns3_set_rst_done(struct hns3_hw *hw)
4749 {
4750         struct hns3_pf_rst_done_cmd *req;
4751         struct hns3_cmd_desc desc;
4752
4753         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4754         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4755         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4756         return hns3_cmd_send(hw, &desc, 1);
4757 }
4758
4759 static int
4760 hns3_stop_service(struct hns3_adapter *hns)
4761 {
4762         struct hns3_hw *hw = &hns->hw;
4763         struct rte_eth_dev *eth_dev;
4764
4765         eth_dev = &rte_eth_devices[hw->data->port_id];
4766         if (hw->adapter_state == HNS3_NIC_STARTED)
4767                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4768         hw->mac.link_status = ETH_LINK_DOWN;
4769
4770         hns3_set_rxtx_function(eth_dev);
4771         rte_wmb();
4772         /* Disable datapath on secondary process. */
4773         hns3_mp_req_stop_rxtx(eth_dev);
4774         rte_delay_ms(hw->tqps_num);
4775
4776         rte_spinlock_lock(&hw->lock);
4777         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4778             hw->adapter_state == HNS3_NIC_STOPPING) {
4779                 hns3_do_stop(hns);
4780                 hw->reset.mbuf_deferred_free = true;
4781         } else
4782                 hw->reset.mbuf_deferred_free = false;
4783
4784         /*
4785          * It is cumbersome for hardware to pick-and-choose entries for deletion
4786          * from table space. Hence, for function reset software intervention is
4787          * required to delete the entries
4788          */
4789         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4790                 hns3_configure_all_mc_mac_addr(hns, true);
4791         rte_spinlock_unlock(&hw->lock);
4792
4793         return 0;
4794 }
4795
4796 static int
4797 hns3_start_service(struct hns3_adapter *hns)
4798 {
4799         struct hns3_hw *hw = &hns->hw;
4800         struct rte_eth_dev *eth_dev;
4801
4802         if (hw->reset.level == HNS3_IMP_RESET ||
4803             hw->reset.level == HNS3_GLOBAL_RESET)
4804                 hns3_set_rst_done(hw);
4805         eth_dev = &rte_eth_devices[hw->data->port_id];
4806         hns3_set_rxtx_function(eth_dev);
4807         hns3_mp_req_start_rxtx(eth_dev);
4808         if (hw->adapter_state == HNS3_NIC_STARTED)
4809                 hns3_service_handler(eth_dev);
4810
4811         return 0;
4812 }
4813
4814 static int
4815 hns3_restore_conf(struct hns3_adapter *hns)
4816 {
4817         struct hns3_hw *hw = &hns->hw;
4818         int ret;
4819
4820         ret = hns3_configure_all_mac_addr(hns, false);
4821         if (ret)
4822                 return ret;
4823
4824         ret = hns3_configure_all_mc_mac_addr(hns, false);
4825         if (ret)
4826                 goto err_mc_mac;
4827
4828         ret = hns3_dev_promisc_restore(hns);
4829         if (ret)
4830                 goto err_promisc;
4831
4832         ret = hns3_restore_vlan_table(hns);
4833         if (ret)
4834                 goto err_promisc;
4835
4836         ret = hns3_restore_vlan_conf(hns);
4837         if (ret)
4838                 goto err_promisc;
4839
4840         ret = hns3_restore_all_fdir_filter(hns);
4841         if (ret)
4842                 goto err_promisc;
4843
4844         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4845                 ret = hns3_do_start(hns, false);
4846                 if (ret)
4847                         goto err_promisc;
4848                 hns3_info(hw, "hns3 dev restart successful!");
4849         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4850                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4851         return 0;
4852
4853 err_promisc:
4854         hns3_configure_all_mc_mac_addr(hns, true);
4855 err_mc_mac:
4856         hns3_configure_all_mac_addr(hns, true);
4857         return ret;
4858 }
4859
4860 static void
4861 hns3_reset_service(void *param)
4862 {
4863         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4864         struct hns3_hw *hw = &hns->hw;
4865         enum hns3_reset_level reset_level;
4866         struct timeval tv_delta;
4867         struct timeval tv_start;
4868         struct timeval tv;
4869         uint64_t msec;
4870         int ret;
4871
4872         /*
4873          * The interrupt is not triggered within the delay time.
4874          * The interrupt may have been lost. It is necessary to handle
4875          * the interrupt to recover from the error.
4876          */
4877         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4878                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4879                 hns3_err(hw, "Handling interrupts in delayed tasks");
4880                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4881                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4882                 if (reset_level == HNS3_NONE_RESET) {
4883                         hns3_err(hw, "No reset level is set, try IMP reset");
4884                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4885                 }
4886         }
4887         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4888
4889         /*
4890          * Check if there is any ongoing reset in the hardware. This status can
4891          * be checked from reset_pending. If there is then, we need to wait for
4892          * hardware to complete reset.
4893          *    a. If we are able to figure out in reasonable time that hardware
4894          *       has fully resetted then, we can proceed with driver, client
4895          *       reset.
4896          *    b. else, we can come back later to check this status so re-sched
4897          *       now.
4898          */
4899         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4900         if (reset_level != HNS3_NONE_RESET) {
4901                 gettimeofday(&tv_start, NULL);
4902                 ret = hns3_reset_process(hns, reset_level);
4903                 gettimeofday(&tv, NULL);
4904                 timersub(&tv, &tv_start, &tv_delta);
4905                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4906                        tv_delta.tv_usec / USEC_PER_MSEC;
4907                 if (msec > HNS3_RESET_PROCESS_MS)
4908                         hns3_err(hw, "%d handle long time delta %" PRIx64
4909                                      " ms time=%ld.%.6ld",
4910                                  hw->reset.level, msec,
4911                                  tv.tv_sec, tv.tv_usec);
4912                 if (ret == -EAGAIN)
4913                         return;
4914         }
4915
4916         /* Check if we got any *new* reset requests to be honored */
4917         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4918         if (reset_level != HNS3_NONE_RESET)
4919                 hns3_msix_process(hns, reset_level);
4920 }
4921
4922 static const struct eth_dev_ops hns3_eth_dev_ops = {
4923         .dev_start          = hns3_dev_start,
4924         .dev_stop           = hns3_dev_stop,
4925         .dev_close          = hns3_dev_close,
4926         .promiscuous_enable = hns3_dev_promiscuous_enable,
4927         .promiscuous_disable = hns3_dev_promiscuous_disable,
4928         .allmulticast_enable  = hns3_dev_allmulticast_enable,
4929         .allmulticast_disable = hns3_dev_allmulticast_disable,
4930         .mtu_set            = hns3_dev_mtu_set,
4931         .stats_get          = hns3_stats_get,
4932         .stats_reset        = hns3_stats_reset,
4933         .xstats_get         = hns3_dev_xstats_get,
4934         .xstats_get_names   = hns3_dev_xstats_get_names,
4935         .xstats_reset       = hns3_dev_xstats_reset,
4936         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
4937         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4938         .dev_infos_get          = hns3_dev_infos_get,
4939         .fw_version_get         = hns3_fw_version_get,
4940         .rx_queue_setup         = hns3_rx_queue_setup,
4941         .tx_queue_setup         = hns3_tx_queue_setup,
4942         .rx_queue_release       = hns3_dev_rx_queue_release,
4943         .tx_queue_release       = hns3_dev_tx_queue_release,
4944         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
4945         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
4946         .dev_configure          = hns3_dev_configure,
4947         .flow_ctrl_get          = hns3_flow_ctrl_get,
4948         .flow_ctrl_set          = hns3_flow_ctrl_set,
4949         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4950         .mac_addr_add           = hns3_add_mac_addr,
4951         .mac_addr_remove        = hns3_remove_mac_addr,
4952         .mac_addr_set           = hns3_set_default_mac_addr,
4953         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
4954         .link_update            = hns3_dev_link_update,
4955         .rss_hash_update        = hns3_dev_rss_hash_update,
4956         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
4957         .reta_update            = hns3_dev_rss_reta_update,
4958         .reta_query             = hns3_dev_rss_reta_query,
4959         .filter_ctrl            = hns3_dev_filter_ctrl,
4960         .vlan_filter_set        = hns3_vlan_filter_set,
4961         .vlan_tpid_set          = hns3_vlan_tpid_set,
4962         .vlan_offload_set       = hns3_vlan_offload_set,
4963         .vlan_pvid_set          = hns3_vlan_pvid_set,
4964         .get_reg                = hns3_get_regs,
4965         .get_dcb_info           = hns3_get_dcb_info,
4966         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4967 };
4968
4969 static const struct hns3_reset_ops hns3_reset_ops = {
4970         .reset_service       = hns3_reset_service,
4971         .stop_service        = hns3_stop_service,
4972         .prepare_reset       = hns3_prepare_reset,
4973         .wait_hardware_ready = hns3_wait_hardware_ready,
4974         .reinit_dev          = hns3_reinit_dev,
4975         .restore_conf        = hns3_restore_conf,
4976         .start_service       = hns3_start_service,
4977 };
4978
4979 static int
4980 hns3_dev_init(struct rte_eth_dev *eth_dev)
4981 {
4982         struct rte_device *dev = eth_dev->device;
4983         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4984         struct hns3_adapter *hns = eth_dev->data->dev_private;
4985         struct hns3_hw *hw = &hns->hw;
4986         uint16_t device_id = pci_dev->id.device_id;
4987         int ret;
4988
4989         PMD_INIT_FUNC_TRACE();
4990         eth_dev->process_private = (struct hns3_process_private *)
4991             rte_zmalloc_socket("hns3_filter_list",
4992                                sizeof(struct hns3_process_private),
4993                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4994         if (eth_dev->process_private == NULL) {
4995                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4996                 return -ENOMEM;
4997         }
4998         /* initialize flow filter lists */
4999         hns3_filterlist_init(eth_dev);
5000
5001         hns3_set_rxtx_function(eth_dev);
5002         eth_dev->dev_ops = &hns3_eth_dev_ops;
5003         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5004                 hns3_mp_init_secondary();
5005                 hw->secondary_cnt++;
5006                 return 0;
5007         }
5008
5009         hns3_mp_init_primary();
5010         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5011
5012         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5013             device_id == HNS3_DEV_ID_50GE_RDMA ||
5014             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5015                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5016
5017         hns->is_vf = false;
5018         hw->data = eth_dev->data;
5019
5020         /*
5021          * Set default max packet size according to the mtu
5022          * default vale in DPDK frame.
5023          */
5024         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5025
5026         ret = hns3_reset_init(hw);
5027         if (ret)
5028                 goto err_init_reset;
5029         hw->reset.ops = &hns3_reset_ops;
5030
5031         ret = hns3_init_pf(eth_dev);
5032         if (ret) {
5033                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5034                 goto err_init_pf;
5035         }
5036
5037         /* Allocate memory for storing MAC addresses */
5038         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5039                                                sizeof(struct rte_ether_addr) *
5040                                                HNS3_UC_MACADDR_NUM, 0);
5041         if (eth_dev->data->mac_addrs == NULL) {
5042                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5043                              "to store MAC addresses",
5044                              sizeof(struct rte_ether_addr) *
5045                              HNS3_UC_MACADDR_NUM);
5046                 ret = -ENOMEM;
5047                 goto err_rte_zmalloc;
5048         }
5049
5050         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5051                             &eth_dev->data->mac_addrs[0]);
5052
5053         hw->adapter_state = HNS3_NIC_INITIALIZED;
5054         /*
5055          * Pass the information to the rte_eth_dev_close() that it should also
5056          * release the private port resources.
5057          */
5058         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5059
5060         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5061                 hns3_err(hw, "Reschedule reset service after dev_init");
5062                 hns3_schedule_reset(hns);
5063         } else {
5064                 /* IMP will wait ready flag before reset */
5065                 hns3_notify_reset_ready(hw, false);
5066         }
5067
5068         hns3_info(hw, "hns3 dev initialization successful!");
5069         return 0;
5070
5071 err_rte_zmalloc:
5072         hns3_uninit_pf(eth_dev);
5073
5074 err_init_pf:
5075         rte_free(hw->reset.wait_data);
5076 err_init_reset:
5077         eth_dev->dev_ops = NULL;
5078         eth_dev->rx_pkt_burst = NULL;
5079         eth_dev->tx_pkt_burst = NULL;
5080         eth_dev->tx_pkt_prepare = NULL;
5081         rte_free(eth_dev->process_private);
5082         eth_dev->process_private = NULL;
5083         return ret;
5084 }
5085
5086 static int
5087 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5088 {
5089         struct hns3_adapter *hns = eth_dev->data->dev_private;
5090         struct hns3_hw *hw = &hns->hw;
5091
5092         PMD_INIT_FUNC_TRACE();
5093
5094         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5095                 return -EPERM;
5096
5097         eth_dev->dev_ops = NULL;
5098         eth_dev->rx_pkt_burst = NULL;
5099         eth_dev->tx_pkt_burst = NULL;
5100         eth_dev->tx_pkt_prepare = NULL;
5101         if (hw->adapter_state < HNS3_NIC_CLOSING)
5102                 hns3_dev_close(eth_dev);
5103
5104         hw->adapter_state = HNS3_NIC_REMOVED;
5105         return 0;
5106 }
5107
5108 static int
5109 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5110                    struct rte_pci_device *pci_dev)
5111 {
5112         return rte_eth_dev_pci_generic_probe(pci_dev,
5113                                              sizeof(struct hns3_adapter),
5114                                              hns3_dev_init);
5115 }
5116
5117 static int
5118 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5119 {
5120         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5121 }
5122
5123 static const struct rte_pci_id pci_id_hns3_map[] = {
5124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5129         { .vendor_id = 0, /* sentinel */ },
5130 };
5131
5132 static struct rte_pci_driver rte_hns3_pmd = {
5133         .id_table = pci_id_hns3_map,
5134         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5135         .probe = eth_hns3_pci_probe,
5136         .remove = eth_hns3_pci_remove,
5137 };
5138
5139 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5140 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5141 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5142
5143 RTE_INIT(hns3_init_log)
5144 {
5145         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5146         if (hns3_logtype_init >= 0)
5147                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5148         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5149         if (hns3_logtype_driver >= 0)
5150                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5151 }