drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80 static int hns3_update_speed_duplex(struct rte_eth_dev *eth_dev);
  81
  82 static void
  83 hns3_pf_disable_irq0(struct hns3_hw *hw)
  84 {
  85         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  86 }
  87
  88 static void
  89 hns3_pf_enable_irq0(struct hns3_hw *hw)
  90 {
  91         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  92 }
  93
  94 static enum hns3_evt_cause
  95 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  96 {
  97         struct hns3_hw *hw = &hns->hw;
  98         uint32_t vector0_int_stats;
  99         uint32_t cmdq_src_val;
 100         uint32_t val;
 101         enum hns3_evt_cause ret;
 102
 103         /* fetch the events from their corresponding regs */
 104         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 105         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 106
 107         /*
 108          * Assumption: If by any chance reset and mailbox events are reported
 109          * together then we will only process reset event and defer the
 110          * processing of the mailbox events. Since, we would have not cleared
 111          * RX CMDQ event this time we would receive again another interrupt
 112          * from H/W just for the mailbox.
 113          */
 114         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 115                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 116                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 117                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 118                 if (clearval) {
 119                         hw->reset.stats.imp_cnt++;
 120                         hns3_warn(hw, "IMP reset detected, clear reset status");
 121                 } else {
 122                         hns3_schedule_delayed_reset(hns);
 123                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 124                 }
 125
 126                 ret = HNS3_VECTOR0_EVENT_RST;
 127                 goto out;
 128         }
 129
 130         /* Global reset */
 131         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 132                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 133                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 134                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 135                 if (clearval) {
 136                         hw->reset.stats.global_cnt++;
 137                         hns3_warn(hw, "Global reset detected, clear reset status");
 138                 } else {
 139                         hns3_schedule_delayed_reset(hns);
 140                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 141                 }
 142
 143                 ret = HNS3_VECTOR0_EVENT_RST;
 144                 goto out;
 145         }
 146
 147         /* check for vector0 msix event source */
 148         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 149                 val = vector0_int_stats;
 150                 ret = HNS3_VECTOR0_EVENT_ERR;
 151                 goto out;
 152         }
 153
 154         /* check for vector0 mailbox(=CMDQ RX) event source */
 155         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 156                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 157                 val = cmdq_src_val;
 158                 ret = HNS3_VECTOR0_EVENT_MBX;
 159                 goto out;
 160         }
 161
 162         if (clearval && (vector0_int_stats || cmdq_src_val))
 163                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 164                           vector0_int_stats, cmdq_src_val);
 165         val = vector0_int_stats;
 166         ret = HNS3_VECTOR0_EVENT_OTHER;
 167 out:
 168
 169         if (clearval)
 170                 *clearval = val;
 171         return ret;
 172 }
 173
 174 static void
 175 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 176 {
 177         if (event_type == HNS3_VECTOR0_EVENT_RST)
 178                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 179         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 180                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 181 }
 182
 183 static void
 184 hns3_clear_all_event_cause(struct hns3_hw *hw)
 185 {
 186         uint32_t vector0_int_stats;
 187         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 188
 189         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 190                 hns3_warn(hw, "Probe during IMP reset interrupt");
 191
 192         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 193                 hns3_warn(hw, "Probe during Global reset interrupt");
 194
 195         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 196                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 198                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 199         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 200 }
 201
 202 static void
 203 hns3_interrupt_handler(void *param)
 204 {
 205         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 206         struct hns3_adapter *hns = dev->data->dev_private;
 207         struct hns3_hw *hw = &hns->hw;
 208         enum hns3_evt_cause event_cause;
 209         uint32_t clearval = 0;
 210
 211         /* Disable interrupt */
 212         hns3_pf_disable_irq0(hw);
 213
 214         event_cause = hns3_check_event_cause(hns, &clearval);
 215
 216         /* vector 0 interrupt is shared with reset and mailbox source events. */
 217         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 218                 hns3_handle_msix_error(hns, &hw->reset.request);
 219                 hns3_schedule_reset(hns);
 220         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 221                 hns3_schedule_reset(hns);
 222         else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
 223                 hns3_dev_handle_mbx_msg(hw);
 224         else
 225                 hns3_err(hw, "Received unknown event");
 226
 227         hns3_clear_event_cause(hw, event_cause, clearval);
 228         /* Enable interrupt if it is not cause by reset */
 229         hns3_pf_enable_irq0(hw);
 230 }
 231
 232 static int
 233 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 234 {
 235 #define HNS3_VLAN_OFFSET_160            160
 236         struct hns3_vlan_filter_pf_cfg_cmd *req;
 237         struct hns3_hw *hw = &hns->hw;
 238         uint8_t vlan_offset_byte_val;
 239         struct hns3_cmd_desc desc;
 240         uint8_t vlan_offset_byte;
 241         uint8_t vlan_offset_160;
 242         int ret;
 243
 244         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 245
 246         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 247         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 248         vlan_offset_byte_val = 1 << (vlan_id % 8);
 249
 250         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 251         req->vlan_offset = vlan_offset_160;
 252         req->vlan_cfg = on ? 0 : 1;
 253         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 254
 255         ret = hns3_cmd_send(hw, &desc, 1);
 256         if (ret)
 257                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 258                          vlan_id, ret);
 259
 260         return ret;
 261 }
 262
 263 static void
 264 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 265 {
 266         struct hns3_user_vlan_table *vlan_entry;
 267         struct hns3_pf *pf = &hns->pf;
 268
 269         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 270                 if (vlan_entry->vlan_id == vlan_id) {
 271                         if (vlan_entry->hd_tbl_status)
 272                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 273                         LIST_REMOVE(vlan_entry, next);
 274                         rte_free(vlan_entry);
 275                         break;
 276                 }
 277         }
 278 }
 279
 280 static void
 281 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 282                         bool writen_to_tbl)
 283 {
 284         struct hns3_user_vlan_table *vlan_entry;
 285         struct hns3_hw *hw = &hns->hw;
 286         struct hns3_pf *pf = &hns->pf;
 287
 288         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 289                 if (vlan_entry->vlan_id == vlan_id)
 290                         return;
 291         }
 292
 293         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 294         if (vlan_entry == NULL) {
 295                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 296                 return;
 297         }
 298
 299         vlan_entry->hd_tbl_status = writen_to_tbl;
 300         vlan_entry->vlan_id = vlan_id;
 301
 302         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 303 }
 304
 305 static int
 306 hns3_restore_vlan_table(struct hns3_adapter *hns)
 307 {
 308         struct hns3_user_vlan_table *vlan_entry;
 309         struct hns3_pf *pf = &hns->pf;
 310         uint16_t vlan_id;
 311         int ret = 0;
 312
 313         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 314                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 315                                                1);
 316                 return ret;
 317         }
 318
 319         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 320                 if (vlan_entry->hd_tbl_status) {
 321                         vlan_id = vlan_entry->vlan_id;
 322                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 323                         if (ret)
 324                                 break;
 325                 }
 326         }
 327
 328         return ret;
 329 }
 330
 331 static int
 332 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 333 {
 334         struct hns3_pf *pf = &hns->pf;
 335         bool writen_to_tbl = false;
 336         int ret = 0;
 337
 338         /*
 339          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 340          * for normal packet, deleting vlan id 0 is not allowed.
 341          */
 342         if (on == 0 && vlan_id == 0)
 343                 return 0;
 344
 345         /*
 346          * When port base vlan enabled, we use port base vlan as the vlan
 347          * filter condition. In this case, we don't update vlan filter table
 348          * when user add new vlan or remove exist vlan, just update the
 349          * vlan list. The vlan id in vlan list will be writen in vlan filter
 350          * table until port base vlan disabled
 351          */
 352         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 353                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 354                 writen_to_tbl = true;
 355         }
 356
 357         if (ret == 0 && vlan_id) {
 358                 if (on)
 359                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 360                 else
 361                         hns3_rm_dev_vlan_table(hns, vlan_id);
 362         }
 363         return ret;
 364 }
 365
 366 static int
 367 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 368 {
 369         struct hns3_adapter *hns = dev->data->dev_private;
 370         struct hns3_hw *hw = &hns->hw;
 371         int ret;
 372
 373         rte_spinlock_lock(&hw->lock);
 374         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 375         rte_spinlock_unlock(&hw->lock);
 376         return ret;
 377 }
 378
 379 static int
 380 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 381                          uint16_t tpid)
 382 {
 383         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 384         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 385         struct hns3_hw *hw = &hns->hw;
 386         struct hns3_cmd_desc desc;
 387         int ret;
 388
 389         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 390              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 391                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 392                 return -EINVAL;
 393         }
 394
 395         if (tpid != RTE_ETHER_TYPE_VLAN) {
 396                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 397                 return -EINVAL;
 398         }
 399
 400         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 401         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 402
 403         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 404                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 405                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 406         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 407                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 408                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 409                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 410                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 411         }
 412
 413         ret = hns3_cmd_send(hw, &desc, 1);
 414         if (ret) {
 415                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 416                          ret);
 417                 return ret;
 418         }
 419
 420         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 421
 422         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 423         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 424         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 425
 426         ret = hns3_cmd_send(hw, &desc, 1);
 427         if (ret)
 428                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 429                          ret);
 430         return ret;
 431 }
 432
 433 static int
 434 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 435                    uint16_t tpid)
 436 {
 437         struct hns3_adapter *hns = dev->data->dev_private;
 438         struct hns3_hw *hw = &hns->hw;
 439         int ret;
 440
 441         rte_spinlock_lock(&hw->lock);
 442         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 443         rte_spinlock_unlock(&hw->lock);
 444         return ret;
 445 }
 446
 447 static int
 448 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 449                              struct hns3_rx_vtag_cfg *vcfg)
 450 {
 451         struct hns3_vport_vtag_rx_cfg_cmd *req;
 452         struct hns3_hw *hw = &hns->hw;
 453         struct hns3_cmd_desc desc;
 454         uint16_t vport_id;
 455         uint8_t bitmap;
 456         int ret;
 457
 458         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 459
 460         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 461         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 462                      vcfg->strip_tag1_en ? 1 : 0);
 463         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 464                      vcfg->strip_tag2_en ? 1 : 0);
 465         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 466                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 467         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 468                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 469
 470         /*
 471          * In current version VF is not supported when PF is driven by DPDK
 472          * driver, the PF-related vf_id is 0, just need to configure parameters
 473          * for vport_id 0.
 474          */
 475         vport_id = 0;
 476         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 477         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 478         req->vf_bitmap[req->vf_offset] = bitmap;
 479
 480         ret = hns3_cmd_send(hw, &desc, 1);
 481         if (ret)
 482                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 483         return ret;
 484 }
 485
 486 static void
 487 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_rx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 492 }
 493
 494 static void
 495 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 496                            struct hns3_tx_vtag_cfg *vcfg)
 497 {
 498         struct hns3_pf *pf = &hns->pf;
 499         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 500 }
 501
 502 static int
 503 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 504 {
 505         struct hns3_rx_vtag_cfg rxvlan_cfg;
 506         struct hns3_pf *pf = &hns->pf;
 507         struct hns3_hw *hw = &hns->hw;
 508         int ret;
 509
 510         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 511                 rxvlan_cfg.strip_tag1_en = false;
 512                 rxvlan_cfg.strip_tag2_en = enable;
 513         } else {
 514                 rxvlan_cfg.strip_tag1_en = enable;
 515                 rxvlan_cfg.strip_tag2_en = true;
 516         }
 517
 518         rxvlan_cfg.vlan1_vlan_prionly = false;
 519         rxvlan_cfg.vlan2_vlan_prionly = false;
 520         rxvlan_cfg.rx_vlan_offload_en = enable;
 521
 522         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 523         if (ret) {
 524                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 525                 return ret;
 526         }
 527
 528         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 529
 530         return ret;
 531 }
 532
 533 static int
 534 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 535                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 536 {
 537         struct hns3_vlan_filter_ctrl_cmd *req;
 538         struct hns3_cmd_desc desc;
 539         int ret;
 540
 541         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 542
 543         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 544         req->vlan_type = vlan_type;
 545         req->vlan_fe = filter_en ? fe_type : 0;
 546         req->vf_id = vf_id;
 547
 548         ret = hns3_cmd_send(hw, &desc, 1);
 549         if (ret)
 550                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 551
 552         return ret;
 553 }
 554
 555 static int
 556 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 557 {
 558         struct hns3_hw *hw = &hns->hw;
 559         int ret;
 560
 561         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 562                                         HNS3_FILTER_FE_EGRESS, false, 0);
 563         if (ret) {
 564                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 565                 return ret;
 566         }
 567
 568         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 569                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 570         if (ret)
 571                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 572
 573         return ret;
 574 }
 575
 576 static int
 577 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 578 {
 579         struct hns3_adapter *hns = dev->data->dev_private;
 580         struct hns3_hw *hw = &hns->hw;
 581         struct rte_eth_rxmode *rxmode;
 582         unsigned int tmp_mask;
 583         bool enable;
 584         int ret = 0;
 585
 586         rte_spinlock_lock(&hw->lock);
 587         rxmode = &dev->data->dev_conf.rxmode;
 588         tmp_mask = (unsigned int)mask;
 589         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 590                 /* Enable or disable VLAN stripping */
 591                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 592                     true : false;
 593
 594                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 595                 if (ret) {
 596                         rte_spinlock_unlock(&hw->lock);
 597                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 598                         return ret;
 599                 }
 600         }
 601
 602         rte_spinlock_unlock(&hw->lock);
 603
 604         return ret;
 605 }
 606
 607 static int
 608 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 609                              struct hns3_tx_vtag_cfg *vcfg)
 610 {
 611         struct hns3_vport_vtag_tx_cfg_cmd *req;
 612         struct hns3_cmd_desc desc;
 613         struct hns3_hw *hw = &hns->hw;
 614         uint16_t vport_id;
 615         uint8_t bitmap;
 616         int ret;
 617
 618         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 619
 620         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 621         req->def_vlan_tag1 = vcfg->default_tag1;
 622         req->def_vlan_tag2 = vcfg->default_tag2;
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 624                      vcfg->accept_tag1 ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 626                      vcfg->accept_untag1 ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 628                      vcfg->accept_tag2 ? 1 : 0);
 629         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 630                      vcfg->accept_untag2 ? 1 : 0);
 631         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 632                      vcfg->insert_tag1_en ? 1 : 0);
 633         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 634                      vcfg->insert_tag2_en ? 1 : 0);
 635         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 636
 637         /*
 638          * In current version VF is not supported when PF is driven by DPDK
 639          * driver, the PF-related vf_id is 0, just need to configure parameters
 640          * for vport_id 0.
 641          */
 642         vport_id = 0;
 643         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 644         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 645         req->vf_bitmap[req->vf_offset] = bitmap;
 646
 647         ret = hns3_cmd_send(hw, &desc, 1);
 648         if (ret)
 649                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 650
 651         return ret;
 652 }
 653
 654 static int
 655 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 656                      uint16_t pvid)
 657 {
 658         struct hns3_hw *hw = &hns->hw;
 659         struct hns3_tx_vtag_cfg txvlan_cfg;
 660         int ret;
 661
 662         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 663                 txvlan_cfg.accept_tag1 = true;
 664                 txvlan_cfg.insert_tag1_en = false;
 665                 txvlan_cfg.default_tag1 = 0;
 666         } else {
 667                 txvlan_cfg.accept_tag1 = false;
 668                 txvlan_cfg.insert_tag1_en = true;
 669                 txvlan_cfg.default_tag1 = pvid;
 670         }
 671
 672         txvlan_cfg.accept_untag1 = true;
 673         txvlan_cfg.accept_tag2 = true;
 674         txvlan_cfg.accept_untag2 = true;
 675         txvlan_cfg.insert_tag2_en = false;
 676         txvlan_cfg.default_tag2 = 0;
 677
 678         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 679         if (ret) {
 680                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 681                          ret);
 682                 return ret;
 683         }
 684
 685         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 686         return ret;
 687 }
 688
 689 static void
 690 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 691 {
 692         struct hns3_pf *pf = &hns->pf;
 693
 694         pf->port_base_vlan_cfg.state = on ?
 695             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 696
 697         pf->port_base_vlan_cfg.pvid = pvid;
 698 }
 699
 700 static void
 701 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 702 {
 703         struct hns3_user_vlan_table *vlan_entry;
 704         struct hns3_pf *pf = &hns->pf;
 705
 706         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 707                 if (vlan_entry->hd_tbl_status)
 708                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 709
 710                 vlan_entry->hd_tbl_status = false;
 711         }
 712
 713         if (is_del_list) {
 714                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 715                 while (vlan_entry) {
 716                         LIST_REMOVE(vlan_entry, next);
 717                         rte_free(vlan_entry);
 718                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 719                 }
 720         }
 721 }
 722
 723 static void
 724 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 725 {
 726         struct hns3_user_vlan_table *vlan_entry;
 727         struct hns3_pf *pf = &hns->pf;
 728
 729         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 730                 if (!vlan_entry->hd_tbl_status)
 731                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 732
 733                 vlan_entry->hd_tbl_status = true;
 734         }
 735 }
 736
 737 static void
 738 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         struct hns3_pf *pf = &hns->pf;
 742         int ret;
 743
 744         hns3_rm_all_vlan_table(hns, true);
 745         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 746                 ret = hns3_set_port_vlan_filter(hns,
 747                                                 pf->port_base_vlan_cfg.pvid, 0);
 748                 if (ret) {
 749                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 750                                  ret);
 751                         return;
 752                 }
 753         }
 754 }
 755
 756 static int
 757 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 758                                 uint16_t port_base_vlan_state,
 759                                 uint16_t new_pvid, uint16_t old_pvid)
 760 {
 761         struct hns3_pf *pf = &hns->pf;
 762         struct hns3_hw *hw = &hns->hw;
 763         int ret = 0;
 764
 765         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 766                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 767                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 768                         if (ret) {
 769                                 hns3_err(hw,
 770                                          "Failed to clear clear old pvid filter, ret =%d",
 771                                          ret);
 772                                 return ret;
 773                         }
 774                 }
 775
 776                 hns3_rm_all_vlan_table(hns, false);
 777                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 778         }
 779
 780         if (new_pvid != 0) {
 781                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 782                 if (ret) {
 783                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 784                                  ret);
 785                         return ret;
 786                 }
 787         }
 788
 789         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 790                 hns3_add_all_vlan_table(hns);
 791
 792         return ret;
 793 }
 794
 795 static int
 796 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 797 {
 798         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 799         struct hns3_hw *hw = &hns->hw;
 800         bool rx_strip_en;
 801         int ret;
 802
 803         rx_strip_en = on ? true : false;
 804         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 805         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 806         rx_vlan_cfg.vlan1_vlan_prionly = false;
 807         rx_vlan_cfg.vlan2_vlan_prionly = false;
 808         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 809
 810         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 811         if (ret) {
 812                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 813                 return ret;
 814         }
 815
 816         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 817         return ret;
 818 }
 819
 820 static int
 821 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 822 {
 823         struct hns3_pf *pf = &hns->pf;
 824         struct hns3_hw *hw = &hns->hw;
 825         uint16_t port_base_vlan_state;
 826         uint16_t old_pvid;
 827         int ret;
 828
 829         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 830                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 831                         hns3_warn(hw, "Invalid operation! As current pvid set "
 832                                   "is %u, disable pvid %u is invalid",
 833                                   pf->port_base_vlan_cfg.pvid, pvid);
 834                 return 0;
 835         }
 836
 837         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 838                                     HNS3_PORT_BASE_VLAN_DISABLE;
 839         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 840         if (ret) {
 841                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 842                 return ret;
 843         }
 844
 845         ret = hns3_en_rx_strip_all(hns, on);
 846         if (ret) {
 847                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 848                 return ret;
 849         }
 850
 851         if (pvid == HNS3_INVLID_PVID)
 852                 goto out;
 853         old_pvid = pf->port_base_vlan_cfg.pvid;
 854         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 855                                               old_pvid);
 856         if (ret) {
 857                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 858                          ret);
 859                 return ret;
 860         }
 861
 862 out:
 863         hns3_store_port_base_vlan_info(hns, pvid, on);
 864         return ret;
 865 }
 866
 867 static int
 868 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 869 {
 870         struct hns3_adapter *hns = dev->data->dev_private;
 871         struct hns3_hw *hw = &hns->hw;
 872         int ret;
 873
 874         rte_spinlock_lock(&hw->lock);
 875         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 876         rte_spinlock_unlock(&hw->lock);
 877         return ret;
 878 }
 879
 880 static void
 881 init_port_base_vlan_info(struct hns3_hw *hw)
 882 {
 883         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 884         struct hns3_pf *pf = &hns->pf;
 885
 886         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 887         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 888 }
 889
 890 static int
 891 hns3_default_vlan_config(struct hns3_adapter *hns)
 892 {
 893         struct hns3_hw *hw = &hns->hw;
 894         int ret;
 895
 896         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 897         if (ret)
 898                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 899         return ret;
 900 }
 901
 902 static int
 903 hns3_init_vlan_config(struct hns3_adapter *hns)
 904 {
 905         struct hns3_hw *hw = &hns->hw;
 906         int ret;
 907
 908         /*
 909          * This function can be called in the initialization and reset process,
 910          * when in reset process, it means that hardware had been reseted
 911          * successfully and we need to restore the hardware configuration to
 912          * ensure that the hardware configuration remains unchanged before and
 913          * after reset.
 914          */
 915         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 916                 init_port_base_vlan_info(hw);
 917
 918         ret = hns3_enable_vlan_filter(hns, true);
 919         if (ret) {
 920                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 921                 return ret;
 922         }
 923
 924         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 925                                        RTE_ETHER_TYPE_VLAN);
 926         if (ret) {
 927                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 928                 return ret;
 929         }
 930
 931         /*
 932          * When in the reinit dev stage of the reset process, the following
 933          * vlan-related configurations may differ from those at initialization,
 934          * we will restore configurations to hardware in hns3_restore_vlan_table
 935          * and hns3_restore_vlan_conf later.
 936          */
 937         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 938                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 939                 if (ret) {
 940                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 941                         return ret;
 942                 }
 943
 944                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 945                 if (ret) {
 946                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 947                                  ret);
 948                         return ret;
 949                 }
 950         }
 951
 952         return hns3_default_vlan_config(hns);
 953 }
 954
 955 static int
 956 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 957 {
 958         struct hns3_pf *pf = &hns->pf;
 959         struct hns3_hw *hw = &hns->hw;
 960         int ret;
 961
 962         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 963         if (ret) {
 964                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 965                 return ret;
 966         }
 967
 968         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 969         if (ret)
 970                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 977 {
 978         struct hns3_adapter *hns = dev->data->dev_private;
 979         struct rte_eth_dev_data *data = dev->data;
 980         struct rte_eth_txmode *txmode;
 981         struct hns3_hw *hw = &hns->hw;
 982         int ret;
 983
 984         txmode = &data->dev_conf.txmode;
 985         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 986                 hns3_warn(hw,
 987                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 988                           "configuration is not supported! Ignore these two "
 989                           "parameters: hw_vlan_reject_tagged(%d), "
 990                           "hw_vlan_reject_untagged(%d)",
 991                           txmode->hw_vlan_reject_tagged,
 992                           txmode->hw_vlan_reject_untagged);
 993
 994         /* Apply vlan offload setting */
 995         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 996         if (ret) {
 997                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 998                 return ret;
 999         }
1000
1001         /* Apply pvid setting */
1002         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
1003                                  txmode->hw_vlan_insert_pvid);
1004         if (ret)
1005                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
1006                          txmode->pvid, ret);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1013                 unsigned int tso_mss_max)
1014 {
1015         struct hns3_cfg_tso_status_cmd *req;
1016         struct hns3_cmd_desc desc;
1017         uint16_t tso_mss;
1018
1019         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1020
1021         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1022
1023         tso_mss = 0;
1024         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1025                        tso_mss_min);
1026         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1027
1028         tso_mss = 0;
1029         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1030                        tso_mss_max);
1031         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1032
1033         return hns3_cmd_send(hw, &desc, 1);
1034 }
1035
1036 int
1037 hns3_config_gro(struct hns3_hw *hw, bool en)
1038 {
1039         struct hns3_cfg_gro_status_cmd *req;
1040         struct hns3_cmd_desc desc;
1041         int ret;
1042
1043         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1044         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1045
1046         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1047
1048         ret = hns3_cmd_send(hw, &desc, 1);
1049         if (ret)
1050                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1057                    uint16_t *allocated_size, bool is_alloc)
1058 {
1059         struct hns3_umv_spc_alc_cmd *req;
1060         struct hns3_cmd_desc desc;
1061         int ret;
1062
1063         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1064         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1065         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1066         req->space_size = rte_cpu_to_le_32(space_size);
1067
1068         ret = hns3_cmd_send(hw, &desc, 1);
1069         if (ret) {
1070                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1071                              is_alloc ? "allocate" : "free", ret);
1072                 return ret;
1073         }
1074
1075         if (is_alloc && allocated_size)
1076                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1077
1078         return 0;
1079 }
1080
1081 static int
1082 hns3_init_umv_space(struct hns3_hw *hw)
1083 {
1084         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1085         struct hns3_pf *pf = &hns->pf;
1086         uint16_t allocated_size = 0;
1087         int ret;
1088
1089         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1090                                  true);
1091         if (ret)
1092                 return ret;
1093
1094         if (allocated_size < pf->wanted_umv_size)
1095                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1096                              pf->wanted_umv_size, allocated_size);
1097
1098         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1099                                                 pf->wanted_umv_size;
1100         pf->used_umv_size = 0;
1101         return 0;
1102 }
1103
1104 static int
1105 hns3_uninit_umv_space(struct hns3_hw *hw)
1106 {
1107         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1108         struct hns3_pf *pf = &hns->pf;
1109         int ret;
1110
1111         if (pf->max_umv_size == 0)
1112                 return 0;
1113
1114         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1115         if (ret)
1116                 return ret;
1117
1118         pf->max_umv_size = 0;
1119
1120         return 0;
1121 }
1122
1123 static bool
1124 hns3_is_umv_space_full(struct hns3_hw *hw)
1125 {
1126         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1127         struct hns3_pf *pf = &hns->pf;
1128         bool is_full;
1129
1130         is_full = (pf->used_umv_size >= pf->max_umv_size);
1131
1132         return is_full;
1133 }
1134
1135 static void
1136 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1137 {
1138         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1139         struct hns3_pf *pf = &hns->pf;
1140
1141         if (is_free) {
1142                 if (pf->used_umv_size > 0)
1143                         pf->used_umv_size--;
1144         } else
1145                 pf->used_umv_size++;
1146 }
1147
1148 static void
1149 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1150                       const uint8_t *addr, bool is_mc)
1151 {
1152         const unsigned char *mac_addr = addr;
1153         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1154                             ((uint32_t)mac_addr[2] << 16) |
1155                             ((uint32_t)mac_addr[1] << 8) |
1156                             (uint32_t)mac_addr[0];
1157         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1158
1159         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1160         if (is_mc) {
1161                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1162                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1163                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1164         }
1165
1166         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1167         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1168 }
1169
1170 static int
1171 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1172                              uint8_t resp_code,
1173                              enum hns3_mac_vlan_tbl_opcode op)
1174 {
1175         if (cmdq_resp) {
1176                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1177                          cmdq_resp);
1178                 return -EIO;
1179         }
1180
1181         if (op == HNS3_MAC_VLAN_ADD) {
1182                 if (resp_code == 0 || resp_code == 1) {
1183                         return 0;
1184                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1185                         hns3_err(hw, "add mac addr failed for uc_overflow");
1186                         return -ENOSPC;
1187                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1188                         hns3_err(hw, "add mac addr failed for mc_overflow");
1189                         return -ENOSPC;
1190                 }
1191
1192                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1193                          resp_code);
1194                 return -EIO;
1195         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1196                 if (resp_code == 0) {
1197                         return 0;
1198                 } else if (resp_code == 1) {
1199                         hns3_dbg(hw, "remove mac addr failed for miss");
1200                         return -ENOENT;
1201                 }
1202
1203                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1204                          resp_code);
1205                 return -EIO;
1206         } else if (op == HNS3_MAC_VLAN_LKUP) {
1207                 if (resp_code == 0) {
1208                         return 0;
1209                 } else if (resp_code == 1) {
1210                         hns3_dbg(hw, "lookup mac addr failed for miss");
1211                         return -ENOENT;
1212                 }
1213
1214                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1215                          resp_code);
1216                 return -EIO;
1217         }
1218
1219         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1220                  op);
1221
1222         return -EINVAL;
1223 }
1224
1225 static int
1226 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1227                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1228                          struct hns3_cmd_desc *desc, bool is_mc)
1229 {
1230         uint8_t resp_code;
1231         uint16_t retval;
1232         int ret;
1233
1234         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1235         if (is_mc) {
1236                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1237                 memcpy(desc[0].data, req,
1238                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1239                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1240                                           true);
1241                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1242                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1243                                           true);
1244                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1245         } else {
1246                 memcpy(desc[0].data, req,
1247                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1248                 ret = hns3_cmd_send(hw, desc, 1);
1249         }
1250         if (ret) {
1251                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1252                          ret);
1253                 return ret;
1254         }
1255         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1256         retval = rte_le_to_cpu_16(desc[0].retval);
1257
1258         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1259                                             HNS3_MAC_VLAN_LKUP);
1260 }
1261
1262 static int
1263 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1264                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1265                       struct hns3_cmd_desc *mc_desc)
1266 {
1267         uint8_t resp_code;
1268         uint16_t retval;
1269         int cfg_status;
1270         int ret;
1271
1272         if (mc_desc == NULL) {
1273                 struct hns3_cmd_desc desc;
1274
1275                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1276                 memcpy(desc.data, req,
1277                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1278                 ret = hns3_cmd_send(hw, &desc, 1);
1279                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1280                 retval = rte_le_to_cpu_16(desc.retval);
1281
1282                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1283                                                           HNS3_MAC_VLAN_ADD);
1284         } else {
1285                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1286                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1287                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1288                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1289                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1290                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1291                 memcpy(mc_desc[0].data, req,
1292                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1293                 mc_desc[0].retval = 0;
1294                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1295                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1296                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1297
1298                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1299                                                           HNS3_MAC_VLAN_ADD);
1300         }
1301
1302         if (ret) {
1303                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1304                 return ret;
1305         }
1306
1307         return cfg_status;
1308 }
1309
1310 static int
1311 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1312                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1313 {
1314         struct hns3_cmd_desc desc;
1315         uint8_t resp_code;
1316         uint16_t retval;
1317         int ret;
1318
1319         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1320
1321         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1322
1323         ret = hns3_cmd_send(hw, &desc, 1);
1324         if (ret) {
1325                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1326                 return ret;
1327         }
1328         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1329         retval = rte_le_to_cpu_16(desc.retval);
1330
1331         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1332                                             HNS3_MAC_VLAN_REMOVE);
1333 }
1334
1335 static int
1336 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1337 {
1338         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1339         struct hns3_mac_vlan_tbl_entry_cmd req;
1340         struct hns3_pf *pf = &hns->pf;
1341         struct hns3_cmd_desc desc;
1342         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1343         uint16_t egress_port = 0;
1344         uint8_t vf_id;
1345         int ret;
1346
1347         /* check if mac addr is valid */
1348         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1349                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1350                                       mac_addr);
1351                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1352                          mac_str);
1353                 return -EINVAL;
1354         }
1355
1356         memset(&req, 0, sizeof(req));
1357
1358         /*
1359          * In current version VF is not supported when PF is driven by DPDK
1360          * driver, the PF-related vf_id is 0, just need to configure parameters
1361          * for vf_id 0.
1362          */
1363         vf_id = 0;
1364         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1365                        HNS3_MAC_EPORT_VFID_S, vf_id);
1366
1367         req.egress_port = rte_cpu_to_le_16(egress_port);
1368
1369         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1370
1371         /*
1372          * Lookup the mac address in the mac_vlan table, and add
1373          * it if the entry is inexistent. Repeated unicast entry
1374          * is not allowed in the mac vlan table.
1375          */
1376         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1377         if (ret == -ENOENT) {
1378                 if (!hns3_is_umv_space_full(hw)) {
1379                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1380                         if (!ret)
1381                                 hns3_update_umv_space(hw, false);
1382                         return ret;
1383                 }
1384
1385                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1386
1387                 return -ENOSPC;
1388         }
1389
1390         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1391
1392         /* check if we just hit the duplicate */
1393         if (ret == 0) {
1394                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1395                 return 0;
1396         }
1397
1398         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1399                  mac_str);
1400
1401         return ret;
1402 }
1403
1404 static int
1405 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1406                   uint32_t idx, __rte_unused uint32_t pool)
1407 {
1408         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1410         int ret;
1411
1412         rte_spinlock_lock(&hw->lock);
1413         ret = hns3_add_uc_addr_common(hw, mac_addr);
1414         if (ret) {
1415                 rte_spinlock_unlock(&hw->lock);
1416                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1417                                       mac_addr);
1418                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1419                 return ret;
1420         }
1421
1422         if (idx == 0)
1423                 hw->mac.default_addr_setted = true;
1424         rte_spinlock_unlock(&hw->lock);
1425
1426         return ret;
1427 }
1428
1429 static int
1430 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1431 {
1432         struct hns3_mac_vlan_tbl_entry_cmd req;
1433         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1434         int ret;
1435
1436         /* check if mac addr is valid */
1437         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1438                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1439                                       mac_addr);
1440                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1441                          mac_str);
1442                 return -EINVAL;
1443         }
1444
1445         memset(&req, 0, sizeof(req));
1446         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1447         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1448         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1449         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1450                 return 0;
1451         else if (ret == 0)
1452                 hns3_update_umv_space(hw, true);
1453
1454         return ret;
1455 }
1456
1457 static void
1458 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1459 {
1460         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         /* index will be checked by upper level rte interface */
1462         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1463         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1464         int ret;
1465
1466         rte_spinlock_lock(&hw->lock);
1467         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1468         if (ret) {
1469                 rte_spinlock_unlock(&hw->lock);
1470                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1471                                       mac_addr);
1472                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1473                 return;
1474         }
1475
1476         rte_spinlock_unlock(&hw->lock);
1477 }
1478
1479 static int
1480 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1481                           struct rte_ether_addr *mac_addr)
1482 {
1483         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1484         struct rte_ether_addr *oaddr;
1485         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1486         bool default_addr_setted;
1487         bool rm_succes = false;
1488         int ret, ret_val;
1489
1490         /* check if mac addr is valid */
1491         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1492                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1493                                       mac_addr);
1494                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1495                          mac_str);
1496                 return -EINVAL;
1497         }
1498
1499         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1500         default_addr_setted = hw->mac.default_addr_setted;
1501         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1502                 return 0;
1503
1504         rte_spinlock_lock(&hw->lock);
1505         if (default_addr_setted) {
1506                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1507                 if (ret) {
1508                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1509                                               oaddr);
1510                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1511                                   mac_str, ret);
1512                         rm_succes = false;
1513                 } else
1514                         rm_succes = true;
1515         }
1516
1517         ret = hns3_add_uc_addr_common(hw, mac_addr);
1518         if (ret) {
1519                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1520                                       mac_addr);
1521                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1522                 goto err_add_uc_addr;
1523         }
1524
1525         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1526         if (ret) {
1527                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1528                 goto err_pause_addr_cfg;
1529         }
1530
1531         rte_ether_addr_copy(mac_addr,
1532                             (struct rte_ether_addr *)hw->mac.mac_addr);
1533         hw->mac.default_addr_setted = true;
1534         rte_spinlock_unlock(&hw->lock);
1535
1536         return 0;
1537
1538 err_pause_addr_cfg:
1539         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1540         if (ret_val) {
1541                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1542                                       mac_addr);
1543                 hns3_warn(hw,
1544                           "Failed to roll back to del setted mac addr(%s): %d",
1545                           mac_str, ret_val);
1546         }
1547
1548 err_add_uc_addr:
1549         if (rm_succes) {
1550                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1551                 if (ret_val) {
1552                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1553                                               oaddr);
1554                         hns3_warn(hw,
1555                                   "Failed to restore old uc mac addr(%s): %d",
1556                                   mac_str, ret_val);
1557                         hw->mac.default_addr_setted = false;
1558                 }
1559         }
1560         rte_spinlock_unlock(&hw->lock);
1561
1562         return ret;
1563 }
1564
1565 static int
1566 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1567 {
1568         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1569         struct hns3_hw *hw = &hns->hw;
1570         struct rte_ether_addr *addr;
1571         int err = 0;
1572         int ret;
1573         int i;
1574
1575         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1576                 addr = &hw->data->mac_addrs[i];
1577                 if (!rte_is_valid_assigned_ether_addr(addr))
1578                         continue;
1579                 if (del)
1580                         ret = hns3_remove_uc_addr_common(hw, addr);
1581                 else
1582                         ret = hns3_add_uc_addr_common(hw, addr);
1583                 if (ret) {
1584                         err = ret;
1585                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1586                                               addr);
1587                         hns3_dbg(hw,
1588                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1589                                  del ? "remove" : "restore", mac_str, ret, i);
1590                 }
1591         }
1592         return err;
1593 }
1594
1595 static void
1596 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1597 {
1598 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1599         uint8_t word_num;
1600         uint8_t bit_num;
1601
1602         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1603                 word_num = vfid / 32;
1604                 bit_num = vfid % 32;
1605                 if (clr)
1606                         desc[1].data[word_num] &=
1607                             rte_cpu_to_le_32(~(1UL << bit_num));
1608                 else
1609                         desc[1].data[word_num] |=
1610                             rte_cpu_to_le_32(1UL << bit_num);
1611         } else {
1612                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1613                 bit_num = vfid % 32;
1614                 if (clr)
1615                         desc[2].data[word_num] &=
1616                             rte_cpu_to_le_32(~(1UL << bit_num));
1617                 else
1618                         desc[2].data[word_num] |=
1619                             rte_cpu_to_le_32(1UL << bit_num);
1620         }
1621 }
1622
1623 static int
1624 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1625 {
1626         struct hns3_mac_vlan_tbl_entry_cmd req;
1627         struct hns3_cmd_desc desc[3];
1628         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1629         uint8_t vf_id;
1630         int ret;
1631
1632         /* Check if mac addr is valid */
1633         if (!rte_is_multicast_ether_addr(mac_addr)) {
1634                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1635                                       mac_addr);
1636                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1637                          mac_str);
1638                 return -EINVAL;
1639         }
1640
1641         memset(&req, 0, sizeof(req));
1642         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1643         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1644         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1645         if (ret) {
1646                 /* This mac addr do not exist, add new entry for it */
1647                 memset(desc[0].data, 0, sizeof(desc[0].data));
1648                 memset(desc[1].data, 0, sizeof(desc[0].data));
1649                 memset(desc[2].data, 0, sizeof(desc[0].data));
1650         }
1651
1652         /*
1653          * In current version VF is not supported when PF is driven by DPDK
1654          * driver, the PF-related vf_id is 0, just need to configure parameters
1655          * for vf_id 0.
1656          */
1657         vf_id = 0;
1658         hns3_update_desc_vfid(desc, vf_id, false);
1659         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1660         if (ret) {
1661                 if (ret == -ENOSPC)
1662                         hns3_err(hw, "mc mac vlan table is full");
1663                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1664                                       mac_addr);
1665                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1666         }
1667
1668         return ret;
1669 }
1670
1671 static int
1672 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1673 {
1674         struct hns3_mac_vlan_tbl_entry_cmd req;
1675         struct hns3_cmd_desc desc[3];
1676         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1677         uint8_t vf_id;
1678         int ret;
1679
1680         /* Check if mac addr is valid */
1681         if (!rte_is_multicast_ether_addr(mac_addr)) {
1682                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1683                                       mac_addr);
1684                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1685                          mac_str);
1686                 return -EINVAL;
1687         }
1688
1689         memset(&req, 0, sizeof(req));
1690         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1691         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1692         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1693         if (ret == 0) {
1694                 /*
1695                  * This mac addr exist, remove this handle's VFID for it.
1696                  * In current version VF is not supported when PF is driven by
1697                  * DPDK driver, the PF-related vf_id is 0, just need to
1698                  * configure parameters for vf_id 0.
1699                  */
1700                 vf_id = 0;
1701                 hns3_update_desc_vfid(desc, vf_id, true);
1702
1703                 /* All the vfid is zero, so need to delete this entry */
1704                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1705         } else if (ret == -ENOENT) {
1706                 /* This mac addr doesn't exist. */
1707                 return 0;
1708         }
1709
1710         if (ret) {
1711                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1712                                       mac_addr);
1713                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1714         }
1715
1716         return ret;
1717 }
1718
1719 static int
1720 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1721                            struct rte_ether_addr *mc_addr_set,
1722                            uint32_t nb_mc_addr)
1723 {
1724         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1725         struct rte_ether_addr *addr;
1726         uint32_t i;
1727         uint32_t j;
1728
1729         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1730                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1731                          "invalid. valid range: 0~%d",
1732                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1733                 return -EINVAL;
1734         }
1735
1736         /* Check if input mac addresses are valid */
1737         for (i = 0; i < nb_mc_addr; i++) {
1738                 addr = &mc_addr_set[i];
1739                 if (!rte_is_multicast_ether_addr(addr)) {
1740                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1741                                               addr);
1742                         hns3_err(hw,
1743                                  "Failed to set mc mac addr, addr(%s) invalid.",
1744                                  mac_str);
1745                         return -EINVAL;
1746                 }
1747
1748                 /* Check if there are duplicate addresses */
1749                 for (j = i + 1; j < nb_mc_addr; j++) {
1750                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1751                                 rte_ether_format_addr(mac_str,
1752                                                       RTE_ETHER_ADDR_FMT_SIZE,
1753                                                       addr);
1754                                 hns3_err(hw, "Failed to set mc mac addr, "
1755                                          "addrs invalid. two same addrs(%s).",
1756                                          mac_str);
1757                                 return -EINVAL;
1758                         }
1759                 }
1760         }
1761
1762         return 0;
1763 }
1764
1765 static void
1766 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1767                            struct rte_ether_addr *mc_addr_set,
1768                            int mc_addr_num,
1769                            struct rte_ether_addr *reserved_addr_list,
1770                            int *reserved_addr_num,
1771                            struct rte_ether_addr *add_addr_list,
1772                            int *add_addr_num,
1773                            struct rte_ether_addr *rm_addr_list,
1774                            int *rm_addr_num)
1775 {
1776         struct rte_ether_addr *addr;
1777         int current_addr_num;
1778         int reserved_num = 0;
1779         int add_num = 0;
1780         int rm_num = 0;
1781         int num;
1782         int i;
1783         int j;
1784         bool same_addr;
1785
1786         /* Calculate the mc mac address list that should be removed */
1787         current_addr_num = hw->mc_addrs_num;
1788         for (i = 0; i < current_addr_num; i++) {
1789                 addr = &hw->mc_addrs[i];
1790                 same_addr = false;
1791                 for (j = 0; j < mc_addr_num; j++) {
1792                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1793                                 same_addr = true;
1794                                 break;
1795                         }
1796                 }
1797
1798                 if (!same_addr) {
1799                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1800                         rm_num++;
1801                 } else {
1802                         rte_ether_addr_copy(addr,
1803                                             &reserved_addr_list[reserved_num]);
1804                         reserved_num++;
1805                 }
1806         }
1807
1808         /* Calculate the mc mac address list that should be added */
1809         for (i = 0; i < mc_addr_num; i++) {
1810                 addr = &mc_addr_set[i];
1811                 same_addr = false;
1812                 for (j = 0; j < current_addr_num; j++) {
1813                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1814                                 same_addr = true;
1815                                 break;
1816                         }
1817                 }
1818
1819                 if (!same_addr) {
1820                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1821                         add_num++;
1822                 }
1823         }
1824
1825         /* Reorder the mc mac address list maintained by driver */
1826         for (i = 0; i < reserved_num; i++)
1827                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1828
1829         for (i = 0; i < rm_num; i++) {
1830                 num = reserved_num + i;
1831                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1832         }
1833
1834         *reserved_addr_num = reserved_num;
1835         *add_addr_num = add_num;
1836         *rm_addr_num = rm_num;
1837 }
1838
1839 static int
1840 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1841                           struct rte_ether_addr *mc_addr_set,
1842                           uint32_t nb_mc_addr)
1843 {
1844         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1846         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1847         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1848         struct rte_ether_addr *addr;
1849         int reserved_addr_num;
1850         int add_addr_num;
1851         int rm_addr_num;
1852         int mc_addr_num;
1853         int num;
1854         int ret;
1855         int i;
1856
1857         /* Check if input parameters are valid */
1858         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1859         if (ret)
1860                 return ret;
1861
1862         rte_spinlock_lock(&hw->lock);
1863
1864         /*
1865          * Calculate the mc mac address lists those should be removed and be
1866          * added, Reorder the mc mac address list maintained by driver.
1867          */
1868         mc_addr_num = (int)nb_mc_addr;
1869         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1870                                    reserved_addr_list, &reserved_addr_num,
1871                                    add_addr_list, &add_addr_num,
1872                                    rm_addr_list, &rm_addr_num);
1873
1874         /* Remove mc mac addresses */
1875         for (i = 0; i < rm_addr_num; i++) {
1876                 num = rm_addr_num - i - 1;
1877                 addr = &rm_addr_list[num];
1878                 ret = hns3_remove_mc_addr(hw, addr);
1879                 if (ret) {
1880                         rte_spinlock_unlock(&hw->lock);
1881                         return ret;
1882                 }
1883                 hw->mc_addrs_num--;
1884         }
1885
1886         /* Add mc mac addresses */
1887         for (i = 0; i < add_addr_num; i++) {
1888                 addr = &add_addr_list[i];
1889                 ret = hns3_add_mc_addr(hw, addr);
1890                 if (ret) {
1891                         rte_spinlock_unlock(&hw->lock);
1892                         return ret;
1893                 }
1894
1895                 num = reserved_addr_num + i;
1896                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1897                 hw->mc_addrs_num++;
1898         }
1899         rte_spinlock_unlock(&hw->lock);
1900
1901         return 0;
1902 }
1903
1904 static int
1905 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1906 {
1907         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1908         struct hns3_hw *hw = &hns->hw;
1909         struct rte_ether_addr *addr;
1910         int err = 0;
1911         int ret;
1912         int i;
1913
1914         for (i = 0; i < hw->mc_addrs_num; i++) {
1915                 addr = &hw->mc_addrs[i];
1916                 if (!rte_is_multicast_ether_addr(addr))
1917                         continue;
1918                 if (del)
1919                         ret = hns3_remove_mc_addr(hw, addr);
1920                 else
1921                         ret = hns3_add_mc_addr(hw, addr);
1922                 if (ret) {
1923                         err = ret;
1924                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1925                                               addr);
1926                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1927                                  del ? "Remove" : "Restore", mac_str);
1928                 }
1929         }
1930         return err;
1931 }
1932
1933 static int
1934 hns3_check_mq_mode(struct rte_eth_dev *dev)
1935 {
1936         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1937         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1938         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1940         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1941         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1942         uint8_t num_tc;
1943         int max_tc = 0;
1944         int i;
1945
1946         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1947         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1948
1949         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1950                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1951                          "rx_mq_mode = %d", rx_mq_mode);
1952                 return -EINVAL;
1953         }
1954
1955         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1956             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1957                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1958                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1959                          rx_mq_mode, tx_mq_mode);
1960                 return -EINVAL;
1961         }
1962
1963         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1964                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1965                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1966                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1967                         return -EINVAL;
1968                 }
1969
1970                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1971                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1972                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1973                                  "nb_tcs(%d) != %d or %d in rx direction.",
1974                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1975                         return -EINVAL;
1976                 }
1977
1978                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1979                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1980                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1981                         return -EINVAL;
1982                 }
1983
1984                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1985                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1986                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1987                                          "is not equal to one in tx direction.",
1988                                          i, dcb_rx_conf->dcb_tc[i]);
1989                                 return -EINVAL;
1990                         }
1991                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1992                                 max_tc = dcb_rx_conf->dcb_tc[i];
1993                 }
1994
1995                 num_tc = max_tc + 1;
1996                 if (num_tc > dcb_rx_conf->nb_tcs) {
1997                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1998                                  num_tc, dcb_rx_conf->nb_tcs);
1999                         return -EINVAL;
2000                 }
2001         }
2002
2003         return 0;
2004 }
2005
2006 static int
2007 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2008 {
2009         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2010
2011         if (!hns3_dev_dcb_supported(hw)) {
2012                 hns3_err(hw, "this port does not support dcb configurations.");
2013                 return -EOPNOTSUPP;
2014         }
2015
2016         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2017                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2018                 return -EOPNOTSUPP;
2019         }
2020
2021         /* Check multiple queue mode */
2022         return hns3_check_mq_mode(dev);
2023 }
2024
2025 static int
2026 hns3_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id, bool mmap,
2027                            enum hns3_ring_type queue_type, uint16_t queue_id)
2028 {
2029         struct hns3_cmd_desc desc;
2030         struct hns3_ctrl_vector_chain_cmd *req =
2031                 (struct hns3_ctrl_vector_chain_cmd *)desc.data;
2032         enum hns3_cmd_status status;
2033         enum hns3_opcode_type op;
2034         uint16_t tqp_type_and_id = 0;
2035         const char *op_str;
2036         uint16_t type;
2037         uint16_t gl;
2038
2039         op = mmap ? HNS3_OPC_ADD_RING_TO_VECTOR : HNS3_OPC_DEL_RING_TO_VECTOR;
2040         hns3_cmd_setup_basic_desc(&desc, op, false);
2041         req->int_vector_id = vector_id;
2042
2043         if (queue_type == HNS3_RING_TYPE_RX)
2044                 gl = HNS3_RING_GL_RX;
2045         else
2046                 gl = HNS3_RING_GL_TX;
2047
2048         type = queue_type;
2049
2050         hns3_set_field(tqp_type_and_id, HNS3_INT_TYPE_M, HNS3_INT_TYPE_S,
2051                        type);
2052         hns3_set_field(tqp_type_and_id, HNS3_TQP_ID_M, HNS3_TQP_ID_S, queue_id);
2053         hns3_set_field(tqp_type_and_id, HNS3_INT_GL_IDX_M, HNS3_INT_GL_IDX_S,
2054                        gl);
2055         req->tqp_type_and_id[0] = rte_cpu_to_le_16(tqp_type_and_id);
2056         req->int_cause_num = 1;
2057         op_str = mmap ? "Map" : "Unmap";
2058         status = hns3_cmd_send(hw, &desc, 1);
2059         if (status) {
2060                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, status is %d.",
2061                          op_str, queue_id, req->int_vector_id, status);
2062                 return status;
2063         }
2064
2065         return 0;
2066 }
2067
2068 static int
2069 hns3_init_ring_with_vector(struct hns3_hw *hw)
2070 {
2071         uint8_t vec;
2072         int ret;
2073         int i;
2074
2075         /*
2076          * In hns3 network engine, vector 0 is always the misc interrupt of this
2077          * function, vector 1~N can be used respectively for the queues of the
2078          * function. Tx and Rx queues with the same number share the interrupt
2079          * vector. In the initialization clearing the all hardware mapping
2080          * relationship configurations between queues and interrupt vectors is
2081          * needed, so some error caused by the residual configurations, such as
2082          * the unexpected Tx interrupt, can be avoid. Because of the hardware
2083          * constraints in hns3 hardware engine, we have to implement clearing
2084          * the mapping relationship configurations by binding all queues to the
2085          * last interrupt vector and reserving the last interrupt vector. This
2086          * method results in a decrease of the maximum queues when upper
2087          * applications call the rte_eth_dev_configure API function to enable
2088          * Rx interrupt.
2089          */
2090         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
2091         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
2092         for (i = 0; i < hw->intr_tqps_num; i++) {
2093                 /*
2094                  * Set gap limiter and rate limiter configuration of queue's
2095                  * interrupt.
2096                  */
2097                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
2098                                        HNS3_TQP_INTR_GL_DEFAULT);
2099                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
2100                                        HNS3_TQP_INTR_GL_DEFAULT);
2101                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
2102
2103                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2104                                                  HNS3_RING_TYPE_TX, i);
2105                 if (ret) {
2106                         PMD_INIT_LOG(ERR, "PF fail to unbind TX ring(%d) with "
2107                                           "vector: %d, ret=%d", i, vec, ret);
2108                         return ret;
2109                 }
2110
2111                 ret = hns3_bind_ring_with_vector(hw, vec, false,
2112                                                  HNS3_RING_TYPE_RX, i);
2113                 if (ret) {
2114                         PMD_INIT_LOG(ERR, "PF fail to unbind RX ring(%d) with "
2115                                           "vector: %d, ret=%d", i, vec, ret);
2116                         return ret;
2117                 }
2118         }
2119
2120         return 0;
2121 }
2122
2123 static int
2124 hns3_dev_configure(struct rte_eth_dev *dev)
2125 {
2126         struct hns3_adapter *hns = dev->data->dev_private;
2127         struct rte_eth_conf *conf = &dev->data->dev_conf;
2128         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2129         struct hns3_hw *hw = &hns->hw;
2130         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2131         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2132         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2133         struct rte_eth_rss_conf rss_conf;
2134         uint16_t mtu;
2135         int ret;
2136
2137         /*
2138          * Hardware does not support individually enable/disable/reset the Tx or
2139          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
2140          * and Rx queues at the same time. When the numbers of Tx queues
2141          * allocated by upper applications are not equal to the numbers of Rx
2142          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
2143          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
2144          * these fake queues are imperceptible, and can not be used by upper
2145          * applications.
2146          */
2147         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
2148         if (ret) {
2149                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
2150                 return ret;
2151         }
2152
2153         hw->adapter_state = HNS3_NIC_CONFIGURING;
2154         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2155                 hns3_err(hw, "setting link speed/duplex not supported");
2156                 ret = -EINVAL;
2157                 goto cfg_err;
2158         }
2159
2160         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2161                 ret = hns3_check_dcb_cfg(dev);
2162                 if (ret)
2163                         goto cfg_err;
2164         }
2165
2166         /* When RSS is not configured, redirect the packet queue 0 */
2167         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2168                 rss_conf = conf->rx_adv_conf.rss_conf;
2169                 if (rss_conf.rss_key == NULL) {
2170                         rss_conf.rss_key = rss_cfg->key;
2171                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2172                 }
2173
2174                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2175                 if (ret)
2176                         goto cfg_err;
2177         }
2178
2179         /*
2180          * If jumbo frames are enabled, MTU needs to be refreshed
2181          * according to the maximum RX packet length.
2182          */
2183         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2184                 /*
2185                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2186                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2187                  * can safely assign to "uint16_t" type variable.
2188                  */
2189                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2190                 ret = hns3_dev_mtu_set(dev, mtu);
2191                 if (ret)
2192                         goto cfg_err;
2193                 dev->data->mtu = mtu;
2194         }
2195
2196         ret = hns3_dev_configure_vlan(dev);
2197         if (ret)
2198                 goto cfg_err;
2199
2200         hw->adapter_state = HNS3_NIC_CONFIGURED;
2201
2202         return 0;
2203
2204 cfg_err:
2205         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
2206         hw->adapter_state = HNS3_NIC_INITIALIZED;
2207
2208         return ret;
2209 }
2210
2211 static int
2212 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2213 {
2214         struct hns3_config_max_frm_size_cmd *req;
2215         struct hns3_cmd_desc desc;
2216
2217         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2218
2219         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2220         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2221         req->min_frm_size = RTE_ETHER_MIN_LEN;
2222
2223         return hns3_cmd_send(hw, &desc, 1);
2224 }
2225
2226 static int
2227 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2228 {
2229         int ret;
2230
2231         ret = hns3_set_mac_mtu(hw, mps);
2232         if (ret) {
2233                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2234                 return ret;
2235         }
2236
2237         ret = hns3_buffer_alloc(hw);
2238         if (ret) {
2239                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2240                 return ret;
2241         }
2242
2243         return 0;
2244 }
2245
2246 static int
2247 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2248 {
2249         struct hns3_adapter *hns = dev->data->dev_private;
2250         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2251         struct hns3_hw *hw = &hns->hw;
2252         bool is_jumbo_frame;
2253         int ret;
2254
2255         if (dev->data->dev_started) {
2256                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2257                          "before configuration", dev->data->port_id);
2258                 return -EBUSY;
2259         }
2260
2261         rte_spinlock_lock(&hw->lock);
2262         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2263         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2264
2265         /*
2266          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2267          * assign to "uint16_t" type variable.
2268          */
2269         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2270         if (ret) {
2271                 rte_spinlock_unlock(&hw->lock);
2272                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2273                          dev->data->port_id, mtu, ret);
2274                 return ret;
2275         }
2276         hns->pf.mps = (uint16_t)frame_size;
2277         if (is_jumbo_frame)
2278                 dev->data->dev_conf.rxmode.offloads |=
2279                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2280         else
2281                 dev->data->dev_conf.rxmode.offloads &=
2282                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2283         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2284         rte_spinlock_unlock(&hw->lock);
2285
2286         return 0;
2287 }
2288
2289 static int
2290 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2291 {
2292         struct hns3_adapter *hns = eth_dev->data->dev_private;
2293         struct hns3_hw *hw = &hns->hw;
2294         uint16_t queue_num = hw->tqps_num;
2295
2296         /*
2297          * In interrupt mode, 'max_rx_queues' is set based on the number of
2298          * MSI-X interrupt resources of the hardware.
2299          */
2300         if (hw->data->dev_conf.intr_conf.rxq == 1)
2301                 queue_num = hw->intr_tqps_num;
2302
2303         info->max_rx_queues = queue_num;
2304         info->max_tx_queues = hw->tqps_num;
2305         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2306         info->min_rx_bufsize = hw->rx_buf_len;
2307         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2308         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2309         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2310                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2311                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2312                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2313                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2314                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2315                                  DEV_RX_OFFLOAD_KEEP_CRC |
2316                                  DEV_RX_OFFLOAD_SCATTER |
2317                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2318                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2319                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2320                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2321                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2322         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2323         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2324                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2325                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2326                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2327                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2328                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2329                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2330                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2331                                  DEV_TX_OFFLOAD_TCP_TSO |
2332                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2333                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
2334                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
2335                                  info->tx_queue_offload_capa);
2336
2337         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2338                 .nb_max = HNS3_MAX_RING_DESC,
2339                 .nb_min = HNS3_MIN_RING_DESC,
2340                 .nb_align = HNS3_ALIGN_RING_DESC,
2341         };
2342
2343         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2344                 .nb_max = HNS3_MAX_RING_DESC,
2345                 .nb_min = HNS3_MIN_RING_DESC,
2346                 .nb_align = HNS3_ALIGN_RING_DESC,
2347         };
2348
2349         info->vmdq_queue_num = 0;
2350
2351         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2352         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2353         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2354
2355         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2356         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2357         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2358         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2359         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2360         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2361
2362         return 0;
2363 }
2364
2365 static int
2366 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2367                     size_t fw_size)
2368 {
2369         struct hns3_adapter *hns = eth_dev->data->dev_private;
2370         struct hns3_hw *hw = &hns->hw;
2371         int ret;
2372
2373         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2374         ret += 1; /* add the size of '\0' */
2375         if (fw_size < (uint32_t)ret)
2376                 return ret;
2377         else
2378                 return 0;
2379 }
2380
2381 static int
2382 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2383                      __rte_unused int wait_to_complete)
2384 {
2385         struct hns3_adapter *hns = eth_dev->data->dev_private;
2386         struct hns3_hw *hw = &hns->hw;
2387         struct hns3_mac *mac = &hw->mac;
2388         struct rte_eth_link new_link;
2389
2390         if (!hns3_is_reset_pending(hns)) {
2391                 hns3_update_speed_duplex(eth_dev);
2392                 hns3_update_link_status(hw);
2393         }
2394
2395         memset(&new_link, 0, sizeof(new_link));
2396         switch (mac->link_speed) {
2397         case ETH_SPEED_NUM_10M:
2398         case ETH_SPEED_NUM_100M:
2399         case ETH_SPEED_NUM_1G:
2400         case ETH_SPEED_NUM_10G:
2401         case ETH_SPEED_NUM_25G:
2402         case ETH_SPEED_NUM_40G:
2403         case ETH_SPEED_NUM_50G:
2404         case ETH_SPEED_NUM_100G:
2405                 new_link.link_speed = mac->link_speed;
2406                 break;
2407         default:
2408                 new_link.link_speed = ETH_SPEED_NUM_100M;
2409                 break;
2410         }
2411
2412         new_link.link_duplex = mac->link_duplex;
2413         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2414         new_link.link_autoneg =
2415             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2416
2417         return rte_eth_linkstatus_set(eth_dev, &new_link);
2418 }
2419
2420 static int
2421 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2422 {
2423         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2424         struct hns3_pf *pf = &hns->pf;
2425
2426         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2427                 return -EINVAL;
2428
2429         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2430
2431         return 0;
2432 }
2433
2434 static int
2435 hns3_query_function_status(struct hns3_hw *hw)
2436 {
2437 #define HNS3_QUERY_MAX_CNT              10
2438 #define HNS3_QUERY_SLEEP_MSCOEND        1
2439         struct hns3_func_status_cmd *req;
2440         struct hns3_cmd_desc desc;
2441         int timeout = 0;
2442         int ret;
2443
2444         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2445         req = (struct hns3_func_status_cmd *)desc.data;
2446
2447         do {
2448                 ret = hns3_cmd_send(hw, &desc, 1);
2449                 if (ret) {
2450                         PMD_INIT_LOG(ERR, "query function status failed %d",
2451                                      ret);
2452                         return ret;
2453                 }
2454
2455                 /* Check pf reset is done */
2456                 if (req->pf_state)
2457                         break;
2458
2459                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2460         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2461
2462         return hns3_parse_func_status(hw, req);
2463 }
2464
2465 static int
2466 hns3_query_pf_resource(struct hns3_hw *hw)
2467 {
2468         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2469         struct hns3_pf *pf = &hns->pf;
2470         struct hns3_pf_res_cmd *req;
2471         struct hns3_cmd_desc desc;
2472         uint16_t num_msi;
2473         int ret;
2474
2475         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2476         ret = hns3_cmd_send(hw, &desc, 1);
2477         if (ret) {
2478                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2479                 return ret;
2480         }
2481
2482         req = (struct hns3_pf_res_cmd *)desc.data;
2483         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2484         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2485         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2486         pf->func_num = rte_le_to_cpu_16(req->pf_own_fun_number);
2487
2488         if (req->tx_buf_size)
2489                 pf->tx_buf_size =
2490                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2491         else
2492                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2493
2494         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2495
2496         if (req->dv_buf_size)
2497                 pf->dv_buf_size =
2498                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2499         else
2500                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2501
2502         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2503
2504         num_msi = hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2505                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
2506         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
2507
2508         return 0;
2509 }
2510
2511 static void
2512 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2513 {
2514         struct hns3_cfg_param_cmd *req;
2515         uint64_t mac_addr_tmp_high;
2516         uint64_t mac_addr_tmp;
2517         uint32_t i;
2518
2519         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2520
2521         /* get the configuration */
2522         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2523                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2524         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2525                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2526         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2527                                            HNS3_CFG_TQP_DESC_N_M,
2528                                            HNS3_CFG_TQP_DESC_N_S);
2529
2530         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2531                                        HNS3_CFG_PHY_ADDR_M,
2532                                        HNS3_CFG_PHY_ADDR_S);
2533         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2534                                          HNS3_CFG_MEDIA_TP_M,
2535                                          HNS3_CFG_MEDIA_TP_S);
2536         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2537                                          HNS3_CFG_RX_BUF_LEN_M,
2538                                          HNS3_CFG_RX_BUF_LEN_S);
2539         /* get mac address */
2540         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2541         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2542                                            HNS3_CFG_MAC_ADDR_H_M,
2543                                            HNS3_CFG_MAC_ADDR_H_S);
2544
2545         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2546
2547         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2548                                             HNS3_CFG_DEFAULT_SPEED_M,
2549                                             HNS3_CFG_DEFAULT_SPEED_S);
2550         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2551                                            HNS3_CFG_RSS_SIZE_M,
2552                                            HNS3_CFG_RSS_SIZE_S);
2553
2554         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2555                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2556
2557         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2558         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2559
2560         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2561                                             HNS3_CFG_SPEED_ABILITY_M,
2562                                             HNS3_CFG_SPEED_ABILITY_S);
2563         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2564                                         HNS3_CFG_UMV_TBL_SPACE_M,
2565                                         HNS3_CFG_UMV_TBL_SPACE_S);
2566         if (!cfg->umv_space)
2567                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2568 }
2569
2570 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2571  * @hw: pointer to struct hns3_hw
2572  * @hcfg: the config structure to be getted
2573  */
2574 static int
2575 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2576 {
2577         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2578         struct hns3_cfg_param_cmd *req;
2579         uint32_t offset;
2580         uint32_t i;
2581         int ret;
2582
2583         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2584                 offset = 0;
2585                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2586                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2587                                           true);
2588                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2589                                i * HNS3_CFG_RD_LEN_BYTES);
2590                 /* Len should be divided by 4 when send to hardware */
2591                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2592                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2593                 req->offset = rte_cpu_to_le_32(offset);
2594         }
2595
2596         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2597         if (ret) {
2598                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2599                 return ret;
2600         }
2601
2602         hns3_parse_cfg(hcfg, desc);
2603
2604         return 0;
2605 }
2606
2607 static int
2608 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2609 {
2610         switch (speed_cmd) {
2611         case HNS3_CFG_SPEED_10M:
2612                 *speed = ETH_SPEED_NUM_10M;
2613                 break;
2614         case HNS3_CFG_SPEED_100M:
2615                 *speed = ETH_SPEED_NUM_100M;
2616                 break;
2617         case HNS3_CFG_SPEED_1G:
2618                 *speed = ETH_SPEED_NUM_1G;
2619                 break;
2620         case HNS3_CFG_SPEED_10G:
2621                 *speed = ETH_SPEED_NUM_10G;
2622                 break;
2623         case HNS3_CFG_SPEED_25G:
2624                 *speed = ETH_SPEED_NUM_25G;
2625                 break;
2626         case HNS3_CFG_SPEED_40G:
2627                 *speed = ETH_SPEED_NUM_40G;
2628                 break;
2629         case HNS3_CFG_SPEED_50G:
2630                 *speed = ETH_SPEED_NUM_50G;
2631                 break;
2632         case HNS3_CFG_SPEED_100G:
2633                 *speed = ETH_SPEED_NUM_100G;
2634                 break;
2635         default:
2636                 return -EINVAL;
2637         }
2638
2639         return 0;
2640 }
2641
2642 static int
2643 hns3_get_board_configuration(struct hns3_hw *hw)
2644 {
2645         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2646         struct hns3_pf *pf = &hns->pf;
2647         struct hns3_cfg cfg;
2648         int ret;
2649
2650         ret = hns3_get_board_cfg(hw, &cfg);
2651         if (ret) {
2652                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2653                 return ret;
2654         }
2655
2656         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2657                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2658                 return -EOPNOTSUPP;
2659         }
2660
2661         hw->mac.media_type = cfg.media_type;
2662         hw->rss_size_max = cfg.rss_size_max;
2663         hw->rx_buf_len = cfg.rx_buf_len;
2664         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2665         hw->mac.phy_addr = cfg.phy_addr;
2666         hw->mac.default_addr_setted = false;
2667         hw->num_tx_desc = cfg.tqp_desc_num;
2668         hw->num_rx_desc = cfg.tqp_desc_num;
2669         hw->dcb_info.num_pg = 1;
2670         hw->dcb_info.hw_pfc_map = 0;
2671
2672         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2673         if (ret) {
2674                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2675                              cfg.default_speed, ret);
2676                 return ret;
2677         }
2678
2679         pf->tc_max = cfg.tc_num;
2680         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2681                 PMD_INIT_LOG(WARNING,
2682                              "Get TC num(%u) from flash, set TC num to 1",
2683                              pf->tc_max);
2684                 pf->tc_max = 1;
2685         }
2686
2687         /* Dev does not support DCB */
2688         if (!hns3_dev_dcb_supported(hw)) {
2689                 pf->tc_max = 1;
2690                 pf->pfc_max = 0;
2691         } else
2692                 pf->pfc_max = pf->tc_max;
2693
2694         hw->dcb_info.num_tc = 1;
2695         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2696                                      hw->tqps_num / hw->dcb_info.num_tc);
2697         hns3_set_bit(hw->hw_tc_map, 0, 1);
2698         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2699
2700         pf->wanted_umv_size = cfg.umv_space;
2701
2702         return ret;
2703 }
2704
2705 static int
2706 hns3_get_configuration(struct hns3_hw *hw)
2707 {
2708         int ret;
2709
2710         ret = hns3_query_function_status(hw);
2711         if (ret) {
2712                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2713                 return ret;
2714         }
2715
2716         /* Get pf resource */
2717         ret = hns3_query_pf_resource(hw);
2718         if (ret) {
2719                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2720                 return ret;
2721         }
2722
2723         ret = hns3_get_board_configuration(hw);
2724         if (ret) {
2725                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2726                 return ret;
2727         }
2728
2729         return 0;
2730 }
2731
2732 static int
2733 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2734                       uint16_t tqp_vid, bool is_pf)
2735 {
2736         struct hns3_tqp_map_cmd *req;
2737         struct hns3_cmd_desc desc;
2738         int ret;
2739
2740         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2741
2742         req = (struct hns3_tqp_map_cmd *)desc.data;
2743         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2744         req->tqp_vf = func_id;
2745         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2746         if (!is_pf)
2747                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2748         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2749
2750         ret = hns3_cmd_send(hw, &desc, 1);
2751         if (ret)
2752                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2753
2754         return ret;
2755 }
2756
2757 static int
2758 hns3_map_tqp(struct hns3_hw *hw)
2759 {
2760         uint16_t tqps_num = hw->total_tqps_num;
2761         uint16_t func_id;
2762         uint16_t tqp_id;
2763         bool is_pf;
2764         int num;
2765         int ret;
2766         int i;
2767
2768         /*
2769          * In current version VF is not supported when PF is driven by DPDK
2770          * driver, so we allocate tqps to PF as much as possible.
2771          */
2772         tqp_id = 0;
2773         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2774         for (func_id = 0; func_id < num; func_id++) {
2775                 is_pf = func_id == 0 ? true : false;
2776                 for (i = 0;
2777                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2778                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2779                                                     is_pf);
2780                         if (ret)
2781                                 return ret;
2782                 }
2783         }
2784
2785         return 0;
2786 }
2787
2788 static int
2789 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2790 {
2791         struct hns3_config_mac_speed_dup_cmd *req;
2792         struct hns3_cmd_desc desc;
2793         int ret;
2794
2795         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2796
2797         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2798
2799         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2800
2801         switch (speed) {
2802         case ETH_SPEED_NUM_10M:
2803                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2804                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2805                 break;
2806         case ETH_SPEED_NUM_100M:
2807                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2808                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2809                 break;
2810         case ETH_SPEED_NUM_1G:
2811                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2812                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2813                 break;
2814         case ETH_SPEED_NUM_10G:
2815                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2816                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2817                 break;
2818         case ETH_SPEED_NUM_25G:
2819                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2820                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2821                 break;
2822         case ETH_SPEED_NUM_40G:
2823                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2824                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2825                 break;
2826         case ETH_SPEED_NUM_50G:
2827                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2828                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2829                 break;
2830         case ETH_SPEED_NUM_100G:
2831                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2832                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2833                 break;
2834         default:
2835                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2836                 return -EINVAL;
2837         }
2838
2839         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2840
2841         ret = hns3_cmd_send(hw, &desc, 1);
2842         if (ret)
2843                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2844
2845         return ret;
2846 }
2847
2848 static int
2849 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2850 {
2851         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2852         struct hns3_pf *pf = &hns->pf;
2853         struct hns3_priv_buf *priv;
2854         uint32_t i, total_size;
2855
2856         total_size = pf->pkt_buf_size;
2857
2858         /* alloc tx buffer for all enabled tc */
2859         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2860                 priv = &buf_alloc->priv_buf[i];
2861
2862                 if (hw->hw_tc_map & BIT(i)) {
2863                         if (total_size < pf->tx_buf_size)
2864                                 return -ENOMEM;
2865
2866                         priv->tx_buf_size = pf->tx_buf_size;
2867                 } else
2868                         priv->tx_buf_size = 0;
2869
2870                 total_size -= priv->tx_buf_size;
2871         }
2872
2873         return 0;
2874 }
2875
2876 static int
2877 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2878 {
2879 /* TX buffer size is unit by 128 byte */
2880 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2881 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2882         struct hns3_tx_buff_alloc_cmd *req;
2883         struct hns3_cmd_desc desc;
2884         uint32_t buf_size;
2885         uint32_t i;
2886         int ret;
2887
2888         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2889
2890         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2891         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2892                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2893
2894                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2895                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2896                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2897         }
2898
2899         ret = hns3_cmd_send(hw, &desc, 1);
2900         if (ret)
2901                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2902
2903         return ret;
2904 }
2905
2906 static int
2907 hns3_get_tc_num(struct hns3_hw *hw)
2908 {
2909         int cnt = 0;
2910         uint8_t i;
2911
2912         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2913                 if (hw->hw_tc_map & BIT(i))
2914                         cnt++;
2915         return cnt;
2916 }
2917
2918 static uint32_t
2919 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2920 {
2921         struct hns3_priv_buf *priv;
2922         uint32_t rx_priv = 0;
2923         int i;
2924
2925         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2926                 priv = &buf_alloc->priv_buf[i];
2927                 if (priv->enable)
2928                         rx_priv += priv->buf_size;
2929         }
2930         return rx_priv;
2931 }
2932
2933 static uint32_t
2934 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2935 {
2936         uint32_t total_tx_size = 0;
2937         uint32_t i;
2938
2939         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2940                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2941
2942         return total_tx_size;
2943 }
2944
2945 /* Get the number of pfc enabled TCs, which have private buffer */
2946 static int
2947 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2948 {
2949         struct hns3_priv_buf *priv;
2950         int cnt = 0;
2951         uint8_t i;
2952
2953         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2954                 priv = &buf_alloc->priv_buf[i];
2955                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2956                         cnt++;
2957         }
2958
2959         return cnt;
2960 }
2961
2962 /* Get the number of pfc disabled TCs, which have private buffer */
2963 static int
2964 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2965                          struct hns3_pkt_buf_alloc *buf_alloc)
2966 {
2967         struct hns3_priv_buf *priv;
2968         int cnt = 0;
2969         uint8_t i;
2970
2971         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2972                 priv = &buf_alloc->priv_buf[i];
2973                 if (hw->hw_tc_map & BIT(i) &&
2974                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2975                         cnt++;
2976         }
2977
2978         return cnt;
2979 }
2980
2981 static bool
2982 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2983                   uint32_t rx_all)
2984 {
2985         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2986         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2987         struct hns3_pf *pf = &hns->pf;
2988         uint32_t shared_buf, aligned_mps;
2989         uint32_t rx_priv;
2990         uint8_t tc_num;
2991         uint8_t i;
2992
2993         tc_num = hns3_get_tc_num(hw);
2994         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2995
2996         if (hns3_dev_dcb_supported(hw))
2997                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2998                                         pf->dv_buf_size;
2999         else
3000                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
3001                                         + pf->dv_buf_size;
3002
3003         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
3004         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
3005                              HNS3_BUF_SIZE_UNIT);
3006
3007         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
3008         if (rx_all < rx_priv + shared_std)
3009                 return false;
3010
3011         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
3012         buf_alloc->s_buf.buf_size = shared_buf;
3013         if (hns3_dev_dcb_supported(hw)) {
3014                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
3015                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
3016                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
3017                                   HNS3_BUF_SIZE_UNIT);
3018         } else {
3019                 buf_alloc->s_buf.self.high =
3020                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3021                 buf_alloc->s_buf.self.low = aligned_mps;
3022         }
3023
3024         if (hns3_dev_dcb_supported(hw)) {
3025                 hi_thrd = shared_buf - pf->dv_buf_size;
3026
3027                 if (tc_num <= NEED_RESERVE_TC_NUM)
3028                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
3029                                         / BUF_MAX_PERCENT;
3030
3031                 if (tc_num)
3032                         hi_thrd = hi_thrd / tc_num;
3033
3034                 hi_thrd = max_t(uint32_t, hi_thrd,
3035                                 HNS3_BUF_MUL_BY * aligned_mps);
3036                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
3037                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
3038         } else {
3039                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
3040                 lo_thrd = aligned_mps;
3041         }
3042
3043         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3044                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
3045                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
3046         }
3047
3048         return true;
3049 }
3050
3051 static bool
3052 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
3053                      struct hns3_pkt_buf_alloc *buf_alloc)
3054 {
3055         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3056         struct hns3_pf *pf = &hns->pf;
3057         struct hns3_priv_buf *priv;
3058         uint32_t aligned_mps;
3059         uint32_t rx_all;
3060         uint8_t i;
3061
3062         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3063         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
3064
3065         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3066                 priv = &buf_alloc->priv_buf[i];
3067
3068                 priv->enable = 0;
3069                 priv->wl.low = 0;
3070                 priv->wl.high = 0;
3071                 priv->buf_size = 0;
3072
3073                 if (!(hw->hw_tc_map & BIT(i)))
3074                         continue;
3075
3076                 priv->enable = 1;
3077                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
3078                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
3079                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
3080                                                 HNS3_BUF_SIZE_UNIT);
3081                 } else {
3082                         priv->wl.low = 0;
3083                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
3084                                         aligned_mps;
3085                 }
3086
3087                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
3088         }
3089
3090         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3091 }
3092
3093 static bool
3094 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
3095                              struct hns3_pkt_buf_alloc *buf_alloc)
3096 {
3097         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3098         struct hns3_pf *pf = &hns->pf;
3099         struct hns3_priv_buf *priv;
3100         int no_pfc_priv_num;
3101         uint32_t rx_all;
3102         uint8_t mask;
3103         int i;
3104
3105         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3106         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
3107
3108         /* let the last to be cleared first */
3109         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3110                 priv = &buf_alloc->priv_buf[i];
3111                 mask = BIT((uint8_t)i);
3112
3113                 if (hw->hw_tc_map & mask &&
3114                     !(hw->dcb_info.hw_pfc_map & mask)) {
3115                         /* Clear the no pfc TC private buffer */
3116                         priv->wl.low = 0;
3117                         priv->wl.high = 0;
3118                         priv->buf_size = 0;
3119                         priv->enable = 0;
3120                         no_pfc_priv_num--;
3121                 }
3122
3123                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3124                     no_pfc_priv_num == 0)
3125                         break;
3126         }
3127
3128         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3129 }
3130
3131 static bool
3132 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3133                            struct hns3_pkt_buf_alloc *buf_alloc)
3134 {
3135         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3136         struct hns3_pf *pf = &hns->pf;
3137         struct hns3_priv_buf *priv;
3138         uint32_t rx_all;
3139         int pfc_priv_num;
3140         uint8_t mask;
3141         int i;
3142
3143         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3144         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3145
3146         /* let the last to be cleared first */
3147         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3148                 priv = &buf_alloc->priv_buf[i];
3149                 mask = BIT((uint8_t)i);
3150
3151                 if (hw->hw_tc_map & mask &&
3152                     hw->dcb_info.hw_pfc_map & mask) {
3153                         /* Reduce the number of pfc TC with private buffer */
3154                         priv->wl.low = 0;
3155                         priv->enable = 0;
3156                         priv->wl.high = 0;
3157                         priv->buf_size = 0;
3158                         pfc_priv_num--;
3159                 }
3160                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3161                     pfc_priv_num == 0)
3162                         break;
3163         }
3164
3165         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3166 }
3167
3168 static bool
3169 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3170                           struct hns3_pkt_buf_alloc *buf_alloc)
3171 {
3172 #define COMPENSATE_BUFFER       0x3C00
3173 #define COMPENSATE_HALF_MPS_NUM 5
3174 #define PRIV_WL_GAP             0x1800
3175         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3176         struct hns3_pf *pf = &hns->pf;
3177         uint32_t tc_num = hns3_get_tc_num(hw);
3178         uint32_t half_mps = pf->mps >> 1;
3179         struct hns3_priv_buf *priv;
3180         uint32_t min_rx_priv;
3181         uint32_t rx_priv;
3182         uint8_t i;
3183
3184         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3185         if (tc_num)
3186                 rx_priv = rx_priv / tc_num;
3187
3188         if (tc_num <= NEED_RESERVE_TC_NUM)
3189                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3190
3191         /*
3192          * Minimum value of private buffer in rx direction (min_rx_priv) is
3193          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3194          * buffer if rx_priv is greater than min_rx_priv.
3195          */
3196         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3197                         COMPENSATE_HALF_MPS_NUM * half_mps;
3198         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3199         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3200
3201         if (rx_priv < min_rx_priv)
3202                 return false;
3203
3204         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3205                 priv = &buf_alloc->priv_buf[i];
3206
3207                 priv->enable = 0;
3208                 priv->wl.low = 0;
3209                 priv->wl.high = 0;
3210                 priv->buf_size = 0;
3211
3212                 if (!(hw->hw_tc_map & BIT(i)))
3213                         continue;
3214
3215                 priv->enable = 1;
3216                 priv->buf_size = rx_priv;
3217                 priv->wl.high = rx_priv - pf->dv_buf_size;
3218                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3219         }
3220
3221         buf_alloc->s_buf.buf_size = 0;
3222
3223         return true;
3224 }
3225
3226 /*
3227  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3228  * @hw: pointer to struct hns3_hw
3229  * @buf_alloc: pointer to buffer calculation data
3230  * @return: 0: calculate sucessful, negative: fail
3231  */
3232 static int
3233 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3234 {
3235         /* When DCB is not supported, rx private buffer is not allocated. */
3236         if (!hns3_dev_dcb_supported(hw)) {
3237                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3238                 struct hns3_pf *pf = &hns->pf;
3239                 uint32_t rx_all = pf->pkt_buf_size;
3240
3241                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3242                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3243                         return -ENOMEM;
3244
3245                 return 0;
3246         }
3247
3248         /*
3249          * Try to allocate privated packet buffer for all TCs without share
3250          * buffer.
3251          */
3252         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3253                 return 0;
3254
3255         /*
3256          * Try to allocate privated packet buffer for all TCs with share
3257          * buffer.
3258          */
3259         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3260                 return 0;
3261
3262         /*
3263          * For different application scenes, the enabled port number, TC number
3264          * and no_drop TC number are different. In order to obtain the better
3265          * performance, software could allocate the buffer size and configure
3266          * the waterline by tring to decrease the private buffer size according
3267          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3268          * enabled tc.
3269          */
3270         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3271                 return 0;
3272
3273         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3274                 return 0;
3275
3276         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3277                 return 0;
3278
3279         return -ENOMEM;
3280 }
3281
3282 static int
3283 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3284 {
3285         struct hns3_rx_priv_buff_cmd *req;
3286         struct hns3_cmd_desc desc;
3287         uint32_t buf_size;
3288         int ret;
3289         int i;
3290
3291         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3292         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3293
3294         /* Alloc private buffer TCs */
3295         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3296                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3297
3298                 req->buf_num[i] =
3299                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3300                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3301         }
3302
3303         buf_size = buf_alloc->s_buf.buf_size;
3304         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3305                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3306
3307         ret = hns3_cmd_send(hw, &desc, 1);
3308         if (ret)
3309                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3310
3311         return ret;
3312 }
3313
3314 static int
3315 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3316 {
3317 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3318         struct hns3_rx_priv_wl_buf *req;
3319         struct hns3_priv_buf *priv;
3320         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3321         int i, j;
3322         int ret;
3323
3324         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3325                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3326                                           false);
3327                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3328
3329                 /* The first descriptor set the NEXT bit to 1 */
3330                 if (i == 0)
3331                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3332                 else
3333                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3334
3335                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3336                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3337
3338                         priv = &buf_alloc->priv_buf[idx];
3339                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3340                                                         HNS3_BUF_UNIT_S);
3341                         req->tc_wl[j].high |=
3342                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3343                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3344                                                         HNS3_BUF_UNIT_S);
3345                         req->tc_wl[j].low |=
3346                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3347                 }
3348         }
3349
3350         /* Send 2 descriptor at one time */
3351         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3352         if (ret)
3353                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3354                              ret);
3355         return ret;
3356 }
3357
3358 static int
3359 hns3_common_thrd_config(struct hns3_hw *hw,
3360                         struct hns3_pkt_buf_alloc *buf_alloc)
3361 {
3362 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3363         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3364         struct hns3_rx_com_thrd *req;
3365         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3366         struct hns3_tc_thrd *tc;
3367         int tc_idx;
3368         int i, j;
3369         int ret;
3370
3371         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3372                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3373                                           false);
3374                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3375
3376                 /* The first descriptor set the NEXT bit to 1 */
3377                 if (i == 0)
3378                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3379                 else
3380                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3381
3382                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3383                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3384                         tc = &s_buf->tc_thrd[tc_idx];
3385
3386                         req->com_thrd[j].high =
3387                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3388                         req->com_thrd[j].high |=
3389                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3390                         req->com_thrd[j].low =
3391                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3392                         req->com_thrd[j].low |=
3393                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3394                 }
3395         }
3396
3397         /* Send 2 descriptors at one time */
3398         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3399         if (ret)
3400                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3401
3402         return ret;
3403 }
3404
3405 static int
3406 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3407 {
3408         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3409         struct hns3_rx_com_wl *req;
3410         struct hns3_cmd_desc desc;
3411         int ret;
3412
3413         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3414
3415         req = (struct hns3_rx_com_wl *)desc.data;
3416         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3417         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3418
3419         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3420         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3421
3422         ret = hns3_cmd_send(hw, &desc, 1);
3423         if (ret)
3424                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3425
3426         return ret;
3427 }
3428
3429 int
3430 hns3_buffer_alloc(struct hns3_hw *hw)
3431 {
3432         struct hns3_pkt_buf_alloc pkt_buf;
3433         int ret;
3434
3435         memset(&pkt_buf, 0, sizeof(pkt_buf));
3436         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3437         if (ret) {
3438                 PMD_INIT_LOG(ERR,
3439                              "could not calc tx buffer size for all TCs %d",
3440                              ret);
3441                 return ret;
3442         }
3443
3444         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3445         if (ret) {
3446                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3447                 return ret;
3448         }
3449
3450         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3451         if (ret) {
3452                 PMD_INIT_LOG(ERR,
3453                              "could not calc rx priv buffer size for all TCs %d",
3454                              ret);
3455                 return ret;
3456         }
3457
3458         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3459         if (ret) {
3460                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3461                 return ret;
3462         }
3463
3464         if (hns3_dev_dcb_supported(hw)) {
3465                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3466                 if (ret) {
3467                         PMD_INIT_LOG(ERR,
3468                                      "could not configure rx private waterline %d",
3469                                      ret);
3470                         return ret;
3471                 }
3472
3473                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3474                 if (ret) {
3475                         PMD_INIT_LOG(ERR,
3476                                      "could not configure common threshold %d",
3477                                      ret);
3478                         return ret;
3479                 }
3480         }
3481
3482         ret = hns3_common_wl_config(hw, &pkt_buf);
3483         if (ret)
3484                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3485                              ret);
3486
3487         return ret;
3488 }
3489
3490 static int
3491 hns3_mac_init(struct hns3_hw *hw)
3492 {
3493         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3494         struct hns3_mac *mac = &hw->mac;
3495         struct hns3_pf *pf = &hns->pf;
3496         int ret;
3497
3498         pf->support_sfp_query = true;
3499         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3500         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3501         if (ret) {
3502                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3503                 return ret;
3504         }
3505
3506         mac->link_status = ETH_LINK_DOWN;
3507
3508         return hns3_config_mtu(hw, pf->mps);
3509 }
3510
3511 static int
3512 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3513 {
3514 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3515 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3516 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3517 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3518         int return_status;
3519
3520         if (cmdq_resp) {
3521                 PMD_INIT_LOG(ERR,
3522                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3523                              cmdq_resp);
3524                 return -EIO;
3525         }
3526
3527         switch (resp_code) {
3528         case HNS3_ETHERTYPE_SUCCESS_ADD:
3529         case HNS3_ETHERTYPE_ALREADY_ADD:
3530                 return_status = 0;
3531                 break;
3532         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3533                 PMD_INIT_LOG(ERR,
3534                              "add mac ethertype failed for manager table overflow.");
3535                 return_status = -EIO;
3536                 break;
3537         case HNS3_ETHERTYPE_KEY_CONFLICT:
3538                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3539                 return_status = -EIO;
3540                 break;
3541         default:
3542                 PMD_INIT_LOG(ERR,
3543                              "add mac ethertype failed for undefined, code=%d.",
3544                              resp_code);
3545                 return_status = -EIO;
3546         }
3547
3548         return return_status;
3549 }
3550
3551 static int
3552 hns3_add_mgr_tbl(struct hns3_hw *hw,
3553                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3554 {
3555         struct hns3_cmd_desc desc;
3556         uint8_t resp_code;
3557         uint16_t retval;
3558         int ret;
3559
3560         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3561         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3562
3563         ret = hns3_cmd_send(hw, &desc, 1);
3564         if (ret) {
3565                 PMD_INIT_LOG(ERR,
3566                              "add mac ethertype failed for cmd_send, ret =%d.",
3567                              ret);
3568                 return ret;
3569         }
3570
3571         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3572         retval = rte_le_to_cpu_16(desc.retval);
3573
3574         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3575 }
3576
3577 static void
3578 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3579                      int *table_item_num)
3580 {
3581         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3582
3583         /*
3584          * In current version, we add one item in management table as below:
3585          * 0x0180C200000E -- LLDP MC address
3586          */
3587         tbl = mgr_table;
3588         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3589         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3590         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3591         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3592         tbl->i_port_bitmap = 0x1;
3593         *table_item_num = 1;
3594 }
3595
3596 static int
3597 hns3_init_mgr_tbl(struct hns3_hw *hw)
3598 {
3599 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3600         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3601         int table_item_num;
3602         int ret;
3603         int i;
3604
3605         memset(mgr_table, 0, sizeof(mgr_table));
3606         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3607         for (i = 0; i < table_item_num; i++) {
3608                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3609                 if (ret) {
3610                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3611                                      ret);
3612                         return ret;
3613                 }
3614         }
3615
3616         return 0;
3617 }
3618
3619 static void
3620 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3621                         bool en_mc, bool en_bc, int vport_id)
3622 {
3623         if (!param)
3624                 return;
3625
3626         memset(param, 0, sizeof(struct hns3_promisc_param));
3627         if (en_uc)
3628                 param->enable = HNS3_PROMISC_EN_UC;
3629         if (en_mc)
3630                 param->enable |= HNS3_PROMISC_EN_MC;
3631         if (en_bc)
3632                 param->enable |= HNS3_PROMISC_EN_BC;
3633         param->vf_id = vport_id;
3634 }
3635
3636 static int
3637 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3638 {
3639         struct hns3_promisc_cfg_cmd *req;
3640         struct hns3_cmd_desc desc;
3641         int ret;
3642
3643         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3644
3645         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3646         req->vf_id = param->vf_id;
3647         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3648             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3649
3650         ret = hns3_cmd_send(hw, &desc, 1);
3651         if (ret)
3652                 PMD_INIT_LOG(ERR, "Set promisc mode fail, ret = %d", ret);
3653
3654         return ret;
3655 }
3656
3657 static int
3658 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3659 {
3660         struct hns3_promisc_param param;
3661         bool en_bc_pmc = true;
3662         uint8_t vf_id;
3663         int ret;
3664
3665         /*
3666          * In current version VF is not supported when PF is driven by DPDK
3667          * driver, the PF-related vf_id is 0, just need to configure parameters
3668          * for vf_id 0.
3669          */
3670         vf_id = 0;
3671
3672         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3673         ret = hns3_cmd_set_promisc_mode(hw, &param);
3674         if (ret)
3675                 return ret;
3676
3677         return 0;
3678 }
3679
3680 static int
3681 hns3_clear_all_vfs_promisc_mode(struct hns3_hw *hw)
3682 {
3683         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3684         struct hns3_pf *pf = &hns->pf;
3685         struct hns3_promisc_param param;
3686         uint16_t func_id;
3687         int ret;
3688
3689         /* func_id 0 is denoted PF, the VFs start from 1 */
3690         for (func_id = 1; func_id < pf->func_num; func_id++) {
3691                 hns3_promisc_param_init(&param, false, false, false, func_id);
3692                 ret = hns3_cmd_set_promisc_mode(hw, &param);
3693                 if (ret)
3694                         return ret;
3695         }
3696
3697         return 0;
3698 }
3699
3700 static int
3701 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3702 {
3703         struct hns3_adapter *hns = dev->data->dev_private;
3704         struct hns3_hw *hw = &hns->hw;
3705         int ret;
3706
3707         rte_spinlock_lock(&hw->lock);
3708         ret = hns3_set_promisc_mode(hw, true, true);
3709         rte_spinlock_unlock(&hw->lock);
3710         if (ret)
3711                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
3712                          ret);
3713
3714         return ret;
3715 }
3716
3717 static int
3718 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3719 {
3720         bool allmulti = dev->data->all_multicast ? true : false;
3721         struct hns3_adapter *hns = dev->data->dev_private;
3722         struct hns3_hw *hw = &hns->hw;
3723         int ret;
3724
3725         /* If now in all_multicast mode, must remain in all_multicast mode. */
3726         rte_spinlock_lock(&hw->lock);
3727         ret = hns3_set_promisc_mode(hw, false, allmulti);
3728         rte_spinlock_unlock(&hw->lock);
3729         if (ret)
3730                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
3731                          ret);
3732
3733         return ret;
3734 }
3735
3736 static int
3737 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3738 {
3739         struct hns3_adapter *hns = dev->data->dev_private;
3740         struct hns3_hw *hw = &hns->hw;
3741         int ret;
3742
3743         if (dev->data->promiscuous)
3744                 return 0;
3745
3746         rte_spinlock_lock(&hw->lock);
3747         ret = hns3_set_promisc_mode(hw, false, true);
3748         rte_spinlock_unlock(&hw->lock);
3749         if (ret)
3750                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
3751                          ret);
3752
3753         return ret;
3754 }
3755
3756 static int
3757 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3758 {
3759         struct hns3_adapter *hns = dev->data->dev_private;
3760         struct hns3_hw *hw = &hns->hw;
3761         int ret;
3762
3763         /* If now in promiscuous mode, must remain in all_multicast mode. */
3764         if (dev->data->promiscuous)
3765                 return 0;
3766
3767         rte_spinlock_lock(&hw->lock);
3768         ret = hns3_set_promisc_mode(hw, false, false);
3769         rte_spinlock_unlock(&hw->lock);
3770         if (ret)
3771                 hns3_err(hw, "Failed to disable allmulticast mode, ret =  %d",
3772                          ret);
3773
3774         return ret;
3775 }
3776
3777 static int
3778 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3779 {
3780         struct hns3_hw *hw = &hns->hw;
3781         bool allmulti = hw->data->all_multicast ? true : false;
3782
3783         if (hw->data->promiscuous)
3784                 return hns3_set_promisc_mode(hw, true, true);
3785
3786         return hns3_set_promisc_mode(hw, false, allmulti);
3787 }
3788
3789 static int
3790 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3791 {
3792         struct hns3_sfp_speed_cmd *resp;
3793         struct hns3_cmd_desc desc;
3794         int ret;
3795
3796         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3797         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3798         ret = hns3_cmd_send(hw, &desc, 1);
3799         if (ret == -EOPNOTSUPP) {
3800                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3801                 return ret;
3802         } else if (ret) {
3803                 hns3_err(hw, "get sfp speed failed %d", ret);
3804                 return ret;
3805         }
3806
3807         *speed = resp->sfp_speed;
3808
3809         return 0;
3810 }
3811
3812 static uint8_t
3813 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3814 {
3815         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3816                 duplex = ETH_LINK_FULL_DUPLEX;
3817
3818         return duplex;
3819 }
3820
3821 static int
3822 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3823 {
3824         struct hns3_mac *mac = &hw->mac;
3825         int ret;
3826
3827         duplex = hns3_check_speed_dup(duplex, speed);
3828         if (mac->link_speed == speed && mac->link_duplex == duplex)
3829                 return 0;
3830
3831         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3832         if (ret)
3833                 return ret;
3834
3835         mac->link_speed = speed;
3836         mac->link_duplex = duplex;
3837
3838         return 0;
3839 }
3840
3841 static int
3842 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3843 {
3844         struct hns3_adapter *hns = eth_dev->data->dev_private;
3845         struct hns3_hw *hw = &hns->hw;
3846         struct hns3_pf *pf = &hns->pf;
3847         uint32_t speed;
3848         int ret;
3849
3850         /* If IMP do not support get SFP/qSFP speed, return directly */
3851         if (!pf->support_sfp_query)
3852                 return 0;
3853
3854         ret = hns3_get_sfp_speed(hw, &speed);
3855         if (ret == -EOPNOTSUPP) {
3856                 pf->support_sfp_query = false;
3857                 return ret;
3858         } else if (ret)
3859                 return ret;
3860
3861         if (speed == ETH_SPEED_NUM_NONE)
3862                 return 0; /* do nothing if no SFP */
3863
3864         /* Config full duplex for SFP */
3865         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3866 }
3867
3868 static int
3869 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3870 {
3871         struct hns3_config_mac_mode_cmd *req;
3872         struct hns3_cmd_desc desc;
3873         uint32_t loop_en = 0;
3874         uint8_t val = 0;
3875         int ret;
3876
3877         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3878
3879         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3880         if (enable)
3881                 val = 1;
3882         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3883         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3884         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3885         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3886         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3887         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3888         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3889         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3890         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3891         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3892         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3893         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3894         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3895         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3896         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3897
3898         ret = hns3_cmd_send(hw, &desc, 1);
3899         if (ret)
3900                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3901
3902         return ret;
3903 }
3904
3905 static int
3906 hns3_get_mac_link_status(struct hns3_hw *hw)
3907 {
3908         struct hns3_link_status_cmd *req;
3909         struct hns3_cmd_desc desc;
3910         int link_status;
3911         int ret;
3912
3913         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3914         ret = hns3_cmd_send(hw, &desc, 1);
3915         if (ret) {
3916                 hns3_err(hw, "get link status cmd failed %d", ret);
3917                 return ETH_LINK_DOWN;
3918         }
3919
3920         req = (struct hns3_link_status_cmd *)desc.data;
3921         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3922
3923         return !!link_status;
3924 }
3925
3926 void
3927 hns3_update_link_status(struct hns3_hw *hw)
3928 {
3929         int state;
3930
3931         state = hns3_get_mac_link_status(hw);
3932         if (state != hw->mac.link_status) {
3933                 hw->mac.link_status = state;
3934                 hns3_warn(hw, "Link status change to %s!", state ? "up" : "down");
3935         }
3936 }
3937
3938 static void
3939 hns3_service_handler(void *param)
3940 {
3941         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3942         struct hns3_adapter *hns = eth_dev->data->dev_private;
3943         struct hns3_hw *hw = &hns->hw;
3944
3945         if (!hns3_is_reset_pending(hns)) {
3946                 hns3_update_speed_duplex(eth_dev);
3947                 hns3_update_link_status(hw);
3948         } else
3949                 hns3_warn(hw, "Cancel the query when reset is pending");
3950
3951         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3952 }
3953
3954 static int
3955 hns3_init_hardware(struct hns3_adapter *hns)
3956 {
3957         struct hns3_hw *hw = &hns->hw;
3958         int ret;
3959
3960         ret = hns3_map_tqp(hw);
3961         if (ret) {
3962                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3963                 return ret;
3964         }
3965
3966         ret = hns3_init_umv_space(hw);
3967         if (ret) {
3968                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3969                 return ret;
3970         }
3971
3972         ret = hns3_mac_init(hw);
3973         if (ret) {
3974                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3975                 goto err_mac_init;
3976         }
3977
3978         ret = hns3_init_mgr_tbl(hw);
3979         if (ret) {
3980                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3981                 goto err_mac_init;
3982         }
3983
3984         ret = hns3_set_promisc_mode(hw, false, false);
3985         if (ret) {
3986                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3987                 goto err_mac_init;
3988         }
3989
3990         ret = hns3_clear_all_vfs_promisc_mode(hw);
3991         if (ret) {
3992                 PMD_INIT_LOG(ERR, "Failed to clear all vfs promisc mode: %d",
3993                              ret);
3994                 goto err_mac_init;
3995         }
3996
3997         ret = hns3_init_vlan_config(hns);
3998         if (ret) {
3999                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
4000                 goto err_mac_init;
4001         }
4002
4003         ret = hns3_dcb_init(hw);
4004         if (ret) {
4005                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
4006                 goto err_mac_init;
4007         }
4008
4009         ret = hns3_init_fd_config(hns);
4010         if (ret) {
4011                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
4012                 goto err_mac_init;
4013         }
4014
4015         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
4016         if (ret) {
4017                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
4018                 goto err_mac_init;
4019         }
4020
4021         ret = hns3_config_gro(hw, false);
4022         if (ret) {
4023                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
4024                 goto err_mac_init;
4025         }
4026         return 0;
4027
4028 err_mac_init:
4029         hns3_uninit_umv_space(hw);
4030         return ret;
4031 }
4032
4033 static int
4034 hns3_init_pf(struct rte_eth_dev *eth_dev)
4035 {
4036         struct rte_device *dev = eth_dev->device;
4037         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4038         struct hns3_adapter *hns = eth_dev->data->dev_private;
4039         struct hns3_hw *hw = &hns->hw;
4040         int ret;
4041
4042         PMD_INIT_FUNC_TRACE();
4043
4044         /* Get hardware io base address from pcie BAR2 IO space */
4045         hw->io_base = pci_dev->mem_resource[2].addr;
4046
4047         /* Firmware command queue initialize */
4048         ret = hns3_cmd_init_queue(hw);
4049         if (ret) {
4050                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
4051                 goto err_cmd_init_queue;
4052         }
4053
4054         hns3_clear_all_event_cause(hw);
4055
4056         /* Firmware command initialize */
4057         ret = hns3_cmd_init(hw);
4058         if (ret) {
4059                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
4060                 goto err_cmd_init;
4061         }
4062
4063         ret = rte_intr_callback_register(&pci_dev->intr_handle,
4064                                          hns3_interrupt_handler,
4065                                          eth_dev);
4066         if (ret) {
4067                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
4068                 goto err_intr_callback_register;
4069         }
4070
4071         /* Enable interrupt */
4072         rte_intr_enable(&pci_dev->intr_handle);
4073         hns3_pf_enable_irq0(hw);
4074
4075         /* Get configuration */
4076         ret = hns3_get_configuration(hw);
4077         if (ret) {
4078                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
4079                 goto err_get_config;
4080         }
4081
4082         ret = hns3_init_hardware(hns);
4083         if (ret) {
4084                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
4085                 goto err_get_config;
4086         }
4087
4088         /* Initialize flow director filter list & hash */
4089         ret = hns3_fdir_filter_init(hns);
4090         if (ret) {
4091                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
4092                 goto err_hw_init;
4093         }
4094
4095         hns3_set_default_rss_args(hw);
4096
4097         ret = hns3_enable_hw_error_intr(hns, true);
4098         if (ret) {
4099                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
4100                              ret);
4101                 goto err_fdir;
4102         }
4103
4104         /*
4105          * In the initialization clearing the all hardware mapping relationship
4106          * configurations between queues and interrupt vectors is needed, so
4107          * some error caused by the residual configurations, such as the
4108          * unexpected interrupt, can be avoid.
4109          */
4110         ret = hns3_init_ring_with_vector(hw);
4111         if (ret)
4112                 goto err_fdir;
4113
4114         return 0;
4115
4116 err_fdir:
4117         hns3_fdir_filter_uninit(hns);
4118 err_hw_init:
4119         hns3_uninit_umv_space(hw);
4120
4121 err_get_config:
4122         hns3_pf_disable_irq0(hw);
4123         rte_intr_disable(&pci_dev->intr_handle);
4124         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4125                              eth_dev);
4126
4127 err_intr_callback_register:
4128         hns3_cmd_uninit(hw);
4129
4130 err_cmd_init:
4131         hns3_cmd_destroy_queue(hw);
4132
4133 err_cmd_init_queue:
4134         hw->io_base = NULL;
4135
4136         return ret;
4137 }
4138
4139 static void
4140 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
4141 {
4142         struct hns3_adapter *hns = eth_dev->data->dev_private;
4143         struct rte_device *dev = eth_dev->device;
4144         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4145         struct hns3_hw *hw = &hns->hw;
4146
4147         PMD_INIT_FUNC_TRACE();
4148
4149         hns3_enable_hw_error_intr(hns, false);
4150         hns3_rss_uninit(hns);
4151         hns3_fdir_filter_uninit(hns);
4152         hns3_uninit_umv_space(hw);
4153         hns3_pf_disable_irq0(hw);
4154         rte_intr_disable(&pci_dev->intr_handle);
4155         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
4156                              eth_dev);
4157         hns3_cmd_uninit(hw);
4158         hns3_cmd_destroy_queue(hw);
4159         hw->io_base = NULL;
4160 }
4161
4162 static int
4163 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
4164 {
4165         struct hns3_hw *hw = &hns->hw;
4166         int ret;
4167
4168         ret = hns3_dcb_cfg_update(hns);
4169         if (ret)
4170                 return ret;
4171
4172         /* Enable queues */
4173         ret = hns3_start_queues(hns, reset_queue);
4174         if (ret) {
4175                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4176                 return ret;
4177         }
4178
4179         /* Enable MAC */
4180         ret = hns3_cfg_mac_mode(hw, true);
4181         if (ret) {
4182                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4183                 goto err_config_mac_mode;
4184         }
4185         return 0;
4186
4187 err_config_mac_mode:
4188         hns3_stop_queues(hns, true);
4189         return ret;
4190 }
4191
4192 static int
4193 hns3_map_rx_interrupt(struct rte_eth_dev *dev)
4194 {
4195         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4196         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4197         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198         uint32_t intr_vector;
4199         uint8_t base = 0;
4200         uint8_t vec = 0;
4201         uint16_t q_id;
4202         int ret;
4203
4204         if (dev->data->dev_conf.intr_conf.rxq == 0)
4205                 return 0;
4206
4207         /* disable uio/vfio intr/eventfd mapping */
4208         rte_intr_disable(intr_handle);
4209
4210         /* check and configure queue intr-vector mapping */
4211         if (rte_intr_cap_multiple(intr_handle) ||
4212             !RTE_ETH_DEV_SRIOV(dev).active) {
4213                 intr_vector = hw->used_rx_queues;
4214                 /* creates event fd for each intr vector when MSIX is used */
4215                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4216                         return -EINVAL;
4217         }
4218         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4219                 intr_handle->intr_vec =
4220                         rte_zmalloc("intr_vec",
4221                                     hw->used_rx_queues * sizeof(int), 0);
4222                 if (intr_handle->intr_vec == NULL) {
4223                         hns3_err(hw, "Failed to allocate %d rx_queues"
4224                                      " intr_vec", hw->used_rx_queues);
4225                         ret = -ENOMEM;
4226                         goto alloc_intr_vec_error;
4227                 }
4228         }
4229
4230         if (rte_intr_allow_others(intr_handle)) {
4231                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4232                 base = RTE_INTR_VEC_RXTX_OFFSET;
4233         }
4234         if (rte_intr_dp_is_en(intr_handle)) {
4235                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4236                         ret = hns3_bind_ring_with_vector(hw, vec, true,
4237                                                          HNS3_RING_TYPE_RX,
4238                                                          q_id);
4239                         if (ret)
4240                                 goto bind_vector_error;
4241                         intr_handle->intr_vec[q_id] = vec;
4242                         if (vec < base + intr_handle->nb_efd - 1)
4243                                 vec++;
4244                 }
4245         }
4246         rte_intr_enable(intr_handle);
4247         return 0;
4248
4249 bind_vector_error:
4250         rte_intr_efd_disable(intr_handle);
4251         if (intr_handle->intr_vec) {
4252                 free(intr_handle->intr_vec);
4253                 intr_handle->intr_vec = NULL;
4254         }
4255         return ret;
4256 alloc_intr_vec_error:
4257         rte_intr_efd_disable(intr_handle);
4258         return ret;
4259 }
4260
4261 static int
4262 hns3_dev_start(struct rte_eth_dev *dev)
4263 {
4264         struct hns3_adapter *hns = dev->data->dev_private;
4265         struct hns3_hw *hw = &hns->hw;
4266         int ret;
4267
4268         PMD_INIT_FUNC_TRACE();
4269         if (rte_atomic16_read(&hw->reset.resetting))
4270                 return -EBUSY;
4271
4272         rte_spinlock_lock(&hw->lock);
4273         hw->adapter_state = HNS3_NIC_STARTING;
4274
4275         ret = hns3_do_start(hns, true);
4276         if (ret) {
4277                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4278                 rte_spinlock_unlock(&hw->lock);
4279                 return ret;
4280         }
4281
4282         hw->adapter_state = HNS3_NIC_STARTED;
4283         rte_spinlock_unlock(&hw->lock);
4284
4285         ret = hns3_map_rx_interrupt(dev);
4286         if (ret)
4287                 return ret;
4288         hns3_set_rxtx_function(dev);
4289         hns3_mp_req_start_rxtx(dev);
4290         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, dev);
4291
4292         hns3_info(hw, "hns3 dev start successful!");
4293         return 0;
4294 }
4295
4296 static int
4297 hns3_do_stop(struct hns3_adapter *hns)
4298 {
4299         struct hns3_hw *hw = &hns->hw;
4300         bool reset_queue;
4301         int ret;
4302
4303         ret = hns3_cfg_mac_mode(hw, false);
4304         if (ret)
4305                 return ret;
4306         hw->mac.link_status = ETH_LINK_DOWN;
4307
4308         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4309                 hns3_configure_all_mac_addr(hns, true);
4310                 reset_queue = true;
4311         } else
4312                 reset_queue = false;
4313         hw->mac.default_addr_setted = false;
4314         return hns3_stop_queues(hns, reset_queue);
4315 }
4316
4317 static void
4318 hns3_unmap_rx_interrupt(struct rte_eth_dev *dev)
4319 {
4320         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4321         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4322         struct hns3_adapter *hns = dev->data->dev_private;
4323         struct hns3_hw *hw = &hns->hw;
4324         uint8_t base = 0;
4325         uint8_t vec = 0;
4326         uint16_t q_id;
4327
4328         if (dev->data->dev_conf.intr_conf.rxq == 0)
4329                 return;
4330
4331         /* unmap the ring with vector */
4332         if (rte_intr_allow_others(intr_handle)) {
4333                 vec = RTE_INTR_VEC_RXTX_OFFSET;
4334                 base = RTE_INTR_VEC_RXTX_OFFSET;
4335         }
4336         if (rte_intr_dp_is_en(intr_handle)) {
4337                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
4338                         (void)hns3_bind_ring_with_vector(hw, vec, false,
4339                                                          HNS3_RING_TYPE_RX,
4340                                                          q_id);
4341                         if (vec < base + intr_handle->nb_efd - 1)
4342                                 vec++;
4343                 }
4344         }
4345         /* Clean datapath event and queue/vec mapping */
4346         rte_intr_efd_disable(intr_handle);
4347         if (intr_handle->intr_vec) {
4348                 rte_free(intr_handle->intr_vec);
4349                 intr_handle->intr_vec = NULL;
4350         }
4351 }
4352
4353 static void
4354 hns3_dev_stop(struct rte_eth_dev *dev)
4355 {
4356         struct hns3_adapter *hns = dev->data->dev_private;
4357         struct hns3_hw *hw = &hns->hw;
4358
4359         PMD_INIT_FUNC_TRACE();
4360
4361         hw->adapter_state = HNS3_NIC_STOPPING;
4362         hns3_set_rxtx_function(dev);
4363         rte_wmb();
4364         /* Disable datapath on secondary process. */
4365         hns3_mp_req_stop_rxtx(dev);
4366         /* Prevent crashes when queues are still in use. */
4367         rte_delay_ms(hw->tqps_num);
4368
4369         rte_spinlock_lock(&hw->lock);
4370         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4371                 hns3_do_stop(hns);
4372                 hns3_dev_release_mbufs(hns);
4373                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4374         }
4375         rte_eal_alarm_cancel(hns3_service_handler, dev);
4376         rte_spinlock_unlock(&hw->lock);
4377         hns3_unmap_rx_interrupt(dev);
4378 }
4379
4380 static void
4381 hns3_dev_close(struct rte_eth_dev *eth_dev)
4382 {
4383         struct hns3_adapter *hns = eth_dev->data->dev_private;
4384         struct hns3_hw *hw = &hns->hw;
4385
4386         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4387                 rte_free(eth_dev->process_private);
4388                 eth_dev->process_private = NULL;
4389                 return;
4390         }
4391
4392         if (hw->adapter_state == HNS3_NIC_STARTED)
4393                 hns3_dev_stop(eth_dev);
4394
4395         hw->adapter_state = HNS3_NIC_CLOSING;
4396         hns3_reset_abort(hns);
4397         hw->adapter_state = HNS3_NIC_CLOSED;
4398
4399         hns3_configure_all_mc_mac_addr(hns, true);
4400         hns3_remove_all_vlan_table(hns);
4401         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4402         hns3_uninit_pf(eth_dev);
4403         hns3_free_all_queues(eth_dev);
4404         rte_free(hw->reset.wait_data);
4405         rte_free(eth_dev->process_private);
4406         eth_dev->process_private = NULL;
4407         hns3_mp_uninit_primary();
4408         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4409 }
4410
4411 static int
4412 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4413 {
4414         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4416
4417         fc_conf->pause_time = pf->pause_time;
4418
4419         /* return fc current mode */
4420         switch (hw->current_mode) {
4421         case HNS3_FC_FULL:
4422                 fc_conf->mode = RTE_FC_FULL;
4423                 break;
4424         case HNS3_FC_TX_PAUSE:
4425                 fc_conf->mode = RTE_FC_TX_PAUSE;
4426                 break;
4427         case HNS3_FC_RX_PAUSE:
4428                 fc_conf->mode = RTE_FC_RX_PAUSE;
4429                 break;
4430         case HNS3_FC_NONE:
4431         default:
4432                 fc_conf->mode = RTE_FC_NONE;
4433                 break;
4434         }
4435
4436         return 0;
4437 }
4438
4439 static void
4440 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4441 {
4442         switch (mode) {
4443         case RTE_FC_NONE:
4444                 hw->requested_mode = HNS3_FC_NONE;
4445                 break;
4446         case RTE_FC_RX_PAUSE:
4447                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4448                 break;
4449         case RTE_FC_TX_PAUSE:
4450                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4451                 break;
4452         case RTE_FC_FULL:
4453                 hw->requested_mode = HNS3_FC_FULL;
4454                 break;
4455         default:
4456                 hw->requested_mode = HNS3_FC_NONE;
4457                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4458                           "configured to RTE_FC_NONE", mode);
4459                 break;
4460         }
4461 }
4462
4463 static int
4464 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4465 {
4466         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4467         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4468         int ret;
4469
4470         if (fc_conf->high_water || fc_conf->low_water ||
4471             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4472                 hns3_err(hw, "Unsupported flow control settings specified, "
4473                          "high_water(%u), low_water(%u), send_xon(%u) and "
4474                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4475                          fc_conf->high_water, fc_conf->low_water,
4476                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4477                 return -EINVAL;
4478         }
4479         if (fc_conf->autoneg) {
4480                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4481                 return -EINVAL;
4482         }
4483         if (!fc_conf->pause_time) {
4484                 hns3_err(hw, "Invalid pause time %d setting.",
4485                          fc_conf->pause_time);
4486                 return -EINVAL;
4487         }
4488
4489         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4490             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4491                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4492                          "current_fc_status = %d", hw->current_fc_status);
4493                 return -EOPNOTSUPP;
4494         }
4495
4496         hns3_get_fc_mode(hw, fc_conf->mode);
4497         if (hw->requested_mode == hw->current_mode &&
4498             pf->pause_time == fc_conf->pause_time)
4499                 return 0;
4500
4501         rte_spinlock_lock(&hw->lock);
4502         ret = hns3_fc_enable(dev, fc_conf);
4503         rte_spinlock_unlock(&hw->lock);
4504
4505         return ret;
4506 }
4507
4508 static int
4509 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4510                             struct rte_eth_pfc_conf *pfc_conf)
4511 {
4512         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4513         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4514         uint8_t priority;
4515         int ret;
4516
4517         if (!hns3_dev_dcb_supported(hw)) {
4518                 hns3_err(hw, "This port does not support dcb configurations.");
4519                 return -EOPNOTSUPP;
4520         }
4521
4522         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4523             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4524                 hns3_err(hw, "Unsupported flow control settings specified, "
4525                          "high_water(%u), low_water(%u), send_xon(%u) and "
4526                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4527                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4528                          pfc_conf->fc.send_xon,
4529                          pfc_conf->fc.mac_ctrl_frame_fwd);
4530                 return -EINVAL;
4531         }
4532         if (pfc_conf->fc.autoneg) {
4533                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4534                 return -EINVAL;
4535         }
4536         if (pfc_conf->fc.pause_time == 0) {
4537                 hns3_err(hw, "Invalid pause time %d setting.",
4538                          pfc_conf->fc.pause_time);
4539                 return -EINVAL;
4540         }
4541
4542         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4543             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4544                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4545                              "current_fc_status = %d", hw->current_fc_status);
4546                 return -EOPNOTSUPP;
4547         }
4548
4549         priority = pfc_conf->priority;
4550         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4551         if (hw->dcb_info.pfc_en & BIT(priority) &&
4552             hw->requested_mode == hw->current_mode &&
4553             pfc_conf->fc.pause_time == pf->pause_time)
4554                 return 0;
4555
4556         rte_spinlock_lock(&hw->lock);
4557         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4558         rte_spinlock_unlock(&hw->lock);
4559
4560         return ret;
4561 }
4562
4563 static int
4564 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4565 {
4566         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4567         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4568         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4569         int i;
4570
4571         rte_spinlock_lock(&hw->lock);
4572         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4573                 dcb_info->nb_tcs = pf->local_max_tc;
4574         else
4575                 dcb_info->nb_tcs = 1;
4576
4577         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4578                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4579         for (i = 0; i < dcb_info->nb_tcs; i++)
4580                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4581
4582         for (i = 0; i < hw->num_tc; i++) {
4583                 dcb_info->tc_queue.tc_rxq[0][i].base = hw->alloc_rss_size * i;
4584                 dcb_info->tc_queue.tc_txq[0][i].base =
4585                                                 hw->tc_queue[i].tqp_offset;
4586                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = hw->alloc_rss_size;
4587                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4588                                                 hw->tc_queue[i].tqp_count;
4589         }
4590         rte_spinlock_unlock(&hw->lock);
4591
4592         return 0;
4593 }
4594
4595 static int
4596 hns3_reinit_dev(struct hns3_adapter *hns)
4597 {
4598         struct hns3_hw *hw = &hns->hw;
4599         int ret;
4600
4601         ret = hns3_cmd_init(hw);
4602         if (ret) {
4603                 hns3_err(hw, "Failed to init cmd: %d", ret);
4604                 return ret;
4605         }
4606
4607         ret = hns3_reset_all_queues(hns);
4608         if (ret) {
4609                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4610                 goto err_init;
4611         }
4612
4613         ret = hns3_init_hardware(hns);
4614         if (ret) {
4615                 hns3_err(hw, "Failed to init hardware: %d", ret);
4616                 goto err_init;
4617         }
4618
4619         ret = hns3_enable_hw_error_intr(hns, true);
4620         if (ret) {
4621                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4622                              ret);
4623                 goto err_mac_init;
4624         }
4625         hns3_info(hw, "Reset done, driver initialization finished.");
4626
4627         return 0;
4628
4629 err_mac_init:
4630         hns3_uninit_umv_space(hw);
4631 err_init:
4632         hns3_cmd_uninit(hw);
4633
4634         return ret;
4635 }
4636
4637 static bool
4638 is_pf_reset_done(struct hns3_hw *hw)
4639 {
4640         uint32_t val, reg, reg_bit;
4641
4642         switch (hw->reset.level) {
4643         case HNS3_IMP_RESET:
4644                 reg = HNS3_GLOBAL_RESET_REG;
4645                 reg_bit = HNS3_IMP_RESET_BIT;
4646                 break;
4647         case HNS3_GLOBAL_RESET:
4648                 reg = HNS3_GLOBAL_RESET_REG;
4649                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4650                 break;
4651         case HNS3_FUNC_RESET:
4652                 reg = HNS3_FUN_RST_ING;
4653                 reg_bit = HNS3_FUN_RST_ING_B;
4654                 break;
4655         case HNS3_FLR_RESET:
4656         default:
4657                 hns3_err(hw, "Wait for unsupported reset level: %d",
4658                          hw->reset.level);
4659                 return true;
4660         }
4661         val = hns3_read_dev(hw, reg);
4662         if (hns3_get_bit(val, reg_bit))
4663                 return false;
4664         else
4665                 return true;
4666 }
4667
4668 bool
4669 hns3_is_reset_pending(struct hns3_adapter *hns)
4670 {
4671         struct hns3_hw *hw = &hns->hw;
4672         enum hns3_reset_level reset;
4673
4674         hns3_check_event_cause(hns, NULL);
4675         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4676         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4677                 hns3_warn(hw, "High level reset %d is pending", reset);
4678                 return true;
4679         }
4680         reset = hns3_get_reset_level(hns, &hw->reset.request);
4681         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4682                 hns3_warn(hw, "High level reset %d is request", reset);
4683                 return true;
4684         }
4685         return false;
4686 }
4687
4688 static int
4689 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4690 {
4691         struct hns3_hw *hw = &hns->hw;
4692         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4693         struct timeval tv;
4694
4695         if (wait_data->result == HNS3_WAIT_SUCCESS)
4696                 return 0;
4697         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4698                 gettimeofday(&tv, NULL);
4699                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4700                           tv.tv_sec, tv.tv_usec);
4701                 return -ETIME;
4702         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4703                 return -EAGAIN;
4704
4705         wait_data->hns = hns;
4706         wait_data->check_completion = is_pf_reset_done;
4707         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4708                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4709         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4710         wait_data->count = HNS3_RESET_WAIT_CNT;
4711         wait_data->result = HNS3_WAIT_REQUEST;
4712         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4713         return -EAGAIN;
4714 }
4715
4716 static int
4717 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4718 {
4719         struct hns3_cmd_desc desc;
4720         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4721
4722         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4723         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4724         req->fun_reset_vfid = func_id;
4725
4726         return hns3_cmd_send(hw, &desc, 1);
4727 }
4728
4729 static int
4730 hns3_imp_reset_cmd(struct hns3_hw *hw)
4731 {
4732         struct hns3_cmd_desc desc;
4733
4734         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4735         desc.data[0] = 0xeedd;
4736
4737         return hns3_cmd_send(hw, &desc, 1);
4738 }
4739
4740 static void
4741 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4742 {
4743         struct hns3_hw *hw = &hns->hw;
4744         struct timeval tv;
4745         uint32_t val;
4746
4747         gettimeofday(&tv, NULL);
4748         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4749             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4750                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4751                           tv.tv_sec, tv.tv_usec);
4752                 return;
4753         }
4754
4755         switch (reset_level) {
4756         case HNS3_IMP_RESET:
4757                 hns3_imp_reset_cmd(hw);
4758                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4759                           tv.tv_sec, tv.tv_usec);
4760                 break;
4761         case HNS3_GLOBAL_RESET:
4762                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4763                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4764                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4765                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4766                           tv.tv_sec, tv.tv_usec);
4767                 break;
4768         case HNS3_FUNC_RESET:
4769                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4770                           tv.tv_sec, tv.tv_usec);
4771                 /* schedule again to check later */
4772                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4773                 hns3_schedule_reset(hns);
4774                 break;
4775         default:
4776                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4777                 return;
4778         }
4779         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4780 }
4781
4782 static enum hns3_reset_level
4783 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4784 {
4785         struct hns3_hw *hw = &hns->hw;
4786         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4787
4788         /* Return the highest priority reset level amongst all */
4789         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4790                 reset_level = HNS3_IMP_RESET;
4791         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4792                 reset_level = HNS3_GLOBAL_RESET;
4793         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4794                 reset_level = HNS3_FUNC_RESET;
4795         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4796                 reset_level = HNS3_FLR_RESET;
4797
4798         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4799                 return HNS3_NONE_RESET;
4800
4801         return reset_level;
4802 }
4803
4804 static int
4805 hns3_prepare_reset(struct hns3_adapter *hns)
4806 {
4807         struct hns3_hw *hw = &hns->hw;
4808         uint32_t reg_val;
4809         int ret;
4810
4811         switch (hw->reset.level) {
4812         case HNS3_FUNC_RESET:
4813                 ret = hns3_func_reset_cmd(hw, 0);
4814                 if (ret)
4815                         return ret;
4816
4817                 /*
4818                  * After performaning pf reset, it is not necessary to do the
4819                  * mailbox handling or send any command to firmware, because
4820                  * any mailbox handling or command to firmware is only valid
4821                  * after hns3_cmd_init is called.
4822                  */
4823                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4824                 hw->reset.stats.request_cnt++;
4825                 break;
4826         case HNS3_IMP_RESET:
4827                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4828                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4829                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4830                 break;
4831         default:
4832                 break;
4833         }
4834         return 0;
4835 }
4836
4837 static int
4838 hns3_set_rst_done(struct hns3_hw *hw)
4839 {
4840         struct hns3_pf_rst_done_cmd *req;
4841         struct hns3_cmd_desc desc;
4842
4843         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4844         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4845         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4846         return hns3_cmd_send(hw, &desc, 1);
4847 }
4848
4849 static int
4850 hns3_stop_service(struct hns3_adapter *hns)
4851 {
4852         struct hns3_hw *hw = &hns->hw;
4853         struct rte_eth_dev *eth_dev;
4854
4855         eth_dev = &rte_eth_devices[hw->data->port_id];
4856         if (hw->adapter_state == HNS3_NIC_STARTED)
4857                 rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4858         hw->mac.link_status = ETH_LINK_DOWN;
4859
4860         hns3_set_rxtx_function(eth_dev);
4861         rte_wmb();
4862         /* Disable datapath on secondary process. */
4863         hns3_mp_req_stop_rxtx(eth_dev);
4864         rte_delay_ms(hw->tqps_num);
4865
4866         rte_spinlock_lock(&hw->lock);
4867         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4868             hw->adapter_state == HNS3_NIC_STOPPING) {
4869                 hns3_do_stop(hns);
4870                 hw->reset.mbuf_deferred_free = true;
4871         } else
4872                 hw->reset.mbuf_deferred_free = false;
4873
4874         /*
4875          * It is cumbersome for hardware to pick-and-choose entries for deletion
4876          * from table space. Hence, for function reset software intervention is
4877          * required to delete the entries
4878          */
4879         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4880                 hns3_configure_all_mc_mac_addr(hns, true);
4881         rte_spinlock_unlock(&hw->lock);
4882
4883         return 0;
4884 }
4885
4886 static int
4887 hns3_start_service(struct hns3_adapter *hns)
4888 {
4889         struct hns3_hw *hw = &hns->hw;
4890         struct rte_eth_dev *eth_dev;
4891
4892         if (hw->reset.level == HNS3_IMP_RESET ||
4893             hw->reset.level == HNS3_GLOBAL_RESET)
4894                 hns3_set_rst_done(hw);
4895         eth_dev = &rte_eth_devices[hw->data->port_id];
4896         hns3_set_rxtx_function(eth_dev);
4897         hns3_mp_req_start_rxtx(eth_dev);
4898         if (hw->adapter_state == HNS3_NIC_STARTED)
4899                 hns3_service_handler(eth_dev);
4900
4901         return 0;
4902 }
4903
4904 static int
4905 hns3_restore_conf(struct hns3_adapter *hns)
4906 {
4907         struct hns3_hw *hw = &hns->hw;
4908         int ret;
4909
4910         ret = hns3_configure_all_mac_addr(hns, false);
4911         if (ret)
4912                 return ret;
4913
4914         ret = hns3_configure_all_mc_mac_addr(hns, false);
4915         if (ret)
4916                 goto err_mc_mac;
4917
4918         ret = hns3_dev_promisc_restore(hns);
4919         if (ret)
4920                 goto err_promisc;
4921
4922         ret = hns3_restore_vlan_table(hns);
4923         if (ret)
4924                 goto err_promisc;
4925
4926         ret = hns3_restore_vlan_conf(hns);
4927         if (ret)
4928                 goto err_promisc;
4929
4930         ret = hns3_restore_all_fdir_filter(hns);
4931         if (ret)
4932                 goto err_promisc;
4933
4934         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4935                 ret = hns3_do_start(hns, false);
4936                 if (ret)
4937                         goto err_promisc;
4938                 hns3_info(hw, "hns3 dev restart successful!");
4939         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4940                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4941         return 0;
4942
4943 err_promisc:
4944         hns3_configure_all_mc_mac_addr(hns, true);
4945 err_mc_mac:
4946         hns3_configure_all_mac_addr(hns, true);
4947         return ret;
4948 }
4949
4950 static void
4951 hns3_reset_service(void *param)
4952 {
4953         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4954         struct hns3_hw *hw = &hns->hw;
4955         enum hns3_reset_level reset_level;
4956         struct timeval tv_delta;
4957         struct timeval tv_start;
4958         struct timeval tv;
4959         uint64_t msec;
4960         int ret;
4961
4962         /*
4963          * The interrupt is not triggered within the delay time.
4964          * The interrupt may have been lost. It is necessary to handle
4965          * the interrupt to recover from the error.
4966          */
4967         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4968                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4969                 hns3_err(hw, "Handling interrupts in delayed tasks");
4970                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4971                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4972                 if (reset_level == HNS3_NONE_RESET) {
4973                         hns3_err(hw, "No reset level is set, try IMP reset");
4974                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4975                 }
4976         }
4977         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4978
4979         /*
4980          * Check if there is any ongoing reset in the hardware. This status can
4981          * be checked from reset_pending. If there is then, we need to wait for
4982          * hardware to complete reset.
4983          *    a. If we are able to figure out in reasonable time that hardware
4984          *       has fully resetted then, we can proceed with driver, client
4985          *       reset.
4986          *    b. else, we can come back later to check this status so re-sched
4987          *       now.
4988          */
4989         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4990         if (reset_level != HNS3_NONE_RESET) {
4991                 gettimeofday(&tv_start, NULL);
4992                 ret = hns3_reset_process(hns, reset_level);
4993                 gettimeofday(&tv, NULL);
4994                 timersub(&tv, &tv_start, &tv_delta);
4995                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4996                        tv_delta.tv_usec / USEC_PER_MSEC;
4997                 if (msec > HNS3_RESET_PROCESS_MS)
4998                         hns3_err(hw, "%d handle long time delta %" PRIx64
4999                                      " ms time=%ld.%.6ld",
5000                                  hw->reset.level, msec,
5001                                  tv.tv_sec, tv.tv_usec);
5002                 if (ret == -EAGAIN)
5003                         return;
5004         }
5005
5006         /* Check if we got any *new* reset requests to be honored */
5007         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
5008         if (reset_level != HNS3_NONE_RESET)
5009                 hns3_msix_process(hns, reset_level);
5010 }
5011
5012 static const struct eth_dev_ops hns3_eth_dev_ops = {
5013         .dev_start          = hns3_dev_start,
5014         .dev_stop           = hns3_dev_stop,
5015         .dev_close          = hns3_dev_close,
5016         .promiscuous_enable = hns3_dev_promiscuous_enable,
5017         .promiscuous_disable = hns3_dev_promiscuous_disable,
5018         .allmulticast_enable  = hns3_dev_allmulticast_enable,
5019         .allmulticast_disable = hns3_dev_allmulticast_disable,
5020         .mtu_set            = hns3_dev_mtu_set,
5021         .stats_get          = hns3_stats_get,
5022         .stats_reset        = hns3_stats_reset,
5023         .xstats_get         = hns3_dev_xstats_get,
5024         .xstats_get_names   = hns3_dev_xstats_get_names,
5025         .xstats_reset       = hns3_dev_xstats_reset,
5026         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
5027         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
5028         .dev_infos_get          = hns3_dev_infos_get,
5029         .fw_version_get         = hns3_fw_version_get,
5030         .rx_queue_setup         = hns3_rx_queue_setup,
5031         .tx_queue_setup         = hns3_tx_queue_setup,
5032         .rx_queue_release       = hns3_dev_rx_queue_release,
5033         .tx_queue_release       = hns3_dev_tx_queue_release,
5034         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
5035         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
5036         .dev_configure          = hns3_dev_configure,
5037         .flow_ctrl_get          = hns3_flow_ctrl_get,
5038         .flow_ctrl_set          = hns3_flow_ctrl_set,
5039         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
5040         .mac_addr_add           = hns3_add_mac_addr,
5041         .mac_addr_remove        = hns3_remove_mac_addr,
5042         .mac_addr_set           = hns3_set_default_mac_addr,
5043         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
5044         .link_update            = hns3_dev_link_update,
5045         .rss_hash_update        = hns3_dev_rss_hash_update,
5046         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
5047         .reta_update            = hns3_dev_rss_reta_update,
5048         .reta_query             = hns3_dev_rss_reta_query,
5049         .filter_ctrl            = hns3_dev_filter_ctrl,
5050         .vlan_filter_set        = hns3_vlan_filter_set,
5051         .vlan_tpid_set          = hns3_vlan_tpid_set,
5052         .vlan_offload_set       = hns3_vlan_offload_set,
5053         .vlan_pvid_set          = hns3_vlan_pvid_set,
5054         .get_reg                = hns3_get_regs,
5055         .get_dcb_info           = hns3_get_dcb_info,
5056         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
5057 };
5058
5059 static const struct hns3_reset_ops hns3_reset_ops = {
5060         .reset_service       = hns3_reset_service,
5061         .stop_service        = hns3_stop_service,
5062         .prepare_reset       = hns3_prepare_reset,
5063         .wait_hardware_ready = hns3_wait_hardware_ready,
5064         .reinit_dev          = hns3_reinit_dev,
5065         .restore_conf        = hns3_restore_conf,
5066         .start_service       = hns3_start_service,
5067 };
5068
5069 static int
5070 hns3_dev_init(struct rte_eth_dev *eth_dev)
5071 {
5072         struct rte_device *dev = eth_dev->device;
5073         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
5074         struct hns3_adapter *hns = eth_dev->data->dev_private;
5075         struct hns3_hw *hw = &hns->hw;
5076         uint16_t device_id = pci_dev->id.device_id;
5077         int ret;
5078
5079         PMD_INIT_FUNC_TRACE();
5080         eth_dev->process_private = (struct hns3_process_private *)
5081             rte_zmalloc_socket("hns3_filter_list",
5082                                sizeof(struct hns3_process_private),
5083                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
5084         if (eth_dev->process_private == NULL) {
5085                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
5086                 return -ENOMEM;
5087         }
5088         /* initialize flow filter lists */
5089         hns3_filterlist_init(eth_dev);
5090
5091         hns3_set_rxtx_function(eth_dev);
5092         eth_dev->dev_ops = &hns3_eth_dev_ops;
5093         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
5094                 hns3_mp_init_secondary();
5095                 hw->secondary_cnt++;
5096                 return 0;
5097         }
5098
5099         hns3_mp_init_primary();
5100         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
5101
5102         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
5103             device_id == HNS3_DEV_ID_50GE_RDMA ||
5104             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
5105                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
5106
5107         hns->is_vf = false;
5108         hw->data = eth_dev->data;
5109
5110         /*
5111          * Set default max packet size according to the mtu
5112          * default vale in DPDK frame.
5113          */
5114         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
5115
5116         ret = hns3_reset_init(hw);
5117         if (ret)
5118                 goto err_init_reset;
5119         hw->reset.ops = &hns3_reset_ops;
5120
5121         ret = hns3_init_pf(eth_dev);
5122         if (ret) {
5123                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
5124                 goto err_init_pf;
5125         }
5126
5127         /* Allocate memory for storing MAC addresses */
5128         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
5129                                                sizeof(struct rte_ether_addr) *
5130                                                HNS3_UC_MACADDR_NUM, 0);
5131         if (eth_dev->data->mac_addrs == NULL) {
5132                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
5133                              "to store MAC addresses",
5134                              sizeof(struct rte_ether_addr) *
5135                              HNS3_UC_MACADDR_NUM);
5136                 ret = -ENOMEM;
5137                 goto err_rte_zmalloc;
5138         }
5139
5140         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
5141                             &eth_dev->data->mac_addrs[0]);
5142
5143         hw->adapter_state = HNS3_NIC_INITIALIZED;
5144         /*
5145          * Pass the information to the rte_eth_dev_close() that it should also
5146          * release the private port resources.
5147          */
5148         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5149
5150         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
5151                 hns3_err(hw, "Reschedule reset service after dev_init");
5152                 hns3_schedule_reset(hns);
5153         } else {
5154                 /* IMP will wait ready flag before reset */
5155                 hns3_notify_reset_ready(hw, false);
5156         }
5157
5158         hns3_info(hw, "hns3 dev initialization successful!");
5159         return 0;
5160
5161 err_rte_zmalloc:
5162         hns3_uninit_pf(eth_dev);
5163
5164 err_init_pf:
5165         rte_free(hw->reset.wait_data);
5166 err_init_reset:
5167         eth_dev->dev_ops = NULL;
5168         eth_dev->rx_pkt_burst = NULL;
5169         eth_dev->tx_pkt_burst = NULL;
5170         eth_dev->tx_pkt_prepare = NULL;
5171         rte_free(eth_dev->process_private);
5172         eth_dev->process_private = NULL;
5173         return ret;
5174 }
5175
5176 static int
5177 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
5178 {
5179         struct hns3_adapter *hns = eth_dev->data->dev_private;
5180         struct hns3_hw *hw = &hns->hw;
5181
5182         PMD_INIT_FUNC_TRACE();
5183
5184         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5185                 return -EPERM;
5186
5187         eth_dev->dev_ops = NULL;
5188         eth_dev->rx_pkt_burst = NULL;
5189         eth_dev->tx_pkt_burst = NULL;
5190         eth_dev->tx_pkt_prepare = NULL;
5191         if (hw->adapter_state < HNS3_NIC_CLOSING)
5192                 hns3_dev_close(eth_dev);
5193
5194         hw->adapter_state = HNS3_NIC_REMOVED;
5195         return 0;
5196 }
5197
5198 static int
5199 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5200                    struct rte_pci_device *pci_dev)
5201 {
5202         return rte_eth_dev_pci_generic_probe(pci_dev,
5203                                              sizeof(struct hns3_adapter),
5204                                              hns3_dev_init);
5205 }
5206
5207 static int
5208 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
5209 {
5210         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
5211 }
5212
5213 static const struct rte_pci_id pci_id_hns3_map[] = {
5214         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
5215         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
5216         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
5217         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
5218         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
5219         { .vendor_id = 0, /* sentinel */ },
5220 };
5221
5222 static struct rte_pci_driver rte_hns3_pmd = {
5223         .id_table = pci_id_hns3_map,
5224         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
5225         .probe = eth_hns3_pci_probe,
5226         .remove = eth_hns3_pci_remove,
5227 };
5228
5229 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
5230 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
5231 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
5232
5233 RTE_INIT(hns3_init_log)
5234 {
5235         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
5236         if (hns3_logtype_init >= 0)
5237                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
5238         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
5239         if (hns3_logtype_driver >= 0)
5240                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
5241 }