drivers/net/hns3/hns3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <stdio.h>
   9 #include <stdint.h>
  10 #include <inttypes.h>
  11 #include <unistd.h>
  12 #include <rte_atomic.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_common.h>
  15 #include <rte_cycles.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_io.h>
  23 #include <rte_log.h>
  24 #include <rte_pci.h>
  25
  26 #include "hns3_ethdev.h"
  27 #include "hns3_logs.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_intr.h"
  30 #include "hns3_regs.h"
  31 #include "hns3_dcb.h"
  32 #include "hns3_mp.h"
  33
  34 #define HNS3_DEFAULT_PORT_CONF_BURST_SIZE       32
  35 #define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM       1
  36
  37 #define HNS3_SERVICE_INTERVAL           1000000 /* us */
  38 #define HNS3_PORT_BASE_VLAN_DISABLE     0
  39 #define HNS3_PORT_BASE_VLAN_ENABLE      1
  40 #define HNS3_INVLID_PVID                0xFFFF
  41
  42 #define HNS3_FILTER_TYPE_VF             0
  43 #define HNS3_FILTER_TYPE_PORT           1
  44 #define HNS3_FILTER_FE_EGRESS_V1_B      BIT(0)
  45 #define HNS3_FILTER_FE_NIC_INGRESS_B    BIT(0)
  46 #define HNS3_FILTER_FE_NIC_EGRESS_B     BIT(1)
  47 #define HNS3_FILTER_FE_ROCE_INGRESS_B   BIT(2)
  48 #define HNS3_FILTER_FE_ROCE_EGRESS_B    BIT(3)
  49 #define HNS3_FILTER_FE_EGRESS           (HNS3_FILTER_FE_NIC_EGRESS_B \
  50                                         | HNS3_FILTER_FE_ROCE_EGRESS_B)
  51 #define HNS3_FILTER_FE_INGRESS          (HNS3_FILTER_FE_NIC_INGRESS_B \
  52                                         | HNS3_FILTER_FE_ROCE_INGRESS_B)
  53
  54 /* Reset related Registers */
  55 #define HNS3_GLOBAL_RESET_BIT           0
  56 #define HNS3_CORE_RESET_BIT             1
  57 #define HNS3_IMP_RESET_BIT              2
  58 #define HNS3_FUN_RST_ING_B              0
  59
  60 #define HNS3_VECTOR0_IMP_RESET_INT_B    1
  61
  62 #define HNS3_RESET_WAIT_MS      100
  63 #define HNS3_RESET_WAIT_CNT     200
  64
  65 int hns3_logtype_init;
  66 int hns3_logtype_driver;
  67
  68 enum hns3_evt_cause {
  69         HNS3_VECTOR0_EVENT_RST,
  70         HNS3_VECTOR0_EVENT_MBX,
  71         HNS3_VECTOR0_EVENT_ERR,
  72         HNS3_VECTOR0_EVENT_OTHER,
  73 };
  74
  75 static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
  76                                                  uint64_t *levels);
  77 static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  78 static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
  79                                     int on);
  80
  81 static void
  82 hns3_pf_disable_irq0(struct hns3_hw *hw)
  83 {
  84         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
  85 }
  86
  87 static void
  88 hns3_pf_enable_irq0(struct hns3_hw *hw)
  89 {
  90         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
  91 }
  92
  93 static enum hns3_evt_cause
  94 hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
  95 {
  96         struct hns3_hw *hw = &hns->hw;
  97         uint32_t vector0_int_stats;
  98         uint32_t cmdq_src_val;
  99         uint32_t val;
 100         enum hns3_evt_cause ret;
 101
 102         /* fetch the events from their corresponding regs */
 103         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 104         cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
 105
 106         /*
 107          * Assumption: If by any chance reset and mailbox events are reported
 108          * together then we will only process reset event and defer the
 109          * processing of the mailbox events. Since, we would have not cleared
 110          * RX CMDQ event this time we would receive again another interrupt
 111          * from H/W just for the mailbox.
 112          */
 113         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
 114                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 115                 hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
 116                 val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
 117                 if (clearval) {
 118                         hw->reset.stats.imp_cnt++;
 119                         hns3_warn(hw, "IMP reset detected, clear reset status");
 120                 } else {
 121                         hns3_schedule_delayed_reset(hns);
 122                         hns3_warn(hw, "IMP reset detected, don't clear reset status");
 123                 }
 124
 125                 ret = HNS3_VECTOR0_EVENT_RST;
 126                 goto out;
 127         }
 128
 129         /* Global reset */
 130         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
 131                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 132                 hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
 133                 val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
 134                 if (clearval) {
 135                         hw->reset.stats.global_cnt++;
 136                         hns3_warn(hw, "Global reset detected, clear reset status");
 137                 } else {
 138                         hns3_schedule_delayed_reset(hns);
 139                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 140                 }
 141
 142                 ret = HNS3_VECTOR0_EVENT_RST;
 143                 goto out;
 144         }
 145
 146         /* check for vector0 msix event source */
 147         if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK) {
 148                 val = vector0_int_stats;
 149                 ret = HNS3_VECTOR0_EVENT_ERR;
 150                 goto out;
 151         }
 152
 153         /* check for vector0 mailbox(=CMDQ RX) event source */
 154         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
 155                 cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 156                 val = cmdq_src_val;
 157                 ret = HNS3_VECTOR0_EVENT_MBX;
 158                 goto out;
 159         }
 160
 161         if (clearval && (vector0_int_stats || cmdq_src_val))
 162                 hns3_warn(hw, "surprise irq ector0_int_stats:0x%x cmdq_src_val:0x%x",
 163                           vector0_int_stats, cmdq_src_val);
 164         val = vector0_int_stats;
 165         ret = HNS3_VECTOR0_EVENT_OTHER;
 166 out:
 167
 168         if (clearval)
 169                 *clearval = val;
 170         return ret;
 171 }
 172
 173 static void
 174 hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
 175 {
 176         if (event_type == HNS3_VECTOR0_EVENT_RST)
 177                 hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
 178         else if (event_type == HNS3_VECTOR0_EVENT_MBX)
 179                 hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 180 }
 181
 182 static void
 183 hns3_clear_all_event_cause(struct hns3_hw *hw)
 184 {
 185         uint32_t vector0_int_stats;
 186         vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
 187
 188         if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
 189                 hns3_warn(hw, "Probe during IMP reset interrupt");
 190
 191         if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
 192                 hns3_warn(hw, "Probe during Global reset interrupt");
 193
 194         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
 195                                BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
 196                                BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
 197                                BIT(HNS3_VECTOR0_CORERESET_INT_B));
 198         hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
 199 }
 200
 201 static void
 202 hns3_interrupt_handler(void *param)
 203 {
 204         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 205         struct hns3_adapter *hns = dev->data->dev_private;
 206         struct hns3_hw *hw = &hns->hw;
 207         enum hns3_evt_cause event_cause;
 208         uint32_t clearval = 0;
 209
 210         /* Disable interrupt */
 211         hns3_pf_disable_irq0(hw);
 212
 213         event_cause = hns3_check_event_cause(hns, &clearval);
 214
 215         /* vector 0 interrupt is shared with reset and mailbox source events. */
 216         if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
 217                 hns3_handle_msix_error(hns, &hw->reset.request);
 218                 hns3_schedule_reset(hns);
 219         } else if (event_cause == HNS3_VECTOR0_EVENT_RST)
 220                 hns3_schedule_reset(hns);
 221         else
 222                 hns3_err(hw, "Received unknown event");
 223
 224         hns3_clear_event_cause(hw, event_cause, clearval);
 225         /* Enable interrupt if it is not cause by reset */
 226         hns3_pf_enable_irq0(hw);
 227 }
 228
 229 static int
 230 hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 231 {
 232 #define HNS3_VLAN_OFFSET_160            160
 233         struct hns3_vlan_filter_pf_cfg_cmd *req;
 234         struct hns3_hw *hw = &hns->hw;
 235         uint8_t vlan_offset_byte_val;
 236         struct hns3_cmd_desc desc;
 237         uint8_t vlan_offset_byte;
 238         uint8_t vlan_offset_160;
 239         int ret;
 240
 241         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
 242
 243         vlan_offset_160 = vlan_id / HNS3_VLAN_OFFSET_160;
 244         vlan_offset_byte = (vlan_id % HNS3_VLAN_OFFSET_160) / 8;
 245         vlan_offset_byte_val = 1 << (vlan_id % 8);
 246
 247         req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
 248         req->vlan_offset = vlan_offset_160;
 249         req->vlan_cfg = on ? 0 : 1;
 250         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
 251
 252         ret = hns3_cmd_send(hw, &desc, 1);
 253         if (ret)
 254                 hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
 255                          vlan_id, ret);
 256
 257         return ret;
 258 }
 259
 260 static void
 261 hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
 262 {
 263         struct hns3_user_vlan_table *vlan_entry;
 264         struct hns3_pf *pf = &hns->pf;
 265
 266         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 267                 if (vlan_entry->vlan_id == vlan_id) {
 268                         if (vlan_entry->hd_tbl_status)
 269                                 hns3_set_port_vlan_filter(hns, vlan_id, 0);
 270                         LIST_REMOVE(vlan_entry, next);
 271                         rte_free(vlan_entry);
 272                         break;
 273                 }
 274         }
 275 }
 276
 277 static void
 278 hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
 279                         bool writen_to_tbl)
 280 {
 281         struct hns3_user_vlan_table *vlan_entry;
 282         struct hns3_hw *hw = &hns->hw;
 283         struct hns3_pf *pf = &hns->pf;
 284
 285         vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
 286         if (vlan_entry == NULL) {
 287                 hns3_err(hw, "Failed to malloc hns3 vlan table");
 288                 return;
 289         }
 290
 291         vlan_entry->hd_tbl_status = writen_to_tbl;
 292         vlan_entry->vlan_id = vlan_id;
 293
 294         LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
 295 }
 296
 297 static int
 298 hns3_restore_vlan_table(struct hns3_adapter *hns)
 299 {
 300         struct hns3_user_vlan_table *vlan_entry;
 301         struct hns3_pf *pf = &hns->pf;
 302         uint16_t vlan_id;
 303         int ret = 0;
 304
 305         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE) {
 306                 ret = hns3_vlan_pvid_configure(hns, pf->port_base_vlan_cfg.pvid,
 307                                                1);
 308                 return ret;
 309         }
 310
 311         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 312                 if (vlan_entry->hd_tbl_status) {
 313                         vlan_id = vlan_entry->vlan_id;
 314                         ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
 315                         if (ret)
 316                                 break;
 317                 }
 318         }
 319
 320         return ret;
 321 }
 322
 323 static int
 324 hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 325 {
 326         struct hns3_pf *pf = &hns->pf;
 327         bool writen_to_tbl = false;
 328         int ret = 0;
 329
 330         /*
 331          * When vlan filter is enabled, hardware regards vlan id 0 as the entry
 332          * for normal packet, deleting vlan id 0 is not allowed.
 333          */
 334         if (on == 0 && vlan_id == 0)
 335                 return 0;
 336
 337         /*
 338          * When port base vlan enabled, we use port base vlan as the vlan
 339          * filter condition. In this case, we don't update vlan filter table
 340          * when user add new vlan or remove exist vlan, just update the
 341          * vlan list. The vlan id in vlan list will be writen in vlan filter
 342          * table until port base vlan disabled
 343          */
 344         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 345                 ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
 346                 writen_to_tbl = true;
 347         }
 348
 349         if (ret == 0 && vlan_id) {
 350                 if (on)
 351                         hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
 352                 else
 353                         hns3_rm_dev_vlan_table(hns, vlan_id);
 354         }
 355         return ret;
 356 }
 357
 358 static int
 359 hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 360 {
 361         struct hns3_adapter *hns = dev->data->dev_private;
 362         struct hns3_hw *hw = &hns->hw;
 363         int ret;
 364
 365         rte_spinlock_lock(&hw->lock);
 366         ret = hns3_vlan_filter_configure(hns, vlan_id, on);
 367         rte_spinlock_unlock(&hw->lock);
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
 373                          uint16_t tpid)
 374 {
 375         struct hns3_rx_vlan_type_cfg_cmd *rx_req;
 376         struct hns3_tx_vlan_type_cfg_cmd *tx_req;
 377         struct hns3_hw *hw = &hns->hw;
 378         struct hns3_cmd_desc desc;
 379         int ret;
 380
 381         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
 382              vlan_type != ETH_VLAN_TYPE_OUTER)) {
 383                 hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
 384                 return -EINVAL;
 385         }
 386
 387         if (tpid != RTE_ETHER_TYPE_VLAN) {
 388                 hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
 389                 return -EINVAL;
 390         }
 391
 392         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
 393         rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
 394
 395         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
 396                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 397                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 398         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
 399                 rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
 400                 rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
 401                 rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
 402                 rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
 403         }
 404
 405         ret = hns3_cmd_send(hw, &desc, 1);
 406         if (ret) {
 407                 hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
 408                          ret);
 409                 return ret;
 410         }
 411
 412         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
 413
 414         tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
 415         tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
 416         tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
 417
 418         ret = hns3_cmd_send(hw, &desc, 1);
 419         if (ret)
 420                 hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
 421                          ret);
 422         return ret;
 423 }
 424
 425 static int
 426 hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
 427                    uint16_t tpid)
 428 {
 429         struct hns3_adapter *hns = dev->data->dev_private;
 430         struct hns3_hw *hw = &hns->hw;
 431         int ret;
 432
 433         rte_spinlock_lock(&hw->lock);
 434         ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
 435         rte_spinlock_unlock(&hw->lock);
 436         return ret;
 437 }
 438
 439 static int
 440 hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
 441                              struct hns3_rx_vtag_cfg *vcfg)
 442 {
 443         struct hns3_vport_vtag_rx_cfg_cmd *req;
 444         struct hns3_hw *hw = &hns->hw;
 445         struct hns3_cmd_desc desc;
 446         uint16_t vport_id;
 447         uint8_t bitmap;
 448         int ret;
 449
 450         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
 451
 452         req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
 453         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
 454                      vcfg->strip_tag1_en ? 1 : 0);
 455         hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
 456                      vcfg->strip_tag2_en ? 1 : 0);
 457         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
 458                      vcfg->vlan1_vlan_prionly ? 1 : 0);
 459         hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
 460                      vcfg->vlan2_vlan_prionly ? 1 : 0);
 461
 462         /*
 463          * In current version VF is not supported when PF is driven by DPDK
 464          * driver, the PF-related vf_id is 0, just need to configure parameters
 465          * for vport_id 0.
 466          */
 467         vport_id = 0;
 468         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 469         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 470         req->vf_bitmap[req->vf_offset] = bitmap;
 471
 472         ret = hns3_cmd_send(hw, &desc, 1);
 473         if (ret)
 474                 hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
 475         return ret;
 476 }
 477
 478 static void
 479 hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
 480                            struct hns3_rx_vtag_cfg *vcfg)
 481 {
 482         struct hns3_pf *pf = &hns->pf;
 483         memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
 484 }
 485
 486 static void
 487 hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
 488                            struct hns3_tx_vtag_cfg *vcfg)
 489 {
 490         struct hns3_pf *pf = &hns->pf;
 491         memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
 492 }
 493
 494 static int
 495 hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
 496 {
 497         struct hns3_rx_vtag_cfg rxvlan_cfg;
 498         struct hns3_pf *pf = &hns->pf;
 499         struct hns3_hw *hw = &hns->hw;
 500         int ret;
 501
 502         if (pf->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
 503                 rxvlan_cfg.strip_tag1_en = false;
 504                 rxvlan_cfg.strip_tag2_en = enable;
 505         } else {
 506                 rxvlan_cfg.strip_tag1_en = enable;
 507                 rxvlan_cfg.strip_tag2_en = true;
 508         }
 509
 510         rxvlan_cfg.vlan1_vlan_prionly = false;
 511         rxvlan_cfg.vlan2_vlan_prionly = false;
 512         rxvlan_cfg.rx_vlan_offload_en = enable;
 513
 514         ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
 515         if (ret) {
 516                 hns3_err(hw, "enable strip rx vtag failed, ret =%d", ret);
 517                 return ret;
 518         }
 519
 520         hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
 521
 522         return ret;
 523 }
 524
 525 static int
 526 hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
 527                           uint8_t fe_type, bool filter_en, uint8_t vf_id)
 528 {
 529         struct hns3_vlan_filter_ctrl_cmd *req;
 530         struct hns3_cmd_desc desc;
 531         int ret;
 532
 533         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
 534
 535         req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
 536         req->vlan_type = vlan_type;
 537         req->vlan_fe = filter_en ? fe_type : 0;
 538         req->vf_id = vf_id;
 539
 540         ret = hns3_cmd_send(hw, &desc, 1);
 541         if (ret)
 542                 hns3_err(hw, "set vlan filter fail, ret =%d", ret);
 543
 544         return ret;
 545 }
 546
 547 static int
 548 hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
 549 {
 550         struct hns3_hw *hw = &hns->hw;
 551         int ret;
 552
 553         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
 554                                         HNS3_FILTER_FE_EGRESS, false, 0);
 555         if (ret) {
 556                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 557                 return ret;
 558         }
 559
 560         ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
 561                                         HNS3_FILTER_FE_INGRESS, enable, 0);
 562         if (ret)
 563                 hns3_err(hw, "hns3 enable filter fail, ret =%d", ret);
 564
 565         return ret;
 566 }
 567
 568 static int
 569 hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 570 {
 571         struct hns3_adapter *hns = dev->data->dev_private;
 572         struct hns3_hw *hw = &hns->hw;
 573         struct rte_eth_rxmode *rxmode;
 574         unsigned int tmp_mask;
 575         bool enable;
 576         int ret = 0;
 577
 578         rte_spinlock_lock(&hw->lock);
 579         rxmode = &dev->data->dev_conf.rxmode;
 580         tmp_mask = (unsigned int)mask;
 581         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 582                 /* Enable or disable VLAN stripping */
 583                 enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
 584                     true : false;
 585
 586                 ret = hns3_en_hw_strip_rxvtag(hns, enable);
 587                 if (ret) {
 588                         rte_spinlock_unlock(&hw->lock);
 589                         hns3_err(hw, "failed to enable rx strip, ret =%d", ret);
 590                         return ret;
 591                 }
 592         }
 593
 594         rte_spinlock_unlock(&hw->lock);
 595
 596         return ret;
 597 }
 598
 599 static int
 600 hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
 601                              struct hns3_tx_vtag_cfg *vcfg)
 602 {
 603         struct hns3_vport_vtag_tx_cfg_cmd *req;
 604         struct hns3_cmd_desc desc;
 605         struct hns3_hw *hw = &hns->hw;
 606         uint16_t vport_id;
 607         uint8_t bitmap;
 608         int ret;
 609
 610         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
 611
 612         req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
 613         req->def_vlan_tag1 = vcfg->default_tag1;
 614         req->def_vlan_tag2 = vcfg->default_tag2;
 615         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
 616                      vcfg->accept_tag1 ? 1 : 0);
 617         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
 618                      vcfg->accept_untag1 ? 1 : 0);
 619         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
 620                      vcfg->accept_tag2 ? 1 : 0);
 621         hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
 622                      vcfg->accept_untag2 ? 1 : 0);
 623         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
 624                      vcfg->insert_tag1_en ? 1 : 0);
 625         hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
 626                      vcfg->insert_tag2_en ? 1 : 0);
 627         hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
 628
 629         /*
 630          * In current version VF is not supported when PF is driven by DPDK
 631          * driver, the PF-related vf_id is 0, just need to configure parameters
 632          * for vport_id 0.
 633          */
 634         vport_id = 0;
 635         req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
 636         bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
 637         req->vf_bitmap[req->vf_offset] = bitmap;
 638
 639         ret = hns3_cmd_send(hw, &desc, 1);
 640         if (ret)
 641                 hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
 642
 643         return ret;
 644 }
 645
 646 static int
 647 hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
 648                      uint16_t pvid)
 649 {
 650         struct hns3_hw *hw = &hns->hw;
 651         struct hns3_tx_vtag_cfg txvlan_cfg;
 652         int ret;
 653
 654         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
 655                 txvlan_cfg.accept_tag1 = true;
 656                 txvlan_cfg.insert_tag1_en = false;
 657                 txvlan_cfg.default_tag1 = 0;
 658         } else {
 659                 txvlan_cfg.accept_tag1 = false;
 660                 txvlan_cfg.insert_tag1_en = true;
 661                 txvlan_cfg.default_tag1 = pvid;
 662         }
 663
 664         txvlan_cfg.accept_untag1 = true;
 665         txvlan_cfg.accept_tag2 = true;
 666         txvlan_cfg.accept_untag2 = true;
 667         txvlan_cfg.insert_tag2_en = false;
 668         txvlan_cfg.default_tag2 = 0;
 669
 670         ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
 671         if (ret) {
 672                 hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
 673                          ret);
 674                 return ret;
 675         }
 676
 677         hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
 678         return ret;
 679 }
 680
 681 static void
 682 hns3_store_port_base_vlan_info(struct hns3_adapter *hns, uint16_t pvid, int on)
 683 {
 684         struct hns3_pf *pf = &hns->pf;
 685
 686         pf->port_base_vlan_cfg.state = on ?
 687             HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
 688
 689         pf->port_base_vlan_cfg.pvid = pvid;
 690 }
 691
 692 static void
 693 hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
 694 {
 695         struct hns3_user_vlan_table *vlan_entry;
 696         struct hns3_pf *pf = &hns->pf;
 697
 698         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 699                 if (vlan_entry->hd_tbl_status)
 700                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
 701
 702                 vlan_entry->hd_tbl_status = false;
 703         }
 704
 705         if (is_del_list) {
 706                 vlan_entry = LIST_FIRST(&pf->vlan_list);
 707                 while (vlan_entry) {
 708                         LIST_REMOVE(vlan_entry, next);
 709                         rte_free(vlan_entry);
 710                         vlan_entry = LIST_FIRST(&pf->vlan_list);
 711                 }
 712         }
 713 }
 714
 715 static void
 716 hns3_add_all_vlan_table(struct hns3_adapter *hns)
 717 {
 718         struct hns3_user_vlan_table *vlan_entry;
 719         struct hns3_pf *pf = &hns->pf;
 720
 721         LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
 722                 if (!vlan_entry->hd_tbl_status)
 723                         hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
 724
 725                 vlan_entry->hd_tbl_status = true;
 726         }
 727 }
 728
 729 static void
 730 hns3_remove_all_vlan_table(struct hns3_adapter *hns)
 731 {
 732         struct hns3_hw *hw = &hns->hw;
 733         struct hns3_pf *pf = &hns->pf;
 734         int ret;
 735
 736         hns3_rm_all_vlan_table(hns, true);
 737         if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID) {
 738                 ret = hns3_set_port_vlan_filter(hns,
 739                                                 pf->port_base_vlan_cfg.pvid, 0);
 740                 if (ret) {
 741                         hns3_err(hw, "Failed to remove all vlan table, ret =%d",
 742                                  ret);
 743                         return;
 744                 }
 745         }
 746 }
 747
 748 static int
 749 hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
 750                                 uint16_t port_base_vlan_state,
 751                                 uint16_t new_pvid, uint16_t old_pvid)
 752 {
 753         struct hns3_pf *pf = &hns->pf;
 754         struct hns3_hw *hw = &hns->hw;
 755         int ret = 0;
 756
 757         if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
 758                 if (old_pvid != HNS3_INVLID_PVID && old_pvid != 0) {
 759                         ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
 760                         if (ret) {
 761                                 hns3_err(hw,
 762                                          "Failed to clear clear old pvid filter, ret =%d",
 763                                          ret);
 764                                 return ret;
 765                         }
 766                 }
 767
 768                 hns3_rm_all_vlan_table(hns, false);
 769                 return hns3_set_port_vlan_filter(hns, new_pvid, 1);
 770         }
 771
 772         if (new_pvid != 0) {
 773                 ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
 774                 if (ret) {
 775                         hns3_err(hw, "Failed to set port vlan filter, ret =%d",
 776                                  ret);
 777                         return ret;
 778                 }
 779         }
 780
 781         if (new_pvid == pf->port_base_vlan_cfg.pvid)
 782                 hns3_add_all_vlan_table(hns);
 783
 784         return ret;
 785 }
 786
 787 static int
 788 hns3_en_rx_strip_all(struct hns3_adapter *hns, int on)
 789 {
 790         struct hns3_rx_vtag_cfg rx_vlan_cfg;
 791         struct hns3_hw *hw = &hns->hw;
 792         bool rx_strip_en;
 793         int ret;
 794
 795         rx_strip_en = on ? true : false;
 796         rx_vlan_cfg.strip_tag1_en = rx_strip_en;
 797         rx_vlan_cfg.strip_tag2_en = rx_strip_en;
 798         rx_vlan_cfg.vlan1_vlan_prionly = false;
 799         rx_vlan_cfg.vlan2_vlan_prionly = false;
 800         rx_vlan_cfg.rx_vlan_offload_en = rx_strip_en;
 801
 802         ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
 803         if (ret) {
 804                 hns3_err(hw, "enable strip rx failed, ret =%d", ret);
 805                 return ret;
 806         }
 807
 808         hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
 809         return ret;
 810 }
 811
 812 static int
 813 hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
 814 {
 815         struct hns3_pf *pf = &hns->pf;
 816         struct hns3_hw *hw = &hns->hw;
 817         uint16_t port_base_vlan_state;
 818         uint16_t old_pvid;
 819         int ret;
 820
 821         if (on == 0 && pvid != pf->port_base_vlan_cfg.pvid) {
 822                 if (pf->port_base_vlan_cfg.pvid != HNS3_INVLID_PVID)
 823                         hns3_warn(hw, "Invalid operation! As current pvid set "
 824                                   "is %u, disable pvid %u is invalid",
 825                                   pf->port_base_vlan_cfg.pvid, pvid);
 826                 return 0;
 827         }
 828
 829         port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
 830                                     HNS3_PORT_BASE_VLAN_DISABLE;
 831         ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
 832         if (ret) {
 833                 hns3_err(hw, "Failed to config tx vlan, ret =%d", ret);
 834                 return ret;
 835         }
 836
 837         ret = hns3_en_rx_strip_all(hns, on);
 838         if (ret) {
 839                 hns3_err(hw, "Failed to config rx vlan strip, ret =%d", ret);
 840                 return ret;
 841         }
 842
 843         if (pvid == HNS3_INVLID_PVID)
 844                 goto out;
 845         old_pvid = pf->port_base_vlan_cfg.pvid;
 846         ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid,
 847                                               old_pvid);
 848         if (ret) {
 849                 hns3_err(hw, "Failed to update vlan filter entries, ret =%d",
 850                          ret);
 851                 return ret;
 852         }
 853
 854 out:
 855         hns3_store_port_base_vlan_info(hns, pvid, on);
 856         return ret;
 857 }
 858
 859 static int
 860 hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
 861 {
 862         struct hns3_adapter *hns = dev->data->dev_private;
 863         struct hns3_hw *hw = &hns->hw;
 864         int ret;
 865
 866         rte_spinlock_lock(&hw->lock);
 867         ret = hns3_vlan_pvid_configure(hns, pvid, on);
 868         rte_spinlock_unlock(&hw->lock);
 869         return ret;
 870 }
 871
 872 static void
 873 init_port_base_vlan_info(struct hns3_hw *hw)
 874 {
 875         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 876         struct hns3_pf *pf = &hns->pf;
 877
 878         pf->port_base_vlan_cfg.state = HNS3_PORT_BASE_VLAN_DISABLE;
 879         pf->port_base_vlan_cfg.pvid = HNS3_INVLID_PVID;
 880 }
 881
 882 static int
 883 hns3_default_vlan_config(struct hns3_adapter *hns)
 884 {
 885         struct hns3_hw *hw = &hns->hw;
 886         int ret;
 887
 888         ret = hns3_set_port_vlan_filter(hns, 0, 1);
 889         if (ret)
 890                 hns3_err(hw, "default vlan 0 config failed, ret =%d", ret);
 891         return ret;
 892 }
 893
 894 static int
 895 hns3_init_vlan_config(struct hns3_adapter *hns)
 896 {
 897         struct hns3_hw *hw = &hns->hw;
 898         int ret;
 899
 900         /*
 901          * This function can be called in the initialization and reset process,
 902          * when in reset process, it means that hardware had been reseted
 903          * successfully and we need to restore the hardware configuration to
 904          * ensure that the hardware configuration remains unchanged before and
 905          * after reset.
 906          */
 907         if (rte_atomic16_read(&hw->reset.resetting) == 0)
 908                 init_port_base_vlan_info(hw);
 909
 910         ret = hns3_enable_vlan_filter(hns, true);
 911         if (ret) {
 912                 hns3_err(hw, "vlan init fail in pf, ret =%d", ret);
 913                 return ret;
 914         }
 915
 916         ret = hns3_vlan_tpid_configure(hns, ETH_VLAN_TYPE_INNER,
 917                                        RTE_ETHER_TYPE_VLAN);
 918         if (ret) {
 919                 hns3_err(hw, "tpid set fail in pf, ret =%d", ret);
 920                 return ret;
 921         }
 922
 923         /*
 924          * When in the reinit dev stage of the reset process, the following
 925          * vlan-related configurations may differ from those at initialization,
 926          * we will restore configurations to hardware in hns3_restore_vlan_table
 927          * and hns3_restore_vlan_conf later.
 928          */
 929         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
 930                 ret = hns3_vlan_pvid_configure(hns, HNS3_INVLID_PVID, 0);
 931                 if (ret) {
 932                         hns3_err(hw, "pvid set fail in pf, ret =%d", ret);
 933                         return ret;
 934                 }
 935
 936                 ret = hns3_en_hw_strip_rxvtag(hns, false);
 937                 if (ret) {
 938                         hns3_err(hw, "rx strip configure fail in pf, ret =%d",
 939                                  ret);
 940                         return ret;
 941                 }
 942         }
 943
 944         return hns3_default_vlan_config(hns);
 945 }
 946
 947 static int
 948 hns3_restore_vlan_conf(struct hns3_adapter *hns)
 949 {
 950         struct hns3_pf *pf = &hns->pf;
 951         struct hns3_hw *hw = &hns->hw;
 952         int ret;
 953
 954         ret = hns3_set_vlan_rx_offload_cfg(hns, &pf->vtag_config.rx_vcfg);
 955         if (ret) {
 956                 hns3_err(hw, "hns3 restore vlan rx conf fail, ret =%d", ret);
 957                 return ret;
 958         }
 959
 960         ret = hns3_set_vlan_tx_offload_cfg(hns, &pf->vtag_config.tx_vcfg);
 961         if (ret)
 962                 hns3_err(hw, "hns3 restore vlan tx conf fail, ret =%d", ret);
 963
 964         return ret;
 965 }
 966
 967 static int
 968 hns3_dev_configure_vlan(struct rte_eth_dev *dev)
 969 {
 970         struct hns3_adapter *hns = dev->data->dev_private;
 971         struct rte_eth_dev_data *data = dev->data;
 972         struct rte_eth_txmode *txmode;
 973         struct hns3_hw *hw = &hns->hw;
 974         int ret;
 975
 976         txmode = &data->dev_conf.txmode;
 977         if (txmode->hw_vlan_reject_tagged || txmode->hw_vlan_reject_untagged)
 978                 hns3_warn(hw,
 979                           "hw_vlan_reject_tagged or hw_vlan_reject_untagged "
 980                           "configuration is not supported! Ignore these two "
 981                           "parameters: hw_vlan_reject_tagged(%d), "
 982                           "hw_vlan_reject_untagged(%d)",
 983                           txmode->hw_vlan_reject_tagged,
 984                           txmode->hw_vlan_reject_untagged);
 985
 986         /* Apply vlan offload setting */
 987         ret = hns3_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 988         if (ret) {
 989                 hns3_err(hw, "dev config vlan Strip failed, ret =%d", ret);
 990                 return ret;
 991         }
 992
 993         /* Apply pvid setting */
 994         ret = hns3_vlan_pvid_set(dev, txmode->pvid,
 995                                  txmode->hw_vlan_insert_pvid);
 996         if (ret)
 997                 hns3_err(hw, "dev config vlan pvid(%d) failed, ret =%d",
 998                          txmode->pvid, ret);
 999
1000         return ret;
1001 }
1002
1003 static int
1004 hns3_config_tso(struct hns3_hw *hw, unsigned int tso_mss_min,
1005                 unsigned int tso_mss_max)
1006 {
1007         struct hns3_cfg_tso_status_cmd *req;
1008         struct hns3_cmd_desc desc;
1009         uint16_t tso_mss;
1010
1011         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TSO_GENERIC_CONFIG, false);
1012
1013         req = (struct hns3_cfg_tso_status_cmd *)desc.data;
1014
1015         tso_mss = 0;
1016         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1017                        tso_mss_min);
1018         req->tso_mss_min = rte_cpu_to_le_16(tso_mss);
1019
1020         tso_mss = 0;
1021         hns3_set_field(tso_mss, HNS3_TSO_MSS_MIN_M, HNS3_TSO_MSS_MIN_S,
1022                        tso_mss_max);
1023         req->tso_mss_max = rte_cpu_to_le_16(tso_mss);
1024
1025         return hns3_cmd_send(hw, &desc, 1);
1026 }
1027
1028 int
1029 hns3_config_gro(struct hns3_hw *hw, bool en)
1030 {
1031         struct hns3_cfg_gro_status_cmd *req;
1032         struct hns3_cmd_desc desc;
1033         int ret;
1034
1035         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_GRO_GENERIC_CONFIG, false);
1036         req = (struct hns3_cfg_gro_status_cmd *)desc.data;
1037
1038         req->gro_en = rte_cpu_to_le_16(en ? 1 : 0);
1039
1040         ret = hns3_cmd_send(hw, &desc, 1);
1041         if (ret)
1042                 hns3_err(hw, "GRO hardware config cmd failed, ret = %d", ret);
1043
1044         return ret;
1045 }
1046
1047 static int
1048 hns3_set_umv_space(struct hns3_hw *hw, uint16_t space_size,
1049                    uint16_t *allocated_size, bool is_alloc)
1050 {
1051         struct hns3_umv_spc_alc_cmd *req;
1052         struct hns3_cmd_desc desc;
1053         int ret;
1054
1055         req = (struct hns3_umv_spc_alc_cmd *)desc.data;
1056         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ALLOCATE, false);
1057         hns3_set_bit(req->allocate, HNS3_UMV_SPC_ALC_B, is_alloc ? 0 : 1);
1058         req->space_size = rte_cpu_to_le_32(space_size);
1059
1060         ret = hns3_cmd_send(hw, &desc, 1);
1061         if (ret) {
1062                 PMD_INIT_LOG(ERR, "%s umv space failed for cmd_send, ret =%d",
1063                              is_alloc ? "allocate" : "free", ret);
1064                 return ret;
1065         }
1066
1067         if (is_alloc && allocated_size)
1068                 *allocated_size = rte_le_to_cpu_32(desc.data[1]);
1069
1070         return 0;
1071 }
1072
1073 static int
1074 hns3_init_umv_space(struct hns3_hw *hw)
1075 {
1076         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1077         struct hns3_pf *pf = &hns->pf;
1078         uint16_t allocated_size = 0;
1079         int ret;
1080
1081         ret = hns3_set_umv_space(hw, pf->wanted_umv_size, &allocated_size,
1082                                  true);
1083         if (ret)
1084                 return ret;
1085
1086         if (allocated_size < pf->wanted_umv_size)
1087                 PMD_INIT_LOG(WARNING, "Alloc umv space failed, want %u, get %u",
1088                              pf->wanted_umv_size, allocated_size);
1089
1090         pf->max_umv_size = (!!allocated_size) ? allocated_size :
1091                                                 pf->wanted_umv_size;
1092         pf->used_umv_size = 0;
1093         return 0;
1094 }
1095
1096 static int
1097 hns3_uninit_umv_space(struct hns3_hw *hw)
1098 {
1099         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1100         struct hns3_pf *pf = &hns->pf;
1101         int ret;
1102
1103         if (pf->max_umv_size == 0)
1104                 return 0;
1105
1106         ret = hns3_set_umv_space(hw, pf->max_umv_size, NULL, false);
1107         if (ret)
1108                 return ret;
1109
1110         pf->max_umv_size = 0;
1111
1112         return 0;
1113 }
1114
1115 static bool
1116 hns3_is_umv_space_full(struct hns3_hw *hw)
1117 {
1118         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1119         struct hns3_pf *pf = &hns->pf;
1120         bool is_full;
1121
1122         is_full = (pf->used_umv_size >= pf->max_umv_size);
1123
1124         return is_full;
1125 }
1126
1127 static void
1128 hns3_update_umv_space(struct hns3_hw *hw, bool is_free)
1129 {
1130         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1131         struct hns3_pf *pf = &hns->pf;
1132
1133         if (is_free) {
1134                 if (pf->used_umv_size > 0)
1135                         pf->used_umv_size--;
1136         } else
1137                 pf->used_umv_size++;
1138 }
1139
1140 static void
1141 hns3_prepare_mac_addr(struct hns3_mac_vlan_tbl_entry_cmd *new_req,
1142                       const uint8_t *addr, bool is_mc)
1143 {
1144         const unsigned char *mac_addr = addr;
1145         uint32_t high_val = ((uint32_t)mac_addr[3] << 24) |
1146                             ((uint32_t)mac_addr[2] << 16) |
1147                             ((uint32_t)mac_addr[1] << 8) |
1148                             (uint32_t)mac_addr[0];
1149         uint32_t low_val = ((uint32_t)mac_addr[5] << 8) | (uint32_t)mac_addr[4];
1150
1151         hns3_set_bit(new_req->flags, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1152         if (is_mc) {
1153                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1154                 hns3_set_bit(new_req->entry_type, HNS3_MAC_VLAN_BIT1_EN_B, 1);
1155                 hns3_set_bit(new_req->mc_mac_en, HNS3_MAC_VLAN_BIT0_EN_B, 1);
1156         }
1157
1158         new_req->mac_addr_hi32 = rte_cpu_to_le_32(high_val);
1159         new_req->mac_addr_lo16 = rte_cpu_to_le_16(low_val & 0xffff);
1160 }
1161
1162 static int
1163 hns3_get_mac_vlan_cmd_status(struct hns3_hw *hw, uint16_t cmdq_resp,
1164                              uint8_t resp_code,
1165                              enum hns3_mac_vlan_tbl_opcode op)
1166 {
1167         if (cmdq_resp) {
1168                 hns3_err(hw, "cmdq execute failed for get_mac_vlan_cmd_status,status=%u",
1169                          cmdq_resp);
1170                 return -EIO;
1171         }
1172
1173         if (op == HNS3_MAC_VLAN_ADD) {
1174                 if (resp_code == 0 || resp_code == 1) {
1175                         return 0;
1176                 } else if (resp_code == HNS3_ADD_UC_OVERFLOW) {
1177                         hns3_err(hw, "add mac addr failed for uc_overflow");
1178                         return -ENOSPC;
1179                 } else if (resp_code == HNS3_ADD_MC_OVERFLOW) {
1180                         hns3_err(hw, "add mac addr failed for mc_overflow");
1181                         return -ENOSPC;
1182                 }
1183
1184                 hns3_err(hw, "add mac addr failed for undefined, code=%u",
1185                          resp_code);
1186                 return -EIO;
1187         } else if (op == HNS3_MAC_VLAN_REMOVE) {
1188                 if (resp_code == 0) {
1189                         return 0;
1190                 } else if (resp_code == 1) {
1191                         hns3_dbg(hw, "remove mac addr failed for miss");
1192                         return -ENOENT;
1193                 }
1194
1195                 hns3_err(hw, "remove mac addr failed for undefined, code=%u",
1196                          resp_code);
1197                 return -EIO;
1198         } else if (op == HNS3_MAC_VLAN_LKUP) {
1199                 if (resp_code == 0) {
1200                         return 0;
1201                 } else if (resp_code == 1) {
1202                         hns3_dbg(hw, "lookup mac addr failed for miss");
1203                         return -ENOENT;
1204                 }
1205
1206                 hns3_err(hw, "lookup mac addr failed for undefined, code=%u",
1207                          resp_code);
1208                 return -EIO;
1209         }
1210
1211         hns3_err(hw, "unknown opcode for get_mac_vlan_cmd_status, opcode=%u",
1212                  op);
1213
1214         return -EINVAL;
1215 }
1216
1217 static int
1218 hns3_lookup_mac_vlan_tbl(struct hns3_hw *hw,
1219                          struct hns3_mac_vlan_tbl_entry_cmd *req,
1220                          struct hns3_cmd_desc *desc, bool is_mc)
1221 {
1222         uint8_t resp_code;
1223         uint16_t retval;
1224         int ret;
1225
1226         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_MAC_VLAN_ADD, true);
1227         if (is_mc) {
1228                 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1229                 memcpy(desc[0].data, req,
1230                            sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1231                 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_MAC_VLAN_ADD,
1232                                           true);
1233                 desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1234                 hns3_cmd_setup_basic_desc(&desc[2], HNS3_OPC_MAC_VLAN_ADD,
1235                                           true);
1236                 ret = hns3_cmd_send(hw, desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1237         } else {
1238                 memcpy(desc[0].data, req,
1239                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1240                 ret = hns3_cmd_send(hw, desc, 1);
1241         }
1242         if (ret) {
1243                 hns3_err(hw, "lookup mac addr failed for cmd_send, ret =%d.",
1244                          ret);
1245                 return ret;
1246         }
1247         resp_code = (rte_le_to_cpu_32(desc[0].data[0]) >> 8) & 0xff;
1248         retval = rte_le_to_cpu_16(desc[0].retval);
1249
1250         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1251                                             HNS3_MAC_VLAN_LKUP);
1252 }
1253
1254 static int
1255 hns3_add_mac_vlan_tbl(struct hns3_hw *hw,
1256                       struct hns3_mac_vlan_tbl_entry_cmd *req,
1257                       struct hns3_cmd_desc *mc_desc)
1258 {
1259         uint8_t resp_code;
1260         uint16_t retval;
1261         int cfg_status;
1262         int ret;
1263
1264         if (mc_desc == NULL) {
1265                 struct hns3_cmd_desc desc;
1266
1267                 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_ADD, false);
1268                 memcpy(desc.data, req,
1269                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1270                 ret = hns3_cmd_send(hw, &desc, 1);
1271                 resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1272                 retval = rte_le_to_cpu_16(desc.retval);
1273
1274                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1275                                                           HNS3_MAC_VLAN_ADD);
1276         } else {
1277                 hns3_cmd_reuse_desc(&mc_desc[0], false);
1278                 mc_desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1279                 hns3_cmd_reuse_desc(&mc_desc[1], false);
1280                 mc_desc[1].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1281                 hns3_cmd_reuse_desc(&mc_desc[2], false);
1282                 mc_desc[2].flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_NEXT);
1283                 memcpy(mc_desc[0].data, req,
1284                        sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1285                 mc_desc[0].retval = 0;
1286                 ret = hns3_cmd_send(hw, mc_desc, HNS3_MC_MAC_VLAN_ADD_DESC_NUM);
1287                 resp_code = (rte_le_to_cpu_32(mc_desc[0].data[0]) >> 8) & 0xff;
1288                 retval = rte_le_to_cpu_16(mc_desc[0].retval);
1289
1290                 cfg_status = hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1291                                                           HNS3_MAC_VLAN_ADD);
1292         }
1293
1294         if (ret) {
1295                 hns3_err(hw, "add mac addr failed for cmd_send, ret =%d", ret);
1296                 return ret;
1297         }
1298
1299         return cfg_status;
1300 }
1301
1302 static int
1303 hns3_remove_mac_vlan_tbl(struct hns3_hw *hw,
1304                          struct hns3_mac_vlan_tbl_entry_cmd *req)
1305 {
1306         struct hns3_cmd_desc desc;
1307         uint8_t resp_code;
1308         uint16_t retval;
1309         int ret;
1310
1311         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_REMOVE, false);
1312
1313         memcpy(desc.data, req, sizeof(struct hns3_mac_vlan_tbl_entry_cmd));
1314
1315         ret = hns3_cmd_send(hw, &desc, 1);
1316         if (ret) {
1317                 hns3_err(hw, "del mac addr failed for cmd_send, ret =%d", ret);
1318                 return ret;
1319         }
1320         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
1321         retval = rte_le_to_cpu_16(desc.retval);
1322
1323         return hns3_get_mac_vlan_cmd_status(hw, retval, resp_code,
1324                                             HNS3_MAC_VLAN_REMOVE);
1325 }
1326
1327 static int
1328 hns3_add_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1329 {
1330         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
1331         struct hns3_mac_vlan_tbl_entry_cmd req;
1332         struct hns3_pf *pf = &hns->pf;
1333         struct hns3_cmd_desc desc;
1334         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1335         uint16_t egress_port = 0;
1336         uint8_t vf_id;
1337         int ret;
1338
1339         /* check if mac addr is valid */
1340         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1341                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1342                                       mac_addr);
1343                 hns3_err(hw, "Add unicast mac addr err! addr(%s) invalid",
1344                          mac_str);
1345                 return -EINVAL;
1346         }
1347
1348         memset(&req, 0, sizeof(req));
1349
1350         /*
1351          * In current version VF is not supported when PF is driven by DPDK
1352          * driver, the PF-related vf_id is 0, just need to configure parameters
1353          * for vf_id 0.
1354          */
1355         vf_id = 0;
1356         hns3_set_field(egress_port, HNS3_MAC_EPORT_VFID_M,
1357                        HNS3_MAC_EPORT_VFID_S, vf_id);
1358
1359         req.egress_port = rte_cpu_to_le_16(egress_port);
1360
1361         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1362
1363         /*
1364          * Lookup the mac address in the mac_vlan table, and add
1365          * it if the entry is inexistent. Repeated unicast entry
1366          * is not allowed in the mac vlan table.
1367          */
1368         ret = hns3_lookup_mac_vlan_tbl(hw, &req, &desc, false);
1369         if (ret == -ENOENT) {
1370                 if (!hns3_is_umv_space_full(hw)) {
1371                         ret = hns3_add_mac_vlan_tbl(hw, &req, NULL);
1372                         if (!ret)
1373                                 hns3_update_umv_space(hw, false);
1374                         return ret;
1375                 }
1376
1377                 hns3_err(hw, "UC MAC table full(%u)", pf->used_umv_size);
1378
1379                 return -ENOSPC;
1380         }
1381
1382         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, mac_addr);
1383
1384         /* check if we just hit the duplicate */
1385         if (ret == 0) {
1386                 hns3_dbg(hw, "mac addr(%s) has been in the MAC table", mac_str);
1387                 return 0;
1388         }
1389
1390         hns3_err(hw, "PF failed to add unicast entry(%s) in the MAC table",
1391                  mac_str);
1392
1393         return ret;
1394 }
1395
1396 static int
1397 hns3_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1398                   uint32_t idx, __attribute__ ((unused)) uint32_t pool)
1399 {
1400         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1402         int ret;
1403
1404         rte_spinlock_lock(&hw->lock);
1405         ret = hns3_add_uc_addr_common(hw, mac_addr);
1406         if (ret) {
1407                 rte_spinlock_unlock(&hw->lock);
1408                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1409                                       mac_addr);
1410                 hns3_err(hw, "Failed to add mac addr(%s): %d", mac_str, ret);
1411                 return ret;
1412         }
1413
1414         if (idx == 0)
1415                 hw->mac.default_addr_setted = true;
1416         rte_spinlock_unlock(&hw->lock);
1417
1418         return ret;
1419 }
1420
1421 static int
1422 hns3_remove_uc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1423 {
1424         struct hns3_mac_vlan_tbl_entry_cmd req;
1425         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1426         int ret;
1427
1428         /* check if mac addr is valid */
1429         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1430                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1431                                       mac_addr);
1432                 hns3_err(hw, "Remove unicast mac addr err! addr(%s) invalid",
1433                          mac_str);
1434                 return -EINVAL;
1435         }
1436
1437         memset(&req, 0, sizeof(req));
1438         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1439         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, false);
1440         ret = hns3_remove_mac_vlan_tbl(hw, &req);
1441         if (ret == -ENOENT) /* mac addr isn't existent in the mac vlan table. */
1442                 return 0;
1443         else if (ret == 0)
1444                 hns3_update_umv_space(hw, true);
1445
1446         return ret;
1447 }
1448
1449 static void
1450 hns3_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
1451 {
1452         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1453         /* index will be checked by upper level rte interface */
1454         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
1455         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1456         int ret;
1457
1458         rte_spinlock_lock(&hw->lock);
1459         ret = hns3_remove_uc_addr_common(hw, mac_addr);
1460         if (ret) {
1461                 rte_spinlock_unlock(&hw->lock);
1462                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1463                                       mac_addr);
1464                 hns3_err(hw, "Failed to remove mac addr(%s): %d", mac_str, ret);
1465                 return;
1466         }
1467
1468         if (idx == 0)
1469                 hw->mac.default_addr_setted = false;
1470         rte_spinlock_unlock(&hw->lock);
1471 }
1472
1473 static int
1474 hns3_set_default_mac_addr(struct rte_eth_dev *dev,
1475                           struct rte_ether_addr *mac_addr)
1476 {
1477         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1478         struct rte_ether_addr *oaddr;
1479         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1480         bool default_addr_setted;
1481         bool rm_succes = false;
1482         int ret, ret_val;
1483
1484         /* check if mac addr is valid */
1485         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
1486                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1487                                       mac_addr);
1488                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid",
1489                          mac_str);
1490                 return -EINVAL;
1491         }
1492
1493         oaddr = (struct rte_ether_addr *)hw->mac.mac_addr;
1494         default_addr_setted = hw->mac.default_addr_setted;
1495         if (default_addr_setted && !!rte_is_same_ether_addr(mac_addr, oaddr))
1496                 return 0;
1497
1498         rte_spinlock_lock(&hw->lock);
1499         if (default_addr_setted) {
1500                 ret = hns3_remove_uc_addr_common(hw, oaddr);
1501                 if (ret) {
1502                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1503                                               oaddr);
1504                         hns3_warn(hw, "Remove old uc mac address(%s) fail: %d",
1505                                   mac_str, ret);
1506                         rm_succes = false;
1507                 } else
1508                         rm_succes = true;
1509         }
1510
1511         ret = hns3_add_uc_addr_common(hw, mac_addr);
1512         if (ret) {
1513                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1514                                       mac_addr);
1515                 hns3_err(hw, "Failed to set mac addr(%s): %d", mac_str, ret);
1516                 goto err_add_uc_addr;
1517         }
1518
1519         ret = hns3_pause_addr_cfg(hw, mac_addr->addr_bytes);
1520         if (ret) {
1521                 hns3_err(hw, "Failed to configure mac pause address: %d", ret);
1522                 goto err_pause_addr_cfg;
1523         }
1524
1525         rte_ether_addr_copy(mac_addr,
1526                             (struct rte_ether_addr *)hw->mac.mac_addr);
1527         hw->mac.default_addr_setted = true;
1528         rte_spinlock_unlock(&hw->lock);
1529
1530         return 0;
1531
1532 err_pause_addr_cfg:
1533         ret_val = hns3_remove_uc_addr_common(hw, mac_addr);
1534         if (ret_val) {
1535                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1536                                       mac_addr);
1537                 hns3_warn(hw,
1538                           "Failed to roll back to del setted mac addr(%s): %d",
1539                           mac_str, ret_val);
1540         }
1541
1542 err_add_uc_addr:
1543         if (rm_succes) {
1544                 ret_val = hns3_add_uc_addr_common(hw, oaddr);
1545                 if (ret_val) {
1546                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1547                                               oaddr);
1548                         hns3_warn(hw,
1549                                   "Failed to restore old uc mac addr(%s): %d",
1550                                   mac_str, ret_val);
1551                         hw->mac.default_addr_setted = false;
1552                 }
1553         }
1554         rte_spinlock_unlock(&hw->lock);
1555
1556         return ret;
1557 }
1558
1559 static int
1560 hns3_configure_all_mac_addr(struct hns3_adapter *hns, bool del)
1561 {
1562         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1563         struct hns3_hw *hw = &hns->hw;
1564         struct rte_ether_addr *addr;
1565         int err = 0;
1566         int ret;
1567         int i;
1568
1569         for (i = 0; i < HNS3_UC_MACADDR_NUM; i++) {
1570                 addr = &hw->data->mac_addrs[i];
1571                 if (!rte_is_valid_assigned_ether_addr(addr))
1572                         continue;
1573                 if (del)
1574                         ret = hns3_remove_uc_addr_common(hw, addr);
1575                 else
1576                         ret = hns3_add_uc_addr_common(hw, addr);
1577                 if (ret) {
1578                         err = ret;
1579                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1580                                               addr);
1581                         hns3_dbg(hw,
1582                                  "Failed to %s mac addr(%s). ret:%d i:%d",
1583                                  del ? "remove" : "restore", mac_str, ret, i);
1584                 }
1585         }
1586         return err;
1587 }
1588
1589 static void
1590 hns3_update_desc_vfid(struct hns3_cmd_desc *desc, uint8_t vfid, bool clr)
1591 {
1592 #define HNS3_VF_NUM_IN_FIRST_DESC 192
1593         uint8_t word_num;
1594         uint8_t bit_num;
1595
1596         if (vfid < HNS3_VF_NUM_IN_FIRST_DESC) {
1597                 word_num = vfid / 32;
1598                 bit_num = vfid % 32;
1599                 if (clr)
1600                         desc[1].data[word_num] &=
1601                             rte_cpu_to_le_32(~(1UL << bit_num));
1602                 else
1603                         desc[1].data[word_num] |=
1604                             rte_cpu_to_le_32(1UL << bit_num);
1605         } else {
1606                 word_num = (vfid - HNS3_VF_NUM_IN_FIRST_DESC) / 32;
1607                 bit_num = vfid % 32;
1608                 if (clr)
1609                         desc[2].data[word_num] &=
1610                             rte_cpu_to_le_32(~(1UL << bit_num));
1611                 else
1612                         desc[2].data[word_num] |=
1613                             rte_cpu_to_le_32(1UL << bit_num);
1614         }
1615 }
1616
1617 static int
1618 hns3_add_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1619 {
1620         struct hns3_mac_vlan_tbl_entry_cmd req;
1621         struct hns3_cmd_desc desc[3];
1622         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1623         uint8_t vf_id;
1624         int ret;
1625
1626         /* Check if mac addr is valid */
1627         if (!rte_is_multicast_ether_addr(mac_addr)) {
1628                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1629                                       mac_addr);
1630                 hns3_err(hw, "Failed to add mc mac addr, addr(%s) invalid",
1631                          mac_str);
1632                 return -EINVAL;
1633         }
1634
1635         memset(&req, 0, sizeof(req));
1636         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1637         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1638         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1639         if (ret) {
1640                 /* This mac addr do not exist, add new entry for it */
1641                 memset(desc[0].data, 0, sizeof(desc[0].data));
1642                 memset(desc[1].data, 0, sizeof(desc[0].data));
1643                 memset(desc[2].data, 0, sizeof(desc[0].data));
1644         }
1645
1646         /*
1647          * In current version VF is not supported when PF is driven by DPDK
1648          * driver, the PF-related vf_id is 0, just need to configure parameters
1649          * for vf_id 0.
1650          */
1651         vf_id = 0;
1652         hns3_update_desc_vfid(desc, vf_id, false);
1653         ret = hns3_add_mac_vlan_tbl(hw, &req, desc);
1654         if (ret) {
1655                 if (ret == -ENOSPC)
1656                         hns3_err(hw, "mc mac vlan table is full");
1657                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1658                                       mac_addr);
1659                 hns3_err(hw, "Failed to add mc mac addr(%s): %d", mac_str, ret);
1660         }
1661
1662         return ret;
1663 }
1664
1665 static int
1666 hns3_remove_mc_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
1667 {
1668         struct hns3_mac_vlan_tbl_entry_cmd req;
1669         struct hns3_cmd_desc desc[3];
1670         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1671         uint8_t vf_id;
1672         int ret;
1673
1674         /* Check if mac addr is valid */
1675         if (!rte_is_multicast_ether_addr(mac_addr)) {
1676                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1677                                       mac_addr);
1678                 hns3_err(hw, "Failed to rm mc mac addr, addr(%s) invalid",
1679                          mac_str);
1680                 return -EINVAL;
1681         }
1682
1683         memset(&req, 0, sizeof(req));
1684         hns3_set_bit(req.entry_type, HNS3_MAC_VLAN_BIT0_EN_B, 0);
1685         hns3_prepare_mac_addr(&req, mac_addr->addr_bytes, true);
1686         ret = hns3_lookup_mac_vlan_tbl(hw, &req, desc, true);
1687         if (ret == 0) {
1688                 /*
1689                  * This mac addr exist, remove this handle's VFID for it.
1690                  * In current version VF is not supported when PF is driven by
1691                  * DPDK driver, the PF-related vf_id is 0, just need to
1692                  * configure parameters for vf_id 0.
1693                  */
1694                 vf_id = 0;
1695                 hns3_update_desc_vfid(desc, vf_id, true);
1696
1697                 /* All the vfid is zero, so need to delete this entry */
1698                 ret = hns3_remove_mac_vlan_tbl(hw, &req);
1699         } else if (ret == -ENOENT) {
1700                 /* This mac addr doesn't exist. */
1701                 return 0;
1702         }
1703
1704         if (ret) {
1705                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1706                                       mac_addr);
1707                 hns3_err(hw, "Failed to rm mc mac addr(%s): %d", mac_str, ret);
1708         }
1709
1710         return ret;
1711 }
1712
1713 static int
1714 hns3_set_mc_addr_chk_param(struct hns3_hw *hw,
1715                            struct rte_ether_addr *mc_addr_set,
1716                            uint32_t nb_mc_addr)
1717 {
1718         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1719         struct rte_ether_addr *addr;
1720         uint32_t i;
1721         uint32_t j;
1722
1723         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
1724                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
1725                          "invalid. valid range: 0~%d",
1726                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
1727                 return -EINVAL;
1728         }
1729
1730         /* Check if input mac addresses are valid */
1731         for (i = 0; i < nb_mc_addr; i++) {
1732                 addr = &mc_addr_set[i];
1733                 if (!rte_is_multicast_ether_addr(addr)) {
1734                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1735                                               addr);
1736                         hns3_err(hw,
1737                                  "Failed to set mc mac addr, addr(%s) invalid.",
1738                                  mac_str);
1739                         return -EINVAL;
1740                 }
1741
1742                 /* Check if there are duplicate addresses */
1743                 for (j = i + 1; j < nb_mc_addr; j++) {
1744                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1745                                 rte_ether_format_addr(mac_str,
1746                                                       RTE_ETHER_ADDR_FMT_SIZE,
1747                                                       addr);
1748                                 hns3_err(hw, "Failed to set mc mac addr, "
1749                                          "addrs invalid. two same addrs(%s).",
1750                                          mac_str);
1751                                 return -EINVAL;
1752                         }
1753                 }
1754         }
1755
1756         return 0;
1757 }
1758
1759 static void
1760 hns3_set_mc_addr_calc_addr(struct hns3_hw *hw,
1761                            struct rte_ether_addr *mc_addr_set,
1762                            int mc_addr_num,
1763                            struct rte_ether_addr *reserved_addr_list,
1764                            int *reserved_addr_num,
1765                            struct rte_ether_addr *add_addr_list,
1766                            int *add_addr_num,
1767                            struct rte_ether_addr *rm_addr_list,
1768                            int *rm_addr_num)
1769 {
1770         struct rte_ether_addr *addr;
1771         int current_addr_num;
1772         int reserved_num = 0;
1773         int add_num = 0;
1774         int rm_num = 0;
1775         int num;
1776         int i;
1777         int j;
1778         bool same_addr;
1779
1780         /* Calculate the mc mac address list that should be removed */
1781         current_addr_num = hw->mc_addrs_num;
1782         for (i = 0; i < current_addr_num; i++) {
1783                 addr = &hw->mc_addrs[i];
1784                 same_addr = false;
1785                 for (j = 0; j < mc_addr_num; j++) {
1786                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
1787                                 same_addr = true;
1788                                 break;
1789                         }
1790                 }
1791
1792                 if (!same_addr) {
1793                         rte_ether_addr_copy(addr, &rm_addr_list[rm_num]);
1794                         rm_num++;
1795                 } else {
1796                         rte_ether_addr_copy(addr,
1797                                             &reserved_addr_list[reserved_num]);
1798                         reserved_num++;
1799                 }
1800         }
1801
1802         /* Calculate the mc mac address list that should be added */
1803         for (i = 0; i < mc_addr_num; i++) {
1804                 addr = &mc_addr_set[i];
1805                 same_addr = false;
1806                 for (j = 0; j < current_addr_num; j++) {
1807                         if (rte_is_same_ether_addr(addr, &hw->mc_addrs[j])) {
1808                                 same_addr = true;
1809                                 break;
1810                         }
1811                 }
1812
1813                 if (!same_addr) {
1814                         rte_ether_addr_copy(addr, &add_addr_list[add_num]);
1815                         add_num++;
1816                 }
1817         }
1818
1819         /* Reorder the mc mac address list maintained by driver */
1820         for (i = 0; i < reserved_num; i++)
1821                 rte_ether_addr_copy(&reserved_addr_list[i], &hw->mc_addrs[i]);
1822
1823         for (i = 0; i < rm_num; i++) {
1824                 num = reserved_num + i;
1825                 rte_ether_addr_copy(&rm_addr_list[i], &hw->mc_addrs[num]);
1826         }
1827
1828         *reserved_addr_num = reserved_num;
1829         *add_addr_num = add_num;
1830         *rm_addr_num = rm_num;
1831 }
1832
1833 static int
1834 hns3_set_mc_mac_addr_list(struct rte_eth_dev *dev,
1835                           struct rte_ether_addr *mc_addr_set,
1836                           uint32_t nb_mc_addr)
1837 {
1838         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1839         struct rte_ether_addr reserved_addr_list[HNS3_MC_MACADDR_NUM];
1840         struct rte_ether_addr add_addr_list[HNS3_MC_MACADDR_NUM];
1841         struct rte_ether_addr rm_addr_list[HNS3_MC_MACADDR_NUM];
1842         struct rte_ether_addr *addr;
1843         int reserved_addr_num;
1844         int add_addr_num;
1845         int rm_addr_num;
1846         int mc_addr_num;
1847         int num;
1848         int ret;
1849         int i;
1850
1851         /* Check if input parameters are valid */
1852         ret = hns3_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
1853         if (ret)
1854                 return ret;
1855
1856         rte_spinlock_lock(&hw->lock);
1857
1858         /*
1859          * Calculate the mc mac address lists those should be removed and be
1860          * added, Reorder the mc mac address list maintained by driver.
1861          */
1862         mc_addr_num = (int)nb_mc_addr;
1863         hns3_set_mc_addr_calc_addr(hw, mc_addr_set, mc_addr_num,
1864                                    reserved_addr_list, &reserved_addr_num,
1865                                    add_addr_list, &add_addr_num,
1866                                    rm_addr_list, &rm_addr_num);
1867
1868         /* Remove mc mac addresses */
1869         for (i = 0; i < rm_addr_num; i++) {
1870                 num = rm_addr_num - i - 1;
1871                 addr = &rm_addr_list[num];
1872                 ret = hns3_remove_mc_addr(hw, addr);
1873                 if (ret) {
1874                         rte_spinlock_unlock(&hw->lock);
1875                         return ret;
1876                 }
1877                 hw->mc_addrs_num--;
1878         }
1879
1880         /* Add mc mac addresses */
1881         for (i = 0; i < add_addr_num; i++) {
1882                 addr = &add_addr_list[i];
1883                 ret = hns3_add_mc_addr(hw, addr);
1884                 if (ret) {
1885                         rte_spinlock_unlock(&hw->lock);
1886                         return ret;
1887                 }
1888
1889                 num = reserved_addr_num + i;
1890                 rte_ether_addr_copy(addr, &hw->mc_addrs[num]);
1891                 hw->mc_addrs_num++;
1892         }
1893         rte_spinlock_unlock(&hw->lock);
1894
1895         return 0;
1896 }
1897
1898 static int
1899 hns3_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
1900 {
1901         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1902         struct hns3_hw *hw = &hns->hw;
1903         struct rte_ether_addr *addr;
1904         int err = 0;
1905         int ret;
1906         int i;
1907
1908         for (i = 0; i < hw->mc_addrs_num; i++) {
1909                 addr = &hw->mc_addrs[i];
1910                 if (!rte_is_multicast_ether_addr(addr))
1911                         continue;
1912                 if (del)
1913                         ret = hns3_remove_mc_addr(hw, addr);
1914                 else
1915                         ret = hns3_add_mc_addr(hw, addr);
1916                 if (ret) {
1917                         err = ret;
1918                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1919                                               addr);
1920                         hns3_dbg(hw, "%s mc mac addr: %s failed",
1921                                  del ? "Remove" : "Restore", mac_str);
1922                 }
1923         }
1924         return err;
1925 }
1926
1927 static int
1928 hns3_check_mq_mode(struct rte_eth_dev *dev)
1929 {
1930         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1931         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
1932         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1934         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
1935         struct rte_eth_dcb_tx_conf *dcb_tx_conf;
1936         uint8_t num_tc;
1937         int max_tc = 0;
1938         int i;
1939
1940         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
1941         dcb_tx_conf = &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
1942
1943         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1944                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB_RSS is not supported. "
1945                          "rx_mq_mode = %d", rx_mq_mode);
1946                 return -EINVAL;
1947         }
1948
1949         if (rx_mq_mode == ETH_MQ_RX_VMDQ_DCB ||
1950             tx_mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1951                 hns3_err(hw, "ETH_MQ_RX_VMDQ_DCB and ETH_MQ_TX_VMDQ_DCB "
1952                          "is not supported. rx_mq_mode = %d, tx_mq_mode = %d",
1953                          rx_mq_mode, tx_mq_mode);
1954                 return -EINVAL;
1955         }
1956
1957         if (rx_mq_mode == ETH_MQ_RX_DCB_RSS) {
1958                 if (dcb_rx_conf->nb_tcs > pf->tc_max) {
1959                         hns3_err(hw, "nb_tcs(%u) > max_tc(%u) driver supported.",
1960                                  dcb_rx_conf->nb_tcs, pf->tc_max);
1961                         return -EINVAL;
1962                 }
1963
1964                 if (!(dcb_rx_conf->nb_tcs == HNS3_4_TCS ||
1965                       dcb_rx_conf->nb_tcs == HNS3_8_TCS)) {
1966                         hns3_err(hw, "on ETH_MQ_RX_DCB_RSS mode, "
1967                                  "nb_tcs(%d) != %d or %d in rx direction.",
1968                                  dcb_rx_conf->nb_tcs, HNS3_4_TCS, HNS3_8_TCS);
1969                         return -EINVAL;
1970                 }
1971
1972                 if (dcb_rx_conf->nb_tcs != dcb_tx_conf->nb_tcs) {
1973                         hns3_err(hw, "num_tcs(%d) of tx is not equal to rx(%d)",
1974                                  dcb_tx_conf->nb_tcs, dcb_rx_conf->nb_tcs);
1975                         return -EINVAL;
1976                 }
1977
1978                 for (i = 0; i < HNS3_MAX_USER_PRIO; i++) {
1979                         if (dcb_rx_conf->dcb_tc[i] != dcb_tx_conf->dcb_tc[i]) {
1980                                 hns3_err(hw, "dcb_tc[%d] = %d in rx direction, "
1981                                          "is not equal to one in tx direction.",
1982                                          i, dcb_rx_conf->dcb_tc[i]);
1983                                 return -EINVAL;
1984                         }
1985                         if (dcb_rx_conf->dcb_tc[i] > max_tc)
1986                                 max_tc = dcb_rx_conf->dcb_tc[i];
1987                 }
1988
1989                 num_tc = max_tc + 1;
1990                 if (num_tc > dcb_rx_conf->nb_tcs) {
1991                         hns3_err(hw, "max num_tc(%u) mapped > nb_tcs(%u)",
1992                                  num_tc, dcb_rx_conf->nb_tcs);
1993                         return -EINVAL;
1994                 }
1995         }
1996
1997         return 0;
1998 }
1999
2000 static int
2001 hns3_check_dcb_cfg(struct rte_eth_dev *dev)
2002 {
2003         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004
2005         if (!hns3_dev_dcb_supported(hw)) {
2006                 hns3_err(hw, "this port does not support dcb configurations.");
2007                 return -EOPNOTSUPP;
2008         }
2009
2010         if (hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE) {
2011                 hns3_err(hw, "MAC pause enabled, cannot config dcb info.");
2012                 return -EOPNOTSUPP;
2013         }
2014
2015         /* Check multiple queue mode */
2016         return hns3_check_mq_mode(dev);
2017 }
2018
2019 static int
2020 hns3_dev_configure(struct rte_eth_dev *dev)
2021 {
2022         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
2024         struct rte_eth_conf *conf = &dev->data->dev_conf;
2025         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
2026         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2027         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2028         struct rte_eth_rss_conf rss_conf;
2029         uint16_t mtu;
2030         int ret;
2031
2032         /*
2033          * Hardware does not support where the number of rx and tx queues is
2034          * not equal in hip08.
2035          */
2036         if (nb_rx_q != nb_tx_q) {
2037                 hns3_err(hw,
2038                          "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! "
2039                          "Hardware does not support this configuration!",
2040                          nb_rx_q, nb_tx_q);
2041                 return -EINVAL;
2042         }
2043
2044         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
2045                 hns3_err(hw, "setting link speed/duplex not supported");
2046                 return -EINVAL;
2047         }
2048
2049         hw->adapter_state = HNS3_NIC_CONFIGURING;
2050         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG) {
2051                 ret = hns3_check_dcb_cfg(dev);
2052                 if (ret)
2053                         goto cfg_err;
2054         }
2055
2056         /* When RSS is not configured, redirect the packet queue 0 */
2057         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
2058                 rss_conf = conf->rx_adv_conf.rss_conf;
2059                 if (rss_conf.rss_key == NULL) {
2060                         rss_conf.rss_key = rss_cfg->key;
2061                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
2062                 }
2063
2064                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
2065                 if (ret)
2066                         goto cfg_err;
2067         }
2068
2069         /*
2070          * If jumbo frames are enabled, MTU needs to be refreshed
2071          * according to the maximum RX packet length.
2072          */
2073         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2074                 /*
2075                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
2076                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
2077                  * can safely assign to "uint16_t" type variable.
2078                  */
2079                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
2080                 ret = hns3_dev_mtu_set(dev, mtu);
2081                 if (ret)
2082                         goto cfg_err;
2083                 dev->data->mtu = mtu;
2084         }
2085
2086         ret = hns3_dev_configure_vlan(dev);
2087         if (ret)
2088                 goto cfg_err;
2089
2090         hw->adapter_state = HNS3_NIC_CONFIGURED;
2091
2092         return 0;
2093
2094 cfg_err:
2095         hw->adapter_state = HNS3_NIC_INITIALIZED;
2096         return ret;
2097 }
2098
2099 static int
2100 hns3_set_mac_mtu(struct hns3_hw *hw, uint16_t new_mps)
2101 {
2102         struct hns3_config_max_frm_size_cmd *req;
2103         struct hns3_cmd_desc desc;
2104
2105         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAX_FRM_SIZE, false);
2106
2107         req = (struct hns3_config_max_frm_size_cmd *)desc.data;
2108         req->max_frm_size = rte_cpu_to_le_16(new_mps);
2109         req->min_frm_size = HNS3_MIN_FRAME_LEN;
2110
2111         return hns3_cmd_send(hw, &desc, 1);
2112 }
2113
2114 static int
2115 hns3_config_mtu(struct hns3_hw *hw, uint16_t mps)
2116 {
2117         int ret;
2118
2119         ret = hns3_set_mac_mtu(hw, mps);
2120         if (ret) {
2121                 hns3_err(hw, "Failed to set mtu, ret = %d", ret);
2122                 return ret;
2123         }
2124
2125         ret = hns3_buffer_alloc(hw);
2126         if (ret) {
2127                 hns3_err(hw, "Failed to allocate buffer, ret = %d", ret);
2128                 return ret;
2129         }
2130
2131         return 0;
2132 }
2133
2134 static int
2135 hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2136 {
2137         struct hns3_adapter *hns = dev->data->dev_private;
2138         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
2139         struct hns3_hw *hw = &hns->hw;
2140         bool is_jumbo_frame;
2141         int ret;
2142
2143         if (dev->data->dev_started) {
2144                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
2145                          "before configuration", dev->data->port_id);
2146                 return -EBUSY;
2147         }
2148
2149         rte_spinlock_lock(&hw->lock);
2150         is_jumbo_frame = frame_size > RTE_ETHER_MAX_LEN ? true : false;
2151         frame_size = RTE_MAX(frame_size, HNS3_DEFAULT_FRAME_LEN);
2152
2153         /*
2154          * Maximum value of frame_size is HNS3_MAX_FRAME_LEN, so it can safely
2155          * assign to "uint16_t" type variable.
2156          */
2157         ret = hns3_config_mtu(hw, (uint16_t)frame_size);
2158         if (ret) {
2159                 rte_spinlock_unlock(&hw->lock);
2160                 hns3_err(hw, "Failed to set mtu, port %u mtu %u: %d",
2161                          dev->data->port_id, mtu, ret);
2162                 return ret;
2163         }
2164         hns->pf.mps = (uint16_t)frame_size;
2165         if (is_jumbo_frame)
2166                 dev->data->dev_conf.rxmode.offloads |=
2167                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
2168         else
2169                 dev->data->dev_conf.rxmode.offloads &=
2170                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2171         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2172         rte_spinlock_unlock(&hw->lock);
2173
2174         return 0;
2175 }
2176
2177 static int
2178 hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
2179 {
2180         struct hns3_adapter *hns = eth_dev->data->dev_private;
2181         struct hns3_hw *hw = &hns->hw;
2182
2183         info->max_rx_queues = hw->tqps_num;
2184         info->max_tx_queues = hw->tqps_num;
2185         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
2186         info->min_rx_bufsize = hw->rx_buf_len;
2187         info->max_mac_addrs = HNS3_UC_MACADDR_NUM;
2188         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
2189         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
2190                                  DEV_RX_OFFLOAD_TCP_CKSUM |
2191                                  DEV_RX_OFFLOAD_UDP_CKSUM |
2192                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
2193                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2194                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
2195                                  DEV_RX_OFFLOAD_KEEP_CRC |
2196                                  DEV_RX_OFFLOAD_SCATTER |
2197                                  DEV_RX_OFFLOAD_VLAN_STRIP |
2198                                  DEV_RX_OFFLOAD_QINQ_STRIP |
2199                                  DEV_RX_OFFLOAD_VLAN_FILTER |
2200                                  DEV_RX_OFFLOAD_VLAN_EXTEND |
2201                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
2202         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2203         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2204                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
2205                                  DEV_TX_OFFLOAD_TCP_CKSUM |
2206                                  DEV_TX_OFFLOAD_UDP_CKSUM |
2207                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
2208                                  DEV_TX_OFFLOAD_VLAN_INSERT |
2209                                  DEV_TX_OFFLOAD_QINQ_INSERT |
2210                                  DEV_TX_OFFLOAD_MULTI_SEGS |
2211                                  info->tx_queue_offload_capa);
2212
2213         info->rx_desc_lim = (struct rte_eth_desc_lim) {
2214                 .nb_max = HNS3_MAX_RING_DESC,
2215                 .nb_min = HNS3_MIN_RING_DESC,
2216                 .nb_align = HNS3_ALIGN_RING_DESC,
2217         };
2218
2219         info->tx_desc_lim = (struct rte_eth_desc_lim) {
2220                 .nb_max = HNS3_MAX_RING_DESC,
2221                 .nb_min = HNS3_MIN_RING_DESC,
2222                 .nb_align = HNS3_ALIGN_RING_DESC,
2223         };
2224
2225         info->vmdq_queue_num = 0;
2226
2227         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
2228         info->hash_key_size = HNS3_RSS_KEY_SIZE;
2229         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
2230
2231         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2232         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
2233         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2234         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
2235         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2236         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
2237
2238         return 0;
2239 }
2240
2241 static int
2242 hns3_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2243                     size_t fw_size)
2244 {
2245         struct hns3_adapter *hns = eth_dev->data->dev_private;
2246         struct hns3_hw *hw = &hns->hw;
2247         int ret;
2248
2249         ret = snprintf(fw_version, fw_size, "0x%08x", hw->fw_version);
2250         ret += 1; /* add the size of '\0' */
2251         if (fw_size < (uint32_t)ret)
2252                 return ret;
2253         else
2254                 return 0;
2255 }
2256
2257 static int
2258 hns3_dev_link_update(struct rte_eth_dev *eth_dev,
2259                      __rte_unused int wait_to_complete)
2260 {
2261         struct hns3_adapter *hns = eth_dev->data->dev_private;
2262         struct hns3_hw *hw = &hns->hw;
2263         struct hns3_mac *mac = &hw->mac;
2264         struct rte_eth_link new_link;
2265
2266         memset(&new_link, 0, sizeof(new_link));
2267         switch (mac->link_speed) {
2268         case ETH_SPEED_NUM_10M:
2269         case ETH_SPEED_NUM_100M:
2270         case ETH_SPEED_NUM_1G:
2271         case ETH_SPEED_NUM_10G:
2272         case ETH_SPEED_NUM_25G:
2273         case ETH_SPEED_NUM_40G:
2274         case ETH_SPEED_NUM_50G:
2275         case ETH_SPEED_NUM_100G:
2276                 new_link.link_speed = mac->link_speed;
2277                 break;
2278         default:
2279                 new_link.link_speed = ETH_SPEED_NUM_100M;
2280                 break;
2281         }
2282
2283         new_link.link_duplex = mac->link_duplex;
2284         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2285         new_link.link_autoneg =
2286             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2287
2288         return rte_eth_linkstatus_set(eth_dev, &new_link);
2289 }
2290
2291 static int
2292 hns3_parse_func_status(struct hns3_hw *hw, struct hns3_func_status_cmd *status)
2293 {
2294         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2295         struct hns3_pf *pf = &hns->pf;
2296
2297         if (!(status->pf_state & HNS3_PF_STATE_DONE))
2298                 return -EINVAL;
2299
2300         pf->is_main_pf = (status->pf_state & HNS3_PF_STATE_MAIN) ? true : false;
2301
2302         return 0;
2303 }
2304
2305 static int
2306 hns3_query_function_status(struct hns3_hw *hw)
2307 {
2308 #define HNS3_QUERY_MAX_CNT              10
2309 #define HNS3_QUERY_SLEEP_MSCOEND        1
2310         struct hns3_func_status_cmd *req;
2311         struct hns3_cmd_desc desc;
2312         int timeout = 0;
2313         int ret;
2314
2315         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FUNC_STATUS, true);
2316         req = (struct hns3_func_status_cmd *)desc.data;
2317
2318         do {
2319                 ret = hns3_cmd_send(hw, &desc, 1);
2320                 if (ret) {
2321                         PMD_INIT_LOG(ERR, "query function status failed %d",
2322                                      ret);
2323                         return ret;
2324                 }
2325
2326                 /* Check pf reset is done */
2327                 if (req->pf_state)
2328                         break;
2329
2330                 rte_delay_ms(HNS3_QUERY_SLEEP_MSCOEND);
2331         } while (timeout++ < HNS3_QUERY_MAX_CNT);
2332
2333         return hns3_parse_func_status(hw, req);
2334 }
2335
2336 static int
2337 hns3_query_pf_resource(struct hns3_hw *hw)
2338 {
2339         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2340         struct hns3_pf *pf = &hns->pf;
2341         struct hns3_pf_res_cmd *req;
2342         struct hns3_cmd_desc desc;
2343         int ret;
2344
2345         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_PF_RSRC, true);
2346         ret = hns3_cmd_send(hw, &desc, 1);
2347         if (ret) {
2348                 PMD_INIT_LOG(ERR, "query pf resource failed %d", ret);
2349                 return ret;
2350         }
2351
2352         req = (struct hns3_pf_res_cmd *)desc.data;
2353         hw->total_tqps_num = rte_le_to_cpu_16(req->tqp_num);
2354         pf->pkt_buf_size = rte_le_to_cpu_16(req->buf_size) << HNS3_BUF_UNIT_S;
2355         hw->tqps_num = RTE_MIN(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2356
2357         if (req->tx_buf_size)
2358                 pf->tx_buf_size =
2359                     rte_le_to_cpu_16(req->tx_buf_size) << HNS3_BUF_UNIT_S;
2360         else
2361                 pf->tx_buf_size = HNS3_DEFAULT_TX_BUF;
2362
2363         pf->tx_buf_size = roundup(pf->tx_buf_size, HNS3_BUF_SIZE_UNIT);
2364
2365         if (req->dv_buf_size)
2366                 pf->dv_buf_size =
2367                     rte_le_to_cpu_16(req->dv_buf_size) << HNS3_BUF_UNIT_S;
2368         else
2369                 pf->dv_buf_size = HNS3_DEFAULT_DV;
2370
2371         pf->dv_buf_size = roundup(pf->dv_buf_size, HNS3_BUF_SIZE_UNIT);
2372
2373         hw->num_msi =
2374             hns3_get_field(rte_le_to_cpu_16(req->pf_intr_vector_number),
2375                            HNS3_PF_VEC_NUM_M, HNS3_PF_VEC_NUM_S);
2376
2377         return 0;
2378 }
2379
2380 static void
2381 hns3_parse_cfg(struct hns3_cfg *cfg, struct hns3_cmd_desc *desc)
2382 {
2383         struct hns3_cfg_param_cmd *req;
2384         uint64_t mac_addr_tmp_high;
2385         uint64_t mac_addr_tmp;
2386         uint32_t i;
2387
2388         req = (struct hns3_cfg_param_cmd *)desc[0].data;
2389
2390         /* get the configuration */
2391         cfg->vmdq_vport_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2392                                              HNS3_CFG_VMDQ_M, HNS3_CFG_VMDQ_S);
2393         cfg->tc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2394                                      HNS3_CFG_TC_NUM_M, HNS3_CFG_TC_NUM_S);
2395         cfg->tqp_desc_num = hns3_get_field(rte_le_to_cpu_32(req->param[0]),
2396                                            HNS3_CFG_TQP_DESC_N_M,
2397                                            HNS3_CFG_TQP_DESC_N_S);
2398
2399         cfg->phy_addr = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2400                                        HNS3_CFG_PHY_ADDR_M,
2401                                        HNS3_CFG_PHY_ADDR_S);
2402         cfg->media_type = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2403                                          HNS3_CFG_MEDIA_TP_M,
2404                                          HNS3_CFG_MEDIA_TP_S);
2405         cfg->rx_buf_len = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2406                                          HNS3_CFG_RX_BUF_LEN_M,
2407                                          HNS3_CFG_RX_BUF_LEN_S);
2408         /* get mac address */
2409         mac_addr_tmp = rte_le_to_cpu_32(req->param[2]);
2410         mac_addr_tmp_high = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2411                                            HNS3_CFG_MAC_ADDR_H_M,
2412                                            HNS3_CFG_MAC_ADDR_H_S);
2413
2414         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
2415
2416         cfg->default_speed = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2417                                             HNS3_CFG_DEFAULT_SPEED_M,
2418                                             HNS3_CFG_DEFAULT_SPEED_S);
2419         cfg->rss_size_max = hns3_get_field(rte_le_to_cpu_32(req->param[3]),
2420                                            HNS3_CFG_RSS_SIZE_M,
2421                                            HNS3_CFG_RSS_SIZE_S);
2422
2423         for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2424                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
2425
2426         req = (struct hns3_cfg_param_cmd *)desc[1].data;
2427         cfg->numa_node_map = rte_le_to_cpu_32(req->param[0]);
2428
2429         cfg->speed_ability = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2430                                             HNS3_CFG_SPEED_ABILITY_M,
2431                                             HNS3_CFG_SPEED_ABILITY_S);
2432         cfg->umv_space = hns3_get_field(rte_le_to_cpu_32(req->param[1]),
2433                                         HNS3_CFG_UMV_TBL_SPACE_M,
2434                                         HNS3_CFG_UMV_TBL_SPACE_S);
2435         if (!cfg->umv_space)
2436                 cfg->umv_space = HNS3_DEFAULT_UMV_SPACE_PER_PF;
2437 }
2438
2439 /* hns3_get_board_cfg: query the static parameter from NCL_config file in flash
2440  * @hw: pointer to struct hns3_hw
2441  * @hcfg: the config structure to be getted
2442  */
2443 static int
2444 hns3_get_board_cfg(struct hns3_hw *hw, struct hns3_cfg *hcfg)
2445 {
2446         struct hns3_cmd_desc desc[HNS3_PF_CFG_DESC_NUM];
2447         struct hns3_cfg_param_cmd *req;
2448         uint32_t offset;
2449         uint32_t i;
2450         int ret;
2451
2452         for (i = 0; i < HNS3_PF_CFG_DESC_NUM; i++) {
2453                 offset = 0;
2454                 req = (struct hns3_cfg_param_cmd *)desc[i].data;
2455                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_GET_CFG_PARAM,
2456                                           true);
2457                 hns3_set_field(offset, HNS3_CFG_OFFSET_M, HNS3_CFG_OFFSET_S,
2458                                i * HNS3_CFG_RD_LEN_BYTES);
2459                 /* Len should be divided by 4 when send to hardware */
2460                 hns3_set_field(offset, HNS3_CFG_RD_LEN_M, HNS3_CFG_RD_LEN_S,
2461                                HNS3_CFG_RD_LEN_BYTES / HNS3_CFG_RD_LEN_UNIT);
2462                 req->offset = rte_cpu_to_le_32(offset);
2463         }
2464
2465         ret = hns3_cmd_send(hw, desc, HNS3_PF_CFG_DESC_NUM);
2466         if (ret) {
2467                 PMD_INIT_LOG(ERR, "get config failed %d.", ret);
2468                 return ret;
2469         }
2470
2471         hns3_parse_cfg(hcfg, desc);
2472
2473         return 0;
2474 }
2475
2476 static int
2477 hns3_parse_speed(int speed_cmd, uint32_t *speed)
2478 {
2479         switch (speed_cmd) {
2480         case HNS3_CFG_SPEED_10M:
2481                 *speed = ETH_SPEED_NUM_10M;
2482                 break;
2483         case HNS3_CFG_SPEED_100M:
2484                 *speed = ETH_SPEED_NUM_100M;
2485                 break;
2486         case HNS3_CFG_SPEED_1G:
2487                 *speed = ETH_SPEED_NUM_1G;
2488                 break;
2489         case HNS3_CFG_SPEED_10G:
2490                 *speed = ETH_SPEED_NUM_10G;
2491                 break;
2492         case HNS3_CFG_SPEED_25G:
2493                 *speed = ETH_SPEED_NUM_25G;
2494                 break;
2495         case HNS3_CFG_SPEED_40G:
2496                 *speed = ETH_SPEED_NUM_40G;
2497                 break;
2498         case HNS3_CFG_SPEED_50G:
2499                 *speed = ETH_SPEED_NUM_50G;
2500                 break;
2501         case HNS3_CFG_SPEED_100G:
2502                 *speed = ETH_SPEED_NUM_100G;
2503                 break;
2504         default:
2505                 return -EINVAL;
2506         }
2507
2508         return 0;
2509 }
2510
2511 static int
2512 hns3_get_board_configuration(struct hns3_hw *hw)
2513 {
2514         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2515         struct hns3_pf *pf = &hns->pf;
2516         struct hns3_cfg cfg;
2517         int ret;
2518
2519         ret = hns3_get_board_cfg(hw, &cfg);
2520         if (ret) {
2521                 PMD_INIT_LOG(ERR, "get board config failed %d", ret);
2522                 return ret;
2523         }
2524
2525         if (cfg.media_type == HNS3_MEDIA_TYPE_COPPER) {
2526                 PMD_INIT_LOG(ERR, "media type is copper, not supported.");
2527                 return -EOPNOTSUPP;
2528         }
2529
2530         hw->mac.media_type = cfg.media_type;
2531         hw->rss_size_max = cfg.rss_size_max;
2532         hw->rx_buf_len = cfg.rx_buf_len;
2533         memcpy(hw->mac.mac_addr, cfg.mac_addr, RTE_ETHER_ADDR_LEN);
2534         hw->mac.phy_addr = cfg.phy_addr;
2535         hw->mac.default_addr_setted = false;
2536         hw->num_tx_desc = cfg.tqp_desc_num;
2537         hw->num_rx_desc = cfg.tqp_desc_num;
2538         hw->dcb_info.num_pg = 1;
2539         hw->dcb_info.hw_pfc_map = 0;
2540
2541         ret = hns3_parse_speed(cfg.default_speed, &hw->mac.link_speed);
2542         if (ret) {
2543                 PMD_INIT_LOG(ERR, "Get wrong speed %d, ret = %d",
2544                              cfg.default_speed, ret);
2545                 return ret;
2546         }
2547
2548         pf->tc_max = cfg.tc_num;
2549         if (pf->tc_max > HNS3_MAX_TC_NUM || pf->tc_max < 1) {
2550                 PMD_INIT_LOG(WARNING,
2551                              "Get TC num(%u) from flash, set TC num to 1",
2552                              pf->tc_max);
2553                 pf->tc_max = 1;
2554         }
2555
2556         /* Dev does not support DCB */
2557         if (!hns3_dev_dcb_supported(hw)) {
2558                 pf->tc_max = 1;
2559                 pf->pfc_max = 0;
2560         } else
2561                 pf->pfc_max = pf->tc_max;
2562
2563         hw->dcb_info.num_tc = 1;
2564         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max,
2565                                      hw->tqps_num / hw->dcb_info.num_tc);
2566         hns3_set_bit(hw->hw_tc_map, 0, 1);
2567         pf->tx_sch_mode = HNS3_FLAG_TC_BASE_SCH_MODE;
2568
2569         pf->wanted_umv_size = cfg.umv_space;
2570
2571         return ret;
2572 }
2573
2574 static int
2575 hns3_get_configuration(struct hns3_hw *hw)
2576 {
2577         int ret;
2578
2579         ret = hns3_query_function_status(hw);
2580         if (ret) {
2581                 PMD_INIT_LOG(ERR, "Failed to query function status: %d.", ret);
2582                 return ret;
2583         }
2584
2585         /* Get pf resource */
2586         ret = hns3_query_pf_resource(hw);
2587         if (ret) {
2588                 PMD_INIT_LOG(ERR, "Failed to query pf resource: %d", ret);
2589                 return ret;
2590         }
2591
2592         ret = hns3_get_board_configuration(hw);
2593         if (ret) {
2594                 PMD_INIT_LOG(ERR, "Failed to get board configuration: %d", ret);
2595                 return ret;
2596         }
2597
2598         return 0;
2599 }
2600
2601 static int
2602 hns3_map_tqps_to_func(struct hns3_hw *hw, uint16_t func_id, uint16_t tqp_pid,
2603                       uint16_t tqp_vid, bool is_pf)
2604 {
2605         struct hns3_tqp_map_cmd *req;
2606         struct hns3_cmd_desc desc;
2607         int ret;
2608
2609         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SET_TQP_MAP, false);
2610
2611         req = (struct hns3_tqp_map_cmd *)desc.data;
2612         req->tqp_id = rte_cpu_to_le_16(tqp_pid);
2613         req->tqp_vf = func_id;
2614         req->tqp_flag = 1 << HNS3_TQP_MAP_EN_B;
2615         if (!is_pf)
2616                 req->tqp_flag |= (1 << HNS3_TQP_MAP_TYPE_B);
2617         req->tqp_vid = rte_cpu_to_le_16(tqp_vid);
2618
2619         ret = hns3_cmd_send(hw, &desc, 1);
2620         if (ret)
2621                 PMD_INIT_LOG(ERR, "TQP map failed %d", ret);
2622
2623         return ret;
2624 }
2625
2626 static int
2627 hns3_map_tqp(struct hns3_hw *hw)
2628 {
2629         uint16_t tqps_num = hw->total_tqps_num;
2630         uint16_t func_id;
2631         uint16_t tqp_id;
2632         int num;
2633         int ret;
2634         int i;
2635
2636         /*
2637          * In current version VF is not supported when PF is driven by DPDK
2638          * driver, so we allocate tqps to PF as much as possible.
2639          */
2640         tqp_id = 0;
2641         num = DIV_ROUND_UP(hw->total_tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
2642         for (func_id = 0; func_id < num; func_id++) {
2643                 for (i = 0;
2644                      i < HNS3_MAX_TQP_NUM_PER_FUNC && tqp_id < tqps_num; i++) {
2645                         ret = hns3_map_tqps_to_func(hw, func_id, tqp_id++, i,
2646                                                     true);
2647                         if (ret)
2648                                 return ret;
2649                 }
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int
2656 hns3_cfg_mac_speed_dup_hw(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
2657 {
2658         struct hns3_config_mac_speed_dup_cmd *req;
2659         struct hns3_cmd_desc desc;
2660         int ret;
2661
2662         req = (struct hns3_config_mac_speed_dup_cmd *)desc.data;
2663
2664         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_SPEED_DUP, false);
2665
2666         hns3_set_bit(req->speed_dup, HNS3_CFG_DUPLEX_B, !!duplex ? 1 : 0);
2667
2668         switch (speed) {
2669         case ETH_SPEED_NUM_10M:
2670                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2671                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10M);
2672                 break;
2673         case ETH_SPEED_NUM_100M:
2674                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2675                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100M);
2676                 break;
2677         case ETH_SPEED_NUM_1G:
2678                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2679                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_1G);
2680                 break;
2681         case ETH_SPEED_NUM_10G:
2682                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2683                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_10G);
2684                 break;
2685         case ETH_SPEED_NUM_25G:
2686                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2687                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_25G);
2688                 break;
2689         case ETH_SPEED_NUM_40G:
2690                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2691                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_40G);
2692                 break;
2693         case ETH_SPEED_NUM_50G:
2694                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2695                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_50G);
2696                 break;
2697         case ETH_SPEED_NUM_100G:
2698                 hns3_set_field(req->speed_dup, HNS3_CFG_SPEED_M,
2699                                HNS3_CFG_SPEED_S, HNS3_CFG_SPEED_100G);
2700                 break;
2701         default:
2702                 PMD_INIT_LOG(ERR, "invalid speed (%u)", speed);
2703                 return -EINVAL;
2704         }
2705
2706         hns3_set_bit(req->mac_change_fec_en, HNS3_CFG_MAC_SPEED_CHANGE_EN_B, 1);
2707
2708         ret = hns3_cmd_send(hw, &desc, 1);
2709         if (ret)
2710                 PMD_INIT_LOG(ERR, "mac speed/duplex config cmd failed %d", ret);
2711
2712         return ret;
2713 }
2714
2715 static int
2716 hns3_tx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2717 {
2718         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2719         struct hns3_pf *pf = &hns->pf;
2720         struct hns3_priv_buf *priv;
2721         uint32_t i, total_size;
2722
2723         total_size = pf->pkt_buf_size;
2724
2725         /* alloc tx buffer for all enabled tc */
2726         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2727                 priv = &buf_alloc->priv_buf[i];
2728
2729                 if (hw->hw_tc_map & BIT(i)) {
2730                         if (total_size < pf->tx_buf_size)
2731                                 return -ENOMEM;
2732
2733                         priv->tx_buf_size = pf->tx_buf_size;
2734                 } else
2735                         priv->tx_buf_size = 0;
2736
2737                 total_size -= priv->tx_buf_size;
2738         }
2739
2740         return 0;
2741 }
2742
2743 static int
2744 hns3_tx_buffer_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2745 {
2746 /* TX buffer size is unit by 128 byte */
2747 #define HNS3_BUF_SIZE_UNIT_SHIFT        7
2748 #define HNS3_BUF_SIZE_UPDATE_EN_MSK     BIT(15)
2749         struct hns3_tx_buff_alloc_cmd *req;
2750         struct hns3_cmd_desc desc;
2751         uint32_t buf_size;
2752         uint32_t i;
2753         int ret;
2754
2755         req = (struct hns3_tx_buff_alloc_cmd *)desc.data;
2756
2757         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TX_BUFF_ALLOC, 0);
2758         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2759                 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
2760
2761                 buf_size = buf_size >> HNS3_BUF_SIZE_UNIT_SHIFT;
2762                 req->tx_pkt_buff[i] = rte_cpu_to_le_16(buf_size |
2763                                                 HNS3_BUF_SIZE_UPDATE_EN_MSK);
2764         }
2765
2766         ret = hns3_cmd_send(hw, &desc, 1);
2767         if (ret)
2768                 PMD_INIT_LOG(ERR, "tx buffer alloc cmd failed %d", ret);
2769
2770         return ret;
2771 }
2772
2773 static int
2774 hns3_get_tc_num(struct hns3_hw *hw)
2775 {
2776         int cnt = 0;
2777         uint8_t i;
2778
2779         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2780                 if (hw->hw_tc_map & BIT(i))
2781                         cnt++;
2782         return cnt;
2783 }
2784
2785 static uint32_t
2786 hns3_get_rx_priv_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2787 {
2788         struct hns3_priv_buf *priv;
2789         uint32_t rx_priv = 0;
2790         int i;
2791
2792         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2793                 priv = &buf_alloc->priv_buf[i];
2794                 if (priv->enable)
2795                         rx_priv += priv->buf_size;
2796         }
2797         return rx_priv;
2798 }
2799
2800 static uint32_t
2801 hns3_get_tx_buff_alloced(struct hns3_pkt_buf_alloc *buf_alloc)
2802 {
2803         uint32_t total_tx_size = 0;
2804         uint32_t i;
2805
2806         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
2807                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
2808
2809         return total_tx_size;
2810 }
2811
2812 /* Get the number of pfc enabled TCs, which have private buffer */
2813 static int
2814 hns3_get_pfc_priv_num(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
2815 {
2816         struct hns3_priv_buf *priv;
2817         int cnt = 0;
2818         uint8_t i;
2819
2820         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2821                 priv = &buf_alloc->priv_buf[i];
2822                 if ((hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2823                         cnt++;
2824         }
2825
2826         return cnt;
2827 }
2828
2829 /* Get the number of pfc disabled TCs, which have private buffer */
2830 static int
2831 hns3_get_no_pfc_priv_num(struct hns3_hw *hw,
2832                          struct hns3_pkt_buf_alloc *buf_alloc)
2833 {
2834         struct hns3_priv_buf *priv;
2835         int cnt = 0;
2836         uint8_t i;
2837
2838         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2839                 priv = &buf_alloc->priv_buf[i];
2840                 if (hw->hw_tc_map & BIT(i) &&
2841                     !(hw->dcb_info.hw_pfc_map & BIT(i)) && priv->enable)
2842                         cnt++;
2843         }
2844
2845         return cnt;
2846 }
2847
2848 static bool
2849 hns3_is_rx_buf_ok(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc,
2850                   uint32_t rx_all)
2851 {
2852         uint32_t shared_buf_min, shared_buf_tc, shared_std, hi_thrd, lo_thrd;
2853         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2854         struct hns3_pf *pf = &hns->pf;
2855         uint32_t shared_buf, aligned_mps;
2856         uint32_t rx_priv;
2857         uint8_t tc_num;
2858         uint8_t i;
2859
2860         tc_num = hns3_get_tc_num(hw);
2861         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2862
2863         if (hns3_dev_dcb_supported(hw))
2864                 shared_buf_min = HNS3_BUF_MUL_BY * aligned_mps +
2865                                         pf->dv_buf_size;
2866         else
2867                 shared_buf_min = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF
2868                                         + pf->dv_buf_size;
2869
2870         shared_buf_tc = tc_num * aligned_mps + aligned_mps;
2871         shared_std = roundup(max_t(uint32_t, shared_buf_min, shared_buf_tc),
2872                              HNS3_BUF_SIZE_UNIT);
2873
2874         rx_priv = hns3_get_rx_priv_buff_alloced(buf_alloc);
2875         if (rx_all < rx_priv + shared_std)
2876                 return false;
2877
2878         shared_buf = rounddown(rx_all - rx_priv, HNS3_BUF_SIZE_UNIT);
2879         buf_alloc->s_buf.buf_size = shared_buf;
2880         if (hns3_dev_dcb_supported(hw)) {
2881                 buf_alloc->s_buf.self.high = shared_buf - pf->dv_buf_size;
2882                 buf_alloc->s_buf.self.low = buf_alloc->s_buf.self.high
2883                         - roundup(aligned_mps / HNS3_BUF_DIV_BY,
2884                                   HNS3_BUF_SIZE_UNIT);
2885         } else {
2886                 buf_alloc->s_buf.self.high =
2887                         aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2888                 buf_alloc->s_buf.self.low = aligned_mps;
2889         }
2890
2891         if (hns3_dev_dcb_supported(hw)) {
2892                 hi_thrd = shared_buf - pf->dv_buf_size;
2893
2894                 if (tc_num <= NEED_RESERVE_TC_NUM)
2895                         hi_thrd = hi_thrd * BUF_RESERVE_PERCENT
2896                                         / BUF_MAX_PERCENT;
2897
2898                 if (tc_num)
2899                         hi_thrd = hi_thrd / tc_num;
2900
2901                 hi_thrd = max_t(uint32_t, hi_thrd,
2902                                 HNS3_BUF_MUL_BY * aligned_mps);
2903                 hi_thrd = rounddown(hi_thrd, HNS3_BUF_SIZE_UNIT);
2904                 lo_thrd = hi_thrd - aligned_mps / HNS3_BUF_DIV_BY;
2905         } else {
2906                 hi_thrd = aligned_mps + HNS3_NON_DCB_ADDITIONAL_BUF;
2907                 lo_thrd = aligned_mps;
2908         }
2909
2910         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2911                 buf_alloc->s_buf.tc_thrd[i].low = lo_thrd;
2912                 buf_alloc->s_buf.tc_thrd[i].high = hi_thrd;
2913         }
2914
2915         return true;
2916 }
2917
2918 static bool
2919 hns3_rx_buf_calc_all(struct hns3_hw *hw, bool max,
2920                      struct hns3_pkt_buf_alloc *buf_alloc)
2921 {
2922         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2923         struct hns3_pf *pf = &hns->pf;
2924         struct hns3_priv_buf *priv;
2925         uint32_t aligned_mps;
2926         uint32_t rx_all;
2927         uint8_t i;
2928
2929         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2930         aligned_mps = roundup(pf->mps, HNS3_BUF_SIZE_UNIT);
2931
2932         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
2933                 priv = &buf_alloc->priv_buf[i];
2934
2935                 priv->enable = 0;
2936                 priv->wl.low = 0;
2937                 priv->wl.high = 0;
2938                 priv->buf_size = 0;
2939
2940                 if (!(hw->hw_tc_map & BIT(i)))
2941                         continue;
2942
2943                 priv->enable = 1;
2944                 if (hw->dcb_info.hw_pfc_map & BIT(i)) {
2945                         priv->wl.low = max ? aligned_mps : HNS3_BUF_SIZE_UNIT;
2946                         priv->wl.high = roundup(priv->wl.low + aligned_mps,
2947                                                 HNS3_BUF_SIZE_UNIT);
2948                 } else {
2949                         priv->wl.low = 0;
2950                         priv->wl.high = max ? (aligned_mps * HNS3_BUF_MUL_BY) :
2951                                         aligned_mps;
2952                 }
2953
2954                 priv->buf_size = priv->wl.high + pf->dv_buf_size;
2955         }
2956
2957         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2958 }
2959
2960 static bool
2961 hns3_drop_nopfc_buf_till_fit(struct hns3_hw *hw,
2962                              struct hns3_pkt_buf_alloc *buf_alloc)
2963 {
2964         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
2965         struct hns3_pf *pf = &hns->pf;
2966         struct hns3_priv_buf *priv;
2967         int no_pfc_priv_num;
2968         uint32_t rx_all;
2969         uint8_t mask;
2970         int i;
2971
2972         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
2973         no_pfc_priv_num = hns3_get_no_pfc_priv_num(hw, buf_alloc);
2974
2975         /* let the last to be cleared first */
2976         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
2977                 priv = &buf_alloc->priv_buf[i];
2978                 mask = BIT((uint8_t)i);
2979
2980                 if (hw->hw_tc_map & mask &&
2981                     !(hw->dcb_info.hw_pfc_map & mask)) {
2982                         /* Clear the no pfc TC private buffer */
2983                         priv->wl.low = 0;
2984                         priv->wl.high = 0;
2985                         priv->buf_size = 0;
2986                         priv->enable = 0;
2987                         no_pfc_priv_num--;
2988                 }
2989
2990                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
2991                     no_pfc_priv_num == 0)
2992                         break;
2993         }
2994
2995         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
2996 }
2997
2998 static bool
2999 hns3_drop_pfc_buf_till_fit(struct hns3_hw *hw,
3000                            struct hns3_pkt_buf_alloc *buf_alloc)
3001 {
3002         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3003         struct hns3_pf *pf = &hns->pf;
3004         struct hns3_priv_buf *priv;
3005         uint32_t rx_all;
3006         int pfc_priv_num;
3007         uint8_t mask;
3008         int i;
3009
3010         rx_all = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3011         pfc_priv_num = hns3_get_pfc_priv_num(hw, buf_alloc);
3012
3013         /* let the last to be cleared first */
3014         for (i = HNS3_MAX_TC_NUM - 1; i >= 0; i--) {
3015                 priv = &buf_alloc->priv_buf[i];
3016                 mask = BIT((uint8_t)i);
3017
3018                 if (hw->hw_tc_map & mask &&
3019                     hw->dcb_info.hw_pfc_map & mask) {
3020                         /* Reduce the number of pfc TC with private buffer */
3021                         priv->wl.low = 0;
3022                         priv->enable = 0;
3023                         priv->wl.high = 0;
3024                         priv->buf_size = 0;
3025                         pfc_priv_num--;
3026                 }
3027                 if (hns3_is_rx_buf_ok(hw, buf_alloc, rx_all) ||
3028                     pfc_priv_num == 0)
3029                         break;
3030         }
3031
3032         return hns3_is_rx_buf_ok(hw, buf_alloc, rx_all);
3033 }
3034
3035 static bool
3036 hns3_only_alloc_priv_buff(struct hns3_hw *hw,
3037                           struct hns3_pkt_buf_alloc *buf_alloc)
3038 {
3039 #define COMPENSATE_BUFFER       0x3C00
3040 #define COMPENSATE_HALF_MPS_NUM 5
3041 #define PRIV_WL_GAP             0x1800
3042         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3043         struct hns3_pf *pf = &hns->pf;
3044         uint32_t tc_num = hns3_get_tc_num(hw);
3045         uint32_t half_mps = pf->mps >> 1;
3046         struct hns3_priv_buf *priv;
3047         uint32_t min_rx_priv;
3048         uint32_t rx_priv;
3049         uint8_t i;
3050
3051         rx_priv = pf->pkt_buf_size - hns3_get_tx_buff_alloced(buf_alloc);
3052         if (tc_num)
3053                 rx_priv = rx_priv / tc_num;
3054
3055         if (tc_num <= NEED_RESERVE_TC_NUM)
3056                 rx_priv = rx_priv * BUF_RESERVE_PERCENT / BUF_MAX_PERCENT;
3057
3058         /*
3059          * Minimum value of private buffer in rx direction (min_rx_priv) is
3060          * equal to "DV + 2.5 * MPS + 15KB". Driver only allocates rx private
3061          * buffer if rx_priv is greater than min_rx_priv.
3062          */
3063         min_rx_priv = pf->dv_buf_size + COMPENSATE_BUFFER +
3064                         COMPENSATE_HALF_MPS_NUM * half_mps;
3065         min_rx_priv = roundup(min_rx_priv, HNS3_BUF_SIZE_UNIT);
3066         rx_priv = rounddown(rx_priv, HNS3_BUF_SIZE_UNIT);
3067
3068         if (rx_priv < min_rx_priv)
3069                 return false;
3070
3071         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3072                 priv = &buf_alloc->priv_buf[i];
3073
3074                 priv->enable = 0;
3075                 priv->wl.low = 0;
3076                 priv->wl.high = 0;
3077                 priv->buf_size = 0;
3078
3079                 if (!(hw->hw_tc_map & BIT(i)))
3080                         continue;
3081
3082                 priv->enable = 1;
3083                 priv->buf_size = rx_priv;
3084                 priv->wl.high = rx_priv - pf->dv_buf_size;
3085                 priv->wl.low = priv->wl.high - PRIV_WL_GAP;
3086         }
3087
3088         buf_alloc->s_buf.buf_size = 0;
3089
3090         return true;
3091 }
3092
3093 /*
3094  * hns3_rx_buffer_calc: calculate the rx private buffer size for all TCs
3095  * @hw: pointer to struct hns3_hw
3096  * @buf_alloc: pointer to buffer calculation data
3097  * @return: 0: calculate sucessful, negative: fail
3098  */
3099 static int
3100 hns3_rx_buffer_calc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3101 {
3102         /* When DCB is not supported, rx private buffer is not allocated. */
3103         if (!hns3_dev_dcb_supported(hw)) {
3104                 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3105                 struct hns3_pf *pf = &hns->pf;
3106                 uint32_t rx_all = pf->pkt_buf_size;
3107
3108                 rx_all -= hns3_get_tx_buff_alloced(buf_alloc);
3109                 if (!hns3_is_rx_buf_ok(hw, buf_alloc, rx_all))
3110                         return -ENOMEM;
3111
3112                 return 0;
3113         }
3114
3115         /*
3116          * Try to allocate privated packet buffer for all TCs without share
3117          * buffer.
3118          */
3119         if (hns3_only_alloc_priv_buff(hw, buf_alloc))
3120                 return 0;
3121
3122         /*
3123          * Try to allocate privated packet buffer for all TCs with share
3124          * buffer.
3125          */
3126         if (hns3_rx_buf_calc_all(hw, true, buf_alloc))
3127                 return 0;
3128
3129         /*
3130          * For different application scenes, the enabled port number, TC number
3131          * and no_drop TC number are different. In order to obtain the better
3132          * performance, software could allocate the buffer size and configure
3133          * the waterline by tring to decrease the private buffer size according
3134          * to the order, namely, waterline of valided tc, pfc disabled tc, pfc
3135          * enabled tc.
3136          */
3137         if (hns3_rx_buf_calc_all(hw, false, buf_alloc))
3138                 return 0;
3139
3140         if (hns3_drop_nopfc_buf_till_fit(hw, buf_alloc))
3141                 return 0;
3142
3143         if (hns3_drop_pfc_buf_till_fit(hw, buf_alloc))
3144                 return 0;
3145
3146         return -ENOMEM;
3147 }
3148
3149 static int
3150 hns3_rx_priv_buf_alloc(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3151 {
3152         struct hns3_rx_priv_buff_cmd *req;
3153         struct hns3_cmd_desc desc;
3154         uint32_t buf_size;
3155         int ret;
3156         int i;
3157
3158         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_PRIV_BUFF_ALLOC, false);
3159         req = (struct hns3_rx_priv_buff_cmd *)desc.data;
3160
3161         /* Alloc private buffer TCs */
3162         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
3163                 struct hns3_priv_buf *priv = &buf_alloc->priv_buf[i];
3164
3165                 req->buf_num[i] =
3166                         rte_cpu_to_le_16(priv->buf_size >> HNS3_BUF_UNIT_S);
3167                 req->buf_num[i] |= rte_cpu_to_le_16(1 << HNS3_TC0_PRI_BUF_EN_B);
3168         }
3169
3170         buf_size = buf_alloc->s_buf.buf_size;
3171         req->shared_buf = rte_cpu_to_le_16((buf_size >> HNS3_BUF_UNIT_S) |
3172                                            (1 << HNS3_TC0_PRI_BUF_EN_B));
3173
3174         ret = hns3_cmd_send(hw, &desc, 1);
3175         if (ret)
3176                 PMD_INIT_LOG(ERR, "rx private buffer alloc cmd failed %d", ret);
3177
3178         return ret;
3179 }
3180
3181 static int
3182 hns3_rx_priv_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3183 {
3184 #define HNS3_RX_PRIV_WL_ALLOC_DESC_NUM 2
3185         struct hns3_rx_priv_wl_buf *req;
3186         struct hns3_priv_buf *priv;
3187         struct hns3_cmd_desc desc[HNS3_RX_PRIV_WL_ALLOC_DESC_NUM];
3188         int i, j;
3189         int ret;
3190
3191         for (i = 0; i < HNS3_RX_PRIV_WL_ALLOC_DESC_NUM; i++) {
3192                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_PRIV_WL_ALLOC,
3193                                           false);
3194                 req = (struct hns3_rx_priv_wl_buf *)desc[i].data;
3195
3196                 /* The first descriptor set the NEXT bit to 1 */
3197                 if (i == 0)
3198                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3199                 else
3200                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3201
3202                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3203                         uint32_t idx = i * HNS3_TC_NUM_ONE_DESC + j;
3204
3205                         priv = &buf_alloc->priv_buf[idx];
3206                         req->tc_wl[j].high = rte_cpu_to_le_16(priv->wl.high >>
3207                                                         HNS3_BUF_UNIT_S);
3208                         req->tc_wl[j].high |=
3209                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3210                         req->tc_wl[j].low = rte_cpu_to_le_16(priv->wl.low >>
3211                                                         HNS3_BUF_UNIT_S);
3212                         req->tc_wl[j].low |=
3213                                 rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3214                 }
3215         }
3216
3217         /* Send 2 descriptor at one time */
3218         ret = hns3_cmd_send(hw, desc, HNS3_RX_PRIV_WL_ALLOC_DESC_NUM);
3219         if (ret)
3220                 PMD_INIT_LOG(ERR, "rx private waterline config cmd failed %d",
3221                              ret);
3222         return ret;
3223 }
3224
3225 static int
3226 hns3_common_thrd_config(struct hns3_hw *hw,
3227                         struct hns3_pkt_buf_alloc *buf_alloc)
3228 {
3229 #define HNS3_RX_COM_THRD_ALLOC_DESC_NUM 2
3230         struct hns3_shared_buf *s_buf = &buf_alloc->s_buf;
3231         struct hns3_rx_com_thrd *req;
3232         struct hns3_cmd_desc desc[HNS3_RX_COM_THRD_ALLOC_DESC_NUM];
3233         struct hns3_tc_thrd *tc;
3234         int tc_idx;
3235         int i, j;
3236         int ret;
3237
3238         for (i = 0; i < HNS3_RX_COM_THRD_ALLOC_DESC_NUM; i++) {
3239                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_RX_COM_THRD_ALLOC,
3240                                           false);
3241                 req = (struct hns3_rx_com_thrd *)&desc[i].data;
3242
3243                 /* The first descriptor set the NEXT bit to 1 */
3244                 if (i == 0)
3245                         desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3246                 else
3247                         desc[i].flag &= ~rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
3248
3249                 for (j = 0; j < HNS3_TC_NUM_ONE_DESC; j++) {
3250                         tc_idx = i * HNS3_TC_NUM_ONE_DESC + j;
3251                         tc = &s_buf->tc_thrd[tc_idx];
3252
3253                         req->com_thrd[j].high =
3254                                 rte_cpu_to_le_16(tc->high >> HNS3_BUF_UNIT_S);
3255                         req->com_thrd[j].high |=
3256                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3257                         req->com_thrd[j].low =
3258                                 rte_cpu_to_le_16(tc->low >> HNS3_BUF_UNIT_S);
3259                         req->com_thrd[j].low |=
3260                                  rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3261                 }
3262         }
3263
3264         /* Send 2 descriptors at one time */
3265         ret = hns3_cmd_send(hw, desc, HNS3_RX_COM_THRD_ALLOC_DESC_NUM);
3266         if (ret)
3267                 PMD_INIT_LOG(ERR, "common threshold config cmd failed %d", ret);
3268
3269         return ret;
3270 }
3271
3272 static int
3273 hns3_common_wl_config(struct hns3_hw *hw, struct hns3_pkt_buf_alloc *buf_alloc)
3274 {
3275         struct hns3_shared_buf *buf = &buf_alloc->s_buf;
3276         struct hns3_rx_com_wl *req;
3277         struct hns3_cmd_desc desc;
3278         int ret;
3279
3280         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RX_COM_WL_ALLOC, false);
3281
3282         req = (struct hns3_rx_com_wl *)desc.data;
3283         req->com_wl.high = rte_cpu_to_le_16(buf->self.high >> HNS3_BUF_UNIT_S);
3284         req->com_wl.high |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3285
3286         req->com_wl.low = rte_cpu_to_le_16(buf->self.low >> HNS3_BUF_UNIT_S);
3287         req->com_wl.low |= rte_cpu_to_le_16(BIT(HNS3_RX_PRIV_EN_B));
3288
3289         ret = hns3_cmd_send(hw, &desc, 1);
3290         if (ret)
3291                 PMD_INIT_LOG(ERR, "common waterline config cmd failed %d", ret);
3292
3293         return ret;
3294 }
3295
3296 int
3297 hns3_buffer_alloc(struct hns3_hw *hw)
3298 {
3299         struct hns3_pkt_buf_alloc pkt_buf;
3300         int ret;
3301
3302         memset(&pkt_buf, 0, sizeof(pkt_buf));
3303         ret = hns3_tx_buffer_calc(hw, &pkt_buf);
3304         if (ret) {
3305                 PMD_INIT_LOG(ERR,
3306                              "could not calc tx buffer size for all TCs %d",
3307                              ret);
3308                 return ret;
3309         }
3310
3311         ret = hns3_tx_buffer_alloc(hw, &pkt_buf);
3312         if (ret) {
3313                 PMD_INIT_LOG(ERR, "could not alloc tx buffers %d", ret);
3314                 return ret;
3315         }
3316
3317         ret = hns3_rx_buffer_calc(hw, &pkt_buf);
3318         if (ret) {
3319                 PMD_INIT_LOG(ERR,
3320                              "could not calc rx priv buffer size for all TCs %d",
3321                              ret);
3322                 return ret;
3323         }
3324
3325         ret = hns3_rx_priv_buf_alloc(hw, &pkt_buf);
3326         if (ret) {
3327                 PMD_INIT_LOG(ERR, "could not alloc rx priv buffer %d", ret);
3328                 return ret;
3329         }
3330
3331         if (hns3_dev_dcb_supported(hw)) {
3332                 ret = hns3_rx_priv_wl_config(hw, &pkt_buf);
3333                 if (ret) {
3334                         PMD_INIT_LOG(ERR,
3335                                      "could not configure rx private waterline %d",
3336                                      ret);
3337                         return ret;
3338                 }
3339
3340                 ret = hns3_common_thrd_config(hw, &pkt_buf);
3341                 if (ret) {
3342                         PMD_INIT_LOG(ERR,
3343                                      "could not configure common threshold %d",
3344                                      ret);
3345                         return ret;
3346                 }
3347         }
3348
3349         ret = hns3_common_wl_config(hw, &pkt_buf);
3350         if (ret)
3351                 PMD_INIT_LOG(ERR, "could not configure common waterline %d",
3352                              ret);
3353
3354         return ret;
3355 }
3356
3357 static int
3358 hns3_mac_init(struct hns3_hw *hw)
3359 {
3360         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
3361         struct hns3_mac *mac = &hw->mac;
3362         struct hns3_pf *pf = &hns->pf;
3363         int ret;
3364
3365         pf->support_sfp_query = true;
3366         mac->link_duplex = ETH_LINK_FULL_DUPLEX;
3367         ret = hns3_cfg_mac_speed_dup_hw(hw, mac->link_speed, mac->link_duplex);
3368         if (ret) {
3369                 PMD_INIT_LOG(ERR, "Config mac speed dup fail ret = %d", ret);
3370                 return ret;
3371         }
3372
3373         mac->link_status = ETH_LINK_DOWN;
3374
3375         return hns3_config_mtu(hw, pf->mps);
3376 }
3377
3378 static int
3379 hns3_get_mac_ethertype_cmd_status(uint16_t cmdq_resp, uint8_t resp_code)
3380 {
3381 #define HNS3_ETHERTYPE_SUCCESS_ADD              0
3382 #define HNS3_ETHERTYPE_ALREADY_ADD              1
3383 #define HNS3_ETHERTYPE_MGR_TBL_OVERFLOW         2
3384 #define HNS3_ETHERTYPE_KEY_CONFLICT             3
3385         int return_status;
3386
3387         if (cmdq_resp) {
3388                 PMD_INIT_LOG(ERR,
3389                              "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
3390                              cmdq_resp);
3391                 return -EIO;
3392         }
3393
3394         switch (resp_code) {
3395         case HNS3_ETHERTYPE_SUCCESS_ADD:
3396         case HNS3_ETHERTYPE_ALREADY_ADD:
3397                 return_status = 0;
3398                 break;
3399         case HNS3_ETHERTYPE_MGR_TBL_OVERFLOW:
3400                 PMD_INIT_LOG(ERR,
3401                              "add mac ethertype failed for manager table overflow.");
3402                 return_status = -EIO;
3403                 break;
3404         case HNS3_ETHERTYPE_KEY_CONFLICT:
3405                 PMD_INIT_LOG(ERR, "add mac ethertype failed for key conflict.");
3406                 return_status = -EIO;
3407                 break;
3408         default:
3409                 PMD_INIT_LOG(ERR,
3410                              "add mac ethertype failed for undefined, code=%d.",
3411                              resp_code);
3412                 return_status = -EIO;
3413         }
3414
3415         return return_status;
3416 }
3417
3418 static int
3419 hns3_add_mgr_tbl(struct hns3_hw *hw,
3420                  const struct hns3_mac_mgr_tbl_entry_cmd *req)
3421 {
3422         struct hns3_cmd_desc desc;
3423         uint8_t resp_code;
3424         uint16_t retval;
3425         int ret;
3426
3427         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_ETHTYPE_ADD, false);
3428         memcpy(desc.data, req, sizeof(struct hns3_mac_mgr_tbl_entry_cmd));
3429
3430         ret = hns3_cmd_send(hw, &desc, 1);
3431         if (ret) {
3432                 PMD_INIT_LOG(ERR,
3433                              "add mac ethertype failed for cmd_send, ret =%d.",
3434                              ret);
3435                 return ret;
3436         }
3437
3438         resp_code = (rte_le_to_cpu_32(desc.data[0]) >> 8) & 0xff;
3439         retval = rte_le_to_cpu_16(desc.retval);
3440
3441         return hns3_get_mac_ethertype_cmd_status(retval, resp_code);
3442 }
3443
3444 static void
3445 hns3_prepare_mgr_tbl(struct hns3_mac_mgr_tbl_entry_cmd *mgr_table,
3446                      int *table_item_num)
3447 {
3448         struct hns3_mac_mgr_tbl_entry_cmd *tbl;
3449
3450         /*
3451          * In current version, we add one item in management table as below:
3452          * 0x0180C200000E -- LLDP MC address
3453          */
3454         tbl = mgr_table;
3455         tbl->flags = HNS3_MAC_MGR_MASK_VLAN_B;
3456         tbl->ethter_type = rte_cpu_to_le_16(HNS3_MAC_ETHERTYPE_LLDP);
3457         tbl->mac_addr_hi32 = rte_cpu_to_le_32(htonl(0x0180C200));
3458         tbl->mac_addr_lo16 = rte_cpu_to_le_16(htons(0x000E));
3459         tbl->i_port_bitmap = 0x1;
3460         *table_item_num = 1;
3461 }
3462
3463 static int
3464 hns3_init_mgr_tbl(struct hns3_hw *hw)
3465 {
3466 #define HNS_MAC_MGR_TBL_MAX_SIZE        16
3467         struct hns3_mac_mgr_tbl_entry_cmd mgr_table[HNS_MAC_MGR_TBL_MAX_SIZE];
3468         int table_item_num;
3469         int ret;
3470         int i;
3471
3472         memset(mgr_table, 0, sizeof(mgr_table));
3473         hns3_prepare_mgr_tbl(mgr_table, &table_item_num);
3474         for (i = 0; i < table_item_num; i++) {
3475                 ret = hns3_add_mgr_tbl(hw, &mgr_table[i]);
3476                 if (ret) {
3477                         PMD_INIT_LOG(ERR, "add mac ethertype failed, ret =%d",
3478                                      ret);
3479                         return ret;
3480                 }
3481         }
3482
3483         return 0;
3484 }
3485
3486 static void
3487 hns3_promisc_param_init(struct hns3_promisc_param *param, bool en_uc,
3488                         bool en_mc, bool en_bc, int vport_id)
3489 {
3490         if (!param)
3491                 return;
3492
3493         memset(param, 0, sizeof(struct hns3_promisc_param));
3494         if (en_uc)
3495                 param->enable = HNS3_PROMISC_EN_UC;
3496         if (en_mc)
3497                 param->enable |= HNS3_PROMISC_EN_MC;
3498         if (en_bc)
3499                 param->enable |= HNS3_PROMISC_EN_BC;
3500         param->vf_id = vport_id;
3501 }
3502
3503 static int
3504 hns3_cmd_set_promisc_mode(struct hns3_hw *hw, struct hns3_promisc_param *param)
3505 {
3506         struct hns3_promisc_cfg_cmd *req;
3507         struct hns3_cmd_desc desc;
3508         int ret;
3509
3510         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PROMISC_MODE, false);
3511
3512         req = (struct hns3_promisc_cfg_cmd *)desc.data;
3513         req->vf_id = param->vf_id;
3514         req->flag = (param->enable << HNS3_PROMISC_EN_B) |
3515             HNS3_PROMISC_TX_EN_B | HNS3_PROMISC_RX_EN_B;
3516
3517         ret = hns3_cmd_send(hw, &desc, 1);
3518         if (ret)
3519                 PMD_INIT_LOG(ERR, "Set promisc mode fail, status is %d", ret);
3520
3521         return ret;
3522 }
3523
3524 static int
3525 hns3_set_promisc_mode(struct hns3_hw *hw, bool en_uc_pmc, bool en_mc_pmc)
3526 {
3527         struct hns3_promisc_param param;
3528         bool en_bc_pmc = true;
3529         uint8_t vf_id;
3530         int ret;
3531
3532         /*
3533          * In current version VF is not supported when PF is driven by DPDK
3534          * driver, the PF-related vf_id is 0, just need to configure parameters
3535          * for vf_id 0.
3536          */
3537         vf_id = 0;
3538
3539         hns3_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, en_bc_pmc, vf_id);
3540         ret = hns3_cmd_set_promisc_mode(hw, &param);
3541         if (ret)
3542                 return ret;
3543
3544         return 0;
3545 }
3546
3547 static int
3548 hns3_dev_promiscuous_enable(struct rte_eth_dev *dev)
3549 {
3550         struct hns3_adapter *hns = dev->data->dev_private;
3551         struct hns3_hw *hw = &hns->hw;
3552         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3553         int ret = 0;
3554
3555         rte_spinlock_lock(&hw->lock);
3556         ret = hns3_set_promisc_mode(hw, true, en_mc_pmc);
3557         rte_spinlock_unlock(&hw->lock);
3558         if (ret)
3559                 hns3_err(hw, "Failed to enable promiscuous mode: %d", ret);
3560
3561         return ret;
3562 }
3563
3564 static int
3565 hns3_dev_promiscuous_disable(struct rte_eth_dev *dev)
3566 {
3567         struct hns3_adapter *hns = dev->data->dev_private;
3568         struct hns3_hw *hw = &hns->hw;
3569         bool en_mc_pmc = (dev->data->all_multicast == 1) ? true : false;
3570         int ret = 0;
3571
3572         /* If now in all_multicast mode, must remain in all_multicast mode. */
3573         rte_spinlock_lock(&hw->lock);
3574         ret = hns3_set_promisc_mode(hw, false, en_mc_pmc);
3575         rte_spinlock_unlock(&hw->lock);
3576         if (ret)
3577                 hns3_err(hw, "Failed to disable promiscuous mode: %d", ret);
3578
3579         return ret;
3580 }
3581
3582 static int
3583 hns3_dev_allmulticast_enable(struct rte_eth_dev *dev)
3584 {
3585         struct hns3_adapter *hns = dev->data->dev_private;
3586         struct hns3_hw *hw = &hns->hw;
3587         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3588         int ret = 0;
3589
3590         rte_spinlock_lock(&hw->lock);
3591         ret = hns3_set_promisc_mode(hw, en_uc_pmc, true);
3592         rte_spinlock_unlock(&hw->lock);
3593         if (ret)
3594                 hns3_err(hw, "Failed to enable allmulticast mode: %d", ret);
3595
3596         return ret;
3597 }
3598
3599 static int
3600 hns3_dev_allmulticast_disable(struct rte_eth_dev *dev)
3601 {
3602         struct hns3_adapter *hns = dev->data->dev_private;
3603         struct hns3_hw *hw = &hns->hw;
3604         bool en_uc_pmc = (dev->data->promiscuous == 1) ? true : false;
3605         int ret = 0;
3606
3607         /* If now in promiscuous mode, must remain in all_multicast mode. */
3608         if (dev->data->promiscuous == 1)
3609                 return 0;
3610
3611         rte_spinlock_lock(&hw->lock);
3612         ret = hns3_set_promisc_mode(hw, en_uc_pmc, false);
3613         rte_spinlock_unlock(&hw->lock);
3614         if (ret)
3615                 hns3_err(hw, "Failed to disable allmulticast mode: %d", ret);
3616
3617         return ret;
3618 }
3619
3620 static int
3621 hns3_dev_promisc_restore(struct hns3_adapter *hns)
3622 {
3623         struct hns3_hw *hw = &hns->hw;
3624         bool en_mc_pmc;
3625         bool en_uc_pmc;
3626
3627         en_uc_pmc = (hw->data->promiscuous == 1) ? true : false;
3628         en_mc_pmc = (hw->data->all_multicast == 1) ? true : false;
3629
3630         return hns3_set_promisc_mode(hw, en_uc_pmc, en_mc_pmc);
3631 }
3632
3633 static int
3634 hns3_get_sfp_speed(struct hns3_hw *hw, uint32_t *speed)
3635 {
3636         struct hns3_sfp_speed_cmd *resp;
3637         struct hns3_cmd_desc desc;
3638         int ret;
3639
3640         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_SFP_GET_SPEED, true);
3641         resp = (struct hns3_sfp_speed_cmd *)desc.data;
3642         ret = hns3_cmd_send(hw, &desc, 1);
3643         if (ret == -EOPNOTSUPP) {
3644                 hns3_err(hw, "IMP do not support get SFP speed %d", ret);
3645                 return ret;
3646         } else if (ret) {
3647                 hns3_err(hw, "get sfp speed failed %d", ret);
3648                 return ret;
3649         }
3650
3651         *speed = resp->sfp_speed;
3652
3653         return 0;
3654 }
3655
3656 static uint8_t
3657 hns3_check_speed_dup(uint8_t duplex, uint32_t speed)
3658 {
3659         if (!(speed == ETH_SPEED_NUM_10M || speed == ETH_SPEED_NUM_100M))
3660                 duplex = ETH_LINK_FULL_DUPLEX;
3661
3662         return duplex;
3663 }
3664
3665 static int
3666 hns3_cfg_mac_speed_dup(struct hns3_hw *hw, uint32_t speed, uint8_t duplex)
3667 {
3668         struct hns3_mac *mac = &hw->mac;
3669         int ret;
3670
3671         duplex = hns3_check_speed_dup(duplex, speed);
3672         if (mac->link_speed == speed && mac->link_duplex == duplex)
3673                 return 0;
3674
3675         ret = hns3_cfg_mac_speed_dup_hw(hw, speed, duplex);
3676         if (ret)
3677                 return ret;
3678
3679         mac->link_speed = speed;
3680         mac->link_duplex = duplex;
3681
3682         return 0;
3683 }
3684
3685 static int
3686 hns3_update_speed_duplex(struct rte_eth_dev *eth_dev)
3687 {
3688         struct hns3_adapter *hns = eth_dev->data->dev_private;
3689         struct hns3_hw *hw = &hns->hw;
3690         struct hns3_pf *pf = &hns->pf;
3691         uint32_t speed;
3692         int ret;
3693
3694         /* If IMP do not support get SFP/qSFP speed, return directly */
3695         if (!pf->support_sfp_query)
3696                 return 0;
3697
3698         ret = hns3_get_sfp_speed(hw, &speed);
3699         if (ret == -EOPNOTSUPP) {
3700                 pf->support_sfp_query = false;
3701                 return ret;
3702         } else if (ret)
3703                 return ret;
3704
3705         if (speed == ETH_SPEED_NUM_NONE)
3706                 return 0; /* do nothing if no SFP */
3707
3708         /* Config full duplex for SFP */
3709         return hns3_cfg_mac_speed_dup(hw, speed, ETH_LINK_FULL_DUPLEX);
3710 }
3711
3712 static int
3713 hns3_cfg_mac_mode(struct hns3_hw *hw, bool enable)
3714 {
3715         struct hns3_config_mac_mode_cmd *req;
3716         struct hns3_cmd_desc desc;
3717         uint32_t loop_en = 0;
3718         uint8_t val = 0;
3719         int ret;
3720
3721         req = (struct hns3_config_mac_mode_cmd *)desc.data;
3722
3723         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CONFIG_MAC_MODE, false);
3724         if (enable)
3725                 val = 1;
3726         hns3_set_bit(loop_en, HNS3_MAC_TX_EN_B, val);
3727         hns3_set_bit(loop_en, HNS3_MAC_RX_EN_B, val);
3728         hns3_set_bit(loop_en, HNS3_MAC_PAD_TX_B, val);
3729         hns3_set_bit(loop_en, HNS3_MAC_PAD_RX_B, val);
3730         hns3_set_bit(loop_en, HNS3_MAC_1588_TX_B, 0);
3731         hns3_set_bit(loop_en, HNS3_MAC_1588_RX_B, 0);
3732         hns3_set_bit(loop_en, HNS3_MAC_APP_LP_B, 0);
3733         hns3_set_bit(loop_en, HNS3_MAC_LINE_LP_B, 0);
3734         hns3_set_bit(loop_en, HNS3_MAC_FCS_TX_B, val);
3735         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_B, val);
3736         hns3_set_bit(loop_en, HNS3_MAC_RX_FCS_STRIP_B, val);
3737         hns3_set_bit(loop_en, HNS3_MAC_TX_OVERSIZE_TRUNCATE_B, val);
3738         hns3_set_bit(loop_en, HNS3_MAC_RX_OVERSIZE_TRUNCATE_B, val);
3739         hns3_set_bit(loop_en, HNS3_MAC_TX_UNDER_MIN_ERR_B, val);
3740         req->txrx_pad_fcs_loop_en = rte_cpu_to_le_32(loop_en);
3741
3742         ret = hns3_cmd_send(hw, &desc, 1);
3743         if (ret)
3744                 PMD_INIT_LOG(ERR, "mac enable fail, ret =%d.", ret);
3745
3746         return ret;
3747 }
3748
3749 static int
3750 hns3_get_mac_link_status(struct hns3_hw *hw)
3751 {
3752         struct hns3_link_status_cmd *req;
3753         struct hns3_cmd_desc desc;
3754         int link_status;
3755         int ret;
3756
3757         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_LINK_STATUS, true);
3758         ret = hns3_cmd_send(hw, &desc, 1);
3759         if (ret) {
3760                 hns3_err(hw, "get link status cmd failed %d", ret);
3761                 return ret;
3762         }
3763
3764         req = (struct hns3_link_status_cmd *)desc.data;
3765         link_status = req->status & HNS3_LINK_STATUS_UP_M;
3766
3767         return !!link_status;
3768 }
3769
3770 static void
3771 hns3_update_link_status(struct hns3_hw *hw)
3772 {
3773         int state;
3774
3775         state = hns3_get_mac_link_status(hw);
3776         if (state != hw->mac.link_status)
3777                 hw->mac.link_status = state;
3778 }
3779
3780 static void
3781 hns3_service_handler(void *param)
3782 {
3783         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
3784         struct hns3_adapter *hns = eth_dev->data->dev_private;
3785         struct hns3_hw *hw = &hns->hw;
3786
3787         if (!hns3_is_reset_pending(hns)) {
3788                 hns3_update_speed_duplex(eth_dev);
3789                 hns3_update_link_status(hw);
3790         } else
3791                 hns3_warn(hw, "Cancel the query when reset is pending");
3792
3793         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
3794 }
3795
3796 static int
3797 hns3_init_hardware(struct hns3_adapter *hns)
3798 {
3799         struct hns3_hw *hw = &hns->hw;
3800         int ret;
3801
3802         ret = hns3_map_tqp(hw);
3803         if (ret) {
3804                 PMD_INIT_LOG(ERR, "Failed to map tqp: %d", ret);
3805                 return ret;
3806         }
3807
3808         ret = hns3_init_umv_space(hw);
3809         if (ret) {
3810                 PMD_INIT_LOG(ERR, "Failed to init umv space: %d", ret);
3811                 return ret;
3812         }
3813
3814         ret = hns3_mac_init(hw);
3815         if (ret) {
3816                 PMD_INIT_LOG(ERR, "Failed to init MAC: %d", ret);
3817                 goto err_mac_init;
3818         }
3819
3820         ret = hns3_init_mgr_tbl(hw);
3821         if (ret) {
3822                 PMD_INIT_LOG(ERR, "Failed to init manager table: %d", ret);
3823                 goto err_mac_init;
3824         }
3825
3826         ret = hns3_set_promisc_mode(hw, false, false);
3827         if (ret) {
3828                 PMD_INIT_LOG(ERR, "Failed to set promisc mode: %d", ret);
3829                 goto err_mac_init;
3830         }
3831
3832         ret = hns3_init_vlan_config(hns);
3833         if (ret) {
3834                 PMD_INIT_LOG(ERR, "Failed to init vlan: %d", ret);
3835                 goto err_mac_init;
3836         }
3837
3838         ret = hns3_dcb_init(hw);
3839         if (ret) {
3840                 PMD_INIT_LOG(ERR, "Failed to init dcb: %d", ret);
3841                 goto err_mac_init;
3842         }
3843
3844         ret = hns3_init_fd_config(hns);
3845         if (ret) {
3846                 PMD_INIT_LOG(ERR, "Failed to init flow director: %d", ret);
3847                 goto err_mac_init;
3848         }
3849
3850         ret = hns3_config_tso(hw, HNS3_TSO_MSS_MIN, HNS3_TSO_MSS_MAX);
3851         if (ret) {
3852                 PMD_INIT_LOG(ERR, "Failed to config tso: %d", ret);
3853                 goto err_mac_init;
3854         }
3855
3856         ret = hns3_config_gro(hw, false);
3857         if (ret) {
3858                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
3859                 goto err_mac_init;
3860         }
3861         return 0;
3862
3863 err_mac_init:
3864         hns3_uninit_umv_space(hw);
3865         return ret;
3866 }
3867
3868 static int
3869 hns3_init_pf(struct rte_eth_dev *eth_dev)
3870 {
3871         struct rte_device *dev = eth_dev->device;
3872         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3873         struct hns3_adapter *hns = eth_dev->data->dev_private;
3874         struct hns3_hw *hw = &hns->hw;
3875         int ret;
3876
3877         PMD_INIT_FUNC_TRACE();
3878
3879         /* Get hardware io base address from pcie BAR2 IO space */
3880         hw->io_base = pci_dev->mem_resource[2].addr;
3881
3882         /* Firmware command queue initialize */
3883         ret = hns3_cmd_init_queue(hw);
3884         if (ret) {
3885                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
3886                 goto err_cmd_init_queue;
3887         }
3888
3889         hns3_clear_all_event_cause(hw);
3890
3891         /* Firmware command initialize */
3892         ret = hns3_cmd_init(hw);
3893         if (ret) {
3894                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
3895                 goto err_cmd_init;
3896         }
3897
3898         ret = rte_intr_callback_register(&pci_dev->intr_handle,
3899                                          hns3_interrupt_handler,
3900                                          eth_dev);
3901         if (ret) {
3902                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
3903                 goto err_intr_callback_register;
3904         }
3905
3906         /* Enable interrupt */
3907         rte_intr_enable(&pci_dev->intr_handle);
3908         hns3_pf_enable_irq0(hw);
3909
3910         /* Get configuration */
3911         ret = hns3_get_configuration(hw);
3912         if (ret) {
3913                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
3914                 goto err_get_config;
3915         }
3916
3917         ret = hns3_init_hardware(hns);
3918         if (ret) {
3919                 PMD_INIT_LOG(ERR, "Failed to init hardware: %d", ret);
3920                 goto err_get_config;
3921         }
3922
3923         /* Initialize flow director filter list & hash */
3924         ret = hns3_fdir_filter_init(hns);
3925         if (ret) {
3926                 PMD_INIT_LOG(ERR, "Failed to alloc hashmap for fdir: %d", ret);
3927                 goto err_hw_init;
3928         }
3929
3930         hns3_set_default_rss_args(hw);
3931
3932         ret = hns3_enable_hw_error_intr(hns, true);
3933         if (ret) {
3934                 PMD_INIT_LOG(ERR, "fail to enable hw error interrupts: %d",
3935                              ret);
3936                 goto err_fdir;
3937         }
3938
3939         return 0;
3940
3941 err_fdir:
3942         hns3_fdir_filter_uninit(hns);
3943 err_hw_init:
3944         hns3_uninit_umv_space(hw);
3945
3946 err_get_config:
3947         hns3_pf_disable_irq0(hw);
3948         rte_intr_disable(&pci_dev->intr_handle);
3949         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
3950                              eth_dev);
3951
3952 err_intr_callback_register:
3953         hns3_cmd_uninit(hw);
3954
3955 err_cmd_init:
3956         hns3_cmd_destroy_queue(hw);
3957
3958 err_cmd_init_queue:
3959         hw->io_base = NULL;
3960
3961         return ret;
3962 }
3963
3964 static void
3965 hns3_uninit_pf(struct rte_eth_dev *eth_dev)
3966 {
3967         struct hns3_adapter *hns = eth_dev->data->dev_private;
3968         struct rte_device *dev = eth_dev->device;
3969         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
3970         struct hns3_hw *hw = &hns->hw;
3971
3972         PMD_INIT_FUNC_TRACE();
3973
3974         hns3_enable_hw_error_intr(hns, false);
3975         hns3_rss_uninit(hns);
3976         hns3_fdir_filter_uninit(hns);
3977         hns3_uninit_umv_space(hw);
3978         hns3_pf_disable_irq0(hw);
3979         rte_intr_disable(&pci_dev->intr_handle);
3980         hns3_intr_unregister(&pci_dev->intr_handle, hns3_interrupt_handler,
3981                              eth_dev);
3982         hns3_cmd_uninit(hw);
3983         hns3_cmd_destroy_queue(hw);
3984         hw->io_base = NULL;
3985 }
3986
3987 static int
3988 hns3_do_start(struct hns3_adapter *hns, bool reset_queue)
3989 {
3990         struct hns3_hw *hw = &hns->hw;
3991         int ret;
3992
3993         ret = hns3_dcb_cfg_update(hns);
3994         if (ret)
3995                 return ret;
3996
3997         /* Enable queues */
3998         ret = hns3_start_queues(hns, reset_queue);
3999         if (ret) {
4000                 PMD_INIT_LOG(ERR, "Failed to start queues: %d", ret);
4001                 return ret;
4002         }
4003
4004         /* Enable MAC */
4005         ret = hns3_cfg_mac_mode(hw, true);
4006         if (ret) {
4007                 PMD_INIT_LOG(ERR, "Failed to enable MAC: %d", ret);
4008                 goto err_config_mac_mode;
4009         }
4010         return 0;
4011
4012 err_config_mac_mode:
4013         hns3_stop_queues(hns, true);
4014         return ret;
4015 }
4016
4017 static int
4018 hns3_dev_start(struct rte_eth_dev *eth_dev)
4019 {
4020         struct hns3_adapter *hns = eth_dev->data->dev_private;
4021         struct hns3_hw *hw = &hns->hw;
4022         int ret;
4023
4024         PMD_INIT_FUNC_TRACE();
4025         if (rte_atomic16_read(&hw->reset.resetting))
4026                 return -EBUSY;
4027         rte_spinlock_lock(&hw->lock);
4028         hw->adapter_state = HNS3_NIC_STARTING;
4029
4030         ret = hns3_do_start(hns, true);
4031         if (ret) {
4032                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4033                 rte_spinlock_unlock(&hw->lock);
4034                 return ret;
4035         }
4036
4037         hw->adapter_state = HNS3_NIC_STARTED;
4038         rte_spinlock_unlock(&hw->lock);
4039         hns3_set_rxtx_function(eth_dev);
4040         hns3_mp_req_start_rxtx(eth_dev);
4041
4042         hns3_info(hw, "hns3 dev start successful!");
4043         return 0;
4044 }
4045
4046 static int
4047 hns3_do_stop(struct hns3_adapter *hns)
4048 {
4049         struct hns3_hw *hw = &hns->hw;
4050         bool reset_queue;
4051         int ret;
4052
4053         ret = hns3_cfg_mac_mode(hw, false);
4054         if (ret)
4055                 return ret;
4056         hw->mac.link_status = ETH_LINK_DOWN;
4057
4058         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
4059                 hns3_configure_all_mac_addr(hns, true);
4060                 reset_queue = true;
4061         } else
4062                 reset_queue = false;
4063         hw->mac.default_addr_setted = false;
4064         return hns3_stop_queues(hns, reset_queue);
4065 }
4066
4067 static void
4068 hns3_dev_stop(struct rte_eth_dev *eth_dev)
4069 {
4070         struct hns3_adapter *hns = eth_dev->data->dev_private;
4071         struct hns3_hw *hw = &hns->hw;
4072
4073         PMD_INIT_FUNC_TRACE();
4074
4075         hw->adapter_state = HNS3_NIC_STOPPING;
4076         hns3_set_rxtx_function(eth_dev);
4077         rte_wmb();
4078         /* Disable datapath on secondary process. */
4079         hns3_mp_req_stop_rxtx(eth_dev);
4080         /* Prevent crashes when queues are still in use. */
4081         rte_delay_ms(hw->tqps_num);
4082
4083         rte_spinlock_lock(&hw->lock);
4084         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
4085                 hns3_do_stop(hns);
4086                 hns3_dev_release_mbufs(hns);
4087                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4088         }
4089         rte_spinlock_unlock(&hw->lock);
4090 }
4091
4092 static void
4093 hns3_dev_close(struct rte_eth_dev *eth_dev)
4094 {
4095         struct hns3_adapter *hns = eth_dev->data->dev_private;
4096         struct hns3_hw *hw = &hns->hw;
4097
4098         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4099                 rte_free(eth_dev->process_private);
4100                 eth_dev->process_private = NULL;
4101                 return;
4102         }
4103
4104         if (hw->adapter_state == HNS3_NIC_STARTED)
4105                 hns3_dev_stop(eth_dev);
4106
4107         hw->adapter_state = HNS3_NIC_CLOSING;
4108         hns3_reset_abort(hns);
4109         hw->adapter_state = HNS3_NIC_CLOSED;
4110         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4111
4112         hns3_configure_all_mc_mac_addr(hns, true);
4113         hns3_remove_all_vlan_table(hns);
4114         hns3_vlan_txvlan_cfg(hns, HNS3_PORT_BASE_VLAN_DISABLE, 0);
4115         hns3_uninit_pf(eth_dev);
4116         hns3_free_all_queues(eth_dev);
4117         rte_free(hw->reset.wait_data);
4118         rte_free(eth_dev->process_private);
4119         eth_dev->process_private = NULL;
4120         hns3_mp_uninit_primary();
4121         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
4122 }
4123
4124 static int
4125 hns3_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4126 {
4127         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4128         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4129
4130         fc_conf->pause_time = pf->pause_time;
4131
4132         /* return fc current mode */
4133         switch (hw->current_mode) {
4134         case HNS3_FC_FULL:
4135                 fc_conf->mode = RTE_FC_FULL;
4136                 break;
4137         case HNS3_FC_TX_PAUSE:
4138                 fc_conf->mode = RTE_FC_TX_PAUSE;
4139                 break;
4140         case HNS3_FC_RX_PAUSE:
4141                 fc_conf->mode = RTE_FC_RX_PAUSE;
4142                 break;
4143         case HNS3_FC_NONE:
4144         default:
4145                 fc_conf->mode = RTE_FC_NONE;
4146                 break;
4147         }
4148
4149         return 0;
4150 }
4151
4152 static void
4153 hns3_get_fc_mode(struct hns3_hw *hw, enum rte_eth_fc_mode mode)
4154 {
4155         switch (mode) {
4156         case RTE_FC_NONE:
4157                 hw->requested_mode = HNS3_FC_NONE;
4158                 break;
4159         case RTE_FC_RX_PAUSE:
4160                 hw->requested_mode = HNS3_FC_RX_PAUSE;
4161                 break;
4162         case RTE_FC_TX_PAUSE:
4163                 hw->requested_mode = HNS3_FC_TX_PAUSE;
4164                 break;
4165         case RTE_FC_FULL:
4166                 hw->requested_mode = HNS3_FC_FULL;
4167                 break;
4168         default:
4169                 hw->requested_mode = HNS3_FC_NONE;
4170                 hns3_warn(hw, "fc_mode(%u) exceeds member scope and is "
4171                           "configured to RTE_FC_NONE", mode);
4172                 break;
4173         }
4174 }
4175
4176 static int
4177 hns3_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4178 {
4179         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4180         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4181         int ret;
4182
4183         if (fc_conf->high_water || fc_conf->low_water ||
4184             fc_conf->send_xon || fc_conf->mac_ctrl_frame_fwd) {
4185                 hns3_err(hw, "Unsupported flow control settings specified, "
4186                          "high_water(%u), low_water(%u), send_xon(%u) and "
4187                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4188                          fc_conf->high_water, fc_conf->low_water,
4189                          fc_conf->send_xon, fc_conf->mac_ctrl_frame_fwd);
4190                 return -EINVAL;
4191         }
4192         if (fc_conf->autoneg) {
4193                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4194                 return -EINVAL;
4195         }
4196         if (!fc_conf->pause_time) {
4197                 hns3_err(hw, "Invalid pause time %d setting.",
4198                          fc_conf->pause_time);
4199                 return -EINVAL;
4200         }
4201
4202         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4203             hw->current_fc_status == HNS3_FC_STATUS_MAC_PAUSE)) {
4204                 hns3_err(hw, "PFC is enabled. Cannot set MAC pause. "
4205                          "current_fc_status = %d", hw->current_fc_status);
4206                 return -EOPNOTSUPP;
4207         }
4208
4209         hns3_get_fc_mode(hw, fc_conf->mode);
4210         if (hw->requested_mode == hw->current_mode &&
4211             pf->pause_time == fc_conf->pause_time)
4212                 return 0;
4213
4214         rte_spinlock_lock(&hw->lock);
4215         ret = hns3_fc_enable(dev, fc_conf);
4216         rte_spinlock_unlock(&hw->lock);
4217
4218         return ret;
4219 }
4220
4221 static int
4222 hns3_priority_flow_ctrl_set(struct rte_eth_dev *dev,
4223                             struct rte_eth_pfc_conf *pfc_conf)
4224 {
4225         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4226         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4227         uint8_t priority;
4228         int ret;
4229
4230         if (!hns3_dev_dcb_supported(hw)) {
4231                 hns3_err(hw, "This port does not support dcb configurations.");
4232                 return -EOPNOTSUPP;
4233         }
4234
4235         if (pfc_conf->fc.high_water || pfc_conf->fc.low_water ||
4236             pfc_conf->fc.send_xon || pfc_conf->fc.mac_ctrl_frame_fwd) {
4237                 hns3_err(hw, "Unsupported flow control settings specified, "
4238                          "high_water(%u), low_water(%u), send_xon(%u) and "
4239                          "mac_ctrl_frame_fwd(%u) must be set to '0'",
4240                          pfc_conf->fc.high_water, pfc_conf->fc.low_water,
4241                          pfc_conf->fc.send_xon,
4242                          pfc_conf->fc.mac_ctrl_frame_fwd);
4243                 return -EINVAL;
4244         }
4245         if (pfc_conf->fc.autoneg) {
4246                 hns3_err(hw, "Unsupported fc auto-negotiation setting.");
4247                 return -EINVAL;
4248         }
4249         if (pfc_conf->fc.pause_time == 0) {
4250                 hns3_err(hw, "Invalid pause time %d setting.",
4251                          pfc_conf->fc.pause_time);
4252                 return -EINVAL;
4253         }
4254
4255         if (!(hw->current_fc_status == HNS3_FC_STATUS_NONE ||
4256             hw->current_fc_status == HNS3_FC_STATUS_PFC)) {
4257                 hns3_err(hw, "MAC pause is enabled. Cannot set PFC."
4258                              "current_fc_status = %d", hw->current_fc_status);
4259                 return -EOPNOTSUPP;
4260         }
4261
4262         priority = pfc_conf->priority;
4263         hns3_get_fc_mode(hw, pfc_conf->fc.mode);
4264         if (hw->dcb_info.pfc_en & BIT(priority) &&
4265             hw->requested_mode == hw->current_mode &&
4266             pfc_conf->fc.pause_time == pf->pause_time)
4267                 return 0;
4268
4269         rte_spinlock_lock(&hw->lock);
4270         ret = hns3_dcb_pfc_enable(dev, pfc_conf);
4271         rte_spinlock_unlock(&hw->lock);
4272
4273         return ret;
4274 }
4275
4276 static int
4277 hns3_get_dcb_info(struct rte_eth_dev *dev, struct rte_eth_dcb_info *dcb_info)
4278 {
4279         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4280         struct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4281         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
4282         int i;
4283
4284         rte_spinlock_lock(&hw->lock);
4285         if ((uint32_t)mq_mode & ETH_MQ_RX_DCB_FLAG)
4286                 dcb_info->nb_tcs = pf->local_max_tc;
4287         else
4288                 dcb_info->nb_tcs = 1;
4289
4290         for (i = 0; i < HNS3_MAX_USER_PRIO; i++)
4291                 dcb_info->prio_tc[i] = hw->dcb_info.prio_tc[i];
4292         for (i = 0; i < dcb_info->nb_tcs; i++)
4293                 dcb_info->tc_bws[i] = hw->dcb_info.pg_info[0].tc_dwrr[i];
4294
4295         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
4296                 dcb_info->tc_queue.tc_rxq[0][i].base =
4297                                         hw->tc_queue[i].tqp_offset;
4298                 dcb_info->tc_queue.tc_txq[0][i].base =
4299                                         hw->tc_queue[i].tqp_offset;
4300                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue =
4301                                         hw->tc_queue[i].tqp_count;
4302                 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
4303                                         hw->tc_queue[i].tqp_count;
4304         }
4305         rte_spinlock_unlock(&hw->lock);
4306
4307         return 0;
4308 }
4309
4310 static int
4311 hns3_reinit_dev(struct hns3_adapter *hns)
4312 {
4313         struct hns3_hw *hw = &hns->hw;
4314         int ret;
4315
4316         ret = hns3_cmd_init(hw);
4317         if (ret) {
4318                 hns3_err(hw, "Failed to init cmd: %d", ret);
4319                 return ret;
4320         }
4321
4322         ret = hns3_reset_all_queues(hns);
4323         if (ret) {
4324                 hns3_err(hw, "Failed to reset all queues: %d", ret);
4325                 goto err_init;
4326         }
4327
4328         ret = hns3_init_hardware(hns);
4329         if (ret) {
4330                 hns3_err(hw, "Failed to init hardware: %d", ret);
4331                 goto err_init;
4332         }
4333
4334         ret = hns3_enable_hw_error_intr(hns, true);
4335         if (ret) {
4336                 hns3_err(hw, "fail to enable hw error interrupts: %d",
4337                              ret);
4338                 goto err_mac_init;
4339         }
4340         hns3_info(hw, "Reset done, driver initialization finished.");
4341
4342         return 0;
4343
4344 err_mac_init:
4345         hns3_uninit_umv_space(hw);
4346 err_init:
4347         hns3_cmd_uninit(hw);
4348
4349         return ret;
4350 }
4351
4352 static bool
4353 is_pf_reset_done(struct hns3_hw *hw)
4354 {
4355         uint32_t val, reg, reg_bit;
4356
4357         switch (hw->reset.level) {
4358         case HNS3_IMP_RESET:
4359                 reg = HNS3_GLOBAL_RESET_REG;
4360                 reg_bit = HNS3_IMP_RESET_BIT;
4361                 break;
4362         case HNS3_GLOBAL_RESET:
4363                 reg = HNS3_GLOBAL_RESET_REG;
4364                 reg_bit = HNS3_GLOBAL_RESET_BIT;
4365                 break;
4366         case HNS3_FUNC_RESET:
4367                 reg = HNS3_FUN_RST_ING;
4368                 reg_bit = HNS3_FUN_RST_ING_B;
4369                 break;
4370         case HNS3_FLR_RESET:
4371         default:
4372                 hns3_err(hw, "Wait for unsupported reset level: %d",
4373                          hw->reset.level);
4374                 return true;
4375         }
4376         val = hns3_read_dev(hw, reg);
4377         if (hns3_get_bit(val, reg_bit))
4378                 return false;
4379         else
4380                 return true;
4381 }
4382
4383 bool
4384 hns3_is_reset_pending(struct hns3_adapter *hns)
4385 {
4386         struct hns3_hw *hw = &hns->hw;
4387         enum hns3_reset_level reset;
4388
4389         hns3_check_event_cause(hns, NULL);
4390         reset = hns3_get_reset_level(hns, &hw->reset.pending);
4391         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4392                 hns3_warn(hw, "High level reset %d is pending", reset);
4393                 return true;
4394         }
4395         reset = hns3_get_reset_level(hns, &hw->reset.request);
4396         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
4397                 hns3_warn(hw, "High level reset %d is request", reset);
4398                 return true;
4399         }
4400         return false;
4401 }
4402
4403 static int
4404 hns3_wait_hardware_ready(struct hns3_adapter *hns)
4405 {
4406         struct hns3_hw *hw = &hns->hw;
4407         struct hns3_wait_data *wait_data = hw->reset.wait_data;
4408         struct timeval tv;
4409
4410         if (wait_data->result == HNS3_WAIT_SUCCESS)
4411                 return 0;
4412         else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
4413                 gettimeofday(&tv, NULL);
4414                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
4415                           tv.tv_sec, tv.tv_usec);
4416                 return -ETIME;
4417         } else if (wait_data->result == HNS3_WAIT_REQUEST)
4418                 return -EAGAIN;
4419
4420         wait_data->hns = hns;
4421         wait_data->check_completion = is_pf_reset_done;
4422         wait_data->end_ms = (uint64_t)HNS3_RESET_WAIT_CNT *
4423                                       HNS3_RESET_WAIT_MS + get_timeofday_ms();
4424         wait_data->interval = HNS3_RESET_WAIT_MS * USEC_PER_MSEC;
4425         wait_data->count = HNS3_RESET_WAIT_CNT;
4426         wait_data->result = HNS3_WAIT_REQUEST;
4427         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
4428         return -EAGAIN;
4429 }
4430
4431 static int
4432 hns3_func_reset_cmd(struct hns3_hw *hw, int func_id)
4433 {
4434         struct hns3_cmd_desc desc;
4435         struct hns3_reset_cmd *req = (struct hns3_reset_cmd *)desc.data;
4436
4437         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false);
4438         hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_FUNC_B, 1);
4439         req->fun_reset_vfid = func_id;
4440
4441         return hns3_cmd_send(hw, &desc, 1);
4442 }
4443
4444 static int
4445 hns3_imp_reset_cmd(struct hns3_hw *hw)
4446 {
4447         struct hns3_cmd_desc desc;
4448
4449         hns3_cmd_setup_basic_desc(&desc, 0xFFFE, false);
4450         desc.data[0] = 0xeedd;
4451
4452         return hns3_cmd_send(hw, &desc, 1);
4453 }
4454
4455 static void
4456 hns3_msix_process(struct hns3_adapter *hns, enum hns3_reset_level reset_level)
4457 {
4458         struct hns3_hw *hw = &hns->hw;
4459         struct timeval tv;
4460         uint32_t val;
4461
4462         gettimeofday(&tv, NULL);
4463         if (hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG) ||
4464             hns3_read_dev(hw, HNS3_FUN_RST_ING)) {
4465                 hns3_warn(hw, "Don't process msix during resetting time=%ld.%.6ld",
4466                           tv.tv_sec, tv.tv_usec);
4467                 return;
4468         }
4469
4470         switch (reset_level) {
4471         case HNS3_IMP_RESET:
4472                 hns3_imp_reset_cmd(hw);
4473                 hns3_warn(hw, "IMP Reset requested time=%ld.%.6ld",
4474                           tv.tv_sec, tv.tv_usec);
4475                 break;
4476         case HNS3_GLOBAL_RESET:
4477                 val = hns3_read_dev(hw, HNS3_GLOBAL_RESET_REG);
4478                 hns3_set_bit(val, HNS3_GLOBAL_RESET_BIT, 1);
4479                 hns3_write_dev(hw, HNS3_GLOBAL_RESET_REG, val);
4480                 hns3_warn(hw, "Global Reset requested time=%ld.%.6ld",
4481                           tv.tv_sec, tv.tv_usec);
4482                 break;
4483         case HNS3_FUNC_RESET:
4484                 hns3_warn(hw, "PF Reset requested time=%ld.%.6ld",
4485                           tv.tv_sec, tv.tv_usec);
4486                 /* schedule again to check later */
4487                 hns3_atomic_set_bit(HNS3_FUNC_RESET, &hw->reset.pending);
4488                 hns3_schedule_reset(hns);
4489                 break;
4490         default:
4491                 hns3_warn(hw, "Unsupported reset level: %d", reset_level);
4492                 return;
4493         }
4494         hns3_atomic_clear_bit(reset_level, &hw->reset.request);
4495 }
4496
4497 static enum hns3_reset_level
4498 hns3_get_reset_level(struct hns3_adapter *hns, uint64_t *levels)
4499 {
4500         struct hns3_hw *hw = &hns->hw;
4501         enum hns3_reset_level reset_level = HNS3_NONE_RESET;
4502
4503         /* Return the highest priority reset level amongst all */
4504         if (hns3_atomic_test_bit(HNS3_IMP_RESET, levels))
4505                 reset_level = HNS3_IMP_RESET;
4506         else if (hns3_atomic_test_bit(HNS3_GLOBAL_RESET, levels))
4507                 reset_level = HNS3_GLOBAL_RESET;
4508         else if (hns3_atomic_test_bit(HNS3_FUNC_RESET, levels))
4509                 reset_level = HNS3_FUNC_RESET;
4510         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
4511                 reset_level = HNS3_FLR_RESET;
4512
4513         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
4514                 return HNS3_NONE_RESET;
4515
4516         return reset_level;
4517 }
4518
4519 static int
4520 hns3_prepare_reset(struct hns3_adapter *hns)
4521 {
4522         struct hns3_hw *hw = &hns->hw;
4523         uint32_t reg_val;
4524         int ret;
4525
4526         switch (hw->reset.level) {
4527         case HNS3_FUNC_RESET:
4528                 ret = hns3_func_reset_cmd(hw, 0);
4529                 if (ret)
4530                         return ret;
4531
4532                 /*
4533                  * After performaning pf reset, it is not necessary to do the
4534                  * mailbox handling or send any command to firmware, because
4535                  * any mailbox handling or command to firmware is only valid
4536                  * after hns3_cmd_init is called.
4537                  */
4538                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
4539                 hw->reset.stats.request_cnt++;
4540                 break;
4541         case HNS3_IMP_RESET:
4542                 reg_val = hns3_read_dev(hw, HNS3_VECTOR0_OTER_EN_REG);
4543                 hns3_write_dev(hw, HNS3_VECTOR0_OTER_EN_REG, reg_val |
4544                                BIT(HNS3_VECTOR0_IMP_RESET_INT_B));
4545                 break;
4546         default:
4547                 break;
4548         }
4549         return 0;
4550 }
4551
4552 static int
4553 hns3_set_rst_done(struct hns3_hw *hw)
4554 {
4555         struct hns3_pf_rst_done_cmd *req;
4556         struct hns3_cmd_desc desc;
4557
4558         req = (struct hns3_pf_rst_done_cmd *)desc.data;
4559         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PF_RST_DONE, false);
4560         req->pf_rst_done |= HNS3_PF_RESET_DONE_BIT;
4561         return hns3_cmd_send(hw, &desc, 1);
4562 }
4563
4564 static int
4565 hns3_stop_service(struct hns3_adapter *hns)
4566 {
4567         struct hns3_hw *hw = &hns->hw;
4568         struct rte_eth_dev *eth_dev;
4569
4570         eth_dev = &rte_eth_devices[hw->data->port_id];
4571         rte_eal_alarm_cancel(hns3_service_handler, eth_dev);
4572         hw->mac.link_status = ETH_LINK_DOWN;
4573
4574         hns3_set_rxtx_function(eth_dev);
4575         rte_wmb();
4576         /* Disable datapath on secondary process. */
4577         hns3_mp_req_stop_rxtx(eth_dev);
4578         rte_delay_ms(hw->tqps_num);
4579
4580         rte_spinlock_lock(&hw->lock);
4581         if (hns->hw.adapter_state == HNS3_NIC_STARTED ||
4582             hw->adapter_state == HNS3_NIC_STOPPING) {
4583                 hns3_do_stop(hns);
4584                 hw->reset.mbuf_deferred_free = true;
4585         } else
4586                 hw->reset.mbuf_deferred_free = false;
4587
4588         /*
4589          * It is cumbersome for hardware to pick-and-choose entries for deletion
4590          * from table space. Hence, for function reset software intervention is
4591          * required to delete the entries
4592          */
4593         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
4594                 hns3_configure_all_mc_mac_addr(hns, true);
4595         rte_spinlock_unlock(&hw->lock);
4596
4597         return 0;
4598 }
4599
4600 static int
4601 hns3_start_service(struct hns3_adapter *hns)
4602 {
4603         struct hns3_hw *hw = &hns->hw;
4604         struct rte_eth_dev *eth_dev;
4605
4606         if (hw->reset.level == HNS3_IMP_RESET ||
4607             hw->reset.level == HNS3_GLOBAL_RESET)
4608                 hns3_set_rst_done(hw);
4609         eth_dev = &rte_eth_devices[hw->data->port_id];
4610         hns3_set_rxtx_function(eth_dev);
4611         hns3_mp_req_start_rxtx(eth_dev);
4612         hns3_service_handler(eth_dev);
4613         return 0;
4614 }
4615
4616 static int
4617 hns3_restore_conf(struct hns3_adapter *hns)
4618 {
4619         struct hns3_hw *hw = &hns->hw;
4620         int ret;
4621
4622         ret = hns3_configure_all_mac_addr(hns, false);
4623         if (ret)
4624                 return ret;
4625
4626         ret = hns3_configure_all_mc_mac_addr(hns, false);
4627         if (ret)
4628                 goto err_mc_mac;
4629
4630         ret = hns3_dev_promisc_restore(hns);
4631         if (ret)
4632                 goto err_promisc;
4633
4634         ret = hns3_restore_vlan_table(hns);
4635         if (ret)
4636                 goto err_promisc;
4637
4638         ret = hns3_restore_vlan_conf(hns);
4639         if (ret)
4640                 goto err_promisc;
4641
4642         ret = hns3_restore_all_fdir_filter(hns);
4643         if (ret)
4644                 goto err_promisc;
4645
4646         if (hns->hw.adapter_state == HNS3_NIC_STARTED) {
4647                 ret = hns3_do_start(hns, false);
4648                 if (ret)
4649                         goto err_promisc;
4650                 hns3_info(hw, "hns3 dev restart successful!");
4651         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
4652                 hw->adapter_state = HNS3_NIC_CONFIGURED;
4653         return 0;
4654
4655 err_promisc:
4656         hns3_configure_all_mc_mac_addr(hns, true);
4657 err_mc_mac:
4658         hns3_configure_all_mac_addr(hns, true);
4659         return ret;
4660 }
4661
4662 static void
4663 hns3_reset_service(void *param)
4664 {
4665         struct hns3_adapter *hns = (struct hns3_adapter *)param;
4666         struct hns3_hw *hw = &hns->hw;
4667         enum hns3_reset_level reset_level;
4668         struct timeval tv_delta;
4669         struct timeval tv_start;
4670         struct timeval tv;
4671         uint64_t msec;
4672         int ret;
4673
4674         /*
4675          * The interrupt is not triggered within the delay time.
4676          * The interrupt may have been lost. It is necessary to handle
4677          * the interrupt to recover from the error.
4678          */
4679         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
4680                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
4681                 hns3_err(hw, "Handling interrupts in delayed tasks");
4682                 hns3_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
4683                 reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4684                 if (reset_level == HNS3_NONE_RESET) {
4685                         hns3_err(hw, "No reset level is set, try IMP reset");
4686                         hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
4687                 }
4688         }
4689         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
4690
4691         /*
4692          * Check if there is any ongoing reset in the hardware. This status can
4693          * be checked from reset_pending. If there is then, we need to wait for
4694          * hardware to complete reset.
4695          *    a. If we are able to figure out in reasonable time that hardware
4696          *       has fully resetted then, we can proceed with driver, client
4697          *       reset.
4698          *    b. else, we can come back later to check this status so re-sched
4699          *       now.
4700          */
4701         reset_level = hns3_get_reset_level(hns, &hw->reset.pending);
4702         if (reset_level != HNS3_NONE_RESET) {
4703                 gettimeofday(&tv_start, NULL);
4704                 ret = hns3_reset_process(hns, reset_level);
4705                 gettimeofday(&tv, NULL);
4706                 timersub(&tv, &tv_start, &tv_delta);
4707                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
4708                        tv_delta.tv_usec / USEC_PER_MSEC;
4709                 if (msec > HNS3_RESET_PROCESS_MS)
4710                         hns3_err(hw, "%d handle long time delta %" PRIx64
4711                                      " ms time=%ld.%.6ld",
4712                                  hw->reset.level, msec,
4713                                  tv.tv_sec, tv.tv_usec);
4714                 if (ret == -EAGAIN)
4715                         return;
4716         }
4717
4718         /* Check if we got any *new* reset requests to be honored */
4719         reset_level = hns3_get_reset_level(hns, &hw->reset.request);
4720         if (reset_level != HNS3_NONE_RESET)
4721                 hns3_msix_process(hns, reset_level);
4722 }
4723
4724 static const struct eth_dev_ops hns3_eth_dev_ops = {
4725         .dev_start          = hns3_dev_start,
4726         .dev_stop           = hns3_dev_stop,
4727         .dev_close          = hns3_dev_close,
4728         .promiscuous_enable = hns3_dev_promiscuous_enable,
4729         .promiscuous_disable = hns3_dev_promiscuous_disable,
4730         .allmulticast_enable  = hns3_dev_allmulticast_enable,
4731         .allmulticast_disable = hns3_dev_allmulticast_disable,
4732         .mtu_set            = hns3_dev_mtu_set,
4733         .stats_get          = hns3_stats_get,
4734         .stats_reset        = hns3_stats_reset,
4735         .xstats_get         = hns3_dev_xstats_get,
4736         .xstats_get_names   = hns3_dev_xstats_get_names,
4737         .xstats_reset       = hns3_dev_xstats_reset,
4738         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
4739         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
4740         .dev_infos_get          = hns3_dev_infos_get,
4741         .fw_version_get         = hns3_fw_version_get,
4742         .rx_queue_setup         = hns3_rx_queue_setup,
4743         .tx_queue_setup         = hns3_tx_queue_setup,
4744         .rx_queue_release       = hns3_dev_rx_queue_release,
4745         .tx_queue_release       = hns3_dev_tx_queue_release,
4746         .dev_configure          = hns3_dev_configure,
4747         .flow_ctrl_get          = hns3_flow_ctrl_get,
4748         .flow_ctrl_set          = hns3_flow_ctrl_set,
4749         .priority_flow_ctrl_set = hns3_priority_flow_ctrl_set,
4750         .mac_addr_add           = hns3_add_mac_addr,
4751         .mac_addr_remove        = hns3_remove_mac_addr,
4752         .mac_addr_set           = hns3_set_default_mac_addr,
4753         .set_mc_addr_list       = hns3_set_mc_mac_addr_list,
4754         .link_update            = hns3_dev_link_update,
4755         .rss_hash_update        = hns3_dev_rss_hash_update,
4756         .rss_hash_conf_get      = hns3_dev_rss_hash_conf_get,
4757         .reta_update            = hns3_dev_rss_reta_update,
4758         .reta_query             = hns3_dev_rss_reta_query,
4759         .filter_ctrl            = hns3_dev_filter_ctrl,
4760         .vlan_filter_set        = hns3_vlan_filter_set,
4761         .vlan_tpid_set          = hns3_vlan_tpid_set,
4762         .vlan_offload_set       = hns3_vlan_offload_set,
4763         .vlan_pvid_set          = hns3_vlan_pvid_set,
4764         .get_reg                = hns3_get_regs,
4765         .get_dcb_info           = hns3_get_dcb_info,
4766         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
4767 };
4768
4769 static const struct hns3_reset_ops hns3_reset_ops = {
4770         .reset_service       = hns3_reset_service,
4771         .stop_service        = hns3_stop_service,
4772         .prepare_reset       = hns3_prepare_reset,
4773         .wait_hardware_ready = hns3_wait_hardware_ready,
4774         .reinit_dev          = hns3_reinit_dev,
4775         .restore_conf        = hns3_restore_conf,
4776         .start_service       = hns3_start_service,
4777 };
4778
4779 static int
4780 hns3_dev_init(struct rte_eth_dev *eth_dev)
4781 {
4782         struct rte_device *dev = eth_dev->device;
4783         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
4784         struct hns3_adapter *hns = eth_dev->data->dev_private;
4785         struct hns3_hw *hw = &hns->hw;
4786         uint16_t device_id = pci_dev->id.device_id;
4787         int ret;
4788
4789         PMD_INIT_FUNC_TRACE();
4790         eth_dev->process_private = (struct hns3_process_private *)
4791             rte_zmalloc_socket("hns3_filter_list",
4792                                sizeof(struct hns3_process_private),
4793                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
4794         if (eth_dev->process_private == NULL) {
4795                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
4796                 return -ENOMEM;
4797         }
4798         /* initialize flow filter lists */
4799         hns3_filterlist_init(eth_dev);
4800
4801         hns3_set_rxtx_function(eth_dev);
4802         eth_dev->dev_ops = &hns3_eth_dev_ops;
4803         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
4804                 hns3_mp_init_secondary();
4805                 hw->secondary_cnt++;
4806                 return 0;
4807         }
4808
4809         hns3_mp_init_primary();
4810         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
4811
4812         if (device_id == HNS3_DEV_ID_25GE_RDMA ||
4813             device_id == HNS3_DEV_ID_50GE_RDMA ||
4814             device_id == HNS3_DEV_ID_100G_RDMA_MACSEC)
4815                 hns3_set_bit(hw->flag, HNS3_DEV_SUPPORT_DCB_B, 1);
4816
4817         hns->is_vf = false;
4818         hw->data = eth_dev->data;
4819
4820         /*
4821          * Set default max packet size according to the mtu
4822          * default vale in DPDK frame.
4823          */
4824         hns->pf.mps = hw->data->mtu + HNS3_ETH_OVERHEAD;
4825
4826         ret = hns3_reset_init(hw);
4827         if (ret)
4828                 goto err_init_reset;
4829         hw->reset.ops = &hns3_reset_ops;
4830
4831         ret = hns3_init_pf(eth_dev);
4832         if (ret) {
4833                 PMD_INIT_LOG(ERR, "Failed to init pf: %d", ret);
4834                 goto err_init_pf;
4835         }
4836
4837         /* Allocate memory for storing MAC addresses */
4838         eth_dev->data->mac_addrs = rte_zmalloc("hns3-mac",
4839                                                sizeof(struct rte_ether_addr) *
4840                                                HNS3_UC_MACADDR_NUM, 0);
4841         if (eth_dev->data->mac_addrs == NULL) {
4842                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
4843                              "to store MAC addresses",
4844                              sizeof(struct rte_ether_addr) *
4845                              HNS3_UC_MACADDR_NUM);
4846                 ret = -ENOMEM;
4847                 goto err_rte_zmalloc;
4848         }
4849
4850         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
4851                             &eth_dev->data->mac_addrs[0]);
4852
4853         hw->adapter_state = HNS3_NIC_INITIALIZED;
4854         /*
4855          * Pass the information to the rte_eth_dev_close() that it should also
4856          * release the private port resources.
4857          */
4858         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4859
4860         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
4861                 hns3_err(hw, "Reschedule reset service after dev_init");
4862                 hns3_schedule_reset(hns);
4863         } else {
4864                 /* IMP will wait ready flag before reset */
4865                 hns3_notify_reset_ready(hw, false);
4866         }
4867
4868         rte_eal_alarm_set(HNS3_SERVICE_INTERVAL, hns3_service_handler, eth_dev);
4869         hns3_info(hw, "hns3 dev initialization successful!");
4870         return 0;
4871
4872 err_rte_zmalloc:
4873         hns3_uninit_pf(eth_dev);
4874
4875 err_init_pf:
4876         rte_free(hw->reset.wait_data);
4877 err_init_reset:
4878         eth_dev->dev_ops = NULL;
4879         eth_dev->rx_pkt_burst = NULL;
4880         eth_dev->tx_pkt_burst = NULL;
4881         eth_dev->tx_pkt_prepare = NULL;
4882         rte_free(eth_dev->process_private);
4883         eth_dev->process_private = NULL;
4884         return ret;
4885 }
4886
4887 static int
4888 hns3_dev_uninit(struct rte_eth_dev *eth_dev)
4889 {
4890         struct hns3_adapter *hns = eth_dev->data->dev_private;
4891         struct hns3_hw *hw = &hns->hw;
4892
4893         PMD_INIT_FUNC_TRACE();
4894
4895         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4896                 return -EPERM;
4897
4898         eth_dev->dev_ops = NULL;
4899         eth_dev->rx_pkt_burst = NULL;
4900         eth_dev->tx_pkt_burst = NULL;
4901         eth_dev->tx_pkt_prepare = NULL;
4902         if (hw->adapter_state < HNS3_NIC_CLOSING)
4903                 hns3_dev_close(eth_dev);
4904
4905         hw->adapter_state = HNS3_NIC_REMOVED;
4906         return 0;
4907 }
4908
4909 static int
4910 eth_hns3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4911                    struct rte_pci_device *pci_dev)
4912 {
4913         return rte_eth_dev_pci_generic_probe(pci_dev,
4914                                              sizeof(struct hns3_adapter),
4915                                              hns3_dev_init);
4916 }
4917
4918 static int
4919 eth_hns3_pci_remove(struct rte_pci_device *pci_dev)
4920 {
4921         return rte_eth_dev_pci_generic_remove(pci_dev, hns3_dev_uninit);
4922 }
4923
4924 static const struct rte_pci_id pci_id_hns3_map[] = {
4925         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_GE) },
4926         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE) },
4927         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_25GE_RDMA) },
4928         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_50GE_RDMA) },
4929         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_MACSEC) },
4930         { .vendor_id = 0, /* sentinel */ },
4931 };
4932
4933 static struct rte_pci_driver rte_hns3_pmd = {
4934         .id_table = pci_id_hns3_map,
4935         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
4936         .probe = eth_hns3_pci_probe,
4937         .remove = eth_hns3_pci_remove,
4938 };
4939
4940 RTE_PMD_REGISTER_PCI(net_hns3, rte_hns3_pmd);
4941 RTE_PMD_REGISTER_PCI_TABLE(net_hns3, pci_id_hns3_map);
4942 RTE_PMD_REGISTER_KMOD_DEP(net_hns3, "* igb_uio | vfio-pci");
4943
4944 RTE_INIT(hns3_init_log)
4945 {
4946         hns3_logtype_init = rte_log_register("pmd.net.hns3.init");
4947         if (hns3_logtype_init >= 0)
4948                 rte_log_set_level(hns3_logtype_init, RTE_LOG_NOTICE);
4949         hns3_logtype_driver = rte_log_register("pmd.net.hns3.driver");
4950         if (hns3_logtype_driver >= 0)
4951                 rte_log_set_level(hns3_logtype_driver, RTE_LOG_NOTICE);
4952 }