drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 /* set PCI bus mastering */
  63 static void
  64 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  65 {
  66         uint16_t reg;
  67
  68         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  69
  70         if (op)
  71                 /* set the master bit */
  72                 reg |= PCI_COMMAND_MASTER;
  73         else
  74                 reg &= ~(PCI_COMMAND_MASTER);
  75
  76         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  77 }
  78
  79 /**
  80  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  81  * @cap: the capability
  82  *
  83  * Return the address of the given capability within the PCI capability list.
  84  */
  85 static int
  86 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  87 {
  88 #define MAX_PCIE_CAPABILITY 48
  89         uint16_t status;
  90         uint8_t pos;
  91         uint8_t id;
  92         int ttl;
  93
  94         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 100         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 101                 rte_pci_read_config(device, &id, sizeof(id),
 102                                     (pos + PCI_CAP_LIST_ID));
 103
 104                 if (id == 0xFF)
 105                         break;
 106
 107                 if (id == cap)
 108                         return (int)pos;
 109
 110                 rte_pci_read_config(device, &pos, sizeof(pos),
 111                                     (pos + PCI_CAP_LIST_NEXT));
 112         }
 113         return 0;
 114 }
 115
 116 static int
 117 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 118 {
 119         uint16_t control;
 120         int pos;
 121
 122         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 123         if (pos) {
 124                 rte_pci_read_config(device, &control, sizeof(control),
 125                                     (pos + PCI_MSIX_FLAGS));
 126                 if (op)
 127                         control |= PCI_MSIX_FLAGS_ENABLE;
 128                 else
 129                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 130                 rte_pci_write_config(device, &control, sizeof(control),
 131                                      (pos + PCI_MSIX_FLAGS));
 132                 return 0;
 133         }
 134         return -ENXIO;
 135 }
 136
 137 static int
 138 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 139                     __attribute__ ((unused)) uint32_t idx,
 140                     __attribute__ ((unused)) uint32_t pool)
 141 {
 142         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 143         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 144         int ret;
 145
 146         rte_spinlock_lock(&hw->lock);
 147         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 148                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 149                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 150         rte_spinlock_unlock(&hw->lock);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
 155                          ret);
 156         }
 157
 158         return ret;
 159 }
 160
 161 static void
 162 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 163 {
 164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 165         /* index will be checked by upper level rte interface */
 166         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 168         int ret;
 169
 170         rte_spinlock_lock(&hw->lock);
 171         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 172                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 173                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 174                                 NULL, 0);
 175         rte_spinlock_unlock(&hw->lock);
 176         if (ret) {
 177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 178                                       mac_addr);
 179                 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
 180                          mac_str, ret);
 181         }
 182 }
 183
 184 static int
 185 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 186                             struct rte_ether_addr *mac_addr)
 187 {
 188 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 190         struct rte_ether_addr *old_addr;
 191         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 196                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 197                                       mac_addr);
 198                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid.",
 199                          mac_str);
 200                 return -EINVAL;
 201         }
 202
 203         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 204         rte_spinlock_lock(&hw->lock);
 205         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 206         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 207                RTE_ETHER_ADDR_LEN);
 208
 209         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 210                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 211                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 212         if (ret) {
 213                 /*
 214                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 215                  * driver. When user has configured a MAC address for VF device
 216                  * by "ip link set ..." command based on the PF device, the hns3
 217                  * PF kernel ethdev driver does not allow VF driver to request
 218                  * reconfiguring a different default MAC address, and return
 219                  * -EPREM to VF driver through mailbox.
 220                  */
 221                 if (ret == -EPERM) {
 222                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 223                                               old_addr);
 224                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 225                                   mac_str);
 226                 } else {
 227                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 228                                               mac_addr);
 229                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 230                                  mac_str, ret);
 231                 }
 232         }
 233
 234         rte_ether_addr_copy(mac_addr,
 235                             (struct rte_ether_addr *)hw->mac.mac_addr);
 236         rte_spinlock_unlock(&hw->lock);
 237
 238         return ret;
 239 }
 240
 241 static int
 242 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 243 {
 244         struct hns3_hw *hw = &hns->hw;
 245         struct rte_ether_addr *addr;
 246         enum hns3_mbx_mac_vlan_subcode opcode;
 247         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 248         int ret = 0;
 249         int i;
 250
 251         if (del)
 252                 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
 253         else
 254                 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
 255         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 256                 addr = &hw->data->mac_addrs[i];
 257                 if (!rte_is_valid_assigned_ether_addr(addr))
 258                         continue;
 259                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 260                 hns3_dbg(hw, "rm mac addr: %s", mac_str);
 261                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
 262                                         addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 263                                         false, NULL, 0);
 264                 if (ret) {
 265                         hns3_err(hw, "Failed to remove mac addr for vf: %d",
 266                                  ret);
 267                         break;
 268                 }
 269         }
 270         return ret;
 271 }
 272
 273 static int
 274 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
 275                        struct rte_ether_addr *mac_addr)
 276 {
 277         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 278         struct hns3_hw *hw = &hns->hw;
 279         int ret;
 280
 281         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 282                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 283                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 284                                 NULL, 0);
 285         if (ret) {
 286                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 287                                       mac_addr);
 288                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 289                          mac_str, ret);
 290                 return ret;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int
 297 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
 298                           struct rte_ether_addr *mac_addr)
 299 {
 300         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 301         struct hns3_hw *hw = &hns->hw;
 302         int ret;
 303
 304         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 305                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 306                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 307                                 NULL, 0);
 308         if (ret) {
 309                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 310                                       mac_addr);
 311                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 312                          mac_str, ret);
 313                 return ret;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int
 320 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 321                             struct rte_ether_addr *mc_addr_set,
 322                             uint32_t nb_mc_addr)
 323 {
 324         struct hns3_adapter *hns = dev->data->dev_private;
 325         struct hns3_hw *hw = &hns->hw;
 326         struct rte_ether_addr *addr;
 327         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 328         int cur_addr_num;
 329         int set_addr_num;
 330         int num;
 331         int ret;
 332         int i;
 333
 334         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 335                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 336                          "invalid. valid range: 0~%d",
 337                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 338                 return -EINVAL;
 339         }
 340
 341         set_addr_num = (int)nb_mc_addr;
 342         for (i = 0; i < set_addr_num; i++) {
 343                 addr = &mc_addr_set[i];
 344                 if (!rte_is_multicast_ether_addr(addr)) {
 345                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 346                                               addr);
 347                         hns3_err(hw,
 348                                  "Failed to set mc mac addr, addr(%s) invalid.",
 349                                  mac_str);
 350                         return -EINVAL;
 351                 }
 352         }
 353         rte_spinlock_lock(&hw->lock);
 354         cur_addr_num = hw->mc_addrs_num;
 355         for (i = 0; i < cur_addr_num; i++) {
 356                 num = cur_addr_num - i - 1;
 357                 addr = &hw->mc_addrs[num];
 358                 ret = hns3vf_remove_mc_mac_addr(hns, addr);
 359                 if (ret) {
 360                         rte_spinlock_unlock(&hw->lock);
 361                         return ret;
 362                 }
 363
 364                 hw->mc_addrs_num--;
 365         }
 366
 367         for (i = 0; i < set_addr_num; i++) {
 368                 addr = &mc_addr_set[i];
 369                 ret = hns3vf_add_mc_mac_addr(hns, addr);
 370                 if (ret) {
 371                         rte_spinlock_unlock(&hw->lock);
 372                         return ret;
 373                 }
 374
 375                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 376                 hw->mc_addrs_num++;
 377         }
 378         rte_spinlock_unlock(&hw->lock);
 379
 380         return 0;
 381 }
 382
 383 static int
 384 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 385 {
 386         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 387         struct hns3_hw *hw = &hns->hw;
 388         struct rte_ether_addr *addr;
 389         int err = 0;
 390         int ret;
 391         int i;
 392
 393         for (i = 0; i < hw->mc_addrs_num; i++) {
 394                 addr = &hw->mc_addrs[i];
 395                 if (!rte_is_multicast_ether_addr(addr))
 396                         continue;
 397                 if (del)
 398                         ret = hns3vf_remove_mc_mac_addr(hns, addr);
 399                 else
 400                         ret = hns3vf_add_mc_mac_addr(hns, addr);
 401                 if (ret) {
 402                         err = ret;
 403                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 404                                               addr);
 405                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 406                                  del ? "Remove" : "Restore", mac_str, ret);
 407                 }
 408         }
 409         return err;
 410 }
 411
 412 static int
 413 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc)
 414 {
 415         struct hns3_mbx_vf_to_pf_cmd *req;
 416         struct hns3_cmd_desc desc;
 417         int ret;
 418
 419         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 420
 421         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 422         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 423         req->msg[1] = en_bc_pmc ? 1 : 0;
 424
 425         ret = hns3_cmd_send(hw, &desc, 1);
 426         if (ret)
 427                 hns3_err(hw, "Set promisc mode fail, status is %d", ret);
 428
 429         return ret;
 430 }
 431
 432 static int
 433 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 434                              bool mmap, enum hns3_ring_type queue_type,
 435                              uint16_t queue_id)
 436 {
 437         struct hns3_vf_bind_vector_msg bind_msg;
 438         const char *op_str;
 439         uint16_t code;
 440         int ret;
 441
 442         memset(&bind_msg, 0, sizeof(bind_msg));
 443         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 444                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 445         bind_msg.vector_id = vector_id;
 446
 447         if (queue_type == HNS3_RING_TYPE_RX)
 448                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 449         else
 450                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 451
 452         bind_msg.param[0].ring_type = queue_type;
 453         bind_msg.ring_num = 1;
 454         bind_msg.param[0].tqp_index = queue_id;
 455         op_str = mmap ? "Map" : "Unmap";
 456         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 457                                 sizeof(bind_msg), false, NULL, 0);
 458         if (ret) {
 459                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 460                          op_str, queue_id, bind_msg.vector_id, ret);
 461                 return ret;
 462         }
 463
 464         return 0;
 465 }
 466
 467 static int
 468 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 469 {
 470         uint8_t vec;
 471         int ret;
 472         int i;
 473
 474         /*
 475          * In hns3 network engine, vector 0 is always the misc interrupt of this
 476          * function, vector 1~N can be used respectively for the queues of the
 477          * function. Tx and Rx queues with the same number share the interrupt
 478          * vector. In the initialization clearing the all hardware mapping
 479          * relationship configurations between queues and interrupt vectors is
 480          * needed, so some error caused by the residual configurations, such as
 481          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 482          * constraints in hns3 hardware engine, we have to implement clearing
 483          * the mapping relationship configurations by binding all queues to the
 484          * last interrupt vector and reserving the last interrupt vector. This
 485          * method results in a decrease of the maximum queues when upper
 486          * applications call the rte_eth_dev_configure API function to enable
 487          * Rx interrupt.
 488          */
 489         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 490         hw->intr_tqps_num = vec - 1; /* the last interrupt is reserved */
 491         for (i = 0; i < hw->intr_tqps_num; i++) {
 492                 /*
 493                  * Set gap limiter and rate limiter configuration of queue's
 494                  * interrupt.
 495                  */
 496                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 497                                        HNS3_TQP_INTR_GL_DEFAULT);
 498                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 499                                        HNS3_TQP_INTR_GL_DEFAULT);
 500                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 501
 502                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 503                                                    HNS3_RING_TYPE_TX, i);
 504                 if (ret) {
 505                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 506                                           "vector: %d, ret=%d", i, vec, ret);
 507                         return ret;
 508                 }
 509
 510                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 511                                                    HNS3_RING_TYPE_RX, i);
 512                 if (ret) {
 513                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 514                                           "vector: %d, ret=%d", i, vec, ret);
 515                         return ret;
 516                 }
 517         }
 518
 519         return 0;
 520 }
 521
 522 static int
 523 hns3vf_dev_configure(struct rte_eth_dev *dev)
 524 {
 525         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 526         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 527         struct rte_eth_conf *conf = &dev->data->dev_conf;
 528         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 529         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 530         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 531         struct rte_eth_rss_conf rss_conf;
 532         uint16_t mtu;
 533         int ret;
 534
 535         /*
 536          * Hardware does not support individually enable/disable/reset the Tx or
 537          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 538          * and Rx queues at the same time. When the numbers of Tx queues
 539          * allocated by upper applications are not equal to the numbers of Rx
 540          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 541          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 542          * these fake queues are imperceptible, and can not be used by upper
 543          * applications.
 544          */
 545         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 546         if (ret) {
 547                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 548                 return ret;
 549         }
 550
 551         hw->adapter_state = HNS3_NIC_CONFIGURING;
 552         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 553                 hns3_err(hw, "setting link speed/duplex not supported");
 554                 ret = -EINVAL;
 555                 goto cfg_err;
 556         }
 557
 558         /* When RSS is not configured, redirect the packet queue 0 */
 559         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 560                 rss_conf = conf->rx_adv_conf.rss_conf;
 561                 if (rss_conf.rss_key == NULL) {
 562                         rss_conf.rss_key = rss_cfg->key;
 563                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 564                 }
 565
 566                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 567                 if (ret)
 568                         goto cfg_err;
 569         }
 570
 571         /*
 572          * If jumbo frames are enabled, MTU needs to be refreshed
 573          * according to the maximum RX packet length.
 574          */
 575         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 576                 /*
 577                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 578                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 579                  * can safely assign to "uint16_t" type variable.
 580                  */
 581                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 582                 ret = hns3vf_dev_mtu_set(dev, mtu);
 583                 if (ret)
 584                         goto cfg_err;
 585                 dev->data->mtu = mtu;
 586         }
 587
 588         ret = hns3vf_dev_configure_vlan(dev);
 589         if (ret)
 590                 goto cfg_err;
 591
 592         hw->adapter_state = HNS3_NIC_CONFIGURED;
 593         return 0;
 594
 595 cfg_err:
 596         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 597         hw->adapter_state = HNS3_NIC_INITIALIZED;
 598
 599         return ret;
 600 }
 601
 602 static int
 603 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 604 {
 605         int ret;
 606
 607         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 608                                 sizeof(mtu), true, NULL, 0);
 609         if (ret)
 610                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 611
 612         return ret;
 613 }
 614
 615 static int
 616 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 617 {
 618         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 619         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 620         int ret;
 621
 622         /*
 623          * The hns3 PF/VF devices on the same port share the hardware MTU
 624          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 625          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 626          * driver, there is no need to stop the port for hns3 VF device, and the
 627          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 628          * PF's MTU.
 629          */
 630         if (rte_atomic16_read(&hw->reset.resetting)) {
 631                 hns3_err(hw, "Failed to set mtu during resetting");
 632                 return -EIO;
 633         }
 634
 635         rte_spinlock_lock(&hw->lock);
 636         ret = hns3vf_config_mtu(hw, mtu);
 637         if (ret) {
 638                 rte_spinlock_unlock(&hw->lock);
 639                 return ret;
 640         }
 641         if (frame_size > RTE_ETHER_MAX_LEN)
 642                 dev->data->dev_conf.rxmode.offloads |=
 643                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 644         else
 645                 dev->data->dev_conf.rxmode.offloads &=
 646                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 647         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 648         rte_spinlock_unlock(&hw->lock);
 649
 650         return 0;
 651 }
 652
 653 static int
 654 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 655 {
 656         struct hns3_adapter *hns = eth_dev->data->dev_private;
 657         struct hns3_hw *hw = &hns->hw;
 658         uint16_t q_num = hw->tqps_num;
 659
 660         /*
 661          * In interrupt mode, 'max_rx_queues' is set based on the number of
 662          * MSI-X interrupt resources of the hardware.
 663          */
 664         if (hw->data->dev_conf.intr_conf.rxq == 1)
 665                 q_num = hw->intr_tqps_num;
 666
 667         info->max_rx_queues = q_num;
 668         info->max_tx_queues = hw->tqps_num;
 669         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 670         info->min_rx_bufsize = hw->rx_buf_len;
 671         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 672         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 673
 674         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 675                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 676                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 677                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 678                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 679                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 680                                  DEV_RX_OFFLOAD_KEEP_CRC |
 681                                  DEV_RX_OFFLOAD_SCATTER |
 682                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 683                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 684                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 685                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 686         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 687         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 688                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 689                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 690                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 691                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 692                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 693                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 694                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 695                                  DEV_TX_OFFLOAD_TCP_TSO |
 696                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 697                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 698                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 699                                  info->tx_queue_offload_capa);
 700
 701         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 702                 .nb_max = HNS3_MAX_RING_DESC,
 703                 .nb_min = HNS3_MIN_RING_DESC,
 704                 .nb_align = HNS3_ALIGN_RING_DESC,
 705         };
 706
 707         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 708                 .nb_max = HNS3_MAX_RING_DESC,
 709                 .nb_min = HNS3_MIN_RING_DESC,
 710                 .nb_align = HNS3_ALIGN_RING_DESC,
 711         };
 712
 713         info->vmdq_queue_num = 0;
 714
 715         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 716         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 717         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 718         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 719         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 720
 721         return 0;
 722 }
 723
 724 static void
 725 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 726 {
 727         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 728 }
 729
 730 static void
 731 hns3vf_disable_irq0(struct hns3_hw *hw)
 732 {
 733         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 734 }
 735
 736 static void
 737 hns3vf_enable_irq0(struct hns3_hw *hw)
 738 {
 739         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 740 }
 741
 742 static enum hns3vf_evt_cause
 743 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 744 {
 745         struct hns3_hw *hw = &hns->hw;
 746         enum hns3vf_evt_cause ret;
 747         uint32_t cmdq_stat_reg;
 748         uint32_t rst_ing_reg;
 749         uint32_t val;
 750
 751         /* Fetch the events from their corresponding regs */
 752         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 753
 754         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 755                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 756                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 757                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 758                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 759                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 760                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 761                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 762                 if (clearval) {
 763                         hw->reset.stats.global_cnt++;
 764                         hns3_warn(hw, "Global reset detected, clear reset status");
 765                 } else {
 766                         hns3_schedule_delayed_reset(hns);
 767                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 768                 }
 769
 770                 ret = HNS3VF_VECTOR0_EVENT_RST;
 771                 goto out;
 772         }
 773
 774         /* Check for vector0 mailbox(=CMDQ RX) event source */
 775         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 776                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 777                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 778                 goto out;
 779         }
 780
 781         val = 0;
 782         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 783 out:
 784         if (clearval)
 785                 *clearval = val;
 786         return ret;
 787 }
 788
 789 static void
 790 hns3vf_interrupt_handler(void *param)
 791 {
 792         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 793         struct hns3_adapter *hns = dev->data->dev_private;
 794         struct hns3_hw *hw = &hns->hw;
 795         enum hns3vf_evt_cause event_cause;
 796         uint32_t clearval;
 797
 798         if (hw->irq_thread_id == 0)
 799                 hw->irq_thread_id = pthread_self();
 800
 801         /* Disable interrupt */
 802         hns3vf_disable_irq0(hw);
 803
 804         /* Read out interrupt causes */
 805         event_cause = hns3vf_check_event_cause(hns, &clearval);
 806
 807         switch (event_cause) {
 808         case HNS3VF_VECTOR0_EVENT_RST:
 809                 hns3_schedule_reset(hns);
 810                 break;
 811         case HNS3VF_VECTOR0_EVENT_MBX:
 812                 hns3_dev_handle_mbx_msg(hw);
 813                 break;
 814         default:
 815                 break;
 816         }
 817
 818         /* Clear interrupt causes */
 819         hns3vf_clear_event_cause(hw, clearval);
 820
 821         /* Enable interrupt */
 822         hns3vf_enable_irq0(hw);
 823 }
 824
 825 static int
 826 hns3vf_check_tqp_info(struct hns3_hw *hw)
 827 {
 828         uint16_t tqps_num;
 829
 830         tqps_num = hw->tqps_num;
 831         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
 832                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
 833                                   "range: 1~%d",
 834                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
 835                 return -EINVAL;
 836         }
 837
 838         if (hw->rx_buf_len == 0)
 839                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
 840         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 841
 842         return 0;
 843 }
 844
 845 static int
 846 hns3vf_get_queue_info(struct hns3_hw *hw)
 847 {
 848 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 849         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 850         int ret;
 851
 852         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 853                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 854         if (ret) {
 855                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 856                 return ret;
 857         }
 858
 859         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 860         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 861         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
 862
 863         return hns3vf_check_tqp_info(hw);
 864 }
 865
 866 static int
 867 hns3vf_get_queue_depth(struct hns3_hw *hw)
 868 {
 869 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
 870         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
 871         int ret;
 872
 873         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
 874                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
 875         if (ret) {
 876                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
 877                              ret);
 878                 return ret;
 879         }
 880
 881         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
 882         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
 883
 884         return 0;
 885 }
 886
 887 static int
 888 hns3vf_get_tc_info(struct hns3_hw *hw)
 889 {
 890         uint8_t resp_msg;
 891         int ret;
 892
 893         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
 894                                 true, &resp_msg, sizeof(resp_msg));
 895         if (ret) {
 896                 hns3_err(hw, "VF request to get TC info from PF failed %d",
 897                          ret);
 898                 return ret;
 899         }
 900
 901         hw->hw_tc_map = resp_msg;
 902
 903         return 0;
 904 }
 905
 906 static int
 907 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
 908 {
 909         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
 910         int ret;
 911
 912         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
 913                                 true, host_mac, RTE_ETHER_ADDR_LEN);
 914         if (ret) {
 915                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
 916                 return ret;
 917         }
 918
 919         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
 920
 921         return 0;
 922 }
 923
 924 static int
 925 hns3vf_get_configuration(struct hns3_hw *hw)
 926 {
 927         int ret;
 928
 929         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
 930
 931         /* Get queue configuration from PF */
 932         ret = hns3vf_get_queue_info(hw);
 933         if (ret)
 934                 return ret;
 935
 936         /* Get queue depth info from PF */
 937         ret = hns3vf_get_queue_depth(hw);
 938         if (ret)
 939                 return ret;
 940
 941         /* Get user defined VF MAC addr from PF */
 942         ret = hns3vf_get_host_mac_addr(hw);
 943         if (ret)
 944                 return ret;
 945
 946         /* Get tc configuration from PF */
 947         return hns3vf_get_tc_info(hw);
 948 }
 949
 950 static int
 951 hns3vf_set_tc_info(struct hns3_adapter *hns)
 952 {
 953         struct hns3_hw *hw = &hns->hw;
 954         uint16_t nb_rx_q = hw->data->nb_rx_queues;
 955         uint16_t nb_tx_q = hw->data->nb_tx_queues;
 956         uint8_t i;
 957
 958         hw->num_tc = 0;
 959         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
 960                 if (hw->hw_tc_map & BIT(i))
 961                         hw->num_tc++;
 962
 963         if (nb_rx_q < hw->num_tc) {
 964                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
 965                          nb_rx_q, hw->num_tc);
 966                 return -EINVAL;
 967         }
 968
 969         if (nb_tx_q < hw->num_tc) {
 970                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
 971                          nb_tx_q, hw->num_tc);
 972                 return -EINVAL;
 973         }
 974
 975         hns3_set_rss_size(hw, nb_rx_q);
 976         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
 977
 978         return 0;
 979 }
 980
 981 static void
 982 hns3vf_request_link_info(struct hns3_hw *hw)
 983 {
 984         uint8_t resp_msg;
 985         int ret;
 986
 987         if (rte_atomic16_read(&hw->reset.resetting))
 988                 return;
 989         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 990                                 &resp_msg, sizeof(resp_msg));
 991         if (ret)
 992                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
 993 }
 994
 995 static int
 996 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 997 {
 998 #define HNS3VF_VLAN_MBX_MSG_LEN 5
 999         struct hns3_hw *hw = &hns->hw;
1000         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1001         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1002         uint8_t is_kill = on ? 0 : 1;
1003
1004         msg_data[0] = is_kill;
1005         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1006         memcpy(&msg_data[3], &proto, sizeof(proto));
1007
1008         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1009                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1010                                  0);
1011 }
1012
1013 static int
1014 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1015 {
1016         struct hns3_adapter *hns = dev->data->dev_private;
1017         struct hns3_hw *hw = &hns->hw;
1018         int ret;
1019
1020         if (rte_atomic16_read(&hw->reset.resetting)) {
1021                 hns3_err(hw,
1022                          "vf set vlan id failed during resetting, vlan_id =%u",
1023                          vlan_id);
1024                 return -EIO;
1025         }
1026         rte_spinlock_lock(&hw->lock);
1027         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1028         rte_spinlock_unlock(&hw->lock);
1029         if (ret)
1030                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1031                          vlan_id, ret);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1038 {
1039         uint8_t msg_data;
1040         int ret;
1041
1042         msg_data = enable ? 1 : 0;
1043         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1044                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1045         if (ret)
1046                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1047
1048         return ret;
1049 }
1050
1051 static int
1052 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1053 {
1054         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1055         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1056         unsigned int tmp_mask;
1057
1058         tmp_mask = (unsigned int)mask;
1059         /* Vlan stripping setting */
1060         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1061                 rte_spinlock_lock(&hw->lock);
1062                 /* Enable or disable VLAN stripping */
1063                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1064                         hns3vf_en_hw_strip_rxvtag(hw, true);
1065                 else
1066                         hns3vf_en_hw_strip_rxvtag(hw, false);
1067                 rte_spinlock_unlock(&hw->lock);
1068         }
1069
1070         return 0;
1071 }
1072
1073 static int
1074 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1075 {
1076         struct rte_vlan_filter_conf *vfc;
1077         struct hns3_hw *hw = &hns->hw;
1078         uint16_t vlan_id;
1079         uint64_t vbit;
1080         uint64_t ids;
1081         int ret = 0;
1082         uint32_t i;
1083
1084         vfc = &hw->data->vlan_filter_conf;
1085         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1086                 if (vfc->ids[i] == 0)
1087                         continue;
1088                 ids = vfc->ids[i];
1089                 while (ids) {
1090                         /*
1091                          * 64 means the num bits of ids, one bit corresponds to
1092                          * one vlan id
1093                          */
1094                         vlan_id = 64 * i;
1095                         /* count trailing zeroes */
1096                         vbit = ~ids & (ids - 1);
1097                         /* clear least significant bit set */
1098                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1099                         for (; vbit;) {
1100                                 vbit >>= 1;
1101                                 vlan_id++;
1102                         }
1103                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1104                         if (ret) {
1105                                 hns3_err(hw,
1106                                          "VF handle vlan table failed, ret =%d, on = %d",
1107                                          ret, on);
1108                                 return ret;
1109                         }
1110                 }
1111         }
1112
1113         return ret;
1114 }
1115
1116 static int
1117 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1118 {
1119         return hns3vf_handle_all_vlan_table(hns, 0);
1120 }
1121
1122 static int
1123 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1124 {
1125         struct hns3_hw *hw = &hns->hw;
1126         struct rte_eth_conf *dev_conf;
1127         bool en;
1128         int ret;
1129
1130         dev_conf = &hw->data->dev_conf;
1131         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1132                                                                    : false;
1133         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1134         if (ret)
1135                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1136                          ret);
1137         return ret;
1138 }
1139
1140 static int
1141 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1142 {
1143         struct hns3_adapter *hns = dev->data->dev_private;
1144         struct rte_eth_dev_data *data = dev->data;
1145         struct hns3_hw *hw = &hns->hw;
1146         int ret;
1147
1148         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1149             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1150             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1151                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1152                               "or hw_vlan_insert_pvid is not support!");
1153         }
1154
1155         /* Apply vlan offload setting */
1156         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1157         if (ret)
1158                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1159
1160         return ret;
1161 }
1162
1163 static int
1164 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1165 {
1166         uint8_t msg_data;
1167
1168         msg_data = alive ? 1 : 0;
1169         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1170                                  sizeof(msg_data), false, NULL, 0);
1171 }
1172
1173 static void
1174 hns3vf_keep_alive_handler(void *param)
1175 {
1176         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1177         struct hns3_adapter *hns = eth_dev->data->dev_private;
1178         struct hns3_hw *hw = &hns->hw;
1179         uint8_t respmsg;
1180         int ret;
1181
1182         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1183                                 false, &respmsg, sizeof(uint8_t));
1184         if (ret)
1185                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1186                          ret);
1187
1188         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1189                           eth_dev);
1190 }
1191
1192 static void
1193 hns3vf_service_handler(void *param)
1194 {
1195         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1196         struct hns3_adapter *hns = eth_dev->data->dev_private;
1197         struct hns3_hw *hw = &hns->hw;
1198
1199         /*
1200          * The query link status and reset processing are executed in the
1201          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1202          * and the query operation will time out after 30ms. In the case of
1203          * multiple PF/VFs, each query failure timeout causes the IMP reset
1204          * interrupt to fail to respond within 100ms.
1205          * Before querying the link status, check whether there is a reset
1206          * pending, and if so, abandon the query.
1207          */
1208         if (!hns3vf_is_reset_pending(hns))
1209                 hns3vf_request_link_info(hw);
1210         else
1211                 hns3_warn(hw, "Cancel the query when reset is pending");
1212
1213         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1214                           eth_dev);
1215 }
1216
1217 static int
1218 hns3_query_vf_resource(struct hns3_hw *hw)
1219 {
1220         struct hns3_vf_res_cmd *req;
1221         struct hns3_cmd_desc desc;
1222         uint16_t num_msi;
1223         int ret;
1224
1225         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1226         ret = hns3_cmd_send(hw, &desc, 1);
1227         if (ret) {
1228                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1229                 return ret;
1230         }
1231
1232         req = (struct hns3_vf_res_cmd *)desc.data;
1233         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1234                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1235         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1236                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1237                          num_msi, HNS3_MIN_VECTOR_NUM);
1238                 return -EINVAL;
1239         }
1240
1241         hw->num_msi = (num_msi > hw->tqps_num + 1) ? hw->tqps_num + 1 : num_msi;
1242
1243         return 0;
1244 }
1245
1246 static int
1247 hns3vf_init_hardware(struct hns3_adapter *hns)
1248 {
1249         struct hns3_hw *hw = &hns->hw;
1250         uint16_t mtu = hw->data->mtu;
1251         int ret;
1252
1253         ret = hns3vf_set_promisc_mode(hw, true);
1254         if (ret)
1255                 return ret;
1256
1257         ret = hns3vf_config_mtu(hw, mtu);
1258         if (ret)
1259                 goto err_init_hardware;
1260
1261         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1262         if (ret) {
1263                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1264                 goto err_init_hardware;
1265         }
1266
1267         ret = hns3_config_gro(hw, false);
1268         if (ret) {
1269                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1270                 goto err_init_hardware;
1271         }
1272
1273         ret = hns3vf_set_alive(hw, true);
1274         if (ret) {
1275                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1276                 goto err_init_hardware;
1277         }
1278
1279         hns3vf_request_link_info(hw);
1280         return 0;
1281
1282 err_init_hardware:
1283         (void)hns3vf_set_promisc_mode(hw, false);
1284         return ret;
1285 }
1286
1287 static int
1288 hns3vf_clear_vport_list(struct hns3_hw *hw)
1289 {
1290         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1291                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1292                                  NULL, 0);
1293 }
1294
1295 static int
1296 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1297 {
1298         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1299         struct hns3_adapter *hns = eth_dev->data->dev_private;
1300         struct hns3_hw *hw = &hns->hw;
1301         int ret;
1302
1303         PMD_INIT_FUNC_TRACE();
1304
1305         /* Get hardware io base address from pcie BAR2 IO space */
1306         hw->io_base = pci_dev->mem_resource[2].addr;
1307
1308         /* Firmware command queue initialize */
1309         ret = hns3_cmd_init_queue(hw);
1310         if (ret) {
1311                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1312                 goto err_cmd_init_queue;
1313         }
1314
1315         /* Firmware command initialize */
1316         ret = hns3_cmd_init(hw);
1317         if (ret) {
1318                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1319                 goto err_cmd_init;
1320         }
1321
1322         /* Get VF resource */
1323         ret = hns3_query_vf_resource(hw);
1324         if (ret)
1325                 goto err_cmd_init;
1326
1327         rte_spinlock_init(&hw->mbx_resp.lock);
1328
1329         hns3vf_clear_event_cause(hw, 0);
1330
1331         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1332                                          hns3vf_interrupt_handler, eth_dev);
1333         if (ret) {
1334                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1335                 goto err_intr_callback_register;
1336         }
1337
1338         /* Enable interrupt */
1339         rte_intr_enable(&pci_dev->intr_handle);
1340         hns3vf_enable_irq0(hw);
1341
1342         /* Get configuration from PF */
1343         ret = hns3vf_get_configuration(hw);
1344         if (ret) {
1345                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1346                 goto err_get_config;
1347         }
1348
1349         /*
1350          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1351          * on the host by "ip link set ..." command. To avoid some incorrect
1352          * scenes, for example, hns3 VF PMD driver fails to receive and send
1353          * packets after user configure the MAC address by using the
1354          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1355          * address strategy as the hns3 kernel ethdev driver in the
1356          * initialization. If user configure a MAC address by the ip command
1357          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1358          * start with a random MAC address in the initialization.
1359          */
1360         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1361         if (ret)
1362                 rte_eth_random_addr(hw->mac.mac_addr);
1363
1364         ret = hns3vf_clear_vport_list(hw);
1365         if (ret) {
1366                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1367                 goto err_get_config;
1368         }
1369
1370         ret = hns3vf_init_hardware(hns);
1371         if (ret)
1372                 goto err_get_config;
1373
1374         hns3_set_default_rss_args(hw);
1375
1376         /*
1377          * In the initialization clearing the all hardware mapping relationship
1378          * configurations between queues and interrupt vectors is needed, so
1379          * some error caused by the residual configurations, such as the
1380          * unexpected interrupt, can be avoid.
1381          */
1382         ret = hns3vf_init_ring_with_vector(hw);
1383         if (ret)
1384                 goto err_get_config;
1385
1386         return 0;
1387
1388 err_get_config:
1389         hns3vf_disable_irq0(hw);
1390         rte_intr_disable(&pci_dev->intr_handle);
1391         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1392                              eth_dev);
1393 err_intr_callback_register:
1394         hns3_cmd_uninit(hw);
1395
1396 err_cmd_init:
1397         hns3_cmd_destroy_queue(hw);
1398
1399 err_cmd_init_queue:
1400         hw->io_base = NULL;
1401
1402         return ret;
1403 }
1404
1405 static void
1406 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1407 {
1408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1409         struct hns3_adapter *hns = eth_dev->data->dev_private;
1410         struct hns3_hw *hw = &hns->hw;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         hns3_rss_uninit(hns);
1415         (void)hns3vf_set_alive(hw, false);
1416         (void)hns3vf_set_promisc_mode(hw, false);
1417         hns3vf_disable_irq0(hw);
1418         rte_intr_disable(&pci_dev->intr_handle);
1419         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1420                              eth_dev);
1421         hns3_cmd_uninit(hw);
1422         hns3_cmd_destroy_queue(hw);
1423         hw->io_base = NULL;
1424 }
1425
1426 static int
1427 hns3vf_do_stop(struct hns3_adapter *hns)
1428 {
1429         struct hns3_hw *hw = &hns->hw;
1430         bool reset_queue;
1431
1432         hw->mac.link_status = ETH_LINK_DOWN;
1433
1434         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1435                 hns3vf_configure_mac_addr(hns, true);
1436                 reset_queue = true;
1437         } else
1438                 reset_queue = false;
1439         return hns3_stop_queues(hns, reset_queue);
1440 }
1441
1442 static void
1443 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1444 {
1445         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1446         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1447         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1448         uint8_t base = 0;
1449         uint8_t vec = 0;
1450         uint16_t q_id;
1451
1452         if (dev->data->dev_conf.intr_conf.rxq == 0)
1453                 return;
1454
1455         /* unmap the ring with vector */
1456         if (rte_intr_allow_others(intr_handle)) {
1457                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1458                 base = RTE_INTR_VEC_RXTX_OFFSET;
1459         }
1460         if (rte_intr_dp_is_en(intr_handle)) {
1461                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1462                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1463                                                            HNS3_RING_TYPE_RX,
1464                                                            q_id);
1465                         if (vec < base + intr_handle->nb_efd - 1)
1466                                 vec++;
1467                 }
1468         }
1469         /* Clean datapath event and queue/vec mapping */
1470         rte_intr_efd_disable(intr_handle);
1471         if (intr_handle->intr_vec) {
1472                 rte_free(intr_handle->intr_vec);
1473                 intr_handle->intr_vec = NULL;
1474         }
1475 }
1476
1477 static void
1478 hns3vf_dev_stop(struct rte_eth_dev *dev)
1479 {
1480         struct hns3_adapter *hns = dev->data->dev_private;
1481         struct hns3_hw *hw = &hns->hw;
1482
1483         PMD_INIT_FUNC_TRACE();
1484
1485         hw->adapter_state = HNS3_NIC_STOPPING;
1486         hns3_set_rxtx_function(dev);
1487         rte_wmb();
1488         /* Disable datapath on secondary process. */
1489         hns3_mp_req_stop_rxtx(dev);
1490         /* Prevent crashes when queues are still in use. */
1491         rte_delay_ms(hw->tqps_num);
1492
1493         rte_spinlock_lock(&hw->lock);
1494         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1495                 hns3vf_do_stop(hns);
1496                 hns3_dev_release_mbufs(hns);
1497                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1498         }
1499         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1500         rte_spinlock_unlock(&hw->lock);
1501
1502         hns3vf_unmap_rx_interrupt(dev);
1503 }
1504
1505 static void
1506 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1507 {
1508         struct hns3_adapter *hns = eth_dev->data->dev_private;
1509         struct hns3_hw *hw = &hns->hw;
1510
1511         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1512                 return;
1513
1514         if (hw->adapter_state == HNS3_NIC_STARTED)
1515                 hns3vf_dev_stop(eth_dev);
1516
1517         hw->adapter_state = HNS3_NIC_CLOSING;
1518         hns3_reset_abort(hns);
1519         hw->adapter_state = HNS3_NIC_CLOSED;
1520         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1521         hns3vf_configure_all_mc_mac_addr(hns, true);
1522         hns3vf_remove_all_vlan_table(hns);
1523         hns3vf_uninit_vf(eth_dev);
1524         hns3_free_all_queues(eth_dev);
1525         rte_free(hw->reset.wait_data);
1526         rte_free(eth_dev->process_private);
1527         eth_dev->process_private = NULL;
1528         hns3_mp_uninit_primary();
1529         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1530 }
1531
1532 static int
1533 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1534                        __rte_unused int wait_to_complete)
1535 {
1536         struct hns3_adapter *hns = eth_dev->data->dev_private;
1537         struct hns3_hw *hw = &hns->hw;
1538         struct hns3_mac *mac = &hw->mac;
1539         struct rte_eth_link new_link;
1540
1541         memset(&new_link, 0, sizeof(new_link));
1542         switch (mac->link_speed) {
1543         case ETH_SPEED_NUM_10M:
1544         case ETH_SPEED_NUM_100M:
1545         case ETH_SPEED_NUM_1G:
1546         case ETH_SPEED_NUM_10G:
1547         case ETH_SPEED_NUM_25G:
1548         case ETH_SPEED_NUM_40G:
1549         case ETH_SPEED_NUM_50G:
1550         case ETH_SPEED_NUM_100G:
1551                 new_link.link_speed = mac->link_speed;
1552                 break;
1553         default:
1554                 new_link.link_speed = ETH_SPEED_NUM_100M;
1555                 break;
1556         }
1557
1558         new_link.link_duplex = mac->link_duplex;
1559         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1560         new_link.link_autoneg =
1561             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1562
1563         return rte_eth_linkstatus_set(eth_dev, &new_link);
1564 }
1565
1566 static int
1567 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1568 {
1569         struct hns3_hw *hw = &hns->hw;
1570         int ret;
1571
1572         ret = hns3vf_set_tc_info(hns);
1573         if (ret)
1574                 return ret;
1575
1576         ret = hns3_start_queues(hns, reset_queue);
1577         if (ret) {
1578                 hns3_err(hw, "Failed to start queues: %d", ret);
1579                 return ret;
1580         }
1581
1582         return 0;
1583 }
1584
1585 static int
1586 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1587 {
1588         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1589         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1590         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1591         uint32_t intr_vector;
1592         uint8_t base = 0;
1593         uint8_t vec = 0;
1594         uint16_t q_id;
1595         int ret;
1596
1597         if (dev->data->dev_conf.intr_conf.rxq == 0)
1598                 return 0;
1599
1600         /* disable uio/vfio intr/eventfd mapping */
1601         rte_intr_disable(intr_handle);
1602
1603         /* check and configure queue intr-vector mapping */
1604         if (rte_intr_cap_multiple(intr_handle) ||
1605             !RTE_ETH_DEV_SRIOV(dev).active) {
1606                 intr_vector = hw->used_rx_queues;
1607                 /* It creates event fd for each intr vector when MSIX is used */
1608                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1609                         return -EINVAL;
1610         }
1611         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1612                 intr_handle->intr_vec =
1613                         rte_zmalloc("intr_vec",
1614                                     hw->used_rx_queues * sizeof(int), 0);
1615                 if (intr_handle->intr_vec == NULL) {
1616                         hns3_err(hw, "Failed to allocate %d rx_queues"
1617                                      " intr_vec", hw->used_rx_queues);
1618                         ret = -ENOMEM;
1619                         goto vf_alloc_intr_vec_error;
1620                 }
1621         }
1622
1623         if (rte_intr_allow_others(intr_handle)) {
1624                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1625                 base = RTE_INTR_VEC_RXTX_OFFSET;
1626         }
1627         if (rte_intr_dp_is_en(intr_handle)) {
1628                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1629                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1630                                                            HNS3_RING_TYPE_RX,
1631                                                            q_id);
1632                         if (ret)
1633                                 goto vf_bind_vector_error;
1634                         intr_handle->intr_vec[q_id] = vec;
1635                         if (vec < base + intr_handle->nb_efd - 1)
1636                                 vec++;
1637                 }
1638         }
1639         rte_intr_enable(intr_handle);
1640         return 0;
1641
1642 vf_bind_vector_error:
1643         rte_intr_efd_disable(intr_handle);
1644         if (intr_handle->intr_vec) {
1645                 free(intr_handle->intr_vec);
1646                 intr_handle->intr_vec = NULL;
1647         }
1648         return ret;
1649 vf_alloc_intr_vec_error:
1650         rte_intr_efd_disable(intr_handle);
1651         return ret;
1652 }
1653
1654 static int
1655 hns3vf_dev_start(struct rte_eth_dev *dev)
1656 {
1657         struct hns3_adapter *hns = dev->data->dev_private;
1658         struct hns3_hw *hw = &hns->hw;
1659         int ret;
1660
1661         PMD_INIT_FUNC_TRACE();
1662         if (rte_atomic16_read(&hw->reset.resetting))
1663                 return -EBUSY;
1664
1665         rte_spinlock_lock(&hw->lock);
1666         hw->adapter_state = HNS3_NIC_STARTING;
1667         ret = hns3vf_do_start(hns, true);
1668         if (ret) {
1669                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1670                 rte_spinlock_unlock(&hw->lock);
1671                 return ret;
1672         }
1673         hw->adapter_state = HNS3_NIC_STARTED;
1674         rte_spinlock_unlock(&hw->lock);
1675
1676         ret = hns3vf_map_rx_interrupt(dev);
1677         if (ret)
1678                 return ret;
1679         hns3_set_rxtx_function(dev);
1680         hns3_mp_req_start_rxtx(dev);
1681         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1682
1683         return ret;
1684 }
1685
1686 static bool
1687 is_vf_reset_done(struct hns3_hw *hw)
1688 {
1689 #define HNS3_FUN_RST_ING_BITS \
1690         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1691          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1692          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1693          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1694
1695         uint32_t val;
1696
1697         if (hw->reset.level == HNS3_VF_RESET) {
1698                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1699                 if (val & HNS3_VF_RST_ING_BIT)
1700                         return false;
1701         } else {
1702                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1703                 if (val & HNS3_FUN_RST_ING_BITS)
1704                         return false;
1705         }
1706         return true;
1707 }
1708
1709 bool
1710 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1711 {
1712         struct hns3_hw *hw = &hns->hw;
1713         enum hns3_reset_level reset;
1714
1715         hns3vf_check_event_cause(hns, NULL);
1716         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1717         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1718                 hns3_warn(hw, "High level reset %d is pending", reset);
1719                 return true;
1720         }
1721         return false;
1722 }
1723
1724 static int
1725 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1726 {
1727         struct hns3_hw *hw = &hns->hw;
1728         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1729         struct timeval tv;
1730
1731         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1732                 /*
1733                  * After vf reset is ready, the PF may not have completed
1734                  * the reset processing. The vf sending mbox to PF may fail
1735                  * during the pf reset, so it is better to add extra delay.
1736                  */
1737                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1738                     hw->reset.level == HNS3_FLR_RESET)
1739                         return 0;
1740                 /* Reset retry process, no need to add extra delay. */
1741                 if (hw->reset.attempts)
1742                         return 0;
1743                 if (wait_data->check_completion == NULL)
1744                         return 0;
1745
1746                 wait_data->check_completion = NULL;
1747                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1748                 wait_data->count = 1;
1749                 wait_data->result = HNS3_WAIT_REQUEST;
1750                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1751                                   wait_data);
1752                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1753                 return -EAGAIN;
1754         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1755                 gettimeofday(&tv, NULL);
1756                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1757                           tv.tv_sec, tv.tv_usec);
1758                 return -ETIME;
1759         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1760                 return -EAGAIN;
1761
1762         wait_data->hns = hns;
1763         wait_data->check_completion = is_vf_reset_done;
1764         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1765                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
1766         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1767         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1768         wait_data->result = HNS3_WAIT_REQUEST;
1769         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1770         return -EAGAIN;
1771 }
1772
1773 static int
1774 hns3vf_prepare_reset(struct hns3_adapter *hns)
1775 {
1776         struct hns3_hw *hw = &hns->hw;
1777         int ret = 0;
1778
1779         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1780                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1781                                         0, true, NULL, 0);
1782         }
1783         rte_atomic16_set(&hw->reset.disable_cmd, 1);
1784
1785         return ret;
1786 }
1787
1788 static int
1789 hns3vf_stop_service(struct hns3_adapter *hns)
1790 {
1791         struct hns3_hw *hw = &hns->hw;
1792         struct rte_eth_dev *eth_dev;
1793
1794         eth_dev = &rte_eth_devices[hw->data->port_id];
1795         if (hw->adapter_state == HNS3_NIC_STARTED)
1796                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1797         hw->mac.link_status = ETH_LINK_DOWN;
1798
1799         hns3_set_rxtx_function(eth_dev);
1800         rte_wmb();
1801         /* Disable datapath on secondary process. */
1802         hns3_mp_req_stop_rxtx(eth_dev);
1803         rte_delay_ms(hw->tqps_num);
1804
1805         rte_spinlock_lock(&hw->lock);
1806         if (hw->adapter_state == HNS3_NIC_STARTED ||
1807             hw->adapter_state == HNS3_NIC_STOPPING) {
1808                 hns3vf_do_stop(hns);
1809                 hw->reset.mbuf_deferred_free = true;
1810         } else
1811                 hw->reset.mbuf_deferred_free = false;
1812
1813         /*
1814          * It is cumbersome for hardware to pick-and-choose entries for deletion
1815          * from table space. Hence, for function reset software intervention is
1816          * required to delete the entries.
1817          */
1818         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
1819                 hns3vf_configure_all_mc_mac_addr(hns, true);
1820         rte_spinlock_unlock(&hw->lock);
1821
1822         return 0;
1823 }
1824
1825 static int
1826 hns3vf_start_service(struct hns3_adapter *hns)
1827 {
1828         struct hns3_hw *hw = &hns->hw;
1829         struct rte_eth_dev *eth_dev;
1830
1831         eth_dev = &rte_eth_devices[hw->data->port_id];
1832         hns3_set_rxtx_function(eth_dev);
1833         hns3_mp_req_start_rxtx(eth_dev);
1834         if (hw->adapter_state == HNS3_NIC_STARTED)
1835                 hns3vf_service_handler(eth_dev);
1836
1837         return 0;
1838 }
1839
1840 static int
1841 hns3vf_check_default_mac_change(struct hns3_hw *hw)
1842 {
1843         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
1844         struct rte_ether_addr *hw_mac;
1845         int ret;
1846
1847         /*
1848          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1849          * on the host by "ip link set ..." command. If the hns3 PF kernel
1850          * ethdev driver sets the MAC address for VF device after the
1851          * initialization of the related VF device, the PF driver will notify
1852          * VF driver to reset VF device to make the new MAC address effective
1853          * immediately. The hns3 VF PMD driver should check whether the MAC
1854          * address has been changed by the PF kernel ethdev driver, if changed
1855          * VF driver should configure hardware using the new MAC address in the
1856          * recovering hardware configuration stage of the reset process.
1857          */
1858         ret = hns3vf_get_host_mac_addr(hw);
1859         if (ret)
1860                 return ret;
1861
1862         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
1863         ret = rte_is_zero_ether_addr(hw_mac);
1864         if (ret) {
1865                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
1866         } else {
1867                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
1868                 if (!ret) {
1869                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
1870                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
1871                                               &hw->data->mac_addrs[0]);
1872                         hns3_warn(hw, "Default MAC address has been changed to:"
1873                                   " %s by the host PF kernel ethdev driver",
1874                                   mac_str);
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int
1882 hns3vf_restore_conf(struct hns3_adapter *hns)
1883 {
1884         struct hns3_hw *hw = &hns->hw;
1885         int ret;
1886
1887         ret = hns3vf_check_default_mac_change(hw);
1888         if (ret)
1889                 return ret;
1890
1891         ret = hns3vf_configure_mac_addr(hns, false);
1892         if (ret)
1893                 return ret;
1894
1895         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
1896         if (ret)
1897                 goto err_mc_mac;
1898
1899         ret = hns3vf_restore_vlan_conf(hns);
1900         if (ret)
1901                 goto err_vlan_table;
1902
1903         if (hw->adapter_state == HNS3_NIC_STARTED) {
1904                 ret = hns3vf_do_start(hns, false);
1905                 if (ret)
1906                         goto err_vlan_table;
1907                 hns3_info(hw, "hns3vf dev restart successful!");
1908         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
1909                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1910         return 0;
1911
1912 err_vlan_table:
1913         hns3vf_configure_all_mc_mac_addr(hns, true);
1914 err_mc_mac:
1915         hns3vf_configure_mac_addr(hns, true);
1916         return ret;
1917 }
1918
1919 static enum hns3_reset_level
1920 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
1921 {
1922         enum hns3_reset_level reset_level;
1923
1924         /* return the highest priority reset level amongst all */
1925         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
1926                 reset_level = HNS3_VF_RESET;
1927         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
1928                 reset_level = HNS3_VF_FULL_RESET;
1929         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
1930                 reset_level = HNS3_VF_PF_FUNC_RESET;
1931         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
1932                 reset_level = HNS3_VF_FUNC_RESET;
1933         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
1934                 reset_level = HNS3_FLR_RESET;
1935         else
1936                 reset_level = HNS3_NONE_RESET;
1937
1938         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
1939                 return HNS3_NONE_RESET;
1940
1941         return reset_level;
1942 }
1943
1944 static void
1945 hns3vf_reset_service(void *param)
1946 {
1947         struct hns3_adapter *hns = (struct hns3_adapter *)param;
1948         struct hns3_hw *hw = &hns->hw;
1949         enum hns3_reset_level reset_level;
1950         struct timeval tv_delta;
1951         struct timeval tv_start;
1952         struct timeval tv;
1953         uint64_t msec;
1954
1955         /*
1956          * The interrupt is not triggered within the delay time.
1957          * The interrupt may have been lost. It is necessary to handle
1958          * the interrupt to recover from the error.
1959          */
1960         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
1961                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
1962                 hns3_err(hw, "Handling interrupts in delayed tasks");
1963                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
1964                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
1965                 if (reset_level == HNS3_NONE_RESET) {
1966                         hns3_err(hw, "No reset level is set, try global reset");
1967                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1968                 }
1969         }
1970         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
1971
1972         /*
1973          * Hardware reset has been notified, we now have to poll & check if
1974          * hardware has actually completed the reset sequence.
1975          */
1976         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
1977         if (reset_level != HNS3_NONE_RESET) {
1978                 gettimeofday(&tv_start, NULL);
1979                 hns3_reset_process(hns, reset_level);
1980                 gettimeofday(&tv, NULL);
1981                 timersub(&tv, &tv_start, &tv_delta);
1982                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
1983                        tv_delta.tv_usec / USEC_PER_MSEC;
1984                 if (msec > HNS3_RESET_PROCESS_MS)
1985                         hns3_err(hw, "%d handle long time delta %" PRIx64
1986                                  " ms time=%ld.%.6ld",
1987                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
1988         }
1989 }
1990
1991 static int
1992 hns3vf_reinit_dev(struct hns3_adapter *hns)
1993 {
1994         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
1995         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1996         struct hns3_hw *hw = &hns->hw;
1997         int ret;
1998
1999         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2000                 rte_intr_disable(&pci_dev->intr_handle);
2001                 hns3vf_set_bus_master(pci_dev, true);
2002         }
2003
2004         /* Firmware command initialize */
2005         ret = hns3_cmd_init(hw);
2006         if (ret) {
2007                 hns3_err(hw, "Failed to init cmd: %d", ret);
2008                 goto err_cmd_init;
2009         }
2010
2011         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2012                 /*
2013                  * UIO enables msix by writing the pcie configuration space
2014                  * vfio_pci enables msix in rte_intr_enable.
2015                  */
2016                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2017                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2018                         if (hns3vf_enable_msix(pci_dev, true))
2019                                 hns3_err(hw, "Failed to enable msix");
2020                 }
2021
2022                 rte_intr_enable(&pci_dev->intr_handle);
2023         }
2024
2025         ret = hns3_reset_all_queues(hns);
2026         if (ret) {
2027                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2028                 goto err_init;
2029         }
2030
2031         ret = hns3vf_init_hardware(hns);
2032         if (ret) {
2033                 hns3_err(hw, "Failed to init hardware: %d", ret);
2034                 goto err_init;
2035         }
2036
2037         return 0;
2038
2039 err_cmd_init:
2040         hns3vf_set_bus_master(pci_dev, false);
2041 err_init:
2042         hns3_cmd_uninit(hw);
2043         return ret;
2044 }
2045
2046 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2047         .dev_start          = hns3vf_dev_start,
2048         .dev_stop           = hns3vf_dev_stop,
2049         .dev_close          = hns3vf_dev_close,
2050         .mtu_set            = hns3vf_dev_mtu_set,
2051         .stats_get          = hns3_stats_get,
2052         .stats_reset        = hns3_stats_reset,
2053         .xstats_get         = hns3_dev_xstats_get,
2054         .xstats_get_names   = hns3_dev_xstats_get_names,
2055         .xstats_reset       = hns3_dev_xstats_reset,
2056         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2057         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2058         .dev_infos_get      = hns3vf_dev_infos_get,
2059         .rx_queue_setup     = hns3_rx_queue_setup,
2060         .tx_queue_setup     = hns3_tx_queue_setup,
2061         .rx_queue_release   = hns3_dev_rx_queue_release,
2062         .tx_queue_release   = hns3_dev_tx_queue_release,
2063         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2064         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2065         .dev_configure      = hns3vf_dev_configure,
2066         .mac_addr_add       = hns3vf_add_mac_addr,
2067         .mac_addr_remove    = hns3vf_remove_mac_addr,
2068         .mac_addr_set       = hns3vf_set_default_mac_addr,
2069         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2070         .link_update        = hns3vf_dev_link_update,
2071         .rss_hash_update    = hns3_dev_rss_hash_update,
2072         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2073         .reta_update        = hns3_dev_rss_reta_update,
2074         .reta_query         = hns3_dev_rss_reta_query,
2075         .filter_ctrl        = hns3_dev_filter_ctrl,
2076         .vlan_filter_set    = hns3vf_vlan_filter_set,
2077         .vlan_offload_set   = hns3vf_vlan_offload_set,
2078         .get_reg            = hns3_get_regs,
2079         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2080 };
2081
2082 static const struct hns3_reset_ops hns3vf_reset_ops = {
2083         .reset_service       = hns3vf_reset_service,
2084         .stop_service        = hns3vf_stop_service,
2085         .prepare_reset       = hns3vf_prepare_reset,
2086         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2087         .reinit_dev          = hns3vf_reinit_dev,
2088         .restore_conf        = hns3vf_restore_conf,
2089         .start_service       = hns3vf_start_service,
2090 };
2091
2092 static int
2093 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2094 {
2095         struct hns3_adapter *hns = eth_dev->data->dev_private;
2096         struct hns3_hw *hw = &hns->hw;
2097         int ret;
2098
2099         PMD_INIT_FUNC_TRACE();
2100
2101         eth_dev->process_private = (struct hns3_process_private *)
2102             rte_zmalloc_socket("hns3_filter_list",
2103                                sizeof(struct hns3_process_private),
2104                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2105         if (eth_dev->process_private == NULL) {
2106                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2107                 return -ENOMEM;
2108         }
2109
2110         /* initialize flow filter lists */
2111         hns3_filterlist_init(eth_dev);
2112
2113         hns3_set_rxtx_function(eth_dev);
2114         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2115         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2116                 hns3_mp_init_secondary();
2117                 hw->secondary_cnt++;
2118                 return 0;
2119         }
2120
2121         hns3_mp_init_primary();
2122
2123         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2124         hns->is_vf = true;
2125         hw->data = eth_dev->data;
2126
2127         ret = hns3_reset_init(hw);
2128         if (ret)
2129                 goto err_init_reset;
2130         hw->reset.ops = &hns3vf_reset_ops;
2131
2132         ret = hns3vf_init_vf(eth_dev);
2133         if (ret) {
2134                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2135                 goto err_init_vf;
2136         }
2137
2138         /* Allocate memory for storing MAC addresses */
2139         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2140                                                sizeof(struct rte_ether_addr) *
2141                                                HNS3_VF_UC_MACADDR_NUM, 0);
2142         if (eth_dev->data->mac_addrs == NULL) {
2143                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2144                              "to store MAC addresses",
2145                              sizeof(struct rte_ether_addr) *
2146                              HNS3_VF_UC_MACADDR_NUM);
2147                 ret = -ENOMEM;
2148                 goto err_rte_zmalloc;
2149         }
2150
2151         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2152                             &eth_dev->data->mac_addrs[0]);
2153         hw->adapter_state = HNS3_NIC_INITIALIZED;
2154         /*
2155          * Pass the information to the rte_eth_dev_close() that it should also
2156          * release the private port resources.
2157          */
2158         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2159
2160         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2161                 hns3_err(hw, "Reschedule reset service after dev_init");
2162                 hns3_schedule_reset(hns);
2163         } else {
2164                 /* IMP will wait ready flag before reset */
2165                 hns3_notify_reset_ready(hw, false);
2166         }
2167         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2168                           eth_dev);
2169         return 0;
2170
2171 err_rte_zmalloc:
2172         hns3vf_uninit_vf(eth_dev);
2173
2174 err_init_vf:
2175         rte_free(hw->reset.wait_data);
2176
2177 err_init_reset:
2178         eth_dev->dev_ops = NULL;
2179         eth_dev->rx_pkt_burst = NULL;
2180         eth_dev->tx_pkt_burst = NULL;
2181         eth_dev->tx_pkt_prepare = NULL;
2182         rte_free(eth_dev->process_private);
2183         eth_dev->process_private = NULL;
2184
2185         return ret;
2186 }
2187
2188 static int
2189 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2190 {
2191         struct hns3_adapter *hns = eth_dev->data->dev_private;
2192         struct hns3_hw *hw = &hns->hw;
2193
2194         PMD_INIT_FUNC_TRACE();
2195
2196         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2197                 return -EPERM;
2198
2199         eth_dev->dev_ops = NULL;
2200         eth_dev->rx_pkt_burst = NULL;
2201         eth_dev->tx_pkt_burst = NULL;
2202         eth_dev->tx_pkt_prepare = NULL;
2203
2204         if (hw->adapter_state < HNS3_NIC_CLOSING)
2205                 hns3vf_dev_close(eth_dev);
2206
2207         hw->adapter_state = HNS3_NIC_REMOVED;
2208         return 0;
2209 }
2210
2211 static int
2212 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2213                      struct rte_pci_device *pci_dev)
2214 {
2215         return rte_eth_dev_pci_generic_probe(pci_dev,
2216                                              sizeof(struct hns3_adapter),
2217                                              hns3vf_dev_init);
2218 }
2219
2220 static int
2221 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2222 {
2223         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2224 }
2225
2226 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2227         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2228         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2229         { .vendor_id = 0, /* sentinel */ },
2230 };
2231
2232 static struct rte_pci_driver rte_hns3vf_pmd = {
2233         .id_table = pci_id_hns3vf_map,
2234         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2235         .probe = eth_hns3vf_pci_probe,
2236         .remove = eth_hns3vf_pci_remove,
2237 };
2238
2239 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2240 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2241 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");