drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 209 {
 210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 211         struct rte_ether_addr *addr;
 212         int ret;
 213         int i;
 214
 215         for (i = 0; i < hw->mc_addrs_num; i++) {
 216                 addr = &hw->mc_addrs[i];
 217                 /* Check if there are duplicate addresses */
 218                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 219                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 220                                               addr);
 221                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 222                                  "(%s) is added by the set_mc_mac_addr_list "
 223                                  "API", mac_str);
 224                         return -EINVAL;
 225                 }
 226         }
 227
 228         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 229         if (ret) {
 230                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 231                                       mac_addr);
 232                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 233                          mac_str, ret);
 234         }
 235         return ret;
 236 }
 237
 238 static int
 239 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 240                     __rte_unused uint32_t idx,
 241                     __rte_unused uint32_t pool)
 242 {
 243         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 245         int ret;
 246
 247         rte_spinlock_lock(&hw->lock);
 248
 249         /*
 250          * In hns3 network engine adding UC and MC mac address with different
 251          * commands with firmware. We need to determine whether the input
 252          * address is a UC or a MC address to call different commands.
 253          * By the way, it is recommended calling the API function named
 254          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 255          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 256          * may affect the specifications of UC mac addresses.
 257          */
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 260         else
 261                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 268                          ret);
 269         }
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 276 {
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         /* index will be checked by upper level rte interface */
 279         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         rte_spinlock_lock(&hw->lock);
 284
 285         if (rte_is_multicast_ether_addr(mac_addr))
 286                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 287         else
 288                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 289
 290         rte_spinlock_unlock(&hw->lock);
 291         if (ret) {
 292                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 293                                       mac_addr);
 294                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 295                          mac_str, ret);
 296         }
 297 }
 298
 299 static int
 300 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 301                             struct rte_ether_addr *mac_addr)
 302 {
 303 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 304         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 305         struct rte_ether_addr *old_addr;
 306         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 308         int ret;
 309
 310         /*
 311          * It has been guaranteed that input parameter named mac_addr is valid
 312          * address in the rte layer of DPDK framework.
 313          */
 314         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 315         rte_spinlock_lock(&hw->lock);
 316         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 317         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 318                RTE_ETHER_ADDR_LEN);
 319
 320         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 321                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 322                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 323         if (ret) {
 324                 /*
 325                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 326                  * driver. When user has configured a MAC address for VF device
 327                  * by "ip link set ..." command based on the PF device, the hns3
 328                  * PF kernel ethdev driver does not allow VF driver to request
 329                  * reconfiguring a different default MAC address, and return
 330                  * -EPREM to VF driver through mailbox.
 331                  */
 332                 if (ret == -EPERM) {
 333                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 334                                               old_addr);
 335                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 336                                   mac_str);
 337                 } else {
 338                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 339                                               mac_addr);
 340                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 341                                  mac_str, ret);
 342                 }
 343         }
 344
 345         rte_ether_addr_copy(mac_addr,
 346                             (struct rte_ether_addr *)hw->mac.mac_addr);
 347         rte_spinlock_unlock(&hw->lock);
 348
 349         return ret;
 350 }
 351
 352 static int
 353 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 354 {
 355         struct hns3_hw *hw = &hns->hw;
 356         struct rte_ether_addr *addr;
 357         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 358         int err = 0;
 359         int ret;
 360         int i;
 361
 362         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 363                 addr = &hw->data->mac_addrs[i];
 364                 if (rte_is_zero_ether_addr(addr))
 365                         continue;
 366                 if (rte_is_multicast_ether_addr(addr))
 367                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 368                               hns3vf_add_mc_mac_addr(hw, addr);
 369                 else
 370                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 371                               hns3vf_add_uc_mac_addr(hw, addr);
 372
 373                 if (ret) {
 374                         err = ret;
 375                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 376                                               addr);
 377                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 378                                  "ret = %d.", del ? "remove" : "restore",
 379                                  mac_str, i, ret);
 380                 }
 381         }
 382         return err;
 383 }
 384
 385 static int
 386 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 387                        struct rte_ether_addr *mac_addr)
 388 {
 389         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 390         int ret;
 391
 392         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 393                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 394                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 395                                 NULL, 0);
 396         if (ret) {
 397                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 398                                       mac_addr);
 399                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 400                          mac_str, ret);
 401         }
 402
 403         return ret;
 404 }
 405
 406 static int
 407 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 408                           struct rte_ether_addr *mac_addr)
 409 {
 410         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 411         int ret;
 412
 413         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 414                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 415                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 416                                 NULL, 0);
 417         if (ret) {
 418                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 419                                       mac_addr);
 420                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 421                          mac_str, ret);
 422         }
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 429                              struct rte_ether_addr *mc_addr_set,
 430                              uint32_t nb_mc_addr)
 431 {
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         struct rte_ether_addr *addr;
 434         uint32_t i;
 435         uint32_t j;
 436
 437         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 438                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 439                          "invalid. valid range: 0~%d",
 440                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 441                 return -EINVAL;
 442         }
 443
 444         /* Check if input mac addresses are valid */
 445         for (i = 0; i < nb_mc_addr; i++) {
 446                 addr = &mc_addr_set[i];
 447                 if (!rte_is_multicast_ether_addr(addr)) {
 448                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 449                                               addr);
 450                         hns3_err(hw,
 451                                  "failed to set mc mac addr, addr(%s) invalid.",
 452                                  mac_str);
 453                         return -EINVAL;
 454                 }
 455
 456                 /* Check if there are duplicate addresses */
 457                 for (j = i + 1; j < nb_mc_addr; j++) {
 458                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 459                                 hns3_ether_format_addr(mac_str,
 460                                                       RTE_ETHER_ADDR_FMT_SIZE,
 461                                                       addr);
 462                                 hns3_err(hw, "failed to set mc mac addr, "
 463                                          "addrs invalid. two same addrs(%s).",
 464                                          mac_str);
 465                                 return -EINVAL;
 466                         }
 467                 }
 468
 469                 /*
 470                  * Check if there are duplicate addresses between mac_addrs
 471                  * and mc_addr_set
 472                  */
 473                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 474                         if (rte_is_same_ether_addr(addr,
 475                                                    &hw->data->mac_addrs[j])) {
 476                                 hns3_ether_format_addr(mac_str,
 477                                                       RTE_ETHER_ADDR_FMT_SIZE,
 478                                                       addr);
 479                                 hns3_err(hw, "failed to set mc mac addr, "
 480                                          "addrs invalid. addrs(%s) has already "
 481                                          "configured in mac_addr add API",
 482                                          mac_str);
 483                                 return -EINVAL;
 484                         }
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int
 492 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 493                             struct rte_ether_addr *mc_addr_set,
 494                             uint32_t nb_mc_addr)
 495 {
 496         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 497         struct rte_ether_addr *addr;
 498         int cur_addr_num;
 499         int set_addr_num;
 500         int num;
 501         int ret;
 502         int i;
 503
 504         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 505         if (ret)
 506                 return ret;
 507
 508         rte_spinlock_lock(&hw->lock);
 509         cur_addr_num = hw->mc_addrs_num;
 510         for (i = 0; i < cur_addr_num; i++) {
 511                 num = cur_addr_num - i - 1;
 512                 addr = &hw->mc_addrs[num];
 513                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 514                 if (ret) {
 515                         rte_spinlock_unlock(&hw->lock);
 516                         return ret;
 517                 }
 518
 519                 hw->mc_addrs_num--;
 520         }
 521
 522         set_addr_num = (int)nb_mc_addr;
 523         for (i = 0; i < set_addr_num; i++) {
 524                 addr = &mc_addr_set[i];
 525                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 526                 if (ret) {
 527                         rte_spinlock_unlock(&hw->lock);
 528                         return ret;
 529                 }
 530
 531                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 532                 hw->mc_addrs_num++;
 533         }
 534         rte_spinlock_unlock(&hw->lock);
 535
 536         return 0;
 537 }
 538
 539 static int
 540 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 541 {
 542         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 543         struct hns3_hw *hw = &hns->hw;
 544         struct rte_ether_addr *addr;
 545         int err = 0;
 546         int ret;
 547         int i;
 548
 549         for (i = 0; i < hw->mc_addrs_num; i++) {
 550                 addr = &hw->mc_addrs[i];
 551                 if (!rte_is_multicast_ether_addr(addr))
 552                         continue;
 553                 if (del)
 554                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 555                 else
 556                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 557                 if (ret) {
 558                         err = ret;
 559                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 560                                               addr);
 561                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 562                                  del ? "Remove" : "Restore", mac_str, ret);
 563                 }
 564         }
 565         return err;
 566 }
 567
 568 static int
 569 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 570                         bool en_uc_pmc, bool en_mc_pmc)
 571 {
 572         struct hns3_mbx_vf_to_pf_cmd *req;
 573         struct hns3_cmd_desc desc;
 574         int ret;
 575
 576         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 577
 578         /*
 579          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 580          * so there are some features for promiscuous/allmulticast mode in hns3
 581          * VF PMD driver as below:
 582          * 1. The promiscuous/allmulticast mode can be configured successfully
 583          *    only based on the trusted VF device. If based on the non trusted
 584          *    VF device, configuring promiscuous/allmulticast mode will fail.
 585          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 586          *    kernel ethdev driver on the host by the following command:
 587          *      "ip link set <eth num> vf <vf id> turst on"
 588          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 589          *    driver can receive the ingress and outgoing traffic. In the words,
 590          *    all the ingress packets, all the packets sent from the PF and
 591          *    other VFs on the same physical port.
 592          * 3. Note: Because of the hardware constraints, By default vlan filter
 593          *    is enabled and couldn't be turned off based on VF device, so vlan
 594          *    filter is still effective even in promiscuous mode. If upper
 595          *    applications don't call rte_eth_dev_vlan_filter API function to
 596          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 597          *    the packets with vlan tag in promiscuoue mode.
 598          */
 599         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 600         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 601         req->msg[1] = en_bc_pmc ? 1 : 0;
 602         req->msg[2] = en_uc_pmc ? 1 : 0;
 603         req->msg[3] = en_mc_pmc ? 1 : 0;
 604         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 605
 606         ret = hns3_cmd_send(hw, &desc, 1);
 607         if (ret)
 608                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 609
 610         return ret;
 611 }
 612
 613 static int
 614 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 615 {
 616         struct hns3_adapter *hns = dev->data->dev_private;
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 621         if (ret)
 622                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 623                         ret);
 624         return ret;
 625 }
 626
 627 static int
 628 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 629 {
 630         bool allmulti = dev->data->all_multicast ? true : false;
 631         struct hns3_adapter *hns = dev->data->dev_private;
 632         struct hns3_hw *hw = &hns->hw;
 633         int ret;
 634
 635         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 636         if (ret)
 637                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 638                         ret);
 639         return ret;
 640 }
 641
 642 static int
 643 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 644 {
 645         struct hns3_adapter *hns = dev->data->dev_private;
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         if (dev->data->promiscuous)
 650                 return 0;
 651
 652         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 653         if (ret)
 654                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 655                         ret);
 656         return ret;
 657 }
 658
 659 static int
 660 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         int ret;
 665
 666         if (dev->data->promiscuous)
 667                 return 0;
 668
 669         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 670         if (ret)
 671                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 672                         ret);
 673         return ret;
 674 }
 675
 676 static int
 677 hns3vf_restore_promisc(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         bool allmulti = hw->data->all_multicast ? true : false;
 681
 682         if (hw->data->promiscuous)
 683                 return hns3vf_set_promisc_mode(hw, true, true, true);
 684
 685         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 686 }
 687
 688 static int
 689 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 690                              bool mmap, enum hns3_ring_type queue_type,
 691                              uint16_t queue_id)
 692 {
 693         struct hns3_vf_bind_vector_msg bind_msg;
 694         const char *op_str;
 695         uint16_t code;
 696         int ret;
 697
 698         memset(&bind_msg, 0, sizeof(bind_msg));
 699         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 700                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 701         bind_msg.vector_id = vector_id;
 702
 703         if (queue_type == HNS3_RING_TYPE_RX)
 704                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 705         else
 706                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 707
 708         bind_msg.param[0].ring_type = queue_type;
 709         bind_msg.ring_num = 1;
 710         bind_msg.param[0].tqp_index = queue_id;
 711         op_str = mmap ? "Map" : "Unmap";
 712         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 713                                 sizeof(bind_msg), false, NULL, 0);
 714         if (ret)
 715                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 716                          op_str, queue_id, bind_msg.vector_id, ret);
 717
 718         return ret;
 719 }
 720
 721 static int
 722 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 723 {
 724         uint16_t vec;
 725         int ret;
 726         int i;
 727
 728         /*
 729          * In hns3 network engine, vector 0 is always the misc interrupt of this
 730          * function, vector 1~N can be used respectively for the queues of the
 731          * function. Tx and Rx queues with the same number share the interrupt
 732          * vector. In the initialization clearing the all hardware mapping
 733          * relationship configurations between queues and interrupt vectors is
 734          * needed, so some error caused by the residual configurations, such as
 735          * the unexpected Tx interrupt, can be avoid.
 736          */
 737         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 738         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 739                 vec = vec - 1; /* the last interrupt is reserved */
 740         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 741         for (i = 0; i < hw->intr_tqps_num; i++) {
 742                 /*
 743                  * Set gap limiter/rate limiter/quanity limiter algorithm
 744                  * configuration for interrupt coalesce of queue's interrupt.
 745                  */
 746                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 747                                        HNS3_TQP_INTR_GL_DEFAULT);
 748                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 749                                        HNS3_TQP_INTR_GL_DEFAULT);
 750                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 751                 /*
 752                  * QL(quantity limiter) is not used currently, just set 0 to
 753                  * close it.
 754                  */
 755                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 756
 757                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 758                                                    HNS3_RING_TYPE_TX, i);
 759                 if (ret) {
 760                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 761                                           "vector: %u, ret=%d", i, vec, ret);
 762                         return ret;
 763                 }
 764
 765                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 766                                                    HNS3_RING_TYPE_RX, i);
 767                 if (ret) {
 768                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 769                                           "vector: %u, ret=%d", i, vec, ret);
 770                         return ret;
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int
 778 hns3vf_dev_configure(struct rte_eth_dev *dev)
 779 {
 780         struct hns3_adapter *hns = dev->data->dev_private;
 781         struct hns3_hw *hw = &hns->hw;
 782         struct rte_eth_conf *conf = &dev->data->dev_conf;
 783         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 784         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 785         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 786         struct rte_eth_rss_conf rss_conf;
 787         bool gro_en;
 788         int ret;
 789
 790         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 791
 792         /*
 793          * Some versions of hardware network engine does not support
 794          * individually enable/disable/reset the Tx or Rx queue. These devices
 795          * must enable/disable/reset Tx and Rx queues at the same time. When the
 796          * numbers of Tx queues allocated by upper applications are not equal to
 797          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 798          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 799          * work as usual. But these fake queues are imperceptible, and can not
 800          * be used by upper applications.
 801          */
 802         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 803         if (ret) {
 804                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 805                 hw->cfg_max_queues = 0;
 806                 return ret;
 807         }
 808
 809         hw->adapter_state = HNS3_NIC_CONFIGURING;
 810         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 811                 hns3_err(hw, "setting link speed/duplex not supported");
 812                 ret = -EINVAL;
 813                 goto cfg_err;
 814         }
 815
 816         /* When RSS is not configured, redirect the packet queue 0 */
 817         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 818                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 819                 hw->rss_dis_flag = false;
 820                 rss_conf = conf->rx_adv_conf.rss_conf;
 821                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 822                 if (ret)
 823                         goto cfg_err;
 824         }
 825
 826         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 827         if (ret != 0)
 828                 goto cfg_err;
 829
 830         ret = hns3vf_dev_configure_vlan(dev);
 831         if (ret)
 832                 goto cfg_err;
 833
 834         /* config hardware GRO */
 835         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 836         ret = hns3_config_gro(hw, gro_en);
 837         if (ret)
 838                 goto cfg_err;
 839
 840         hns3_init_rx_ptype_tble(dev);
 841
 842         hw->adapter_state = HNS3_NIC_CONFIGURED;
 843         return 0;
 844
 845 cfg_err:
 846         hw->cfg_max_queues = 0;
 847         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 848         hw->adapter_state = HNS3_NIC_INITIALIZED;
 849
 850         return ret;
 851 }
 852
 853 static int
 854 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 855 {
 856         int ret;
 857
 858         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 859                                 sizeof(mtu), true, NULL, 0);
 860         if (ret)
 861                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 862
 863         return ret;
 864 }
 865
 866 static int
 867 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 868 {
 869         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 871         int ret;
 872
 873         /*
 874          * The hns3 PF/VF devices on the same port share the hardware MTU
 875          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 876          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 877          * driver, there is no need to stop the port for hns3 VF device, and the
 878          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 879          * PF's MTU.
 880          */
 881         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 882                 hns3_err(hw, "Failed to set mtu during resetting");
 883                 return -EIO;
 884         }
 885
 886         /*
 887          * when Rx of scattered packets is off, we have some possibility of
 888          * using vector Rx process function or simple Rx functions in hns3 PMD
 889          * driver. If the input MTU is increased and the maximum length of
 890          * received packets is greater than the length of a buffer for Rx
 891          * packet, the hardware network engine needs to use multiple BDs and
 892          * buffers to store these packets. This will cause problems when still
 893          * using vector Rx process function or simple Rx function to receiving
 894          * packets. So, when Rx of scattered packets is off and device is
 895          * started, it is not permitted to increase MTU so that the maximum
 896          * length of Rx packets is greater than Rx buffer length.
 897          */
 898         if (dev->data->dev_started && !dev->data->scattered_rx &&
 899             frame_size > hw->rx_buf_len) {
 900                 hns3_err(hw, "failed to set mtu because current is "
 901                         "not scattered rx mode");
 902                 return -EOPNOTSUPP;
 903         }
 904
 905         rte_spinlock_lock(&hw->lock);
 906         ret = hns3vf_config_mtu(hw, mtu);
 907         if (ret) {
 908                 rte_spinlock_unlock(&hw->lock);
 909                 return ret;
 910         }
 911         if (mtu > RTE_ETHER_MTU)
 912                 dev->data->dev_conf.rxmode.offloads |=
 913                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 914         else
 915                 dev->data->dev_conf.rxmode.offloads &=
 916                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 917         rte_spinlock_unlock(&hw->lock);
 918
 919         return 0;
 920 }
 921
 922 static int
 923 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 924 {
 925         struct hns3_adapter *hns = eth_dev->data->dev_private;
 926         struct hns3_hw *hw = &hns->hw;
 927         uint16_t q_num = hw->tqps_num;
 928
 929         /*
 930          * In interrupt mode, 'max_rx_queues' is set based on the number of
 931          * MSI-X interrupt resources of the hardware.
 932          */
 933         if (hw->data->dev_conf.intr_conf.rxq == 1)
 934                 q_num = hw->intr_tqps_num;
 935
 936         info->max_rx_queues = q_num;
 937         info->max_tx_queues = hw->tqps_num;
 938         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 939         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 940         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 941         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 942         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 943
 944         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 945                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 946                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 947                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 948                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 949                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 950                                  DEV_RX_OFFLOAD_SCATTER |
 951                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 952                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 953                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 954                                  DEV_RX_OFFLOAD_RSS_HASH |
 955                                  DEV_RX_OFFLOAD_TCP_LRO);
 956         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 957                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 958                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 959                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 960                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 961                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 962                                  DEV_TX_OFFLOAD_TCP_TSO |
 963                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 964                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 965                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 966                                  DEV_TX_OFFLOAD_MBUF_FAST_FREE |
 967                                  hns3_txvlan_cap_get(hw));
 968
 969         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 970                 info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
 971
 972         if (hns3_dev_get_support(hw, INDEP_TXRX))
 973                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 974                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 975
 976         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 977                 .nb_max = HNS3_MAX_RING_DESC,
 978                 .nb_min = HNS3_MIN_RING_DESC,
 979                 .nb_align = HNS3_ALIGN_RING_DESC,
 980         };
 981
 982         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 983                 .nb_max = HNS3_MAX_RING_DESC,
 984                 .nb_min = HNS3_MIN_RING_DESC,
 985                 .nb_align = HNS3_ALIGN_RING_DESC,
 986                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 987                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 988         };
 989
 990         info->default_rxconf = (struct rte_eth_rxconf) {
 991                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 992                 /*
 993                  * If there are no available Rx buffer descriptors, incoming
 994                  * packets are always dropped by hardware based on hns3 network
 995                  * engine.
 996                  */
 997                 .rx_drop_en = 1,
 998                 .offloads = 0,
 999         };
1000         info->default_txconf = (struct rte_eth_txconf) {
1001                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
1002                 .offloads = 0,
1003         };
1004
1005         info->reta_size = hw->rss_ind_tbl_size;
1006         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1007         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1008
1009         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1010         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1011         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1012         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1013         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1014         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1015
1016         return 0;
1017 }
1018
1019 static void
1020 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1021 {
1022         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1023 }
1024
1025 static void
1026 hns3vf_disable_irq0(struct hns3_hw *hw)
1027 {
1028         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1029 }
1030
1031 static void
1032 hns3vf_enable_irq0(struct hns3_hw *hw)
1033 {
1034         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1035 }
1036
1037 static enum hns3vf_evt_cause
1038 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1039 {
1040         struct hns3_hw *hw = &hns->hw;
1041         enum hns3vf_evt_cause ret;
1042         uint32_t cmdq_stat_reg;
1043         uint32_t rst_ing_reg;
1044         uint32_t val;
1045
1046         /* Fetch the events from their corresponding regs */
1047         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1048         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1049                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1050                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1051                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1052                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1053                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1054                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1055                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1056                 if (clearval) {
1057                         hw->reset.stats.global_cnt++;
1058                         hns3_warn(hw, "Global reset detected, clear reset status");
1059                 } else {
1060                         hns3_schedule_delayed_reset(hns);
1061                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1062                 }
1063
1064                 ret = HNS3VF_VECTOR0_EVENT_RST;
1065                 goto out;
1066         }
1067
1068         /* Check for vector0 mailbox(=CMDQ RX) event source */
1069         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1070                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1071                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1072                 goto out;
1073         }
1074
1075         val = 0;
1076         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1077 out:
1078         if (clearval)
1079                 *clearval = val;
1080         return ret;
1081 }
1082
1083 static void
1084 hns3vf_interrupt_handler(void *param)
1085 {
1086         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1087         struct hns3_adapter *hns = dev->data->dev_private;
1088         struct hns3_hw *hw = &hns->hw;
1089         enum hns3vf_evt_cause event_cause;
1090         uint32_t clearval;
1091
1092         /* Disable interrupt */
1093         hns3vf_disable_irq0(hw);
1094
1095         /* Read out interrupt causes */
1096         event_cause = hns3vf_check_event_cause(hns, &clearval);
1097         /* Clear interrupt causes */
1098         hns3vf_clear_event_cause(hw, clearval);
1099
1100         switch (event_cause) {
1101         case HNS3VF_VECTOR0_EVENT_RST:
1102                 hns3_schedule_reset(hns);
1103                 break;
1104         case HNS3VF_VECTOR0_EVENT_MBX:
1105                 hns3_dev_handle_mbx_msg(hw);
1106                 break;
1107         default:
1108                 break;
1109         }
1110
1111         /* Enable interrupt */
1112         hns3vf_enable_irq0(hw);
1113 }
1114
1115 static void
1116 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1117 {
1118         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1119         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1120         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1121         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1122 }
1123
1124 static void
1125 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1126 {
1127         struct hns3_dev_specs_0_cmd *req0;
1128
1129         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1130
1131         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1132         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1133         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1134         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1135 }
1136
1137 static int
1138 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1139 {
1140         if (hw->rss_ind_tbl_size == 0 ||
1141             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1142                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1143                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1144                               HNS3_RSS_IND_TBL_SIZE_MAX);
1145                 return -EINVAL;
1146         }
1147
1148         return 0;
1149 }
1150
1151 static int
1152 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1153 {
1154         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1155         int ret;
1156         int i;
1157
1158         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1159                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1160                                           true);
1161                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1162         }
1163         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1164
1165         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1166         if (ret)
1167                 return ret;
1168
1169         hns3vf_parse_dev_specifications(hw, desc);
1170
1171         return hns3vf_check_dev_specifications(hw);
1172 }
1173
1174 void
1175 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1176 {
1177         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1178                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1179         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1180         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1181
1182         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1183                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1184                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1185 }
1186
1187 static void
1188 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1189 {
1190 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1191
1192         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1193         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1194         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1195         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1196         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1197
1198         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1199                          __ATOMIC_RELEASE);
1200
1201         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1202                                 NULL, 0);
1203
1204         while (remain_ms > 0) {
1205                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1206                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1207                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1208                         break;
1209                 remain_ms--;
1210         }
1211
1212         /*
1213          * When exit above loop, the pf_push_lsc_cap could be one of the three
1214          * state: unknown (means pf not ack), not_supported, supported.
1215          * Here config it as 'not_supported' when it's 'unknown' state.
1216          */
1217         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1218                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1219
1220         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1221                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1222                 hns3_info(hw, "detect PF support push link status change!");
1223         } else {
1224                 /*
1225                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1226                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1227                  * the RTE_ETH_DEV_INTR_LSC capability.
1228                  */
1229                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1230         }
1231 }
1232
1233 static int
1234 hns3vf_get_capability(struct hns3_hw *hw)
1235 {
1236         struct rte_pci_device *pci_dev;
1237         struct rte_eth_dev *eth_dev;
1238         uint8_t revision;
1239         int ret;
1240
1241         eth_dev = &rte_eth_devices[hw->data->port_id];
1242         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1243
1244         /* Get PCI revision id */
1245         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1246                                   HNS3_PCI_REVISION_ID);
1247         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1248                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1249                              ret);
1250                 return -EIO;
1251         }
1252         hw->revision = revision;
1253
1254         if (revision < PCI_REVISION_ID_HIP09_A) {
1255                 hns3vf_set_default_dev_specifications(hw);
1256                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1257                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1258                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1259                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1260                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1261                 hw->rss_info.ipv6_sctp_offload_supported = false;
1262                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1263                 return 0;
1264         }
1265
1266         ret = hns3vf_query_dev_specifications(hw);
1267         if (ret) {
1268                 PMD_INIT_LOG(ERR,
1269                              "failed to query dev specifications, ret = %d",
1270                              ret);
1271                 return ret;
1272         }
1273
1274         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1275         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1276         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1277         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1278         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1279         hw->rss_info.ipv6_sctp_offload_supported = true;
1280         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1281
1282         return 0;
1283 }
1284
1285 static int
1286 hns3vf_check_tqp_info(struct hns3_hw *hw)
1287 {
1288         if (hw->tqps_num == 0) {
1289                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1290                 return -EINVAL;
1291         }
1292
1293         if (hw->rss_size_max == 0) {
1294                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1295                 return -EINVAL;
1296         }
1297
1298         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1299
1300         return 0;
1301 }
1302
1303 static int
1304 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1305 {
1306         uint8_t resp_msg;
1307         int ret;
1308
1309         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1310                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1311                                 true, &resp_msg, sizeof(resp_msg));
1312         if (ret) {
1313                 if (ret == -ETIME) {
1314                         /*
1315                          * Getting current port based VLAN state from PF driver
1316                          * will not affect VF driver's basic function. Because
1317                          * the VF driver relies on hns3 PF kernel ether driver,
1318                          * to avoid introducing compatibility issues with older
1319                          * version of PF driver, no failure will be returned
1320                          * when the return value is ETIME. This return value has
1321                          * the following scenarios:
1322                          * 1) Firmware didn't return the results in time
1323                          * 2) the result return by firmware is timeout
1324                          * 3) the older version of kernel side PF driver does
1325                          *    not support this mailbox message.
1326                          * For scenarios 1 and 2, it is most likely that a
1327                          * hardware error has occurred, or a hardware reset has
1328                          * occurred. In this case, these errors will be caught
1329                          * by other functions.
1330                          */
1331                         PMD_INIT_LOG(WARNING,
1332                                 "failed to get PVID state for timeout, maybe "
1333                                 "kernel side PF driver doesn't support this "
1334                                 "mailbox message, or firmware didn't respond.");
1335                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1336                 } else {
1337                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1338                                 " ret = %d", ret);
1339                         return ret;
1340                 }
1341         }
1342         hw->port_base_vlan_cfg.state = resp_msg ?
1343                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1344         return 0;
1345 }
1346
1347 static int
1348 hns3vf_get_queue_info(struct hns3_hw *hw)
1349 {
1350 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1351         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1352         int ret;
1353
1354         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1355                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1356         if (ret) {
1357                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1358                 return ret;
1359         }
1360
1361         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1362         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1363
1364         return hns3vf_check_tqp_info(hw);
1365 }
1366
1367 static int
1368 hns3vf_get_queue_depth(struct hns3_hw *hw)
1369 {
1370 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1371         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1372         int ret;
1373
1374         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1375                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1376         if (ret) {
1377                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1378                              ret);
1379                 return ret;
1380         }
1381
1382         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1383         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1384
1385         return 0;
1386 }
1387
1388 static void
1389 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1390 {
1391         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1392                 hns3_set_bit(hw->capability,
1393                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1394 }
1395
1396 static int
1397 hns3vf_get_num_tc(struct hns3_hw *hw)
1398 {
1399         uint8_t num_tc = 0;
1400         uint32_t i;
1401
1402         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1403                 if (hw->hw_tc_map & BIT(i))
1404                         num_tc++;
1405         }
1406         return num_tc;
1407 }
1408
1409 static int
1410 hns3vf_get_basic_info(struct hns3_hw *hw)
1411 {
1412         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1413         struct hns3_basic_info *basic_info;
1414         int ret;
1415
1416         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1417                                 true, resp_msg, sizeof(resp_msg));
1418         if (ret) {
1419                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1420                                 ret);
1421                 return ret;
1422         }
1423
1424         basic_info = (struct hns3_basic_info *)resp_msg;
1425         hw->hw_tc_map = basic_info->hw_tc_map;
1426         hw->num_tc = hns3vf_get_num_tc(hw);
1427         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1428         hns3vf_update_caps(hw, basic_info->caps);
1429
1430         return 0;
1431 }
1432
1433 static int
1434 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1435 {
1436         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1437         int ret;
1438
1439         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1440                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1441         if (ret) {
1442                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1443                 return ret;
1444         }
1445
1446         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1447
1448         return 0;
1449 }
1450
1451 static int
1452 hns3vf_get_configuration(struct hns3_hw *hw)
1453 {
1454         int ret;
1455
1456         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1457         hw->rss_dis_flag = false;
1458
1459         /* Get device capability */
1460         ret = hns3vf_get_capability(hw);
1461         if (ret) {
1462                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1463                 return ret;
1464         }
1465
1466         hns3vf_get_push_lsc_cap(hw);
1467
1468         /* Get basic info from PF */
1469         ret = hns3vf_get_basic_info(hw);
1470         if (ret)
1471                 return ret;
1472
1473         /* Get queue configuration from PF */
1474         ret = hns3vf_get_queue_info(hw);
1475         if (ret)
1476                 return ret;
1477
1478         /* Get queue depth info from PF */
1479         ret = hns3vf_get_queue_depth(hw);
1480         if (ret)
1481                 return ret;
1482
1483         /* Get user defined VF MAC addr from PF */
1484         ret = hns3vf_get_host_mac_addr(hw);
1485         if (ret)
1486                 return ret;
1487
1488         return hns3vf_get_port_base_vlan_filter_state(hw);
1489 }
1490
1491 static int
1492 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1493                             uint16_t nb_tx_q)
1494 {
1495         struct hns3_hw *hw = &hns->hw;
1496
1497         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1498 }
1499
1500 static void
1501 hns3vf_request_link_info(struct hns3_hw *hw)
1502 {
1503         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1504         bool send_req;
1505         int ret;
1506
1507         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1508                 return;
1509
1510         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1511                    vf->req_link_info_cnt > 0;
1512         if (!send_req)
1513                 return;
1514
1515         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1516                                 NULL, 0);
1517         if (ret) {
1518                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1519                 return;
1520         }
1521
1522         if (vf->req_link_info_cnt > 0)
1523                 vf->req_link_info_cnt--;
1524 }
1525
1526 void
1527 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1528                           uint32_t link_speed, uint8_t link_duplex)
1529 {
1530         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1531         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1532         struct hns3_mac *mac = &hw->mac;
1533         int ret;
1534
1535         /*
1536          * PF kernel driver may push link status when VF driver is in resetting,
1537          * driver will stop polling job in this case, after resetting done
1538          * driver will start polling job again.
1539          * When polling job started, driver will get initial link status by
1540          * sending request to PF kernel driver, then could update link status by
1541          * process PF kernel driver's link status mailbox message.
1542          */
1543         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1544                 return;
1545
1546         if (hw->adapter_state != HNS3_NIC_STARTED)
1547                 return;
1548
1549         mac->link_status = link_status;
1550         mac->link_speed = link_speed;
1551         mac->link_duplex = link_duplex;
1552         ret = hns3vf_dev_link_update(dev, 0);
1553         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1554                 hns3_start_report_lse(dev);
1555 }
1556
1557 static int
1558 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1559 {
1560 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1561         struct hns3_hw *hw = &hns->hw;
1562         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1563         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1564         uint8_t is_kill = on ? 0 : 1;
1565
1566         msg_data[0] = is_kill;
1567         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1568         memcpy(&msg_data[3], &proto, sizeof(proto));
1569
1570         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1571                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1572                                  0);
1573 }
1574
1575 static int
1576 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1577 {
1578         struct hns3_adapter *hns = dev->data->dev_private;
1579         struct hns3_hw *hw = &hns->hw;
1580         int ret;
1581
1582         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1583                 hns3_err(hw,
1584                          "vf set vlan id failed during resetting, vlan_id =%u",
1585                          vlan_id);
1586                 return -EIO;
1587         }
1588         rte_spinlock_lock(&hw->lock);
1589         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1590         rte_spinlock_unlock(&hw->lock);
1591         if (ret)
1592                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1593                          vlan_id, ret);
1594
1595         return ret;
1596 }
1597
1598 static int
1599 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1600 {
1601         uint8_t msg_data;
1602         int ret;
1603
1604         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1605                 return 0;
1606
1607         msg_data = enable ? 1 : 0;
1608         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1609                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1610                         sizeof(msg_data), true, NULL, 0);
1611         if (ret)
1612                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1613                                 enable ? "enable" : "disable", ret);
1614
1615         return ret;
1616 }
1617
1618 static int
1619 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1620 {
1621         uint8_t msg_data;
1622         int ret;
1623
1624         msg_data = enable ? 1 : 0;
1625         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1626                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1627         if (ret)
1628                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1629                                 enable ? "enable" : "disable", ret);
1630
1631         return ret;
1632 }
1633
1634 static int
1635 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1636 {
1637         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1638         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1639         unsigned int tmp_mask;
1640         int ret = 0;
1641
1642         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1643                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1644                              "mask = 0x%x", mask);
1645                 return -EIO;
1646         }
1647
1648         tmp_mask = (unsigned int)mask;
1649
1650         if (tmp_mask & ETH_VLAN_FILTER_MASK) {
1651                 rte_spinlock_lock(&hw->lock);
1652                 /* Enable or disable VLAN filter */
1653                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1654                         ret = hns3vf_en_vlan_filter(hw, true);
1655                 else
1656                         ret = hns3vf_en_vlan_filter(hw, false);
1657                 rte_spinlock_unlock(&hw->lock);
1658                 if (ret)
1659                         return ret;
1660         }
1661
1662         /* Vlan stripping setting */
1663         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1664                 rte_spinlock_lock(&hw->lock);
1665                 /* Enable or disable VLAN stripping */
1666                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1667                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1668                 else
1669                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1670                 rte_spinlock_unlock(&hw->lock);
1671         }
1672
1673         return ret;
1674 }
1675
1676 static int
1677 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1678 {
1679         struct rte_vlan_filter_conf *vfc;
1680         struct hns3_hw *hw = &hns->hw;
1681         uint16_t vlan_id;
1682         uint64_t vbit;
1683         uint64_t ids;
1684         int ret = 0;
1685         uint32_t i;
1686
1687         vfc = &hw->data->vlan_filter_conf;
1688         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1689                 if (vfc->ids[i] == 0)
1690                         continue;
1691                 ids = vfc->ids[i];
1692                 while (ids) {
1693                         /*
1694                          * 64 means the num bits of ids, one bit corresponds to
1695                          * one vlan id
1696                          */
1697                         vlan_id = 64 * i;
1698                         /* count trailing zeroes */
1699                         vbit = ~ids & (ids - 1);
1700                         /* clear least significant bit set */
1701                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1702                         for (; vbit;) {
1703                                 vbit >>= 1;
1704                                 vlan_id++;
1705                         }
1706                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1707                         if (ret) {
1708                                 hns3_err(hw,
1709                                          "VF handle vlan table failed, ret =%d, on = %d",
1710                                          ret, on);
1711                                 return ret;
1712                         }
1713                 }
1714         }
1715
1716         return ret;
1717 }
1718
1719 static int
1720 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1721 {
1722         return hns3vf_handle_all_vlan_table(hns, 0);
1723 }
1724
1725 static int
1726 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1727 {
1728         struct hns3_hw *hw = &hns->hw;
1729         struct rte_eth_conf *dev_conf;
1730         bool en;
1731         int ret;
1732
1733         dev_conf = &hw->data->dev_conf;
1734         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1735                                                                    : false;
1736         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1737         if (ret)
1738                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1739                          ret);
1740         return ret;
1741 }
1742
1743 static int
1744 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1745 {
1746         struct hns3_adapter *hns = dev->data->dev_private;
1747         struct rte_eth_dev_data *data = dev->data;
1748         struct hns3_hw *hw = &hns->hw;
1749         int ret;
1750
1751         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1752             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1753             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1754                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1755                               "or hw_vlan_insert_pvid is not support!");
1756         }
1757
1758         /* Apply vlan offload setting */
1759         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK |
1760                                         ETH_VLAN_FILTER_MASK);
1761         if (ret)
1762                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1763
1764         return ret;
1765 }
1766
1767 static int
1768 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1769 {
1770         uint8_t msg_data;
1771
1772         msg_data = alive ? 1 : 0;
1773         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1774                                  sizeof(msg_data), false, NULL, 0);
1775 }
1776
1777 static void
1778 hns3vf_keep_alive_handler(void *param)
1779 {
1780         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1781         struct hns3_adapter *hns = eth_dev->data->dev_private;
1782         struct hns3_hw *hw = &hns->hw;
1783         int ret;
1784
1785         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1786                                 false, NULL, 0);
1787         if (ret)
1788                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1789                          ret);
1790
1791         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1792                           eth_dev);
1793 }
1794
1795 static void
1796 hns3vf_service_handler(void *param)
1797 {
1798         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1799         struct hns3_adapter *hns = eth_dev->data->dev_private;
1800         struct hns3_hw *hw = &hns->hw;
1801
1802         /*
1803          * The query link status and reset processing are executed in the
1804          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1805          * and the query operation will timeout after 30ms. In the case of
1806          * multiple PF/VFs, each query failure timeout causes the IMP reset
1807          * interrupt to fail to respond within 100ms.
1808          * Before querying the link status, check whether there is a reset
1809          * pending, and if so, abandon the query.
1810          */
1811         if (!hns3vf_is_reset_pending(hns))
1812                 hns3vf_request_link_info(hw);
1813         else
1814                 hns3_warn(hw, "Cancel the query when reset is pending");
1815
1816         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1817                           eth_dev);
1818 }
1819
1820 static void
1821 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1822 {
1823 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1824
1825         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1826
1827         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1828                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1829
1830         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1831
1832         hns3vf_service_handler(dev);
1833 }
1834
1835 static void
1836 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1837 {
1838         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1839
1840         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1841
1842         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1843 }
1844
1845 static int
1846 hns3_query_vf_resource(struct hns3_hw *hw)
1847 {
1848         struct hns3_vf_res_cmd *req;
1849         struct hns3_cmd_desc desc;
1850         uint16_t num_msi;
1851         int ret;
1852
1853         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1854         ret = hns3_cmd_send(hw, &desc, 1);
1855         if (ret) {
1856                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1857                 return ret;
1858         }
1859
1860         req = (struct hns3_vf_res_cmd *)desc.data;
1861         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1862                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1863         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1864                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1865                          num_msi, HNS3_MIN_VECTOR_NUM);
1866                 return -EINVAL;
1867         }
1868
1869         hw->num_msi = num_msi;
1870
1871         return 0;
1872 }
1873
1874 static int
1875 hns3vf_init_hardware(struct hns3_adapter *hns)
1876 {
1877         struct hns3_hw *hw = &hns->hw;
1878         uint16_t mtu = hw->data->mtu;
1879         int ret;
1880
1881         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1882         if (ret)
1883                 return ret;
1884
1885         ret = hns3vf_config_mtu(hw, mtu);
1886         if (ret)
1887                 goto err_init_hardware;
1888
1889         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1890         if (ret) {
1891                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1892                 goto err_init_hardware;
1893         }
1894
1895         ret = hns3_config_gro(hw, false);
1896         if (ret) {
1897                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1898                 goto err_init_hardware;
1899         }
1900
1901         /*
1902          * In the initialization clearing the all hardware mapping relationship
1903          * configurations between queues and interrupt vectors is needed, so
1904          * some error caused by the residual configurations, such as the
1905          * unexpected interrupt, can be avoid.
1906          */
1907         ret = hns3vf_init_ring_with_vector(hw);
1908         if (ret) {
1909                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1910                 goto err_init_hardware;
1911         }
1912
1913         return 0;
1914
1915 err_init_hardware:
1916         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1917         return ret;
1918 }
1919
1920 static int
1921 hns3vf_clear_vport_list(struct hns3_hw *hw)
1922 {
1923         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1924                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1925                                  NULL, 0);
1926 }
1927
1928 static int
1929 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1930 {
1931         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1932         struct hns3_adapter *hns = eth_dev->data->dev_private;
1933         struct hns3_hw *hw = &hns->hw;
1934         int ret;
1935
1936         PMD_INIT_FUNC_TRACE();
1937
1938         /* Get hardware io base address from pcie BAR2 IO space */
1939         hw->io_base = pci_dev->mem_resource[2].addr;
1940
1941         /* Firmware command queue initialize */
1942         ret = hns3_cmd_init_queue(hw);
1943         if (ret) {
1944                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1945                 goto err_cmd_init_queue;
1946         }
1947
1948         /* Firmware command initialize */
1949         ret = hns3_cmd_init(hw);
1950         if (ret) {
1951                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1952                 goto err_cmd_init;
1953         }
1954
1955         hns3_tx_push_init(eth_dev);
1956
1957         /* Get VF resource */
1958         ret = hns3_query_vf_resource(hw);
1959         if (ret)
1960                 goto err_cmd_init;
1961
1962         rte_spinlock_init(&hw->mbx_resp.lock);
1963
1964         hns3vf_clear_event_cause(hw, 0);
1965
1966         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1967                                          hns3vf_interrupt_handler, eth_dev);
1968         if (ret) {
1969                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1970                 goto err_intr_callback_register;
1971         }
1972
1973         /* Enable interrupt */
1974         rte_intr_enable(&pci_dev->intr_handle);
1975         hns3vf_enable_irq0(hw);
1976
1977         /* Get configuration from PF */
1978         ret = hns3vf_get_configuration(hw);
1979         if (ret) {
1980                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1981                 goto err_get_config;
1982         }
1983
1984         ret = hns3_tqp_stats_init(hw);
1985         if (ret)
1986                 goto err_get_config;
1987
1988         /* Hardware statistics of imissed registers cleared. */
1989         ret = hns3_update_imissed_stats(hw, true);
1990         if (ret) {
1991                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1992                 goto err_set_tc_queue;
1993         }
1994
1995         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1996         if (ret) {
1997                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1998                 goto err_set_tc_queue;
1999         }
2000
2001         ret = hns3vf_clear_vport_list(hw);
2002         if (ret) {
2003                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
2004                 goto err_set_tc_queue;
2005         }
2006
2007         ret = hns3vf_init_hardware(hns);
2008         if (ret)
2009                 goto err_set_tc_queue;
2010
2011         hns3_rss_set_default_args(hw);
2012
2013         ret = hns3vf_set_alive(hw, true);
2014         if (ret) {
2015                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
2016                 goto err_set_tc_queue;
2017         }
2018
2019         return 0;
2020
2021 err_set_tc_queue:
2022         hns3_tqp_stats_uninit(hw);
2023
2024 err_get_config:
2025         hns3vf_disable_irq0(hw);
2026         rte_intr_disable(&pci_dev->intr_handle);
2027         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2028                              eth_dev);
2029 err_intr_callback_register:
2030 err_cmd_init:
2031         hns3_cmd_uninit(hw);
2032         hns3_cmd_destroy_queue(hw);
2033 err_cmd_init_queue:
2034         hw->io_base = NULL;
2035
2036         return ret;
2037 }
2038
2039 static void
2040 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2041 {
2042         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2043         struct hns3_adapter *hns = eth_dev->data->dev_private;
2044         struct hns3_hw *hw = &hns->hw;
2045
2046         PMD_INIT_FUNC_TRACE();
2047
2048         hns3_rss_uninit(hns);
2049         (void)hns3_config_gro(hw, false);
2050         (void)hns3vf_set_alive(hw, false);
2051         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2052         hns3_flow_uninit(eth_dev);
2053         hns3_tqp_stats_uninit(hw);
2054         hns3vf_disable_irq0(hw);
2055         rte_intr_disable(&pci_dev->intr_handle);
2056         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2057                              eth_dev);
2058         hns3_cmd_uninit(hw);
2059         hns3_cmd_destroy_queue(hw);
2060         hw->io_base = NULL;
2061 }
2062
2063 static int
2064 hns3vf_do_stop(struct hns3_adapter *hns)
2065 {
2066         struct hns3_hw *hw = &hns->hw;
2067         int ret;
2068
2069         hw->mac.link_status = ETH_LINK_DOWN;
2070
2071         /*
2072          * The "hns3vf_do_stop" function will also be called by .stop_service to
2073          * prepare reset. At the time of global or IMP reset, the command cannot
2074          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2075          * accessed during the reset process. So the mbuf can not be released
2076          * during reset and is required to be released after the reset is
2077          * completed.
2078          */
2079         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2080                 hns3_dev_release_mbufs(hns);
2081
2082         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2083                 hns3vf_configure_mac_addr(hns, true);
2084                 ret = hns3_reset_all_tqps(hns);
2085                 if (ret) {
2086                         hns3_err(hw, "failed to reset all queues ret = %d",
2087                                  ret);
2088                         return ret;
2089                 }
2090         }
2091         return 0;
2092 }
2093
2094 static void
2095 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2096 {
2097         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2099         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2100         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2101         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2102         uint16_t q_id;
2103
2104         if (dev->data->dev_conf.intr_conf.rxq == 0)
2105                 return;
2106
2107         /* unmap the ring with vector */
2108         if (rte_intr_allow_others(intr_handle)) {
2109                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2110                 base = RTE_INTR_VEC_RXTX_OFFSET;
2111         }
2112         if (rte_intr_dp_is_en(intr_handle)) {
2113                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2114                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2115                                                            HNS3_RING_TYPE_RX,
2116                                                            q_id);
2117                         if (vec < base + intr_handle->nb_efd - 1)
2118                                 vec++;
2119                 }
2120         }
2121         /* Clean datapath event and queue/vec mapping */
2122         rte_intr_efd_disable(intr_handle);
2123         if (intr_handle->intr_vec) {
2124                 rte_free(intr_handle->intr_vec);
2125                 intr_handle->intr_vec = NULL;
2126         }
2127 }
2128
2129 static int
2130 hns3vf_dev_stop(struct rte_eth_dev *dev)
2131 {
2132         struct hns3_adapter *hns = dev->data->dev_private;
2133         struct hns3_hw *hw = &hns->hw;
2134
2135         PMD_INIT_FUNC_TRACE();
2136         dev->data->dev_started = 0;
2137
2138         hw->adapter_state = HNS3_NIC_STOPPING;
2139         hns3_set_rxtx_function(dev);
2140         rte_wmb();
2141         /* Disable datapath on secondary process. */
2142         hns3_mp_req_stop_rxtx(dev);
2143         /* Prevent crashes when queues are still in use. */
2144         rte_delay_ms(hw->cfg_max_queues);
2145
2146         rte_spinlock_lock(&hw->lock);
2147         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2148                 hns3_stop_tqps(hw);
2149                 hns3vf_do_stop(hns);
2150                 hns3vf_unmap_rx_interrupt(dev);
2151                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2152         }
2153         hns3_rx_scattered_reset(dev);
2154         hns3vf_stop_poll_job(dev);
2155         hns3_stop_report_lse(dev);
2156         rte_spinlock_unlock(&hw->lock);
2157
2158         return 0;
2159 }
2160
2161 static int
2162 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2163 {
2164         struct hns3_adapter *hns = eth_dev->data->dev_private;
2165         struct hns3_hw *hw = &hns->hw;
2166         int ret = 0;
2167
2168         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2169                 return 0;
2170
2171         if (hw->adapter_state == HNS3_NIC_STARTED)
2172                 ret = hns3vf_dev_stop(eth_dev);
2173
2174         hw->adapter_state = HNS3_NIC_CLOSING;
2175         hns3_reset_abort(hns);
2176         hw->adapter_state = HNS3_NIC_CLOSED;
2177         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2178         hns3vf_configure_all_mc_mac_addr(hns, true);
2179         hns3vf_remove_all_vlan_table(hns);
2180         hns3vf_uninit_vf(eth_dev);
2181         hns3_free_all_queues(eth_dev);
2182         rte_free(hw->reset.wait_data);
2183         hns3_mp_uninit_primary();
2184         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2185
2186         return ret;
2187 }
2188
2189 static int
2190 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2191                       size_t fw_size)
2192 {
2193         struct hns3_adapter *hns = eth_dev->data->dev_private;
2194         struct hns3_hw *hw = &hns->hw;
2195         uint32_t version = hw->fw_version;
2196         int ret;
2197
2198         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2199                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2200                                       HNS3_FW_VERSION_BYTE3_S),
2201                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2202                                       HNS3_FW_VERSION_BYTE2_S),
2203                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2204                                       HNS3_FW_VERSION_BYTE1_S),
2205                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2206                                       HNS3_FW_VERSION_BYTE0_S));
2207         if (ret < 0)
2208                 return -EINVAL;
2209
2210         ret += 1; /* add the size of '\0' */
2211         if (fw_size < (size_t)ret)
2212                 return ret;
2213         else
2214                 return 0;
2215 }
2216
2217 static int
2218 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2219                        __rte_unused int wait_to_complete)
2220 {
2221         struct hns3_adapter *hns = eth_dev->data->dev_private;
2222         struct hns3_hw *hw = &hns->hw;
2223         struct hns3_mac *mac = &hw->mac;
2224         struct rte_eth_link new_link;
2225
2226         memset(&new_link, 0, sizeof(new_link));
2227         switch (mac->link_speed) {
2228         case ETH_SPEED_NUM_10M:
2229         case ETH_SPEED_NUM_100M:
2230         case ETH_SPEED_NUM_1G:
2231         case ETH_SPEED_NUM_10G:
2232         case ETH_SPEED_NUM_25G:
2233         case ETH_SPEED_NUM_40G:
2234         case ETH_SPEED_NUM_50G:
2235         case ETH_SPEED_NUM_100G:
2236         case ETH_SPEED_NUM_200G:
2237                 if (mac->link_status)
2238                         new_link.link_speed = mac->link_speed;
2239                 break;
2240         default:
2241                 if (mac->link_status)
2242                         new_link.link_speed = ETH_SPEED_NUM_UNKNOWN;
2243                 break;
2244         }
2245
2246         if (!mac->link_status)
2247                 new_link.link_speed = ETH_SPEED_NUM_NONE;
2248
2249         new_link.link_duplex = mac->link_duplex;
2250         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
2251         new_link.link_autoneg =
2252             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
2253
2254         return rte_eth_linkstatus_set(eth_dev, &new_link);
2255 }
2256
2257 static int
2258 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2259 {
2260         struct hns3_hw *hw = &hns->hw;
2261         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2262         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2263         int ret;
2264
2265         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2266         if (ret)
2267                 return ret;
2268
2269         hns3_enable_rxd_adv_layout(hw);
2270
2271         ret = hns3_init_queues(hns, reset_queue);
2272         if (ret)
2273                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2274
2275         return ret;
2276 }
2277
2278 static int
2279 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2280 {
2281         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2282         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2283         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2285         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2286         uint32_t intr_vector;
2287         uint16_t q_id;
2288         int ret;
2289
2290         /*
2291          * hns3 needs a separate interrupt to be used as event interrupt which
2292          * could not be shared with task queue pair, so KERNEL drivers need
2293          * support multiple interrupt vectors.
2294          */
2295         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2296             !rte_intr_cap_multiple(intr_handle))
2297                 return 0;
2298
2299         rte_intr_disable(intr_handle);
2300         intr_vector = hw->used_rx_queues;
2301         /* It creates event fd for each intr vector when MSIX is used */
2302         if (rte_intr_efd_enable(intr_handle, intr_vector))
2303                 return -EINVAL;
2304
2305         if (intr_handle->intr_vec == NULL) {
2306                 intr_handle->intr_vec =
2307                         rte_zmalloc("intr_vec",
2308                                     hw->used_rx_queues * sizeof(int), 0);
2309                 if (intr_handle->intr_vec == NULL) {
2310                         hns3_err(hw, "Failed to allocate %u rx_queues"
2311                                      " intr_vec", hw->used_rx_queues);
2312                         ret = -ENOMEM;
2313                         goto vf_alloc_intr_vec_error;
2314                 }
2315         }
2316
2317         if (rte_intr_allow_others(intr_handle)) {
2318                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2319                 base = RTE_INTR_VEC_RXTX_OFFSET;
2320         }
2321
2322         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2323                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2324                                                    HNS3_RING_TYPE_RX, q_id);
2325                 if (ret)
2326                         goto vf_bind_vector_error;
2327                 intr_handle->intr_vec[q_id] = vec;
2328                 /*
2329                  * If there are not enough efds (e.g. not enough interrupt),
2330                  * remaining queues will be bond to the last interrupt.
2331                  */
2332                 if (vec < base + intr_handle->nb_efd - 1)
2333                         vec++;
2334         }
2335         rte_intr_enable(intr_handle);
2336         return 0;
2337
2338 vf_bind_vector_error:
2339         rte_free(intr_handle->intr_vec);
2340         intr_handle->intr_vec = NULL;
2341 vf_alloc_intr_vec_error:
2342         rte_intr_efd_disable(intr_handle);
2343         return ret;
2344 }
2345
2346 static int
2347 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2348 {
2349         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2350         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2351         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2352         uint16_t q_id;
2353         int ret;
2354
2355         if (dev->data->dev_conf.intr_conf.rxq == 0)
2356                 return 0;
2357
2358         if (rte_intr_dp_is_en(intr_handle)) {
2359                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2360                         ret = hns3vf_bind_ring_with_vector(hw,
2361                                         intr_handle->intr_vec[q_id], true,
2362                                         HNS3_RING_TYPE_RX, q_id);
2363                         if (ret)
2364                                 return ret;
2365                 }
2366         }
2367
2368         return 0;
2369 }
2370
2371 static void
2372 hns3vf_restore_filter(struct rte_eth_dev *dev)
2373 {
2374         hns3_restore_rss_filter(dev);
2375 }
2376
2377 static int
2378 hns3vf_dev_start(struct rte_eth_dev *dev)
2379 {
2380         struct hns3_adapter *hns = dev->data->dev_private;
2381         struct hns3_hw *hw = &hns->hw;
2382         int ret;
2383
2384         PMD_INIT_FUNC_TRACE();
2385         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2386                 return -EBUSY;
2387
2388         rte_spinlock_lock(&hw->lock);
2389         hw->adapter_state = HNS3_NIC_STARTING;
2390         ret = hns3vf_do_start(hns, true);
2391         if (ret) {
2392                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2393                 rte_spinlock_unlock(&hw->lock);
2394                 return ret;
2395         }
2396         ret = hns3vf_map_rx_interrupt(dev);
2397         if (ret)
2398                 goto map_rx_inter_err;
2399
2400         /*
2401          * There are three register used to control the status of a TQP
2402          * (contains a pair of Tx queue and Rx queue) in the new version network
2403          * engine. One is used to control the enabling of Tx queue, the other is
2404          * used to control the enabling of Rx queue, and the last is the master
2405          * switch used to control the enabling of the tqp. The Tx register and
2406          * TQP register must be enabled at the same time to enable a Tx queue.
2407          * The same applies to the Rx queue. For the older network enginem, this
2408          * function only refresh the enabled flag, and it is used to update the
2409          * status of queue in the dpdk framework.
2410          */
2411         ret = hns3_start_all_txqs(dev);
2412         if (ret)
2413                 goto map_rx_inter_err;
2414
2415         ret = hns3_start_all_rxqs(dev);
2416         if (ret)
2417                 goto start_all_rxqs_fail;
2418
2419         hw->adapter_state = HNS3_NIC_STARTED;
2420         rte_spinlock_unlock(&hw->lock);
2421
2422         hns3_rx_scattered_calc(dev);
2423         hns3_set_rxtx_function(dev);
2424         hns3_mp_req_start_rxtx(dev);
2425
2426         hns3vf_restore_filter(dev);
2427
2428         /* Enable interrupt of all rx queues before enabling queues */
2429         hns3_dev_all_rx_queue_intr_enable(hw, true);
2430         hns3_start_tqps(hw);
2431
2432         if (dev->data->dev_conf.intr_conf.lsc != 0)
2433                 hns3vf_dev_link_update(dev, 0);
2434         hns3vf_start_poll_job(dev);
2435
2436         return ret;
2437
2438 start_all_rxqs_fail:
2439         hns3_stop_all_txqs(dev);
2440 map_rx_inter_err:
2441         (void)hns3vf_do_stop(hns);
2442         hw->adapter_state = HNS3_NIC_CONFIGURED;
2443         rte_spinlock_unlock(&hw->lock);
2444
2445         return ret;
2446 }
2447
2448 static bool
2449 is_vf_reset_done(struct hns3_hw *hw)
2450 {
2451 #define HNS3_FUN_RST_ING_BITS \
2452         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2453          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2454          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2455          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2456
2457         uint32_t val;
2458
2459         if (hw->reset.level == HNS3_VF_RESET) {
2460                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2461                 if (val & HNS3_VF_RST_ING_BIT)
2462                         return false;
2463         } else {
2464                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2465                 if (val & HNS3_FUN_RST_ING_BITS)
2466                         return false;
2467         }
2468         return true;
2469 }
2470
2471 bool
2472 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2473 {
2474         struct hns3_hw *hw = &hns->hw;
2475         enum hns3_reset_level reset;
2476
2477         /*
2478          * According to the protocol of PCIe, FLR to a PF device resets the PF
2479          * state as well as the SR-IOV extended capability including VF Enable
2480          * which means that VFs no longer exist.
2481          *
2482          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2483          * is in FLR stage, the register state of VF device is not reliable,
2484          * so register states detection can not be carried out. In this case,
2485          * we just ignore the register states and return false to indicate that
2486          * there are no other reset states that need to be processed by driver.
2487          */
2488         if (hw->reset.level == HNS3_VF_FULL_RESET)
2489                 return false;
2490
2491         /* Check the registers to confirm whether there is reset pending */
2492         hns3vf_check_event_cause(hns, NULL);
2493         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2494         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2495             hw->reset.level < reset) {
2496                 hns3_warn(hw, "High level reset %d is pending", reset);
2497                 return true;
2498         }
2499         return false;
2500 }
2501
2502 static int
2503 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2504 {
2505         struct hns3_hw *hw = &hns->hw;
2506         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2507         struct timeval tv;
2508
2509         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2510                 /*
2511                  * After vf reset is ready, the PF may not have completed
2512                  * the reset processing. The vf sending mbox to PF may fail
2513                  * during the pf reset, so it is better to add extra delay.
2514                  */
2515                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2516                     hw->reset.level == HNS3_FLR_RESET)
2517                         return 0;
2518                 /* Reset retry process, no need to add extra delay. */
2519                 if (hw->reset.attempts)
2520                         return 0;
2521                 if (wait_data->check_completion == NULL)
2522                         return 0;
2523
2524                 wait_data->check_completion = NULL;
2525                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2526                 wait_data->count = 1;
2527                 wait_data->result = HNS3_WAIT_REQUEST;
2528                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2529                                   wait_data);
2530                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2531                 return -EAGAIN;
2532         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2533                 hns3_clock_gettime(&tv);
2534                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2535                           tv.tv_sec, tv.tv_usec);
2536                 return -ETIME;
2537         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2538                 return -EAGAIN;
2539
2540         wait_data->hns = hns;
2541         wait_data->check_completion = is_vf_reset_done;
2542         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2543                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2544         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2545         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2546         wait_data->result = HNS3_WAIT_REQUEST;
2547         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2548         return -EAGAIN;
2549 }
2550
2551 static int
2552 hns3vf_prepare_reset(struct hns3_adapter *hns)
2553 {
2554         struct hns3_hw *hw = &hns->hw;
2555         int ret;
2556
2557         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2558                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2559                                         0, true, NULL, 0);
2560                 if (ret)
2561                         return ret;
2562         }
2563         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2564
2565         return 0;
2566 }
2567
2568 static int
2569 hns3vf_stop_service(struct hns3_adapter *hns)
2570 {
2571         struct hns3_hw *hw = &hns->hw;
2572         struct rte_eth_dev *eth_dev;
2573
2574         eth_dev = &rte_eth_devices[hw->data->port_id];
2575         if (hw->adapter_state == HNS3_NIC_STARTED) {
2576                 /*
2577                  * Make sure call update link status before hns3vf_stop_poll_job
2578                  * because update link status depend on polling job exist.
2579                  */
2580                 hns3vf_update_link_status(hw, ETH_LINK_DOWN, hw->mac.link_speed,
2581                                           hw->mac.link_duplex);
2582                 hns3vf_stop_poll_job(eth_dev);
2583         }
2584         hw->mac.link_status = ETH_LINK_DOWN;
2585
2586         hns3_set_rxtx_function(eth_dev);
2587         rte_wmb();
2588         /* Disable datapath on secondary process. */
2589         hns3_mp_req_stop_rxtx(eth_dev);
2590         rte_delay_ms(hw->cfg_max_queues);
2591
2592         rte_spinlock_lock(&hw->lock);
2593         if (hw->adapter_state == HNS3_NIC_STARTED ||
2594             hw->adapter_state == HNS3_NIC_STOPPING) {
2595                 hns3_enable_all_queues(hw, false);
2596                 hns3vf_do_stop(hns);
2597                 hw->reset.mbuf_deferred_free = true;
2598         } else
2599                 hw->reset.mbuf_deferred_free = false;
2600
2601         /*
2602          * It is cumbersome for hardware to pick-and-choose entries for deletion
2603          * from table space. Hence, for function reset software intervention is
2604          * required to delete the entries.
2605          */
2606         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2607                 hns3vf_configure_all_mc_mac_addr(hns, true);
2608         rte_spinlock_unlock(&hw->lock);
2609
2610         return 0;
2611 }
2612
2613 static int
2614 hns3vf_start_service(struct hns3_adapter *hns)
2615 {
2616         struct hns3_hw *hw = &hns->hw;
2617         struct rte_eth_dev *eth_dev;
2618
2619         eth_dev = &rte_eth_devices[hw->data->port_id];
2620         hns3_set_rxtx_function(eth_dev);
2621         hns3_mp_req_start_rxtx(eth_dev);
2622         if (hw->adapter_state == HNS3_NIC_STARTED) {
2623                 hns3vf_start_poll_job(eth_dev);
2624
2625                 /* Enable interrupt of all rx queues before enabling queues */
2626                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2627                 /*
2628                  * Enable state of each rxq and txq will be recovered after
2629                  * reset, so we need to restore them before enable all tqps;
2630                  */
2631                 hns3_restore_tqp_enable_state(hw);
2632                 /*
2633                  * When finished the initialization, enable queues to receive
2634                  * and transmit packets.
2635                  */
2636                 hns3_enable_all_queues(hw, true);
2637         }
2638
2639         return 0;
2640 }
2641
2642 static int
2643 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2644 {
2645         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2646         struct rte_ether_addr *hw_mac;
2647         int ret;
2648
2649         /*
2650          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2651          * on the host by "ip link set ..." command. If the hns3 PF kernel
2652          * ethdev driver sets the MAC address for VF device after the
2653          * initialization of the related VF device, the PF driver will notify
2654          * VF driver to reset VF device to make the new MAC address effective
2655          * immediately. The hns3 VF PMD driver should check whether the MAC
2656          * address has been changed by the PF kernel ethdev driver, if changed
2657          * VF driver should configure hardware using the new MAC address in the
2658          * recovering hardware configuration stage of the reset process.
2659          */
2660         ret = hns3vf_get_host_mac_addr(hw);
2661         if (ret)
2662                 return ret;
2663
2664         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2665         ret = rte_is_zero_ether_addr(hw_mac);
2666         if (ret) {
2667                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2668         } else {
2669                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2670                 if (!ret) {
2671                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2672                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2673                                               &hw->data->mac_addrs[0]);
2674                         hns3_warn(hw, "Default MAC address has been changed to:"
2675                                   " %s by the host PF kernel ethdev driver",
2676                                   mac_str);
2677                 }
2678         }
2679
2680         return 0;
2681 }
2682
2683 static int
2684 hns3vf_restore_conf(struct hns3_adapter *hns)
2685 {
2686         struct hns3_hw *hw = &hns->hw;
2687         int ret;
2688
2689         ret = hns3vf_check_default_mac_change(hw);
2690         if (ret)
2691                 return ret;
2692
2693         ret = hns3vf_configure_mac_addr(hns, false);
2694         if (ret)
2695                 return ret;
2696
2697         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2698         if (ret)
2699                 goto err_mc_mac;
2700
2701         ret = hns3vf_restore_promisc(hns);
2702         if (ret)
2703                 goto err_vlan_table;
2704
2705         ret = hns3vf_restore_vlan_conf(hns);
2706         if (ret)
2707                 goto err_vlan_table;
2708
2709         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2710         if (ret)
2711                 goto err_vlan_table;
2712
2713         ret = hns3vf_restore_rx_interrupt(hw);
2714         if (ret)
2715                 goto err_vlan_table;
2716
2717         ret = hns3_restore_gro_conf(hw);
2718         if (ret)
2719                 goto err_vlan_table;
2720
2721         if (hw->adapter_state == HNS3_NIC_STARTED) {
2722                 ret = hns3vf_do_start(hns, false);
2723                 if (ret)
2724                         goto err_vlan_table;
2725                 hns3_info(hw, "hns3vf dev restart successful!");
2726         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2727                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2728
2729         ret = hns3vf_set_alive(hw, true);
2730         if (ret) {
2731                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2732                 goto err_vlan_table;
2733         }
2734
2735         return 0;
2736
2737 err_vlan_table:
2738         hns3vf_configure_all_mc_mac_addr(hns, true);
2739 err_mc_mac:
2740         hns3vf_configure_mac_addr(hns, true);
2741         return ret;
2742 }
2743
2744 static enum hns3_reset_level
2745 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2746 {
2747         enum hns3_reset_level reset_level;
2748
2749         /* return the highest priority reset level amongst all */
2750         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2751                 reset_level = HNS3_VF_RESET;
2752         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2753                 reset_level = HNS3_VF_FULL_RESET;
2754         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2755                 reset_level = HNS3_VF_PF_FUNC_RESET;
2756         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2757                 reset_level = HNS3_VF_FUNC_RESET;
2758         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2759                 reset_level = HNS3_FLR_RESET;
2760         else
2761                 reset_level = HNS3_NONE_RESET;
2762
2763         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2764                 return HNS3_NONE_RESET;
2765
2766         return reset_level;
2767 }
2768
2769 static void
2770 hns3vf_reset_service(void *param)
2771 {
2772         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2773         struct hns3_hw *hw = &hns->hw;
2774         enum hns3_reset_level reset_level;
2775         struct timeval tv_delta;
2776         struct timeval tv_start;
2777         struct timeval tv;
2778         uint64_t msec;
2779
2780         /*
2781          * The interrupt is not triggered within the delay time.
2782          * The interrupt may have been lost. It is necessary to handle
2783          * the interrupt to recover from the error.
2784          */
2785         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2786                             SCHEDULE_DEFERRED) {
2787                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2788                                  __ATOMIC_RELAXED);
2789                 hns3_err(hw, "Handling interrupts in delayed tasks");
2790                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2791                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2792                 if (reset_level == HNS3_NONE_RESET) {
2793                         hns3_err(hw, "No reset level is set, try global reset");
2794                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2795                 }
2796         }
2797         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2798
2799         /*
2800          * Hardware reset has been notified, we now have to poll & check if
2801          * hardware has actually completed the reset sequence.
2802          */
2803         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2804         if (reset_level != HNS3_NONE_RESET) {
2805                 hns3_clock_gettime(&tv_start);
2806                 hns3_reset_process(hns, reset_level);
2807                 hns3_clock_gettime(&tv);
2808                 timersub(&tv, &tv_start, &tv_delta);
2809                 msec = hns3_clock_calctime_ms(&tv_delta);
2810                 if (msec > HNS3_RESET_PROCESS_MS)
2811                         hns3_err(hw, "%d handle long time delta %" PRIu64
2812                                  " ms time=%ld.%.6ld",
2813                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2814         }
2815 }
2816
2817 static int
2818 hns3vf_reinit_dev(struct hns3_adapter *hns)
2819 {
2820         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2821         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2822         struct hns3_hw *hw = &hns->hw;
2823         int ret;
2824
2825         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2826                 rte_intr_disable(&pci_dev->intr_handle);
2827                 ret = hns3vf_set_bus_master(pci_dev, true);
2828                 if (ret < 0) {
2829                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2830                         return ret;
2831                 }
2832         }
2833
2834         /* Firmware command initialize */
2835         ret = hns3_cmd_init(hw);
2836         if (ret) {
2837                 hns3_err(hw, "Failed to init cmd: %d", ret);
2838                 return ret;
2839         }
2840
2841         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2842                 /*
2843                  * UIO enables msix by writing the pcie configuration space
2844                  * vfio_pci enables msix in rte_intr_enable.
2845                  */
2846                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2847                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2848                         if (hns3vf_enable_msix(pci_dev, true))
2849                                 hns3_err(hw, "Failed to enable msix");
2850                 }
2851
2852                 rte_intr_enable(&pci_dev->intr_handle);
2853         }
2854
2855         ret = hns3_reset_all_tqps(hns);
2856         if (ret) {
2857                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2858                 return ret;
2859         }
2860
2861         ret = hns3vf_init_hardware(hns);
2862         if (ret) {
2863                 hns3_err(hw, "Failed to init hardware: %d", ret);
2864                 return ret;
2865         }
2866
2867         return 0;
2868 }
2869
2870 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2871         .dev_configure      = hns3vf_dev_configure,
2872         .dev_start          = hns3vf_dev_start,
2873         .dev_stop           = hns3vf_dev_stop,
2874         .dev_close          = hns3vf_dev_close,
2875         .mtu_set            = hns3vf_dev_mtu_set,
2876         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2877         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2878         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2879         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2880         .stats_get          = hns3_stats_get,
2881         .stats_reset        = hns3_stats_reset,
2882         .xstats_get         = hns3_dev_xstats_get,
2883         .xstats_get_names   = hns3_dev_xstats_get_names,
2884         .xstats_reset       = hns3_dev_xstats_reset,
2885         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2886         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2887         .dev_infos_get      = hns3vf_dev_infos_get,
2888         .fw_version_get     = hns3vf_fw_version_get,
2889         .rx_queue_setup     = hns3_rx_queue_setup,
2890         .tx_queue_setup     = hns3_tx_queue_setup,
2891         .rx_queue_release   = hns3_dev_rx_queue_release,
2892         .tx_queue_release   = hns3_dev_tx_queue_release,
2893         .rx_queue_start     = hns3_dev_rx_queue_start,
2894         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2895         .tx_queue_start     = hns3_dev_tx_queue_start,
2896         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2897         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2898         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2899         .rxq_info_get       = hns3_rxq_info_get,
2900         .txq_info_get       = hns3_txq_info_get,
2901         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2902         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2903         .mac_addr_add       = hns3vf_add_mac_addr,
2904         .mac_addr_remove    = hns3vf_remove_mac_addr,
2905         .mac_addr_set       = hns3vf_set_default_mac_addr,
2906         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2907         .link_update        = hns3vf_dev_link_update,
2908         .rss_hash_update    = hns3_dev_rss_hash_update,
2909         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2910         .reta_update        = hns3_dev_rss_reta_update,
2911         .reta_query         = hns3_dev_rss_reta_query,
2912         .flow_ops_get       = hns3_dev_flow_ops_get,
2913         .vlan_filter_set    = hns3vf_vlan_filter_set,
2914         .vlan_offload_set   = hns3vf_vlan_offload_set,
2915         .get_reg            = hns3_get_regs,
2916         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2917         .tx_done_cleanup    = hns3_tx_done_cleanup,
2918 };
2919
2920 static const struct hns3_reset_ops hns3vf_reset_ops = {
2921         .reset_service       = hns3vf_reset_service,
2922         .stop_service        = hns3vf_stop_service,
2923         .prepare_reset       = hns3vf_prepare_reset,
2924         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2925         .reinit_dev          = hns3vf_reinit_dev,
2926         .restore_conf        = hns3vf_restore_conf,
2927         .start_service       = hns3vf_start_service,
2928 };
2929
2930 static int
2931 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2932 {
2933         struct hns3_adapter *hns = eth_dev->data->dev_private;
2934         struct hns3_hw *hw = &hns->hw;
2935         int ret;
2936
2937         PMD_INIT_FUNC_TRACE();
2938
2939         hns3_flow_init(eth_dev);
2940
2941         hns3_set_rxtx_function(eth_dev);
2942         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2943         eth_dev->rx_queue_count = hns3_rx_queue_count;
2944         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2945                 ret = hns3_mp_init_secondary();
2946                 if (ret) {
2947                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2948                                           "process, ret = %d", ret);
2949                         goto err_mp_init_secondary;
2950                 }
2951                 hw->secondary_cnt++;
2952                 hns3_tx_push_init(eth_dev);
2953                 return 0;
2954         }
2955
2956         ret = hns3_mp_init_primary();
2957         if (ret) {
2958                 PMD_INIT_LOG(ERR,
2959                              "Failed to init for primary process, ret = %d",
2960                              ret);
2961                 goto err_mp_init_primary;
2962         }
2963
2964         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2965         hns->is_vf = true;
2966         hw->data = eth_dev->data;
2967         hns3_parse_devargs(eth_dev);
2968
2969         ret = hns3_reset_init(hw);
2970         if (ret)
2971                 goto err_init_reset;
2972         hw->reset.ops = &hns3vf_reset_ops;
2973
2974         ret = hns3vf_init_vf(eth_dev);
2975         if (ret) {
2976                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2977                 goto err_init_vf;
2978         }
2979
2980         /* Allocate memory for storing MAC addresses */
2981         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2982                                                sizeof(struct rte_ether_addr) *
2983                                                HNS3_VF_UC_MACADDR_NUM, 0);
2984         if (eth_dev->data->mac_addrs == NULL) {
2985                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2986                              "to store MAC addresses",
2987                              sizeof(struct rte_ether_addr) *
2988                              HNS3_VF_UC_MACADDR_NUM);
2989                 ret = -ENOMEM;
2990                 goto err_rte_zmalloc;
2991         }
2992
2993         /*
2994          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2995          * on the host by "ip link set ..." command. To avoid some incorrect
2996          * scenes, for example, hns3 VF PMD driver fails to receive and send
2997          * packets after user configure the MAC address by using the
2998          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2999          * address strategy as the hns3 kernel ethdev driver in the
3000          * initialization. If user configure a MAC address by the ip command
3001          * for VF device, then hns3 VF PMD driver will start with it, otherwise
3002          * start with a random MAC address in the initialization.
3003          */
3004         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
3005                 rte_eth_random_addr(hw->mac.mac_addr);
3006         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
3007                             &eth_dev->data->mac_addrs[0]);
3008
3009         hw->adapter_state = HNS3_NIC_INITIALIZED;
3010
3011         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
3012                             SCHEDULE_PENDING) {
3013                 hns3_err(hw, "Reschedule reset service after dev_init");
3014                 hns3_schedule_reset(hns);
3015         } else {
3016                 /* IMP will wait ready flag before reset */
3017                 hns3_notify_reset_ready(hw, false);
3018         }
3019         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3020                           eth_dev);
3021         return 0;
3022
3023 err_rte_zmalloc:
3024         hns3vf_uninit_vf(eth_dev);
3025
3026 err_init_vf:
3027         rte_free(hw->reset.wait_data);
3028
3029 err_init_reset:
3030         hns3_mp_uninit_primary();
3031
3032 err_mp_init_primary:
3033 err_mp_init_secondary:
3034         eth_dev->dev_ops = NULL;
3035         eth_dev->rx_pkt_burst = NULL;
3036         eth_dev->rx_descriptor_status = NULL;
3037         eth_dev->tx_pkt_burst = NULL;
3038         eth_dev->tx_pkt_prepare = NULL;
3039         eth_dev->tx_descriptor_status = NULL;
3040
3041         return ret;
3042 }
3043
3044 static int
3045 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3046 {
3047         struct hns3_adapter *hns = eth_dev->data->dev_private;
3048         struct hns3_hw *hw = &hns->hw;
3049
3050         PMD_INIT_FUNC_TRACE();
3051
3052         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3053                 return 0;
3054
3055         if (hw->adapter_state < HNS3_NIC_CLOSING)
3056                 hns3vf_dev_close(eth_dev);
3057
3058         hw->adapter_state = HNS3_NIC_REMOVED;
3059         return 0;
3060 }
3061
3062 static int
3063 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3064                      struct rte_pci_device *pci_dev)
3065 {
3066         return rte_eth_dev_pci_generic_probe(pci_dev,
3067                                              sizeof(struct hns3_adapter),
3068                                              hns3vf_dev_init);
3069 }
3070
3071 static int
3072 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3073 {
3074         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3075 }
3076
3077 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3078         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3079         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3080         { .vendor_id = 0, }, /* sentinel */
3081 };
3082
3083 static struct rte_pci_driver rte_hns3vf_pmd = {
3084         .id_table = pci_id_hns3vf_map,
3085         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3086         .probe = eth_hns3vf_pci_probe,
3087         .remove = eth_hns3vf_pci_remove,
3088 };
3089
3090 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3091 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3092 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3093 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3094                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3095                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3096                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> ");