drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 /* set PCI bus mastering */
  63 static void
  64 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  65 {
  66         uint16_t reg;
  67
  68         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  69
  70         if (op)
  71                 /* set the master bit */
  72                 reg |= PCI_COMMAND_MASTER;
  73         else
  74                 reg &= ~(PCI_COMMAND_MASTER);
  75
  76         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  77 }
  78
  79 /**
  80  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  81  * @cap: the capability
  82  *
  83  * Return the address of the given capability within the PCI capability list.
  84  */
  85 static int
  86 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  87 {
  88 #define MAX_PCIE_CAPABILITY 48
  89         uint16_t status;
  90         uint8_t pos;
  91         uint8_t id;
  92         int ttl;
  93
  94         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 100         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 101                 rte_pci_read_config(device, &id, sizeof(id),
 102                                     (pos + PCI_CAP_LIST_ID));
 103
 104                 if (id == 0xFF)
 105                         break;
 106
 107                 if (id == cap)
 108                         return (int)pos;
 109
 110                 rte_pci_read_config(device, &pos, sizeof(pos),
 111                                     (pos + PCI_CAP_LIST_NEXT));
 112         }
 113         return 0;
 114 }
 115
 116 static int
 117 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 118 {
 119         uint16_t control;
 120         int pos;
 121
 122         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 123         if (pos) {
 124                 rte_pci_read_config(device, &control, sizeof(control),
 125                                     (pos + PCI_MSIX_FLAGS));
 126                 if (op)
 127                         control |= PCI_MSIX_FLAGS_ENABLE;
 128                 else
 129                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 130                 rte_pci_write_config(device, &control, sizeof(control),
 131                                      (pos + PCI_MSIX_FLAGS));
 132                 return 0;
 133         }
 134         return -1;
 135 }
 136
 137 static int
 138 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 139                     __attribute__ ((unused)) uint32_t idx,
 140                     __attribute__ ((unused)) uint32_t pool)
 141 {
 142         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 143         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 144         int ret;
 145
 146         rte_spinlock_lock(&hw->lock);
 147         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 148                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 149                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 150         rte_spinlock_unlock(&hw->lock);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "Failed to add mac addr(%s) for vf: %d", mac_str,
 155                          ret);
 156         }
 157
 158         return ret;
 159 }
 160
 161 static void
 162 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 163 {
 164         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 165         /* index will be checked by upper level rte interface */
 166         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 167         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 168         int ret;
 169
 170         rte_spinlock_lock(&hw->lock);
 171         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 172                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 173                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 174                                 NULL, 0);
 175         rte_spinlock_unlock(&hw->lock);
 176         if (ret) {
 177                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 178                                       mac_addr);
 179                 hns3_err(hw, "Failed to remove mac addr(%s) for vf: %d",
 180                          mac_str, ret);
 181         }
 182 }
 183
 184 static int
 185 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 186                             struct rte_ether_addr *mac_addr)
 187 {
 188 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 189         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 190         struct rte_ether_addr *old_addr;
 191         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 192         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 193         int ret;
 194
 195         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
 196                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 197                                       mac_addr);
 198                 hns3_err(hw, "Failed to set mac addr, addr(%s) invalid.",
 199                          mac_str);
 200                 return -EINVAL;
 201         }
 202
 203         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 204         rte_spinlock_lock(&hw->lock);
 205         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 206         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 207                RTE_ETHER_ADDR_LEN);
 208
 209         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 210                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 211                                 HNS3_TWO_ETHER_ADDR_LEN, false, NULL, 0);
 212         if (ret) {
 213                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 214                                       mac_addr);
 215                 hns3_err(hw, "Failed to set mac addr(%s) for vf: %d", mac_str,
 216                          ret);
 217         }
 218
 219         rte_ether_addr_copy(mac_addr,
 220                             (struct rte_ether_addr *)hw->mac.mac_addr);
 221         rte_spinlock_unlock(&hw->lock);
 222
 223         return ret;
 224 }
 225
 226 static int
 227 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 228 {
 229         struct hns3_hw *hw = &hns->hw;
 230         struct rte_ether_addr *addr;
 231         enum hns3_mbx_mac_vlan_subcode opcode;
 232         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 233         int ret = 0;
 234         int i;
 235
 236         if (del)
 237                 opcode = HNS3_MBX_MAC_VLAN_UC_REMOVE;
 238         else
 239                 opcode = HNS3_MBX_MAC_VLAN_UC_ADD;
 240         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 241                 addr = &hw->data->mac_addrs[i];
 242                 if (!rte_is_valid_assigned_ether_addr(addr))
 243                         continue;
 244                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE, addr);
 245                 hns3_dbg(hw, "rm mac addr: %s", mac_str);
 246                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST, opcode,
 247                                         addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 248                                         false, NULL, 0);
 249                 if (ret) {
 250                         hns3_err(hw, "Failed to remove mac addr for vf: %d",
 251                                  ret);
 252                         break;
 253                 }
 254         }
 255         return ret;
 256 }
 257
 258 static int
 259 hns3vf_add_mc_mac_addr(struct hns3_adapter *hns,
 260                        struct rte_ether_addr *mac_addr)
 261 {
 262         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 263         struct hns3_hw *hw = &hns->hw;
 264         int ret;
 265
 266         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 267                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 268                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 269                                 NULL, 0);
 270         if (ret) {
 271                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 272                                       mac_addr);
 273                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 274                          mac_str, ret);
 275                 return ret;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static int
 282 hns3vf_remove_mc_mac_addr(struct hns3_adapter *hns,
 283                           struct rte_ether_addr *mac_addr)
 284 {
 285         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 286         struct hns3_hw *hw = &hns->hw;
 287         int ret;
 288
 289         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 290                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 291                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 292                                 NULL, 0);
 293         if (ret) {
 294                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 295                                       mac_addr);
 296                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 297                          mac_str, ret);
 298                 return ret;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int
 305 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 306                             struct rte_ether_addr *mc_addr_set,
 307                             uint32_t nb_mc_addr)
 308 {
 309         struct hns3_adapter *hns = dev->data->dev_private;
 310         struct hns3_hw *hw = &hns->hw;
 311         struct rte_ether_addr *addr;
 312         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 313         int cur_addr_num;
 314         int set_addr_num;
 315         int num;
 316         int ret;
 317         int i;
 318
 319         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 320                 hns3_err(hw, "Failed to set mc mac addr, nb_mc_addr(%d) "
 321                          "invalid. valid range: 0~%d",
 322                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 323                 return -EINVAL;
 324         }
 325
 326         set_addr_num = (int)nb_mc_addr;
 327         for (i = 0; i < set_addr_num; i++) {
 328                 addr = &mc_addr_set[i];
 329                 if (!rte_is_multicast_ether_addr(addr)) {
 330                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 331                                               addr);
 332                         hns3_err(hw,
 333                                  "Failed to set mc mac addr, addr(%s) invalid.",
 334                                  mac_str);
 335                         return -EINVAL;
 336                 }
 337         }
 338         rte_spinlock_lock(&hw->lock);
 339         cur_addr_num = hw->mc_addrs_num;
 340         for (i = 0; i < cur_addr_num; i++) {
 341                 num = cur_addr_num - i - 1;
 342                 addr = &hw->mc_addrs[num];
 343                 ret = hns3vf_remove_mc_mac_addr(hns, addr);
 344                 if (ret) {
 345                         rte_spinlock_unlock(&hw->lock);
 346                         return ret;
 347                 }
 348
 349                 hw->mc_addrs_num--;
 350         }
 351
 352         for (i = 0; i < set_addr_num; i++) {
 353                 addr = &mc_addr_set[i];
 354                 ret = hns3vf_add_mc_mac_addr(hns, addr);
 355                 if (ret) {
 356                         rte_spinlock_unlock(&hw->lock);
 357                         return ret;
 358                 }
 359
 360                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 361                 hw->mc_addrs_num++;
 362         }
 363         rte_spinlock_unlock(&hw->lock);
 364
 365         return 0;
 366 }
 367
 368 static int
 369 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 370 {
 371         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 372         struct hns3_hw *hw = &hns->hw;
 373         struct rte_ether_addr *addr;
 374         int err = 0;
 375         int ret;
 376         int i;
 377
 378         for (i = 0; i < hw->mc_addrs_num; i++) {
 379                 addr = &hw->mc_addrs[i];
 380                 if (!rte_is_multicast_ether_addr(addr))
 381                         continue;
 382                 if (del)
 383                         ret = hns3vf_remove_mc_mac_addr(hns, addr);
 384                 else
 385                         ret = hns3vf_add_mc_mac_addr(hns, addr);
 386                 if (ret) {
 387                         err = ret;
 388                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 389                                               addr);
 390                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 391                                  del ? "Remove" : "Restore", mac_str, ret);
 392                 }
 393         }
 394         return err;
 395 }
 396
 397 static int
 398 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc)
 399 {
 400         struct hns3_mbx_vf_to_pf_cmd *req;
 401         struct hns3_cmd_desc desc;
 402         int ret;
 403
 404         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 405
 406         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 407         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 408         req->msg[1] = en_bc_pmc ? 1 : 0;
 409
 410         ret = hns3_cmd_send(hw, &desc, 1);
 411         if (ret)
 412                 hns3_err(hw, "Set promisc mode fail, status is %d", ret);
 413
 414         return ret;
 415 }
 416
 417 static int
 418 hns3vf_dev_configure(struct rte_eth_dev *dev)
 419 {
 420         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 421         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 422         struct rte_eth_conf *conf = &dev->data->dev_conf;
 423         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 424         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 425         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 426         struct rte_eth_rss_conf rss_conf;
 427         uint16_t mtu;
 428         int ret;
 429
 430         /*
 431          * Hardware does not support where the number of rx and tx queues is
 432          * not equal in hip08.
 433          */
 434         if (nb_rx_q != nb_tx_q) {
 435                 hns3_err(hw,
 436                          "nb_rx_queues(%u) not equal with nb_tx_queues(%u)! "
 437                          "Hardware does not support this configuration!",
 438                          nb_rx_q, nb_tx_q);
 439                 return -EINVAL;
 440         }
 441
 442         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 443                 hns3_err(hw, "setting link speed/duplex not supported");
 444                 return -EINVAL;
 445         }
 446
 447         hw->adapter_state = HNS3_NIC_CONFIGURING;
 448
 449         /* When RSS is not configured, redirect the packet queue 0 */
 450         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 451                 rss_conf = conf->rx_adv_conf.rss_conf;
 452                 if (rss_conf.rss_key == NULL) {
 453                         rss_conf.rss_key = rss_cfg->key;
 454                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 455                 }
 456
 457                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 458                 if (ret)
 459                         goto cfg_err;
 460         }
 461
 462         /*
 463          * If jumbo frames are enabled, MTU needs to be refreshed
 464          * according to the maximum RX packet length.
 465          */
 466         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 467                 /*
 468                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 469                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 470                  * can safely assign to "uint16_t" type variable.
 471                  */
 472                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 473                 ret = hns3vf_dev_mtu_set(dev, mtu);
 474                 if (ret)
 475                         goto cfg_err;
 476                 dev->data->mtu = mtu;
 477         }
 478
 479         ret = hns3vf_dev_configure_vlan(dev);
 480         if (ret)
 481                 goto cfg_err;
 482
 483         hw->adapter_state = HNS3_NIC_CONFIGURED;
 484         return 0;
 485
 486 cfg_err:
 487         hw->adapter_state = HNS3_NIC_INITIALIZED;
 488         return ret;
 489 }
 490
 491 static int
 492 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 493 {
 494         int ret;
 495
 496         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 497                                 sizeof(mtu), true, NULL, 0);
 498         if (ret)
 499                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 500
 501         return ret;
 502 }
 503
 504 static int
 505 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 506 {
 507         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 508         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 509         int ret;
 510
 511         if (dev->data->dev_started) {
 512                 hns3_err(hw, "Failed to set mtu, port %u must be stopped "
 513                          "before configuration", dev->data->port_id);
 514                 return -EBUSY;
 515         }
 516
 517         if (rte_atomic16_read(&hw->reset.resetting)) {
 518                 hns3_err(hw, "Failed to set mtu during resetting");
 519                 return -EIO;
 520         }
 521
 522         rte_spinlock_lock(&hw->lock);
 523         ret = hns3vf_config_mtu(hw, mtu);
 524         if (ret) {
 525                 rte_spinlock_unlock(&hw->lock);
 526                 return ret;
 527         }
 528         if (frame_size > RTE_ETHER_MAX_LEN)
 529                 dev->data->dev_conf.rxmode.offloads |=
 530                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 531         else
 532                 dev->data->dev_conf.rxmode.offloads &=
 533                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 534         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 535         rte_spinlock_unlock(&hw->lock);
 536
 537         return 0;
 538 }
 539
 540 static int
 541 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 542 {
 543         struct hns3_adapter *hns = eth_dev->data->dev_private;
 544         struct hns3_hw *hw = &hns->hw;
 545
 546         info->max_rx_queues = hw->tqps_num;
 547         info->max_tx_queues = hw->tqps_num;
 548         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 549         info->min_rx_bufsize = hw->rx_buf_len;
 550         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 551         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 552
 553         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 554                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 555                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 556                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 557                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 558                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 559                                  DEV_RX_OFFLOAD_KEEP_CRC |
 560                                  DEV_RX_OFFLOAD_SCATTER |
 561                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 562                                  DEV_RX_OFFLOAD_QINQ_STRIP |
 563                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 564                                  DEV_RX_OFFLOAD_JUMBO_FRAME);
 565         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 566         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 567                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 568                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 569                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 570                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 571                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 572                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 573                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 574                                  info->tx_queue_offload_capa);
 575
 576         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 577                 .nb_max = HNS3_MAX_RING_DESC,
 578                 .nb_min = HNS3_MIN_RING_DESC,
 579                 .nb_align = HNS3_ALIGN_RING_DESC,
 580         };
 581
 582         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 583                 .nb_max = HNS3_MAX_RING_DESC,
 584                 .nb_min = HNS3_MIN_RING_DESC,
 585                 .nb_align = HNS3_ALIGN_RING_DESC,
 586         };
 587
 588         info->vmdq_queue_num = 0;
 589
 590         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 591         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 592         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 593         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 594         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 595
 596         return 0;
 597 }
 598
 599 static void
 600 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 601 {
 602         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 603 }
 604
 605 static void
 606 hns3vf_disable_irq0(struct hns3_hw *hw)
 607 {
 608         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 609 }
 610
 611 static void
 612 hns3vf_enable_irq0(struct hns3_hw *hw)
 613 {
 614         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 615 }
 616
 617 static enum hns3vf_evt_cause
 618 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 619 {
 620         struct hns3_hw *hw = &hns->hw;
 621         enum hns3vf_evt_cause ret;
 622         uint32_t cmdq_stat_reg;
 623         uint32_t rst_ing_reg;
 624         uint32_t val;
 625
 626         /* Fetch the events from their corresponding regs */
 627         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 628
 629         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 630                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 631                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 632                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 633                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 634                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 635                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 636                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 637                 if (clearval) {
 638                         hw->reset.stats.global_cnt++;
 639                         hns3_warn(hw, "Global reset detected, clear reset status");
 640                 } else {
 641                         hns3_schedule_delayed_reset(hns);
 642                         hns3_warn(hw, "Global reset detected, don't clear reset status");
 643                 }
 644
 645                 ret = HNS3VF_VECTOR0_EVENT_RST;
 646                 goto out;
 647         }
 648
 649         /* Check for vector0 mailbox(=CMDQ RX) event source */
 650         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
 651                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
 652                 ret = HNS3VF_VECTOR0_EVENT_MBX;
 653                 goto out;
 654         }
 655
 656         val = 0;
 657         ret = HNS3VF_VECTOR0_EVENT_OTHER;
 658 out:
 659         if (clearval)
 660                 *clearval = val;
 661         return ret;
 662 }
 663
 664 static void
 665 hns3vf_interrupt_handler(void *param)
 666 {
 667         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 668         struct hns3_adapter *hns = dev->data->dev_private;
 669         struct hns3_hw *hw = &hns->hw;
 670         enum hns3vf_evt_cause event_cause;
 671         uint32_t clearval;
 672
 673         if (hw->irq_thread_id == 0)
 674                 hw->irq_thread_id = pthread_self();
 675
 676         /* Disable interrupt */
 677         hns3vf_disable_irq0(hw);
 678
 679         /* Read out interrupt causes */
 680         event_cause = hns3vf_check_event_cause(hns, &clearval);
 681
 682         switch (event_cause) {
 683         case HNS3VF_VECTOR0_EVENT_RST:
 684                 hns3_schedule_reset(hns);
 685                 break;
 686         case HNS3VF_VECTOR0_EVENT_MBX:
 687                 hns3_dev_handle_mbx_msg(hw);
 688                 break;
 689         default:
 690                 break;
 691         }
 692
 693         /* Clear interrupt causes */
 694         hns3vf_clear_event_cause(hw, clearval);
 695
 696         /* Enable interrupt */
 697         hns3vf_enable_irq0(hw);
 698 }
 699
 700 static int
 701 hns3vf_check_tqp_info(struct hns3_hw *hw)
 702 {
 703         uint16_t tqps_num;
 704
 705         tqps_num = hw->tqps_num;
 706         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
 707                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
 708                                   "range: 1~%d",
 709                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
 710                 return -EINVAL;
 711         }
 712
 713         if (hw->rx_buf_len == 0)
 714                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
 715         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
 716
 717         return 0;
 718 }
 719
 720 static int
 721 hns3vf_get_queue_info(struct hns3_hw *hw)
 722 {
 723 #define HNS3VF_TQPS_RSS_INFO_LEN        6
 724         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
 725         int ret;
 726
 727         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
 728                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
 729         if (ret) {
 730                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
 731                 return ret;
 732         }
 733
 734         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
 735         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
 736         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
 737
 738         return hns3vf_check_tqp_info(hw);
 739 }
 740
 741 static int
 742 hns3vf_get_queue_depth(struct hns3_hw *hw)
 743 {
 744 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
 745         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
 746         int ret;
 747
 748         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
 749                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
 750         if (ret) {
 751                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
 752                              ret);
 753                 return ret;
 754         }
 755
 756         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
 757         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
 758
 759         return 0;
 760 }
 761
 762 static int
 763 hns3vf_get_tc_info(struct hns3_hw *hw)
 764 {
 765         uint8_t resp_msg;
 766         int ret;
 767
 768         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
 769                                 true, &resp_msg, sizeof(resp_msg));
 770         if (ret) {
 771                 hns3_err(hw, "VF request to get TC info from PF failed %d",
 772                          ret);
 773                 return ret;
 774         }
 775
 776         hw->hw_tc_map = resp_msg;
 777
 778         return 0;
 779 }
 780
 781 static int
 782 hns3vf_get_configuration(struct hns3_hw *hw)
 783 {
 784         int ret;
 785
 786         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
 787
 788         /* Get queue configuration from PF */
 789         ret = hns3vf_get_queue_info(hw);
 790         if (ret)
 791                 return ret;
 792
 793         /* Get queue depth info from PF */
 794         ret = hns3vf_get_queue_depth(hw);
 795         if (ret)
 796                 return ret;
 797
 798         /* Get tc configuration from PF */
 799         return hns3vf_get_tc_info(hw);
 800 }
 801
 802 static void
 803 hns3vf_set_tc_info(struct hns3_adapter *hns)
 804 {
 805         struct hns3_hw *hw = &hns->hw;
 806         uint16_t nb_rx_q = hw->data->nb_rx_queues;
 807         uint16_t new_tqps;
 808         uint8_t i;
 809
 810         hw->num_tc = 0;
 811         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
 812                 if (hw->hw_tc_map & BIT(i))
 813                         hw->num_tc++;
 814
 815         new_tqps = RTE_MIN(hw->tqps_num, nb_rx_q);
 816         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, new_tqps / hw->num_tc);
 817         hw->alloc_tqps = hw->alloc_rss_size * hw->num_tc;
 818
 819         hns3_tc_queue_mapping_cfg(hw);
 820 }
 821
 822 static void
 823 hns3vf_request_link_info(struct hns3_hw *hw)
 824 {
 825         uint8_t resp_msg;
 826         int ret;
 827
 828         if (rte_atomic16_read(&hw->reset.resetting))
 829                 return;
 830         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
 831                                 &resp_msg, sizeof(resp_msg));
 832         if (ret)
 833                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
 834 }
 835
 836 static int
 837 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
 838 {
 839 #define HNS3VF_VLAN_MBX_MSG_LEN 5
 840         struct hns3_hw *hw = &hns->hw;
 841         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
 842         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
 843         uint8_t is_kill = on ? 0 : 1;
 844
 845         msg_data[0] = is_kill;
 846         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
 847         memcpy(&msg_data[3], &proto, sizeof(proto));
 848
 849         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
 850                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
 851                                  0);
 852 }
 853
 854 static int
 855 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 856 {
 857         struct hns3_adapter *hns = dev->data->dev_private;
 858         struct hns3_hw *hw = &hns->hw;
 859         int ret;
 860
 861         if (rte_atomic16_read(&hw->reset.resetting)) {
 862                 hns3_err(hw,
 863                          "vf set vlan id failed during resetting, vlan_id =%u",
 864                          vlan_id);
 865                 return -EIO;
 866         }
 867         rte_spinlock_lock(&hw->lock);
 868         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
 869         rte_spinlock_unlock(&hw->lock);
 870         if (ret)
 871                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
 872                          vlan_id, ret);
 873
 874         return ret;
 875 }
 876
 877 static int
 878 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
 879 {
 880         uint8_t msg_data;
 881         int ret;
 882
 883         msg_data = enable ? 1 : 0;
 884         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
 885                                 &msg_data, sizeof(msg_data), false, NULL, 0);
 886         if (ret)
 887                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
 888
 889         return ret;
 890 }
 891
 892 static int
 893 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 894 {
 895         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 896         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
 897         unsigned int tmp_mask;
 898
 899         tmp_mask = (unsigned int)mask;
 900         /* Vlan stripping setting */
 901         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
 902                 rte_spinlock_lock(&hw->lock);
 903                 /* Enable or disable VLAN stripping */
 904                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 905                         hns3vf_en_hw_strip_rxvtag(hw, true);
 906                 else
 907                         hns3vf_en_hw_strip_rxvtag(hw, false);
 908                 rte_spinlock_unlock(&hw->lock);
 909         }
 910
 911         return 0;
 912 }
 913
 914 static int
 915 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
 916 {
 917         struct rte_vlan_filter_conf *vfc;
 918         struct hns3_hw *hw = &hns->hw;
 919         uint16_t vlan_id;
 920         uint64_t vbit;
 921         uint64_t ids;
 922         int ret = 0;
 923         uint32_t i;
 924
 925         vfc = &hw->data->vlan_filter_conf;
 926         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
 927                 if (vfc->ids[i] == 0)
 928                         continue;
 929                 ids = vfc->ids[i];
 930                 while (ids) {
 931                         /*
 932                          * 64 means the num bits of ids, one bit corresponds to
 933                          * one vlan id
 934                          */
 935                         vlan_id = 64 * i;
 936                         /* count trailing zeroes */
 937                         vbit = ~ids & (ids - 1);
 938                         /* clear least significant bit set */
 939                         ids ^= (ids ^ (ids - 1)) ^ vbit;
 940                         for (; vbit;) {
 941                                 vbit >>= 1;
 942                                 vlan_id++;
 943                         }
 944                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
 945                         if (ret) {
 946                                 hns3_err(hw,
 947                                          "VF handle vlan table failed, ret =%d, on = %d",
 948                                          ret, on);
 949                                 return ret;
 950                         }
 951                 }
 952         }
 953
 954         return ret;
 955 }
 956
 957 static int
 958 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
 959 {
 960         return hns3vf_handle_all_vlan_table(hns, 0);
 961 }
 962
 963 static int
 964 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
 965 {
 966         struct hns3_hw *hw = &hns->hw;
 967         struct rte_eth_conf *dev_conf;
 968         bool en;
 969         int ret;
 970
 971         dev_conf = &hw->data->dev_conf;
 972         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
 973                                                                    : false;
 974         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
 975         if (ret)
 976                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
 977                          ret);
 978         return ret;
 979 }
 980
 981 static int
 982 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
 983 {
 984         struct hns3_adapter *hns = dev->data->dev_private;
 985         struct rte_eth_dev_data *data = dev->data;
 986         struct hns3_hw *hw = &hns->hw;
 987         int ret;
 988
 989         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
 990             data->dev_conf.txmode.hw_vlan_reject_untagged ||
 991             data->dev_conf.txmode.hw_vlan_insert_pvid) {
 992                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
 993                               "or hw_vlan_insert_pvid is not support!");
 994         }
 995
 996         /* Apply vlan offload setting */
 997         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
 998         if (ret)
 999                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1000
1001         return ret;
1002 }
1003
1004 static int
1005 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1006 {
1007         uint8_t msg_data;
1008
1009         msg_data = alive ? 1 : 0;
1010         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1011                                  sizeof(msg_data), false, NULL, 0);
1012 }
1013
1014 static void
1015 hns3vf_keep_alive_handler(void *param)
1016 {
1017         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1018         struct hns3_adapter *hns = eth_dev->data->dev_private;
1019         struct hns3_hw *hw = &hns->hw;
1020         uint8_t respmsg;
1021         int ret;
1022
1023         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1024                                 false, &respmsg, sizeof(uint8_t));
1025         if (ret)
1026                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1027                          ret);
1028
1029         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1030                           eth_dev);
1031 }
1032
1033 static void
1034 hns3vf_service_handler(void *param)
1035 {
1036         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1037         struct hns3_adapter *hns = eth_dev->data->dev_private;
1038         struct hns3_hw *hw = &hns->hw;
1039
1040         /*
1041          * The query link status and reset processing are executed in the
1042          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1043          * and the query operation will time out after 30ms. In the case of
1044          * multiple PF/VFs, each query failure timeout causes the IMP reset
1045          * interrupt to fail to respond within 100ms.
1046          * Before querying the link status, check whether there is a reset
1047          * pending, and if so, abandon the query.
1048          */
1049         if (!hns3vf_is_reset_pending(hns))
1050                 hns3vf_request_link_info(hw);
1051         else
1052                 hns3_warn(hw, "Cancel the query when reset is pending");
1053
1054         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1055                           eth_dev);
1056 }
1057
1058 static int
1059 hns3vf_init_hardware(struct hns3_adapter *hns)
1060 {
1061         struct hns3_hw *hw = &hns->hw;
1062         uint16_t mtu = hw->data->mtu;
1063         int ret;
1064
1065         ret = hns3vf_set_promisc_mode(hw, true);
1066         if (ret)
1067                 return ret;
1068
1069         ret = hns3vf_config_mtu(hw, mtu);
1070         if (ret)
1071                 goto err_init_hardware;
1072
1073         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1074         if (ret) {
1075                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1076                 goto err_init_hardware;
1077         }
1078
1079         ret = hns3_config_gro(hw, false);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1082                 goto err_init_hardware;
1083         }
1084
1085         ret = hns3vf_set_alive(hw, true);
1086         if (ret) {
1087                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1088                 goto err_init_hardware;
1089         }
1090
1091         hns3vf_request_link_info(hw);
1092         return 0;
1093
1094 err_init_hardware:
1095         (void)hns3vf_set_promisc_mode(hw, false);
1096         return ret;
1097 }
1098
1099 static int
1100 hns3vf_clear_vport_list(struct hns3_hw *hw)
1101 {
1102         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1103                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1104                                  NULL, 0);
1105 }
1106
1107 static int
1108 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1109 {
1110         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1111         struct hns3_adapter *hns = eth_dev->data->dev_private;
1112         struct hns3_hw *hw = &hns->hw;
1113         int ret;
1114
1115         PMD_INIT_FUNC_TRACE();
1116
1117         /* Get hardware io base address from pcie BAR2 IO space */
1118         hw->io_base = pci_dev->mem_resource[2].addr;
1119
1120         /* Firmware command queue initialize */
1121         ret = hns3_cmd_init_queue(hw);
1122         if (ret) {
1123                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1124                 goto err_cmd_init_queue;
1125         }
1126
1127         /* Firmware command initialize */
1128         ret = hns3_cmd_init(hw);
1129         if (ret) {
1130                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1131                 goto err_cmd_init;
1132         }
1133
1134         rte_spinlock_init(&hw->mbx_resp.lock);
1135
1136         hns3vf_clear_event_cause(hw, 0);
1137
1138         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1139                                          hns3vf_interrupt_handler, eth_dev);
1140         if (ret) {
1141                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1142                 goto err_intr_callback_register;
1143         }
1144
1145         /* Enable interrupt */
1146         rte_intr_enable(&pci_dev->intr_handle);
1147         hns3vf_enable_irq0(hw);
1148
1149         /* Get configuration from PF */
1150         ret = hns3vf_get_configuration(hw);
1151         if (ret) {
1152                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1153                 goto err_get_config;
1154         }
1155
1156         rte_eth_random_addr(hw->mac.mac_addr); /* Generate a random mac addr */
1157
1158         ret = hns3vf_clear_vport_list(hw);
1159         if (ret) {
1160                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1161                 goto err_get_config;
1162         }
1163
1164         ret = hns3vf_init_hardware(hns);
1165         if (ret)
1166                 goto err_get_config;
1167
1168         hns3_set_default_rss_args(hw);
1169
1170         (void)hns3_stats_reset(eth_dev);
1171         return 0;
1172
1173 err_get_config:
1174         hns3vf_disable_irq0(hw);
1175         rte_intr_disable(&pci_dev->intr_handle);
1176         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1177                              eth_dev);
1178 err_intr_callback_register:
1179         hns3_cmd_uninit(hw);
1180
1181 err_cmd_init:
1182         hns3_cmd_destroy_queue(hw);
1183
1184 err_cmd_init_queue:
1185         hw->io_base = NULL;
1186
1187         return ret;
1188 }
1189
1190 static void
1191 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1192 {
1193         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1194         struct hns3_adapter *hns = eth_dev->data->dev_private;
1195         struct hns3_hw *hw = &hns->hw;
1196
1197         PMD_INIT_FUNC_TRACE();
1198
1199         hns3_rss_uninit(hns);
1200         (void)hns3vf_set_alive(hw, false);
1201         (void)hns3vf_set_promisc_mode(hw, false);
1202         hns3vf_disable_irq0(hw);
1203         rte_intr_disable(&pci_dev->intr_handle);
1204         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1205                              eth_dev);
1206         hns3_cmd_uninit(hw);
1207         hns3_cmd_destroy_queue(hw);
1208         hw->io_base = NULL;
1209 }
1210
1211 static int
1212 hns3vf_do_stop(struct hns3_adapter *hns)
1213 {
1214         struct hns3_hw *hw = &hns->hw;
1215         bool reset_queue;
1216
1217         hw->mac.link_status = ETH_LINK_DOWN;
1218
1219         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1220                 hns3vf_configure_mac_addr(hns, true);
1221                 reset_queue = true;
1222         } else
1223                 reset_queue = false;
1224         return hns3_stop_queues(hns, reset_queue);
1225 }
1226
1227 static void
1228 hns3vf_dev_stop(struct rte_eth_dev *eth_dev)
1229 {
1230         struct hns3_adapter *hns = eth_dev->data->dev_private;
1231         struct hns3_hw *hw = &hns->hw;
1232
1233         PMD_INIT_FUNC_TRACE();
1234
1235         hw->adapter_state = HNS3_NIC_STOPPING;
1236         hns3_set_rxtx_function(eth_dev);
1237         rte_wmb();
1238         /* Disable datapath on secondary process. */
1239         hns3_mp_req_stop_rxtx(eth_dev);
1240         /* Prevent crashes when queues are still in use. */
1241         rte_delay_ms(hw->tqps_num);
1242
1243         rte_spinlock_lock(&hw->lock);
1244         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1245                 hns3vf_do_stop(hns);
1246                 hns3_dev_release_mbufs(hns);
1247                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1248         }
1249         rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1250         rte_spinlock_unlock(&hw->lock);
1251 }
1252
1253 static void
1254 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1255 {
1256         struct hns3_adapter *hns = eth_dev->data->dev_private;
1257         struct hns3_hw *hw = &hns->hw;
1258
1259         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1260                 return;
1261
1262         if (hw->adapter_state == HNS3_NIC_STARTED)
1263                 hns3vf_dev_stop(eth_dev);
1264
1265         hw->adapter_state = HNS3_NIC_CLOSING;
1266         hns3_reset_abort(hns);
1267         hw->adapter_state = HNS3_NIC_CLOSED;
1268         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1269         hns3vf_configure_all_mc_mac_addr(hns, true);
1270         hns3vf_remove_all_vlan_table(hns);
1271         hns3vf_uninit_vf(eth_dev);
1272         hns3_free_all_queues(eth_dev);
1273         rte_free(hw->reset.wait_data);
1274         rte_free(eth_dev->process_private);
1275         eth_dev->process_private = NULL;
1276         hns3_mp_uninit_primary();
1277         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1278 }
1279
1280 static int
1281 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1282                        __rte_unused int wait_to_complete)
1283 {
1284         struct hns3_adapter *hns = eth_dev->data->dev_private;
1285         struct hns3_hw *hw = &hns->hw;
1286         struct hns3_mac *mac = &hw->mac;
1287         struct rte_eth_link new_link;
1288
1289         memset(&new_link, 0, sizeof(new_link));
1290         switch (mac->link_speed) {
1291         case ETH_SPEED_NUM_10M:
1292         case ETH_SPEED_NUM_100M:
1293         case ETH_SPEED_NUM_1G:
1294         case ETH_SPEED_NUM_10G:
1295         case ETH_SPEED_NUM_25G:
1296         case ETH_SPEED_NUM_40G:
1297         case ETH_SPEED_NUM_50G:
1298         case ETH_SPEED_NUM_100G:
1299                 new_link.link_speed = mac->link_speed;
1300                 break;
1301         default:
1302                 new_link.link_speed = ETH_SPEED_NUM_100M;
1303                 break;
1304         }
1305
1306         new_link.link_duplex = mac->link_duplex;
1307         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1308         new_link.link_autoneg =
1309             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1310
1311         return rte_eth_linkstatus_set(eth_dev, &new_link);
1312 }
1313
1314 static int
1315 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1316 {
1317         struct hns3_hw *hw = &hns->hw;
1318         int ret;
1319
1320         hns3vf_set_tc_info(hns);
1321
1322         ret = hns3_start_queues(hns, reset_queue);
1323         if (ret) {
1324                 hns3_err(hw, "Failed to start queues: %d", ret);
1325                 return ret;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int
1332 hns3vf_dev_start(struct rte_eth_dev *eth_dev)
1333 {
1334         struct hns3_adapter *hns = eth_dev->data->dev_private;
1335         struct hns3_hw *hw = &hns->hw;
1336         int ret;
1337
1338         PMD_INIT_FUNC_TRACE();
1339         if (rte_atomic16_read(&hw->reset.resetting))
1340                 return -EBUSY;
1341         rte_spinlock_lock(&hw->lock);
1342         hw->adapter_state = HNS3_NIC_STARTING;
1343         ret = hns3vf_do_start(hns, true);
1344         if (ret) {
1345                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1346                 rte_spinlock_unlock(&hw->lock);
1347                 return ret;
1348         }
1349         hw->adapter_state = HNS3_NIC_STARTED;
1350         rte_spinlock_unlock(&hw->lock);
1351         hns3_set_rxtx_function(eth_dev);
1352         hns3_mp_req_start_rxtx(eth_dev);
1353         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1354                           eth_dev);
1355         return 0;
1356 }
1357
1358 static bool
1359 is_vf_reset_done(struct hns3_hw *hw)
1360 {
1361 #define HNS3_FUN_RST_ING_BITS \
1362         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
1363          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
1364          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
1365          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
1366
1367         uint32_t val;
1368
1369         if (hw->reset.level == HNS3_VF_RESET) {
1370                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1371                 if (val & HNS3_VF_RST_ING_BIT)
1372                         return false;
1373         } else {
1374                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1375                 if (val & HNS3_FUN_RST_ING_BITS)
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 bool
1382 hns3vf_is_reset_pending(struct hns3_adapter *hns)
1383 {
1384         struct hns3_hw *hw = &hns->hw;
1385         enum hns3_reset_level reset;
1386
1387         hns3vf_check_event_cause(hns, NULL);
1388         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
1389         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
1390                 hns3_warn(hw, "High level reset %d is pending", reset);
1391                 return true;
1392         }
1393         return false;
1394 }
1395
1396 static int
1397 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
1398 {
1399         struct hns3_hw *hw = &hns->hw;
1400         struct hns3_wait_data *wait_data = hw->reset.wait_data;
1401         struct timeval tv;
1402
1403         if (wait_data->result == HNS3_WAIT_SUCCESS) {
1404                 /*
1405                  * After vf reset is ready, the PF may not have completed
1406                  * the reset processing. The vf sending mbox to PF may fail
1407                  * during the pf reset, so it is better to add extra delay.
1408                  */
1409                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
1410                     hw->reset.level == HNS3_FLR_RESET)
1411                         return 0;
1412                 /* Reset retry process, no need to add extra delay. */
1413                 if (hw->reset.attempts)
1414                         return 0;
1415                 if (wait_data->check_completion == NULL)
1416                         return 0;
1417
1418                 wait_data->check_completion = NULL;
1419                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
1420                 wait_data->count = 1;
1421                 wait_data->result = HNS3_WAIT_REQUEST;
1422                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
1423                                   wait_data);
1424                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
1425                 return -EAGAIN;
1426         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
1427                 gettimeofday(&tv, NULL);
1428                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
1429                           tv.tv_sec, tv.tv_usec);
1430                 return -ETIME;
1431         } else if (wait_data->result == HNS3_WAIT_REQUEST)
1432                 return -EAGAIN;
1433
1434         wait_data->hns = hns;
1435         wait_data->check_completion = is_vf_reset_done;
1436         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
1437                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
1438         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
1439         wait_data->count = HNS3VF_RESET_WAIT_CNT;
1440         wait_data->result = HNS3_WAIT_REQUEST;
1441         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
1442         return -EAGAIN;
1443 }
1444
1445 static int
1446 hns3vf_prepare_reset(struct hns3_adapter *hns)
1447 {
1448         struct hns3_hw *hw = &hns->hw;
1449         int ret = 0;
1450
1451         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
1452                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
1453                                         0, true, NULL, 0);
1454         }
1455         rte_atomic16_set(&hw->reset.disable_cmd, 1);
1456
1457         return ret;
1458 }
1459
1460 static int
1461 hns3vf_stop_service(struct hns3_adapter *hns)
1462 {
1463         struct hns3_hw *hw = &hns->hw;
1464         struct rte_eth_dev *eth_dev;
1465
1466         eth_dev = &rte_eth_devices[hw->data->port_id];
1467         rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
1468         hw->mac.link_status = ETH_LINK_DOWN;
1469
1470         hns3_set_rxtx_function(eth_dev);
1471         rte_wmb();
1472         /* Disable datapath on secondary process. */
1473         hns3_mp_req_stop_rxtx(eth_dev);
1474         rte_delay_ms(hw->tqps_num);
1475
1476         rte_spinlock_lock(&hw->lock);
1477         if (hw->adapter_state == HNS3_NIC_STARTED ||
1478             hw->adapter_state == HNS3_NIC_STOPPING) {
1479                 hns3vf_do_stop(hns);
1480                 hw->reset.mbuf_deferred_free = true;
1481         } else
1482                 hw->reset.mbuf_deferred_free = false;
1483
1484         /*
1485          * It is cumbersome for hardware to pick-and-choose entries for deletion
1486          * from table space. Hence, for function reset software intervention is
1487          * required to delete the entries.
1488          */
1489         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
1490                 hns3vf_configure_all_mc_mac_addr(hns, true);
1491         rte_spinlock_unlock(&hw->lock);
1492
1493         return 0;
1494 }
1495
1496 static int
1497 hns3vf_start_service(struct hns3_adapter *hns)
1498 {
1499         struct hns3_hw *hw = &hns->hw;
1500         struct rte_eth_dev *eth_dev;
1501
1502         eth_dev = &rte_eth_devices[hw->data->port_id];
1503         hns3_set_rxtx_function(eth_dev);
1504         hns3_mp_req_start_rxtx(eth_dev);
1505
1506         hns3vf_service_handler(eth_dev);
1507         return 0;
1508 }
1509
1510 static int
1511 hns3vf_restore_conf(struct hns3_adapter *hns)
1512 {
1513         struct hns3_hw *hw = &hns->hw;
1514         int ret;
1515
1516         ret = hns3vf_configure_mac_addr(hns, false);
1517         if (ret)
1518                 return ret;
1519
1520         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
1521         if (ret)
1522                 goto err_mc_mac;
1523
1524         ret = hns3vf_restore_vlan_conf(hns);
1525         if (ret)
1526                 goto err_vlan_table;
1527
1528         if (hw->adapter_state == HNS3_NIC_STARTED) {
1529                 ret = hns3vf_do_start(hns, false);
1530                 if (ret)
1531                         goto err_vlan_table;
1532                 hns3_info(hw, "hns3vf dev restart successful!");
1533         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
1534                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1535         return 0;
1536
1537 err_vlan_table:
1538         hns3vf_configure_all_mc_mac_addr(hns, true);
1539 err_mc_mac:
1540         hns3vf_configure_mac_addr(hns, true);
1541         return ret;
1542 }
1543
1544 static enum hns3_reset_level
1545 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
1546 {
1547         enum hns3_reset_level reset_level;
1548
1549         /* return the highest priority reset level amongst all */
1550         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
1551                 reset_level = HNS3_VF_RESET;
1552         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
1553                 reset_level = HNS3_VF_FULL_RESET;
1554         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
1555                 reset_level = HNS3_VF_PF_FUNC_RESET;
1556         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
1557                 reset_level = HNS3_VF_FUNC_RESET;
1558         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
1559                 reset_level = HNS3_FLR_RESET;
1560         else
1561                 reset_level = HNS3_NONE_RESET;
1562
1563         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
1564                 return HNS3_NONE_RESET;
1565
1566         return reset_level;
1567 }
1568
1569 static void
1570 hns3vf_reset_service(void *param)
1571 {
1572         struct hns3_adapter *hns = (struct hns3_adapter *)param;
1573         struct hns3_hw *hw = &hns->hw;
1574         enum hns3_reset_level reset_level;
1575         struct timeval tv_delta;
1576         struct timeval tv_start;
1577         struct timeval tv;
1578         uint64_t msec;
1579
1580         /*
1581          * The interrupt is not triggered within the delay time.
1582          * The interrupt may have been lost. It is necessary to handle
1583          * the interrupt to recover from the error.
1584          */
1585         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
1586                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
1587                 hns3_err(hw, "Handling interrupts in delayed tasks");
1588                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
1589                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
1590                 if (reset_level == HNS3_NONE_RESET) {
1591                         hns3_err(hw, "No reset level is set, try global reset");
1592                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1593                 }
1594         }
1595         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
1596
1597         /*
1598          * Hardware reset has been notified, we now have to poll & check if
1599          * hardware has actually completed the reset sequence.
1600          */
1601         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
1602         if (reset_level != HNS3_NONE_RESET) {
1603                 gettimeofday(&tv_start, NULL);
1604                 hns3_reset_process(hns, reset_level);
1605                 gettimeofday(&tv, NULL);
1606                 timersub(&tv, &tv_start, &tv_delta);
1607                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
1608                        tv_delta.tv_usec / USEC_PER_MSEC;
1609                 if (msec > HNS3_RESET_PROCESS_MS)
1610                         hns3_err(hw, "%d handle long time delta %" PRIx64
1611                                  " ms time=%ld.%.6ld",
1612                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
1613         }
1614 }
1615
1616 static int
1617 hns3vf_reinit_dev(struct hns3_adapter *hns)
1618 {
1619         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
1620         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1621         struct hns3_hw *hw = &hns->hw;
1622         int ret;
1623
1624         if (hw->reset.level == HNS3_VF_FULL_RESET) {
1625                 rte_intr_disable(&pci_dev->intr_handle);
1626                 hns3vf_set_bus_master(pci_dev, true);
1627         }
1628
1629         /* Firmware command initialize */
1630         ret = hns3_cmd_init(hw);
1631         if (ret) {
1632                 hns3_err(hw, "Failed to init cmd: %d", ret);
1633                 goto err_cmd_init;
1634         }
1635
1636         if (hw->reset.level == HNS3_VF_FULL_RESET) {
1637                 /*
1638                  * UIO enables msix by writing the pcie configuration space
1639                  * vfio_pci enables msix in rte_intr_enable.
1640                  */
1641                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
1642                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
1643                         if (hns3vf_enable_msix(pci_dev, true))
1644                                 hns3_err(hw, "Failed to enable msix");
1645                 }
1646
1647                 rte_intr_enable(&pci_dev->intr_handle);
1648         }
1649
1650         ret = hns3_reset_all_queues(hns);
1651         if (ret) {
1652                 hns3_err(hw, "Failed to reset all queues: %d", ret);
1653                 goto err_init;
1654         }
1655
1656         ret = hns3vf_init_hardware(hns);
1657         if (ret) {
1658                 hns3_err(hw, "Failed to init hardware: %d", ret);
1659                 goto err_init;
1660         }
1661
1662         return 0;
1663
1664 err_cmd_init:
1665         hns3vf_set_bus_master(pci_dev, false);
1666 err_init:
1667         hns3_cmd_uninit(hw);
1668         return ret;
1669 }
1670
1671 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
1672         .dev_start          = hns3vf_dev_start,
1673         .dev_stop           = hns3vf_dev_stop,
1674         .dev_close          = hns3vf_dev_close,
1675         .mtu_set            = hns3vf_dev_mtu_set,
1676         .stats_get          = hns3_stats_get,
1677         .stats_reset        = hns3_stats_reset,
1678         .xstats_get         = hns3_dev_xstats_get,
1679         .xstats_get_names   = hns3_dev_xstats_get_names,
1680         .xstats_reset       = hns3_dev_xstats_reset,
1681         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
1682         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
1683         .dev_infos_get      = hns3vf_dev_infos_get,
1684         .rx_queue_setup     = hns3_rx_queue_setup,
1685         .tx_queue_setup     = hns3_tx_queue_setup,
1686         .rx_queue_release   = hns3_dev_rx_queue_release,
1687         .tx_queue_release   = hns3_dev_tx_queue_release,
1688         .dev_configure      = hns3vf_dev_configure,
1689         .mac_addr_add       = hns3vf_add_mac_addr,
1690         .mac_addr_remove    = hns3vf_remove_mac_addr,
1691         .mac_addr_set       = hns3vf_set_default_mac_addr,
1692         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
1693         .link_update        = hns3vf_dev_link_update,
1694         .rss_hash_update    = hns3_dev_rss_hash_update,
1695         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
1696         .reta_update        = hns3_dev_rss_reta_update,
1697         .reta_query         = hns3_dev_rss_reta_query,
1698         .filter_ctrl        = hns3_dev_filter_ctrl,
1699         .vlan_filter_set    = hns3vf_vlan_filter_set,
1700         .vlan_offload_set   = hns3vf_vlan_offload_set,
1701         .get_reg            = hns3_get_regs,
1702         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
1703 };
1704
1705 static const struct hns3_reset_ops hns3vf_reset_ops = {
1706         .reset_service       = hns3vf_reset_service,
1707         .stop_service        = hns3vf_stop_service,
1708         .prepare_reset       = hns3vf_prepare_reset,
1709         .wait_hardware_ready = hns3vf_wait_hardware_ready,
1710         .reinit_dev          = hns3vf_reinit_dev,
1711         .restore_conf        = hns3vf_restore_conf,
1712         .start_service       = hns3vf_start_service,
1713 };
1714
1715 static int
1716 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
1717 {
1718         struct hns3_adapter *hns = eth_dev->data->dev_private;
1719         struct hns3_hw *hw = &hns->hw;
1720         int ret;
1721
1722         PMD_INIT_FUNC_TRACE();
1723
1724         eth_dev->process_private = (struct hns3_process_private *)
1725             rte_zmalloc_socket("hns3_filter_list",
1726                                sizeof(struct hns3_process_private),
1727                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
1728         if (eth_dev->process_private == NULL) {
1729                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
1730                 return -ENOMEM;
1731         }
1732
1733         /* initialize flow filter lists */
1734         hns3_filterlist_init(eth_dev);
1735
1736         hns3_set_rxtx_function(eth_dev);
1737         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
1738         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1739                 hns3_mp_init_secondary();
1740                 hw->secondary_cnt++;
1741                 return 0;
1742         }
1743
1744         hns3_mp_init_primary();
1745
1746         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
1747         hns->is_vf = true;
1748         hw->data = eth_dev->data;
1749
1750         ret = hns3_reset_init(hw);
1751         if (ret)
1752                 goto err_init_reset;
1753         hw->reset.ops = &hns3vf_reset_ops;
1754
1755         ret = hns3vf_init_vf(eth_dev);
1756         if (ret) {
1757                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
1758                 goto err_init_vf;
1759         }
1760
1761         /* Allocate memory for storing MAC addresses */
1762         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
1763                                                sizeof(struct rte_ether_addr) *
1764                                                HNS3_VF_UC_MACADDR_NUM, 0);
1765         if (eth_dev->data->mac_addrs == NULL) {
1766                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
1767                              "to store MAC addresses",
1768                              sizeof(struct rte_ether_addr) *
1769                              HNS3_VF_UC_MACADDR_NUM);
1770                 ret = -ENOMEM;
1771                 goto err_rte_zmalloc;
1772         }
1773
1774         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
1775                             &eth_dev->data->mac_addrs[0]);
1776         hw->adapter_state = HNS3_NIC_INITIALIZED;
1777         /*
1778          * Pass the information to the rte_eth_dev_close() that it should also
1779          * release the private port resources.
1780          */
1781         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1782
1783         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
1784                 hns3_err(hw, "Reschedule reset service after dev_init");
1785                 hns3_schedule_reset(hns);
1786         } else {
1787                 /* IMP will wait ready flag before reset */
1788                 hns3_notify_reset_ready(hw, false);
1789         }
1790         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1791                           eth_dev);
1792         return 0;
1793
1794 err_rte_zmalloc:
1795         hns3vf_uninit_vf(eth_dev);
1796
1797 err_init_vf:
1798         rte_free(hw->reset.wait_data);
1799
1800 err_init_reset:
1801         eth_dev->dev_ops = NULL;
1802         eth_dev->rx_pkt_burst = NULL;
1803         eth_dev->tx_pkt_burst = NULL;
1804         eth_dev->tx_pkt_prepare = NULL;
1805         rte_free(eth_dev->process_private);
1806         eth_dev->process_private = NULL;
1807
1808         return ret;
1809 }
1810
1811 static int
1812 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
1813 {
1814         struct hns3_adapter *hns = eth_dev->data->dev_private;
1815         struct hns3_hw *hw = &hns->hw;
1816
1817         PMD_INIT_FUNC_TRACE();
1818
1819         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1820                 return -EPERM;
1821
1822         eth_dev->dev_ops = NULL;
1823         eth_dev->rx_pkt_burst = NULL;
1824         eth_dev->tx_pkt_burst = NULL;
1825         eth_dev->tx_pkt_prepare = NULL;
1826
1827         if (hw->adapter_state < HNS3_NIC_CLOSING)
1828                 hns3vf_dev_close(eth_dev);
1829
1830         hw->adapter_state = HNS3_NIC_REMOVED;
1831         return 0;
1832 }
1833
1834 static int
1835 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1836                      struct rte_pci_device *pci_dev)
1837 {
1838         return rte_eth_dev_pci_generic_probe(pci_dev,
1839                                              sizeof(struct hns3_adapter),
1840                                              hns3vf_dev_init);
1841 }
1842
1843 static int
1844 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
1845 {
1846         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
1847 }
1848
1849 static const struct rte_pci_id pci_id_hns3vf_map[] = {
1850         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
1851         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
1852         { .vendor_id = 0, /* sentinel */ },
1853 };
1854
1855 static struct rte_pci_driver rte_hns3vf_pmd = {
1856         .id_table = pci_id_hns3vf_map,
1857         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1858         .probe = eth_hns3vf_pci_probe,
1859         .remove = eth_hns3vf_pci_remove,
1860 };
1861
1862 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
1863 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
1864 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");