drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2021 HiSilicon Limited.
   3  */
   4
   5 #include <linux/pci_regs.h>
   6 #include <rte_alarm.h>
   7 #include <ethdev_pci.h>
   8 #include <rte_io.h>
   9 #include <rte_pci.h>
  10 #include <rte_vfio.h>
  11
  12 #include "hns3_ethdev.h"
  13 #include "hns3_logs.h"
  14 #include "hns3_rxtx.h"
  15 #include "hns3_regs.h"
  16 #include "hns3_intr.h"
  17 #include "hns3_dcb.h"
  18 #include "hns3_mp.h"
  19
  20 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  21 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  22
  23 #define HNS3VF_RESET_WAIT_MS    20
  24 #define HNS3VF_RESET_WAIT_CNT   2000
  25
  26 /* Reset related Registers */
  27 #define HNS3_GLOBAL_RESET_BIT           0
  28 #define HNS3_CORE_RESET_BIT             1
  29 #define HNS3_IMP_RESET_BIT              2
  30 #define HNS3_FUN_RST_ING_B              0
  31
  32 enum hns3vf_evt_cause {
  33         HNS3VF_VECTOR0_EVENT_RST,
  34         HNS3VF_VECTOR0_EVENT_MBX,
  35         HNS3VF_VECTOR0_EVENT_OTHER,
  36 };
  37
  38 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  39                                                     uint64_t *levels);
  40 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  41 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  42
  43 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  44                                   struct rte_ether_addr *mac_addr);
  45 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  46                                      struct rte_ether_addr *mac_addr);
  47 static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
  48                                    __rte_unused int wait_to_complete);
  49
  50 /* set PCI bus mastering */
  51 static int
  52 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  53 {
  54         uint16_t reg;
  55         int ret;
  56
  57         ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  58         if (ret < 0) {
  59                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
  60                              PCI_COMMAND);
  61                 return ret;
  62         }
  63
  64         if (op)
  65                 /* set the master bit */
  66                 reg |= PCI_COMMAND_MASTER;
  67         else
  68                 reg &= ~(PCI_COMMAND_MASTER);
  69
  70         return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  71 }
  72
  73 /**
  74  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  75  * @cap: the capability
  76  *
  77  * Return the address of the given capability within the PCI capability list.
  78  */
  79 static int
  80 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  81 {
  82 #define MAX_PCIE_CAPABILITY 48
  83         uint16_t status;
  84         uint8_t pos;
  85         uint8_t id;
  86         int ttl;
  87         int ret;
  88
  89         ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  90         if (ret < 0) {
  91                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
  92                 return 0;
  93         }
  94
  95         if (!(status & PCI_STATUS_CAP_LIST))
  96                 return 0;
  97
  98         ttl = MAX_PCIE_CAPABILITY;
  99         ret = rte_pci_read_config(device, &pos, sizeof(pos),
 100                                   PCI_CAPABILITY_LIST);
 101         if (ret < 0) {
 102                 PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 103                              PCI_CAPABILITY_LIST);
 104                 return 0;
 105         }
 106
 107         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 108                 ret = rte_pci_read_config(device, &id, sizeof(id),
 109                                           (pos + PCI_CAP_LIST_ID));
 110                 if (ret < 0) {
 111                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 112                                      (pos + PCI_CAP_LIST_ID));
 113                         break;
 114                 }
 115
 116                 if (id == 0xFF)
 117                         break;
 118
 119                 if (id == cap)
 120                         return (int)pos;
 121
 122                 ret = rte_pci_read_config(device, &pos, sizeof(pos),
 123                                           (pos + PCI_CAP_LIST_NEXT));
 124                 if (ret < 0) {
 125                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 126                                      (pos + PCI_CAP_LIST_NEXT));
 127                         break;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 static int
 134 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 135 {
 136         uint16_t control;
 137         int pos;
 138         int ret;
 139
 140         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 141         if (pos) {
 142                 ret = rte_pci_read_config(device, &control, sizeof(control),
 143                                     (pos + PCI_MSIX_FLAGS));
 144                 if (ret < 0) {
 145                         PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
 146                                      (pos + PCI_MSIX_FLAGS));
 147                         return -ENXIO;
 148                 }
 149
 150                 if (op)
 151                         control |= PCI_MSIX_FLAGS_ENABLE;
 152                 else
 153                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 154                 ret = rte_pci_write_config(device, &control, sizeof(control),
 155                                           (pos + PCI_MSIX_FLAGS));
 156                 if (ret < 0) {
 157                         PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
 158                                     (pos + PCI_MSIX_FLAGS));
 159                         return -ENXIO;
 160                 }
 161
 162                 return 0;
 163         }
 164
 165         return -ENXIO;
 166 }
 167
 168 static int
 169 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 170 {
 171         /* mac address was checked by upper level interface */
 172         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 173         int ret;
 174
 175         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 176                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 177                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 178         if (ret) {
 179                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 180                                       mac_addr);
 181                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 182                          mac_str, ret);
 183         }
 184         return ret;
 185 }
 186
 187 static int
 188 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 189 {
 190         /* mac address was checked by upper level interface */
 191         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 192         int ret;
 193
 194         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 195                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 196                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 197                                 false, NULL, 0);
 198         if (ret) {
 199                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 200                                       mac_addr);
 201                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 202                          mac_str, ret);
 203         }
 204         return ret;
 205 }
 206
 207 static int
 208 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 209 {
 210         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 211         struct rte_ether_addr *addr;
 212         int ret;
 213         int i;
 214
 215         for (i = 0; i < hw->mc_addrs_num; i++) {
 216                 addr = &hw->mc_addrs[i];
 217                 /* Check if there are duplicate addresses */
 218                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 219                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 220                                               addr);
 221                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 222                                  "(%s) is added by the set_mc_mac_addr_list "
 223                                  "API", mac_str);
 224                         return -EINVAL;
 225                 }
 226         }
 227
 228         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 229         if (ret) {
 230                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 231                                       mac_addr);
 232                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 233                          mac_str, ret);
 234         }
 235         return ret;
 236 }
 237
 238 static int
 239 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 240                     __rte_unused uint32_t idx,
 241                     __rte_unused uint32_t pool)
 242 {
 243         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 245         int ret;
 246
 247         rte_spinlock_lock(&hw->lock);
 248
 249         /*
 250          * In hns3 network engine adding UC and MC mac address with different
 251          * commands with firmware. We need to determine whether the input
 252          * address is a UC or a MC address to call different commands.
 253          * By the way, it is recommended calling the API function named
 254          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 255          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 256          * may affect the specifications of UC mac addresses.
 257          */
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 260         else
 261                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 268                          ret);
 269         }
 270
 271         return ret;
 272 }
 273
 274 static void
 275 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 276 {
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         /* index will be checked by upper level rte interface */
 279         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         rte_spinlock_lock(&hw->lock);
 284
 285         if (rte_is_multicast_ether_addr(mac_addr))
 286                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 287         else
 288                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 289
 290         rte_spinlock_unlock(&hw->lock);
 291         if (ret) {
 292                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 293                                       mac_addr);
 294                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 295                          mac_str, ret);
 296         }
 297 }
 298
 299 static int
 300 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 301                             struct rte_ether_addr *mac_addr)
 302 {
 303 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 304         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 305         struct rte_ether_addr *old_addr;
 306         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 307         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 308         int ret;
 309
 310         /*
 311          * It has been guaranteed that input parameter named mac_addr is valid
 312          * address in the rte layer of DPDK framework.
 313          */
 314         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 315         rte_spinlock_lock(&hw->lock);
 316         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 317         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 318                RTE_ETHER_ADDR_LEN);
 319
 320         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 321                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 322                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 323         if (ret) {
 324                 /*
 325                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 326                  * driver. When user has configured a MAC address for VF device
 327                  * by "ip link set ..." command based on the PF device, the hns3
 328                  * PF kernel ethdev driver does not allow VF driver to request
 329                  * reconfiguring a different default MAC address, and return
 330                  * -EPREM to VF driver through mailbox.
 331                  */
 332                 if (ret == -EPERM) {
 333                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 334                                               old_addr);
 335                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 336                                   mac_str);
 337                 } else {
 338                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 339                                               mac_addr);
 340                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 341                                  mac_str, ret);
 342                 }
 343         }
 344
 345         rte_ether_addr_copy(mac_addr,
 346                             (struct rte_ether_addr *)hw->mac.mac_addr);
 347         rte_spinlock_unlock(&hw->lock);
 348
 349         return ret;
 350 }
 351
 352 static int
 353 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 354 {
 355         struct hns3_hw *hw = &hns->hw;
 356         struct rte_ether_addr *addr;
 357         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 358         int err = 0;
 359         int ret;
 360         int i;
 361
 362         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 363                 addr = &hw->data->mac_addrs[i];
 364                 if (rte_is_zero_ether_addr(addr))
 365                         continue;
 366                 if (rte_is_multicast_ether_addr(addr))
 367                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 368                               hns3vf_add_mc_mac_addr(hw, addr);
 369                 else
 370                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 371                               hns3vf_add_uc_mac_addr(hw, addr);
 372
 373                 if (ret) {
 374                         err = ret;
 375                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 376                                               addr);
 377                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 378                                  "ret = %d.", del ? "remove" : "restore",
 379                                  mac_str, i, ret);
 380                 }
 381         }
 382         return err;
 383 }
 384
 385 static int
 386 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 387                        struct rte_ether_addr *mac_addr)
 388 {
 389         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 390         int ret;
 391
 392         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 393                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 394                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 395                                 NULL, 0);
 396         if (ret) {
 397                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 398                                       mac_addr);
 399                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 400                          mac_str, ret);
 401         }
 402
 403         return ret;
 404 }
 405
 406 static int
 407 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 408                           struct rte_ether_addr *mac_addr)
 409 {
 410         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 411         int ret;
 412
 413         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 414                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 415                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 416                                 NULL, 0);
 417         if (ret) {
 418                 hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 419                                       mac_addr);
 420                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 421                          mac_str, ret);
 422         }
 423
 424         return ret;
 425 }
 426
 427 static int
 428 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 429                              struct rte_ether_addr *mc_addr_set,
 430                              uint32_t nb_mc_addr)
 431 {
 432         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 433         struct rte_ether_addr *addr;
 434         uint32_t i;
 435         uint32_t j;
 436
 437         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 438                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%u) "
 439                          "invalid. valid range: 0~%d",
 440                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 441                 return -EINVAL;
 442         }
 443
 444         /* Check if input mac addresses are valid */
 445         for (i = 0; i < nb_mc_addr; i++) {
 446                 addr = &mc_addr_set[i];
 447                 if (!rte_is_multicast_ether_addr(addr)) {
 448                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 449                                               addr);
 450                         hns3_err(hw,
 451                                  "failed to set mc mac addr, addr(%s) invalid.",
 452                                  mac_str);
 453                         return -EINVAL;
 454                 }
 455
 456                 /* Check if there are duplicate addresses */
 457                 for (j = i + 1; j < nb_mc_addr; j++) {
 458                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 459                                 hns3_ether_format_addr(mac_str,
 460                                                       RTE_ETHER_ADDR_FMT_SIZE,
 461                                                       addr);
 462                                 hns3_err(hw, "failed to set mc mac addr, "
 463                                          "addrs invalid. two same addrs(%s).",
 464                                          mac_str);
 465                                 return -EINVAL;
 466                         }
 467                 }
 468
 469                 /*
 470                  * Check if there are duplicate addresses between mac_addrs
 471                  * and mc_addr_set
 472                  */
 473                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 474                         if (rte_is_same_ether_addr(addr,
 475                                                    &hw->data->mac_addrs[j])) {
 476                                 hns3_ether_format_addr(mac_str,
 477                                                       RTE_ETHER_ADDR_FMT_SIZE,
 478                                                       addr);
 479                                 hns3_err(hw, "failed to set mc mac addr, "
 480                                          "addrs invalid. addrs(%s) has already "
 481                                          "configured in mac_addr add API",
 482                                          mac_str);
 483                                 return -EINVAL;
 484                         }
 485                 }
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int
 492 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 493                             struct rte_ether_addr *mc_addr_set,
 494                             uint32_t nb_mc_addr)
 495 {
 496         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 497         struct rte_ether_addr *addr;
 498         int cur_addr_num;
 499         int set_addr_num;
 500         int num;
 501         int ret;
 502         int i;
 503
 504         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 505         if (ret)
 506                 return ret;
 507
 508         rte_spinlock_lock(&hw->lock);
 509         cur_addr_num = hw->mc_addrs_num;
 510         for (i = 0; i < cur_addr_num; i++) {
 511                 num = cur_addr_num - i - 1;
 512                 addr = &hw->mc_addrs[num];
 513                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 514                 if (ret) {
 515                         rte_spinlock_unlock(&hw->lock);
 516                         return ret;
 517                 }
 518
 519                 hw->mc_addrs_num--;
 520         }
 521
 522         set_addr_num = (int)nb_mc_addr;
 523         for (i = 0; i < set_addr_num; i++) {
 524                 addr = &mc_addr_set[i];
 525                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 526                 if (ret) {
 527                         rte_spinlock_unlock(&hw->lock);
 528                         return ret;
 529                 }
 530
 531                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 532                 hw->mc_addrs_num++;
 533         }
 534         rte_spinlock_unlock(&hw->lock);
 535
 536         return 0;
 537 }
 538
 539 static int
 540 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 541 {
 542         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 543         struct hns3_hw *hw = &hns->hw;
 544         struct rte_ether_addr *addr;
 545         int err = 0;
 546         int ret;
 547         int i;
 548
 549         for (i = 0; i < hw->mc_addrs_num; i++) {
 550                 addr = &hw->mc_addrs[i];
 551                 if (!rte_is_multicast_ether_addr(addr))
 552                         continue;
 553                 if (del)
 554                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 555                 else
 556                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 557                 if (ret) {
 558                         err = ret;
 559                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 560                                               addr);
 561                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 562                                  del ? "Remove" : "Restore", mac_str, ret);
 563                 }
 564         }
 565         return err;
 566 }
 567
 568 static int
 569 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 570                         bool en_uc_pmc, bool en_mc_pmc)
 571 {
 572         struct hns3_mbx_vf_to_pf_cmd *req;
 573         struct hns3_cmd_desc desc;
 574         int ret;
 575
 576         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 577
 578         /*
 579          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 580          * so there are some features for promiscuous/allmulticast mode in hns3
 581          * VF PMD driver as below:
 582          * 1. The promiscuous/allmulticast mode can be configured successfully
 583          *    only based on the trusted VF device. If based on the non trusted
 584          *    VF device, configuring promiscuous/allmulticast mode will fail.
 585          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 586          *    kernel ethdev driver on the host by the following command:
 587          *      "ip link set <eth num> vf <vf id> turst on"
 588          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 589          *    driver can receive the ingress and outgoing traffic. In the words,
 590          *    all the ingress packets, all the packets sent from the PF and
 591          *    other VFs on the same physical port.
 592          * 3. Note: Because of the hardware constraints, By default vlan filter
 593          *    is enabled and couldn't be turned off based on VF device, so vlan
 594          *    filter is still effective even in promiscuous mode. If upper
 595          *    applications don't call rte_eth_dev_vlan_filter API function to
 596          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 597          *    the packets with vlan tag in promiscuoue mode.
 598          */
 599         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 600         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 601         req->msg[1] = en_bc_pmc ? 1 : 0;
 602         req->msg[2] = en_uc_pmc ? 1 : 0;
 603         req->msg[3] = en_mc_pmc ? 1 : 0;
 604         req->msg[4] = hw->promisc_mode == HNS3_LIMIT_PROMISC_MODE ? 1 : 0;
 605
 606         ret = hns3_cmd_send(hw, &desc, 1);
 607         if (ret)
 608                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 609
 610         return ret;
 611 }
 612
 613 static int
 614 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 615 {
 616         struct hns3_adapter *hns = dev->data->dev_private;
 617         struct hns3_hw *hw = &hns->hw;
 618         int ret;
 619
 620         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 621         if (ret)
 622                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 623                         ret);
 624         return ret;
 625 }
 626
 627 static int
 628 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 629 {
 630         bool allmulti = dev->data->all_multicast ? true : false;
 631         struct hns3_adapter *hns = dev->data->dev_private;
 632         struct hns3_hw *hw = &hns->hw;
 633         int ret;
 634
 635         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 636         if (ret)
 637                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 638                         ret);
 639         return ret;
 640 }
 641
 642 static int
 643 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 644 {
 645         struct hns3_adapter *hns = dev->data->dev_private;
 646         struct hns3_hw *hw = &hns->hw;
 647         int ret;
 648
 649         if (dev->data->promiscuous)
 650                 return 0;
 651
 652         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 653         if (ret)
 654                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 655                         ret);
 656         return ret;
 657 }
 658
 659 static int
 660 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 661 {
 662         struct hns3_adapter *hns = dev->data->dev_private;
 663         struct hns3_hw *hw = &hns->hw;
 664         int ret;
 665
 666         if (dev->data->promiscuous)
 667                 return 0;
 668
 669         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 670         if (ret)
 671                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 672                         ret);
 673         return ret;
 674 }
 675
 676 static int
 677 hns3vf_restore_promisc(struct hns3_adapter *hns)
 678 {
 679         struct hns3_hw *hw = &hns->hw;
 680         bool allmulti = hw->data->all_multicast ? true : false;
 681
 682         if (hw->data->promiscuous)
 683                 return hns3vf_set_promisc_mode(hw, true, true, true);
 684
 685         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 686 }
 687
 688 static int
 689 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 690                              bool mmap, enum hns3_ring_type queue_type,
 691                              uint16_t queue_id)
 692 {
 693         struct hns3_vf_bind_vector_msg bind_msg;
 694         const char *op_str;
 695         uint16_t code;
 696         int ret;
 697
 698         memset(&bind_msg, 0, sizeof(bind_msg));
 699         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 700                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 701         bind_msg.vector_id = vector_id;
 702
 703         if (queue_type == HNS3_RING_TYPE_RX)
 704                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 705         else
 706                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 707
 708         bind_msg.param[0].ring_type = queue_type;
 709         bind_msg.ring_num = 1;
 710         bind_msg.param[0].tqp_index = queue_id;
 711         op_str = mmap ? "Map" : "Unmap";
 712         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 713                                 sizeof(bind_msg), false, NULL, 0);
 714         if (ret)
 715                 hns3_err(hw, "%s TQP %u fail, vector_id is %u, ret is %d.",
 716                          op_str, queue_id, bind_msg.vector_id, ret);
 717
 718         return ret;
 719 }
 720
 721 static int
 722 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 723 {
 724         uint16_t vec;
 725         int ret;
 726         int i;
 727
 728         /*
 729          * In hns3 network engine, vector 0 is always the misc interrupt of this
 730          * function, vector 1~N can be used respectively for the queues of the
 731          * function. Tx and Rx queues with the same number share the interrupt
 732          * vector. In the initialization clearing the all hardware mapping
 733          * relationship configurations between queues and interrupt vectors is
 734          * needed, so some error caused by the residual configurations, such as
 735          * the unexpected Tx interrupt, can be avoid.
 736          */
 737         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 738         if (hw->intr.mapping_mode == HNS3_INTR_MAPPING_VEC_RSV_ONE)
 739                 vec = vec - 1; /* the last interrupt is reserved */
 740         hw->intr_tqps_num = RTE_MIN(vec, hw->tqps_num);
 741         for (i = 0; i < hw->intr_tqps_num; i++) {
 742                 /*
 743                  * Set gap limiter/rate limiter/quanity limiter algorithm
 744                  * configuration for interrupt coalesce of queue's interrupt.
 745                  */
 746                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 747                                        HNS3_TQP_INTR_GL_DEFAULT);
 748                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 749                                        HNS3_TQP_INTR_GL_DEFAULT);
 750                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 751                 /*
 752                  * QL(quantity limiter) is not used currently, just set 0 to
 753                  * close it.
 754                  */
 755                 hns3_set_queue_intr_ql(hw, i, HNS3_TQP_INTR_QL_DEFAULT);
 756
 757                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 758                                                    HNS3_RING_TYPE_TX, i);
 759                 if (ret) {
 760                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 761                                           "vector: %u, ret=%d", i, vec, ret);
 762                         return ret;
 763                 }
 764
 765                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 766                                                    HNS3_RING_TYPE_RX, i);
 767                 if (ret) {
 768                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 769                                           "vector: %u, ret=%d", i, vec, ret);
 770                         return ret;
 771                 }
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int
 778 hns3vf_dev_configure(struct rte_eth_dev *dev)
 779 {
 780         struct hns3_adapter *hns = dev->data->dev_private;
 781         struct hns3_hw *hw = &hns->hw;
 782         struct rte_eth_conf *conf = &dev->data->dev_conf;
 783         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 784         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 785         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 786         struct rte_eth_rss_conf rss_conf;
 787         bool gro_en;
 788         int ret;
 789
 790         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
 791
 792         /*
 793          * Some versions of hardware network engine does not support
 794          * individually enable/disable/reset the Tx or Rx queue. These devices
 795          * must enable/disable/reset Tx and Rx queues at the same time. When the
 796          * numbers of Tx queues allocated by upper applications are not equal to
 797          * the numbers of Rx queues, driver needs to setup fake Tx or Rx queues
 798          * to adjust numbers of Tx/Rx queues. otherwise, network engine can not
 799          * work as usual. But these fake queues are imperceptible, and can not
 800          * be used by upper applications.
 801          */
 802         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 803         if (ret) {
 804                 hns3_err(hw, "fail to set Rx/Tx fake queues, ret = %d.", ret);
 805                 hw->cfg_max_queues = 0;
 806                 return ret;
 807         }
 808
 809         hw->adapter_state = HNS3_NIC_CONFIGURING;
 810         if (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
 811                 hns3_err(hw, "setting link speed/duplex not supported");
 812                 ret = -EINVAL;
 813                 goto cfg_err;
 814         }
 815
 816         /* When RSS is not configured, redirect the packet queue 0 */
 817         if ((uint32_t)mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
 818                 conf->rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
 819                 hw->rss_dis_flag = false;
 820                 rss_conf = conf->rx_adv_conf.rss_conf;
 821                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 822                 if (ret)
 823                         goto cfg_err;
 824         }
 825
 826         ret = hns3vf_dev_mtu_set(dev, conf->rxmode.mtu);
 827         if (ret != 0)
 828                 goto cfg_err;
 829
 830         ret = hns3vf_dev_configure_vlan(dev);
 831         if (ret)
 832                 goto cfg_err;
 833
 834         /* config hardware GRO */
 835         gro_en = conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO ? true : false;
 836         ret = hns3_config_gro(hw, gro_en);
 837         if (ret)
 838                 goto cfg_err;
 839
 840         hns3_init_rx_ptype_tble(dev);
 841
 842         hw->adapter_state = HNS3_NIC_CONFIGURED;
 843         return 0;
 844
 845 cfg_err:
 846         hw->cfg_max_queues = 0;
 847         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 848         hw->adapter_state = HNS3_NIC_INITIALIZED;
 849
 850         return ret;
 851 }
 852
 853 static int
 854 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 855 {
 856         int ret;
 857
 858         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 859                                 sizeof(mtu), true, NULL, 0);
 860         if (ret)
 861                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 862
 863         return ret;
 864 }
 865
 866 static int
 867 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 868 {
 869         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 871         int ret;
 872
 873         /*
 874          * The hns3 PF/VF devices on the same port share the hardware MTU
 875          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 876          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 877          * driver, there is no need to stop the port for hns3 VF device, and the
 878          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 879          * PF's MTU.
 880          */
 881         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
 882                 hns3_err(hw, "Failed to set mtu during resetting");
 883                 return -EIO;
 884         }
 885
 886         /*
 887          * when Rx of scattered packets is off, we have some possibility of
 888          * using vector Rx process function or simple Rx functions in hns3 PMD
 889          * driver. If the input MTU is increased and the maximum length of
 890          * received packets is greater than the length of a buffer for Rx
 891          * packet, the hardware network engine needs to use multiple BDs and
 892          * buffers to store these packets. This will cause problems when still
 893          * using vector Rx process function or simple Rx function to receiving
 894          * packets. So, when Rx of scattered packets is off and device is
 895          * started, it is not permitted to increase MTU so that the maximum
 896          * length of Rx packets is greater than Rx buffer length.
 897          */
 898         if (dev->data->dev_started && !dev->data->scattered_rx &&
 899             frame_size > hw->rx_buf_len) {
 900                 hns3_err(hw, "failed to set mtu because current is "
 901                         "not scattered rx mode");
 902                 return -EOPNOTSUPP;
 903         }
 904
 905         rte_spinlock_lock(&hw->lock);
 906         ret = hns3vf_config_mtu(hw, mtu);
 907         if (ret) {
 908                 rte_spinlock_unlock(&hw->lock);
 909                 return ret;
 910         }
 911         rte_spinlock_unlock(&hw->lock);
 912
 913         return 0;
 914 }
 915
 916 static int
 917 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 918 {
 919         struct hns3_adapter *hns = eth_dev->data->dev_private;
 920         struct hns3_hw *hw = &hns->hw;
 921         uint16_t q_num = hw->tqps_num;
 922
 923         /*
 924          * In interrupt mode, 'max_rx_queues' is set based on the number of
 925          * MSI-X interrupt resources of the hardware.
 926          */
 927         if (hw->data->dev_conf.intr_conf.rxq == 1)
 928                 q_num = hw->intr_tqps_num;
 929
 930         info->max_rx_queues = q_num;
 931         info->max_tx_queues = hw->tqps_num;
 932         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 933         info->min_rx_bufsize = HNS3_MIN_BD_BUF_SIZE;
 934         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 935         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 936         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 937
 938         info->rx_offload_capa = (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
 939                                  RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
 940                                  RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
 941                                  RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
 942                                  RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 943                                  RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
 944                                  RTE_ETH_RX_OFFLOAD_SCATTER |
 945                                  RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
 946                                  RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
 947                                  RTE_ETH_RX_OFFLOAD_RSS_HASH |
 948                                  RTE_ETH_RX_OFFLOAD_TCP_LRO);
 949         info->tx_offload_capa = (RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 950                                  RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
 951                                  RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
 952                                  RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
 953                                  RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
 954                                  RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
 955                                  RTE_ETH_TX_OFFLOAD_TCP_TSO |
 956                                  RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
 957                                  RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
 958                                  RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
 959                                  RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE |
 960                                  hns3_txvlan_cap_get(hw));
 961
 962         if (hns3_dev_get_support(hw, OUTER_UDP_CKSUM))
 963                 info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM;
 964
 965         if (hns3_dev_get_support(hw, INDEP_TXRX))
 966                 info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 967                                  RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 968
 969         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 970                 .nb_max = HNS3_MAX_RING_DESC,
 971                 .nb_min = HNS3_MIN_RING_DESC,
 972                 .nb_align = HNS3_ALIGN_RING_DESC,
 973         };
 974
 975         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 976                 .nb_max = HNS3_MAX_RING_DESC,
 977                 .nb_min = HNS3_MIN_RING_DESC,
 978                 .nb_align = HNS3_ALIGN_RING_DESC,
 979                 .nb_seg_max = HNS3_MAX_TSO_BD_PER_PKT,
 980                 .nb_mtu_seg_max = hw->max_non_tso_bd_num,
 981         };
 982
 983         info->default_rxconf = (struct rte_eth_rxconf) {
 984                 .rx_free_thresh = HNS3_DEFAULT_RX_FREE_THRESH,
 985                 /*
 986                  * If there are no available Rx buffer descriptors, incoming
 987                  * packets are always dropped by hardware based on hns3 network
 988                  * engine.
 989                  */
 990                 .rx_drop_en = 1,
 991                 .offloads = 0,
 992         };
 993         info->default_txconf = (struct rte_eth_txconf) {
 994                 .tx_rs_thresh = HNS3_DEFAULT_TX_RS_THRESH,
 995                 .offloads = 0,
 996         };
 997
 998         info->reta_size = hw->rss_ind_tbl_size;
 999         info->hash_key_size = HNS3_RSS_KEY_SIZE;
1000         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
1001
1002         info->default_rxportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1003         info->default_txportconf.burst_size = HNS3_DEFAULT_PORT_CONF_BURST_SIZE;
1004         info->default_rxportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1005         info->default_txportconf.nb_queues = HNS3_DEFAULT_PORT_CONF_QUEUES_NUM;
1006         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1007         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
1008
1009         return 0;
1010 }
1011
1012 static void
1013 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
1014 {
1015         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
1016 }
1017
1018 static void
1019 hns3vf_disable_irq0(struct hns3_hw *hw)
1020 {
1021         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
1022 }
1023
1024 static void
1025 hns3vf_enable_irq0(struct hns3_hw *hw)
1026 {
1027         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
1028 }
1029
1030 static enum hns3vf_evt_cause
1031 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
1032 {
1033         struct hns3_hw *hw = &hns->hw;
1034         enum hns3vf_evt_cause ret;
1035         uint32_t cmdq_stat_reg;
1036         uint32_t rst_ing_reg;
1037         uint32_t val;
1038
1039         /* Fetch the events from their corresponding regs */
1040         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
1041         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
1042                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
1043                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
1044                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
1045                 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
1046                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
1047                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
1048                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
1049                 if (clearval) {
1050                         hw->reset.stats.global_cnt++;
1051                         hns3_warn(hw, "Global reset detected, clear reset status");
1052                 } else {
1053                         hns3_schedule_delayed_reset(hns);
1054                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1055                 }
1056
1057                 ret = HNS3VF_VECTOR0_EVENT_RST;
1058                 goto out;
1059         }
1060
1061         /* Check for vector0 mailbox(=CMDQ RX) event source */
1062         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1063                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1064                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1065                 goto out;
1066         }
1067
1068         val = 0;
1069         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1070 out:
1071         if (clearval)
1072                 *clearval = val;
1073         return ret;
1074 }
1075
1076 static void
1077 hns3vf_interrupt_handler(void *param)
1078 {
1079         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1080         struct hns3_adapter *hns = dev->data->dev_private;
1081         struct hns3_hw *hw = &hns->hw;
1082         enum hns3vf_evt_cause event_cause;
1083         uint32_t clearval;
1084
1085         /* Disable interrupt */
1086         hns3vf_disable_irq0(hw);
1087
1088         /* Read out interrupt causes */
1089         event_cause = hns3vf_check_event_cause(hns, &clearval);
1090         /* Clear interrupt causes */
1091         hns3vf_clear_event_cause(hw, clearval);
1092
1093         switch (event_cause) {
1094         case HNS3VF_VECTOR0_EVENT_RST:
1095                 hns3_schedule_reset(hns);
1096                 break;
1097         case HNS3VF_VECTOR0_EVENT_MBX:
1098                 hns3_dev_handle_mbx_msg(hw);
1099                 break;
1100         default:
1101                 break;
1102         }
1103
1104         /* Enable interrupt */
1105         hns3vf_enable_irq0(hw);
1106 }
1107
1108 static void
1109 hns3vf_set_default_dev_specifications(struct hns3_hw *hw)
1110 {
1111         hw->max_non_tso_bd_num = HNS3_MAX_NON_TSO_BD_PER_PKT;
1112         hw->rss_ind_tbl_size = HNS3_RSS_IND_TBL_SIZE;
1113         hw->rss_key_size = HNS3_RSS_KEY_SIZE;
1114         hw->intr.int_ql_max = HNS3_INTR_QL_NONE;
1115 }
1116
1117 static void
1118 hns3vf_parse_dev_specifications(struct hns3_hw *hw, struct hns3_cmd_desc *desc)
1119 {
1120         struct hns3_dev_specs_0_cmd *req0;
1121
1122         req0 = (struct hns3_dev_specs_0_cmd *)desc[0].data;
1123
1124         hw->max_non_tso_bd_num = req0->max_non_tso_bd_num;
1125         hw->rss_ind_tbl_size = rte_le_to_cpu_16(req0->rss_ind_tbl_size);
1126         hw->rss_key_size = rte_le_to_cpu_16(req0->rss_key_size);
1127         hw->intr.int_ql_max = rte_le_to_cpu_16(req0->intr_ql_max);
1128 }
1129
1130 static int
1131 hns3vf_check_dev_specifications(struct hns3_hw *hw)
1132 {
1133         if (hw->rss_ind_tbl_size == 0 ||
1134             hw->rss_ind_tbl_size > HNS3_RSS_IND_TBL_SIZE_MAX) {
1135                 hns3_warn(hw, "the size of hash lookup table configured (%u)"
1136                               " exceeds the maximum(%u)", hw->rss_ind_tbl_size,
1137                               HNS3_RSS_IND_TBL_SIZE_MAX);
1138                 return -EINVAL;
1139         }
1140
1141         return 0;
1142 }
1143
1144 static int
1145 hns3vf_query_dev_specifications(struct hns3_hw *hw)
1146 {
1147         struct hns3_cmd_desc desc[HNS3_QUERY_DEV_SPECS_BD_NUM];
1148         int ret;
1149         int i;
1150
1151         for (i = 0; i < HNS3_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
1152                 hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS,
1153                                           true);
1154                 desc[i].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT);
1155         }
1156         hns3_cmd_setup_basic_desc(&desc[i], HNS3_OPC_QUERY_DEV_SPECS, true);
1157
1158         ret = hns3_cmd_send(hw, desc, HNS3_QUERY_DEV_SPECS_BD_NUM);
1159         if (ret)
1160                 return ret;
1161
1162         hns3vf_parse_dev_specifications(hw, desc);
1163
1164         return hns3vf_check_dev_specifications(hw);
1165 }
1166
1167 void
1168 hns3vf_update_push_lsc_cap(struct hns3_hw *hw, bool supported)
1169 {
1170         uint16_t val = supported ? HNS3_PF_PUSH_LSC_CAP_SUPPORTED :
1171                                    HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1172         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1173         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1174
1175         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1176                 __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1177                                           __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1178 }
1179
1180 static void
1181 hns3vf_get_push_lsc_cap(struct hns3_hw *hw)
1182 {
1183 #define HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS      500
1184
1185         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1186         int32_t remain_ms = HNS3_CHECK_PUSH_LSC_CAP_TIMEOUT_MS;
1187         uint16_t val = HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED;
1188         uint16_t exp = HNS3_PF_PUSH_LSC_CAP_UNKNOWN;
1189         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1190
1191         __atomic_store_n(&vf->pf_push_lsc_cap, HNS3_PF_PUSH_LSC_CAP_UNKNOWN,
1192                          __ATOMIC_RELEASE);
1193
1194         (void)hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1195                                 NULL, 0);
1196
1197         while (remain_ms > 0) {
1198                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
1199                 if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) !=
1200                         HNS3_PF_PUSH_LSC_CAP_UNKNOWN)
1201                         break;
1202                 remain_ms--;
1203         }
1204
1205         /*
1206          * When exit above loop, the pf_push_lsc_cap could be one of the three
1207          * state: unknown (means pf not ack), not_supported, supported.
1208          * Here config it as 'not_supported' when it's 'unknown' state.
1209          */
1210         __atomic_compare_exchange(&vf->pf_push_lsc_cap, &exp, &val, 0,
1211                                   __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE);
1212
1213         if (__atomic_load_n(&vf->pf_push_lsc_cap, __ATOMIC_ACQUIRE) ==
1214                 HNS3_PF_PUSH_LSC_CAP_SUPPORTED) {
1215                 hns3_info(hw, "detect PF support push link status change!");
1216         } else {
1217                 /*
1218                  * Framework already set RTE_ETH_DEV_INTR_LSC bit because driver
1219                  * declared RTE_PCI_DRV_INTR_LSC in drv_flags. So here cleared
1220                  * the RTE_ETH_DEV_INTR_LSC capability.
1221                  */
1222                 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
1223         }
1224 }
1225
1226 static int
1227 hns3vf_get_capability(struct hns3_hw *hw)
1228 {
1229         struct rte_pci_device *pci_dev;
1230         struct rte_eth_dev *eth_dev;
1231         uint8_t revision;
1232         int ret;
1233
1234         eth_dev = &rte_eth_devices[hw->data->port_id];
1235         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1236
1237         /* Get PCI revision id */
1238         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
1239                                   HNS3_PCI_REVISION_ID);
1240         if (ret != HNS3_PCI_REVISION_ID_LEN) {
1241                 PMD_INIT_LOG(ERR, "failed to read pci revision id, ret = %d",
1242                              ret);
1243                 return -EIO;
1244         }
1245         hw->revision = revision;
1246
1247         if (revision < PCI_REVISION_ID_HIP09_A) {
1248                 hns3vf_set_default_dev_specifications(hw);
1249                 hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_RSV_ONE;
1250                 hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_2US;
1251                 hw->tso_mode = HNS3_TSO_SW_CAL_PSEUDO_H_CSUM;
1252                 hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE1;
1253                 hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN;
1254                 hw->rss_info.ipv6_sctp_offload_supported = false;
1255                 hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE;
1256                 return 0;
1257         }
1258
1259         ret = hns3vf_query_dev_specifications(hw);
1260         if (ret) {
1261                 PMD_INIT_LOG(ERR,
1262                              "failed to query dev specifications, ret = %d",
1263                              ret);
1264                 return ret;
1265         }
1266
1267         hw->intr.mapping_mode = HNS3_INTR_MAPPING_VEC_ALL;
1268         hw->intr.gl_unit = HNS3_INTR_COALESCE_GL_UINT_1US;
1269         hw->tso_mode = HNS3_TSO_HW_CAL_PSEUDO_H_CSUM;
1270         hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2;
1271         hw->min_tx_pkt_len = HNS3_HIP09_MIN_TX_PKT_LEN;
1272         hw->rss_info.ipv6_sctp_offload_supported = true;
1273         hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE;
1274
1275         return 0;
1276 }
1277
1278 static int
1279 hns3vf_check_tqp_info(struct hns3_hw *hw)
1280 {
1281         if (hw->tqps_num == 0) {
1282                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(0) from PF.");
1283                 return -EINVAL;
1284         }
1285
1286         if (hw->rss_size_max == 0) {
1287                 PMD_INIT_LOG(ERR, "Get invalid rss_size_max(0) from PF.");
1288                 return -EINVAL;
1289         }
1290
1291         hw->tqps_num = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1292
1293         return 0;
1294 }
1295
1296 static int
1297 hns3vf_get_port_base_vlan_filter_state(struct hns3_hw *hw)
1298 {
1299         uint8_t resp_msg;
1300         int ret;
1301
1302         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1303                                 HNS3_MBX_GET_PORT_BASE_VLAN_STATE, NULL, 0,
1304                                 true, &resp_msg, sizeof(resp_msg));
1305         if (ret) {
1306                 if (ret == -ETIME) {
1307                         /*
1308                          * Getting current port based VLAN state from PF driver
1309                          * will not affect VF driver's basic function. Because
1310                          * the VF driver relies on hns3 PF kernel ether driver,
1311                          * to avoid introducing compatibility issues with older
1312                          * version of PF driver, no failure will be returned
1313                          * when the return value is ETIME. This return value has
1314                          * the following scenarios:
1315                          * 1) Firmware didn't return the results in time
1316                          * 2) the result return by firmware is timeout
1317                          * 3) the older version of kernel side PF driver does
1318                          *    not support this mailbox message.
1319                          * For scenarios 1 and 2, it is most likely that a
1320                          * hardware error has occurred, or a hardware reset has
1321                          * occurred. In this case, these errors will be caught
1322                          * by other functions.
1323                          */
1324                         PMD_INIT_LOG(WARNING,
1325                                 "failed to get PVID state for timeout, maybe "
1326                                 "kernel side PF driver doesn't support this "
1327                                 "mailbox message, or firmware didn't respond.");
1328                         resp_msg = HNS3_PORT_BASE_VLAN_DISABLE;
1329                 } else {
1330                         PMD_INIT_LOG(ERR, "failed to get port based VLAN state,"
1331                                 " ret = %d", ret);
1332                         return ret;
1333                 }
1334         }
1335         hw->port_base_vlan_cfg.state = resp_msg ?
1336                 HNS3_PORT_BASE_VLAN_ENABLE : HNS3_PORT_BASE_VLAN_DISABLE;
1337         return 0;
1338 }
1339
1340 static int
1341 hns3vf_get_queue_info(struct hns3_hw *hw)
1342 {
1343 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1344         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1345         int ret;
1346
1347         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1348                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1349         if (ret) {
1350                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1351                 return ret;
1352         }
1353
1354         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1355         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1356
1357         return hns3vf_check_tqp_info(hw);
1358 }
1359
1360 static int
1361 hns3vf_get_queue_depth(struct hns3_hw *hw)
1362 {
1363 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1364         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1365         int ret;
1366
1367         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1368                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1369         if (ret) {
1370                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1371                              ret);
1372                 return ret;
1373         }
1374
1375         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1376         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1377
1378         return 0;
1379 }
1380
1381 static void
1382 hns3vf_update_caps(struct hns3_hw *hw, uint32_t caps)
1383 {
1384         if (hns3_get_bit(caps, HNS3VF_CAPS_VLAN_FLT_MOD_B))
1385                 hns3_set_bit(hw->capability,
1386                                 HNS3_DEV_SUPPORT_VF_VLAN_FLT_MOD_B, 1);
1387 }
1388
1389 static int
1390 hns3vf_get_num_tc(struct hns3_hw *hw)
1391 {
1392         uint8_t num_tc = 0;
1393         uint32_t i;
1394
1395         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
1396                 if (hw->hw_tc_map & BIT(i))
1397                         num_tc++;
1398         }
1399         return num_tc;
1400 }
1401
1402 static int
1403 hns3vf_get_basic_info(struct hns3_hw *hw)
1404 {
1405         uint8_t resp_msg[HNS3_MBX_MAX_RESP_DATA_SIZE];
1406         struct hns3_basic_info *basic_info;
1407         int ret;
1408
1409         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_BASIC_INFO, 0, NULL, 0,
1410                                 true, resp_msg, sizeof(resp_msg));
1411         if (ret) {
1412                 hns3_err(hw, "failed to get basic info from PF, ret = %d.",
1413                                 ret);
1414                 return ret;
1415         }
1416
1417         basic_info = (struct hns3_basic_info *)resp_msg;
1418         hw->hw_tc_map = basic_info->hw_tc_map;
1419         hw->num_tc = hns3vf_get_num_tc(hw);
1420         hw->pf_vf_if_version = basic_info->pf_vf_if_version;
1421         hns3vf_update_caps(hw, basic_info->caps);
1422
1423         return 0;
1424 }
1425
1426 static int
1427 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1428 {
1429         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1430         int ret;
1431
1432         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1433                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1434         if (ret) {
1435                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1436                 return ret;
1437         }
1438
1439         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1440
1441         return 0;
1442 }
1443
1444 static int
1445 hns3vf_get_configuration(struct hns3_hw *hw)
1446 {
1447         int ret;
1448
1449         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1450         hw->rss_dis_flag = false;
1451
1452         /* Get device capability */
1453         ret = hns3vf_get_capability(hw);
1454         if (ret) {
1455                 PMD_INIT_LOG(ERR, "failed to get device capability: %d.", ret);
1456                 return ret;
1457         }
1458
1459         hns3vf_get_push_lsc_cap(hw);
1460
1461         /* Get basic info from PF */
1462         ret = hns3vf_get_basic_info(hw);
1463         if (ret)
1464                 return ret;
1465
1466         /* Get queue configuration from PF */
1467         ret = hns3vf_get_queue_info(hw);
1468         if (ret)
1469                 return ret;
1470
1471         /* Get queue depth info from PF */
1472         ret = hns3vf_get_queue_depth(hw);
1473         if (ret)
1474                 return ret;
1475
1476         /* Get user defined VF MAC addr from PF */
1477         ret = hns3vf_get_host_mac_addr(hw);
1478         if (ret)
1479                 return ret;
1480
1481         return hns3vf_get_port_base_vlan_filter_state(hw);
1482 }
1483
1484 static int
1485 hns3vf_set_tc_queue_mapping(struct hns3_adapter *hns, uint16_t nb_rx_q,
1486                             uint16_t nb_tx_q)
1487 {
1488         struct hns3_hw *hw = &hns->hw;
1489
1490         return hns3_queue_to_tc_mapping(hw, nb_rx_q, nb_tx_q);
1491 }
1492
1493 static void
1494 hns3vf_request_link_info(struct hns3_hw *hw)
1495 {
1496         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1497         bool send_req;
1498         int ret;
1499
1500         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
1501                 return;
1502
1503         send_req = vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_NOT_SUPPORTED ||
1504                    vf->req_link_info_cnt > 0;
1505         if (!send_req)
1506                 return;
1507
1508         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1509                                 NULL, 0);
1510         if (ret) {
1511                 hns3_err(hw, "failed to fetch link status, ret = %d", ret);
1512                 return;
1513         }
1514
1515         if (vf->req_link_info_cnt > 0)
1516                 vf->req_link_info_cnt--;
1517 }
1518
1519 void
1520 hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,
1521                           uint32_t link_speed, uint8_t link_duplex)
1522 {
1523         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1524         struct hns3_vf *vf = HNS3_DEV_HW_TO_VF(hw);
1525         struct hns3_mac *mac = &hw->mac;
1526         int ret;
1527
1528         /*
1529          * PF kernel driver may push link status when VF driver is in resetting,
1530          * driver will stop polling job in this case, after resetting done
1531          * driver will start polling job again.
1532          * When polling job started, driver will get initial link status by
1533          * sending request to PF kernel driver, then could update link status by
1534          * process PF kernel driver's link status mailbox message.
1535          */
1536         if (!__atomic_load_n(&vf->poll_job_started, __ATOMIC_RELAXED))
1537                 return;
1538
1539         if (hw->adapter_state != HNS3_NIC_STARTED)
1540                 return;
1541
1542         mac->link_status = link_status;
1543         mac->link_speed = link_speed;
1544         mac->link_duplex = link_duplex;
1545         ret = hns3vf_dev_link_update(dev, 0);
1546         if (ret == 0 && dev->data->dev_conf.intr_conf.lsc != 0)
1547                 hns3_start_report_lse(dev);
1548 }
1549
1550 static int
1551 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1552 {
1553 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1554         struct hns3_hw *hw = &hns->hw;
1555         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1556         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1557         uint8_t is_kill = on ? 0 : 1;
1558
1559         msg_data[0] = is_kill;
1560         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1561         memcpy(&msg_data[3], &proto, sizeof(proto));
1562
1563         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1564                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1565                                  0);
1566 }
1567
1568 static int
1569 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1570 {
1571         struct hns3_adapter *hns = dev->data->dev_private;
1572         struct hns3_hw *hw = &hns->hw;
1573         int ret;
1574
1575         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1576                 hns3_err(hw,
1577                          "vf set vlan id failed during resetting, vlan_id =%u",
1578                          vlan_id);
1579                 return -EIO;
1580         }
1581         rte_spinlock_lock(&hw->lock);
1582         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1583         rte_spinlock_unlock(&hw->lock);
1584         if (ret)
1585                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1586                          vlan_id, ret);
1587
1588         return ret;
1589 }
1590
1591 static int
1592 hns3vf_en_vlan_filter(struct hns3_hw *hw, bool enable)
1593 {
1594         uint8_t msg_data;
1595         int ret;
1596
1597         if (!hns3_dev_get_support(hw, VF_VLAN_FLT_MOD))
1598                 return 0;
1599
1600         msg_data = enable ? 1 : 0;
1601         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN,
1602                         HNS3_MBX_ENABLE_VLAN_FILTER, &msg_data,
1603                         sizeof(msg_data), true, NULL, 0);
1604         if (ret)
1605                 hns3_err(hw, "%s vlan filter failed, ret = %d.",
1606                                 enable ? "enable" : "disable", ret);
1607
1608         return ret;
1609 }
1610
1611 static int
1612 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1613 {
1614         uint8_t msg_data;
1615         int ret;
1616
1617         msg_data = enable ? 1 : 0;
1618         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1619                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1620         if (ret)
1621                 hns3_err(hw, "vf %s strip failed, ret = %d.",
1622                                 enable ? "enable" : "disable", ret);
1623
1624         return ret;
1625 }
1626
1627 static int
1628 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1629 {
1630         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1631         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1632         unsigned int tmp_mask;
1633         int ret = 0;
1634
1635         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED)) {
1636                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1637                              "mask = 0x%x", mask);
1638                 return -EIO;
1639         }
1640
1641         tmp_mask = (unsigned int)mask;
1642
1643         if (tmp_mask & RTE_ETH_VLAN_FILTER_MASK) {
1644                 rte_spinlock_lock(&hw->lock);
1645                 /* Enable or disable VLAN filter */
1646                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1647                         ret = hns3vf_en_vlan_filter(hw, true);
1648                 else
1649                         ret = hns3vf_en_vlan_filter(hw, false);
1650                 rte_spinlock_unlock(&hw->lock);
1651                 if (ret)
1652                         return ret;
1653         }
1654
1655         /* Vlan stripping setting */
1656         if (tmp_mask & RTE_ETH_VLAN_STRIP_MASK) {
1657                 rte_spinlock_lock(&hw->lock);
1658                 /* Enable or disable VLAN stripping */
1659                 if (dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1660                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1661                 else
1662                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1663                 rte_spinlock_unlock(&hw->lock);
1664         }
1665
1666         return ret;
1667 }
1668
1669 static int
1670 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1671 {
1672         struct rte_vlan_filter_conf *vfc;
1673         struct hns3_hw *hw = &hns->hw;
1674         uint16_t vlan_id;
1675         uint64_t vbit;
1676         uint64_t ids;
1677         int ret = 0;
1678         uint32_t i;
1679
1680         vfc = &hw->data->vlan_filter_conf;
1681         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1682                 if (vfc->ids[i] == 0)
1683                         continue;
1684                 ids = vfc->ids[i];
1685                 while (ids) {
1686                         /*
1687                          * 64 means the num bits of ids, one bit corresponds to
1688                          * one vlan id
1689                          */
1690                         vlan_id = 64 * i;
1691                         /* count trailing zeroes */
1692                         vbit = ~ids & (ids - 1);
1693                         /* clear least significant bit set */
1694                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1695                         for (; vbit;) {
1696                                 vbit >>= 1;
1697                                 vlan_id++;
1698                         }
1699                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1700                         if (ret) {
1701                                 hns3_err(hw,
1702                                          "VF handle vlan table failed, ret =%d, on = %d",
1703                                          ret, on);
1704                                 return ret;
1705                         }
1706                 }
1707         }
1708
1709         return ret;
1710 }
1711
1712 static int
1713 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1714 {
1715         return hns3vf_handle_all_vlan_table(hns, 0);
1716 }
1717
1718 static int
1719 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1720 {
1721         struct hns3_hw *hw = &hns->hw;
1722         struct rte_eth_conf *dev_conf;
1723         bool en;
1724         int ret;
1725
1726         dev_conf = &hw->data->dev_conf;
1727         en = dev_conf->rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP ? true
1728                                                                    : false;
1729         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1730         if (ret)
1731                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1732                          ret);
1733         return ret;
1734 }
1735
1736 static int
1737 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1738 {
1739         struct hns3_adapter *hns = dev->data->dev_private;
1740         struct rte_eth_dev_data *data = dev->data;
1741         struct hns3_hw *hw = &hns->hw;
1742         int ret;
1743
1744         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1745             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1746             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1747                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1748                               "or hw_vlan_insert_pvid is not support!");
1749         }
1750
1751         /* Apply vlan offload setting */
1752         ret = hns3vf_vlan_offload_set(dev, RTE_ETH_VLAN_STRIP_MASK |
1753                                         RTE_ETH_VLAN_FILTER_MASK);
1754         if (ret)
1755                 hns3_err(hw, "dev config vlan offload failed, ret = %d.", ret);
1756
1757         return ret;
1758 }
1759
1760 static int
1761 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1762 {
1763         uint8_t msg_data;
1764
1765         msg_data = alive ? 1 : 0;
1766         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1767                                  sizeof(msg_data), false, NULL, 0);
1768 }
1769
1770 static void
1771 hns3vf_keep_alive_handler(void *param)
1772 {
1773         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1774         struct hns3_adapter *hns = eth_dev->data->dev_private;
1775         struct hns3_hw *hw = &hns->hw;
1776         int ret;
1777
1778         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1779                                 false, NULL, 0);
1780         if (ret)
1781                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1782                          ret);
1783
1784         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1785                           eth_dev);
1786 }
1787
1788 static void
1789 hns3vf_service_handler(void *param)
1790 {
1791         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1792         struct hns3_adapter *hns = eth_dev->data->dev_private;
1793         struct hns3_hw *hw = &hns->hw;
1794
1795         /*
1796          * The query link status and reset processing are executed in the
1797          * interrupt thread. When the IMP reset occurs, IMP will not respond,
1798          * and the query operation will timeout after 30ms. In the case of
1799          * multiple PF/VFs, each query failure timeout causes the IMP reset
1800          * interrupt to fail to respond within 100ms.
1801          * Before querying the link status, check whether there is a reset
1802          * pending, and if so, abandon the query.
1803          */
1804         if (!hns3vf_is_reset_pending(hns))
1805                 hns3vf_request_link_info(hw);
1806         else
1807                 hns3_warn(hw, "Cancel the query when reset is pending");
1808
1809         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1810                           eth_dev);
1811 }
1812
1813 static void
1814 hns3vf_start_poll_job(struct rte_eth_dev *dev)
1815 {
1816 #define HNS3_REQUEST_LINK_INFO_REMAINS_CNT      3
1817
1818         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1819
1820         if (vf->pf_push_lsc_cap == HNS3_PF_PUSH_LSC_CAP_SUPPORTED)
1821                 vf->req_link_info_cnt = HNS3_REQUEST_LINK_INFO_REMAINS_CNT;
1822
1823         __atomic_store_n(&vf->poll_job_started, 1, __ATOMIC_RELAXED);
1824
1825         hns3vf_service_handler(dev);
1826 }
1827
1828 static void
1829 hns3vf_stop_poll_job(struct rte_eth_dev *dev)
1830 {
1831         struct hns3_vf *vf = HNS3_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1832
1833         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1834
1835         __atomic_store_n(&vf->poll_job_started, 0, __ATOMIC_RELAXED);
1836 }
1837
1838 static int
1839 hns3_query_vf_resource(struct hns3_hw *hw)
1840 {
1841         struct hns3_vf_res_cmd *req;
1842         struct hns3_cmd_desc desc;
1843         uint16_t num_msi;
1844         int ret;
1845
1846         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1847         ret = hns3_cmd_send(hw, &desc, 1);
1848         if (ret) {
1849                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1850                 return ret;
1851         }
1852
1853         req = (struct hns3_vf_res_cmd *)desc.data;
1854         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1855                                  HNS3_VF_VEC_NUM_M, HNS3_VF_VEC_NUM_S);
1856         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1857                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1858                          num_msi, HNS3_MIN_VECTOR_NUM);
1859                 return -EINVAL;
1860         }
1861
1862         hw->num_msi = num_msi;
1863
1864         return 0;
1865 }
1866
1867 static int
1868 hns3vf_init_hardware(struct hns3_adapter *hns)
1869 {
1870         struct hns3_hw *hw = &hns->hw;
1871         uint16_t mtu = hw->data->mtu;
1872         int ret;
1873
1874         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1875         if (ret)
1876                 return ret;
1877
1878         ret = hns3vf_config_mtu(hw, mtu);
1879         if (ret)
1880                 goto err_init_hardware;
1881
1882         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1883         if (ret) {
1884                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1885                 goto err_init_hardware;
1886         }
1887
1888         ret = hns3_config_gro(hw, false);
1889         if (ret) {
1890                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1891                 goto err_init_hardware;
1892         }
1893
1894         /*
1895          * In the initialization clearing the all hardware mapping relationship
1896          * configurations between queues and interrupt vectors is needed, so
1897          * some error caused by the residual configurations, such as the
1898          * unexpected interrupt, can be avoid.
1899          */
1900         ret = hns3vf_init_ring_with_vector(hw);
1901         if (ret) {
1902                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1903                 goto err_init_hardware;
1904         }
1905
1906         return 0;
1907
1908 err_init_hardware:
1909         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1910         return ret;
1911 }
1912
1913 static int
1914 hns3vf_clear_vport_list(struct hns3_hw *hw)
1915 {
1916         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1917                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1918                                  NULL, 0);
1919 }
1920
1921 static int
1922 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1923 {
1924         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1925         struct hns3_adapter *hns = eth_dev->data->dev_private;
1926         struct hns3_hw *hw = &hns->hw;
1927         int ret;
1928
1929         PMD_INIT_FUNC_TRACE();
1930
1931         /* Get hardware io base address from pcie BAR2 IO space */
1932         hw->io_base = pci_dev->mem_resource[2].addr;
1933
1934         /* Firmware command queue initialize */
1935         ret = hns3_cmd_init_queue(hw);
1936         if (ret) {
1937                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1938                 goto err_cmd_init_queue;
1939         }
1940
1941         /* Firmware command initialize */
1942         ret = hns3_cmd_init(hw);
1943         if (ret) {
1944                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1945                 goto err_cmd_init;
1946         }
1947
1948         hns3_tx_push_init(eth_dev);
1949
1950         /* Get VF resource */
1951         ret = hns3_query_vf_resource(hw);
1952         if (ret)
1953                 goto err_cmd_init;
1954
1955         rte_spinlock_init(&hw->mbx_resp.lock);
1956
1957         hns3vf_clear_event_cause(hw, 0);
1958
1959         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1960                                          hns3vf_interrupt_handler, eth_dev);
1961         if (ret) {
1962                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1963                 goto err_intr_callback_register;
1964         }
1965
1966         /* Enable interrupt */
1967         rte_intr_enable(&pci_dev->intr_handle);
1968         hns3vf_enable_irq0(hw);
1969
1970         /* Get configuration from PF */
1971         ret = hns3vf_get_configuration(hw);
1972         if (ret) {
1973                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1974                 goto err_get_config;
1975         }
1976
1977         ret = hns3_tqp_stats_init(hw);
1978         if (ret)
1979                 goto err_get_config;
1980
1981         /* Hardware statistics of imissed registers cleared. */
1982         ret = hns3_update_imissed_stats(hw, true);
1983         if (ret) {
1984                 hns3_err(hw, "clear imissed stats failed, ret = %d", ret);
1985                 goto err_set_tc_queue;
1986         }
1987
1988         ret = hns3vf_set_tc_queue_mapping(hns, hw->tqps_num, hw->tqps_num);
1989         if (ret) {
1990                 PMD_INIT_LOG(ERR, "failed to set tc info, ret = %d.", ret);
1991                 goto err_set_tc_queue;
1992         }
1993
1994         ret = hns3vf_clear_vport_list(hw);
1995         if (ret) {
1996                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1997                 goto err_set_tc_queue;
1998         }
1999
2000         ret = hns3vf_init_hardware(hns);
2001         if (ret)
2002                 goto err_set_tc_queue;
2003
2004         hns3_rss_set_default_args(hw);
2005
2006         ret = hns3vf_set_alive(hw, true);
2007         if (ret) {
2008                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
2009                 goto err_set_tc_queue;
2010         }
2011
2012         return 0;
2013
2014 err_set_tc_queue:
2015         hns3_tqp_stats_uninit(hw);
2016
2017 err_get_config:
2018         hns3vf_disable_irq0(hw);
2019         rte_intr_disable(&pci_dev->intr_handle);
2020         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2021                              eth_dev);
2022 err_intr_callback_register:
2023 err_cmd_init:
2024         hns3_cmd_uninit(hw);
2025         hns3_cmd_destroy_queue(hw);
2026 err_cmd_init_queue:
2027         hw->io_base = NULL;
2028
2029         return ret;
2030 }
2031
2032 static void
2033 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
2034 {
2035         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2036         struct hns3_adapter *hns = eth_dev->data->dev_private;
2037         struct hns3_hw *hw = &hns->hw;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         hns3_rss_uninit(hns);
2042         (void)hns3_config_gro(hw, false);
2043         (void)hns3vf_set_alive(hw, false);
2044         (void)hns3vf_set_promisc_mode(hw, false, false, false);
2045         hns3_flow_uninit(eth_dev);
2046         hns3_tqp_stats_uninit(hw);
2047         hns3vf_disable_irq0(hw);
2048         rte_intr_disable(&pci_dev->intr_handle);
2049         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
2050                              eth_dev);
2051         hns3_cmd_uninit(hw);
2052         hns3_cmd_destroy_queue(hw);
2053         hw->io_base = NULL;
2054 }
2055
2056 static int
2057 hns3vf_do_stop(struct hns3_adapter *hns)
2058 {
2059         struct hns3_hw *hw = &hns->hw;
2060         int ret;
2061
2062         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2063
2064         /*
2065          * The "hns3vf_do_stop" function will also be called by .stop_service to
2066          * prepare reset. At the time of global or IMP reset, the command cannot
2067          * be sent to stop the tx/rx queues. The mbuf in Tx/Rx queues may be
2068          * accessed during the reset process. So the mbuf can not be released
2069          * during reset and is required to be released after the reset is
2070          * completed.
2071          */
2072         if (__atomic_load_n(&hw->reset.resetting,  __ATOMIC_RELAXED) == 0)
2073                 hns3_dev_release_mbufs(hns);
2074
2075         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0) {
2076                 hns3vf_configure_mac_addr(hns, true);
2077                 ret = hns3_reset_all_tqps(hns);
2078                 if (ret) {
2079                         hns3_err(hw, "failed to reset all queues ret = %d",
2080                                  ret);
2081                         return ret;
2082                 }
2083         }
2084         return 0;
2085 }
2086
2087 static void
2088 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
2089 {
2090         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2091         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2092         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2093         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2094         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2095         uint16_t q_id;
2096
2097         if (dev->data->dev_conf.intr_conf.rxq == 0)
2098                 return;
2099
2100         /* unmap the ring with vector */
2101         if (rte_intr_allow_others(intr_handle)) {
2102                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2103                 base = RTE_INTR_VEC_RXTX_OFFSET;
2104         }
2105         if (rte_intr_dp_is_en(intr_handle)) {
2106                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2107                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
2108                                                            HNS3_RING_TYPE_RX,
2109                                                            q_id);
2110                         if (vec < base + intr_handle->nb_efd - 1)
2111                                 vec++;
2112                 }
2113         }
2114         /* Clean datapath event and queue/vec mapping */
2115         rte_intr_efd_disable(intr_handle);
2116         if (intr_handle->intr_vec) {
2117                 rte_free(intr_handle->intr_vec);
2118                 intr_handle->intr_vec = NULL;
2119         }
2120 }
2121
2122 static int
2123 hns3vf_dev_stop(struct rte_eth_dev *dev)
2124 {
2125         struct hns3_adapter *hns = dev->data->dev_private;
2126         struct hns3_hw *hw = &hns->hw;
2127
2128         PMD_INIT_FUNC_TRACE();
2129         dev->data->dev_started = 0;
2130
2131         hw->adapter_state = HNS3_NIC_STOPPING;
2132         hns3_set_rxtx_function(dev);
2133         rte_wmb();
2134         /* Disable datapath on secondary process. */
2135         hns3_mp_req_stop_rxtx(dev);
2136         /* Prevent crashes when queues are still in use. */
2137         rte_delay_ms(hw->cfg_max_queues);
2138
2139         rte_spinlock_lock(&hw->lock);
2140         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED) == 0) {
2141                 hns3_stop_tqps(hw);
2142                 hns3vf_do_stop(hns);
2143                 hns3vf_unmap_rx_interrupt(dev);
2144                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2145         }
2146         hns3_rx_scattered_reset(dev);
2147         hns3vf_stop_poll_job(dev);
2148         hns3_stop_report_lse(dev);
2149         rte_spinlock_unlock(&hw->lock);
2150
2151         return 0;
2152 }
2153
2154 static int
2155 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
2156 {
2157         struct hns3_adapter *hns = eth_dev->data->dev_private;
2158         struct hns3_hw *hw = &hns->hw;
2159         int ret = 0;
2160
2161         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2162                 return 0;
2163
2164         if (hw->adapter_state == HNS3_NIC_STARTED)
2165                 ret = hns3vf_dev_stop(eth_dev);
2166
2167         hw->adapter_state = HNS3_NIC_CLOSING;
2168         hns3_reset_abort(hns);
2169         hw->adapter_state = HNS3_NIC_CLOSED;
2170         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
2171         hns3vf_configure_all_mc_mac_addr(hns, true);
2172         hns3vf_remove_all_vlan_table(hns);
2173         hns3vf_uninit_vf(eth_dev);
2174         hns3_free_all_queues(eth_dev);
2175         rte_free(hw->reset.wait_data);
2176         hns3_mp_uninit_primary();
2177         hns3_warn(hw, "Close port %u finished", hw->data->port_id);
2178
2179         return ret;
2180 }
2181
2182 static int
2183 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
2184                       size_t fw_size)
2185 {
2186         struct hns3_adapter *hns = eth_dev->data->dev_private;
2187         struct hns3_hw *hw = &hns->hw;
2188         uint32_t version = hw->fw_version;
2189         int ret;
2190
2191         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
2192                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
2193                                       HNS3_FW_VERSION_BYTE3_S),
2194                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
2195                                       HNS3_FW_VERSION_BYTE2_S),
2196                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
2197                                       HNS3_FW_VERSION_BYTE1_S),
2198                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
2199                                       HNS3_FW_VERSION_BYTE0_S));
2200         if (ret < 0)
2201                 return -EINVAL;
2202
2203         ret += 1; /* add the size of '\0' */
2204         if (fw_size < (size_t)ret)
2205                 return ret;
2206         else
2207                 return 0;
2208 }
2209
2210 static int
2211 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
2212                        __rte_unused int wait_to_complete)
2213 {
2214         struct hns3_adapter *hns = eth_dev->data->dev_private;
2215         struct hns3_hw *hw = &hns->hw;
2216         struct hns3_mac *mac = &hw->mac;
2217         struct rte_eth_link new_link;
2218
2219         memset(&new_link, 0, sizeof(new_link));
2220         switch (mac->link_speed) {
2221         case RTE_ETH_SPEED_NUM_10M:
2222         case RTE_ETH_SPEED_NUM_100M:
2223         case RTE_ETH_SPEED_NUM_1G:
2224         case RTE_ETH_SPEED_NUM_10G:
2225         case RTE_ETH_SPEED_NUM_25G:
2226         case RTE_ETH_SPEED_NUM_40G:
2227         case RTE_ETH_SPEED_NUM_50G:
2228         case RTE_ETH_SPEED_NUM_100G:
2229         case RTE_ETH_SPEED_NUM_200G:
2230                 if (mac->link_status)
2231                         new_link.link_speed = mac->link_speed;
2232                 break;
2233         default:
2234                 if (mac->link_status)
2235                         new_link.link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2236                 break;
2237         }
2238
2239         if (!mac->link_status)
2240                 new_link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2241
2242         new_link.link_duplex = mac->link_duplex;
2243         new_link.link_status = mac->link_status ? RTE_ETH_LINK_UP : RTE_ETH_LINK_DOWN;
2244         new_link.link_autoneg =
2245             !(eth_dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_FIXED);
2246
2247         return rte_eth_linkstatus_set(eth_dev, &new_link);
2248 }
2249
2250 static int
2251 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
2252 {
2253         struct hns3_hw *hw = &hns->hw;
2254         uint16_t nb_rx_q = hw->data->nb_rx_queues;
2255         uint16_t nb_tx_q = hw->data->nb_tx_queues;
2256         int ret;
2257
2258         ret = hns3vf_set_tc_queue_mapping(hns, nb_rx_q, nb_tx_q);
2259         if (ret)
2260                 return ret;
2261
2262         hns3_enable_rxd_adv_layout(hw);
2263
2264         ret = hns3_init_queues(hns, reset_queue);
2265         if (ret)
2266                 hns3_err(hw, "failed to init queues, ret = %d.", ret);
2267
2268         return ret;
2269 }
2270
2271 static int
2272 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
2273 {
2274         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2275         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2276         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
2278         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
2279         uint32_t intr_vector;
2280         uint16_t q_id;
2281         int ret;
2282
2283         /*
2284          * hns3 needs a separate interrupt to be used as event interrupt which
2285          * could not be shared with task queue pair, so KERNEL drivers need
2286          * support multiple interrupt vectors.
2287          */
2288         if (dev->data->dev_conf.intr_conf.rxq == 0 ||
2289             !rte_intr_cap_multiple(intr_handle))
2290                 return 0;
2291
2292         rte_intr_disable(intr_handle);
2293         intr_vector = hw->used_rx_queues;
2294         /* It creates event fd for each intr vector when MSIX is used */
2295         if (rte_intr_efd_enable(intr_handle, intr_vector))
2296                 return -EINVAL;
2297
2298         if (intr_handle->intr_vec == NULL) {
2299                 intr_handle->intr_vec =
2300                         rte_zmalloc("intr_vec",
2301                                     hw->used_rx_queues * sizeof(int), 0);
2302                 if (intr_handle->intr_vec == NULL) {
2303                         hns3_err(hw, "Failed to allocate %u rx_queues"
2304                                      " intr_vec", hw->used_rx_queues);
2305                         ret = -ENOMEM;
2306                         goto vf_alloc_intr_vec_error;
2307                 }
2308         }
2309
2310         if (rte_intr_allow_others(intr_handle)) {
2311                 vec = RTE_INTR_VEC_RXTX_OFFSET;
2312                 base = RTE_INTR_VEC_RXTX_OFFSET;
2313         }
2314
2315         for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2316                 ret = hns3vf_bind_ring_with_vector(hw, vec, true,
2317                                                    HNS3_RING_TYPE_RX, q_id);
2318                 if (ret)
2319                         goto vf_bind_vector_error;
2320                 intr_handle->intr_vec[q_id] = vec;
2321                 /*
2322                  * If there are not enough efds (e.g. not enough interrupt),
2323                  * remaining queues will be bond to the last interrupt.
2324                  */
2325                 if (vec < base + intr_handle->nb_efd - 1)
2326                         vec++;
2327         }
2328         rte_intr_enable(intr_handle);
2329         return 0;
2330
2331 vf_bind_vector_error:
2332         rte_free(intr_handle->intr_vec);
2333         intr_handle->intr_vec = NULL;
2334 vf_alloc_intr_vec_error:
2335         rte_intr_efd_disable(intr_handle);
2336         return ret;
2337 }
2338
2339 static int
2340 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
2341 {
2342         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
2343         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2344         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2345         uint16_t q_id;
2346         int ret;
2347
2348         if (dev->data->dev_conf.intr_conf.rxq == 0)
2349                 return 0;
2350
2351         if (rte_intr_dp_is_en(intr_handle)) {
2352                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
2353                         ret = hns3vf_bind_ring_with_vector(hw,
2354                                         intr_handle->intr_vec[q_id], true,
2355                                         HNS3_RING_TYPE_RX, q_id);
2356                         if (ret)
2357                                 return ret;
2358                 }
2359         }
2360
2361         return 0;
2362 }
2363
2364 static void
2365 hns3vf_restore_filter(struct rte_eth_dev *dev)
2366 {
2367         hns3_restore_rss_filter(dev);
2368 }
2369
2370 static int
2371 hns3vf_dev_start(struct rte_eth_dev *dev)
2372 {
2373         struct hns3_adapter *hns = dev->data->dev_private;
2374         struct hns3_hw *hw = &hns->hw;
2375         int ret;
2376
2377         PMD_INIT_FUNC_TRACE();
2378         if (__atomic_load_n(&hw->reset.resetting, __ATOMIC_RELAXED))
2379                 return -EBUSY;
2380
2381         rte_spinlock_lock(&hw->lock);
2382         hw->adapter_state = HNS3_NIC_STARTING;
2383         ret = hns3vf_do_start(hns, true);
2384         if (ret) {
2385                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2386                 rte_spinlock_unlock(&hw->lock);
2387                 return ret;
2388         }
2389         ret = hns3vf_map_rx_interrupt(dev);
2390         if (ret)
2391                 goto map_rx_inter_err;
2392
2393         /*
2394          * There are three register used to control the status of a TQP
2395          * (contains a pair of Tx queue and Rx queue) in the new version network
2396          * engine. One is used to control the enabling of Tx queue, the other is
2397          * used to control the enabling of Rx queue, and the last is the master
2398          * switch used to control the enabling of the tqp. The Tx register and
2399          * TQP register must be enabled at the same time to enable a Tx queue.
2400          * The same applies to the Rx queue. For the older network enginem, this
2401          * function only refresh the enabled flag, and it is used to update the
2402          * status of queue in the dpdk framework.
2403          */
2404         ret = hns3_start_all_txqs(dev);
2405         if (ret)
2406                 goto map_rx_inter_err;
2407
2408         ret = hns3_start_all_rxqs(dev);
2409         if (ret)
2410                 goto start_all_rxqs_fail;
2411
2412         hw->adapter_state = HNS3_NIC_STARTED;
2413         rte_spinlock_unlock(&hw->lock);
2414
2415         hns3_rx_scattered_calc(dev);
2416         hns3_set_rxtx_function(dev);
2417         hns3_mp_req_start_rxtx(dev);
2418
2419         hns3vf_restore_filter(dev);
2420
2421         /* Enable interrupt of all rx queues before enabling queues */
2422         hns3_dev_all_rx_queue_intr_enable(hw, true);
2423         hns3_start_tqps(hw);
2424
2425         if (dev->data->dev_conf.intr_conf.lsc != 0)
2426                 hns3vf_dev_link_update(dev, 0);
2427         hns3vf_start_poll_job(dev);
2428
2429         return ret;
2430
2431 start_all_rxqs_fail:
2432         hns3_stop_all_txqs(dev);
2433 map_rx_inter_err:
2434         (void)hns3vf_do_stop(hns);
2435         hw->adapter_state = HNS3_NIC_CONFIGURED;
2436         rte_spinlock_unlock(&hw->lock);
2437
2438         return ret;
2439 }
2440
2441 static bool
2442 is_vf_reset_done(struct hns3_hw *hw)
2443 {
2444 #define HNS3_FUN_RST_ING_BITS \
2445         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2446          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2447          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2448          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2449
2450         uint32_t val;
2451
2452         if (hw->reset.level == HNS3_VF_RESET) {
2453                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2454                 if (val & HNS3_VF_RST_ING_BIT)
2455                         return false;
2456         } else {
2457                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2458                 if (val & HNS3_FUN_RST_ING_BITS)
2459                         return false;
2460         }
2461         return true;
2462 }
2463
2464 bool
2465 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2466 {
2467         struct hns3_hw *hw = &hns->hw;
2468         enum hns3_reset_level reset;
2469
2470         /*
2471          * According to the protocol of PCIe, FLR to a PF device resets the PF
2472          * state as well as the SR-IOV extended capability including VF Enable
2473          * which means that VFs no longer exist.
2474          *
2475          * HNS3_VF_FULL_RESET means PF device is in FLR reset. when PF device
2476          * is in FLR stage, the register state of VF device is not reliable,
2477          * so register states detection can not be carried out. In this case,
2478          * we just ignore the register states and return false to indicate that
2479          * there are no other reset states that need to be processed by driver.
2480          */
2481         if (hw->reset.level == HNS3_VF_FULL_RESET)
2482                 return false;
2483
2484         /* Check the registers to confirm whether there is reset pending */
2485         hns3vf_check_event_cause(hns, NULL);
2486         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2487         if (hw->reset.level != HNS3_NONE_RESET && reset != HNS3_NONE_RESET &&
2488             hw->reset.level < reset) {
2489                 hns3_warn(hw, "High level reset %d is pending", reset);
2490                 return true;
2491         }
2492         return false;
2493 }
2494
2495 static int
2496 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2497 {
2498         struct hns3_hw *hw = &hns->hw;
2499         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2500         struct timeval tv;
2501
2502         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2503                 /*
2504                  * After vf reset is ready, the PF may not have completed
2505                  * the reset processing. The vf sending mbox to PF may fail
2506                  * during the pf reset, so it is better to add extra delay.
2507                  */
2508                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2509                     hw->reset.level == HNS3_FLR_RESET)
2510                         return 0;
2511                 /* Reset retry process, no need to add extra delay. */
2512                 if (hw->reset.attempts)
2513                         return 0;
2514                 if (wait_data->check_completion == NULL)
2515                         return 0;
2516
2517                 wait_data->check_completion = NULL;
2518                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2519                 wait_data->count = 1;
2520                 wait_data->result = HNS3_WAIT_REQUEST;
2521                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2522                                   wait_data);
2523                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2524                 return -EAGAIN;
2525         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2526                 hns3_clock_gettime(&tv);
2527                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2528                           tv.tv_sec, tv.tv_usec);
2529                 return -ETIME;
2530         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2531                 return -EAGAIN;
2532
2533         wait_data->hns = hns;
2534         wait_data->check_completion = is_vf_reset_done;
2535         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2536                                 HNS3VF_RESET_WAIT_MS + hns3_clock_gettime_ms();
2537         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2538         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2539         wait_data->result = HNS3_WAIT_REQUEST;
2540         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2541         return -EAGAIN;
2542 }
2543
2544 static int
2545 hns3vf_prepare_reset(struct hns3_adapter *hns)
2546 {
2547         struct hns3_hw *hw = &hns->hw;
2548         int ret;
2549
2550         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2551                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2552                                         0, true, NULL, 0);
2553                 if (ret)
2554                         return ret;
2555         }
2556         __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED);
2557
2558         return 0;
2559 }
2560
2561 static int
2562 hns3vf_stop_service(struct hns3_adapter *hns)
2563 {
2564         struct hns3_hw *hw = &hns->hw;
2565         struct rte_eth_dev *eth_dev;
2566
2567         eth_dev = &rte_eth_devices[hw->data->port_id];
2568         if (hw->adapter_state == HNS3_NIC_STARTED) {
2569                 /*
2570                  * Make sure call update link status before hns3vf_stop_poll_job
2571                  * because update link status depend on polling job exist.
2572                  */
2573                 hns3vf_update_link_status(hw, RTE_ETH_LINK_DOWN, hw->mac.link_speed,
2574                                           hw->mac.link_duplex);
2575                 hns3vf_stop_poll_job(eth_dev);
2576         }
2577         hw->mac.link_status = RTE_ETH_LINK_DOWN;
2578
2579         hns3_set_rxtx_function(eth_dev);
2580         rte_wmb();
2581         /* Disable datapath on secondary process. */
2582         hns3_mp_req_stop_rxtx(eth_dev);
2583         rte_delay_ms(hw->cfg_max_queues);
2584
2585         rte_spinlock_lock(&hw->lock);
2586         if (hw->adapter_state == HNS3_NIC_STARTED ||
2587             hw->adapter_state == HNS3_NIC_STOPPING) {
2588                 hns3_enable_all_queues(hw, false);
2589                 hns3vf_do_stop(hns);
2590                 hw->reset.mbuf_deferred_free = true;
2591         } else
2592                 hw->reset.mbuf_deferred_free = false;
2593
2594         /*
2595          * It is cumbersome for hardware to pick-and-choose entries for deletion
2596          * from table space. Hence, for function reset software intervention is
2597          * required to delete the entries.
2598          */
2599         if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED) == 0)
2600                 hns3vf_configure_all_mc_mac_addr(hns, true);
2601         rte_spinlock_unlock(&hw->lock);
2602
2603         return 0;
2604 }
2605
2606 static int
2607 hns3vf_start_service(struct hns3_adapter *hns)
2608 {
2609         struct hns3_hw *hw = &hns->hw;
2610         struct rte_eth_dev *eth_dev;
2611
2612         eth_dev = &rte_eth_devices[hw->data->port_id];
2613         hns3_set_rxtx_function(eth_dev);
2614         hns3_mp_req_start_rxtx(eth_dev);
2615         if (hw->adapter_state == HNS3_NIC_STARTED) {
2616                 hns3vf_start_poll_job(eth_dev);
2617
2618                 /* Enable interrupt of all rx queues before enabling queues */
2619                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2620                 /*
2621                  * Enable state of each rxq and txq will be recovered after
2622                  * reset, so we need to restore them before enable all tqps;
2623                  */
2624                 hns3_restore_tqp_enable_state(hw);
2625                 /*
2626                  * When finished the initialization, enable queues to receive
2627                  * and transmit packets.
2628                  */
2629                 hns3_enable_all_queues(hw, true);
2630         }
2631
2632         return 0;
2633 }
2634
2635 static int
2636 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2637 {
2638         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2639         struct rte_ether_addr *hw_mac;
2640         int ret;
2641
2642         /*
2643          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2644          * on the host by "ip link set ..." command. If the hns3 PF kernel
2645          * ethdev driver sets the MAC address for VF device after the
2646          * initialization of the related VF device, the PF driver will notify
2647          * VF driver to reset VF device to make the new MAC address effective
2648          * immediately. The hns3 VF PMD driver should check whether the MAC
2649          * address has been changed by the PF kernel ethdev driver, if changed
2650          * VF driver should configure hardware using the new MAC address in the
2651          * recovering hardware configuration stage of the reset process.
2652          */
2653         ret = hns3vf_get_host_mac_addr(hw);
2654         if (ret)
2655                 return ret;
2656
2657         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2658         ret = rte_is_zero_ether_addr(hw_mac);
2659         if (ret) {
2660                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2661         } else {
2662                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2663                 if (!ret) {
2664                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2665                         hns3_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2666                                               &hw->data->mac_addrs[0]);
2667                         hns3_warn(hw, "Default MAC address has been changed to:"
2668                                   " %s by the host PF kernel ethdev driver",
2669                                   mac_str);
2670                 }
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int
2677 hns3vf_restore_conf(struct hns3_adapter *hns)
2678 {
2679         struct hns3_hw *hw = &hns->hw;
2680         int ret;
2681
2682         ret = hns3vf_check_default_mac_change(hw);
2683         if (ret)
2684                 return ret;
2685
2686         ret = hns3vf_configure_mac_addr(hns, false);
2687         if (ret)
2688                 return ret;
2689
2690         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2691         if (ret)
2692                 goto err_mc_mac;
2693
2694         ret = hns3vf_restore_promisc(hns);
2695         if (ret)
2696                 goto err_vlan_table;
2697
2698         ret = hns3vf_restore_vlan_conf(hns);
2699         if (ret)
2700                 goto err_vlan_table;
2701
2702         ret = hns3vf_get_port_base_vlan_filter_state(hw);
2703         if (ret)
2704                 goto err_vlan_table;
2705
2706         ret = hns3vf_restore_rx_interrupt(hw);
2707         if (ret)
2708                 goto err_vlan_table;
2709
2710         ret = hns3_restore_gro_conf(hw);
2711         if (ret)
2712                 goto err_vlan_table;
2713
2714         if (hw->adapter_state == HNS3_NIC_STARTED) {
2715                 ret = hns3vf_do_start(hns, false);
2716                 if (ret)
2717                         goto err_vlan_table;
2718                 hns3_info(hw, "hns3vf dev restart successful!");
2719         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2720                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2721
2722         ret = hns3vf_set_alive(hw, true);
2723         if (ret) {
2724                 hns3_err(hw, "failed to VF send alive to PF: %d", ret);
2725                 goto err_vlan_table;
2726         }
2727
2728         return 0;
2729
2730 err_vlan_table:
2731         hns3vf_configure_all_mc_mac_addr(hns, true);
2732 err_mc_mac:
2733         hns3vf_configure_mac_addr(hns, true);
2734         return ret;
2735 }
2736
2737 static enum hns3_reset_level
2738 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2739 {
2740         enum hns3_reset_level reset_level;
2741
2742         /* return the highest priority reset level amongst all */
2743         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2744                 reset_level = HNS3_VF_RESET;
2745         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2746                 reset_level = HNS3_VF_FULL_RESET;
2747         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2748                 reset_level = HNS3_VF_PF_FUNC_RESET;
2749         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2750                 reset_level = HNS3_VF_FUNC_RESET;
2751         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2752                 reset_level = HNS3_FLR_RESET;
2753         else
2754                 reset_level = HNS3_NONE_RESET;
2755
2756         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2757                 return HNS3_NONE_RESET;
2758
2759         return reset_level;
2760 }
2761
2762 static void
2763 hns3vf_reset_service(void *param)
2764 {
2765         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2766         struct hns3_hw *hw = &hns->hw;
2767         enum hns3_reset_level reset_level;
2768         struct timeval tv_delta;
2769         struct timeval tv_start;
2770         struct timeval tv;
2771         uint64_t msec;
2772
2773         /*
2774          * The interrupt is not triggered within the delay time.
2775          * The interrupt may have been lost. It is necessary to handle
2776          * the interrupt to recover from the error.
2777          */
2778         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
2779                             SCHEDULE_DEFERRED) {
2780                 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED,
2781                                  __ATOMIC_RELAXED);
2782                 hns3_err(hw, "Handling interrupts in delayed tasks");
2783                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2784                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2785                 if (reset_level == HNS3_NONE_RESET) {
2786                         hns3_err(hw, "No reset level is set, try global reset");
2787                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2788                 }
2789         }
2790         __atomic_store_n(&hw->reset.schedule, SCHEDULE_NONE, __ATOMIC_RELAXED);
2791
2792         /*
2793          * Hardware reset has been notified, we now have to poll & check if
2794          * hardware has actually completed the reset sequence.
2795          */
2796         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2797         if (reset_level != HNS3_NONE_RESET) {
2798                 hns3_clock_gettime(&tv_start);
2799                 hns3_reset_process(hns, reset_level);
2800                 hns3_clock_gettime(&tv);
2801                 timersub(&tv, &tv_start, &tv_delta);
2802                 msec = hns3_clock_calctime_ms(&tv_delta);
2803                 if (msec > HNS3_RESET_PROCESS_MS)
2804                         hns3_err(hw, "%d handle long time delta %" PRIu64
2805                                  " ms time=%ld.%.6ld",
2806                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2807         }
2808 }
2809
2810 static int
2811 hns3vf_reinit_dev(struct hns3_adapter *hns)
2812 {
2813         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2814         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2815         struct hns3_hw *hw = &hns->hw;
2816         int ret;
2817
2818         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2819                 rte_intr_disable(&pci_dev->intr_handle);
2820                 ret = hns3vf_set_bus_master(pci_dev, true);
2821                 if (ret < 0) {
2822                         hns3_err(hw, "failed to set pci bus, ret = %d", ret);
2823                         return ret;
2824                 }
2825         }
2826
2827         /* Firmware command initialize */
2828         ret = hns3_cmd_init(hw);
2829         if (ret) {
2830                 hns3_err(hw, "Failed to init cmd: %d", ret);
2831                 return ret;
2832         }
2833
2834         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2835                 /*
2836                  * UIO enables msix by writing the pcie configuration space
2837                  * vfio_pci enables msix in rte_intr_enable.
2838                  */
2839                 if (pci_dev->kdrv == RTE_PCI_KDRV_IGB_UIO ||
2840                     pci_dev->kdrv == RTE_PCI_KDRV_UIO_GENERIC) {
2841                         if (hns3vf_enable_msix(pci_dev, true))
2842                                 hns3_err(hw, "Failed to enable msix");
2843                 }
2844
2845                 rte_intr_enable(&pci_dev->intr_handle);
2846         }
2847
2848         ret = hns3_reset_all_tqps(hns);
2849         if (ret) {
2850                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2851                 return ret;
2852         }
2853
2854         ret = hns3vf_init_hardware(hns);
2855         if (ret) {
2856                 hns3_err(hw, "Failed to init hardware: %d", ret);
2857                 return ret;
2858         }
2859
2860         return 0;
2861 }
2862
2863 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2864         .dev_configure      = hns3vf_dev_configure,
2865         .dev_start          = hns3vf_dev_start,
2866         .dev_stop           = hns3vf_dev_stop,
2867         .dev_close          = hns3vf_dev_close,
2868         .mtu_set            = hns3vf_dev_mtu_set,
2869         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2870         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2871         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2872         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2873         .stats_get          = hns3_stats_get,
2874         .stats_reset        = hns3_stats_reset,
2875         .xstats_get         = hns3_dev_xstats_get,
2876         .xstats_get_names   = hns3_dev_xstats_get_names,
2877         .xstats_reset       = hns3_dev_xstats_reset,
2878         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2879         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2880         .dev_infos_get      = hns3vf_dev_infos_get,
2881         .fw_version_get     = hns3vf_fw_version_get,
2882         .rx_queue_setup     = hns3_rx_queue_setup,
2883         .tx_queue_setup     = hns3_tx_queue_setup,
2884         .rx_queue_release   = hns3_dev_rx_queue_release,
2885         .tx_queue_release   = hns3_dev_tx_queue_release,
2886         .rx_queue_start     = hns3_dev_rx_queue_start,
2887         .rx_queue_stop      = hns3_dev_rx_queue_stop,
2888         .tx_queue_start     = hns3_dev_tx_queue_start,
2889         .tx_queue_stop      = hns3_dev_tx_queue_stop,
2890         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2891         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2892         .rxq_info_get       = hns3_rxq_info_get,
2893         .txq_info_get       = hns3_txq_info_get,
2894         .rx_burst_mode_get  = hns3_rx_burst_mode_get,
2895         .tx_burst_mode_get  = hns3_tx_burst_mode_get,
2896         .mac_addr_add       = hns3vf_add_mac_addr,
2897         .mac_addr_remove    = hns3vf_remove_mac_addr,
2898         .mac_addr_set       = hns3vf_set_default_mac_addr,
2899         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2900         .link_update        = hns3vf_dev_link_update,
2901         .rss_hash_update    = hns3_dev_rss_hash_update,
2902         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2903         .reta_update        = hns3_dev_rss_reta_update,
2904         .reta_query         = hns3_dev_rss_reta_query,
2905         .flow_ops_get       = hns3_dev_flow_ops_get,
2906         .vlan_filter_set    = hns3vf_vlan_filter_set,
2907         .vlan_offload_set   = hns3vf_vlan_offload_set,
2908         .get_reg            = hns3_get_regs,
2909         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2910         .tx_done_cleanup    = hns3_tx_done_cleanup,
2911 };
2912
2913 static const struct hns3_reset_ops hns3vf_reset_ops = {
2914         .reset_service       = hns3vf_reset_service,
2915         .stop_service        = hns3vf_stop_service,
2916         .prepare_reset       = hns3vf_prepare_reset,
2917         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2918         .reinit_dev          = hns3vf_reinit_dev,
2919         .restore_conf        = hns3vf_restore_conf,
2920         .start_service       = hns3vf_start_service,
2921 };
2922
2923 static int
2924 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2925 {
2926         struct hns3_adapter *hns = eth_dev->data->dev_private;
2927         struct hns3_hw *hw = &hns->hw;
2928         int ret;
2929
2930         PMD_INIT_FUNC_TRACE();
2931
2932         hns3_flow_init(eth_dev);
2933
2934         hns3_set_rxtx_function(eth_dev);
2935         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2936         eth_dev->rx_queue_count = hns3_rx_queue_count;
2937         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2938                 ret = hns3_mp_init_secondary();
2939                 if (ret) {
2940                         PMD_INIT_LOG(ERR, "Failed to init for secondary "
2941                                           "process, ret = %d", ret);
2942                         goto err_mp_init_secondary;
2943                 }
2944                 hw->secondary_cnt++;
2945                 hns3_tx_push_init(eth_dev);
2946                 return 0;
2947         }
2948
2949         ret = hns3_mp_init_primary();
2950         if (ret) {
2951                 PMD_INIT_LOG(ERR,
2952                              "Failed to init for primary process, ret = %d",
2953                              ret);
2954                 goto err_mp_init_primary;
2955         }
2956
2957         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2958         hns->is_vf = true;
2959         hw->data = eth_dev->data;
2960         hns3_parse_devargs(eth_dev);
2961
2962         ret = hns3_reset_init(hw);
2963         if (ret)
2964                 goto err_init_reset;
2965         hw->reset.ops = &hns3vf_reset_ops;
2966
2967         ret = hns3vf_init_vf(eth_dev);
2968         if (ret) {
2969                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2970                 goto err_init_vf;
2971         }
2972
2973         /* Allocate memory for storing MAC addresses */
2974         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2975                                                sizeof(struct rte_ether_addr) *
2976                                                HNS3_VF_UC_MACADDR_NUM, 0);
2977         if (eth_dev->data->mac_addrs == NULL) {
2978                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2979                              "to store MAC addresses",
2980                              sizeof(struct rte_ether_addr) *
2981                              HNS3_VF_UC_MACADDR_NUM);
2982                 ret = -ENOMEM;
2983                 goto err_rte_zmalloc;
2984         }
2985
2986         /*
2987          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2988          * on the host by "ip link set ..." command. To avoid some incorrect
2989          * scenes, for example, hns3 VF PMD driver fails to receive and send
2990          * packets after user configure the MAC address by using the
2991          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
2992          * address strategy as the hns3 kernel ethdev driver in the
2993          * initialization. If user configure a MAC address by the ip command
2994          * for VF device, then hns3 VF PMD driver will start with it, otherwise
2995          * start with a random MAC address in the initialization.
2996          */
2997         if (rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr))
2998                 rte_eth_random_addr(hw->mac.mac_addr);
2999         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
3000                             &eth_dev->data->mac_addrs[0]);
3001
3002         hw->adapter_state = HNS3_NIC_INITIALIZED;
3003
3004         if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) ==
3005                             SCHEDULE_PENDING) {
3006                 hns3_err(hw, "Reschedule reset service after dev_init");
3007                 hns3_schedule_reset(hns);
3008         } else {
3009                 /* IMP will wait ready flag before reset */
3010                 hns3_notify_reset_ready(hw, false);
3011         }
3012         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
3013                           eth_dev);
3014         return 0;
3015
3016 err_rte_zmalloc:
3017         hns3vf_uninit_vf(eth_dev);
3018
3019 err_init_vf:
3020         rte_free(hw->reset.wait_data);
3021
3022 err_init_reset:
3023         hns3_mp_uninit_primary();
3024
3025 err_mp_init_primary:
3026 err_mp_init_secondary:
3027         eth_dev->dev_ops = NULL;
3028         eth_dev->rx_pkt_burst = NULL;
3029         eth_dev->rx_descriptor_status = NULL;
3030         eth_dev->tx_pkt_burst = NULL;
3031         eth_dev->tx_pkt_prepare = NULL;
3032         eth_dev->tx_descriptor_status = NULL;
3033
3034         return ret;
3035 }
3036
3037 static int
3038 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
3039 {
3040         struct hns3_adapter *hns = eth_dev->data->dev_private;
3041         struct hns3_hw *hw = &hns->hw;
3042
3043         PMD_INIT_FUNC_TRACE();
3044
3045         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3046                 return 0;
3047
3048         if (hw->adapter_state < HNS3_NIC_CLOSING)
3049                 hns3vf_dev_close(eth_dev);
3050
3051         hw->adapter_state = HNS3_NIC_REMOVED;
3052         return 0;
3053 }
3054
3055 static int
3056 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3057                      struct rte_pci_device *pci_dev)
3058 {
3059         return rte_eth_dev_pci_generic_probe(pci_dev,
3060                                              sizeof(struct hns3_adapter),
3061                                              hns3vf_dev_init);
3062 }
3063
3064 static int
3065 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
3066 {
3067         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
3068 }
3069
3070 static const struct rte_pci_id pci_id_hns3vf_map[] = {
3071         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
3072         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
3073         { .vendor_id = 0, }, /* sentinel */
3074 };
3075
3076 static struct rte_pci_driver rte_hns3vf_pmd = {
3077         .id_table = pci_id_hns3vf_map,
3078         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3079         .probe = eth_hns3vf_pci_probe,
3080         .remove = eth_hns3vf_pci_remove,
3081 };
3082
3083 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
3084 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
3085 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");
3086 RTE_PMD_REGISTER_PARAM_STRING(net_hns3_vf,
3087                 HNS3_DEVARG_RX_FUNC_HINT "=vec|sve|simple|common "
3088                 HNS3_DEVARG_TX_FUNC_HINT "=vec|sve|simple|common "
3089                 HNS3_DEVARG_DEV_CAPS_MASK "=<1-65535> "
3090                 HNS3_DEVARG_MBX_TIME_LIMIT_MS "=<uint16_t> ");