drivers/net/hns3/hns3_ethdev_vf.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <arpa/inet.h>
  12 #include <linux/pci_regs.h>
  13
  14 #include <rte_alarm.h>
  15 #include <rte_atomic.h>
  16 #include <rte_bus_pci.h>
  17 #include <rte_byteorder.h>
  18 #include <rte_common.h>
  19 #include <rte_cycles.h>
  20 #include <rte_dev.h>
  21 #include <rte_eal.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_ethdev_pci.h>
  25 #include <rte_interrupts.h>
  26 #include <rte_io.h>
  27 #include <rte_log.h>
  28 #include <rte_pci.h>
  29 #include <rte_vfio.h>
  30
  31 #include "hns3_ethdev.h"
  32 #include "hns3_logs.h"
  33 #include "hns3_rxtx.h"
  34 #include "hns3_regs.h"
  35 #include "hns3_intr.h"
  36 #include "hns3_dcb.h"
  37 #include "hns3_mp.h"
  38
  39 #define HNS3VF_KEEP_ALIVE_INTERVAL      2000000 /* us */
  40 #define HNS3VF_SERVICE_INTERVAL         1000000 /* us */
  41
  42 #define HNS3VF_RESET_WAIT_MS    20
  43 #define HNS3VF_RESET_WAIT_CNT   2000
  44
  45 /* Reset related Registers */
  46 #define HNS3_GLOBAL_RESET_BIT           0
  47 #define HNS3_CORE_RESET_BIT             1
  48 #define HNS3_IMP_RESET_BIT              2
  49 #define HNS3_FUN_RST_ING_B              0
  50
  51 enum hns3vf_evt_cause {
  52         HNS3VF_VECTOR0_EVENT_RST,
  53         HNS3VF_VECTOR0_EVENT_MBX,
  54         HNS3VF_VECTOR0_EVENT_OTHER,
  55 };
  56
  57 static enum hns3_reset_level hns3vf_get_reset_level(struct hns3_hw *hw,
  58                                                     uint64_t *levels);
  59 static int hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  60 static int hns3vf_dev_configure_vlan(struct rte_eth_dev *dev);
  61
  62 static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
  63                                   struct rte_ether_addr *mac_addr);
  64 static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
  65                                      struct rte_ether_addr *mac_addr);
  66 /* set PCI bus mastering */
  67 static void
  68 hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
  69 {
  70         uint16_t reg;
  71
  72         rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
  73
  74         if (op)
  75                 /* set the master bit */
  76                 reg |= PCI_COMMAND_MASTER;
  77         else
  78                 reg &= ~(PCI_COMMAND_MASTER);
  79
  80         rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
  81 }
  82
  83 /**
  84  * hns3vf_find_pci_capability - lookup a capability in the PCI capability list
  85  * @cap: the capability
  86  *
  87  * Return the address of the given capability within the PCI capability list.
  88  */
  89 static int
  90 hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
  91 {
  92 #define MAX_PCIE_CAPABILITY 48
  93         uint16_t status;
  94         uint8_t pos;
  95         uint8_t id;
  96         int ttl;
  97
  98         rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
  99         if (!(status & PCI_STATUS_CAP_LIST))
 100                 return 0;
 101
 102         ttl = MAX_PCIE_CAPABILITY;
 103         rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
 104         while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
 105                 rte_pci_read_config(device, &id, sizeof(id),
 106                                     (pos + PCI_CAP_LIST_ID));
 107
 108                 if (id == 0xFF)
 109                         break;
 110
 111                 if (id == cap)
 112                         return (int)pos;
 113
 114                 rte_pci_read_config(device, &pos, sizeof(pos),
 115                                     (pos + PCI_CAP_LIST_NEXT));
 116         }
 117         return 0;
 118 }
 119
 120 static int
 121 hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 122 {
 123         uint16_t control;
 124         int pos;
 125
 126         pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
 127         if (pos) {
 128                 rte_pci_read_config(device, &control, sizeof(control),
 129                                     (pos + PCI_MSIX_FLAGS));
 130                 if (op)
 131                         control |= PCI_MSIX_FLAGS_ENABLE;
 132                 else
 133                         control &= ~PCI_MSIX_FLAGS_ENABLE;
 134                 rte_pci_write_config(device, &control, sizeof(control),
 135                                      (pos + PCI_MSIX_FLAGS));
 136                 return 0;
 137         }
 138         return -ENXIO;
 139 }
 140
 141 static int
 142 hns3vf_add_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 143 {
 144         /* mac address was checked by upper level interface */
 145         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 146         int ret;
 147
 148         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 149                                 HNS3_MBX_MAC_VLAN_UC_ADD, mac_addr->addr_bytes,
 150                                 RTE_ETHER_ADDR_LEN, false, NULL, 0);
 151         if (ret) {
 152                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 153                                       mac_addr);
 154                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 155                          mac_str, ret);
 156         }
 157         return ret;
 158 }
 159
 160 static int
 161 hns3vf_remove_uc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 162 {
 163         /* mac address was checked by upper level interface */
 164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 165         int ret;
 166
 167         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 168                                 HNS3_MBX_MAC_VLAN_UC_REMOVE,
 169                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN,
 170                                 false, NULL, 0);
 171         if (ret) {
 172                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 173                                       mac_addr);
 174                 hns3_err(hw, "failed to add uc mac addr(%s), ret = %d",
 175                          mac_str, ret);
 176         }
 177         return ret;
 178 }
 179
 180 static int
 181 hns3vf_add_mc_addr_common(struct hns3_hw *hw, struct rte_ether_addr *mac_addr)
 182 {
 183         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 184         struct rte_ether_addr *addr;
 185         int ret;
 186         int i;
 187
 188         for (i = 0; i < hw->mc_addrs_num; i++) {
 189                 addr = &hw->mc_addrs[i];
 190                 /* Check if there are duplicate addresses */
 191                 if (rte_is_same_ether_addr(addr, mac_addr)) {
 192                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 193                                               addr);
 194                         hns3_err(hw, "failed to add mc mac addr, same addrs"
 195                                  "(%s) is added by the set_mc_mac_addr_list "
 196                                  "API", mac_str);
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         ret = hns3vf_add_mc_mac_addr(hw, mac_addr);
 202         if (ret) {
 203                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 204                                       mac_addr);
 205                 hns3_err(hw, "failed to add mc mac addr(%s), ret = %d",
 206                          mac_str, ret);
 207         }
 208         return ret;
 209 }
 210
 211 static int
 212 hns3vf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
 213                     __rte_unused uint32_t idx,
 214                     __rte_unused uint32_t pool)
 215 {
 216         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 217         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 218         int ret;
 219
 220         rte_spinlock_lock(&hw->lock);
 221
 222         /*
 223          * In hns3 network engine adding UC and MC mac address with different
 224          * commands with firmware. We need to determine whether the input
 225          * address is a UC or a MC address to call different commands.
 226          * By the way, it is recommended calling the API function named
 227          * rte_eth_dev_set_mc_addr_list to set the MC mac address, because
 228          * using the rte_eth_dev_mac_addr_add API function to set MC mac address
 229          * may affect the specifications of UC mac addresses.
 230          */
 231         if (rte_is_multicast_ether_addr(mac_addr))
 232                 ret = hns3vf_add_mc_addr_common(hw, mac_addr);
 233         else
 234                 ret = hns3vf_add_uc_mac_addr(hw, mac_addr);
 235
 236         rte_spinlock_unlock(&hw->lock);
 237         if (ret) {
 238                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 239                                       mac_addr);
 240                 hns3_err(hw, "failed to add mac addr(%s), ret = %d", mac_str,
 241                          ret);
 242         }
 243
 244         return ret;
 245 }
 246
 247 static void
 248 hns3vf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t idx)
 249 {
 250         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 251         /* index will be checked by upper level rte interface */
 252         struct rte_ether_addr *mac_addr = &dev->data->mac_addrs[idx];
 253         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 254         int ret;
 255
 256         rte_spinlock_lock(&hw->lock);
 257
 258         if (rte_is_multicast_ether_addr(mac_addr))
 259                 ret = hns3vf_remove_mc_mac_addr(hw, mac_addr);
 260         else
 261                 ret = hns3vf_remove_uc_mac_addr(hw, mac_addr);
 262
 263         rte_spinlock_unlock(&hw->lock);
 264         if (ret) {
 265                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 266                                       mac_addr);
 267                 hns3_err(hw, "failed to remove mac addr(%s), ret = %d",
 268                          mac_str, ret);
 269         }
 270 }
 271
 272 static int
 273 hns3vf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                             struct rte_ether_addr *mac_addr)
 275 {
 276 #define HNS3_TWO_ETHER_ADDR_LEN (RTE_ETHER_ADDR_LEN * 2)
 277         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 278         struct rte_ether_addr *old_addr;
 279         uint8_t addr_bytes[HNS3_TWO_ETHER_ADDR_LEN]; /* for 2 MAC addresses */
 280         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 281         int ret;
 282
 283         /*
 284          * It has been guaranteed that input parameter named mac_addr is valid
 285          * address in the rte layer of DPDK framework.
 286          */
 287         old_addr = (struct rte_ether_addr *)hw->mac.mac_addr;
 288         rte_spinlock_lock(&hw->lock);
 289         memcpy(addr_bytes, mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN);
 290         memcpy(&addr_bytes[RTE_ETHER_ADDR_LEN], old_addr->addr_bytes,
 291                RTE_ETHER_ADDR_LEN);
 292
 293         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_UNICAST,
 294                                 HNS3_MBX_MAC_VLAN_UC_MODIFY, addr_bytes,
 295                                 HNS3_TWO_ETHER_ADDR_LEN, true, NULL, 0);
 296         if (ret) {
 297                 /*
 298                  * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev
 299                  * driver. When user has configured a MAC address for VF device
 300                  * by "ip link set ..." command based on the PF device, the hns3
 301                  * PF kernel ethdev driver does not allow VF driver to request
 302                  * reconfiguring a different default MAC address, and return
 303                  * -EPREM to VF driver through mailbox.
 304                  */
 305                 if (ret == -EPERM) {
 306                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 307                                               old_addr);
 308                         hns3_warn(hw, "Has permanet mac addr(%s) for vf",
 309                                   mac_str);
 310                 } else {
 311                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 312                                               mac_addr);
 313                         hns3_err(hw, "Failed to set mac addr(%s) for vf: %d",
 314                                  mac_str, ret);
 315                 }
 316         }
 317
 318         rte_ether_addr_copy(mac_addr,
 319                             (struct rte_ether_addr *)hw->mac.mac_addr);
 320         rte_spinlock_unlock(&hw->lock);
 321
 322         return ret;
 323 }
 324
 325 static int
 326 hns3vf_configure_mac_addr(struct hns3_adapter *hns, bool del)
 327 {
 328         struct hns3_hw *hw = &hns->hw;
 329         struct rte_ether_addr *addr;
 330         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 331         int err = 0;
 332         int ret;
 333         int i;
 334
 335         for (i = 0; i < HNS3_VF_UC_MACADDR_NUM; i++) {
 336                 addr = &hw->data->mac_addrs[i];
 337                 if (rte_is_zero_ether_addr(addr))
 338                         continue;
 339                 if (rte_is_multicast_ether_addr(addr))
 340                         ret = del ? hns3vf_remove_mc_mac_addr(hw, addr) :
 341                               hns3vf_add_mc_mac_addr(hw, addr);
 342                 else
 343                         ret = del ? hns3vf_remove_uc_mac_addr(hw, addr) :
 344                               hns3vf_add_uc_mac_addr(hw, addr);
 345
 346                 if (ret) {
 347                         err = ret;
 348                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 349                                               addr);
 350                         hns3_err(hw, "failed to %s mac addr(%s) index:%d "
 351                                  "ret = %d.", del ? "remove" : "restore",
 352                                  mac_str, i, ret);
 353                 }
 354         }
 355         return err;
 356 }
 357
 358 static int
 359 hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
 360                        struct rte_ether_addr *mac_addr)
 361 {
 362         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 363         int ret;
 364
 365         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 366                                 HNS3_MBX_MAC_VLAN_MC_ADD,
 367                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 368                                 NULL, 0);
 369         if (ret) {
 370                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 371                                       mac_addr);
 372                 hns3_err(hw, "Failed to add mc mac addr(%s) for vf: %d",
 373                          mac_str, ret);
 374         }
 375
 376         return ret;
 377 }
 378
 379 static int
 380 hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
 381                           struct rte_ether_addr *mac_addr)
 382 {
 383         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 384         int ret;
 385
 386         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MULTICAST,
 387                                 HNS3_MBX_MAC_VLAN_MC_REMOVE,
 388                                 mac_addr->addr_bytes, RTE_ETHER_ADDR_LEN, false,
 389                                 NULL, 0);
 390         if (ret) {
 391                 rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 392                                       mac_addr);
 393                 hns3_err(hw, "Failed to remove mc mac addr(%s) for vf: %d",
 394                          mac_str, ret);
 395         }
 396
 397         return ret;
 398 }
 399
 400 static int
 401 hns3vf_set_mc_addr_chk_param(struct hns3_hw *hw,
 402                              struct rte_ether_addr *mc_addr_set,
 403                              uint32_t nb_mc_addr)
 404 {
 405         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 406         struct rte_ether_addr *addr;
 407         uint32_t i;
 408         uint32_t j;
 409
 410         if (nb_mc_addr > HNS3_MC_MACADDR_NUM) {
 411                 hns3_err(hw, "failed to set mc mac addr, nb_mc_addr(%d) "
 412                          "invalid. valid range: 0~%d",
 413                          nb_mc_addr, HNS3_MC_MACADDR_NUM);
 414                 return -EINVAL;
 415         }
 416
 417         /* Check if input mac addresses are valid */
 418         for (i = 0; i < nb_mc_addr; i++) {
 419                 addr = &mc_addr_set[i];
 420                 if (!rte_is_multicast_ether_addr(addr)) {
 421                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 422                                               addr);
 423                         hns3_err(hw,
 424                                  "failed to set mc mac addr, addr(%s) invalid.",
 425                                  mac_str);
 426                         return -EINVAL;
 427                 }
 428
 429                 /* Check if there are duplicate addresses */
 430                 for (j = i + 1; j < nb_mc_addr; j++) {
 431                         if (rte_is_same_ether_addr(addr, &mc_addr_set[j])) {
 432                                 rte_ether_format_addr(mac_str,
 433                                                       RTE_ETHER_ADDR_FMT_SIZE,
 434                                                       addr);
 435                                 hns3_err(hw, "failed to set mc mac addr, "
 436                                          "addrs invalid. two same addrs(%s).",
 437                                          mac_str);
 438                                 return -EINVAL;
 439                         }
 440                 }
 441
 442                 /*
 443                  * Check if there are duplicate addresses between mac_addrs
 444                  * and mc_addr_set
 445                  */
 446                 for (j = 0; j < HNS3_VF_UC_MACADDR_NUM; j++) {
 447                         if (rte_is_same_ether_addr(addr,
 448                                                    &hw->data->mac_addrs[j])) {
 449                                 rte_ether_format_addr(mac_str,
 450                                                       RTE_ETHER_ADDR_FMT_SIZE,
 451                                                       addr);
 452                                 hns3_err(hw, "failed to set mc mac addr, "
 453                                          "addrs invalid. addrs(%s) has already "
 454                                          "configured in mac_addr add API",
 455                                          mac_str);
 456                                 return -EINVAL;
 457                         }
 458                 }
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int
 465 hns3vf_set_mc_mac_addr_list(struct rte_eth_dev *dev,
 466                             struct rte_ether_addr *mc_addr_set,
 467                             uint32_t nb_mc_addr)
 468 {
 469         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 470         struct rte_ether_addr *addr;
 471         int cur_addr_num;
 472         int set_addr_num;
 473         int num;
 474         int ret;
 475         int i;
 476
 477         ret = hns3vf_set_mc_addr_chk_param(hw, mc_addr_set, nb_mc_addr);
 478         if (ret)
 479                 return ret;
 480
 481         rte_spinlock_lock(&hw->lock);
 482         cur_addr_num = hw->mc_addrs_num;
 483         for (i = 0; i < cur_addr_num; i++) {
 484                 num = cur_addr_num - i - 1;
 485                 addr = &hw->mc_addrs[num];
 486                 ret = hns3vf_remove_mc_mac_addr(hw, addr);
 487                 if (ret) {
 488                         rte_spinlock_unlock(&hw->lock);
 489                         return ret;
 490                 }
 491
 492                 hw->mc_addrs_num--;
 493         }
 494
 495         set_addr_num = (int)nb_mc_addr;
 496         for (i = 0; i < set_addr_num; i++) {
 497                 addr = &mc_addr_set[i];
 498                 ret = hns3vf_add_mc_mac_addr(hw, addr);
 499                 if (ret) {
 500                         rte_spinlock_unlock(&hw->lock);
 501                         return ret;
 502                 }
 503
 504                 rte_ether_addr_copy(addr, &hw->mc_addrs[hw->mc_addrs_num]);
 505                 hw->mc_addrs_num++;
 506         }
 507         rte_spinlock_unlock(&hw->lock);
 508
 509         return 0;
 510 }
 511
 512 static int
 513 hns3vf_configure_all_mc_mac_addr(struct hns3_adapter *hns, bool del)
 514 {
 515         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
 516         struct hns3_hw *hw = &hns->hw;
 517         struct rte_ether_addr *addr;
 518         int err = 0;
 519         int ret;
 520         int i;
 521
 522         for (i = 0; i < hw->mc_addrs_num; i++) {
 523                 addr = &hw->mc_addrs[i];
 524                 if (!rte_is_multicast_ether_addr(addr))
 525                         continue;
 526                 if (del)
 527                         ret = hns3vf_remove_mc_mac_addr(hw, addr);
 528                 else
 529                         ret = hns3vf_add_mc_mac_addr(hw, addr);
 530                 if (ret) {
 531                         err = ret;
 532                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
 533                                               addr);
 534                         hns3_err(hw, "Failed to %s mc mac addr: %s for vf: %d",
 535                                  del ? "Remove" : "Restore", mac_str, ret);
 536                 }
 537         }
 538         return err;
 539 }
 540
 541 static int
 542 hns3vf_set_promisc_mode(struct hns3_hw *hw, bool en_bc_pmc,
 543                         bool en_uc_pmc, bool en_mc_pmc)
 544 {
 545         struct hns3_mbx_vf_to_pf_cmd *req;
 546         struct hns3_cmd_desc desc;
 547         int ret;
 548
 549         req = (struct hns3_mbx_vf_to_pf_cmd *)desc.data;
 550
 551         /*
 552          * The hns3 VF PMD driver depends on the hns3 PF kernel ethdev driver,
 553          * so there are some features for promiscuous/allmulticast mode in hns3
 554          * VF PMD driver as below:
 555          * 1. The promiscuous/allmulticast mode can be configured successfully
 556          *    only based on the trusted VF device. If based on the non trusted
 557          *    VF device, configuring promiscuous/allmulticast mode will fail.
 558          *    The hns3 VF device can be confiruged as trusted device by hns3 PF
 559          *    kernel ethdev driver on the host by the following command:
 560          *      "ip link set <eth num> vf <vf id> turst on"
 561          * 2. After the promiscuous mode is configured successfully, hns3 VF PMD
 562          *    driver can receive the ingress and outgoing traffic. In the words,
 563          *    all the ingress packets, all the packets sent from the PF and
 564          *    other VFs on the same physical port.
 565          * 3. Note: Because of the hardware constraints, By default vlan filter
 566          *    is enabled and couldn't be turned off based on VF device, so vlan
 567          *    filter is still effective even in promiscuous mode. If upper
 568          *    applications don't call rte_eth_dev_vlan_filter API function to
 569          *    set vlan based on VF device, hns3 VF PMD driver will can't receive
 570          *    the packets with vlan tag in promiscuoue mode.
 571          */
 572         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MBX_VF_TO_PF, false);
 573         req->msg[0] = HNS3_MBX_SET_PROMISC_MODE;
 574         req->msg[1] = en_bc_pmc ? 1 : 0;
 575         req->msg[2] = en_uc_pmc ? 1 : 0;
 576         req->msg[3] = en_mc_pmc ? 1 : 0;
 577
 578         ret = hns3_cmd_send(hw, &desc, 1);
 579         if (ret)
 580                 hns3_err(hw, "Set promisc mode fail, ret = %d", ret);
 581
 582         return ret;
 583 }
 584
 585 static int
 586 hns3vf_dev_promiscuous_enable(struct rte_eth_dev *dev)
 587 {
 588         struct hns3_adapter *hns = dev->data->dev_private;
 589         struct hns3_hw *hw = &hns->hw;
 590         int ret;
 591
 592         ret = hns3vf_set_promisc_mode(hw, true, true, true);
 593         if (ret)
 594                 hns3_err(hw, "Failed to enable promiscuous mode, ret = %d",
 595                         ret);
 596         return ret;
 597 }
 598
 599 static int
 600 hns3vf_dev_promiscuous_disable(struct rte_eth_dev *dev)
 601 {
 602         bool allmulti = dev->data->all_multicast ? true : false;
 603         struct hns3_adapter *hns = dev->data->dev_private;
 604         struct hns3_hw *hw = &hns->hw;
 605         int ret;
 606
 607         ret = hns3vf_set_promisc_mode(hw, true, false, allmulti);
 608         if (ret)
 609                 hns3_err(hw, "Failed to disable promiscuous mode, ret = %d",
 610                         ret);
 611         return ret;
 612 }
 613
 614 static int
 615 hns3vf_dev_allmulticast_enable(struct rte_eth_dev *dev)
 616 {
 617         struct hns3_adapter *hns = dev->data->dev_private;
 618         struct hns3_hw *hw = &hns->hw;
 619         int ret;
 620
 621         if (dev->data->promiscuous)
 622                 return 0;
 623
 624         ret = hns3vf_set_promisc_mode(hw, true, false, true);
 625         if (ret)
 626                 hns3_err(hw, "Failed to enable allmulticast mode, ret = %d",
 627                         ret);
 628         return ret;
 629 }
 630
 631 static int
 632 hns3vf_dev_allmulticast_disable(struct rte_eth_dev *dev)
 633 {
 634         struct hns3_adapter *hns = dev->data->dev_private;
 635         struct hns3_hw *hw = &hns->hw;
 636         int ret;
 637
 638         if (dev->data->promiscuous)
 639                 return 0;
 640
 641         ret = hns3vf_set_promisc_mode(hw, true, false, false);
 642         if (ret)
 643                 hns3_err(hw, "Failed to disable allmulticast mode, ret = %d",
 644                         ret);
 645         return ret;
 646 }
 647
 648 static int
 649 hns3vf_restore_promisc(struct hns3_adapter *hns)
 650 {
 651         struct hns3_hw *hw = &hns->hw;
 652         bool allmulti = hw->data->all_multicast ? true : false;
 653
 654         if (hw->data->promiscuous)
 655                 return hns3vf_set_promisc_mode(hw, true, true, true);
 656
 657         return hns3vf_set_promisc_mode(hw, true, false, allmulti);
 658 }
 659
 660 static int
 661 hns3vf_bind_ring_with_vector(struct hns3_hw *hw, uint8_t vector_id,
 662                              bool mmap, enum hns3_ring_type queue_type,
 663                              uint16_t queue_id)
 664 {
 665         struct hns3_vf_bind_vector_msg bind_msg;
 666         const char *op_str;
 667         uint16_t code;
 668         int ret;
 669
 670         memset(&bind_msg, 0, sizeof(bind_msg));
 671         code = mmap ? HNS3_MBX_MAP_RING_TO_VECTOR :
 672                 HNS3_MBX_UNMAP_RING_TO_VECTOR;
 673         bind_msg.vector_id = vector_id;
 674
 675         if (queue_type == HNS3_RING_TYPE_RX)
 676                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_RX;
 677         else
 678                 bind_msg.param[0].int_gl_index = HNS3_RING_GL_TX;
 679
 680         bind_msg.param[0].ring_type = queue_type;
 681         bind_msg.ring_num = 1;
 682         bind_msg.param[0].tqp_index = queue_id;
 683         op_str = mmap ? "Map" : "Unmap";
 684         ret = hns3_send_mbx_msg(hw, code, 0, (uint8_t *)&bind_msg,
 685                                 sizeof(bind_msg), false, NULL, 0);
 686         if (ret)
 687                 hns3_err(hw, "%s TQP %d fail, vector_id is %d, ret is %d.",
 688                          op_str, queue_id, bind_msg.vector_id, ret);
 689
 690         return ret;
 691 }
 692
 693 static int
 694 hns3vf_init_ring_with_vector(struct hns3_hw *hw)
 695 {
 696         uint8_t vec;
 697         int ret;
 698         int i;
 699
 700         /*
 701          * In hns3 network engine, vector 0 is always the misc interrupt of this
 702          * function, vector 1~N can be used respectively for the queues of the
 703          * function. Tx and Rx queues with the same number share the interrupt
 704          * vector. In the initialization clearing the all hardware mapping
 705          * relationship configurations between queues and interrupt vectors is
 706          * needed, so some error caused by the residual configurations, such as
 707          * the unexpected Tx interrupt, can be avoid. Because of the hardware
 708          * constraints in hns3 hardware engine, we have to implement clearing
 709          * the mapping relationship configurations by binding all queues to the
 710          * last interrupt vector and reserving the last interrupt vector. This
 711          * method results in a decrease of the maximum queues when upper
 712          * applications call the rte_eth_dev_configure API function to enable
 713          * Rx interrupt.
 714          */
 715         vec = hw->num_msi - 1; /* vector 0 for misc interrupt, not for queue */
 716         /* vec - 1: the last interrupt is reserved */
 717         hw->intr_tqps_num = vec > hw->tqps_num ? hw->tqps_num : vec - 1;
 718         for (i = 0; i < hw->intr_tqps_num; i++) {
 719                 /*
 720                  * Set gap limiter and rate limiter configuration of queue's
 721                  * interrupt.
 722                  */
 723                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_RX,
 724                                        HNS3_TQP_INTR_GL_DEFAULT);
 725                 hns3_set_queue_intr_gl(hw, i, HNS3_RING_GL_TX,
 726                                        HNS3_TQP_INTR_GL_DEFAULT);
 727                 hns3_set_queue_intr_rl(hw, i, HNS3_TQP_INTR_RL_DEFAULT);
 728
 729                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 730                                                    HNS3_RING_TYPE_TX, i);
 731                 if (ret) {
 732                         PMD_INIT_LOG(ERR, "VF fail to unbind TX ring(%d) with "
 733                                           "vector: %d, ret=%d", i, vec, ret);
 734                         return ret;
 735                 }
 736
 737                 ret = hns3vf_bind_ring_with_vector(hw, vec, false,
 738                                                    HNS3_RING_TYPE_RX, i);
 739                 if (ret) {
 740                         PMD_INIT_LOG(ERR, "VF fail to unbind RX ring(%d) with "
 741                                           "vector: %d, ret=%d", i, vec, ret);
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 hns3vf_dev_configure(struct rte_eth_dev *dev)
 751 {
 752         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         struct hns3_rss_conf *rss_cfg = &hw->rss_info;
 754         struct rte_eth_conf *conf = &dev->data->dev_conf;
 755         enum rte_eth_rx_mq_mode mq_mode = conf->rxmode.mq_mode;
 756         uint16_t nb_rx_q = dev->data->nb_rx_queues;
 757         uint16_t nb_tx_q = dev->data->nb_tx_queues;
 758         struct rte_eth_rss_conf rss_conf;
 759         uint16_t mtu;
 760         bool gro_en;
 761         int ret;
 762
 763         /*
 764          * Hardware does not support individually enable/disable/reset the Tx or
 765          * Rx queue in hns3 network engine. Driver must enable/disable/reset Tx
 766          * and Rx queues at the same time. When the numbers of Tx queues
 767          * allocated by upper applications are not equal to the numbers of Rx
 768          * queues, driver needs to setup fake Tx or Rx queues to adjust numbers
 769          * of Tx/Rx queues. otherwise, network engine can not work as usual. But
 770          * these fake queues are imperceptible, and can not be used by upper
 771          * applications.
 772          */
 773         ret = hns3_set_fake_rx_or_tx_queues(dev, nb_rx_q, nb_tx_q);
 774         if (ret) {
 775                 hns3_err(hw, "Failed to set rx/tx fake queues: %d", ret);
 776                 return ret;
 777         }
 778
 779         hw->adapter_state = HNS3_NIC_CONFIGURING;
 780         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 781                 hns3_err(hw, "setting link speed/duplex not supported");
 782                 ret = -EINVAL;
 783                 goto cfg_err;
 784         }
 785
 786         /* When RSS is not configured, redirect the packet queue 0 */
 787         if ((uint32_t)mq_mode & ETH_MQ_RX_RSS_FLAG) {
 788                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 789                 rss_conf = conf->rx_adv_conf.rss_conf;
 790                 if (rss_conf.rss_key == NULL) {
 791                         rss_conf.rss_key = rss_cfg->key;
 792                         rss_conf.rss_key_len = HNS3_RSS_KEY_SIZE;
 793                 }
 794
 795                 ret = hns3_dev_rss_hash_update(dev, &rss_conf);
 796                 if (ret)
 797                         goto cfg_err;
 798         }
 799
 800         /*
 801          * If jumbo frames are enabled, MTU needs to be refreshed
 802          * according to the maximum RX packet length.
 803          */
 804         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 805                 /*
 806                  * Security of max_rx_pkt_len is guaranteed in dpdk frame.
 807                  * Maximum value of max_rx_pkt_len is HNS3_MAX_FRAME_LEN, so it
 808                  * can safely assign to "uint16_t" type variable.
 809                  */
 810                 mtu = (uint16_t)HNS3_PKTLEN_TO_MTU(conf->rxmode.max_rx_pkt_len);
 811                 ret = hns3vf_dev_mtu_set(dev, mtu);
 812                 if (ret)
 813                         goto cfg_err;
 814                 dev->data->mtu = mtu;
 815         }
 816
 817         ret = hns3vf_dev_configure_vlan(dev);
 818         if (ret)
 819                 goto cfg_err;
 820
 821         /* config hardware GRO */
 822         gro_en = conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO ? true : false;
 823         ret = hns3_config_gro(hw, gro_en);
 824         if (ret)
 825                 goto cfg_err;
 826
 827         hw->adapter_state = HNS3_NIC_CONFIGURED;
 828         return 0;
 829
 830 cfg_err:
 831         (void)hns3_set_fake_rx_or_tx_queues(dev, 0, 0);
 832         hw->adapter_state = HNS3_NIC_INITIALIZED;
 833
 834         return ret;
 835 }
 836
 837 static int
 838 hns3vf_config_mtu(struct hns3_hw *hw, uint16_t mtu)
 839 {
 840         int ret;
 841
 842         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_MTU, 0, (const uint8_t *)&mtu,
 843                                 sizeof(mtu), true, NULL, 0);
 844         if (ret)
 845                 hns3_err(hw, "Failed to set mtu (%u) for vf: %d", mtu, ret);
 846
 847         return ret;
 848 }
 849
 850 static int
 851 hns3vf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 852 {
 853         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 854         uint32_t frame_size = mtu + HNS3_ETH_OVERHEAD;
 855         int ret;
 856
 857         /*
 858          * The hns3 PF/VF devices on the same port share the hardware MTU
 859          * configuration. Currently, we send mailbox to inform hns3 PF kernel
 860          * ethdev driver to finish hardware MTU configuration in hns3 VF PMD
 861          * driver, there is no need to stop the port for hns3 VF device, and the
 862          * MTU value issued by hns3 VF PMD driver must be less than or equal to
 863          * PF's MTU.
 864          */
 865         if (rte_atomic16_read(&hw->reset.resetting)) {
 866                 hns3_err(hw, "Failed to set mtu during resetting");
 867                 return -EIO;
 868         }
 869
 870         rte_spinlock_lock(&hw->lock);
 871         ret = hns3vf_config_mtu(hw, mtu);
 872         if (ret) {
 873                 rte_spinlock_unlock(&hw->lock);
 874                 return ret;
 875         }
 876         if (frame_size > RTE_ETHER_MAX_LEN)
 877                 dev->data->dev_conf.rxmode.offloads |=
 878                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 879         else
 880                 dev->data->dev_conf.rxmode.offloads &=
 881                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 882         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 883         rte_spinlock_unlock(&hw->lock);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 hns3vf_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)
 890 {
 891         struct hns3_adapter *hns = eth_dev->data->dev_private;
 892         struct hns3_hw *hw = &hns->hw;
 893         uint16_t q_num = hw->tqps_num;
 894
 895         /*
 896          * In interrupt mode, 'max_rx_queues' is set based on the number of
 897          * MSI-X interrupt resources of the hardware.
 898          */
 899         if (hw->data->dev_conf.intr_conf.rxq == 1)
 900                 q_num = hw->intr_tqps_num;
 901
 902         info->max_rx_queues = q_num;
 903         info->max_tx_queues = hw->tqps_num;
 904         info->max_rx_pktlen = HNS3_MAX_FRAME_LEN; /* CRC included */
 905         info->min_rx_bufsize = hw->rx_buf_len;
 906         info->max_mac_addrs = HNS3_VF_UC_MACADDR_NUM;
 907         info->max_mtu = info->max_rx_pktlen - HNS3_ETH_OVERHEAD;
 908         info->max_lro_pkt_size = HNS3_MAX_LRO_SIZE;
 909
 910         info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM |
 911                                  DEV_RX_OFFLOAD_UDP_CKSUM |
 912                                  DEV_RX_OFFLOAD_TCP_CKSUM |
 913                                  DEV_RX_OFFLOAD_SCTP_CKSUM |
 914                                  DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 915                                  DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
 916                                  DEV_RX_OFFLOAD_KEEP_CRC |
 917                                  DEV_RX_OFFLOAD_SCATTER |
 918                                  DEV_RX_OFFLOAD_VLAN_STRIP |
 919                                  DEV_RX_OFFLOAD_VLAN_FILTER |
 920                                  DEV_RX_OFFLOAD_JUMBO_FRAME |
 921                                  DEV_RX_OFFLOAD_RSS_HASH |
 922                                  DEV_RX_OFFLOAD_TCP_LRO);
 923         info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
 924         info->tx_offload_capa = (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 925                                  DEV_TX_OFFLOAD_IPV4_CKSUM |
 926                                  DEV_TX_OFFLOAD_TCP_CKSUM |
 927                                  DEV_TX_OFFLOAD_UDP_CKSUM |
 928                                  DEV_TX_OFFLOAD_SCTP_CKSUM |
 929                                  DEV_TX_OFFLOAD_VLAN_INSERT |
 930                                  DEV_TX_OFFLOAD_QINQ_INSERT |
 931                                  DEV_TX_OFFLOAD_MULTI_SEGS |
 932                                  DEV_TX_OFFLOAD_TCP_TSO |
 933                                  DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 934                                  DEV_TX_OFFLOAD_GRE_TNL_TSO |
 935                                  DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
 936                                  info->tx_queue_offload_capa);
 937
 938         info->rx_desc_lim = (struct rte_eth_desc_lim) {
 939                 .nb_max = HNS3_MAX_RING_DESC,
 940                 .nb_min = HNS3_MIN_RING_DESC,
 941                 .nb_align = HNS3_ALIGN_RING_DESC,
 942         };
 943
 944         info->tx_desc_lim = (struct rte_eth_desc_lim) {
 945                 .nb_max = HNS3_MAX_RING_DESC,
 946                 .nb_min = HNS3_MIN_RING_DESC,
 947                 .nb_align = HNS3_ALIGN_RING_DESC,
 948         };
 949
 950         info->vmdq_queue_num = 0;
 951
 952         info->reta_size = HNS3_RSS_IND_TBL_SIZE;
 953         info->hash_key_size = HNS3_RSS_KEY_SIZE;
 954         info->flow_type_rss_offloads = HNS3_ETH_RSS_SUPPORT;
 955         info->default_rxportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 956         info->default_txportconf.ring_size = HNS3_DEFAULT_RING_DESC;
 957
 958         return 0;
 959 }
 960
 961 static void
 962 hns3vf_clear_event_cause(struct hns3_hw *hw, uint32_t regclr)
 963 {
 964         hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
 965 }
 966
 967 static void
 968 hns3vf_disable_irq0(struct hns3_hw *hw)
 969 {
 970         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
 971 }
 972
 973 static void
 974 hns3vf_enable_irq0(struct hns3_hw *hw)
 975 {
 976         hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
 977 }
 978
 979 static enum hns3vf_evt_cause
 980 hns3vf_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
 981 {
 982         struct hns3_hw *hw = &hns->hw;
 983         enum hns3vf_evt_cause ret;
 984         uint32_t cmdq_stat_reg;
 985         uint32_t rst_ing_reg;
 986         uint32_t val;
 987
 988         /* Fetch the events from their corresponding regs */
 989         cmdq_stat_reg = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_STAT_REG);
 990
 991         if (BIT(HNS3_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
 992                 rst_ing_reg = hns3_read_dev(hw, HNS3_FUN_RST_ING);
 993                 hns3_warn(hw, "resetting reg: 0x%x", rst_ing_reg);
 994                 hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
 995                 rte_atomic16_set(&hw->reset.disable_cmd, 1);
 996                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
 997                 hns3_write_dev(hw, HNS3_VF_RST_ING, val | HNS3_VF_RST_ING_BIT);
 998                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RST_INT_B);
 999                 if (clearval) {
1000                         hw->reset.stats.global_cnt++;
1001                         hns3_warn(hw, "Global reset detected, clear reset status");
1002                 } else {
1003                         hns3_schedule_delayed_reset(hns);
1004                         hns3_warn(hw, "Global reset detected, don't clear reset status");
1005                 }
1006
1007                 ret = HNS3VF_VECTOR0_EVENT_RST;
1008                 goto out;
1009         }
1010
1011         /* Check for vector0 mailbox(=CMDQ RX) event source */
1012         if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
1013                 val = cmdq_stat_reg & ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
1014                 ret = HNS3VF_VECTOR0_EVENT_MBX;
1015                 goto out;
1016         }
1017
1018         val = 0;
1019         ret = HNS3VF_VECTOR0_EVENT_OTHER;
1020 out:
1021         if (clearval)
1022                 *clearval = val;
1023         return ret;
1024 }
1025
1026 static void
1027 hns3vf_interrupt_handler(void *param)
1028 {
1029         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1030         struct hns3_adapter *hns = dev->data->dev_private;
1031         struct hns3_hw *hw = &hns->hw;
1032         enum hns3vf_evt_cause event_cause;
1033         uint32_t clearval;
1034
1035         if (hw->irq_thread_id == 0)
1036                 hw->irq_thread_id = pthread_self();
1037
1038         /* Disable interrupt */
1039         hns3vf_disable_irq0(hw);
1040
1041         /* Read out interrupt causes */
1042         event_cause = hns3vf_check_event_cause(hns, &clearval);
1043
1044         switch (event_cause) {
1045         case HNS3VF_VECTOR0_EVENT_RST:
1046                 hns3_schedule_reset(hns);
1047                 break;
1048         case HNS3VF_VECTOR0_EVENT_MBX:
1049                 hns3_dev_handle_mbx_msg(hw);
1050                 break;
1051         default:
1052                 break;
1053         }
1054
1055         /* Clear interrupt causes */
1056         hns3vf_clear_event_cause(hw, clearval);
1057
1058         /* Enable interrupt */
1059         hns3vf_enable_irq0(hw);
1060 }
1061
1062 static int
1063 hns3vf_check_tqp_info(struct hns3_hw *hw)
1064 {
1065         uint16_t tqps_num;
1066
1067         tqps_num = hw->tqps_num;
1068         if (tqps_num > HNS3_MAX_TQP_NUM_PER_FUNC || tqps_num == 0) {
1069                 PMD_INIT_LOG(ERR, "Get invalid tqps_num(%u) from PF. valid "
1070                                   "range: 1~%d",
1071                              tqps_num, HNS3_MAX_TQP_NUM_PER_FUNC);
1072                 return -EINVAL;
1073         }
1074
1075         if (hw->rx_buf_len == 0)
1076                 hw->rx_buf_len = HNS3_DEFAULT_RX_BUF_LEN;
1077         hw->alloc_rss_size = RTE_MIN(hw->rss_size_max, hw->tqps_num);
1078
1079         return 0;
1080 }
1081
1082 static int
1083 hns3vf_get_queue_info(struct hns3_hw *hw)
1084 {
1085 #define HNS3VF_TQPS_RSS_INFO_LEN        6
1086         uint8_t resp_msg[HNS3VF_TQPS_RSS_INFO_LEN];
1087         int ret;
1088
1089         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QINFO, 0, NULL, 0, true,
1090                                 resp_msg, HNS3VF_TQPS_RSS_INFO_LEN);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to get tqp info from PF: %d", ret);
1093                 return ret;
1094         }
1095
1096         memcpy(&hw->tqps_num, &resp_msg[0], sizeof(uint16_t));
1097         memcpy(&hw->rss_size_max, &resp_msg[2], sizeof(uint16_t));
1098         memcpy(&hw->rx_buf_len, &resp_msg[4], sizeof(uint16_t));
1099
1100         return hns3vf_check_tqp_info(hw);
1101 }
1102
1103 static int
1104 hns3vf_get_queue_depth(struct hns3_hw *hw)
1105 {
1106 #define HNS3VF_TQPS_DEPTH_INFO_LEN      4
1107         uint8_t resp_msg[HNS3VF_TQPS_DEPTH_INFO_LEN];
1108         int ret;
1109
1110         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_QDEPTH, 0, NULL, 0, true,
1111                                 resp_msg, HNS3VF_TQPS_DEPTH_INFO_LEN);
1112         if (ret) {
1113                 PMD_INIT_LOG(ERR, "Failed to get tqp depth info from PF: %d",
1114                              ret);
1115                 return ret;
1116         }
1117
1118         memcpy(&hw->num_tx_desc, &resp_msg[0], sizeof(uint16_t));
1119         memcpy(&hw->num_rx_desc, &resp_msg[2], sizeof(uint16_t));
1120
1121         return 0;
1122 }
1123
1124 static int
1125 hns3vf_get_tc_info(struct hns3_hw *hw)
1126 {
1127         uint8_t resp_msg;
1128         int ret;
1129
1130         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_TCINFO, 0, NULL, 0,
1131                                 true, &resp_msg, sizeof(resp_msg));
1132         if (ret) {
1133                 hns3_err(hw, "VF request to get TC info from PF failed %d",
1134                          ret);
1135                 return ret;
1136         }
1137
1138         hw->hw_tc_map = resp_msg;
1139
1140         return 0;
1141 }
1142
1143 static int
1144 hns3vf_get_host_mac_addr(struct hns3_hw *hw)
1145 {
1146         uint8_t host_mac[RTE_ETHER_ADDR_LEN];
1147         int ret;
1148
1149         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_MAC_ADDR, 0, NULL, 0,
1150                                 true, host_mac, RTE_ETHER_ADDR_LEN);
1151         if (ret) {
1152                 hns3_err(hw, "Failed to get mac addr from PF: %d", ret);
1153                 return ret;
1154         }
1155
1156         memcpy(hw->mac.mac_addr, host_mac, RTE_ETHER_ADDR_LEN);
1157
1158         return 0;
1159 }
1160
1161 static int
1162 hns3vf_get_configuration(struct hns3_hw *hw)
1163 {
1164         int ret;
1165
1166         hw->mac.media_type = HNS3_MEDIA_TYPE_NONE;
1167         hw->rss_dis_flag = false;
1168
1169         /* Get queue configuration from PF */
1170         ret = hns3vf_get_queue_info(hw);
1171         if (ret)
1172                 return ret;
1173
1174         /* Get queue depth info from PF */
1175         ret = hns3vf_get_queue_depth(hw);
1176         if (ret)
1177                 return ret;
1178
1179         /* Get user defined VF MAC addr from PF */
1180         ret = hns3vf_get_host_mac_addr(hw);
1181         if (ret)
1182                 return ret;
1183
1184         /* Get tc configuration from PF */
1185         return hns3vf_get_tc_info(hw);
1186 }
1187
1188 static int
1189 hns3vf_set_tc_info(struct hns3_adapter *hns)
1190 {
1191         struct hns3_hw *hw = &hns->hw;
1192         uint16_t nb_rx_q = hw->data->nb_rx_queues;
1193         uint16_t nb_tx_q = hw->data->nb_tx_queues;
1194         uint8_t i;
1195
1196         hw->num_tc = 0;
1197         for (i = 0; i < HNS3_MAX_TC_NUM; i++)
1198                 if (hw->hw_tc_map & BIT(i))
1199                         hw->num_tc++;
1200
1201         if (nb_rx_q < hw->num_tc) {
1202                 hns3_err(hw, "number of Rx queues(%d) is less than tcs(%d).",
1203                          nb_rx_q, hw->num_tc);
1204                 return -EINVAL;
1205         }
1206
1207         if (nb_tx_q < hw->num_tc) {
1208                 hns3_err(hw, "number of Tx queues(%d) is less than tcs(%d).",
1209                          nb_tx_q, hw->num_tc);
1210                 return -EINVAL;
1211         }
1212
1213         hns3_set_rss_size(hw, nb_rx_q);
1214         hns3_tc_queue_mapping_cfg(hw, nb_tx_q);
1215
1216         return 0;
1217 }
1218
1219 static void
1220 hns3vf_request_link_info(struct hns3_hw *hw)
1221 {
1222         uint8_t resp_msg;
1223         int ret;
1224
1225         if (rte_atomic16_read(&hw->reset.resetting))
1226                 return;
1227         ret = hns3_send_mbx_msg(hw, HNS3_MBX_GET_LINK_STATUS, 0, NULL, 0, false,
1228                                 &resp_msg, sizeof(resp_msg));
1229         if (ret)
1230                 hns3_err(hw, "Failed to fetch link status from PF: %d", ret);
1231 }
1232
1233 static int
1234 hns3vf_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
1235 {
1236 #define HNS3VF_VLAN_MBX_MSG_LEN 5
1237         struct hns3_hw *hw = &hns->hw;
1238         uint8_t msg_data[HNS3VF_VLAN_MBX_MSG_LEN];
1239         uint16_t proto = htons(RTE_ETHER_TYPE_VLAN);
1240         uint8_t is_kill = on ? 0 : 1;
1241
1242         msg_data[0] = is_kill;
1243         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1244         memcpy(&msg_data[3], &proto, sizeof(proto));
1245
1246         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_FILTER,
1247                                  msg_data, HNS3VF_VLAN_MBX_MSG_LEN, true, NULL,
1248                                  0);
1249 }
1250
1251 static int
1252 hns3vf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1253 {
1254         struct hns3_adapter *hns = dev->data->dev_private;
1255         struct hns3_hw *hw = &hns->hw;
1256         int ret;
1257
1258         if (rte_atomic16_read(&hw->reset.resetting)) {
1259                 hns3_err(hw,
1260                          "vf set vlan id failed during resetting, vlan_id =%u",
1261                          vlan_id);
1262                 return -EIO;
1263         }
1264         rte_spinlock_lock(&hw->lock);
1265         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1266         rte_spinlock_unlock(&hw->lock);
1267         if (ret)
1268                 hns3_err(hw, "vf set vlan id failed, vlan_id =%u, ret =%d",
1269                          vlan_id, ret);
1270
1271         return ret;
1272 }
1273
1274 static int
1275 hns3vf_en_hw_strip_rxvtag(struct hns3_hw *hw, bool enable)
1276 {
1277         uint8_t msg_data;
1278         int ret;
1279
1280         msg_data = enable ? 1 : 0;
1281         ret = hns3_send_mbx_msg(hw, HNS3_MBX_SET_VLAN, HNS3_MBX_VLAN_RX_OFF_CFG,
1282                                 &msg_data, sizeof(msg_data), false, NULL, 0);
1283         if (ret)
1284                 hns3_err(hw, "vf enable strip failed, ret =%d", ret);
1285
1286         return ret;
1287 }
1288
1289 static int
1290 hns3vf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1291 {
1292         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1294         unsigned int tmp_mask;
1295         int ret = 0;
1296
1297         if (rte_atomic16_read(&hw->reset.resetting)) {
1298                 hns3_err(hw, "vf set vlan offload failed during resetting, "
1299                              "mask = 0x%x", mask);
1300                 return -EIO;
1301         }
1302
1303         tmp_mask = (unsigned int)mask;
1304         /* Vlan stripping setting */
1305         if (tmp_mask & ETH_VLAN_STRIP_MASK) {
1306                 rte_spinlock_lock(&hw->lock);
1307                 /* Enable or disable VLAN stripping */
1308                 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1309                         ret = hns3vf_en_hw_strip_rxvtag(hw, true);
1310                 else
1311                         ret = hns3vf_en_hw_strip_rxvtag(hw, false);
1312                 rte_spinlock_unlock(&hw->lock);
1313         }
1314
1315         return ret;
1316 }
1317
1318 static int
1319 hns3vf_handle_all_vlan_table(struct hns3_adapter *hns, int on)
1320 {
1321         struct rte_vlan_filter_conf *vfc;
1322         struct hns3_hw *hw = &hns->hw;
1323         uint16_t vlan_id;
1324         uint64_t vbit;
1325         uint64_t ids;
1326         int ret = 0;
1327         uint32_t i;
1328
1329         vfc = &hw->data->vlan_filter_conf;
1330         for (i = 0; i < RTE_DIM(vfc->ids); i++) {
1331                 if (vfc->ids[i] == 0)
1332                         continue;
1333                 ids = vfc->ids[i];
1334                 while (ids) {
1335                         /*
1336                          * 64 means the num bits of ids, one bit corresponds to
1337                          * one vlan id
1338                          */
1339                         vlan_id = 64 * i;
1340                         /* count trailing zeroes */
1341                         vbit = ~ids & (ids - 1);
1342                         /* clear least significant bit set */
1343                         ids ^= (ids ^ (ids - 1)) ^ vbit;
1344                         for (; vbit;) {
1345                                 vbit >>= 1;
1346                                 vlan_id++;
1347                         }
1348                         ret = hns3vf_vlan_filter_configure(hns, vlan_id, on);
1349                         if (ret) {
1350                                 hns3_err(hw,
1351                                          "VF handle vlan table failed, ret =%d, on = %d",
1352                                          ret, on);
1353                                 return ret;
1354                         }
1355                 }
1356         }
1357
1358         return ret;
1359 }
1360
1361 static int
1362 hns3vf_remove_all_vlan_table(struct hns3_adapter *hns)
1363 {
1364         return hns3vf_handle_all_vlan_table(hns, 0);
1365 }
1366
1367 static int
1368 hns3vf_restore_vlan_conf(struct hns3_adapter *hns)
1369 {
1370         struct hns3_hw *hw = &hns->hw;
1371         struct rte_eth_conf *dev_conf;
1372         bool en;
1373         int ret;
1374
1375         dev_conf = &hw->data->dev_conf;
1376         en = dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP ? true
1377                                                                    : false;
1378         ret = hns3vf_en_hw_strip_rxvtag(hw, en);
1379         if (ret)
1380                 hns3_err(hw, "VF restore vlan conf fail, en =%d, ret =%d", en,
1381                          ret);
1382         return ret;
1383 }
1384
1385 static int
1386 hns3vf_dev_configure_vlan(struct rte_eth_dev *dev)
1387 {
1388         struct hns3_adapter *hns = dev->data->dev_private;
1389         struct rte_eth_dev_data *data = dev->data;
1390         struct hns3_hw *hw = &hns->hw;
1391         int ret;
1392
1393         if (data->dev_conf.txmode.hw_vlan_reject_tagged ||
1394             data->dev_conf.txmode.hw_vlan_reject_untagged ||
1395             data->dev_conf.txmode.hw_vlan_insert_pvid) {
1396                 hns3_warn(hw, "hw_vlan_reject_tagged, hw_vlan_reject_untagged "
1397                               "or hw_vlan_insert_pvid is not support!");
1398         }
1399
1400         /* Apply vlan offload setting */
1401         ret = hns3vf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1402         if (ret)
1403                 hns3_err(hw, "dev config vlan offload failed, ret =%d", ret);
1404
1405         return ret;
1406 }
1407
1408 static int
1409 hns3vf_set_alive(struct hns3_hw *hw, bool alive)
1410 {
1411         uint8_t msg_data;
1412
1413         msg_data = alive ? 1 : 0;
1414         return hns3_send_mbx_msg(hw, HNS3_MBX_SET_ALIVE, 0, &msg_data,
1415                                  sizeof(msg_data), false, NULL, 0);
1416 }
1417
1418 static void
1419 hns3vf_keep_alive_handler(void *param)
1420 {
1421         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1422         struct hns3_adapter *hns = eth_dev->data->dev_private;
1423         struct hns3_hw *hw = &hns->hw;
1424         uint8_t respmsg;
1425         int ret;
1426
1427         ret = hns3_send_mbx_msg(hw, HNS3_MBX_KEEP_ALIVE, 0, NULL, 0,
1428                                 false, &respmsg, sizeof(uint8_t));
1429         if (ret)
1430                 hns3_err(hw, "VF sends keeping alive cmd failed(=%d)",
1431                          ret);
1432
1433         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
1434                           eth_dev);
1435 }
1436
1437 static void
1438 hns3vf_service_handler(void *param)
1439 {
1440         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1441         struct hns3_adapter *hns = eth_dev->data->dev_private;
1442         struct hns3_hw *hw = &hns->hw;
1443
1444         /*
1445          * The query link status and reset processing are executed in the
1446          * interrupt thread.When the IMP reset occurs, IMP will not respond,
1447          * and the query operation will time out after 30ms. In the case of
1448          * multiple PF/VFs, each query failure timeout causes the IMP reset
1449          * interrupt to fail to respond within 100ms.
1450          * Before querying the link status, check whether there is a reset
1451          * pending, and if so, abandon the query.
1452          */
1453         if (!hns3vf_is_reset_pending(hns))
1454                 hns3vf_request_link_info(hw);
1455         else
1456                 hns3_warn(hw, "Cancel the query when reset is pending");
1457
1458         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler,
1459                           eth_dev);
1460 }
1461
1462 static int
1463 hns3_query_vf_resource(struct hns3_hw *hw)
1464 {
1465         struct hns3_vf_res_cmd *req;
1466         struct hns3_cmd_desc desc;
1467         uint16_t num_msi;
1468         int ret;
1469
1470         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_VF_RSRC, true);
1471         ret = hns3_cmd_send(hw, &desc, 1);
1472         if (ret) {
1473                 hns3_err(hw, "query vf resource failed, ret = %d", ret);
1474                 return ret;
1475         }
1476
1477         req = (struct hns3_vf_res_cmd *)desc.data;
1478         num_msi = hns3_get_field(rte_le_to_cpu_16(req->vf_intr_vector_number),
1479                                  HNS3_VEC_NUM_M, HNS3_VEC_NUM_S);
1480         if (num_msi < HNS3_MIN_VECTOR_NUM) {
1481                 hns3_err(hw, "Just %u msi resources, not enough for vf(min:%d)",
1482                          num_msi, HNS3_MIN_VECTOR_NUM);
1483                 return -EINVAL;
1484         }
1485
1486         hw->num_msi = num_msi;
1487
1488         return 0;
1489 }
1490
1491 static int
1492 hns3vf_init_hardware(struct hns3_adapter *hns)
1493 {
1494         struct hns3_hw *hw = &hns->hw;
1495         uint16_t mtu = hw->data->mtu;
1496         int ret;
1497
1498         ret = hns3vf_set_promisc_mode(hw, true, false, false);
1499         if (ret)
1500                 return ret;
1501
1502         ret = hns3vf_config_mtu(hw, mtu);
1503         if (ret)
1504                 goto err_init_hardware;
1505
1506         ret = hns3vf_vlan_filter_configure(hns, 0, 1);
1507         if (ret) {
1508                 PMD_INIT_LOG(ERR, "Failed to initialize VLAN config: %d", ret);
1509                 goto err_init_hardware;
1510         }
1511
1512         ret = hns3_config_gro(hw, false);
1513         if (ret) {
1514                 PMD_INIT_LOG(ERR, "Failed to config gro: %d", ret);
1515                 goto err_init_hardware;
1516         }
1517
1518         /*
1519          * In the initialization clearing the all hardware mapping relationship
1520          * configurations between queues and interrupt vectors is needed, so
1521          * some error caused by the residual configurations, such as the
1522          * unexpected interrupt, can be avoid.
1523          */
1524         ret = hns3vf_init_ring_with_vector(hw);
1525         if (ret) {
1526                 PMD_INIT_LOG(ERR, "Failed to init ring intr vector: %d", ret);
1527                 goto err_init_hardware;
1528         }
1529
1530         ret = hns3vf_set_alive(hw, true);
1531         if (ret) {
1532                 PMD_INIT_LOG(ERR, "Failed to VF send alive to PF: %d", ret);
1533                 goto err_init_hardware;
1534         }
1535
1536         hns3vf_request_link_info(hw);
1537         return 0;
1538
1539 err_init_hardware:
1540         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1541         return ret;
1542 }
1543
1544 static int
1545 hns3vf_clear_vport_list(struct hns3_hw *hw)
1546 {
1547         return hns3_send_mbx_msg(hw, HNS3_MBX_HANDLE_VF_TBL,
1548                                  HNS3_MBX_VPORT_LIST_CLEAR, NULL, 0, false,
1549                                  NULL, 0);
1550 }
1551
1552 static int
1553 hns3vf_init_vf(struct rte_eth_dev *eth_dev)
1554 {
1555         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1556         struct hns3_adapter *hns = eth_dev->data->dev_private;
1557         struct hns3_hw *hw = &hns->hw;
1558         int ret;
1559
1560         PMD_INIT_FUNC_TRACE();
1561
1562         /* Get hardware io base address from pcie BAR2 IO space */
1563         hw->io_base = pci_dev->mem_resource[2].addr;
1564
1565         /* Firmware command queue initialize */
1566         ret = hns3_cmd_init_queue(hw);
1567         if (ret) {
1568                 PMD_INIT_LOG(ERR, "Failed to init cmd queue: %d", ret);
1569                 goto err_cmd_init_queue;
1570         }
1571
1572         /* Firmware command initialize */
1573         ret = hns3_cmd_init(hw);
1574         if (ret) {
1575                 PMD_INIT_LOG(ERR, "Failed to init cmd: %d", ret);
1576                 goto err_cmd_init;
1577         }
1578
1579         /* Get VF resource */
1580         ret = hns3_query_vf_resource(hw);
1581         if (ret)
1582                 goto err_cmd_init;
1583
1584         rte_spinlock_init(&hw->mbx_resp.lock);
1585
1586         hns3vf_clear_event_cause(hw, 0);
1587
1588         ret = rte_intr_callback_register(&pci_dev->intr_handle,
1589                                          hns3vf_interrupt_handler, eth_dev);
1590         if (ret) {
1591                 PMD_INIT_LOG(ERR, "Failed to register intr: %d", ret);
1592                 goto err_intr_callback_register;
1593         }
1594
1595         /* Enable interrupt */
1596         rte_intr_enable(&pci_dev->intr_handle);
1597         hns3vf_enable_irq0(hw);
1598
1599         /* Get configuration from PF */
1600         ret = hns3vf_get_configuration(hw);
1601         if (ret) {
1602                 PMD_INIT_LOG(ERR, "Failed to fetch configuration: %d", ret);
1603                 goto err_get_config;
1604         }
1605
1606         /*
1607          * The hns3 PF ethdev driver in kernel support setting VF MAC address
1608          * on the host by "ip link set ..." command. To avoid some incorrect
1609          * scenes, for example, hns3 VF PMD driver fails to receive and send
1610          * packets after user configure the MAC address by using the
1611          * "ip link set ..." command, hns3 VF PMD driver keep the same MAC
1612          * address strategy as the hns3 kernel ethdev driver in the
1613          * initialization. If user configure a MAC address by the ip command
1614          * for VF device, then hns3 VF PMD driver will start with it, otherwise
1615          * start with a random MAC address in the initialization.
1616          */
1617         ret = rte_is_zero_ether_addr((struct rte_ether_addr *)hw->mac.mac_addr);
1618         if (ret)
1619                 rte_eth_random_addr(hw->mac.mac_addr);
1620
1621         ret = hns3vf_clear_vport_list(hw);
1622         if (ret) {
1623                 PMD_INIT_LOG(ERR, "Failed to clear tbl list: %d", ret);
1624                 goto err_get_config;
1625         }
1626
1627         ret = hns3vf_init_hardware(hns);
1628         if (ret)
1629                 goto err_get_config;
1630
1631         hns3_set_default_rss_args(hw);
1632
1633         return 0;
1634
1635 err_get_config:
1636         hns3vf_disable_irq0(hw);
1637         rte_intr_disable(&pci_dev->intr_handle);
1638         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1639                              eth_dev);
1640 err_intr_callback_register:
1641 err_cmd_init:
1642         hns3_cmd_uninit(hw);
1643         hns3_cmd_destroy_queue(hw);
1644 err_cmd_init_queue:
1645         hw->io_base = NULL;
1646
1647         return ret;
1648 }
1649
1650 static void
1651 hns3vf_uninit_vf(struct rte_eth_dev *eth_dev)
1652 {
1653         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1654         struct hns3_adapter *hns = eth_dev->data->dev_private;
1655         struct hns3_hw *hw = &hns->hw;
1656
1657         PMD_INIT_FUNC_TRACE();
1658
1659         hns3_rss_uninit(hns);
1660         (void)hns3_config_gro(hw, false);
1661         (void)hns3vf_set_alive(hw, false);
1662         (void)hns3vf_set_promisc_mode(hw, false, false, false);
1663         hns3vf_disable_irq0(hw);
1664         rte_intr_disable(&pci_dev->intr_handle);
1665         hns3_intr_unregister(&pci_dev->intr_handle, hns3vf_interrupt_handler,
1666                              eth_dev);
1667         hns3_cmd_uninit(hw);
1668         hns3_cmd_destroy_queue(hw);
1669         hw->io_base = NULL;
1670 }
1671
1672 static int
1673 hns3vf_do_stop(struct hns3_adapter *hns)
1674 {
1675         struct hns3_hw *hw = &hns->hw;
1676         bool reset_queue;
1677
1678         hw->mac.link_status = ETH_LINK_DOWN;
1679
1680         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0) {
1681                 hns3vf_configure_mac_addr(hns, true);
1682                 reset_queue = true;
1683         } else
1684                 reset_queue = false;
1685         return hns3_stop_queues(hns, reset_queue);
1686 }
1687
1688 static void
1689 hns3vf_unmap_rx_interrupt(struct rte_eth_dev *dev)
1690 {
1691         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1695         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1696         uint16_t q_id;
1697
1698         if (dev->data->dev_conf.intr_conf.rxq == 0)
1699                 return;
1700
1701         /* unmap the ring with vector */
1702         if (rte_intr_allow_others(intr_handle)) {
1703                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1704                 base = RTE_INTR_VEC_RXTX_OFFSET;
1705         }
1706         if (rte_intr_dp_is_en(intr_handle)) {
1707                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1708                         (void)hns3vf_bind_ring_with_vector(hw, vec, false,
1709                                                            HNS3_RING_TYPE_RX,
1710                                                            q_id);
1711                         if (vec < base + intr_handle->nb_efd - 1)
1712                                 vec++;
1713                 }
1714         }
1715         /* Clean datapath event and queue/vec mapping */
1716         rte_intr_efd_disable(intr_handle);
1717         if (intr_handle->intr_vec) {
1718                 rte_free(intr_handle->intr_vec);
1719                 intr_handle->intr_vec = NULL;
1720         }
1721 }
1722
1723 static void
1724 hns3vf_dev_stop(struct rte_eth_dev *dev)
1725 {
1726         struct hns3_adapter *hns = dev->data->dev_private;
1727         struct hns3_hw *hw = &hns->hw;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         hw->adapter_state = HNS3_NIC_STOPPING;
1732         hns3_set_rxtx_function(dev);
1733         rte_wmb();
1734         /* Disable datapath on secondary process. */
1735         hns3_mp_req_stop_rxtx(dev);
1736         /* Prevent crashes when queues are still in use. */
1737         rte_delay_ms(hw->tqps_num);
1738
1739         rte_spinlock_lock(&hw->lock);
1740         if (rte_atomic16_read(&hw->reset.resetting) == 0) {
1741                 hns3vf_do_stop(hns);
1742                 hns3vf_unmap_rx_interrupt(dev);
1743                 hns3_dev_release_mbufs(hns);
1744                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1745         }
1746         rte_eal_alarm_cancel(hns3vf_service_handler, dev);
1747         rte_spinlock_unlock(&hw->lock);
1748 }
1749
1750 static void
1751 hns3vf_dev_close(struct rte_eth_dev *eth_dev)
1752 {
1753         struct hns3_adapter *hns = eth_dev->data->dev_private;
1754         struct hns3_hw *hw = &hns->hw;
1755
1756         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1757                 return;
1758
1759         if (hw->adapter_state == HNS3_NIC_STARTED)
1760                 hns3vf_dev_stop(eth_dev);
1761
1762         hw->adapter_state = HNS3_NIC_CLOSING;
1763         hns3_reset_abort(hns);
1764         hw->adapter_state = HNS3_NIC_CLOSED;
1765         rte_eal_alarm_cancel(hns3vf_keep_alive_handler, eth_dev);
1766         hns3vf_configure_all_mc_mac_addr(hns, true);
1767         hns3vf_remove_all_vlan_table(hns);
1768         hns3vf_uninit_vf(eth_dev);
1769         hns3_free_all_queues(eth_dev);
1770         rte_free(hw->reset.wait_data);
1771         rte_free(eth_dev->process_private);
1772         eth_dev->process_private = NULL;
1773         hns3_mp_uninit_primary();
1774         hns3_warn(hw, "Close port %d finished", hw->data->port_id);
1775 }
1776
1777 static int
1778 hns3vf_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
1779                       size_t fw_size)
1780 {
1781         struct hns3_adapter *hns = eth_dev->data->dev_private;
1782         struct hns3_hw *hw = &hns->hw;
1783         uint32_t version = hw->fw_version;
1784         int ret;
1785
1786         ret = snprintf(fw_version, fw_size, "%lu.%lu.%lu.%lu",
1787                        hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
1788                                       HNS3_FW_VERSION_BYTE3_S),
1789                        hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M,
1790                                       HNS3_FW_VERSION_BYTE2_S),
1791                        hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M,
1792                                       HNS3_FW_VERSION_BYTE1_S),
1793                        hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M,
1794                                       HNS3_FW_VERSION_BYTE0_S));
1795         ret += 1; /* add the size of '\0' */
1796         if (fw_size < (uint32_t)ret)
1797                 return ret;
1798         else
1799                 return 0;
1800 }
1801
1802 static int
1803 hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
1804                        __rte_unused int wait_to_complete)
1805 {
1806         struct hns3_adapter *hns = eth_dev->data->dev_private;
1807         struct hns3_hw *hw = &hns->hw;
1808         struct hns3_mac *mac = &hw->mac;
1809         struct rte_eth_link new_link;
1810
1811         memset(&new_link, 0, sizeof(new_link));
1812         switch (mac->link_speed) {
1813         case ETH_SPEED_NUM_10M:
1814         case ETH_SPEED_NUM_100M:
1815         case ETH_SPEED_NUM_1G:
1816         case ETH_SPEED_NUM_10G:
1817         case ETH_SPEED_NUM_25G:
1818         case ETH_SPEED_NUM_40G:
1819         case ETH_SPEED_NUM_50G:
1820         case ETH_SPEED_NUM_100G:
1821                 new_link.link_speed = mac->link_speed;
1822                 break;
1823         default:
1824                 new_link.link_speed = ETH_SPEED_NUM_100M;
1825                 break;
1826         }
1827
1828         new_link.link_duplex = mac->link_duplex;
1829         new_link.link_status = mac->link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
1830         new_link.link_autoneg =
1831             !(eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED);
1832
1833         return rte_eth_linkstatus_set(eth_dev, &new_link);
1834 }
1835
1836 static int
1837 hns3vf_do_start(struct hns3_adapter *hns, bool reset_queue)
1838 {
1839         struct hns3_hw *hw = &hns->hw;
1840         int ret;
1841
1842         ret = hns3vf_set_tc_info(hns);
1843         if (ret)
1844                 return ret;
1845
1846         ret = hns3_start_queues(hns, reset_queue);
1847         if (ret)
1848                 hns3_err(hw, "Failed to start queues: %d", ret);
1849
1850         return ret;
1851 }
1852
1853 static int
1854 hns3vf_map_rx_interrupt(struct rte_eth_dev *dev)
1855 {
1856         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1857         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1858         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         uint8_t base = RTE_INTR_VEC_ZERO_OFFSET;
1860         uint8_t vec = RTE_INTR_VEC_ZERO_OFFSET;
1861         uint32_t intr_vector;
1862         uint16_t q_id;
1863         int ret;
1864
1865         if (dev->data->dev_conf.intr_conf.rxq == 0)
1866                 return 0;
1867
1868         /* disable uio/vfio intr/eventfd mapping */
1869         rte_intr_disable(intr_handle);
1870
1871         /* check and configure queue intr-vector mapping */
1872         if (rte_intr_cap_multiple(intr_handle) ||
1873             !RTE_ETH_DEV_SRIOV(dev).active) {
1874                 intr_vector = hw->used_rx_queues;
1875                 /* It creates event fd for each intr vector when MSIX is used */
1876                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1877                         return -EINVAL;
1878         }
1879         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1880                 intr_handle->intr_vec =
1881                         rte_zmalloc("intr_vec",
1882                                     hw->used_rx_queues * sizeof(int), 0);
1883                 if (intr_handle->intr_vec == NULL) {
1884                         hns3_err(hw, "Failed to allocate %d rx_queues"
1885                                      " intr_vec", hw->used_rx_queues);
1886                         ret = -ENOMEM;
1887                         goto vf_alloc_intr_vec_error;
1888                 }
1889         }
1890
1891         if (rte_intr_allow_others(intr_handle)) {
1892                 vec = RTE_INTR_VEC_RXTX_OFFSET;
1893                 base = RTE_INTR_VEC_RXTX_OFFSET;
1894         }
1895         if (rte_intr_dp_is_en(intr_handle)) {
1896                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1897                         ret = hns3vf_bind_ring_with_vector(hw, vec, true,
1898                                                            HNS3_RING_TYPE_RX,
1899                                                            q_id);
1900                         if (ret)
1901                                 goto vf_bind_vector_error;
1902                         intr_handle->intr_vec[q_id] = vec;
1903                         if (vec < base + intr_handle->nb_efd - 1)
1904                                 vec++;
1905                 }
1906         }
1907         rte_intr_enable(intr_handle);
1908         return 0;
1909
1910 vf_bind_vector_error:
1911         rte_intr_efd_disable(intr_handle);
1912         if (intr_handle->intr_vec) {
1913                 free(intr_handle->intr_vec);
1914                 intr_handle->intr_vec = NULL;
1915         }
1916         return ret;
1917 vf_alloc_intr_vec_error:
1918         rte_intr_efd_disable(intr_handle);
1919         return ret;
1920 }
1921
1922 static int
1923 hns3vf_restore_rx_interrupt(struct hns3_hw *hw)
1924 {
1925         struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
1926         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1927         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1928         uint16_t q_id;
1929         int ret;
1930
1931         if (dev->data->dev_conf.intr_conf.rxq == 0)
1932                 return 0;
1933
1934         if (rte_intr_dp_is_en(intr_handle)) {
1935                 for (q_id = 0; q_id < hw->used_rx_queues; q_id++) {
1936                         ret = hns3vf_bind_ring_with_vector(hw,
1937                                         intr_handle->intr_vec[q_id], true,
1938                                         HNS3_RING_TYPE_RX, q_id);
1939                         if (ret)
1940                                 return ret;
1941                 }
1942         }
1943
1944         return 0;
1945 }
1946
1947 static void
1948 hns3vf_restore_filter(struct rte_eth_dev *dev)
1949 {
1950         hns3_restore_rss_filter(dev);
1951 }
1952
1953 static int
1954 hns3vf_dev_start(struct rte_eth_dev *dev)
1955 {
1956         struct hns3_adapter *hns = dev->data->dev_private;
1957         struct hns3_hw *hw = &hns->hw;
1958         int ret;
1959
1960         PMD_INIT_FUNC_TRACE();
1961         if (rte_atomic16_read(&hw->reset.resetting))
1962                 return -EBUSY;
1963
1964         rte_spinlock_lock(&hw->lock);
1965         hw->adapter_state = HNS3_NIC_STARTING;
1966         ret = hns3vf_do_start(hns, true);
1967         if (ret) {
1968                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1969                 rte_spinlock_unlock(&hw->lock);
1970                 return ret;
1971         }
1972         ret = hns3vf_map_rx_interrupt(dev);
1973         if (ret) {
1974                 hw->adapter_state = HNS3_NIC_CONFIGURED;
1975                 rte_spinlock_unlock(&hw->lock);
1976                 return ret;
1977         }
1978         hw->adapter_state = HNS3_NIC_STARTED;
1979         rte_spinlock_unlock(&hw->lock);
1980
1981         hns3_set_rxtx_function(dev);
1982         hns3_mp_req_start_rxtx(dev);
1983         rte_eal_alarm_set(HNS3VF_SERVICE_INTERVAL, hns3vf_service_handler, dev);
1984
1985         hns3vf_restore_filter(dev);
1986
1987         /* Enable interrupt of all rx queues before enabling queues */
1988         hns3_dev_all_rx_queue_intr_enable(hw, true);
1989         /*
1990          * When finished the initialization, enable queues to receive/transmit
1991          * packets.
1992          */
1993         hns3_enable_all_queues(hw, true);
1994
1995         return ret;
1996 }
1997
1998 static bool
1999 is_vf_reset_done(struct hns3_hw *hw)
2000 {
2001 #define HNS3_FUN_RST_ING_BITS \
2002         (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) | \
2003          BIT(HNS3_VECTOR0_CORERESET_INT_B) | \
2004          BIT(HNS3_VECTOR0_IMPRESET_INT_B) | \
2005          BIT(HNS3_VECTOR0_FUNCRESET_INT_B))
2006
2007         uint32_t val;
2008
2009         if (hw->reset.level == HNS3_VF_RESET) {
2010                 val = hns3_read_dev(hw, HNS3_VF_RST_ING);
2011                 if (val & HNS3_VF_RST_ING_BIT)
2012                         return false;
2013         } else {
2014                 val = hns3_read_dev(hw, HNS3_FUN_RST_ING);
2015                 if (val & HNS3_FUN_RST_ING_BITS)
2016                         return false;
2017         }
2018         return true;
2019 }
2020
2021 bool
2022 hns3vf_is_reset_pending(struct hns3_adapter *hns)
2023 {
2024         struct hns3_hw *hw = &hns->hw;
2025         enum hns3_reset_level reset;
2026
2027         hns3vf_check_event_cause(hns, NULL);
2028         reset = hns3vf_get_reset_level(hw, &hw->reset.pending);
2029         if (hw->reset.level != HNS3_NONE_RESET && hw->reset.level < reset) {
2030                 hns3_warn(hw, "High level reset %d is pending", reset);
2031                 return true;
2032         }
2033         return false;
2034 }
2035
2036 static int
2037 hns3vf_wait_hardware_ready(struct hns3_adapter *hns)
2038 {
2039         struct hns3_hw *hw = &hns->hw;
2040         struct hns3_wait_data *wait_data = hw->reset.wait_data;
2041         struct timeval tv;
2042
2043         if (wait_data->result == HNS3_WAIT_SUCCESS) {
2044                 /*
2045                  * After vf reset is ready, the PF may not have completed
2046                  * the reset processing. The vf sending mbox to PF may fail
2047                  * during the pf reset, so it is better to add extra delay.
2048                  */
2049                 if (hw->reset.level == HNS3_VF_FUNC_RESET ||
2050                     hw->reset.level == HNS3_FLR_RESET)
2051                         return 0;
2052                 /* Reset retry process, no need to add extra delay. */
2053                 if (hw->reset.attempts)
2054                         return 0;
2055                 if (wait_data->check_completion == NULL)
2056                         return 0;
2057
2058                 wait_data->check_completion = NULL;
2059                 wait_data->interval = 1 * MSEC_PER_SEC * USEC_PER_MSEC;
2060                 wait_data->count = 1;
2061                 wait_data->result = HNS3_WAIT_REQUEST;
2062                 rte_eal_alarm_set(wait_data->interval, hns3_wait_callback,
2063                                   wait_data);
2064                 hns3_warn(hw, "hardware is ready, delay 1 sec for PF reset complete");
2065                 return -EAGAIN;
2066         } else if (wait_data->result == HNS3_WAIT_TIMEOUT) {
2067                 gettimeofday(&tv, NULL);
2068                 hns3_warn(hw, "Reset step4 hardware not ready after reset time=%ld.%.6ld",
2069                           tv.tv_sec, tv.tv_usec);
2070                 return -ETIME;
2071         } else if (wait_data->result == HNS3_WAIT_REQUEST)
2072                 return -EAGAIN;
2073
2074         wait_data->hns = hns;
2075         wait_data->check_completion = is_vf_reset_done;
2076         wait_data->end_ms = (uint64_t)HNS3VF_RESET_WAIT_CNT *
2077                                       HNS3VF_RESET_WAIT_MS + get_timeofday_ms();
2078         wait_data->interval = HNS3VF_RESET_WAIT_MS * USEC_PER_MSEC;
2079         wait_data->count = HNS3VF_RESET_WAIT_CNT;
2080         wait_data->result = HNS3_WAIT_REQUEST;
2081         rte_eal_alarm_set(wait_data->interval, hns3_wait_callback, wait_data);
2082         return -EAGAIN;
2083 }
2084
2085 static int
2086 hns3vf_prepare_reset(struct hns3_adapter *hns)
2087 {
2088         struct hns3_hw *hw = &hns->hw;
2089         int ret = 0;
2090
2091         if (hw->reset.level == HNS3_VF_FUNC_RESET) {
2092                 ret = hns3_send_mbx_msg(hw, HNS3_MBX_RESET, 0, NULL,
2093                                         0, true, NULL, 0);
2094         }
2095         rte_atomic16_set(&hw->reset.disable_cmd, 1);
2096
2097         return ret;
2098 }
2099
2100 static int
2101 hns3vf_stop_service(struct hns3_adapter *hns)
2102 {
2103         struct hns3_hw *hw = &hns->hw;
2104         struct rte_eth_dev *eth_dev;
2105
2106         eth_dev = &rte_eth_devices[hw->data->port_id];
2107         if (hw->adapter_state == HNS3_NIC_STARTED)
2108                 rte_eal_alarm_cancel(hns3vf_service_handler, eth_dev);
2109         hw->mac.link_status = ETH_LINK_DOWN;
2110
2111         hns3_set_rxtx_function(eth_dev);
2112         rte_wmb();
2113         /* Disable datapath on secondary process. */
2114         hns3_mp_req_stop_rxtx(eth_dev);
2115         rte_delay_ms(hw->tqps_num);
2116
2117         rte_spinlock_lock(&hw->lock);
2118         if (hw->adapter_state == HNS3_NIC_STARTED ||
2119             hw->adapter_state == HNS3_NIC_STOPPING) {
2120                 hns3vf_do_stop(hns);
2121                 hw->reset.mbuf_deferred_free = true;
2122         } else
2123                 hw->reset.mbuf_deferred_free = false;
2124
2125         /*
2126          * It is cumbersome for hardware to pick-and-choose entries for deletion
2127          * from table space. Hence, for function reset software intervention is
2128          * required to delete the entries.
2129          */
2130         if (rte_atomic16_read(&hw->reset.disable_cmd) == 0)
2131                 hns3vf_configure_all_mc_mac_addr(hns, true);
2132         rte_spinlock_unlock(&hw->lock);
2133
2134         return 0;
2135 }
2136
2137 static int
2138 hns3vf_start_service(struct hns3_adapter *hns)
2139 {
2140         struct hns3_hw *hw = &hns->hw;
2141         struct rte_eth_dev *eth_dev;
2142
2143         eth_dev = &rte_eth_devices[hw->data->port_id];
2144         hns3_set_rxtx_function(eth_dev);
2145         hns3_mp_req_start_rxtx(eth_dev);
2146         if (hw->adapter_state == HNS3_NIC_STARTED) {
2147                 hns3vf_service_handler(eth_dev);
2148
2149                 /* Enable interrupt of all rx queues before enabling queues */
2150                 hns3_dev_all_rx_queue_intr_enable(hw, true);
2151                 /*
2152                  * When finished the initialization, enable queues to receive
2153                  * and transmit packets.
2154                  */
2155                 hns3_enable_all_queues(hw, true);
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int
2162 hns3vf_check_default_mac_change(struct hns3_hw *hw)
2163 {
2164         char mac_str[RTE_ETHER_ADDR_FMT_SIZE];
2165         struct rte_ether_addr *hw_mac;
2166         int ret;
2167
2168         /*
2169          * The hns3 PF ethdev driver in kernel support setting VF MAC address
2170          * on the host by "ip link set ..." command. If the hns3 PF kernel
2171          * ethdev driver sets the MAC address for VF device after the
2172          * initialization of the related VF device, the PF driver will notify
2173          * VF driver to reset VF device to make the new MAC address effective
2174          * immediately. The hns3 VF PMD driver should check whether the MAC
2175          * address has been changed by the PF kernel ethdev driver, if changed
2176          * VF driver should configure hardware using the new MAC address in the
2177          * recovering hardware configuration stage of the reset process.
2178          */
2179         ret = hns3vf_get_host_mac_addr(hw);
2180         if (ret)
2181                 return ret;
2182
2183         hw_mac = (struct rte_ether_addr *)hw->mac.mac_addr;
2184         ret = rte_is_zero_ether_addr(hw_mac);
2185         if (ret) {
2186                 rte_ether_addr_copy(&hw->data->mac_addrs[0], hw_mac);
2187         } else {
2188                 ret = rte_is_same_ether_addr(&hw->data->mac_addrs[0], hw_mac);
2189                 if (!ret) {
2190                         rte_ether_addr_copy(hw_mac, &hw->data->mac_addrs[0]);
2191                         rte_ether_format_addr(mac_str, RTE_ETHER_ADDR_FMT_SIZE,
2192                                               &hw->data->mac_addrs[0]);
2193                         hns3_warn(hw, "Default MAC address has been changed to:"
2194                                   " %s by the host PF kernel ethdev driver",
2195                                   mac_str);
2196                 }
2197         }
2198
2199         return 0;
2200 }
2201
2202 static int
2203 hns3vf_restore_conf(struct hns3_adapter *hns)
2204 {
2205         struct hns3_hw *hw = &hns->hw;
2206         int ret;
2207
2208         ret = hns3vf_check_default_mac_change(hw);
2209         if (ret)
2210                 return ret;
2211
2212         ret = hns3vf_configure_mac_addr(hns, false);
2213         if (ret)
2214                 return ret;
2215
2216         ret = hns3vf_configure_all_mc_mac_addr(hns, false);
2217         if (ret)
2218                 goto err_mc_mac;
2219
2220         ret = hns3vf_restore_promisc(hns);
2221         if (ret)
2222                 goto err_vlan_table;
2223
2224         ret = hns3vf_restore_vlan_conf(hns);
2225         if (ret)
2226                 goto err_vlan_table;
2227
2228         ret = hns3vf_restore_rx_interrupt(hw);
2229         if (ret)
2230                 goto err_vlan_table;
2231
2232         ret = hns3_restore_gro_conf(hw);
2233         if (ret)
2234                 goto err_vlan_table;
2235
2236         if (hw->adapter_state == HNS3_NIC_STARTED) {
2237                 ret = hns3vf_do_start(hns, false);
2238                 if (ret)
2239                         goto err_vlan_table;
2240                 hns3_info(hw, "hns3vf dev restart successful!");
2241         } else if (hw->adapter_state == HNS3_NIC_STOPPING)
2242                 hw->adapter_state = HNS3_NIC_CONFIGURED;
2243         return 0;
2244
2245 err_vlan_table:
2246         hns3vf_configure_all_mc_mac_addr(hns, true);
2247 err_mc_mac:
2248         hns3vf_configure_mac_addr(hns, true);
2249         return ret;
2250 }
2251
2252 static enum hns3_reset_level
2253 hns3vf_get_reset_level(struct hns3_hw *hw, uint64_t *levels)
2254 {
2255         enum hns3_reset_level reset_level;
2256
2257         /* return the highest priority reset level amongst all */
2258         if (hns3_atomic_test_bit(HNS3_VF_RESET, levels))
2259                 reset_level = HNS3_VF_RESET;
2260         else if (hns3_atomic_test_bit(HNS3_VF_FULL_RESET, levels))
2261                 reset_level = HNS3_VF_FULL_RESET;
2262         else if (hns3_atomic_test_bit(HNS3_VF_PF_FUNC_RESET, levels))
2263                 reset_level = HNS3_VF_PF_FUNC_RESET;
2264         else if (hns3_atomic_test_bit(HNS3_VF_FUNC_RESET, levels))
2265                 reset_level = HNS3_VF_FUNC_RESET;
2266         else if (hns3_atomic_test_bit(HNS3_FLR_RESET, levels))
2267                 reset_level = HNS3_FLR_RESET;
2268         else
2269                 reset_level = HNS3_NONE_RESET;
2270
2271         if (hw->reset.level != HNS3_NONE_RESET && reset_level < hw->reset.level)
2272                 return HNS3_NONE_RESET;
2273
2274         return reset_level;
2275 }
2276
2277 static void
2278 hns3vf_reset_service(void *param)
2279 {
2280         struct hns3_adapter *hns = (struct hns3_adapter *)param;
2281         struct hns3_hw *hw = &hns->hw;
2282         enum hns3_reset_level reset_level;
2283         struct timeval tv_delta;
2284         struct timeval tv_start;
2285         struct timeval tv;
2286         uint64_t msec;
2287
2288         /*
2289          * The interrupt is not triggered within the delay time.
2290          * The interrupt may have been lost. It is necessary to handle
2291          * the interrupt to recover from the error.
2292          */
2293         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) {
2294                 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED);
2295                 hns3_err(hw, "Handling interrupts in delayed tasks");
2296                 hns3vf_interrupt_handler(&rte_eth_devices[hw->data->port_id]);
2297                 reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2298                 if (reset_level == HNS3_NONE_RESET) {
2299                         hns3_err(hw, "No reset level is set, try global reset");
2300                         hns3_atomic_set_bit(HNS3_VF_RESET, &hw->reset.pending);
2301                 }
2302         }
2303         rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_NONE);
2304
2305         /*
2306          * Hardware reset has been notified, we now have to poll & check if
2307          * hardware has actually completed the reset sequence.
2308          */
2309         reset_level = hns3vf_get_reset_level(hw, &hw->reset.pending);
2310         if (reset_level != HNS3_NONE_RESET) {
2311                 gettimeofday(&tv_start, NULL);
2312                 hns3_reset_process(hns, reset_level);
2313                 gettimeofday(&tv, NULL);
2314                 timersub(&tv, &tv_start, &tv_delta);
2315                 msec = tv_delta.tv_sec * MSEC_PER_SEC +
2316                        tv_delta.tv_usec / USEC_PER_MSEC;
2317                 if (msec > HNS3_RESET_PROCESS_MS)
2318                         hns3_err(hw, "%d handle long time delta %" PRIx64
2319                                  " ms time=%ld.%.6ld",
2320                                  hw->reset.level, msec, tv.tv_sec, tv.tv_usec);
2321         }
2322 }
2323
2324 static int
2325 hns3vf_reinit_dev(struct hns3_adapter *hns)
2326 {
2327         struct rte_eth_dev *eth_dev = &rte_eth_devices[hns->hw.data->port_id];
2328         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2329         struct hns3_hw *hw = &hns->hw;
2330         int ret;
2331
2332         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2333                 rte_intr_disable(&pci_dev->intr_handle);
2334                 hns3vf_set_bus_master(pci_dev, true);
2335         }
2336
2337         /* Firmware command initialize */
2338         ret = hns3_cmd_init(hw);
2339         if (ret) {
2340                 hns3_err(hw, "Failed to init cmd: %d", ret);
2341                 return ret;
2342         }
2343
2344         if (hw->reset.level == HNS3_VF_FULL_RESET) {
2345                 /*
2346                  * UIO enables msix by writing the pcie configuration space
2347                  * vfio_pci enables msix in rte_intr_enable.
2348                  */
2349                 if (pci_dev->kdrv == RTE_KDRV_IGB_UIO ||
2350                     pci_dev->kdrv == RTE_KDRV_UIO_GENERIC) {
2351                         if (hns3vf_enable_msix(pci_dev, true))
2352                                 hns3_err(hw, "Failed to enable msix");
2353                 }
2354
2355                 rte_intr_enable(&pci_dev->intr_handle);
2356         }
2357
2358         ret = hns3_reset_all_queues(hns);
2359         if (ret) {
2360                 hns3_err(hw, "Failed to reset all queues: %d", ret);
2361                 return ret;
2362         }
2363
2364         ret = hns3vf_init_hardware(hns);
2365         if (ret) {
2366                 hns3_err(hw, "Failed to init hardware: %d", ret);
2367                 return ret;
2368         }
2369
2370         return 0;
2371 }
2372
2373 static const struct eth_dev_ops hns3vf_eth_dev_ops = {
2374         .dev_start          = hns3vf_dev_start,
2375         .dev_stop           = hns3vf_dev_stop,
2376         .dev_close          = hns3vf_dev_close,
2377         .mtu_set            = hns3vf_dev_mtu_set,
2378         .promiscuous_enable = hns3vf_dev_promiscuous_enable,
2379         .promiscuous_disable = hns3vf_dev_promiscuous_disable,
2380         .allmulticast_enable = hns3vf_dev_allmulticast_enable,
2381         .allmulticast_disable = hns3vf_dev_allmulticast_disable,
2382         .stats_get          = hns3_stats_get,
2383         .stats_reset        = hns3_stats_reset,
2384         .xstats_get         = hns3_dev_xstats_get,
2385         .xstats_get_names   = hns3_dev_xstats_get_names,
2386         .xstats_reset       = hns3_dev_xstats_reset,
2387         .xstats_get_by_id   = hns3_dev_xstats_get_by_id,
2388         .xstats_get_names_by_id = hns3_dev_xstats_get_names_by_id,
2389         .dev_infos_get      = hns3vf_dev_infos_get,
2390         .fw_version_get     = hns3vf_fw_version_get,
2391         .rx_queue_setup     = hns3_rx_queue_setup,
2392         .tx_queue_setup     = hns3_tx_queue_setup,
2393         .rx_queue_release   = hns3_dev_rx_queue_release,
2394         .tx_queue_release   = hns3_dev_tx_queue_release,
2395         .rx_queue_intr_enable   = hns3_dev_rx_queue_intr_enable,
2396         .rx_queue_intr_disable  = hns3_dev_rx_queue_intr_disable,
2397         .dev_configure      = hns3vf_dev_configure,
2398         .mac_addr_add       = hns3vf_add_mac_addr,
2399         .mac_addr_remove    = hns3vf_remove_mac_addr,
2400         .mac_addr_set       = hns3vf_set_default_mac_addr,
2401         .set_mc_addr_list   = hns3vf_set_mc_mac_addr_list,
2402         .link_update        = hns3vf_dev_link_update,
2403         .rss_hash_update    = hns3_dev_rss_hash_update,
2404         .rss_hash_conf_get  = hns3_dev_rss_hash_conf_get,
2405         .reta_update        = hns3_dev_rss_reta_update,
2406         .reta_query         = hns3_dev_rss_reta_query,
2407         .filter_ctrl        = hns3_dev_filter_ctrl,
2408         .vlan_filter_set    = hns3vf_vlan_filter_set,
2409         .vlan_offload_set   = hns3vf_vlan_offload_set,
2410         .get_reg            = hns3_get_regs,
2411         .dev_supported_ptypes_get = hns3_dev_supported_ptypes_get,
2412 };
2413
2414 static const struct hns3_reset_ops hns3vf_reset_ops = {
2415         .reset_service       = hns3vf_reset_service,
2416         .stop_service        = hns3vf_stop_service,
2417         .prepare_reset       = hns3vf_prepare_reset,
2418         .wait_hardware_ready = hns3vf_wait_hardware_ready,
2419         .reinit_dev          = hns3vf_reinit_dev,
2420         .restore_conf        = hns3vf_restore_conf,
2421         .start_service       = hns3vf_start_service,
2422 };
2423
2424 static int
2425 hns3vf_dev_init(struct rte_eth_dev *eth_dev)
2426 {
2427         struct rte_device *dev = eth_dev->device;
2428         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev);
2429         struct hns3_adapter *hns = eth_dev->data->dev_private;
2430         struct hns3_hw *hw = &hns->hw;
2431         uint8_t revision;
2432         int ret;
2433
2434         PMD_INIT_FUNC_TRACE();
2435
2436         /* Get PCI revision id */
2437         ret = rte_pci_read_config(pci_dev, &revision, HNS3_PCI_REVISION_ID_LEN,
2438                                   HNS3_PCI_REVISION_ID);
2439         if (ret != HNS3_PCI_REVISION_ID_LEN) {
2440                 PMD_INIT_LOG(ERR, "Failed to read pci revision id, ret = %d",
2441                              ret);
2442                 return -EIO;
2443         }
2444         hw->revision = revision;
2445
2446         eth_dev->process_private = (struct hns3_process_private *)
2447             rte_zmalloc_socket("hns3_filter_list",
2448                                sizeof(struct hns3_process_private),
2449                                RTE_CACHE_LINE_SIZE, eth_dev->device->numa_node);
2450         if (eth_dev->process_private == NULL) {
2451                 PMD_INIT_LOG(ERR, "Failed to alloc memory for process private");
2452                 return -ENOMEM;
2453         }
2454
2455         /* initialize flow filter lists */
2456         hns3_filterlist_init(eth_dev);
2457
2458         hns3_set_rxtx_function(eth_dev);
2459         eth_dev->dev_ops = &hns3vf_eth_dev_ops;
2460         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2461                 hns3_mp_init_secondary();
2462                 hw->secondary_cnt++;
2463                 return 0;
2464         }
2465
2466         hns3_mp_init_primary();
2467
2468         hw->adapter_state = HNS3_NIC_UNINITIALIZED;
2469         hns->is_vf = true;
2470         hw->data = eth_dev->data;
2471
2472         ret = hns3_reset_init(hw);
2473         if (ret)
2474                 goto err_init_reset;
2475         hw->reset.ops = &hns3vf_reset_ops;
2476
2477         ret = hns3vf_init_vf(eth_dev);
2478         if (ret) {
2479                 PMD_INIT_LOG(ERR, "Failed to init vf: %d", ret);
2480                 goto err_init_vf;
2481         }
2482
2483         /* Allocate memory for storing MAC addresses */
2484         eth_dev->data->mac_addrs = rte_zmalloc("hns3vf-mac",
2485                                                sizeof(struct rte_ether_addr) *
2486                                                HNS3_VF_UC_MACADDR_NUM, 0);
2487         if (eth_dev->data->mac_addrs == NULL) {
2488                 PMD_INIT_LOG(ERR, "Failed to allocate %zx bytes needed "
2489                              "to store MAC addresses",
2490                              sizeof(struct rte_ether_addr) *
2491                              HNS3_VF_UC_MACADDR_NUM);
2492                 ret = -ENOMEM;
2493                 goto err_rte_zmalloc;
2494         }
2495
2496         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.mac_addr,
2497                             &eth_dev->data->mac_addrs[0]);
2498         hw->adapter_state = HNS3_NIC_INITIALIZED;
2499         /*
2500          * Pass the information to the rte_eth_dev_close() that it should also
2501          * release the private port resources.
2502          */
2503         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2504
2505         if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_PENDING) {
2506                 hns3_err(hw, "Reschedule reset service after dev_init");
2507                 hns3_schedule_reset(hns);
2508         } else {
2509                 /* IMP will wait ready flag before reset */
2510                 hns3_notify_reset_ready(hw, false);
2511         }
2512         rte_eal_alarm_set(HNS3VF_KEEP_ALIVE_INTERVAL, hns3vf_keep_alive_handler,
2513                           eth_dev);
2514         return 0;
2515
2516 err_rte_zmalloc:
2517         hns3vf_uninit_vf(eth_dev);
2518
2519 err_init_vf:
2520         rte_free(hw->reset.wait_data);
2521
2522 err_init_reset:
2523         eth_dev->dev_ops = NULL;
2524         eth_dev->rx_pkt_burst = NULL;
2525         eth_dev->tx_pkt_burst = NULL;
2526         eth_dev->tx_pkt_prepare = NULL;
2527         rte_free(eth_dev->process_private);
2528         eth_dev->process_private = NULL;
2529
2530         return ret;
2531 }
2532
2533 static int
2534 hns3vf_dev_uninit(struct rte_eth_dev *eth_dev)
2535 {
2536         struct hns3_adapter *hns = eth_dev->data->dev_private;
2537         struct hns3_hw *hw = &hns->hw;
2538
2539         PMD_INIT_FUNC_TRACE();
2540
2541         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2542                 return -EPERM;
2543
2544         eth_dev->dev_ops = NULL;
2545         eth_dev->rx_pkt_burst = NULL;
2546         eth_dev->tx_pkt_burst = NULL;
2547         eth_dev->tx_pkt_prepare = NULL;
2548
2549         if (hw->adapter_state < HNS3_NIC_CLOSING)
2550                 hns3vf_dev_close(eth_dev);
2551
2552         hw->adapter_state = HNS3_NIC_REMOVED;
2553         return 0;
2554 }
2555
2556 static int
2557 eth_hns3vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2558                      struct rte_pci_device *pci_dev)
2559 {
2560         return rte_eth_dev_pci_generic_probe(pci_dev,
2561                                              sizeof(struct hns3_adapter),
2562                                              hns3vf_dev_init);
2563 }
2564
2565 static int
2566 eth_hns3vf_pci_remove(struct rte_pci_device *pci_dev)
2567 {
2568         return rte_eth_dev_pci_generic_remove(pci_dev, hns3vf_dev_uninit);
2569 }
2570
2571 static const struct rte_pci_id pci_id_hns3vf_map[] = {
2572         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_VF) },
2573         { RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HNS3_DEV_ID_100G_RDMA_PFC_VF) },
2574         { .vendor_id = 0, /* sentinel */ },
2575 };
2576
2577 static struct rte_pci_driver rte_hns3vf_pmd = {
2578         .id_table = pci_id_hns3vf_map,
2579         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
2580         .probe = eth_hns3vf_pci_probe,
2581         .remove = eth_hns3vf_pci_remove,
2582 };
2583
2584 RTE_PMD_REGISTER_PCI(net_hns3_vf, rte_hns3vf_pmd);
2585 RTE_PMD_REGISTER_PCI_TABLE(net_hns3_vf, pci_id_hns3vf_map);
2586 RTE_PMD_REGISTER_KMOD_DEP(net_hns3_vf, "* igb_uio | vfio-pci");