drivers/net/hns3/hns3_regs.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <errno.h>
   6 #include <stdarg.h>
   7 #include <stdbool.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <inttypes.h>
  12 #include <unistd.h>
  13 #include <rte_bus_pci.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_dev.h>
  17 #include <rte_eal.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_io.h>
  22 #include <rte_pci.h>
  23
  24 #include "hns3_ethdev.h"
  25 #include "hns3_logs.h"
  26 #include "hns3_rxtx.h"
  27 #include "hns3_regs.h"
  28
  29 #define MAX_SEPARATE_NUM        4
  30 #define SEPARATOR_VALUE         0xFFFFFFFF
  31 #define REG_NUM_PER_LINE        4
  32 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(uint32_t))
  33
  34 static const uint32_t cmdq_reg_addrs[] = {HNS3_CMDQ_TX_ADDR_L_REG,
  35                                           HNS3_CMDQ_TX_ADDR_H_REG,
  36                                           HNS3_CMDQ_TX_DEPTH_REG,
  37                                           HNS3_CMDQ_TX_TAIL_REG,
  38                                           HNS3_CMDQ_TX_HEAD_REG,
  39                                           HNS3_CMDQ_RX_ADDR_L_REG,
  40                                           HNS3_CMDQ_RX_ADDR_H_REG,
  41                                           HNS3_CMDQ_RX_DEPTH_REG,
  42                                           HNS3_CMDQ_RX_TAIL_REG,
  43                                           HNS3_CMDQ_RX_HEAD_REG,
  44                                           HNS3_VECTOR0_CMDQ_SRC_REG,
  45                                           HNS3_CMDQ_INTR_STS_REG,
  46                                           HNS3_CMDQ_INTR_EN_REG,
  47                                           HNS3_CMDQ_INTR_GEN_REG};
  48
  49 static const uint32_t common_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  50                                             HNS3_VECTOR0_OTER_EN_REG,
  51                                             HNS3_MISC_RESET_STS_REG,
  52                                             HNS3_VECTOR0_OTHER_INT_STS_REG,
  53                                             HNS3_GLOBAL_RESET_REG,
  54                                             HNS3_FUN_RST_ING,
  55                                             HNS3_GRO_EN_REG};
  56
  57 static const uint32_t common_vf_reg_addrs[] = {HNS3_MISC_VECTOR_REG_BASE,
  58                                                HNS3_FUN_RST_ING,
  59                                                HNS3_GRO_EN_REG};
  60
  61 static const uint32_t ring_reg_addrs[] = {HNS3_RING_RX_BASEADDR_L_REG,
  62                                           HNS3_RING_RX_BASEADDR_H_REG,
  63                                           HNS3_RING_RX_BD_NUM_REG,
  64                                           HNS3_RING_RX_BD_LEN_REG,
  65                                           HNS3_RING_RX_EN_REG,
  66                                           HNS3_RING_RX_MERGE_EN_REG,
  67                                           HNS3_RING_RX_TAIL_REG,
  68                                           HNS3_RING_RX_HEAD_REG,
  69                                           HNS3_RING_RX_FBDNUM_REG,
  70                                           HNS3_RING_RX_OFFSET_REG,
  71                                           HNS3_RING_RX_FBD_OFFSET_REG,
  72                                           HNS3_RING_RX_STASH_REG,
  73                                           HNS3_RING_RX_BD_ERR_REG,
  74                                           HNS3_RING_TX_BASEADDR_L_REG,
  75                                           HNS3_RING_TX_BASEADDR_H_REG,
  76                                           HNS3_RING_TX_BD_NUM_REG,
  77                                           HNS3_RING_TX_EN_REG,
  78                                           HNS3_RING_TX_PRIORITY_REG,
  79                                           HNS3_RING_TX_TC_REG,
  80                                           HNS3_RING_TX_MERGE_EN_REG,
  81                                           HNS3_RING_TX_TAIL_REG,
  82                                           HNS3_RING_TX_HEAD_REG,
  83                                           HNS3_RING_TX_FBDNUM_REG,
  84                                           HNS3_RING_TX_OFFSET_REG,
  85                                           HNS3_RING_TX_EBD_NUM_REG,
  86                                           HNS3_RING_TX_EBD_OFFSET_REG,
  87                                           HNS3_RING_TX_BD_ERR_REG,
  88                                           HNS3_RING_EN_REG};
  89
  90 static const uint32_t tqp_intr_reg_addrs[] = {HNS3_TQP_INTR_CTRL_REG,
  91                                               HNS3_TQP_INTR_GL0_REG,
  92                                               HNS3_TQP_INTR_GL1_REG,
  93                                               HNS3_TQP_INTR_GL2_REG,
  94                                               HNS3_TQP_INTR_RL_REG};
  95
  96 static int
  97 hns3_get_regs_num(struct hns3_hw *hw, uint32_t *regs_num_32_bit,
  98                   uint32_t *regs_num_64_bit)
  99 {
 100         struct hns3_cmd_desc desc;
 101         int ret;
 102
 103         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_REG_NUM, true);
 104         ret = hns3_cmd_send(hw, &desc, 1);
 105         if (ret) {
 106                 hns3_err(hw, "Query register number cmd failed, ret = %d",
 107                          ret);
 108                 return ret;
 109         }
 110
 111         *regs_num_32_bit = rte_le_to_cpu_32(desc.data[0]);
 112         *regs_num_64_bit = rte_le_to_cpu_32(desc.data[1]);
 113
 114         return 0;
 115 }
 116
 117 static int
 118 hns3_get_regs_length(struct hns3_hw *hw, uint32_t *length)
 119 {
 120         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 121         uint32_t cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
 122         uint32_t regs_num_32_bit, regs_num_64_bit;
 123         uint32_t len;
 124         int ret;
 125
 126         cmdq_lines = sizeof(cmdq_reg_addrs) / REG_LEN_PER_LINE + 1;
 127         if (hns->is_vf)
 128                 common_lines =
 129                         sizeof(common_vf_reg_addrs) / REG_LEN_PER_LINE + 1;
 130         else
 131                 common_lines = sizeof(common_reg_addrs) / REG_LEN_PER_LINE + 1;
 132         ring_lines = sizeof(ring_reg_addrs) / REG_LEN_PER_LINE + 1;
 133         tqp_intr_lines = sizeof(tqp_intr_reg_addrs) / REG_LEN_PER_LINE + 1;
 134
 135         len = (cmdq_lines + common_lines + ring_lines * hw->tqps_num +
 136               tqp_intr_lines * hw->num_msi) * REG_LEN_PER_LINE;
 137
 138         if (!hns->is_vf) {
 139                 ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 140                 if (ret) {
 141                         hns3_err(hw, "Get register number failed, ret = %d.",
 142                                  ret);
 143                         return -ENOTSUP;
 144                 }
 145                 len += regs_num_32_bit * sizeof(uint32_t) +
 146                        regs_num_64_bit * sizeof(uint64_t);
 147         }
 148
 149         *length = len;
 150         return 0;
 151 }
 152
 153 static int
 154 hns3_get_32_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 155 {
 156 #define HNS3_32_BIT_REG_RTN_DATANUM 8
 157 #define HNS3_32_BIT_DESC_NODATA_LEN 2
 158         struct hns3_cmd_desc *desc;
 159         uint32_t *reg_val = data;
 160         uint32_t *desc_data;
 161         int cmd_num;
 162         int i, k, n;
 163         int ret;
 164
 165         if (regs_num == 0)
 166                 return 0;
 167
 168         cmd_num = DIV_ROUND_UP(regs_num + HNS3_32_BIT_DESC_NODATA_LEN,
 169                                HNS3_32_BIT_REG_RTN_DATANUM);
 170         desc = rte_zmalloc("hns3-32bit-regs",
 171                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 172         if (desc == NULL) {
 173                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 174                          "store 32bit regs",
 175                          sizeof(struct hns3_cmd_desc) * cmd_num);
 176                 return -ENOMEM;
 177         }
 178
 179         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_32_BIT_REG, true);
 180         ret = hns3_cmd_send(hw, desc, cmd_num);
 181         if (ret) {
 182                 hns3_err(hw, "Query 32 bit register cmd failed, ret = %d",
 183                          ret);
 184                 rte_free(desc);
 185                 return ret;
 186         }
 187
 188         for (i = 0; i < cmd_num; i++) {
 189                 if (i == 0) {
 190                         desc_data = &desc[i].data[0];
 191                         n = HNS3_32_BIT_REG_RTN_DATANUM -
 192                             HNS3_32_BIT_DESC_NODATA_LEN;
 193                 } else {
 194                         desc_data = (uint32_t *)(&desc[i]);
 195                         n = HNS3_32_BIT_REG_RTN_DATANUM;
 196                 }
 197                 for (k = 0; k < n; k++) {
 198                         *reg_val++ = rte_le_to_cpu_32(*desc_data++);
 199
 200                         regs_num--;
 201                         if (regs_num == 0)
 202                                 break;
 203                 }
 204         }
 205
 206         rte_free(desc);
 207         return 0;
 208 }
 209
 210 static int
 211 hns3_get_64_bit_regs(struct hns3_hw *hw, uint32_t regs_num, void *data)
 212 {
 213 #define HNS3_64_BIT_REG_RTN_DATANUM 4
 214 #define HNS3_64_BIT_DESC_NODATA_LEN 1
 215         struct hns3_cmd_desc *desc;
 216         uint64_t *reg_val = data;
 217         uint64_t *desc_data;
 218         int cmd_num;
 219         int i, k, n;
 220         int ret;
 221
 222         if (regs_num == 0)
 223                 return 0;
 224
 225         cmd_num = DIV_ROUND_UP(regs_num + HNS3_64_BIT_DESC_NODATA_LEN,
 226                                HNS3_64_BIT_REG_RTN_DATANUM);
 227         desc = rte_zmalloc("hns3-64bit-regs",
 228                            sizeof(struct hns3_cmd_desc) * cmd_num, 0);
 229         if (desc == NULL) {
 230                 hns3_err(hw, "Failed to allocate %zx bytes needed to "
 231                          "store 64bit regs",
 232                          sizeof(struct hns3_cmd_desc) * cmd_num);
 233                 return -ENOMEM;
 234         }
 235
 236         hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_QUERY_64_BIT_REG, true);
 237         ret = hns3_cmd_send(hw, desc, cmd_num);
 238         if (ret) {
 239                 hns3_err(hw, "Query 64 bit register cmd failed, ret = %d",
 240                          ret);
 241                 rte_free(desc);
 242                 return ret;
 243         }
 244
 245         for (i = 0; i < cmd_num; i++) {
 246                 if (i == 0) {
 247                         desc_data = (uint64_t *)(&desc[i].data[0]);
 248                         n = HNS3_64_BIT_REG_RTN_DATANUM -
 249                             HNS3_64_BIT_DESC_NODATA_LEN;
 250                 } else {
 251                         desc_data = (uint64_t *)(&desc[i]);
 252                         n = HNS3_64_BIT_REG_RTN_DATANUM;
 253                 }
 254                 for (k = 0; k < n; k++) {
 255                         *reg_val++ = rte_le_to_cpu_64(*desc_data++);
 256
 257                         regs_num--;
 258                         if (!regs_num)
 259                                 break;
 260                 }
 261         }
 262
 263         rte_free(desc);
 264         return 0;
 265 }
 266
 267 static void
 268 hns3_direct_access_regs(struct hns3_hw *hw, uint32_t *data)
 269 {
 270         struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw);
 271         uint32_t reg_offset;
 272         int separator_num;
 273         int reg_um;
 274         int i, j;
 275
 276         /* fetching per-PF registers values from PF PCIe register space */
 277         reg_um = sizeof(cmdq_reg_addrs) / sizeof(uint32_t);
 278         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 279         for (i = 0; i < reg_um; i++)
 280                 *data++ = hns3_read_dev(hw, cmdq_reg_addrs[i]);
 281         for (i = 0; i < separator_num; i++)
 282                 *data++ = SEPARATOR_VALUE;
 283
 284         if (hns->is_vf)
 285                 reg_um = sizeof(common_vf_reg_addrs) / sizeof(uint32_t);
 286         else
 287                 reg_um = sizeof(common_reg_addrs) / sizeof(uint32_t);
 288         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 289         for (i = 0; i < reg_um; i++)
 290                 if (hns->is_vf)
 291                         *data++ = hns3_read_dev(hw, common_vf_reg_addrs[i]);
 292                 else
 293                         *data++ = hns3_read_dev(hw, common_reg_addrs[i]);
 294         for (i = 0; i < separator_num; i++)
 295                 *data++ = SEPARATOR_VALUE;
 296
 297         reg_um = sizeof(ring_reg_addrs) / sizeof(uint32_t);
 298         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 299         for (j = 0; j < hw->tqps_num; j++) {
 300                 reg_offset = hns3_get_tqp_reg_offset(j);
 301                 for (i = 0; i < reg_um; i++)
 302                         *data++ = hns3_read_dev(hw,
 303                                                 ring_reg_addrs[i] + reg_offset);
 304                 for (i = 0; i < separator_num; i++)
 305                         *data++ = SEPARATOR_VALUE;
 306         }
 307
 308         reg_um = sizeof(tqp_intr_reg_addrs) / sizeof(uint32_t);
 309         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
 310         for (j = 0; j < hw->num_msi; j++) {
 311                 reg_offset = HNS3_TQP_INTR_REG_SIZE * j;
 312                 for (i = 0; i < reg_um; i++)
 313                         *data++ = hns3_read_dev(hw,
 314                                                 tqp_intr_reg_addrs[i] +
 315                                                 reg_offset);
 316                 for (i = 0; i < separator_num; i++)
 317                         *data++ = SEPARATOR_VALUE;
 318         }
 319 }
 320
 321 int
 322 hns3_get_regs(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 323 {
 324         struct hns3_adapter *hns = eth_dev->data->dev_private;
 325         struct hns3_hw *hw = &hns->hw;
 326         uint32_t regs_num_32_bit;
 327         uint32_t regs_num_64_bit;
 328         uint32_t length;
 329         uint32_t *data;
 330         int ret;
 331
 332         if (regs == NULL) {
 333                 hns3_err(hw, "the input parameter regs is NULL!");
 334                 return -EINVAL;
 335         }
 336
 337         ret = hns3_get_regs_length(hw, &length);
 338         if (ret)
 339                 return ret;
 340
 341         data = regs->data;
 342         if (data == NULL) {
 343                 regs->length = length;
 344                 regs->width = sizeof(uint32_t);
 345                 return 0;
 346         }
 347
 348         /* Only full register dump is supported */
 349         if (regs->length && regs->length != length)
 350                 return -ENOTSUP;
 351
 352         /* fetching per-PF registers values from PF PCIe register space */
 353         hns3_direct_access_regs(hw, data);
 354
 355         if (hns->is_vf)
 356                 return 0;
 357
 358         ret = hns3_get_regs_num(hw, &regs_num_32_bit, &regs_num_64_bit);
 359         if (ret) {
 360                 hns3_err(hw, "Get register number failed, ret = %d", ret);
 361                 return ret;
 362         }
 363
 364         /* fetching PF common registers values from firmware */
 365         ret = hns3_get_32_bit_regs(hw, regs_num_32_bit, data);
 366         if (ret) {
 367                 hns3_err(hw, "Get 32 bit register failed, ret = %d", ret);
 368                 return ret;
 369         }
 370
 371         data += regs_num_32_bit;
 372         ret = hns3_get_64_bit_regs(hw, regs_num_64_bit, data);
 373         if (ret)
 374                 hns3_err(hw, "Get 64 bit register failed, ret = %d", ret);
 375
 376         return ret;
 377 }