drivers/net/hns3/hns3_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018-2019 Hisilicon Limited.
   3  */
   4
   5 #include <stdarg.h>
   6 #include <stdbool.h>
   7 #include <stdint.h>
   8 #include <stdio.h>
   9 #include <unistd.h>
  10 #include <inttypes.h>
  11 #include <rte_bus_pci.h>
  12 #include <rte_byteorder.h>
  13 #include <rte_common.h>
  14 #include <rte_cycles.h>
  15 #include <rte_dev.h>
  16 #include <rte_eal.h>
  17 #include <rte_ether.h>
  18 #include <rte_vxlan.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_io.h>
  21 #include <rte_ip.h>
  22 #include <rte_gre.h>
  23 #include <rte_net.h>
  24 #include <rte_malloc.h>
  25 #include <rte_pci.h>
  26
  27 #include "hns3_ethdev.h"
  28 #include "hns3_rxtx.h"
  29 #include "hns3_regs.h"
  30 #include "hns3_logs.h"
  31
  32 #define HNS3_CFG_DESC_NUM(num)  ((num) / 8 - 1)
  33 #define DEFAULT_RX_FREE_THRESH  16
  34
  35 static void
  36 hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
  37 {
  38         uint16_t i;
  39
  40         /* Note: Fake rx queue will not enter here */
  41         if (rxq->sw_ring) {
  42                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  43                         if (rxq->sw_ring[i].mbuf) {
  44                                 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
  45                                 rxq->sw_ring[i].mbuf = NULL;
  46                         }
  47                 }
  48         }
  49 }
  50
  51 static void
  52 hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
  53 {
  54         uint16_t i;
  55
  56         /* Note: Fake rx queue will not enter here */
  57         if (txq->sw_ring) {
  58                 for (i = 0; i < txq->nb_tx_desc; i++) {
  59                         if (txq->sw_ring[i].mbuf) {
  60                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
  61                                 txq->sw_ring[i].mbuf = NULL;
  62                         }
  63                 }
  64         }
  65 }
  66
  67 static void
  68 hns3_rx_queue_release(void *queue)
  69 {
  70         struct hns3_rx_queue *rxq = queue;
  71         if (rxq) {
  72                 hns3_rx_queue_release_mbufs(rxq);
  73                 if (rxq->mz)
  74                         rte_memzone_free(rxq->mz);
  75                 if (rxq->sw_ring)
  76                         rte_free(rxq->sw_ring);
  77                 rte_free(rxq);
  78         }
  79 }
  80
  81 static void
  82 hns3_tx_queue_release(void *queue)
  83 {
  84         struct hns3_tx_queue *txq = queue;
  85         if (txq) {
  86                 hns3_tx_queue_release_mbufs(txq);
  87                 if (txq->mz)
  88                         rte_memzone_free(txq->mz);
  89                 if (txq->sw_ring)
  90                         rte_free(txq->sw_ring);
  91                 rte_free(txq);
  92         }
  93 }
  94
  95 void
  96 hns3_dev_rx_queue_release(void *queue)
  97 {
  98         struct hns3_rx_queue *rxq = queue;
  99         struct hns3_adapter *hns;
 100
 101         if (rxq == NULL)
 102                 return;
 103
 104         hns = rxq->hns;
 105         rte_spinlock_lock(&hns->hw.lock);
 106         hns3_rx_queue_release(queue);
 107         rte_spinlock_unlock(&hns->hw.lock);
 108 }
 109
 110 void
 111 hns3_dev_tx_queue_release(void *queue)
 112 {
 113         struct hns3_tx_queue *txq = queue;
 114         struct hns3_adapter *hns;
 115
 116         if (txq == NULL)
 117                 return;
 118
 119         hns = txq->hns;
 120         rte_spinlock_lock(&hns->hw.lock);
 121         hns3_tx_queue_release(queue);
 122         rte_spinlock_unlock(&hns->hw.lock);
 123 }
 124
 125 static void
 126 hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
 127 {
 128         struct hns3_rx_queue *rxq = queue;
 129         struct hns3_adapter *hns;
 130         struct hns3_hw *hw;
 131         uint16_t idx;
 132
 133         if (rxq == NULL)
 134                 return;
 135
 136         hns = rxq->hns;
 137         hw = &hns->hw;
 138         idx = rxq->queue_id;
 139         if (hw->fkq_data.rx_queues[idx]) {
 140                 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
 141                 hw->fkq_data.rx_queues[idx] = NULL;
 142         }
 143
 144         /* free fake rx queue arrays */
 145         if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
 146                 hw->fkq_data.nb_fake_rx_queues = 0;
 147                 rte_free(hw->fkq_data.rx_queues);
 148                 hw->fkq_data.rx_queues = NULL;
 149         }
 150 }
 151
 152 static void
 153 hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
 154 {
 155         struct hns3_tx_queue *txq = queue;
 156         struct hns3_adapter *hns;
 157         struct hns3_hw *hw;
 158         uint16_t idx;
 159
 160         if (txq == NULL)
 161                 return;
 162
 163         hns = txq->hns;
 164         hw = &hns->hw;
 165         idx = txq->queue_id;
 166         if (hw->fkq_data.tx_queues[idx]) {
 167                 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
 168                 hw->fkq_data.tx_queues[idx] = NULL;
 169         }
 170
 171         /* free fake tx queue arrays */
 172         if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
 173                 hw->fkq_data.nb_fake_tx_queues = 0;
 174                 rte_free(hw->fkq_data.tx_queues);
 175                 hw->fkq_data.tx_queues = NULL;
 176         }
 177 }
 178
 179 static void
 180 hns3_free_rx_queues(struct rte_eth_dev *dev)
 181 {
 182         struct hns3_adapter *hns = dev->data->dev_private;
 183         struct hns3_fake_queue_data *fkq_data;
 184         struct hns3_hw *hw = &hns->hw;
 185         uint16_t nb_rx_q;
 186         uint16_t i;
 187
 188         nb_rx_q = hw->data->nb_rx_queues;
 189         for (i = 0; i < nb_rx_q; i++) {
 190                 if (dev->data->rx_queues[i]) {
 191                         hns3_rx_queue_release(dev->data->rx_queues[i]);
 192                         dev->data->rx_queues[i] = NULL;
 193                 }
 194         }
 195
 196         /* Free fake Rx queues */
 197         fkq_data = &hw->fkq_data;
 198         for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
 199                 if (fkq_data->rx_queues[i])
 200                         hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
 201         }
 202 }
 203
 204 static void
 205 hns3_free_tx_queues(struct rte_eth_dev *dev)
 206 {
 207         struct hns3_adapter *hns = dev->data->dev_private;
 208         struct hns3_fake_queue_data *fkq_data;
 209         struct hns3_hw *hw = &hns->hw;
 210         uint16_t nb_tx_q;
 211         uint16_t i;
 212
 213         nb_tx_q = hw->data->nb_tx_queues;
 214         for (i = 0; i < nb_tx_q; i++) {
 215                 if (dev->data->tx_queues[i]) {
 216                         hns3_tx_queue_release(dev->data->tx_queues[i]);
 217                         dev->data->tx_queues[i] = NULL;
 218                 }
 219         }
 220
 221         /* Free fake Tx queues */
 222         fkq_data = &hw->fkq_data;
 223         for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
 224                 if (fkq_data->tx_queues[i])
 225                         hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
 226         }
 227 }
 228
 229 void
 230 hns3_free_all_queues(struct rte_eth_dev *dev)
 231 {
 232         hns3_free_rx_queues(dev);
 233         hns3_free_tx_queues(dev);
 234 }
 235
 236 static int
 237 hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
 238 {
 239         struct rte_mbuf *mbuf;
 240         uint64_t dma_addr;
 241         uint16_t i;
 242
 243         for (i = 0; i < rxq->nb_rx_desc; i++) {
 244                 mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
 245                 if (unlikely(mbuf == NULL)) {
 246                         hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
 247                                  i);
 248                         hns3_rx_queue_release_mbufs(rxq);
 249                         return -ENOMEM;
 250                 }
 251
 252                 rte_mbuf_refcnt_set(mbuf, 1);
 253                 mbuf->next = NULL;
 254                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 255                 mbuf->nb_segs = 1;
 256                 mbuf->port = rxq->port_id;
 257
 258                 rxq->sw_ring[i].mbuf = mbuf;
 259                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 260                 rxq->rx_ring[i].addr = dma_addr;
 261                 rxq->rx_ring[i].rx.bd_base_info = 0;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static int
 268 hns3_buf_size2type(uint32_t buf_size)
 269 {
 270         int bd_size_type;
 271
 272         switch (buf_size) {
 273         case 512:
 274                 bd_size_type = HNS3_BD_SIZE_512_TYPE;
 275                 break;
 276         case 1024:
 277                 bd_size_type = HNS3_BD_SIZE_1024_TYPE;
 278                 break;
 279         case 4096:
 280                 bd_size_type = HNS3_BD_SIZE_4096_TYPE;
 281                 break;
 282         default:
 283                 bd_size_type = HNS3_BD_SIZE_2048_TYPE;
 284         }
 285
 286         return bd_size_type;
 287 }
 288
 289 static void
 290 hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
 291 {
 292         uint32_t rx_buf_len = rxq->rx_buf_len;
 293         uint64_t dma_addr = rxq->rx_ring_phys_addr;
 294
 295         hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
 296         hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
 297                        (uint32_t)((dma_addr >> 31) >> 1));
 298
 299         hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
 300                        hns3_buf_size2type(rx_buf_len));
 301         hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
 302                        HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
 303 }
 304
 305 static void
 306 hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
 307 {
 308         uint64_t dma_addr = txq->tx_ring_phys_addr;
 309
 310         hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
 311         hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
 312                        (uint32_t)((dma_addr >> 31) >> 1));
 313
 314         hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
 315                        HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
 316 }
 317
 318 static void
 319 hns3_enable_all_queues(struct hns3_hw *hw, bool en)
 320 {
 321         uint16_t nb_rx_q = hw->data->nb_rx_queues;
 322         uint16_t nb_tx_q = hw->data->nb_tx_queues;
 323         struct hns3_rx_queue *rxq;
 324         struct hns3_tx_queue *txq;
 325         uint32_t rcb_reg;
 326         int i;
 327
 328         for (i = 0; i < hw->cfg_max_queues; i++) {
 329                 if (i < nb_rx_q)
 330                         rxq = hw->data->rx_queues[i];
 331                 else
 332                         rxq = hw->fkq_data.rx_queues[i - nb_rx_q];
 333                 if (i < nb_tx_q)
 334                         txq = hw->data->tx_queues[i];
 335                 else
 336                         txq = hw->fkq_data.tx_queues[i - nb_tx_q];
 337                 if (rxq == NULL || txq == NULL ||
 338                     (en && (rxq->rx_deferred_start || txq->tx_deferred_start)))
 339                         continue;
 340
 341                 rcb_reg = hns3_read_dev(rxq, HNS3_RING_EN_REG);
 342                 if (en)
 343                         rcb_reg |= BIT(HNS3_RING_EN_B);
 344                 else
 345                         rcb_reg &= ~BIT(HNS3_RING_EN_B);
 346                 hns3_write_dev(rxq, HNS3_RING_EN_REG, rcb_reg);
 347         }
 348 }
 349
 350 static int
 351 hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
 352 {
 353         struct hns3_cfg_com_tqp_queue_cmd *req;
 354         struct hns3_cmd_desc desc;
 355         int ret;
 356
 357         req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
 358
 359         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
 360         req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
 361         req->stream_id = 0;
 362         hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
 363
 364         ret = hns3_cmd_send(hw, &desc, 1);
 365         if (ret)
 366                 hns3_err(hw, "TQP enable fail, ret = %d", ret);
 367
 368         return ret;
 369 }
 370
 371 static int
 372 hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
 373 {
 374         struct hns3_reset_tqp_queue_cmd *req;
 375         struct hns3_cmd_desc desc;
 376         int ret;
 377
 378         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
 379
 380         req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
 381         req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
 382         hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
 383
 384         ret = hns3_cmd_send(hw, &desc, 1);
 385         if (ret)
 386                 hns3_err(hw, "Send tqp reset cmd error, ret = %d", ret);
 387
 388         return ret;
 389 }
 390
 391 static int
 392 hns3_get_reset_status(struct hns3_hw *hw, uint16_t queue_id)
 393 {
 394         struct hns3_reset_tqp_queue_cmd *req;
 395         struct hns3_cmd_desc desc;
 396         int ret;
 397
 398         hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
 399
 400         req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
 401         req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
 402
 403         ret = hns3_cmd_send(hw, &desc, 1);
 404         if (ret) {
 405                 hns3_err(hw, "Get reset status error, ret =%d", ret);
 406                 return ret;
 407         }
 408
 409         return hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
 410 }
 411
 412 static int
 413 hns3_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
 414 {
 415 #define HNS3_TQP_RESET_TRY_MS   200
 416         uint64_t end;
 417         int reset_status;
 418         int ret;
 419
 420         ret = hns3_tqp_enable(hw, queue_id, false);
 421         if (ret)
 422                 return ret;
 423
 424         /*
 425          * In current version VF is not supported when PF is driven by DPDK
 426          * driver, all task queue pairs are mapped to PF function, so PF's queue
 427          * id is equals to the global queue id in PF range.
 428          */
 429         ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
 430         if (ret) {
 431                 hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
 432                 return ret;
 433         }
 434         ret = -ETIMEDOUT;
 435         end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
 436         do {
 437                 /* Wait for tqp hw reset */
 438                 rte_delay_ms(HNS3_POLL_RESPONE_MS);
 439                 reset_status = hns3_get_reset_status(hw, queue_id);
 440                 if (reset_status) {
 441                         ret = 0;
 442                         break;
 443                 }
 444         } while (get_timeofday_ms() < end);
 445
 446         if (ret) {
 447                 hns3_err(hw, "Reset TQP fail, ret = %d", ret);
 448                 return ret;
 449         }
 450
 451         ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
 452         if (ret)
 453                 hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
 454
 455         return ret;
 456 }
 457
 458 static int
 459 hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
 460 {
 461         uint8_t msg_data[2];
 462         int ret;
 463
 464         /* Disable VF's queue before send queue reset msg to PF */
 465         ret = hns3_tqp_enable(hw, queue_id, false);
 466         if (ret)
 467                 return ret;
 468
 469         memcpy(msg_data, &queue_id, sizeof(uint16_t));
 470
 471         return hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
 472                                  sizeof(msg_data), true, NULL, 0);
 473 }
 474
 475 static int
 476 hns3_reset_queue(struct hns3_adapter *hns, uint16_t queue_id)
 477 {
 478         struct hns3_hw *hw = &hns->hw;
 479         if (hns->is_vf)
 480                 return hns3vf_reset_tqp(hw, queue_id);
 481         else
 482                 return hns3_reset_tqp(hw, queue_id);
 483 }
 484
 485 int
 486 hns3_reset_all_queues(struct hns3_adapter *hns)
 487 {
 488         struct hns3_hw *hw = &hns->hw;
 489         int ret, i;
 490
 491         for (i = 0; i < hw->cfg_max_queues; i++) {
 492                 ret = hns3_reset_queue(hns, i);
 493                 if (ret) {
 494                         hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
 495                         return ret;
 496                 }
 497         }
 498         return 0;
 499 }
 500
 501 void
 502 hns3_tqp_intr_enable(struct hns3_hw *hw, uint16_t tpq_int_num, bool en)
 503 {
 504         uint32_t addr, value;
 505
 506         addr = HNS3_TQP_INTR_CTRL_REG + tpq_int_num * HNS3_VECTOR_REG_OFFSET;
 507         value = en ? 1 : 0;
 508
 509         hns3_write_dev(hw, addr, value);
 510 }
 511
 512 int
 513 hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
 514 {
 515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 516         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 517         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 518
 519         if (dev->data->dev_conf.intr_conf.rxq == 0)
 520                 return -ENOTSUP;
 521
 522         /* enable the vectors */
 523         hns3_tqp_intr_enable(hw, queue_id, true);
 524
 525         return rte_intr_ack(intr_handle);
 526 }
 527
 528 int
 529 hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 530 {
 531         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532
 533         if (dev->data->dev_conf.intr_conf.rxq == 0)
 534                 return -ENOTSUP;
 535
 536         /* disable the vectors */
 537         hns3_tqp_intr_enable(hw, queue_id, false);
 538
 539         return 0;
 540 }
 541
 542 static int
 543 hns3_dev_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
 544 {
 545         struct hns3_hw *hw = &hns->hw;
 546         struct hns3_rx_queue *rxq;
 547         int ret;
 548
 549         PMD_INIT_FUNC_TRACE();
 550
 551         rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
 552         ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
 553         if (ret) {
 554                 hns3_err(hw, "Failed to alloc mbuf for No.%d rx queue: %d",
 555                          idx, ret);
 556                 return ret;
 557         }
 558
 559         rxq->next_to_use = 0;
 560         rxq->next_to_clean = 0;
 561         hns3_init_rx_queue_hw(rxq);
 562
 563         return 0;
 564 }
 565
 566 static void
 567 hns3_fake_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
 568 {
 569         struct hns3_hw *hw = &hns->hw;
 570         struct hns3_rx_queue *rxq;
 571
 572         rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
 573         rxq->next_to_use = 0;
 574         rxq->next_to_clean = 0;
 575         hns3_init_rx_queue_hw(rxq);
 576 }
 577
 578 static void
 579 hns3_init_tx_queue(struct hns3_tx_queue *queue)
 580 {
 581         struct hns3_tx_queue *txq = queue;
 582         struct hns3_desc *desc;
 583         int i;
 584
 585         /* Clear tx bd */
 586         desc = txq->tx_ring;
 587         for (i = 0; i < txq->nb_tx_desc; i++) {
 588                 desc->tx.tp_fe_sc_vld_ra_ri = 0;
 589                 desc++;
 590         }
 591
 592         txq->next_to_use = 0;
 593         txq->next_to_clean = 0;
 594         txq->tx_bd_ready = txq->nb_tx_desc - 1;
 595         hns3_init_tx_queue_hw(txq);
 596 }
 597
 598 static void
 599 hns3_dev_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
 600 {
 601         struct hns3_hw *hw = &hns->hw;
 602         struct hns3_tx_queue *txq;
 603
 604         txq = (struct hns3_tx_queue *)hw->data->tx_queues[idx];
 605         hns3_init_tx_queue(txq);
 606 }
 607
 608 static void
 609 hns3_fake_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
 610 {
 611         struct hns3_hw *hw = &hns->hw;
 612         struct hns3_tx_queue *txq;
 613
 614         txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[idx];
 615         hns3_init_tx_queue(txq);
 616 }
 617
 618 static void
 619 hns3_init_tx_ring_tc(struct hns3_adapter *hns)
 620 {
 621         struct hns3_hw *hw = &hns->hw;
 622         struct hns3_tx_queue *txq;
 623         int i, num;
 624
 625         for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
 626                 struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
 627                 int j;
 628
 629                 if (!tc_queue->enable)
 630                         continue;
 631
 632                 for (j = 0; j < tc_queue->tqp_count; j++) {
 633                         num = tc_queue->tqp_offset + j;
 634                         txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
 635                         if (txq == NULL)
 636                                 continue;
 637
 638                         hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
 639                 }
 640         }
 641 }
 642
 643 static int
 644 hns3_start_rx_queues(struct hns3_adapter *hns)
 645 {
 646         struct hns3_hw *hw = &hns->hw;
 647         struct hns3_rx_queue *rxq;
 648         int i, j;
 649         int ret;
 650
 651         /* Initialize RSS for queues */
 652         ret = hns3_config_rss(hns);
 653         if (ret) {
 654                 hns3_err(hw, "Failed to configure rss %d", ret);
 655                 return ret;
 656         }
 657
 658         for (i = 0; i < hw->data->nb_rx_queues; i++) {
 659                 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
 660                 if (rxq == NULL || rxq->rx_deferred_start)
 661                         continue;
 662                 ret = hns3_dev_rx_queue_start(hns, i);
 663                 if (ret) {
 664                         hns3_err(hw, "Failed to start No.%d rx queue: %d", i,
 665                                  ret);
 666                         goto out;
 667                 }
 668         }
 669
 670         for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) {
 671                 rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[i];
 672                 if (rxq == NULL || rxq->rx_deferred_start)
 673                         continue;
 674                 hns3_fake_rx_queue_start(hns, i);
 675         }
 676         return 0;
 677
 678 out:
 679         for (j = 0; j < i; j++) {
 680                 rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
 681                 hns3_rx_queue_release_mbufs(rxq);
 682         }
 683
 684         return ret;
 685 }
 686
 687 static void
 688 hns3_start_tx_queues(struct hns3_adapter *hns)
 689 {
 690         struct hns3_hw *hw = &hns->hw;
 691         struct hns3_tx_queue *txq;
 692         int i;
 693
 694         for (i = 0; i < hw->data->nb_tx_queues; i++) {
 695                 txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
 696                 if (txq == NULL || txq->tx_deferred_start)
 697                         continue;
 698                 hns3_dev_tx_queue_start(hns, i);
 699         }
 700
 701         for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
 702                 txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
 703                 if (txq == NULL || txq->tx_deferred_start)
 704                         continue;
 705                 hns3_fake_tx_queue_start(hns, i);
 706         }
 707
 708         hns3_init_tx_ring_tc(hns);
 709 }
 710
 711 int
 712 hns3_start_queues(struct hns3_adapter *hns, bool reset_queue)
 713 {
 714         struct hns3_hw *hw = &hns->hw;
 715         int ret;
 716
 717         if (reset_queue) {
 718                 ret = hns3_reset_all_queues(hns);
 719                 if (ret) {
 720                         hns3_err(hw, "Failed to reset all queues %d", ret);
 721                         return ret;
 722                 }
 723         }
 724
 725         ret = hns3_start_rx_queues(hns);
 726         if (ret) {
 727                 hns3_err(hw, "Failed to start rx queues: %d", ret);
 728                 return ret;
 729         }
 730
 731         hns3_start_tx_queues(hns);
 732         hns3_enable_all_queues(hw, true);
 733
 734         return 0;
 735 }
 736
 737 int
 738 hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue)
 739 {
 740         struct hns3_hw *hw = &hns->hw;
 741         int ret;
 742
 743         hns3_enable_all_queues(hw, false);
 744         if (reset_queue) {
 745                 ret = hns3_reset_all_queues(hns);
 746                 if (ret) {
 747                         hns3_err(hw, "Failed to reset all queues %d", ret);
 748                         return ret;
 749                 }
 750         }
 751         return 0;
 752 }
 753
 754 static void*
 755 hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
 756                             struct hns3_queue_info *q_info)
 757 {
 758         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 759         const struct rte_memzone *rx_mz;
 760         struct hns3_rx_queue *rxq;
 761         unsigned int rx_desc;
 762
 763         rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
 764                                  RTE_CACHE_LINE_SIZE, q_info->socket_id);
 765         if (rxq == NULL) {
 766                 hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
 767                          q_info->idx);
 768                 return NULL;
 769         }
 770
 771         /* Allocate rx ring hardware descriptors. */
 772         rxq->queue_id = q_info->idx;
 773         rxq->nb_rx_desc = q_info->nb_desc;
 774         rx_desc = rxq->nb_rx_desc * sizeof(struct hns3_desc);
 775         rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
 776                                          rx_desc, HNS3_RING_BASE_ALIGN,
 777                                          q_info->socket_id);
 778         if (rx_mz == NULL) {
 779                 hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
 780                          q_info->idx);
 781                 hns3_rx_queue_release(rxq);
 782                 return NULL;
 783         }
 784         rxq->mz = rx_mz;
 785         rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
 786         rxq->rx_ring_phys_addr = rx_mz->iova;
 787
 788         hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
 789                  rxq->rx_ring_phys_addr);
 790
 791         return rxq;
 792 }
 793
 794 static int
 795 hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 796                          uint16_t nb_desc, unsigned int socket_id)
 797 {
 798         struct hns3_adapter *hns = dev->data->dev_private;
 799         struct hns3_hw *hw = &hns->hw;
 800         struct hns3_queue_info q_info;
 801         struct hns3_rx_queue *rxq;
 802         uint16_t nb_rx_q;
 803
 804         if (hw->fkq_data.rx_queues[idx]) {
 805                 hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
 806                 hw->fkq_data.rx_queues[idx] = NULL;
 807         }
 808
 809         q_info.idx = idx;
 810         q_info.socket_id = socket_id;
 811         q_info.nb_desc = nb_desc;
 812         q_info.type = "hns3 fake RX queue";
 813         q_info.ring_name = "rx_fake_ring";
 814         rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
 815         if (rxq == NULL) {
 816                 hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
 817                 return -ENOMEM;
 818         }
 819
 820         /* Don't need alloc sw_ring, because upper applications don't use it */
 821         rxq->sw_ring = NULL;
 822
 823         rxq->hns = hns;
 824         rxq->rx_deferred_start = false;
 825         rxq->port_id = dev->data->port_id;
 826         rxq->configured = true;
 827         nb_rx_q = dev->data->nb_rx_queues;
 828         rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
 829                                 (nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
 830         rxq->rx_buf_len = hw->rx_buf_len;
 831
 832         rte_spinlock_lock(&hw->lock);
 833         hw->fkq_data.rx_queues[idx] = rxq;
 834         rte_spinlock_unlock(&hw->lock);
 835
 836         return 0;
 837 }
 838
 839 static void*
 840 hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
 841                             struct hns3_queue_info *q_info)
 842 {
 843         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 844         const struct rte_memzone *tx_mz;
 845         struct hns3_tx_queue *txq;
 846         struct hns3_desc *desc;
 847         unsigned int tx_desc;
 848         int i;
 849
 850         txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
 851                                  RTE_CACHE_LINE_SIZE, q_info->socket_id);
 852         if (txq == NULL) {
 853                 hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
 854                          q_info->idx);
 855                 return NULL;
 856         }
 857
 858         /* Allocate tx ring hardware descriptors. */
 859         txq->queue_id = q_info->idx;
 860         txq->nb_tx_desc = q_info->nb_desc;
 861         tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
 862         tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
 863                                          tx_desc, HNS3_RING_BASE_ALIGN,
 864                                          q_info->socket_id);
 865         if (tx_mz == NULL) {
 866                 hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
 867                          q_info->idx);
 868                 hns3_tx_queue_release(txq);
 869                 return NULL;
 870         }
 871         txq->mz = tx_mz;
 872         txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
 873         txq->tx_ring_phys_addr = tx_mz->iova;
 874
 875         hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
 876                  txq->tx_ring_phys_addr);
 877
 878         /* Clear tx bd */
 879         desc = txq->tx_ring;
 880         for (i = 0; i < txq->nb_tx_desc; i++) {
 881                 desc->tx.tp_fe_sc_vld_ra_ri = 0;
 882                 desc++;
 883         }
 884
 885         return txq;
 886 }
 887
 888 static int
 889 hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 890                          uint16_t nb_desc, unsigned int socket_id)
 891 {
 892         struct hns3_adapter *hns = dev->data->dev_private;
 893         struct hns3_hw *hw = &hns->hw;
 894         struct hns3_queue_info q_info;
 895         struct hns3_tx_queue *txq;
 896         uint16_t nb_tx_q;
 897
 898         if (hw->fkq_data.tx_queues[idx] != NULL) {
 899                 hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
 900                 hw->fkq_data.tx_queues[idx] = NULL;
 901         }
 902
 903         q_info.idx = idx;
 904         q_info.socket_id = socket_id;
 905         q_info.nb_desc = nb_desc;
 906         q_info.type = "hns3 fake TX queue";
 907         q_info.ring_name = "tx_fake_ring";
 908         txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
 909         if (txq == NULL) {
 910                 hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
 911                 return -ENOMEM;
 912         }
 913
 914         /* Don't need alloc sw_ring, because upper applications don't use it */
 915         txq->sw_ring = NULL;
 916
 917         txq->hns = hns;
 918         txq->tx_deferred_start = false;
 919         txq->port_id = dev->data->port_id;
 920         txq->configured = true;
 921         nb_tx_q = dev->data->nb_tx_queues;
 922         txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
 923                                 (nb_tx_q + idx) * HNS3_TQP_REG_SIZE);
 924
 925         rte_spinlock_lock(&hw->lock);
 926         hw->fkq_data.tx_queues[idx] = txq;
 927         rte_spinlock_unlock(&hw->lock);
 928
 929         return 0;
 930 }
 931
 932 static int
 933 hns3_fake_rx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
 934 {
 935         uint16_t old_nb_queues = hw->fkq_data.nb_fake_rx_queues;
 936         void **rxq;
 937         uint8_t i;
 938
 939         if (hw->fkq_data.rx_queues == NULL && nb_queues != 0) {
 940                 /* first time configuration */
 941
 942                 uint32_t size;
 943                 size = sizeof(hw->fkq_data.rx_queues[0]) * nb_queues;
 944                 hw->fkq_data.rx_queues = rte_zmalloc("fake_rx_queues", size,
 945                                                      RTE_CACHE_LINE_SIZE);
 946                 if (hw->fkq_data.rx_queues == NULL) {
 947                         hw->fkq_data.nb_fake_rx_queues = 0;
 948                         return -ENOMEM;
 949                 }
 950         } else if (hw->fkq_data.rx_queues != NULL && nb_queues != 0) {
 951                 /* re-configure */
 952
 953                 rxq = hw->fkq_data.rx_queues;
 954                 for (i = nb_queues; i < old_nb_queues; i++)
 955                         hns3_dev_rx_queue_release(rxq[i]);
 956
 957                 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
 958                                   RTE_CACHE_LINE_SIZE);
 959                 if (rxq == NULL)
 960                         return -ENOMEM;
 961                 if (nb_queues > old_nb_queues) {
 962                         uint16_t new_qs = nb_queues - old_nb_queues;
 963                         memset(rxq + old_nb_queues, 0, sizeof(rxq[0]) * new_qs);
 964                 }
 965
 966                 hw->fkq_data.rx_queues = rxq;
 967         } else if (hw->fkq_data.rx_queues != NULL && nb_queues == 0) {
 968                 rxq = hw->fkq_data.rx_queues;
 969                 for (i = nb_queues; i < old_nb_queues; i++)
 970                         hns3_dev_rx_queue_release(rxq[i]);
 971
 972                 rte_free(hw->fkq_data.rx_queues);
 973                 hw->fkq_data.rx_queues = NULL;
 974         }
 975
 976         hw->fkq_data.nb_fake_rx_queues = nb_queues;
 977
 978         return 0;
 979 }
 980
 981 static int
 982 hns3_fake_tx_queue_config(struct hns3_hw *hw, uint16_t nb_queues)
 983 {
 984         uint16_t old_nb_queues = hw->fkq_data.nb_fake_tx_queues;
 985         void **txq;
 986         uint8_t i;
 987
 988         if (hw->fkq_data.tx_queues == NULL && nb_queues != 0) {
 989                 /* first time configuration */
 990
 991                 uint32_t size;
 992                 size = sizeof(hw->fkq_data.tx_queues[0]) * nb_queues;
 993                 hw->fkq_data.tx_queues = rte_zmalloc("fake_tx_queues", size,
 994                                                      RTE_CACHE_LINE_SIZE);
 995                 if (hw->fkq_data.tx_queues == NULL) {
 996                         hw->fkq_data.nb_fake_tx_queues = 0;
 997                         return -ENOMEM;
 998                 }
 999         } else if (hw->fkq_data.tx_queues != NULL && nb_queues != 0) {
1000                 /* re-configure */
1001
1002                 txq = hw->fkq_data.tx_queues;
1003                 for (i = nb_queues; i < old_nb_queues; i++)
1004                         hns3_dev_tx_queue_release(txq[i]);
1005                 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1006                                   RTE_CACHE_LINE_SIZE);
1007                 if (txq == NULL)
1008                         return -ENOMEM;
1009                 if (nb_queues > old_nb_queues) {
1010                         uint16_t new_qs = nb_queues - old_nb_queues;
1011                         memset(txq + old_nb_queues, 0, sizeof(txq[0]) * new_qs);
1012                 }
1013
1014                 hw->fkq_data.tx_queues = txq;
1015         } else if (hw->fkq_data.tx_queues != NULL && nb_queues == 0) {
1016                 txq = hw->fkq_data.tx_queues;
1017                 for (i = nb_queues; i < old_nb_queues; i++)
1018                         hns3_dev_tx_queue_release(txq[i]);
1019
1020                 rte_free(hw->fkq_data.tx_queues);
1021                 hw->fkq_data.tx_queues = NULL;
1022         }
1023         hw->fkq_data.nb_fake_tx_queues = nb_queues;
1024
1025         return 0;
1026 }
1027
1028 int
1029 hns3_set_fake_rx_or_tx_queues(struct rte_eth_dev *dev, uint16_t nb_rx_q,
1030                               uint16_t nb_tx_q)
1031 {
1032         struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1033         uint16_t rx_need_add_nb_q;
1034         uint16_t tx_need_add_nb_q;
1035         uint16_t port_id;
1036         uint16_t q;
1037         int ret;
1038
1039         /* Setup new number of fake RX/TX queues and reconfigure device. */
1040         hw->cfg_max_queues = RTE_MAX(nb_rx_q, nb_tx_q);
1041         rx_need_add_nb_q = hw->cfg_max_queues - nb_rx_q;
1042         tx_need_add_nb_q = hw->cfg_max_queues - nb_tx_q;
1043         ret = hns3_fake_rx_queue_config(hw, rx_need_add_nb_q);
1044         if (ret) {
1045                 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1046                 goto cfg_fake_rx_q_fail;
1047         }
1048
1049         ret = hns3_fake_tx_queue_config(hw, tx_need_add_nb_q);
1050         if (ret) {
1051                 hns3_err(hw, "Fail to configure fake rx queues: %d", ret);
1052                 goto cfg_fake_tx_q_fail;
1053         }
1054
1055         /* Allocate and set up fake RX queue per Ethernet port. */
1056         port_id = hw->data->port_id;
1057         for (q = 0; q < rx_need_add_nb_q; q++) {
1058                 ret = hns3_fake_rx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1059                                                rte_eth_dev_socket_id(port_id));
1060                 if (ret)
1061                         goto setup_fake_rx_q_fail;
1062         }
1063
1064         /* Allocate and set up fake TX queue per Ethernet port. */
1065         for (q = 0; q < tx_need_add_nb_q; q++) {
1066                 ret = hns3_fake_tx_queue_setup(dev, q, HNS3_MIN_RING_DESC,
1067                                                rte_eth_dev_socket_id(port_id));
1068                 if (ret)
1069                         goto setup_fake_tx_q_fail;
1070         }
1071
1072         return 0;
1073
1074 setup_fake_tx_q_fail:
1075 setup_fake_rx_q_fail:
1076         (void)hns3_fake_tx_queue_config(hw, 0);
1077 cfg_fake_tx_q_fail:
1078         (void)hns3_fake_rx_queue_config(hw, 0);
1079 cfg_fake_rx_q_fail:
1080         hw->cfg_max_queues = 0;
1081
1082         return ret;
1083 }
1084
1085 void
1086 hns3_dev_release_mbufs(struct hns3_adapter *hns)
1087 {
1088         struct rte_eth_dev_data *dev_data = hns->hw.data;
1089         struct hns3_rx_queue *rxq;
1090         struct hns3_tx_queue *txq;
1091         int i;
1092
1093         if (dev_data->rx_queues)
1094                 for (i = 0; i < dev_data->nb_rx_queues; i++) {
1095                         rxq = dev_data->rx_queues[i];
1096                         if (rxq == NULL || rxq->rx_deferred_start)
1097                                 continue;
1098                         hns3_rx_queue_release_mbufs(rxq);
1099                 }
1100
1101         if (dev_data->tx_queues)
1102                 for (i = 0; i < dev_data->nb_tx_queues; i++) {
1103                         txq = dev_data->tx_queues[i];
1104                         if (txq == NULL || txq->tx_deferred_start)
1105                                 continue;
1106                         hns3_tx_queue_release_mbufs(txq);
1107                 }
1108 }
1109
1110 int
1111 hns3_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1112                     unsigned int socket_id, const struct rte_eth_rxconf *conf,
1113                     struct rte_mempool *mp)
1114 {
1115         struct hns3_adapter *hns = dev->data->dev_private;
1116         struct hns3_hw *hw = &hns->hw;
1117         struct hns3_queue_info q_info;
1118         struct hns3_rx_queue *rxq;
1119         int rx_entry_len;
1120
1121         if (dev->data->dev_started) {
1122                 hns3_err(hw, "rx_queue_setup after dev_start no supported");
1123                 return -EINVAL;
1124         }
1125
1126         if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1127             nb_desc % HNS3_ALIGN_RING_DESC) {
1128                 hns3_err(hw, "Number (%u) of rx descriptors is invalid",
1129                          nb_desc);
1130                 return -EINVAL;
1131         }
1132
1133         if (dev->data->rx_queues[idx]) {
1134                 hns3_rx_queue_release(dev->data->rx_queues[idx]);
1135                 dev->data->rx_queues[idx] = NULL;
1136         }
1137
1138         q_info.idx = idx;
1139         q_info.socket_id = socket_id;
1140         q_info.nb_desc = nb_desc;
1141         q_info.type = "hns3 RX queue";
1142         q_info.ring_name = "rx_ring";
1143         rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
1144         if (rxq == NULL) {
1145                 hns3_err(hw,
1146                          "Failed to alloc mem and reserve DMA mem for rx ring!");
1147                 return -ENOMEM;
1148         }
1149
1150         rxq->hns = hns;
1151         rxq->mb_pool = mp;
1152         if (conf->rx_free_thresh <= 0)
1153                 rxq->rx_free_thresh = DEFAULT_RX_FREE_THRESH;
1154         else
1155                 rxq->rx_free_thresh = conf->rx_free_thresh;
1156         rxq->rx_deferred_start = conf->rx_deferred_start;
1157
1158         rx_entry_len = sizeof(struct hns3_entry) * rxq->nb_rx_desc;
1159         rxq->sw_ring = rte_zmalloc_socket("hns3 RX sw ring", rx_entry_len,
1160                                           RTE_CACHE_LINE_SIZE, socket_id);
1161         if (rxq->sw_ring == NULL) {
1162                 hns3_err(hw, "Failed to allocate memory for rx sw ring!");
1163                 hns3_rx_queue_release(rxq);
1164                 return -ENOMEM;
1165         }
1166
1167         rxq->next_to_use = 0;
1168         rxq->next_to_clean = 0;
1169         rxq->nb_rx_hold = 0;
1170         rxq->pkt_first_seg = NULL;
1171         rxq->pkt_last_seg = NULL;
1172         rxq->port_id = dev->data->port_id;
1173         rxq->configured = true;
1174         rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1175                                 idx * HNS3_TQP_REG_SIZE);
1176         rxq->rx_buf_len = hw->rx_buf_len;
1177         rxq->l2_errors = 0;
1178         rxq->pkt_len_errors = 0;
1179         rxq->l3_csum_erros = 0;
1180         rxq->l4_csum_erros = 0;
1181         rxq->ol3_csum_erros = 0;
1182         rxq->ol4_csum_erros = 0;
1183
1184         rte_spinlock_lock(&hw->lock);
1185         dev->data->rx_queues[idx] = rxq;
1186         rte_spinlock_unlock(&hw->lock);
1187
1188         return 0;
1189 }
1190
1191 static inline uint32_t
1192 rxd_pkt_info_to_pkt_type(uint32_t pkt_info, uint32_t ol_info)
1193 {
1194 #define HNS3_L2TBL_NUM  4
1195 #define HNS3_L3TBL_NUM  16
1196 #define HNS3_L4TBL_NUM  16
1197 #define HNS3_OL3TBL_NUM 16
1198 #define HNS3_OL4TBL_NUM 16
1199         uint32_t pkt_type = 0;
1200         uint32_t l2id, l3id, l4id;
1201         uint32_t ol3id, ol4id;
1202
1203         static const uint32_t l2table[HNS3_L2TBL_NUM] = {
1204                 RTE_PTYPE_L2_ETHER,
1205                 RTE_PTYPE_L2_ETHER_VLAN,
1206                 RTE_PTYPE_L2_ETHER_QINQ,
1207                 0
1208         };
1209
1210         static const uint32_t l3table[HNS3_L3TBL_NUM] = {
1211                 RTE_PTYPE_L3_IPV4,
1212                 RTE_PTYPE_L3_IPV6,
1213                 RTE_PTYPE_L2_ETHER_ARP,
1214                 RTE_PTYPE_L2_ETHER,
1215                 RTE_PTYPE_L3_IPV4_EXT,
1216                 RTE_PTYPE_L3_IPV6_EXT,
1217                 RTE_PTYPE_L2_ETHER_LLDP,
1218                 0, 0, 0, 0, 0, 0, 0, 0, 0
1219         };
1220
1221         static const uint32_t l4table[HNS3_L4TBL_NUM] = {
1222                 RTE_PTYPE_L4_UDP,
1223                 RTE_PTYPE_L4_TCP,
1224                 RTE_PTYPE_TUNNEL_GRE,
1225                 RTE_PTYPE_L4_SCTP,
1226                 RTE_PTYPE_L4_IGMP,
1227                 RTE_PTYPE_L4_ICMP,
1228                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1229         };
1230
1231         static const uint32_t inner_l2table[HNS3_L2TBL_NUM] = {
1232                 RTE_PTYPE_INNER_L2_ETHER,
1233                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1234                 RTE_PTYPE_INNER_L2_ETHER_QINQ,
1235                 0
1236         };
1237
1238         static const uint32_t inner_l3table[HNS3_L3TBL_NUM] = {
1239                 RTE_PTYPE_INNER_L3_IPV4,
1240                 RTE_PTYPE_INNER_L3_IPV6,
1241                 0,
1242                 RTE_PTYPE_INNER_L2_ETHER,
1243                 RTE_PTYPE_INNER_L3_IPV4_EXT,
1244                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1245                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1246         };
1247
1248         static const uint32_t inner_l4table[HNS3_L4TBL_NUM] = {
1249                 RTE_PTYPE_INNER_L4_UDP,
1250                 RTE_PTYPE_INNER_L4_TCP,
1251                 RTE_PTYPE_TUNNEL_GRE,
1252                 RTE_PTYPE_INNER_L4_SCTP,
1253                 RTE_PTYPE_L4_IGMP,
1254                 RTE_PTYPE_INNER_L4_ICMP,
1255                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1256         };
1257
1258         static const uint32_t ol3table[HNS3_OL3TBL_NUM] = {
1259                 RTE_PTYPE_L3_IPV4,
1260                 RTE_PTYPE_L3_IPV6,
1261                 0, 0,
1262                 RTE_PTYPE_L3_IPV4_EXT,
1263                 RTE_PTYPE_L3_IPV6_EXT,
1264                 0, 0, 0, 0, 0, 0, 0, 0, 0,
1265                 RTE_PTYPE_UNKNOWN
1266         };
1267
1268         static const uint32_t ol4table[HNS3_OL4TBL_NUM] = {
1269                 0,
1270                 RTE_PTYPE_TUNNEL_VXLAN,
1271                 RTE_PTYPE_TUNNEL_NVGRE,
1272                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1273         };
1274
1275         l2id = hns3_get_field(pkt_info, HNS3_RXD_STRP_TAGP_M,
1276                               HNS3_RXD_STRP_TAGP_S);
1277         l3id = hns3_get_field(pkt_info, HNS3_RXD_L3ID_M, HNS3_RXD_L3ID_S);
1278         l4id = hns3_get_field(pkt_info, HNS3_RXD_L4ID_M, HNS3_RXD_L4ID_S);
1279         ol3id = hns3_get_field(ol_info, HNS3_RXD_OL3ID_M, HNS3_RXD_OL3ID_S);
1280         ol4id = hns3_get_field(ol_info, HNS3_RXD_OL4ID_M, HNS3_RXD_OL4ID_S);
1281
1282         if (ol4table[ol4id])
1283                 pkt_type |= (inner_l2table[l2id] | inner_l3table[l3id] |
1284                              inner_l4table[l4id] | ol3table[ol3id] |
1285                              ol4table[ol4id]);
1286         else
1287                 pkt_type |= (l2table[l2id] | l3table[l3id] | l4table[l4id]);
1288         return pkt_type;
1289 }
1290
1291 const uint32_t *
1292 hns3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1293 {
1294         static const uint32_t ptypes[] = {
1295                 RTE_PTYPE_L2_ETHER,
1296                 RTE_PTYPE_L2_ETHER_VLAN,
1297                 RTE_PTYPE_L2_ETHER_QINQ,
1298                 RTE_PTYPE_L2_ETHER_LLDP,
1299                 RTE_PTYPE_L2_ETHER_ARP,
1300                 RTE_PTYPE_L3_IPV4,
1301                 RTE_PTYPE_L3_IPV4_EXT,
1302                 RTE_PTYPE_L3_IPV6,
1303                 RTE_PTYPE_L3_IPV6_EXT,
1304                 RTE_PTYPE_L4_IGMP,
1305                 RTE_PTYPE_L4_ICMP,
1306                 RTE_PTYPE_L4_SCTP,
1307                 RTE_PTYPE_L4_TCP,
1308                 RTE_PTYPE_L4_UDP,
1309                 RTE_PTYPE_TUNNEL_GRE,
1310                 RTE_PTYPE_UNKNOWN
1311         };
1312
1313         if (dev->rx_pkt_burst == hns3_recv_pkts)
1314                 return ptypes;
1315
1316         return NULL;
1317 }
1318
1319 static void
1320 hns3_clean_rx_buffers(struct hns3_rx_queue *rxq, int count)
1321 {
1322         rxq->next_to_use += count;
1323         if (rxq->next_to_use >= rxq->nb_rx_desc)
1324                 rxq->next_to_use -= rxq->nb_rx_desc;
1325
1326         hns3_write_dev(rxq, HNS3_RING_RX_HEAD_REG, count);
1327 }
1328
1329 static int
1330 hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,
1331                    uint32_t bd_base_info, uint32_t l234_info,
1332                    uint32_t *cksum_err)
1333 {
1334         uint32_t tmp = 0;
1335
1336         if (unlikely(l234_info & BIT(HNS3_RXD_L2E_B))) {
1337                 rxq->l2_errors++;
1338                 return -EINVAL;
1339         }
1340
1341         if (unlikely(rxm->pkt_len == 0 ||
1342                 (l234_info & BIT(HNS3_RXD_TRUNCAT_B)))) {
1343                 rxq->pkt_len_errors++;
1344                 return -EINVAL;
1345         }
1346
1347         if (bd_base_info & BIT(HNS3_RXD_L3L4P_B)) {
1348                 if (unlikely(l234_info & BIT(HNS3_RXD_L3E_B))) {
1349                         rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1350                         rxq->l3_csum_erros++;
1351                         tmp |= HNS3_L3_CKSUM_ERR;
1352                 }
1353
1354                 if (unlikely(l234_info & BIT(HNS3_RXD_L4E_B))) {
1355                         rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1356                         rxq->l4_csum_erros++;
1357                         tmp |= HNS3_L4_CKSUM_ERR;
1358                 }
1359
1360                 if (unlikely(l234_info & BIT(HNS3_RXD_OL3E_B))) {
1361                         rxq->ol3_csum_erros++;
1362                         tmp |= HNS3_OUTER_L3_CKSUM_ERR;
1363                 }
1364
1365                 if (unlikely(l234_info & BIT(HNS3_RXD_OL4E_B))) {
1366                         rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1367                         rxq->ol4_csum_erros++;
1368                         tmp |= HNS3_OUTER_L4_CKSUM_ERR;
1369                 }
1370         }
1371         *cksum_err = tmp;
1372
1373         return 0;
1374 }
1375
1376 static void
1377 hns3_rx_set_cksum_flag(struct rte_mbuf *rxm, uint64_t packet_type,
1378                        const uint32_t cksum_err)
1379 {
1380         if (unlikely((packet_type & RTE_PTYPE_TUNNEL_MASK))) {
1381                 if (likely(packet_type & RTE_PTYPE_INNER_L3_MASK) &&
1382                     (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1383                         rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1384                 if (likely(packet_type & RTE_PTYPE_INNER_L4_MASK) &&
1385                     (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1386                         rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1387                 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1388                     (cksum_err & HNS3_OUTER_L4_CKSUM_ERR) == 0)
1389                         rxm->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1390         } else {
1391                 if (likely(packet_type & RTE_PTYPE_L3_MASK) &&
1392                     (cksum_err & HNS3_L3_CKSUM_ERR) == 0)
1393                         rxm->ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1394                 if (likely(packet_type & RTE_PTYPE_L4_MASK) &&
1395                     (cksum_err & HNS3_L4_CKSUM_ERR) == 0)
1396                         rxm->ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1397         }
1398 }
1399
1400 uint16_t
1401 hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1402 {
1403         struct hns3_rx_queue *rxq;      /* RX queue */
1404         struct hns3_desc *rx_ring;      /* RX ring (desc) */
1405         struct hns3_entry *sw_ring;
1406         struct hns3_entry *rxe;
1407         struct hns3_desc *rxdp;         /* pointer of the current desc */
1408         struct rte_mbuf *first_seg;
1409         struct rte_mbuf *last_seg;
1410         struct rte_mbuf *nmb;           /* pointer of the new mbuf */
1411         struct rte_mbuf *rxm;
1412         struct rte_eth_dev *dev;
1413         uint32_t bd_base_info;
1414         uint32_t cksum_err;
1415         uint32_t l234_info;
1416         uint32_t ol_info;
1417         uint64_t dma_addr;
1418         uint16_t data_len;
1419         uint16_t nb_rx_bd;
1420         uint16_t pkt_len;
1421         uint16_t nb_rx;
1422         uint16_t rx_id;
1423         int ret;
1424
1425         nb_rx = 0;
1426         nb_rx_bd = 0;
1427         rxq = rx_queue;
1428         dev = &rte_eth_devices[rxq->port_id];
1429
1430         rx_id = rxq->next_to_clean;
1431         rx_ring = rxq->rx_ring;
1432         first_seg = rxq->pkt_first_seg;
1433         last_seg = rxq->pkt_last_seg;
1434         sw_ring = rxq->sw_ring;
1435
1436         while (nb_rx < nb_pkts) {
1437                 rxdp = &rx_ring[rx_id];
1438                 bd_base_info = rte_le_to_cpu_32(rxdp->rx.bd_base_info);
1439                 if (unlikely(!hns3_get_bit(bd_base_info, HNS3_RXD_VLD_B)))
1440                         break;
1441
1442                 nmb = rte_mbuf_raw_alloc(rxq->mb_pool);
1443                 if (unlikely(nmb == NULL)) {
1444                         dev->data->rx_mbuf_alloc_failed++;
1445                         break;
1446                 }
1447
1448                 nb_rx_bd++;
1449                 rxe = &sw_ring[rx_id];
1450                 rx_id++;
1451                 if (unlikely(rx_id == rxq->nb_rx_desc))
1452                         rx_id = 0;
1453
1454                 rte_prefetch0(sw_ring[rx_id].mbuf);
1455                 if ((rx_id & 0x3) == 0) {
1456                         rte_prefetch0(&rx_ring[rx_id]);
1457                         rte_prefetch0(&sw_ring[rx_id]);
1458                 }
1459
1460                 rxm = rxe->mbuf;
1461                 rxe->mbuf = nmb;
1462
1463                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1464                 rxdp->addr = dma_addr;
1465                 rxdp->rx.bd_base_info = 0;
1466
1467                 rte_cio_rmb();
1468                 /* Load remained descriptor data and extract necessary fields */
1469                 data_len = (uint16_t)(rte_le_to_cpu_16(rxdp->rx.size));
1470                 l234_info = rte_le_to_cpu_32(rxdp->rx.l234_info);
1471                 ol_info = rte_le_to_cpu_32(rxdp->rx.ol_info);
1472
1473                 if (first_seg == NULL) {
1474                         first_seg = rxm;
1475                         first_seg->nb_segs = 1;
1476                 } else {
1477                         first_seg->nb_segs++;
1478                         last_seg->next = rxm;
1479                 }
1480
1481                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1482                 rxm->data_len = data_len;
1483
1484                 if (!hns3_get_bit(bd_base_info, HNS3_RXD_FE_B)) {
1485                         last_seg = rxm;
1486                         continue;
1487                 }
1488
1489                 /* The last buffer of the received packet */
1490                 pkt_len = (uint16_t)(rte_le_to_cpu_16(rxdp->rx.pkt_len));
1491                 first_seg->pkt_len = pkt_len;
1492                 first_seg->port = rxq->port_id;
1493                 first_seg->hash.rss = rte_le_to_cpu_32(rxdp->rx.rss_hash);
1494                 first_seg->ol_flags |= PKT_RX_RSS_HASH;
1495                 if (unlikely(hns3_get_bit(bd_base_info, HNS3_RXD_LUM_B))) {
1496                         first_seg->hash.fdir.hi =
1497                                 rte_le_to_cpu_32(rxdp->rx.fd_id);
1498                         first_seg->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1499                 }
1500                 rxm->next = NULL;
1501
1502                 ret = hns3_handle_bdinfo(rxq, first_seg, bd_base_info,
1503                                          l234_info, &cksum_err);
1504                 if (unlikely(ret))
1505                         goto pkt_err;
1506
1507                 first_seg->packet_type = rxd_pkt_info_to_pkt_type(l234_info,
1508                                                                   ol_info);
1509
1510                 if (bd_base_info & BIT(HNS3_RXD_L3L4P_B))
1511                         hns3_rx_set_cksum_flag(rxm, first_seg->packet_type,
1512                                                cksum_err);
1513
1514                 first_seg->vlan_tci = rte_le_to_cpu_16(rxdp->rx.vlan_tag);
1515                 first_seg->vlan_tci_outer =
1516                         rte_le_to_cpu_16(rxdp->rx.ot_vlan_tag);
1517                 rx_pkts[nb_rx++] = first_seg;
1518                 first_seg = NULL;
1519                 continue;
1520 pkt_err:
1521                 rte_pktmbuf_free(first_seg);
1522                 first_seg = NULL;
1523         }
1524
1525         rxq->next_to_clean = rx_id;
1526         rxq->pkt_first_seg = first_seg;
1527         rxq->pkt_last_seg = last_seg;
1528         hns3_clean_rx_buffers(rxq, nb_rx_bd);
1529
1530         return nb_rx;
1531 }
1532
1533 int
1534 hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
1535                     unsigned int socket_id, const struct rte_eth_txconf *conf)
1536 {
1537         struct hns3_adapter *hns = dev->data->dev_private;
1538         struct hns3_hw *hw = &hns->hw;
1539         struct hns3_queue_info q_info;
1540         struct hns3_tx_queue *txq;
1541         int tx_entry_len;
1542
1543         if (dev->data->dev_started) {
1544                 hns3_err(hw, "tx_queue_setup after dev_start no supported");
1545                 return -EINVAL;
1546         }
1547
1548         if (nb_desc > HNS3_MAX_RING_DESC || nb_desc < HNS3_MIN_RING_DESC ||
1549             nb_desc % HNS3_ALIGN_RING_DESC) {
1550                 hns3_err(hw, "Number (%u) of tx descriptors is invalid",
1551                             nb_desc);
1552                 return -EINVAL;
1553         }
1554
1555         if (dev->data->tx_queues[idx] != NULL) {
1556                 hns3_tx_queue_release(dev->data->tx_queues[idx]);
1557                 dev->data->tx_queues[idx] = NULL;
1558         }
1559
1560         q_info.idx = idx;
1561         q_info.socket_id = socket_id;
1562         q_info.nb_desc = nb_desc;
1563         q_info.type = "hns3 TX queue";
1564         q_info.ring_name = "tx_ring";
1565         txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
1566         if (txq == NULL) {
1567                 hns3_err(hw,
1568                          "Failed to alloc mem and reserve DMA mem for tx ring!");
1569                 return -ENOMEM;
1570         }
1571
1572         txq->tx_deferred_start = conf->tx_deferred_start;
1573         tx_entry_len = sizeof(struct hns3_entry) * txq->nb_tx_desc;
1574         txq->sw_ring = rte_zmalloc_socket("hns3 TX sw ring", tx_entry_len,
1575                                           RTE_CACHE_LINE_SIZE, socket_id);
1576         if (txq->sw_ring == NULL) {
1577                 hns3_err(hw, "Failed to allocate memory for tx sw ring!");
1578                 hns3_tx_queue_release(txq);
1579                 return -ENOMEM;
1580         }
1581
1582         txq->hns = hns;
1583         txq->next_to_use = 0;
1584         txq->next_to_clean = 0;
1585         txq->tx_bd_ready = txq->nb_tx_desc - 1;
1586         txq->port_id = dev->data->port_id;
1587         txq->configured = true;
1588         txq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
1589                                 idx * HNS3_TQP_REG_SIZE);
1590         rte_spinlock_lock(&hw->lock);
1591         dev->data->tx_queues[idx] = txq;
1592         rte_spinlock_unlock(&hw->lock);
1593
1594         return 0;
1595 }
1596
1597 static inline void
1598 hns3_queue_xmit(struct hns3_tx_queue *txq, uint32_t buf_num)
1599 {
1600         hns3_write_dev(txq, HNS3_RING_TX_TAIL_REG, buf_num);
1601 }
1602
1603 static void
1604 hns3_tx_free_useless_buffer(struct hns3_tx_queue *txq)
1605 {
1606         uint16_t tx_next_clean = txq->next_to_clean;
1607         uint16_t tx_next_use   = txq->next_to_use;
1608         uint16_t tx_bd_ready   = txq->tx_bd_ready;
1609         uint16_t tx_bd_max     = txq->nb_tx_desc;
1610         struct hns3_entry *tx_bak_pkt = &txq->sw_ring[tx_next_clean];
1611         struct hns3_desc *desc = &txq->tx_ring[tx_next_clean];
1612         struct rte_mbuf *mbuf;
1613
1614         while ((!hns3_get_bit(desc->tx.tp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B)) &&
1615                 tx_next_use != tx_next_clean) {
1616                 mbuf = tx_bak_pkt->mbuf;
1617                 if (mbuf) {
1618                         rte_pktmbuf_free_seg(mbuf);
1619                         tx_bak_pkt->mbuf = NULL;
1620                 }
1621
1622                 desc++;
1623                 tx_bak_pkt++;
1624                 tx_next_clean++;
1625                 tx_bd_ready++;
1626
1627                 if (tx_next_clean >= tx_bd_max) {
1628                         tx_next_clean = 0;
1629                         desc = txq->tx_ring;
1630                         tx_bak_pkt = txq->sw_ring;
1631                 }
1632         }
1633
1634         txq->next_to_clean = tx_next_clean;
1635         txq->tx_bd_ready   = tx_bd_ready;
1636 }
1637
1638 static void
1639 fill_desc(struct hns3_tx_queue *txq, uint16_t tx_desc_id, struct rte_mbuf *rxm,
1640           bool first, int offset)
1641 {
1642         struct hns3_desc *tx_ring = txq->tx_ring;
1643         struct hns3_desc *desc = &tx_ring[tx_desc_id];
1644         uint8_t frag_end = rxm->next == NULL ? 1 : 0;
1645         uint16_t size = rxm->data_len;
1646         uint16_t rrcfv = 0;
1647         uint64_t ol_flags = rxm->ol_flags;
1648         uint32_t hdr_len;
1649         uint32_t paylen;
1650         uint32_t tmp;
1651
1652         desc->addr = rte_mbuf_data_iova(rxm) + offset;
1653         desc->tx.send_size = rte_cpu_to_le_16(size);
1654         hns3_set_bit(rrcfv, HNS3_TXD_VLD_B, 1);
1655
1656         if (first) {
1657                 hdr_len = rxm->l2_len + rxm->l3_len + rxm->l4_len;
1658                 hdr_len += (ol_flags & PKT_TX_TUNNEL_MASK) ?
1659                            rxm->outer_l2_len + rxm->outer_l3_len : 0;
1660                 paylen = rxm->pkt_len - hdr_len;
1661                 desc->tx.paylen = rte_cpu_to_le_32(paylen);
1662         }
1663
1664         hns3_set_bit(rrcfv, HNS3_TXD_FE_B, frag_end);
1665         desc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(rrcfv);
1666
1667         if (frag_end) {
1668                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1669                         tmp = rte_le_to_cpu_32(desc->tx.type_cs_vlan_tso_len);
1670                         hns3_set_bit(tmp, HNS3_TXD_VLAN_B, 1);
1671                         desc->tx.type_cs_vlan_tso_len = rte_cpu_to_le_32(tmp);
1672                         desc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);
1673                 }
1674
1675                 if (ol_flags & PKT_TX_QINQ_PKT) {
1676                         tmp = rte_le_to_cpu_32(desc->tx.ol_type_vlan_len_msec);
1677                         hns3_set_bit(tmp, HNS3_TXD_OVLAN_B, 1);
1678                         desc->tx.ol_type_vlan_len_msec = rte_cpu_to_le_32(tmp);
1679                         desc->tx.outer_vlan_tag =
1680                                 rte_cpu_to_le_16(rxm->vlan_tci_outer);
1681                 }
1682         }
1683 }
1684
1685 static int
1686 hns3_tx_alloc_mbufs(struct hns3_tx_queue *txq, struct rte_mempool *mb_pool,
1687                     uint16_t nb_new_buf, struct rte_mbuf **alloc_mbuf)
1688 {
1689         struct rte_mbuf *new_mbuf = NULL;
1690         struct rte_eth_dev *dev;
1691         struct rte_mbuf *temp;
1692         struct hns3_hw *hw;
1693         uint16_t i;
1694
1695         /* Allocate enough mbufs */
1696         for (i = 0; i < nb_new_buf; i++) {
1697                 temp = rte_pktmbuf_alloc(mb_pool);
1698                 if (unlikely(temp == NULL)) {
1699                         dev = &rte_eth_devices[txq->port_id];
1700                         hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1701                         hns3_err(hw, "Failed to alloc TX mbuf port_id=%d,"
1702                                      "queue_id=%d in reassemble tx pkts.",
1703                                      txq->port_id, txq->queue_id);
1704                         rte_pktmbuf_free(new_mbuf);
1705                         return -ENOMEM;
1706                 }
1707                 temp->next = new_mbuf;
1708                 new_mbuf = temp;
1709         }
1710
1711         if (new_mbuf == NULL)
1712                 return -ENOMEM;
1713
1714         new_mbuf->nb_segs = nb_new_buf;
1715         *alloc_mbuf = new_mbuf;
1716
1717         return 0;
1718 }
1719
1720 static int
1721 hns3_reassemble_tx_pkts(void *tx_queue, struct rte_mbuf *tx_pkt,
1722                         struct rte_mbuf **new_pkt)
1723 {
1724         struct hns3_tx_queue *txq = tx_queue;
1725         struct rte_mempool *mb_pool;
1726         struct rte_mbuf *new_mbuf;
1727         struct rte_mbuf *temp_new;
1728         struct rte_mbuf *temp;
1729         uint16_t last_buf_len;
1730         uint16_t nb_new_buf;
1731         uint16_t buf_size;
1732         uint16_t buf_len;
1733         uint16_t len_s;
1734         uint16_t len_d;
1735         uint16_t len;
1736         uint16_t i;
1737         int ret;
1738         char *s;
1739         char *d;
1740
1741         mb_pool = tx_pkt->pool;
1742         buf_size = tx_pkt->buf_len - RTE_PKTMBUF_HEADROOM;
1743         nb_new_buf = (tx_pkt->pkt_len - 1) / buf_size + 1;
1744
1745         last_buf_len = tx_pkt->pkt_len % buf_size;
1746         if (last_buf_len == 0)
1747                 last_buf_len = buf_size;
1748
1749         /* Allocate enough mbufs */
1750         ret = hns3_tx_alloc_mbufs(txq, mb_pool, nb_new_buf, &new_mbuf);
1751         if (ret)
1752                 return ret;
1753
1754         /* Copy the original packet content to the new mbufs */
1755         temp = tx_pkt;
1756         s = rte_pktmbuf_mtod(temp, char *);
1757         len_s = temp->data_len;
1758         temp_new = new_mbuf;
1759         for (i = 0; i < nb_new_buf; i++) {
1760                 d = rte_pktmbuf_mtod(temp_new, char *);
1761                 if (i < nb_new_buf - 1)
1762                         buf_len = buf_size;
1763                 else
1764                         buf_len = last_buf_len;
1765                 len_d = buf_len;
1766
1767                 while (len_d) {
1768                         len = RTE_MIN(len_s, len_d);
1769                         memcpy(d, s, len);
1770                         s = s + len;
1771                         d = d + len;
1772                         len_d = len_d - len;
1773                         len_s = len_s - len;
1774
1775                         if (len_s == 0) {
1776                                 temp = temp->next;
1777                                 if (temp == NULL)
1778                                         break;
1779                                 s = rte_pktmbuf_mtod(temp, char *);
1780                                 len_s = temp->data_len;
1781                         }
1782                 }
1783
1784                 temp_new->data_len = buf_len;
1785                 temp_new = temp_new->next;
1786         }
1787
1788         /* free original mbufs */
1789         rte_pktmbuf_free(tx_pkt);
1790
1791         *new_pkt = new_mbuf;
1792
1793         return 0;
1794 }
1795
1796 static void
1797 hns3_parse_outer_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec)
1798 {
1799         uint32_t tmp = *ol_type_vlan_len_msec;
1800
1801         /* (outer) IP header type */
1802         if (ol_flags & PKT_TX_OUTER_IPV4) {
1803                 /* OL3 header size, defined in 4 bytes */
1804                 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
1805                                sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
1806                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1807                         hns3_set_field(tmp, HNS3_TXD_OL3T_M,
1808                                        HNS3_TXD_OL3T_S, HNS3_OL3T_IPV4_CSUM);
1809                 else
1810                         hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
1811                                        HNS3_OL3T_IPV4_NO_CSUM);
1812         } else if (ol_flags & PKT_TX_OUTER_IPV6) {
1813                 hns3_set_field(tmp, HNS3_TXD_OL3T_M, HNS3_TXD_OL3T_S,
1814                                HNS3_OL3T_IPV6);
1815                 /* OL3 header size, defined in 4 bytes */
1816                 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
1817                                sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
1818         }
1819
1820         *ol_type_vlan_len_msec = tmp;
1821 }
1822
1823 static int
1824 hns3_parse_inner_params(uint64_t ol_flags, uint32_t *ol_type_vlan_len_msec,
1825                         struct rte_net_hdr_lens *hdr_lens)
1826 {
1827         uint32_t tmp = *ol_type_vlan_len_msec;
1828         uint8_t l4_len;
1829
1830         /* OL2 header size, defined in 2 bytes */
1831         hns3_set_field(tmp, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
1832                        sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
1833
1834         /* L4TUNT: L4 Tunneling Type */
1835         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
1836         case PKT_TX_TUNNEL_GENEVE:
1837         case PKT_TX_TUNNEL_VXLAN:
1838                 /* MAC in UDP tunnelling packet, include VxLAN */
1839                 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
1840                                HNS3_TUN_MAC_IN_UDP);
1841                 /*
1842                  * OL4 header size, defined in 4 Bytes, it contains outer
1843                  * L4(UDP) length and tunneling length.
1844                  */
1845                 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
1846                                (uint8_t)RTE_ETHER_VXLAN_HLEN >>
1847                                HNS3_L4_LEN_UNIT);
1848                 break;
1849         case PKT_TX_TUNNEL_GRE:
1850                 hns3_set_field(tmp, HNS3_TXD_TUNTYPE_M, HNS3_TXD_TUNTYPE_S,
1851                                HNS3_TUN_NVGRE);
1852                 /*
1853                  * OL4 header size, defined in 4 Bytes, it contains outer
1854                  * L4(GRE) length and tunneling length.
1855                  */
1856                 l4_len = hdr_lens->l4_len + hdr_lens->tunnel_len;
1857                 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
1858                                l4_len >> HNS3_L4_LEN_UNIT);
1859                 break;
1860         default:
1861                 /* For non UDP / GRE tunneling, drop the tunnel packet */
1862                 return -EINVAL;
1863         }
1864
1865         *ol_type_vlan_len_msec = tmp;
1866
1867         return 0;
1868 }
1869
1870 static int
1871 hns3_parse_tunneling_params(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
1872                             uint64_t ol_flags,
1873                             struct rte_net_hdr_lens *hdr_lens)
1874 {
1875         struct hns3_desc *tx_ring = txq->tx_ring;
1876         struct hns3_desc *desc = &tx_ring[tx_desc_id];
1877         uint32_t value = 0;
1878         int ret;
1879
1880         hns3_parse_outer_params(ol_flags, &value);
1881         ret = hns3_parse_inner_params(ol_flags, &value, hdr_lens);
1882         if (ret)
1883                 return -EINVAL;
1884
1885         desc->tx.ol_type_vlan_len_msec |= rte_cpu_to_le_32(value);
1886
1887         return 0;
1888 }
1889
1890 static void
1891 hns3_parse_l3_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
1892 {
1893         uint32_t tmp;
1894
1895         /* Enable L3 checksum offloads */
1896         if (ol_flags & PKT_TX_IPV4) {
1897                 tmp = *type_cs_vlan_tso_len;
1898                 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
1899                                HNS3_L3T_IPV4);
1900                 /* inner(/normal) L3 header size, defined in 4 bytes */
1901                 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
1902                                sizeof(struct rte_ipv4_hdr) >> HNS3_L3_LEN_UNIT);
1903                 if (ol_flags & PKT_TX_IP_CKSUM)
1904                         hns3_set_bit(tmp, HNS3_TXD_L3CS_B, 1);
1905                 *type_cs_vlan_tso_len = tmp;
1906         } else if (ol_flags & PKT_TX_IPV6) {
1907                 tmp = *type_cs_vlan_tso_len;
1908                 /* L3T, IPv6 don't do checksum */
1909                 hns3_set_field(tmp, HNS3_TXD_L3T_M, HNS3_TXD_L3T_S,
1910                                HNS3_L3T_IPV6);
1911                 /* inner(/normal) L3 header size, defined in 4 bytes */
1912                 hns3_set_field(tmp, HNS3_TXD_L3LEN_M, HNS3_TXD_L3LEN_S,
1913                                sizeof(struct rte_ipv6_hdr) >> HNS3_L3_LEN_UNIT);
1914                 *type_cs_vlan_tso_len = tmp;
1915         }
1916 }
1917
1918 static void
1919 hns3_parse_l4_cksum_params(uint64_t ol_flags, uint32_t *type_cs_vlan_tso_len)
1920 {
1921         uint32_t tmp;
1922
1923         /* Enable L4 checksum offloads */
1924         switch (ol_flags & PKT_TX_L4_MASK) {
1925         case PKT_TX_TCP_CKSUM:
1926                 tmp = *type_cs_vlan_tso_len;
1927                 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
1928                                HNS3_L4T_TCP);
1929                 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
1930                 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
1931                                sizeof(struct rte_tcp_hdr) >> HNS3_L4_LEN_UNIT);
1932                 *type_cs_vlan_tso_len = tmp;
1933                 break;
1934         case PKT_TX_UDP_CKSUM:
1935                 tmp = *type_cs_vlan_tso_len;
1936                 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
1937                                HNS3_L4T_UDP);
1938                 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
1939                 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
1940                                sizeof(struct rte_udp_hdr) >> HNS3_L4_LEN_UNIT);
1941                 *type_cs_vlan_tso_len = tmp;
1942                 break;
1943         case PKT_TX_SCTP_CKSUM:
1944                 tmp = *type_cs_vlan_tso_len;
1945                 hns3_set_field(tmp, HNS3_TXD_L4T_M, HNS3_TXD_L4T_S,
1946                                HNS3_L4T_SCTP);
1947                 hns3_set_bit(tmp, HNS3_TXD_L4CS_B, 1);
1948                 hns3_set_field(tmp, HNS3_TXD_L4LEN_M, HNS3_TXD_L4LEN_S,
1949                                sizeof(struct rte_sctp_hdr) >> HNS3_L4_LEN_UNIT);
1950                 *type_cs_vlan_tso_len = tmp;
1951                 break;
1952         default:
1953                 break;
1954         }
1955 }
1956
1957 static void
1958 hns3_txd_enable_checksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
1959                          uint64_t ol_flags)
1960 {
1961         struct hns3_desc *tx_ring = txq->tx_ring;
1962         struct hns3_desc *desc = &tx_ring[tx_desc_id];
1963         uint32_t value = 0;
1964
1965         /* inner(/normal) L2 header size, defined in 2 bytes */
1966         hns3_set_field(value, HNS3_TXD_L2LEN_M, HNS3_TXD_L2LEN_S,
1967                        sizeof(struct rte_ether_hdr) >> HNS3_L2_LEN_UNIT);
1968
1969         hns3_parse_l3_cksum_params(ol_flags, &value);
1970         hns3_parse_l4_cksum_params(ol_flags, &value);
1971
1972         desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(value);
1973 }
1974
1975 uint16_t
1976 hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1977                uint16_t nb_pkts)
1978 {
1979         struct rte_mbuf *m;
1980         uint16_t i;
1981         int ret;
1982
1983         for (i = 0; i < nb_pkts; i++) {
1984                 m = tx_pkts[i];
1985
1986                 /* check the size of packet */
1987                 if (m->pkt_len < RTE_ETHER_MIN_LEN) {
1988                         rte_errno = EINVAL;
1989                         return i;
1990                 }
1991
1992 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1993                 ret = rte_validate_tx_offload(m);
1994                 if (ret != 0) {
1995                         rte_errno = -ret;
1996                         return i;
1997                 }
1998 #endif
1999                 ret = rte_net_intel_cksum_prepare(m);
2000                 if (ret != 0) {
2001                         rte_errno = -ret;
2002                         return i;
2003                 }
2004         }
2005
2006         return i;
2007 }
2008
2009 static int
2010 hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
2011                  const struct rte_mbuf *m, struct rte_net_hdr_lens *hdr_lens)
2012 {
2013         /* Fill in tunneling parameters if necessary */
2014         if (m->ol_flags & PKT_TX_TUNNEL_MASK) {
2015                 (void)rte_net_get_ptype(m, hdr_lens, RTE_PTYPE_ALL_MASK);
2016                 if (hns3_parse_tunneling_params(txq, tx_desc_id, m->ol_flags,
2017                                                 hdr_lens))
2018                         return -EINVAL;
2019         }
2020         /* Enable checksum offloading */
2021         if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK)
2022                 hns3_txd_enable_checksum(txq, tx_desc_id, m->ol_flags);
2023
2024         return 0;
2025 }
2026
2027 uint16_t
2028 hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2029 {
2030         struct rte_net_hdr_lens hdr_lens = {0};
2031         struct hns3_tx_queue *txq = tx_queue;
2032         struct hns3_entry *tx_bak_pkt;
2033         struct rte_mbuf *new_pkt;
2034         struct rte_mbuf *tx_pkt;
2035         struct rte_mbuf *m_seg;
2036         uint32_t nb_hold = 0;
2037         uint16_t tx_next_use;
2038         uint16_t tx_pkt_num;
2039         uint16_t tx_bd_max;
2040         uint16_t nb_buf;
2041         uint16_t nb_tx;
2042         uint16_t i;
2043
2044         /* free useless buffer */
2045         hns3_tx_free_useless_buffer(txq);
2046
2047         tx_next_use   = txq->next_to_use;
2048         tx_bd_max     = txq->nb_tx_desc;
2049         tx_pkt_num = nb_pkts;
2050
2051         /* send packets */
2052         tx_bak_pkt = &txq->sw_ring[tx_next_use];
2053         for (nb_tx = 0; nb_tx < tx_pkt_num; nb_tx++) {
2054                 tx_pkt = *tx_pkts++;
2055
2056                 nb_buf = tx_pkt->nb_segs;
2057
2058                 if (nb_buf > txq->tx_bd_ready) {
2059                         if (nb_tx == 0)
2060                                 return 0;
2061
2062                         goto end_of_tx;
2063                 }
2064
2065                 /*
2066                  * If packet length is greater than HNS3_MAX_FRAME_LEN
2067                  * driver support, the packet will be ignored.
2068                  */
2069                 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) > HNS3_MAX_FRAME_LEN))
2070                         break;
2071
2072                 /*
2073                  * If packet length is less than minimum packet size, driver
2074                  * need to pad it.
2075                  */
2076                 if (unlikely(rte_pktmbuf_pkt_len(tx_pkt) < HNS3_MIN_PKT_SIZE)) {
2077                         uint16_t add_len;
2078                         char *appended;
2079
2080                         add_len = HNS3_MIN_PKT_SIZE -
2081                                          rte_pktmbuf_pkt_len(tx_pkt);
2082                         appended = rte_pktmbuf_append(tx_pkt, add_len);
2083                         if (appended == NULL)
2084                                 break;
2085
2086                         memset(appended, 0, add_len);
2087                 }
2088
2089                 m_seg = tx_pkt;
2090                 if (unlikely(nb_buf > HNS3_MAX_TX_BD_PER_PKT)) {
2091                         if (hns3_reassemble_tx_pkts(txq, tx_pkt, &new_pkt))
2092                                 goto end_of_tx;
2093                         m_seg = new_pkt;
2094                         nb_buf = m_seg->nb_segs;
2095                 }
2096
2097                 if (hns3_parse_cksum(txq, tx_next_use, m_seg, &hdr_lens))
2098                         goto end_of_tx;
2099
2100                 i = 0;
2101                 do {
2102                         fill_desc(txq, tx_next_use, m_seg, (i == 0), 0);
2103                         tx_bak_pkt->mbuf = m_seg;
2104                         m_seg = m_seg->next;
2105                         tx_next_use++;
2106                         tx_bak_pkt++;
2107                         if (tx_next_use >= tx_bd_max) {
2108                                 tx_next_use = 0;
2109                                 tx_bak_pkt = txq->sw_ring;
2110                         }
2111
2112                         i++;
2113                 } while (m_seg != NULL);
2114
2115                 nb_hold += i;
2116                 txq->next_to_use = tx_next_use;
2117                 txq->tx_bd_ready -= i;
2118         }
2119
2120 end_of_tx:
2121
2122         if (likely(nb_tx))
2123                 hns3_queue_xmit(txq, nb_hold);
2124
2125         return nb_tx;
2126 }
2127
2128 static uint16_t
2129 hns3_dummy_rxtx_burst(void *dpdk_txq __rte_unused,
2130                       struct rte_mbuf **pkts __rte_unused,
2131                       uint16_t pkts_n __rte_unused)
2132 {
2133         return 0;
2134 }
2135
2136 void hns3_set_rxtx_function(struct rte_eth_dev *eth_dev)
2137 {
2138         struct hns3_adapter *hns = eth_dev->data->dev_private;
2139
2140         if (hns->hw.adapter_state == HNS3_NIC_STARTED &&
2141             rte_atomic16_read(&hns->hw.reset.resetting) == 0) {
2142                 eth_dev->rx_pkt_burst = hns3_recv_pkts;
2143                 eth_dev->tx_pkt_burst = hns3_xmit_pkts;
2144                 eth_dev->tx_pkt_prepare = hns3_prep_pkts;
2145         } else {
2146                 eth_dev->rx_pkt_burst = hns3_dummy_rxtx_burst;
2147                 eth_dev->tx_pkt_burst = hns3_dummy_rxtx_burst;
2148                 eth_dev->tx_pkt_prepare = hns3_dummy_rxtx_burst;
2149         }
2150 }