1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2020-2021 HiSilicon Limited.
7 #include <ethdev_driver.h>
9 #include "hns3_ethdev.h"
10 #include "hns3_rxtx.h"
11 #include "hns3_rxtx_vec.h"
13 #define PG16_128BIT svwhilelt_b16(0, 8)
14 #define PG16_256BIT svwhilelt_b16(0, 16)
15 #define PG32_256BIT svwhilelt_b32(0, 8)
16 #define PG64_64BIT svwhilelt_b64(0, 1)
17 #define PG64_128BIT svwhilelt_b64(0, 2)
18 #define PG64_256BIT svwhilelt_b64(0, 4)
19 #define PG64_ALLBIT svptrue_b64()
22 #define BD_FIELD_ADDR_OFFSET 0
23 #define BD_FIELD_L234_OFFSET 8
24 #define BD_FIELD_XLEN_OFFSET 12
25 #define BD_FIELD_RSS_OFFSET 16
26 #define BD_FIELD_OL_OFFSET 24
27 #define BD_FIELD_VALID_OFFSET 28
30 uint32_t l234_info[HNS3_SVE_DEFAULT_DESCS_PER_LOOP];
31 uint32_t ol_info[HNS3_SVE_DEFAULT_DESCS_PER_LOOP];
32 uint32_t bd_base_info[HNS3_SVE_DEFAULT_DESCS_PER_LOOP];
33 } HNS3_SVE_KEY_FIELD_S;
35 static inline uint32_t
36 hns3_desc_parse_field_sve(struct hns3_rx_queue *rxq,
37 struct rte_mbuf **rx_pkts,
38 HNS3_SVE_KEY_FIELD_S *key,
44 for (i = 0; i < (int)bd_vld_num; i++) {
45 /* init rte_mbuf.rearm_data last 64-bit */
46 rx_pkts[i]->ol_flags = PKT_RX_RSS_HASH;
48 ret = hns3_handle_bdinfo(rxq, rx_pkts[i], key->bd_base_info[i],
55 rx_pkts[i]->packet_type = hns3_rx_calc_ptype(rxq,
56 key->l234_info[i], key->ol_info[i]);
58 /* Increment bytes counter */
59 rxq->basic_stats.bytes += rx_pkts[i]->pkt_len;
66 hns3_rx_prefetch_mbuf_sve(struct hns3_entry *sw_ring)
68 svuint64_t prf1st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[0]);
69 svuint64_t prf2st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[4]);
70 svprfd_gather_u64base(PG64_256BIT, prf1st, SV_PLDL1KEEP);
71 svprfd_gather_u64base(PG64_256BIT, prf2st, SV_PLDL1KEEP);
74 static inline uint16_t
75 hns3_recv_burst_vec_sve(struct hns3_rx_queue *__restrict rxq,
76 struct rte_mbuf **__restrict rx_pkts,
78 uint64_t *bd_err_mask)
80 #define XLEN_ADJUST_LEN 32
81 #define RSS_ADJUST_LEN 16
82 #define GEN_VLD_U8_ZIP_INDEX svindex_s8(28, -4)
83 uint16_t rx_id = rxq->next_to_use;
84 struct hns3_entry *sw_ring = &rxq->sw_ring[rx_id];
85 struct hns3_desc *rxdp = &rxq->rx_ring[rx_id];
86 struct hns3_desc *rxdp2;
87 HNS3_SVE_KEY_FIELD_S key_field;
88 uint64_t bd_valid_num;
89 uint32_t parse_retcode;
93 uint16_t xlen_adjust[XLEN_ADJUST_LEN] = {
94 0, 0xffff, 1, 0xffff, /* 1st mbuf: pkt_len and dat_len */
95 2, 0xffff, 3, 0xffff, /* 2st mbuf: pkt_len and dat_len */
96 4, 0xffff, 5, 0xffff, /* 3st mbuf: pkt_len and dat_len */
97 6, 0xffff, 7, 0xffff, /* 4st mbuf: pkt_len and dat_len */
98 8, 0xffff, 9, 0xffff, /* 5st mbuf: pkt_len and dat_len */
99 10, 0xffff, 11, 0xffff, /* 6st mbuf: pkt_len and dat_len */
100 12, 0xffff, 13, 0xffff, /* 7st mbuf: pkt_len and dat_len */
101 14, 0xffff, 15, 0xffff, /* 8st mbuf: pkt_len and dat_len */
104 uint32_t rss_adjust[RSS_ADJUST_LEN] = {
105 0, 0xffff, /* 1st mbuf: rss */
106 1, 0xffff, /* 2st mbuf: rss */
107 2, 0xffff, /* 3st mbuf: rss */
108 3, 0xffff, /* 4st mbuf: rss */
109 4, 0xffff, /* 5st mbuf: rss */
110 5, 0xffff, /* 6st mbuf: rss */
111 6, 0xffff, /* 7st mbuf: rss */
112 7, 0xffff, /* 8st mbuf: rss */
115 svbool_t pg32 = svwhilelt_b32(0, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
116 svuint16_t xlen_tbl1 = svld1_u16(PG16_256BIT, xlen_adjust);
117 svuint16_t xlen_tbl2 = svld1_u16(PG16_256BIT, &xlen_adjust[16]);
118 svuint32_t rss_tbl1 = svld1_u32(PG32_256BIT, rss_adjust);
119 svuint32_t rss_tbl2 = svld1_u32(PG32_256BIT, &rss_adjust[8]);
121 for (pos = 0; pos < nb_pkts; pos += HNS3_SVE_DEFAULT_DESCS_PER_LOOP,
122 rxdp += HNS3_SVE_DEFAULT_DESCS_PER_LOOP) {
123 svuint64_t vld_clz, mbp1st, mbp2st, mbuf_init;
124 svuint64_t xlen1st, xlen2st, rss1st, rss2st;
125 svuint32_t l234, ol, vld, vld2, xlen, rss;
128 /* calc how many bd valid: part 1 */
129 vld = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp,
130 svindex_u32(BD_FIELD_VALID_OFFSET, BD_SIZE));
131 vld2 = svlsl_n_u32_z(pg32, vld,
132 HNS3_UINT32_BIT - 1 - HNS3_RXD_VLD_B);
133 vld2 = svreinterpret_u32_s32(svasr_n_s32_z(pg32,
134 svreinterpret_s32_u32(vld2), HNS3_UINT32_BIT - 1));
136 /* load 4 mbuf pointer */
137 mbp1st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[pos]);
139 /* calc how many bd valid: part 2 */
140 vld_u8 = svtbl_u8(svreinterpret_u8_u32(vld2),
141 svreinterpret_u8_s8(GEN_VLD_U8_ZIP_INDEX));
142 vld_clz = svnot_u64_z(PG64_64BIT, svreinterpret_u64_u8(vld_u8));
143 vld_clz = svclz_u64_z(PG64_64BIT, vld_clz);
144 svst1_u64(PG64_64BIT, &bd_valid_num, vld_clz);
145 bd_valid_num /= HNS3_UINT8_BIT;
147 /* load 4 more mbuf pointer */
148 mbp2st = svld1_u64(PG64_256BIT, (uint64_t *)&sw_ring[pos + 4]);
150 /* use offset to control below data load oper ordering */
151 offset = rxq->offset_table[bd_valid_num];
152 rxdp2 = rxdp + offset;
154 /* store 4 mbuf pointer into rx_pkts */
155 svst1_u64(PG64_256BIT, (uint64_t *)&rx_pkts[pos], mbp1st);
157 /* load key field to vector reg */
158 l234 = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
159 svindex_u32(BD_FIELD_L234_OFFSET, BD_SIZE));
160 ol = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
161 svindex_u32(BD_FIELD_OL_OFFSET, BD_SIZE));
163 /* store 4 mbuf pointer into rx_pkts again */
164 svst1_u64(PG64_256BIT, (uint64_t *)&rx_pkts[pos + 4], mbp2st);
166 /* load datalen, pktlen and rss_hash */
167 xlen = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
168 svindex_u32(BD_FIELD_XLEN_OFFSET, BD_SIZE));
169 rss = svld1_gather_u32offset_u32(pg32, (uint32_t *)rxdp2,
170 svindex_u32(BD_FIELD_RSS_OFFSET, BD_SIZE));
172 /* store key field to stash buffer */
173 svst1_u32(pg32, (uint32_t *)key_field.l234_info, l234);
174 svst1_u32(pg32, (uint32_t *)key_field.bd_base_info, vld);
175 svst1_u32(pg32, (uint32_t *)key_field.ol_info, ol);
177 /* sub crc_len for pkt_len and data_len */
178 xlen = svreinterpret_u32_u16(svsub_n_u16_z(PG16_256BIT,
179 svreinterpret_u16_u32(xlen), rxq->crc_len));
181 /* init mbuf_initializer */
182 mbuf_init = svdup_n_u64(rxq->mbuf_initializer);
184 /* extract datalen, pktlen and rss from xlen and rss */
185 xlen1st = svreinterpret_u64_u16(
186 svtbl_u16(svreinterpret_u16_u32(xlen), xlen_tbl1));
187 xlen2st = svreinterpret_u64_u16(
188 svtbl_u16(svreinterpret_u16_u32(xlen), xlen_tbl2));
189 rss1st = svreinterpret_u64_u32(
190 svtbl_u32(svreinterpret_u32_u32(rss), rss_tbl1));
191 rss2st = svreinterpret_u64_u32(
192 svtbl_u32(svreinterpret_u32_u32(rss), rss_tbl2));
194 /* save mbuf_initializer */
195 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp1st,
196 offsetof(struct rte_mbuf, rearm_data), mbuf_init);
197 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp2st,
198 offsetof(struct rte_mbuf, rearm_data), mbuf_init);
200 /* save datalen and pktlen and rss */
201 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp1st,
202 offsetof(struct rte_mbuf, pkt_len), xlen1st);
203 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp1st,
204 offsetof(struct rte_mbuf, hash.rss), rss1st);
205 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp2st,
206 offsetof(struct rte_mbuf, pkt_len), xlen2st);
207 svst1_scatter_u64base_offset_u64(PG64_256BIT, mbp2st,
208 offsetof(struct rte_mbuf, hash.rss), rss2st);
210 rte_prefetch_non_temporal(rxdp +
211 HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
213 parse_retcode = hns3_desc_parse_field_sve(rxq, &rx_pkts[pos],
214 &key_field, bd_valid_num);
215 if (unlikely(parse_retcode))
216 (*bd_err_mask) |= ((uint64_t)parse_retcode) << pos;
218 hns3_rx_prefetch_mbuf_sve(&sw_ring[pos +
219 HNS3_SVE_DEFAULT_DESCS_PER_LOOP]);
221 nb_rx += bd_valid_num;
222 if (unlikely(bd_valid_num < HNS3_SVE_DEFAULT_DESCS_PER_LOOP))
226 rxq->rx_rearm_nb += nb_rx;
227 rxq->next_to_use += nb_rx;
228 if (rxq->next_to_use >= rxq->nb_rx_desc)
229 rxq->next_to_use = 0;
235 hns3_rxq_rearm_mbuf_sve(struct hns3_rx_queue *rxq)
237 #define REARM_LOOP_STEP_NUM 4
238 struct hns3_entry *rxep = &rxq->sw_ring[rxq->rx_rearm_start];
239 struct hns3_desc *rxdp = rxq->rx_ring + rxq->rx_rearm_start;
240 struct hns3_entry *rxep_tmp = rxep;
243 if (unlikely(rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
244 HNS3_DEFAULT_RXQ_REARM_THRESH) < 0)) {
245 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
249 for (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,
250 rxep_tmp += REARM_LOOP_STEP_NUM) {
251 svuint64_t prf = svld1_u64(PG64_256BIT, (uint64_t *)rxep_tmp);
252 svprfd_gather_u64base(PG64_256BIT, prf, SV_PLDL1STRM);
255 for (i = 0; i < HNS3_DEFAULT_RXQ_REARM_THRESH; i += REARM_LOOP_STEP_NUM,
256 rxep += REARM_LOOP_STEP_NUM, rxdp += REARM_LOOP_STEP_NUM) {
257 uint64_t iova[REARM_LOOP_STEP_NUM];
258 iova[0] = rxep[0].mbuf->buf_iova;
259 iova[1] = rxep[1].mbuf->buf_iova;
260 iova[2] = rxep[2].mbuf->buf_iova;
261 iova[3] = rxep[3].mbuf->buf_iova;
262 svuint64_t siova = svld1_u64(PG64_256BIT, iova);
263 siova = svadd_n_u64_z(PG64_256BIT, siova, RTE_PKTMBUF_HEADROOM);
264 svuint64_t ol_base = svdup_n_u64(0);
265 svst1_scatter_u64offset_u64(PG64_256BIT,
266 (uint64_t *)&rxdp[0].addr,
267 svindex_u64(BD_FIELD_ADDR_OFFSET, BD_SIZE), siova);
268 svst1_scatter_u64offset_u64(PG64_256BIT,
269 (uint64_t *)&rxdp[0].addr,
270 svindex_u64(BD_FIELD_OL_OFFSET, BD_SIZE), ol_base);
273 rxq->rx_rearm_start += HNS3_DEFAULT_RXQ_REARM_THRESH;
274 if (rxq->rx_rearm_start >= rxq->nb_rx_desc)
275 rxq->rx_rearm_start = 0;
277 rxq->rx_rearm_nb -= HNS3_DEFAULT_RXQ_REARM_THRESH;
279 hns3_write_reg_opt(rxq->io_head_reg, HNS3_DEFAULT_RXQ_REARM_THRESH);
283 hns3_recv_pkts_vec_sve(void *__restrict rx_queue,
284 struct rte_mbuf **__restrict rx_pkts,
287 struct hns3_rx_queue *rxq = rx_queue;
288 struct hns3_desc *rxdp = &rxq->rx_ring[rxq->next_to_use];
289 uint64_t bd_err_mask; /* bit mask indicate whick pkts is error */
292 rte_prefetch_non_temporal(rxdp);
294 nb_pkts = RTE_MIN(nb_pkts, HNS3_DEFAULT_RX_BURST);
295 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, HNS3_SVE_DEFAULT_DESCS_PER_LOOP);
297 if (rxq->rx_rearm_nb > HNS3_DEFAULT_RXQ_REARM_THRESH)
298 hns3_rxq_rearm_mbuf_sve(rxq);
300 if (unlikely(!(rxdp->rx.bd_base_info &
301 rte_cpu_to_le_32(1u << HNS3_RXD_VLD_B))))
304 hns3_rx_prefetch_mbuf_sve(&rxq->sw_ring[rxq->next_to_use]);
307 nb_rx = hns3_recv_burst_vec_sve(rxq, rx_pkts, nb_pkts, &bd_err_mask);
308 if (unlikely(bd_err_mask))
309 nb_rx = hns3_rx_reassemble_pkts(rx_pkts, nb_rx, bd_err_mask);
315 hns3_tx_free_buffers_sve(struct hns3_tx_queue *txq)
317 #define HNS3_SVE_CHECK_DESCS_PER_LOOP 8
318 #define TX_VLD_U8_ZIP_INDEX svindex_u8(0, 4)
319 svbool_t pg32 = svwhilelt_b32(0, HNS3_SVE_CHECK_DESCS_PER_LOOP);
320 svuint32_t vld, vld2;
323 struct hns3_desc *tx_desc;
327 * All mbufs can be released only when the VLD bits of all
328 * descriptors in a batch are cleared.
330 /* do logical OR operation for all desc's valid field */
331 vld = svdup_n_u32(0);
332 tx_desc = &txq->tx_ring[txq->next_to_clean];
333 for (i = 0; i < txq->tx_rs_thresh; i += HNS3_SVE_CHECK_DESCS_PER_LOOP,
334 tx_desc += HNS3_SVE_CHECK_DESCS_PER_LOOP) {
335 vld2 = svld1_gather_u32offset_u32(pg32, (uint32_t *)tx_desc,
336 svindex_u32(BD_FIELD_VALID_OFFSET, BD_SIZE));
337 vld = svorr_u32_z(pg32, vld, vld2);
339 /* shift left and then right to get all valid bit */
340 vld = svlsl_n_u32_z(pg32, vld,
341 HNS3_UINT32_BIT - 1 - HNS3_TXD_VLD_B);
342 vld = svreinterpret_u32_s32(svasr_n_s32_z(pg32,
343 svreinterpret_s32_u32(vld), HNS3_UINT32_BIT - 1));
344 /* use tbl to compress 32bit-lane to 8bit-lane */
345 vld_u8 = svtbl_u8(svreinterpret_u8_u32(vld), TX_VLD_U8_ZIP_INDEX);
346 /* dump compressed 64bit to variable */
347 svst1_u64(PG64_64BIT, &vld_all, svreinterpret_u64_u8(vld_u8));
351 hns3_tx_bulk_free_buffers(txq);
355 hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq,
356 struct rte_mbuf **pkts,
359 #define DATA_OFF_LEN_VAL_MASK 0xFFFF
360 struct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];
361 struct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];
362 const uint64_t valid_bit = (BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B)) <<
364 svuint64_t base_addr, buf_iova, data_off, data_len, addr;
365 svuint64_t offsets = svindex_u64(0, BD_SIZE);
367 svbool_t pg = svwhilelt_b64_u32(i, nb_pkts);
370 base_addr = svld1_u64(pg, (uint64_t *)pkts);
371 /* calc mbuf's field buf_iova address */
372 buf_iova = svadd_n_u64_z(pg, base_addr,
373 offsetof(struct rte_mbuf, buf_iova));
374 /* calc mbuf's field data_off address */
375 data_off = svadd_n_u64_z(pg, base_addr,
376 offsetof(struct rte_mbuf, data_off));
377 /* calc mbuf's field data_len address */
378 data_len = svadd_n_u64_z(pg, base_addr,
379 offsetof(struct rte_mbuf, data_len));
380 /* store mbuf to tx_entry */
381 svst1_u64(pg, (uint64_t *)tx_entry, base_addr);
382 /* read pkts->buf_iova */
383 buf_iova = svld1_gather_u64base_u64(pg, buf_iova);
384 /* read pkts->data_off's 64bit val */
385 data_off = svld1_gather_u64base_u64(pg, data_off);
386 /* read pkts->data_len's 64bit val */
387 data_len = svld1_gather_u64base_u64(pg, data_len);
388 /* zero data_off high 48bit by svand ops */
389 data_off = svand_n_u64_z(pg, data_off, DATA_OFF_LEN_VAL_MASK);
390 /* zero data_len high 48bit by svand ops */
391 data_len = svand_n_u64_z(pg, data_len, DATA_OFF_LEN_VAL_MASK);
392 /* calc mbuf data region iova addr */
393 addr = svadd_u64_z(pg, buf_iova, data_off);
394 /* shift due data_len's offset is 2byte of BD's second 8byte */
395 data_len = svlsl_n_u64_z(pg, data_len, HNS3_UINT16_BIT);
396 /* save offset 0~7byte of every BD */
397 svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->addr,
399 /* save offset 8~15byte of every BD */
400 svst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.vlan_tag,
402 /* save offset 16~23byte of every BD */
403 svst1_scatter_u64offset_u64(pg,
404 (uint64_t *)&txdp->tx.outer_vlan_tag,
405 offsets, svdup_n_u64(0));
406 /* save offset 24~31byte of every BD */
407 svst1_scatter_u64offset_u64(pg,
408 (uint64_t *)&txdp->tx.paylen_fd_dop_ol4cs,
409 offsets, svdup_n_u64(valid_bit));
411 /* Increment bytes counter */
413 for (idx = 0; idx < svcntd(); idx++)
414 txq->basic_stats.bytes += pkts[idx]->pkt_len;
416 /* update index for next loop */
420 tx_entry += svcntd();
421 pg = svwhilelt_b64_u32(i, nb_pkts);
422 } while (svptest_any(svptrue_b64(), pg));
426 hns3_xmit_fixed_burst_vec_sve(void *__restrict tx_queue,
427 struct rte_mbuf **__restrict tx_pkts,
430 struct hns3_tx_queue *txq = (struct hns3_tx_queue *)tx_queue;
433 if (txq->tx_bd_ready < txq->tx_free_thresh)
434 hns3_tx_free_buffers_sve(txq);
436 nb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);
437 if (unlikely(nb_pkts == 0)) {
438 txq->dfx_stats.queue_full_cnt++;
442 if (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {
443 nb_tx = txq->nb_tx_desc - txq->next_to_use;
444 hns3_tx_fill_hw_ring_sve(txq, tx_pkts, nb_tx);
445 txq->next_to_use = 0;
448 hns3_tx_fill_hw_ring_sve(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);
449 txq->next_to_use += nb_pkts - nb_tx;
451 txq->tx_bd_ready -= nb_pkts;
452 hns3_write_reg_opt(txq->io_tail_reg, nb_pkts);
458 hns3_xmit_pkts_vec_sve(void *tx_queue,
459 struct rte_mbuf **tx_pkts,
462 struct hns3_tx_queue *txq = (struct hns3_tx_queue *)tx_queue;
463 uint16_t ret, new_burst;
467 new_burst = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
468 ret = hns3_xmit_fixed_burst_vec_sve(tx_queue, &tx_pkts[nb_tx],