drivers/net/i40e/base/i40e_common.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #include "i40e_type.h"
   6 #include "i40e_adminq.h"
   7 #include "i40e_prototype.h"
   8 #include "virtchnl.h"
   9
  10 /**
  11  * i40e_set_mac_type - Sets MAC type
  12  * @hw: pointer to the HW structure
  13  *
  14  * This function sets the mac type of the adapter based on the
  15  * vendor ID and device ID stored in the hw structure.
  16  **/
  17 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  18 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  19 #else
  20 STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
  21 #endif
  22 {
  23         enum i40e_status_code status = I40E_SUCCESS;
  24
  25         DEBUGFUNC("i40e_set_mac_type\n");
  26
  27         if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
  28                 switch (hw->device_id) {
  29                 case I40E_DEV_ID_SFP_XL710:
  30                 case I40E_DEV_ID_QEMU:
  31                 case I40E_DEV_ID_KX_B:
  32                 case I40E_DEV_ID_KX_C:
  33                 case I40E_DEV_ID_QSFP_A:
  34                 case I40E_DEV_ID_QSFP_B:
  35                 case I40E_DEV_ID_QSFP_C:
  36                 case I40E_DEV_ID_10G_BASE_T:
  37                 case I40E_DEV_ID_10G_BASE_T4:
  38 #ifdef CARLSVILLE_HW
  39                 case I40E_DEV_ID_10G_BASE_T_BC:
  40 #endif
  41                 case I40E_DEV_ID_20G_KR2:
  42                 case I40E_DEV_ID_20G_KR2_A:
  43                 case I40E_DEV_ID_25G_B:
  44                 case I40E_DEV_ID_25G_SFP28:
  45                 case I40E_DEV_ID_X710_N3000:
  46                 case I40E_DEV_ID_XXV710_N3000:
  47                         hw->mac.type = I40E_MAC_XL710;
  48                         break;
  49 #ifdef X722_A0_SUPPORT
  50                 case I40E_DEV_ID_X722_A0:
  51 #endif
  52                 case I40E_DEV_ID_KX_X722:
  53                 case I40E_DEV_ID_QSFP_X722:
  54                 case I40E_DEV_ID_SFP_X722:
  55                 case I40E_DEV_ID_1G_BASE_T_X722:
  56                 case I40E_DEV_ID_10G_BASE_T_X722:
  57                 case I40E_DEV_ID_SFP_I_X722:
  58                         hw->mac.type = I40E_MAC_X722;
  59                         break;
  60 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  61                 case I40E_DEV_ID_X722_VF:
  62 #ifdef X722_A0_SUPPORT
  63                 case I40E_DEV_ID_X722_A0_VF:
  64 #endif
  65                         hw->mac.type = I40E_MAC_X722_VF;
  66                         break;
  67 #endif /* INTEGRATED_VF || VF_DRIVER */
  68 #if defined(INTEGRATED_VF) || defined(VF_DRIVER)
  69                 case I40E_DEV_ID_VF:
  70                 case I40E_DEV_ID_VF_HV:
  71                 case I40E_DEV_ID_ADAPTIVE_VF:
  72                         hw->mac.type = I40E_MAC_VF;
  73                         break;
  74 #endif
  75                 default:
  76                         hw->mac.type = I40E_MAC_GENERIC;
  77                         break;
  78                 }
  79         } else {
  80                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  81         }
  82
  83         DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
  84                   hw->mac.type, status);
  85         return status;
  86 }
  87
  88 /**
  89  * i40e_aq_str - convert AQ err code to a string
  90  * @hw: pointer to the HW structure
  91  * @aq_err: the AQ error code to convert
  92  **/
  93 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  94 {
  95         switch (aq_err) {
  96         case I40E_AQ_RC_OK:
  97                 return "OK";
  98         case I40E_AQ_RC_EPERM:
  99                 return "I40E_AQ_RC_EPERM";
 100         case I40E_AQ_RC_ENOENT:
 101                 return "I40E_AQ_RC_ENOENT";
 102         case I40E_AQ_RC_ESRCH:
 103                 return "I40E_AQ_RC_ESRCH";
 104         case I40E_AQ_RC_EINTR:
 105                 return "I40E_AQ_RC_EINTR";
 106         case I40E_AQ_RC_EIO:
 107                 return "I40E_AQ_RC_EIO";
 108         case I40E_AQ_RC_ENXIO:
 109                 return "I40E_AQ_RC_ENXIO";
 110         case I40E_AQ_RC_E2BIG:
 111                 return "I40E_AQ_RC_E2BIG";
 112         case I40E_AQ_RC_EAGAIN:
 113                 return "I40E_AQ_RC_EAGAIN";
 114         case I40E_AQ_RC_ENOMEM:
 115                 return "I40E_AQ_RC_ENOMEM";
 116         case I40E_AQ_RC_EACCES:
 117                 return "I40E_AQ_RC_EACCES";
 118         case I40E_AQ_RC_EFAULT:
 119                 return "I40E_AQ_RC_EFAULT";
 120         case I40E_AQ_RC_EBUSY:
 121                 return "I40E_AQ_RC_EBUSY";
 122         case I40E_AQ_RC_EEXIST:
 123                 return "I40E_AQ_RC_EEXIST";
 124         case I40E_AQ_RC_EINVAL:
 125                 return "I40E_AQ_RC_EINVAL";
 126         case I40E_AQ_RC_ENOTTY:
 127                 return "I40E_AQ_RC_ENOTTY";
 128         case I40E_AQ_RC_ENOSPC:
 129                 return "I40E_AQ_RC_ENOSPC";
 130         case I40E_AQ_RC_ENOSYS:
 131                 return "I40E_AQ_RC_ENOSYS";
 132         case I40E_AQ_RC_ERANGE:
 133                 return "I40E_AQ_RC_ERANGE";
 134         case I40E_AQ_RC_EFLUSHED:
 135                 return "I40E_AQ_RC_EFLUSHED";
 136         case I40E_AQ_RC_BAD_ADDR:
 137                 return "I40E_AQ_RC_BAD_ADDR";
 138         case I40E_AQ_RC_EMODE:
 139                 return "I40E_AQ_RC_EMODE";
 140         case I40E_AQ_RC_EFBIG:
 141                 return "I40E_AQ_RC_EFBIG";
 142         }
 143
 144         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 145         return hw->err_str;
 146 }
 147
 148 /**
 149  * i40e_stat_str - convert status err code to a string
 150  * @hw: pointer to the HW structure
 151  * @stat_err: the status error code to convert
 152  **/
 153 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
 154 {
 155         switch (stat_err) {
 156         case I40E_SUCCESS:
 157                 return "OK";
 158         case I40E_ERR_NVM:
 159                 return "I40E_ERR_NVM";
 160         case I40E_ERR_NVM_CHECKSUM:
 161                 return "I40E_ERR_NVM_CHECKSUM";
 162         case I40E_ERR_PHY:
 163                 return "I40E_ERR_PHY";
 164         case I40E_ERR_CONFIG:
 165                 return "I40E_ERR_CONFIG";
 166         case I40E_ERR_PARAM:
 167                 return "I40E_ERR_PARAM";
 168         case I40E_ERR_MAC_TYPE:
 169                 return "I40E_ERR_MAC_TYPE";
 170         case I40E_ERR_UNKNOWN_PHY:
 171                 return "I40E_ERR_UNKNOWN_PHY";
 172         case I40E_ERR_LINK_SETUP:
 173                 return "I40E_ERR_LINK_SETUP";
 174         case I40E_ERR_ADAPTER_STOPPED:
 175                 return "I40E_ERR_ADAPTER_STOPPED";
 176         case I40E_ERR_INVALID_MAC_ADDR:
 177                 return "I40E_ERR_INVALID_MAC_ADDR";
 178         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 179                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 180         case I40E_ERR_MASTER_REQUESTS_PENDING:
 181                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 182         case I40E_ERR_INVALID_LINK_SETTINGS:
 183                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 184         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 185                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 186         case I40E_ERR_RESET_FAILED:
 187                 return "I40E_ERR_RESET_FAILED";
 188         case I40E_ERR_SWFW_SYNC:
 189                 return "I40E_ERR_SWFW_SYNC";
 190         case I40E_ERR_NO_AVAILABLE_VSI:
 191                 return "I40E_ERR_NO_AVAILABLE_VSI";
 192         case I40E_ERR_NO_MEMORY:
 193                 return "I40E_ERR_NO_MEMORY";
 194         case I40E_ERR_BAD_PTR:
 195                 return "I40E_ERR_BAD_PTR";
 196         case I40E_ERR_RING_FULL:
 197                 return "I40E_ERR_RING_FULL";
 198         case I40E_ERR_INVALID_PD_ID:
 199                 return "I40E_ERR_INVALID_PD_ID";
 200         case I40E_ERR_INVALID_QP_ID:
 201                 return "I40E_ERR_INVALID_QP_ID";
 202         case I40E_ERR_INVALID_CQ_ID:
 203                 return "I40E_ERR_INVALID_CQ_ID";
 204         case I40E_ERR_INVALID_CEQ_ID:
 205                 return "I40E_ERR_INVALID_CEQ_ID";
 206         case I40E_ERR_INVALID_AEQ_ID:
 207                 return "I40E_ERR_INVALID_AEQ_ID";
 208         case I40E_ERR_INVALID_SIZE:
 209                 return "I40E_ERR_INVALID_SIZE";
 210         case I40E_ERR_INVALID_ARP_INDEX:
 211                 return "I40E_ERR_INVALID_ARP_INDEX";
 212         case I40E_ERR_INVALID_FPM_FUNC_ID:
 213                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 214         case I40E_ERR_QP_INVALID_MSG_SIZE:
 215                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 216         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 217                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 218         case I40E_ERR_INVALID_FRAG_COUNT:
 219                 return "I40E_ERR_INVALID_FRAG_COUNT";
 220         case I40E_ERR_QUEUE_EMPTY:
 221                 return "I40E_ERR_QUEUE_EMPTY";
 222         case I40E_ERR_INVALID_ALIGNMENT:
 223                 return "I40E_ERR_INVALID_ALIGNMENT";
 224         case I40E_ERR_FLUSHED_QUEUE:
 225                 return "I40E_ERR_FLUSHED_QUEUE";
 226         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 227                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 228         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 229                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 230         case I40E_ERR_TIMEOUT:
 231                 return "I40E_ERR_TIMEOUT";
 232         case I40E_ERR_OPCODE_MISMATCH:
 233                 return "I40E_ERR_OPCODE_MISMATCH";
 234         case I40E_ERR_CQP_COMPL_ERROR:
 235                 return "I40E_ERR_CQP_COMPL_ERROR";
 236         case I40E_ERR_INVALID_VF_ID:
 237                 return "I40E_ERR_INVALID_VF_ID";
 238         case I40E_ERR_INVALID_HMCFN_ID:
 239                 return "I40E_ERR_INVALID_HMCFN_ID";
 240         case I40E_ERR_BACKING_PAGE_ERROR:
 241                 return "I40E_ERR_BACKING_PAGE_ERROR";
 242         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 243                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 244         case I40E_ERR_INVALID_PBLE_INDEX:
 245                 return "I40E_ERR_INVALID_PBLE_INDEX";
 246         case I40E_ERR_INVALID_SD_INDEX:
 247                 return "I40E_ERR_INVALID_SD_INDEX";
 248         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 249                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 250         case I40E_ERR_INVALID_SD_TYPE:
 251                 return "I40E_ERR_INVALID_SD_TYPE";
 252         case I40E_ERR_MEMCPY_FAILED:
 253                 return "I40E_ERR_MEMCPY_FAILED";
 254         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 255                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 256         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 257                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 258         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 259                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 260         case I40E_ERR_SRQ_ENABLED:
 261                 return "I40E_ERR_SRQ_ENABLED";
 262         case I40E_ERR_ADMIN_QUEUE_ERROR:
 263                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 264         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 265                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 266         case I40E_ERR_BUF_TOO_SHORT:
 267                 return "I40E_ERR_BUF_TOO_SHORT";
 268         case I40E_ERR_ADMIN_QUEUE_FULL:
 269                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 270         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 271                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 272         case I40E_ERR_BAD_IWARP_CQE:
 273                 return "I40E_ERR_BAD_IWARP_CQE";
 274         case I40E_ERR_NVM_BLANK_MODE:
 275                 return "I40E_ERR_NVM_BLANK_MODE";
 276         case I40E_ERR_NOT_IMPLEMENTED:
 277                 return "I40E_ERR_NOT_IMPLEMENTED";
 278         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 279                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 280         case I40E_ERR_DIAG_TEST_FAILED:
 281                 return "I40E_ERR_DIAG_TEST_FAILED";
 282         case I40E_ERR_NOT_READY:
 283                 return "I40E_ERR_NOT_READY";
 284         case I40E_NOT_SUPPORTED:
 285                 return "I40E_NOT_SUPPORTED";
 286         case I40E_ERR_FIRMWARE_API_VERSION:
 287                 return "I40E_ERR_FIRMWARE_API_VERSION";
 288         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 289                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 290         }
 291
 292         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 293         return hw->err_str;
 294 }
 295
 296 /**
 297  * i40e_debug_aq
 298  * @hw: debug mask related to admin queue
 299  * @mask: debug mask
 300  * @desc: pointer to admin queue descriptor
 301  * @buffer: pointer to command buffer
 302  * @buf_len: max length of buffer
 303  *
 304  * Dumps debug log about adminq command with descriptor contents.
 305  **/
 306 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 307                    void *buffer, u16 buf_len)
 308 {
 309         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 310         u8 *buf = (u8 *)buffer;
 311         u16 len;
 312         u16 i = 0;
 313
 314         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 315                 return;
 316
 317         len = LE16_TO_CPU(aq_desc->datalen);
 318
 319         i40e_debug(hw, mask,
 320                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 321                    LE16_TO_CPU(aq_desc->opcode),
 322                    LE16_TO_CPU(aq_desc->flags),
 323                    LE16_TO_CPU(aq_desc->datalen),
 324                    LE16_TO_CPU(aq_desc->retval));
 325         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 326                    LE32_TO_CPU(aq_desc->cookie_high),
 327                    LE32_TO_CPU(aq_desc->cookie_low));
 328         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 329                    LE32_TO_CPU(aq_desc->params.internal.param0),
 330                    LE32_TO_CPU(aq_desc->params.internal.param1));
 331         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 332                    LE32_TO_CPU(aq_desc->params.external.addr_high),
 333                    LE32_TO_CPU(aq_desc->params.external.addr_low));
 334
 335         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 336                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 337                 if (buf_len < len)
 338                         len = buf_len;
 339                 /* write the full 16-byte chunks */
 340                 for (i = 0; i < (len - 16); i += 16)
 341                         i40e_debug(hw, mask,
 342                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 343                                    i, buf[i], buf[i+1], buf[i+2], buf[i+3],
 344                                    buf[i+4], buf[i+5], buf[i+6], buf[i+7],
 345                                    buf[i+8], buf[i+9], buf[i+10], buf[i+11],
 346                                    buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
 347                 /* the most we could have left is 16 bytes, pad with zeros */
 348                 if (i < len) {
 349                         char d_buf[16];
 350                         int j, i_sav;
 351
 352                         i_sav = i;
 353                         memset(d_buf, 0, sizeof(d_buf));
 354                         for (j = 0; i < len; j++, i++)
 355                                 d_buf[j] = buf[i];
 356                         i40e_debug(hw, mask,
 357                                    "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
 358                                    i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
 359                                    d_buf[4], d_buf[5], d_buf[6], d_buf[7],
 360                                    d_buf[8], d_buf[9], d_buf[10], d_buf[11],
 361                                    d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
 362                 }
 363         }
 364 }
 365
 366 /**
 367  * i40e_check_asq_alive
 368  * @hw: pointer to the hw struct
 369  *
 370  * Returns true if Queue is enabled else false.
 371  **/
 372 bool i40e_check_asq_alive(struct i40e_hw *hw)
 373 {
 374         if (hw->aq.asq.len)
 375 #ifdef PF_DRIVER
 376 #ifdef INTEGRATED_VF
 377                 if (!i40e_is_vf(hw))
 378                         return !!(rd32(hw, hw->aq.asq.len) &
 379                                 I40E_PF_ATQLEN_ATQENABLE_MASK);
 380 #else
 381                 return !!(rd32(hw, hw->aq.asq.len) &
 382                         I40E_PF_ATQLEN_ATQENABLE_MASK);
 383 #endif /* INTEGRATED_VF */
 384 #endif /* PF_DRIVER */
 385 #ifdef VF_DRIVER
 386 #ifdef INTEGRATED_VF
 387                 if (i40e_is_vf(hw))
 388                         return !!(rd32(hw, hw->aq.asq.len) &
 389                                 I40E_VF_ATQLEN1_ATQENABLE_MASK);
 390 #else
 391                 return !!(rd32(hw, hw->aq.asq.len) &
 392                         I40E_VF_ATQLEN1_ATQENABLE_MASK);
 393 #endif /* INTEGRATED_VF */
 394 #endif /* VF_DRIVER */
 395         return false;
 396 }
 397
 398 /**
 399  * i40e_aq_queue_shutdown
 400  * @hw: pointer to the hw struct
 401  * @unloading: is the driver unloading itself
 402  *
 403  * Tell the Firmware that we're shutting down the AdminQ and whether
 404  * or not the driver is unloading as well.
 405  **/
 406 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
 407                                              bool unloading)
 408 {
 409         struct i40e_aq_desc desc;
 410         struct i40e_aqc_queue_shutdown *cmd =
 411                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 412         enum i40e_status_code status;
 413
 414         i40e_fill_default_direct_cmd_desc(&desc,
 415                                           i40e_aqc_opc_queue_shutdown);
 416
 417         if (unloading)
 418                 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
 419         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 420
 421         return status;
 422 }
 423
 424 /**
 425  * i40e_aq_get_set_rss_lut
 426  * @hw: pointer to the hardware structure
 427  * @vsi_id: vsi fw index
 428  * @pf_lut: for PF table set true, for VSI table set false
 429  * @lut: pointer to the lut buffer provided by the caller
 430  * @lut_size: size of the lut buffer
 431  * @set: set true to set the table, false to get the table
 432  *
 433  * Internal function to get or set RSS look up table
 434  **/
 435 STATIC enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 436                                                      u16 vsi_id, bool pf_lut,
 437                                                      u8 *lut, u16 lut_size,
 438                                                      bool set)
 439 {
 440         enum i40e_status_code status;
 441         struct i40e_aq_desc desc;
 442         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 443                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 444
 445         if (set)
 446                 i40e_fill_default_direct_cmd_desc(&desc,
 447                                                   i40e_aqc_opc_set_rss_lut);
 448         else
 449                 i40e_fill_default_direct_cmd_desc(&desc,
 450                                                   i40e_aqc_opc_get_rss_lut);
 451
 452         /* Indirect command */
 453         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 454         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 455
 456         cmd_resp->vsi_id =
 457                         CPU_TO_LE16((u16)((vsi_id <<
 458                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 459                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 460         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 461
 462         if (pf_lut)
 463                 cmd_resp->flags |= CPU_TO_LE16((u16)
 464                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 465                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 466                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 467         else
 468                 cmd_resp->flags |= CPU_TO_LE16((u16)
 469                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 470                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 471                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 472
 473         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 474
 475         return status;
 476 }
 477
 478 /**
 479  * i40e_aq_get_rss_lut
 480  * @hw: pointer to the hardware structure
 481  * @vsi_id: vsi fw index
 482  * @pf_lut: for PF table set true, for VSI table set false
 483  * @lut: pointer to the lut buffer provided by the caller
 484  * @lut_size: size of the lut buffer
 485  *
 486  * get the RSS lookup table, PF or VSI type
 487  **/
 488 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 489                                           bool pf_lut, u8 *lut, u16 lut_size)
 490 {
 491         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 492                                        false);
 493 }
 494
 495 /**
 496  * i40e_aq_set_rss_lut
 497  * @hw: pointer to the hardware structure
 498  * @vsi_id: vsi fw index
 499  * @pf_lut: for PF table set true, for VSI table set false
 500  * @lut: pointer to the lut buffer provided by the caller
 501  * @lut_size: size of the lut buffer
 502  *
 503  * set the RSS lookup table, PF or VSI type
 504  **/
 505 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 506                                           bool pf_lut, u8 *lut, u16 lut_size)
 507 {
 508         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 509 }
 510
 511 /**
 512  * i40e_aq_get_set_rss_key
 513  * @hw: pointer to the hw struct
 514  * @vsi_id: vsi fw index
 515  * @key: pointer to key info struct
 516  * @set: set true to set the key, false to get the key
 517  *
 518  * get the RSS key per VSI
 519  **/
 520 STATIC enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 521                                       u16 vsi_id,
 522                                       struct i40e_aqc_get_set_rss_key_data *key,
 523                                       bool set)
 524 {
 525         enum i40e_status_code status;
 526         struct i40e_aq_desc desc;
 527         struct i40e_aqc_get_set_rss_key *cmd_resp =
 528                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 529         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 530
 531         if (set)
 532                 i40e_fill_default_direct_cmd_desc(&desc,
 533                                                   i40e_aqc_opc_set_rss_key);
 534         else
 535                 i40e_fill_default_direct_cmd_desc(&desc,
 536                                                   i40e_aqc_opc_get_rss_key);
 537
 538         /* Indirect command */
 539         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
 540         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
 541
 542         cmd_resp->vsi_id =
 543                         CPU_TO_LE16((u16)((vsi_id <<
 544                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 545                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 546         cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 547
 548         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 549
 550         return status;
 551 }
 552
 553 /**
 554  * i40e_aq_get_rss_key
 555  * @hw: pointer to the hw struct
 556  * @vsi_id: vsi fw index
 557  * @key: pointer to key info struct
 558  *
 559  **/
 560 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 561                                       u16 vsi_id,
 562                                       struct i40e_aqc_get_set_rss_key_data *key)
 563 {
 564         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 565 }
 566
 567 /**
 568  * i40e_aq_set_rss_key
 569  * @hw: pointer to the hw struct
 570  * @vsi_id: vsi fw index
 571  * @key: pointer to key info struct
 572  *
 573  * set the RSS key per VSI
 574  **/
 575 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 576                                       u16 vsi_id,
 577                                       struct i40e_aqc_get_set_rss_key_data *key)
 578 {
 579         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 580 }
 581
 582 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 583  * hardware to a bit-field that can be used by SW to more easily determine the
 584  * packet type.
 585  *
 586  * Macros are used to shorten the table lines and make this table human
 587  * readable.
 588  *
 589  * We store the PTYPE in the top byte of the bit field - this is just so that
 590  * we can check that the table doesn't have a row missing, as the index into
 591  * the table should be the PTYPE.
 592  *
 593  * Typical work flow:
 594  *
 595  * IF NOT i40e_ptype_lookup[ptype].known
 596  * THEN
 597  *      Packet is unknown
 598  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 599  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 600  * ELSE
 601  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 602  * ENDIF
 603  */
 604
 605 /* macro to make the table lines short */
 606 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 607         {       PTYPE, \
 608                 1, \
 609                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 610                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 611                 I40E_RX_PTYPE_##OUTER_FRAG, \
 612                 I40E_RX_PTYPE_TUNNEL_##T, \
 613                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 614                 I40E_RX_PTYPE_##TEF, \
 615                 I40E_RX_PTYPE_INNER_PROT_##I, \
 616                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 617
 618 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 619                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 620
 621 /* shorter macros makes the table fit but are terse */
 622 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 623 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 624 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 625
 626 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 627 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 628         /* L2 Packet types */
 629         I40E_PTT_UNUSED_ENTRY(0),
 630         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 631         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 632         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 633         I40E_PTT_UNUSED_ENTRY(4),
 634         I40E_PTT_UNUSED_ENTRY(5),
 635         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 636         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 637         I40E_PTT_UNUSED_ENTRY(8),
 638         I40E_PTT_UNUSED_ENTRY(9),
 639         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 640         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 641         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 642         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 643         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 644         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 645         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 646         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 647         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 648         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 649         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 650         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 651
 652         /* Non Tunneled IPv4 */
 653         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 654         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 655         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 656         I40E_PTT_UNUSED_ENTRY(25),
 657         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 658         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 659         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 660
 661         /* IPv4 --> IPv4 */
 662         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 663         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 664         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 665         I40E_PTT_UNUSED_ENTRY(32),
 666         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 667         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 668         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 669
 670         /* IPv4 --> IPv6 */
 671         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 672         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 673         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 674         I40E_PTT_UNUSED_ENTRY(39),
 675         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 676         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 677         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 678
 679         /* IPv4 --> GRE/NAT */
 680         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 681
 682         /* IPv4 --> GRE/NAT --> IPv4 */
 683         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 684         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 685         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 686         I40E_PTT_UNUSED_ENTRY(47),
 687         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 688         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 689         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 690
 691         /* IPv4 --> GRE/NAT --> IPv6 */
 692         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 693         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 694         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 695         I40E_PTT_UNUSED_ENTRY(54),
 696         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 697         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 698         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 699
 700         /* IPv4 --> GRE/NAT --> MAC */
 701         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 702
 703         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 704         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 705         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 706         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 707         I40E_PTT_UNUSED_ENTRY(62),
 708         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 709         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 710         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 711
 712         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 713         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 714         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 715         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 716         I40E_PTT_UNUSED_ENTRY(69),
 717         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 718         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 719         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 720
 721         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 722         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 723
 724         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 725         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 726         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 727         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 728         I40E_PTT_UNUSED_ENTRY(77),
 729         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 730         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 731         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 732
 733         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 734         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 735         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 736         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 737         I40E_PTT_UNUSED_ENTRY(84),
 738         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 739         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 740         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 741
 742         /* Non Tunneled IPv6 */
 743         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 744         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 745         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 746         I40E_PTT_UNUSED_ENTRY(91),
 747         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 748         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 749         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 750
 751         /* IPv6 --> IPv4 */
 752         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 753         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 754         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 755         I40E_PTT_UNUSED_ENTRY(98),
 756         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 757         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 758         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 759
 760         /* IPv6 --> IPv6 */
 761         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 762         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 763         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 764         I40E_PTT_UNUSED_ENTRY(105),
 765         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 766         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 767         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 768
 769         /* IPv6 --> GRE/NAT */
 770         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 771
 772         /* IPv6 --> GRE/NAT -> IPv4 */
 773         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 774         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 775         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 776         I40E_PTT_UNUSED_ENTRY(113),
 777         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 778         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 779         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 780
 781         /* IPv6 --> GRE/NAT -> IPv6 */
 782         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 783         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 784         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 785         I40E_PTT_UNUSED_ENTRY(120),
 786         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 787         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 788         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 789
 790         /* IPv6 --> GRE/NAT -> MAC */
 791         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 792
 793         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 794         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 795         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 796         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 797         I40E_PTT_UNUSED_ENTRY(128),
 798         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 799         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 800         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 801
 802         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 803         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 804         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 805         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 806         I40E_PTT_UNUSED_ENTRY(135),
 807         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 808         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 809         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 810
 811         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 812         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 813
 814         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 815         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 816         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 817         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 818         I40E_PTT_UNUSED_ENTRY(143),
 819         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 820         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 821         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 822
 823         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 824         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 825         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 826         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 827         I40E_PTT_UNUSED_ENTRY(150),
 828         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 829         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 830         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 831
 832         /* unused entries */
 833         I40E_PTT_UNUSED_ENTRY(154),
 834         I40E_PTT_UNUSED_ENTRY(155),
 835         I40E_PTT_UNUSED_ENTRY(156),
 836         I40E_PTT_UNUSED_ENTRY(157),
 837         I40E_PTT_UNUSED_ENTRY(158),
 838         I40E_PTT_UNUSED_ENTRY(159),
 839
 840         I40E_PTT_UNUSED_ENTRY(160),
 841         I40E_PTT_UNUSED_ENTRY(161),
 842         I40E_PTT_UNUSED_ENTRY(162),
 843         I40E_PTT_UNUSED_ENTRY(163),
 844         I40E_PTT_UNUSED_ENTRY(164),
 845         I40E_PTT_UNUSED_ENTRY(165),
 846         I40E_PTT_UNUSED_ENTRY(166),
 847         I40E_PTT_UNUSED_ENTRY(167),
 848         I40E_PTT_UNUSED_ENTRY(168),
 849         I40E_PTT_UNUSED_ENTRY(169),
 850
 851         I40E_PTT_UNUSED_ENTRY(170),
 852         I40E_PTT_UNUSED_ENTRY(171),
 853         I40E_PTT_UNUSED_ENTRY(172),
 854         I40E_PTT_UNUSED_ENTRY(173),
 855         I40E_PTT_UNUSED_ENTRY(174),
 856         I40E_PTT_UNUSED_ENTRY(175),
 857         I40E_PTT_UNUSED_ENTRY(176),
 858         I40E_PTT_UNUSED_ENTRY(177),
 859         I40E_PTT_UNUSED_ENTRY(178),
 860         I40E_PTT_UNUSED_ENTRY(179),
 861
 862         I40E_PTT_UNUSED_ENTRY(180),
 863         I40E_PTT_UNUSED_ENTRY(181),
 864         I40E_PTT_UNUSED_ENTRY(182),
 865         I40E_PTT_UNUSED_ENTRY(183),
 866         I40E_PTT_UNUSED_ENTRY(184),
 867         I40E_PTT_UNUSED_ENTRY(185),
 868         I40E_PTT_UNUSED_ENTRY(186),
 869         I40E_PTT_UNUSED_ENTRY(187),
 870         I40E_PTT_UNUSED_ENTRY(188),
 871         I40E_PTT_UNUSED_ENTRY(189),
 872
 873         I40E_PTT_UNUSED_ENTRY(190),
 874         I40E_PTT_UNUSED_ENTRY(191),
 875         I40E_PTT_UNUSED_ENTRY(192),
 876         I40E_PTT_UNUSED_ENTRY(193),
 877         I40E_PTT_UNUSED_ENTRY(194),
 878         I40E_PTT_UNUSED_ENTRY(195),
 879         I40E_PTT_UNUSED_ENTRY(196),
 880         I40E_PTT_UNUSED_ENTRY(197),
 881         I40E_PTT_UNUSED_ENTRY(198),
 882         I40E_PTT_UNUSED_ENTRY(199),
 883
 884         I40E_PTT_UNUSED_ENTRY(200),
 885         I40E_PTT_UNUSED_ENTRY(201),
 886         I40E_PTT_UNUSED_ENTRY(202),
 887         I40E_PTT_UNUSED_ENTRY(203),
 888         I40E_PTT_UNUSED_ENTRY(204),
 889         I40E_PTT_UNUSED_ENTRY(205),
 890         I40E_PTT_UNUSED_ENTRY(206),
 891         I40E_PTT_UNUSED_ENTRY(207),
 892         I40E_PTT_UNUSED_ENTRY(208),
 893         I40E_PTT_UNUSED_ENTRY(209),
 894
 895         I40E_PTT_UNUSED_ENTRY(210),
 896         I40E_PTT_UNUSED_ENTRY(211),
 897         I40E_PTT_UNUSED_ENTRY(212),
 898         I40E_PTT_UNUSED_ENTRY(213),
 899         I40E_PTT_UNUSED_ENTRY(214),
 900         I40E_PTT_UNUSED_ENTRY(215),
 901         I40E_PTT_UNUSED_ENTRY(216),
 902         I40E_PTT_UNUSED_ENTRY(217),
 903         I40E_PTT_UNUSED_ENTRY(218),
 904         I40E_PTT_UNUSED_ENTRY(219),
 905
 906         I40E_PTT_UNUSED_ENTRY(220),
 907         I40E_PTT_UNUSED_ENTRY(221),
 908         I40E_PTT_UNUSED_ENTRY(222),
 909         I40E_PTT_UNUSED_ENTRY(223),
 910         I40E_PTT_UNUSED_ENTRY(224),
 911         I40E_PTT_UNUSED_ENTRY(225),
 912         I40E_PTT_UNUSED_ENTRY(226),
 913         I40E_PTT_UNUSED_ENTRY(227),
 914         I40E_PTT_UNUSED_ENTRY(228),
 915         I40E_PTT_UNUSED_ENTRY(229),
 916
 917         I40E_PTT_UNUSED_ENTRY(230),
 918         I40E_PTT_UNUSED_ENTRY(231),
 919         I40E_PTT_UNUSED_ENTRY(232),
 920         I40E_PTT_UNUSED_ENTRY(233),
 921         I40E_PTT_UNUSED_ENTRY(234),
 922         I40E_PTT_UNUSED_ENTRY(235),
 923         I40E_PTT_UNUSED_ENTRY(236),
 924         I40E_PTT_UNUSED_ENTRY(237),
 925         I40E_PTT_UNUSED_ENTRY(238),
 926         I40E_PTT_UNUSED_ENTRY(239),
 927
 928         I40E_PTT_UNUSED_ENTRY(240),
 929         I40E_PTT_UNUSED_ENTRY(241),
 930         I40E_PTT_UNUSED_ENTRY(242),
 931         I40E_PTT_UNUSED_ENTRY(243),
 932         I40E_PTT_UNUSED_ENTRY(244),
 933         I40E_PTT_UNUSED_ENTRY(245),
 934         I40E_PTT_UNUSED_ENTRY(246),
 935         I40E_PTT_UNUSED_ENTRY(247),
 936         I40E_PTT_UNUSED_ENTRY(248),
 937         I40E_PTT_UNUSED_ENTRY(249),
 938
 939         I40E_PTT_UNUSED_ENTRY(250),
 940         I40E_PTT_UNUSED_ENTRY(251),
 941         I40E_PTT_UNUSED_ENTRY(252),
 942         I40E_PTT_UNUSED_ENTRY(253),
 943         I40E_PTT_UNUSED_ENTRY(254),
 944         I40E_PTT_UNUSED_ENTRY(255)
 945 };
 946
 947
 948 /**
 949  * i40e_validate_mac_addr - Validate unicast MAC address
 950  * @mac_addr: pointer to MAC address
 951  *
 952  * Tests a MAC address to ensure it is a valid Individual Address
 953  **/
 954 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
 955 {
 956         enum i40e_status_code status = I40E_SUCCESS;
 957
 958         DEBUGFUNC("i40e_validate_mac_addr");
 959
 960         /* Broadcast addresses ARE multicast addresses
 961          * Make sure it is not a multicast address
 962          * Reject the zero address
 963          */
 964         if (I40E_IS_MULTICAST(mac_addr) ||
 965             (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
 966               mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
 967                 status = I40E_ERR_INVALID_MAC_ADDR;
 968
 969         return status;
 970 }
 971 #ifdef PF_DRIVER
 972
 973 /**
 974  * i40e_init_shared_code - Initialize the shared code
 975  * @hw: pointer to hardware structure
 976  *
 977  * This assigns the MAC type and PHY code and inits the NVM.
 978  * Does not touch the hardware. This function must be called prior to any
 979  * other function in the shared code. The i40e_hw structure should be
 980  * memset to 0 prior to calling this function.  The following fields in
 981  * hw structure should be filled in prior to calling this function:
 982  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 983  * subsystem_vendor_id, and revision_id
 984  **/
 985 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
 986 {
 987         enum i40e_status_code status = I40E_SUCCESS;
 988         u32 port, ari, func_rid;
 989
 990         DEBUGFUNC("i40e_init_shared_code");
 991
 992         i40e_set_mac_type(hw);
 993
 994         switch (hw->mac.type) {
 995         case I40E_MAC_XL710:
 996         case I40E_MAC_X722:
 997                 break;
 998         default:
 999                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1000         }
1001
1002         hw->phy.get_link_info = true;
1003
1004         /* Determine port number and PF number*/
1005         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1006                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1007         hw->port = (u8)port;
1008         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1009                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1010         func_rid = rd32(hw, I40E_PF_FUNC_RID);
1011         if (ari)
1012                 hw->pf_id = (u8)(func_rid & 0xff);
1013         else
1014                 hw->pf_id = (u8)(func_rid & 0x7);
1015
1016         if (hw->mac.type == I40E_MAC_X722)
1017                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1018                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1019
1020         status = i40e_init_nvm(hw);
1021         return status;
1022 }
1023
1024 /**
1025  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1026  * @hw: pointer to the hw struct
1027  * @flags: a return indicator of what addresses were added to the addr store
1028  * @addrs: the requestor's mac addr store
1029  * @cmd_details: pointer to command details structure or NULL
1030  **/
1031 STATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1032                                    u16 *flags,
1033                                    struct i40e_aqc_mac_address_read_data *addrs,
1034                                    struct i40e_asq_cmd_details *cmd_details)
1035 {
1036         struct i40e_aq_desc desc;
1037         struct i40e_aqc_mac_address_read *cmd_data =
1038                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1039         enum i40e_status_code status;
1040
1041         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1042         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1043
1044         status = i40e_asq_send_command(hw, &desc, addrs,
1045                                        sizeof(*addrs), cmd_details);
1046         *flags = LE16_TO_CPU(cmd_data->command_flags);
1047
1048         return status;
1049 }
1050
1051 /**
1052  * i40e_aq_mac_address_write - Change the MAC addresses
1053  * @hw: pointer to the hw struct
1054  * @flags: indicates which MAC to be written
1055  * @mac_addr: address to write
1056  * @cmd_details: pointer to command details structure or NULL
1057  **/
1058 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1059                                     u16 flags, u8 *mac_addr,
1060                                     struct i40e_asq_cmd_details *cmd_details)
1061 {
1062         struct i40e_aq_desc desc;
1063         struct i40e_aqc_mac_address_write *cmd_data =
1064                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1065         enum i40e_status_code status;
1066
1067         i40e_fill_default_direct_cmd_desc(&desc,
1068                                           i40e_aqc_opc_mac_address_write);
1069         cmd_data->command_flags = CPU_TO_LE16(flags);
1070         cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1071         cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1072                                         ((u32)mac_addr[3] << 16) |
1073                                         ((u32)mac_addr[4] << 8) |
1074                                         mac_addr[5]);
1075
1076         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1077
1078         return status;
1079 }
1080
1081 /**
1082  * i40e_get_mac_addr - get MAC address
1083  * @hw: pointer to the HW structure
1084  * @mac_addr: pointer to MAC address
1085  *
1086  * Reads the adapter's MAC address from register
1087  **/
1088 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1089 {
1090         struct i40e_aqc_mac_address_read_data addrs;
1091         enum i40e_status_code status;
1092         u16 flags = 0;
1093
1094         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1095
1096         if (flags & I40E_AQC_LAN_ADDR_VALID)
1097                 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1098                         I40E_NONDMA_TO_NONDMA);
1099
1100         return status;
1101 }
1102
1103 /**
1104  * i40e_get_port_mac_addr - get Port MAC address
1105  * @hw: pointer to the HW structure
1106  * @mac_addr: pointer to Port MAC address
1107  *
1108  * Reads the adapter's Port MAC address
1109  **/
1110 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1111 {
1112         struct i40e_aqc_mac_address_read_data addrs;
1113         enum i40e_status_code status;
1114         u16 flags = 0;
1115
1116         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1117         if (status)
1118                 return status;
1119
1120         if (flags & I40E_AQC_PORT_ADDR_VALID)
1121                 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1122                         I40E_NONDMA_TO_NONDMA);
1123         else
1124                 status = I40E_ERR_INVALID_MAC_ADDR;
1125
1126         return status;
1127 }
1128
1129 /**
1130  * i40e_pre_tx_queue_cfg - pre tx queue configure
1131  * @hw: pointer to the HW structure
1132  * @queue: target pf queue index
1133  * @enable: state change request
1134  *
1135  * Handles hw requirement to indicate intention to enable
1136  * or disable target queue.
1137  **/
1138 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1139 {
1140         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1141         u32 reg_block = 0;
1142         u32 reg_val;
1143
1144         if (abs_queue_idx >= 128) {
1145                 reg_block = abs_queue_idx / 128;
1146                 abs_queue_idx %= 128;
1147         }
1148
1149         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1150         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1151         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1152
1153         if (enable)
1154                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1155         else
1156                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1157
1158         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1159 }
1160
1161 /**
1162  * i40e_get_san_mac_addr - get SAN MAC address
1163  * @hw: pointer to the HW structure
1164  * @mac_addr: pointer to SAN MAC address
1165  *
1166  * Reads the adapter's SAN MAC address from NVM
1167  **/
1168 enum i40e_status_code i40e_get_san_mac_addr(struct i40e_hw *hw,
1169                                             u8 *mac_addr)
1170 {
1171         struct i40e_aqc_mac_address_read_data addrs;
1172         enum i40e_status_code status;
1173         u16 flags = 0;
1174
1175         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1176         if (status)
1177                 return status;
1178
1179         if (flags & I40E_AQC_SAN_ADDR_VALID)
1180                 i40e_memcpy(mac_addr, &addrs.pf_san_mac, sizeof(addrs.pf_san_mac),
1181                         I40E_NONDMA_TO_NONDMA);
1182         else
1183                 status = I40E_ERR_INVALID_MAC_ADDR;
1184
1185         return status;
1186 }
1187
1188 /**
1189  *  i40e_read_pba_string - Reads part number string from EEPROM
1190  *  @hw: pointer to hardware structure
1191  *  @pba_num: stores the part number string from the EEPROM
1192  *  @pba_num_size: part number string buffer length
1193  *
1194  *  Reads the part number string from the EEPROM.
1195  **/
1196 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1197                                             u32 pba_num_size)
1198 {
1199         enum i40e_status_code status = I40E_SUCCESS;
1200         u16 pba_word = 0;
1201         u16 pba_size = 0;
1202         u16 pba_ptr = 0;
1203         u16 i = 0;
1204
1205         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1206         if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1207                 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1208                 return status;
1209         }
1210
1211         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1212         if (status != I40E_SUCCESS) {
1213                 DEBUGOUT("Failed to read PBA Block pointer.\n");
1214                 return status;
1215         }
1216
1217         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1218         if (status != I40E_SUCCESS) {
1219                 DEBUGOUT("Failed to read PBA Block size.\n");
1220                 return status;
1221         }
1222
1223         /* Subtract one to get PBA word count (PBA Size word is included in
1224          * total size)
1225          */
1226         pba_size--;
1227         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1228                 DEBUGOUT("Buffer to small for PBA data.\n");
1229                 return I40E_ERR_PARAM;
1230         }
1231
1232         for (i = 0; i < pba_size; i++) {
1233                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1234                 if (status != I40E_SUCCESS) {
1235                         DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1236                         return status;
1237                 }
1238
1239                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1240                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1241         }
1242         pba_num[(pba_size * 2)] = '\0';
1243
1244         return status;
1245 }
1246
1247 /**
1248  * i40e_get_media_type - Gets media type
1249  * @hw: pointer to the hardware structure
1250  **/
1251 STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1252 {
1253         enum i40e_media_type media;
1254
1255         switch (hw->phy.link_info.phy_type) {
1256         case I40E_PHY_TYPE_10GBASE_SR:
1257         case I40E_PHY_TYPE_10GBASE_LR:
1258         case I40E_PHY_TYPE_1000BASE_SX:
1259         case I40E_PHY_TYPE_1000BASE_LX:
1260         case I40E_PHY_TYPE_40GBASE_SR4:
1261         case I40E_PHY_TYPE_40GBASE_LR4:
1262         case I40E_PHY_TYPE_25GBASE_LR:
1263         case I40E_PHY_TYPE_25GBASE_SR:
1264                 media = I40E_MEDIA_TYPE_FIBER;
1265                 break;
1266         case I40E_PHY_TYPE_100BASE_TX:
1267         case I40E_PHY_TYPE_1000BASE_T:
1268 #ifdef CARLSVILLE_HW
1269         case I40E_PHY_TYPE_2_5GBASE_T:
1270         case I40E_PHY_TYPE_5GBASE_T:
1271 #endif
1272         case I40E_PHY_TYPE_10GBASE_T:
1273                 media = I40E_MEDIA_TYPE_BASET;
1274                 break;
1275         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1276         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1277         case I40E_PHY_TYPE_10GBASE_CR1:
1278         case I40E_PHY_TYPE_40GBASE_CR4:
1279         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1280         case I40E_PHY_TYPE_40GBASE_AOC:
1281         case I40E_PHY_TYPE_10GBASE_AOC:
1282         case I40E_PHY_TYPE_25GBASE_CR:
1283         case I40E_PHY_TYPE_25GBASE_AOC:
1284         case I40E_PHY_TYPE_25GBASE_ACC:
1285                 media = I40E_MEDIA_TYPE_DA;
1286                 break;
1287         case I40E_PHY_TYPE_1000BASE_KX:
1288         case I40E_PHY_TYPE_10GBASE_KX4:
1289         case I40E_PHY_TYPE_10GBASE_KR:
1290         case I40E_PHY_TYPE_40GBASE_KR4:
1291         case I40E_PHY_TYPE_20GBASE_KR2:
1292         case I40E_PHY_TYPE_25GBASE_KR:
1293                 media = I40E_MEDIA_TYPE_BACKPLANE;
1294                 break;
1295         case I40E_PHY_TYPE_SGMII:
1296         case I40E_PHY_TYPE_XAUI:
1297         case I40E_PHY_TYPE_XFI:
1298         case I40E_PHY_TYPE_XLAUI:
1299         case I40E_PHY_TYPE_XLPPI:
1300         default:
1301                 media = I40E_MEDIA_TYPE_UNKNOWN;
1302                 break;
1303         }
1304
1305         return media;
1306 }
1307
1308 /**
1309  * i40e_poll_globr - Poll for Global Reset completion
1310  * @hw: pointer to the hardware structure
1311  * @retry_limit: how many times to retry before failure
1312  **/
1313 STATIC enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1314                                              u32 retry_limit)
1315 {
1316         u32 cnt, reg = 0;
1317
1318         for (cnt = 0; cnt < retry_limit; cnt++) {
1319                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1320                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1321                         return I40E_SUCCESS;
1322                 i40e_msec_delay(100);
1323         }
1324
1325         DEBUGOUT("Global reset failed.\n");
1326         DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1327
1328         return I40E_ERR_RESET_FAILED;
1329 }
1330
1331 #define I40E_PF_RESET_WAIT_COUNT        200
1332 /**
1333  * i40e_pf_reset - Reset the PF
1334  * @hw: pointer to the hardware structure
1335  *
1336  * Assuming someone else has triggered a global reset,
1337  * assure the global reset is complete and then reset the PF
1338  **/
1339 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1340 {
1341         u32 cnt = 0;
1342         u32 cnt1 = 0;
1343         u32 reg = 0;
1344         u32 grst_del;
1345
1346         /* Poll for Global Reset steady state in case of recent GRST.
1347          * The grst delay value is in 100ms units, and we'll wait a
1348          * couple counts longer to be sure we don't just miss the end.
1349          */
1350         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1351                         I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1352                         I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1353
1354         grst_del = min(grst_del * 20, 160U);
1355
1356         for (cnt = 0; cnt < grst_del; cnt++) {
1357                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1358                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1359                         break;
1360                 i40e_msec_delay(100);
1361         }
1362         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1363                 DEBUGOUT("Global reset polling failed to complete.\n");
1364                 return I40E_ERR_RESET_FAILED;
1365         }
1366
1367         /* Now Wait for the FW to be ready */
1368         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1369                 reg = rd32(hw, I40E_GLNVM_ULD);
1370                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1371                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1372                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1373                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1374                         DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1375                         break;
1376                 }
1377                 i40e_msec_delay(10);
1378         }
1379         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1380                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1381                 DEBUGOUT("wait for FW Reset complete timedout\n");
1382                 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1383                 return I40E_ERR_RESET_FAILED;
1384         }
1385
1386         /* If there was a Global Reset in progress when we got here,
1387          * we don't need to do the PF Reset
1388          */
1389         if (!cnt) {
1390                 u32 reg2 = 0;
1391
1392                 reg = rd32(hw, I40E_PFGEN_CTRL);
1393                 wr32(hw, I40E_PFGEN_CTRL,
1394                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1395                 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1396                         reg = rd32(hw, I40E_PFGEN_CTRL);
1397                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1398                                 break;
1399                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1400                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1401                                 break;
1402                         i40e_msec_delay(1);
1403                 }
1404                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1405                         if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1406                                 return I40E_ERR_RESET_FAILED;
1407                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1408                         DEBUGOUT("PF reset polling failed to complete.\n");
1409                         return I40E_ERR_RESET_FAILED;
1410                 }
1411         }
1412
1413         i40e_clear_pxe_mode(hw);
1414
1415
1416         return I40E_SUCCESS;
1417 }
1418
1419 /**
1420  * i40e_clear_hw - clear out any left over hw state
1421  * @hw: pointer to the hw struct
1422  *
1423  * Clear queues and interrupts, typically called at init time,
1424  * but after the capabilities have been found so we know how many
1425  * queues and msix vectors have been allocated.
1426  **/
1427 void i40e_clear_hw(struct i40e_hw *hw)
1428 {
1429         u32 num_queues, base_queue;
1430         u32 num_pf_int;
1431         u32 num_vf_int;
1432         u32 num_vfs;
1433         u32 i, j;
1434         u32 val;
1435         u32 eol = 0x7ff;
1436
1437         /* get number of interrupts, queues, and vfs */
1438         val = rd32(hw, I40E_GLPCI_CNF2);
1439         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1440                         I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1441         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1442                         I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1443
1444         val = rd32(hw, I40E_PFLAN_QALLOC);
1445         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1446                         I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1447         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1448                         I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1449         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1450                 num_queues = (j - base_queue) + 1;
1451         else
1452                 num_queues = 0;
1453
1454         val = rd32(hw, I40E_PF_VT_PFALLOC);
1455         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1456                         I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1457         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1458                         I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1459         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1460                 num_vfs = (j - i) + 1;
1461         else
1462                 num_vfs = 0;
1463
1464         /* stop all the interrupts */
1465         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1466         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1467         for (i = 0; i < num_pf_int - 2; i++)
1468                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1469
1470         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1471         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1472         wr32(hw, I40E_PFINT_LNKLST0, val);
1473         for (i = 0; i < num_pf_int - 2; i++)
1474                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1475         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1476         for (i = 0; i < num_vfs; i++)
1477                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1478         for (i = 0; i < num_vf_int - 2; i++)
1479                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1480
1481         /* warn the HW of the coming Tx disables */
1482         for (i = 0; i < num_queues; i++) {
1483                 u32 abs_queue_idx = base_queue + i;
1484                 u32 reg_block = 0;
1485
1486                 if (abs_queue_idx >= 128) {
1487                         reg_block = abs_queue_idx / 128;
1488                         abs_queue_idx %= 128;
1489                 }
1490
1491                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1492                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1493                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1494                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1495
1496                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1497         }
1498         i40e_usec_delay(400);
1499
1500         /* stop all the queues */
1501         for (i = 0; i < num_queues; i++) {
1502                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1503                 wr32(hw, I40E_QTX_ENA(i), 0);
1504                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1505                 wr32(hw, I40E_QRX_ENA(i), 0);
1506         }
1507
1508         /* short wait for all queue disables to settle */
1509         i40e_usec_delay(50);
1510 }
1511
1512 /**
1513  * i40e_clear_pxe_mode - clear pxe operations mode
1514  * @hw: pointer to the hw struct
1515  *
1516  * Make sure all PXE mode settings are cleared, including things
1517  * like descriptor fetch/write-back mode.
1518  **/
1519 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1520 {
1521         if (i40e_check_asq_alive(hw))
1522                 i40e_aq_clear_pxe_mode(hw, NULL);
1523 }
1524
1525 /**
1526  * i40e_led_is_mine - helper to find matching led
1527  * @hw: pointer to the hw struct
1528  * @idx: index into GPIO registers
1529  *
1530  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1531  */
1532 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1533 {
1534         u32 gpio_val = 0;
1535         u32 port;
1536
1537         if (!hw->func_caps.led[idx])
1538                 return 0;
1539
1540         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1541         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1542                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1543
1544         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1545          * if it is not our port then ignore
1546          */
1547         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1548             (port != hw->port))
1549                 return 0;
1550
1551         return gpio_val;
1552 }
1553
1554 #define I40E_COMBINED_ACTIVITY 0xA
1555 #define I40E_FILTER_ACTIVITY 0xE
1556 #define I40E_LINK_ACTIVITY 0xC
1557 #define I40E_MAC_ACTIVITY 0xD
1558 #define I40E_LED0 22
1559
1560 /**
1561  * i40e_led_get - return current on/off mode
1562  * @hw: pointer to the hw struct
1563  *
1564  * The value returned is the 'mode' field as defined in the
1565  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1566  * values are variations of possible behaviors relating to
1567  * blink, link, and wire.
1568  **/
1569 u32 i40e_led_get(struct i40e_hw *hw)
1570 {
1571         u32 current_mode = 0;
1572         u32 mode = 0;
1573         int i;
1574
1575         /* as per the documentation GPIO 22-29 are the LED
1576          * GPIO pins named LED0..LED7
1577          */
1578         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1579                 u32 gpio_val = i40e_led_is_mine(hw, i);
1580
1581                 if (!gpio_val)
1582                         continue;
1583
1584                 /* ignore gpio LED src mode entries related to the activity
1585                  *  LEDs
1586                  */
1587                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1588                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1589                 switch (current_mode) {
1590                 case I40E_COMBINED_ACTIVITY:
1591                 case I40E_FILTER_ACTIVITY:
1592                 case I40E_MAC_ACTIVITY:
1593                 case I40E_LINK_ACTIVITY:
1594                         continue;
1595                 default:
1596                         break;
1597                 }
1598
1599                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1600                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1601                 break;
1602         }
1603
1604         return mode;
1605 }
1606
1607 /**
1608  * i40e_led_set - set new on/off mode
1609  * @hw: pointer to the hw struct
1610  * @mode: 0=off, 0xf=on (else see manual for mode details)
1611  * @blink: true if the LED should blink when on, false if steady
1612  *
1613  * if this function is used to turn on the blink it should
1614  * be used to disable the blink when restoring the original state.
1615  **/
1616 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1617 {
1618         u32 current_mode = 0;
1619         int i;
1620
1621         if (mode & 0xfffffff0)
1622                 DEBUGOUT1("invalid mode passed in %X\n", mode);
1623
1624         /* as per the documentation GPIO 22-29 are the LED
1625          * GPIO pins named LED0..LED7
1626          */
1627         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1628                 u32 gpio_val = i40e_led_is_mine(hw, i);
1629
1630                 if (!gpio_val)
1631                         continue;
1632
1633                 /* ignore gpio LED src mode entries related to the activity
1634                  * LEDs
1635                  */
1636                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1637                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1638                 switch (current_mode) {
1639                 case I40E_COMBINED_ACTIVITY:
1640                 case I40E_FILTER_ACTIVITY:
1641                 case I40E_MAC_ACTIVITY:
1642                 case I40E_LINK_ACTIVITY:
1643                         continue;
1644                 default:
1645                         break;
1646                 }
1647
1648                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1649                 /* this & is a bit of paranoia, but serves as a range check */
1650                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1651                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1652
1653                 if (blink)
1654                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1655                 else
1656                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1657
1658                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1659                 break;
1660         }
1661 }
1662
1663 /* Admin command wrappers */
1664
1665 /**
1666  * i40e_aq_get_phy_capabilities
1667  * @hw: pointer to the hw struct
1668  * @abilities: structure for PHY capabilities to be filled
1669  * @qualified_modules: report Qualified Modules
1670  * @report_init: report init capabilities (active are default)
1671  * @cmd_details: pointer to command details structure or NULL
1672  *
1673  * Returns the various PHY abilities supported on the Port.
1674  **/
1675 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1676                         bool qualified_modules, bool report_init,
1677                         struct i40e_aq_get_phy_abilities_resp *abilities,
1678                         struct i40e_asq_cmd_details *cmd_details)
1679 {
1680         struct i40e_aq_desc desc;
1681         enum i40e_status_code status;
1682         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1683         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1684
1685         if (!abilities)
1686                 return I40E_ERR_PARAM;
1687
1688         do {
1689                 i40e_fill_default_direct_cmd_desc(&desc,
1690                                                i40e_aqc_opc_get_phy_abilities);
1691
1692                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1693                 if (abilities_size > I40E_AQ_LARGE_BUF)
1694                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1695
1696                 if (qualified_modules)
1697                         desc.params.external.param0 |=
1698                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1699
1700                 if (report_init)
1701                         desc.params.external.param0 |=
1702                         CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1703
1704                 status = i40e_asq_send_command(hw, &desc, abilities,
1705                                                abilities_size, cmd_details);
1706
1707                 if (status != I40E_SUCCESS)
1708                         break;
1709
1710                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1711                         status = I40E_ERR_UNKNOWN_PHY;
1712                         break;
1713                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1714                         i40e_msec_delay(1);
1715                         total_delay++;
1716                         status = I40E_ERR_TIMEOUT;
1717                 }
1718         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1719                  (total_delay < max_delay));
1720
1721         if (status != I40E_SUCCESS)
1722                 return status;
1723
1724         if (report_init) {
1725                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1726                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1727                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1728                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1729                 } else {
1730                         hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1731                         hw->phy.phy_types |=
1732                                         ((u64)abilities->phy_type_ext << 32);
1733                 }
1734         }
1735
1736         return status;
1737 }
1738
1739 /**
1740  * i40e_aq_set_phy_config
1741  * @hw: pointer to the hw struct
1742  * @config: structure with PHY configuration to be set
1743  * @cmd_details: pointer to command details structure or NULL
1744  *
1745  * Set the various PHY configuration parameters
1746  * supported on the Port.One or more of the Set PHY config parameters may be
1747  * ignored in an MFP mode as the PF may not have the privilege to set some
1748  * of the PHY Config parameters. This status will be indicated by the
1749  * command response.
1750  **/
1751 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1752                                 struct i40e_aq_set_phy_config *config,
1753                                 struct i40e_asq_cmd_details *cmd_details)
1754 {
1755         struct i40e_aq_desc desc;
1756         struct i40e_aq_set_phy_config *cmd =
1757                 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1758         enum i40e_status_code status;
1759
1760         if (!config)
1761                 return I40E_ERR_PARAM;
1762
1763         i40e_fill_default_direct_cmd_desc(&desc,
1764                                           i40e_aqc_opc_set_phy_config);
1765
1766         *cmd = *config;
1767
1768         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1769
1770         return status;
1771 }
1772
1773 /**
1774  * i40e_set_fc
1775  * @hw: pointer to the hw struct
1776  * @aq_failures: buffer to return AdminQ failure information
1777  * @atomic_restart: whether to enable atomic link restart
1778  *
1779  * Set the requested flow control mode using set_phy_config.
1780  **/
1781 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1782                                   bool atomic_restart)
1783 {
1784         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1785         struct i40e_aq_get_phy_abilities_resp abilities;
1786         struct i40e_aq_set_phy_config config;
1787         enum i40e_status_code status;
1788         u8 pause_mask = 0x0;
1789
1790         *aq_failures = 0x0;
1791
1792         switch (fc_mode) {
1793         case I40E_FC_FULL:
1794                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1795                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1796                 break;
1797         case I40E_FC_RX_PAUSE:
1798                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1799                 break;
1800         case I40E_FC_TX_PAUSE:
1801                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1802                 break;
1803         default:
1804                 break;
1805         }
1806
1807         /* Get the current phy config */
1808         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1809                                               NULL);
1810         if (status) {
1811                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1812                 return status;
1813         }
1814
1815         memset(&config, 0, sizeof(config));
1816         /* clear the old pause settings */
1817         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1818                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1819         /* set the new abilities */
1820         config.abilities |= pause_mask;
1821         /* If the abilities have changed, then set the new config */
1822         if (config.abilities != abilities.abilities) {
1823                 /* Auto restart link so settings take effect */
1824                 if (atomic_restart)
1825                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1826                 /* Copy over all the old settings */
1827                 config.phy_type = abilities.phy_type;
1828                 config.phy_type_ext = abilities.phy_type_ext;
1829                 config.link_speed = abilities.link_speed;
1830                 config.eee_capability = abilities.eee_capability;
1831                 config.eeer = abilities.eeer_val;
1832                 config.low_power_ctrl = abilities.d3_lpan;
1833                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1834                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1835                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1836
1837                 if (status)
1838                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1839         }
1840         /* Update the link info */
1841         status = i40e_update_link_info(hw);
1842         if (status) {
1843                 /* Wait a little bit (on 40G cards it sometimes takes a really
1844                  * long time for link to come back from the atomic reset)
1845                  * and try once more
1846                  */
1847                 i40e_msec_delay(1000);
1848                 status = i40e_update_link_info(hw);
1849         }
1850         if (status)
1851                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1852
1853         return status;
1854 }
1855
1856 /**
1857  * i40e_aq_set_mac_config
1858  * @hw: pointer to the hw struct
1859  * @max_frame_size: Maximum Frame Size to be supported by the port
1860  * @crc_en: Tell HW to append a CRC to outgoing frames
1861  * @pacing: Pacing configurations
1862  * @cmd_details: pointer to command details structure or NULL
1863  *
1864  * Configure MAC settings for frame size, jumbo frame support and the
1865  * addition of a CRC by the hardware.
1866  **/
1867 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1868                                 u16 max_frame_size,
1869                                 bool crc_en, u16 pacing,
1870                                 struct i40e_asq_cmd_details *cmd_details)
1871 {
1872         struct i40e_aq_desc desc;
1873         struct i40e_aq_set_mac_config *cmd =
1874                 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1875         enum i40e_status_code status;
1876
1877         if (max_frame_size == 0)
1878                 return I40E_ERR_PARAM;
1879
1880         i40e_fill_default_direct_cmd_desc(&desc,
1881                                           i40e_aqc_opc_set_mac_config);
1882
1883         cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1884         cmd->params = ((u8)pacing & 0x0F) << 3;
1885         if (crc_en)
1886                 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1887
1888 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD     0x7FFF
1889         cmd->fc_refresh_threshold =
1890                 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1891
1892         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1893
1894         return status;
1895 }
1896
1897 /**
1898  * i40e_aq_clear_pxe_mode
1899  * @hw: pointer to the hw struct
1900  * @cmd_details: pointer to command details structure or NULL
1901  *
1902  * Tell the firmware that the driver is taking over from PXE
1903  **/
1904 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1905                         struct i40e_asq_cmd_details *cmd_details)
1906 {
1907         enum i40e_status_code status;
1908         struct i40e_aq_desc desc;
1909         struct i40e_aqc_clear_pxe *cmd =
1910                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1911
1912         i40e_fill_default_direct_cmd_desc(&desc,
1913                                           i40e_aqc_opc_clear_pxe_mode);
1914
1915         cmd->rx_cnt = 0x2;
1916
1917         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918
1919         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1920
1921         return status;
1922 }
1923
1924 /**
1925  * i40e_aq_set_link_restart_an
1926  * @hw: pointer to the hw struct
1927  * @enable_link: if true: enable link, if false: disable link
1928  * @cmd_details: pointer to command details structure or NULL
1929  *
1930  * Sets up the link and restarts the Auto-Negotiation over the link.
1931  **/
1932 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1933                 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1934 {
1935         struct i40e_aq_desc desc;
1936         struct i40e_aqc_set_link_restart_an *cmd =
1937                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1938         enum i40e_status_code status;
1939
1940         i40e_fill_default_direct_cmd_desc(&desc,
1941                                           i40e_aqc_opc_set_link_restart_an);
1942
1943         cmd->command = I40E_AQ_PHY_RESTART_AN;
1944         if (enable_link)
1945                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1946         else
1947                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1948
1949         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1950
1951         return status;
1952 }
1953
1954 /**
1955  * i40e_aq_get_link_info
1956  * @hw: pointer to the hw struct
1957  * @enable_lse: enable/disable LinkStatusEvent reporting
1958  * @link: pointer to link status structure - optional
1959  * @cmd_details: pointer to command details structure or NULL
1960  *
1961  * Returns the link status of the adapter.
1962  **/
1963 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1964                                 bool enable_lse, struct i40e_link_status *link,
1965                                 struct i40e_asq_cmd_details *cmd_details)
1966 {
1967         struct i40e_aq_desc desc;
1968         struct i40e_aqc_get_link_status *resp =
1969                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1970         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1971         enum i40e_status_code status;
1972         bool tx_pause, rx_pause;
1973         u16 command_flags;
1974
1975         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1976
1977         if (enable_lse)
1978                 command_flags = I40E_AQ_LSE_ENABLE;
1979         else
1980                 command_flags = I40E_AQ_LSE_DISABLE;
1981         resp->command_flags = CPU_TO_LE16(command_flags);
1982
1983         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1984
1985         if (status != I40E_SUCCESS)
1986                 goto aq_get_link_info_exit;
1987
1988         /* save off old link status information */
1989         i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1990                     sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1991
1992         /* update link status */
1993         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1994         hw->phy.media_type = i40e_get_media_type(hw);
1995         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1996         hw_link_info->link_info = resp->link_info;
1997         hw_link_info->an_info = resp->an_info;
1998         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1999                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
2000         hw_link_info->ext_info = resp->ext_info;
2001         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2002         hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2003         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2004
2005         /* update fc info */
2006         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2007         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2008         if (tx_pause & rx_pause)
2009                 hw->fc.current_mode = I40E_FC_FULL;
2010         else if (tx_pause)
2011                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2012         else if (rx_pause)
2013                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2014         else
2015                 hw->fc.current_mode = I40E_FC_NONE;
2016
2017         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2018                 hw_link_info->crc_enable = true;
2019         else
2020                 hw_link_info->crc_enable = false;
2021
2022         if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2023                 hw_link_info->lse_enable = true;
2024         else
2025                 hw_link_info->lse_enable = false;
2026
2027         if ((hw->mac.type == I40E_MAC_XL710) &&
2028             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2029              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2030                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2031
2032         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
2033             hw->aq.api_min_ver >= 7) {
2034                 __le32 tmp;
2035
2036                 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2037                             I40E_NONDMA_TO_NONDMA);
2038                 hw->phy.phy_types = LE32_TO_CPU(tmp);
2039                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2040         }
2041
2042         /* save link status information */
2043         if (link)
2044                 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2045                             I40E_NONDMA_TO_NONDMA);
2046
2047         /* flag cleared so helper functions don't call AQ again */
2048         hw->phy.get_link_info = false;
2049
2050 aq_get_link_info_exit:
2051         return status;
2052 }
2053
2054 /**
2055  * i40e_aq_set_phy_int_mask
2056  * @hw: pointer to the hw struct
2057  * @mask: interrupt mask to be set
2058  * @cmd_details: pointer to command details structure or NULL
2059  *
2060  * Set link interrupt mask.
2061  **/
2062 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2063                                 u16 mask,
2064                                 struct i40e_asq_cmd_details *cmd_details)
2065 {
2066         struct i40e_aq_desc desc;
2067         struct i40e_aqc_set_phy_int_mask *cmd =
2068                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2069         enum i40e_status_code status;
2070
2071         i40e_fill_default_direct_cmd_desc(&desc,
2072                                           i40e_aqc_opc_set_phy_int_mask);
2073
2074         cmd->event_mask = CPU_TO_LE16(mask);
2075
2076         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2077
2078         return status;
2079 }
2080
2081 /**
2082  * i40e_aq_get_local_advt_reg
2083  * @hw: pointer to the hw struct
2084  * @advt_reg: local AN advertisement register value
2085  * @cmd_details: pointer to command details structure or NULL
2086  *
2087  * Get the Local AN advertisement register value.
2088  **/
2089 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2090                                 u64 *advt_reg,
2091                                 struct i40e_asq_cmd_details *cmd_details)
2092 {
2093         struct i40e_aq_desc desc;
2094         struct i40e_aqc_an_advt_reg *resp =
2095                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2096         enum i40e_status_code status;
2097
2098         i40e_fill_default_direct_cmd_desc(&desc,
2099                                           i40e_aqc_opc_get_local_advt_reg);
2100
2101         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102
2103         if (status != I40E_SUCCESS)
2104                 goto aq_get_local_advt_reg_exit;
2105
2106         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2107         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2108
2109 aq_get_local_advt_reg_exit:
2110         return status;
2111 }
2112
2113 /**
2114  * i40e_aq_set_local_advt_reg
2115  * @hw: pointer to the hw struct
2116  * @advt_reg: local AN advertisement register value
2117  * @cmd_details: pointer to command details structure or NULL
2118  *
2119  * Get the Local AN advertisement register value.
2120  **/
2121 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2122                                 u64 advt_reg,
2123                                 struct i40e_asq_cmd_details *cmd_details)
2124 {
2125         struct i40e_aq_desc desc;
2126         struct i40e_aqc_an_advt_reg *cmd =
2127                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2128         enum i40e_status_code status;
2129
2130         i40e_fill_default_direct_cmd_desc(&desc,
2131                                           i40e_aqc_opc_get_local_advt_reg);
2132
2133         cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2134         cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2135
2136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2137
2138         return status;
2139 }
2140
2141 /**
2142  * i40e_aq_get_partner_advt
2143  * @hw: pointer to the hw struct
2144  * @advt_reg: AN partner advertisement register value
2145  * @cmd_details: pointer to command details structure or NULL
2146  *
2147  * Get the link partner AN advertisement register value.
2148  **/
2149 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2150                                 u64 *advt_reg,
2151                                 struct i40e_asq_cmd_details *cmd_details)
2152 {
2153         struct i40e_aq_desc desc;
2154         struct i40e_aqc_an_advt_reg *resp =
2155                 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2156         enum i40e_status_code status;
2157
2158         i40e_fill_default_direct_cmd_desc(&desc,
2159                                           i40e_aqc_opc_get_partner_advt);
2160
2161         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2162
2163         if (status != I40E_SUCCESS)
2164                 goto aq_get_partner_advt_exit;
2165
2166         *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2167         *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2168
2169 aq_get_partner_advt_exit:
2170         return status;
2171 }
2172
2173 /**
2174  * i40e_aq_set_lb_modes
2175  * @hw: pointer to the hw struct
2176  * @lb_modes: loopback mode to be set
2177  * @cmd_details: pointer to command details structure or NULL
2178  *
2179  * Sets loopback modes.
2180  **/
2181 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,
2182                                 u16 lb_modes,
2183                                 struct i40e_asq_cmd_details *cmd_details)
2184 {
2185         struct i40e_aq_desc desc;
2186         struct i40e_aqc_set_lb_mode *cmd =
2187                 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2188         enum i40e_status_code status;
2189
2190         i40e_fill_default_direct_cmd_desc(&desc,
2191                                           i40e_aqc_opc_set_lb_modes);
2192
2193         cmd->lb_mode = CPU_TO_LE16(lb_modes);
2194
2195         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2196
2197         return status;
2198 }
2199
2200 /**
2201  * i40e_aq_set_phy_debug
2202  * @hw: pointer to the hw struct
2203  * @cmd_flags: debug command flags
2204  * @cmd_details: pointer to command details structure or NULL
2205  *
2206  * Reset the external PHY.
2207  **/
2208 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2209                                 struct i40e_asq_cmd_details *cmd_details)
2210 {
2211         struct i40e_aq_desc desc;
2212         struct i40e_aqc_set_phy_debug *cmd =
2213                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2214         enum i40e_status_code status;
2215
2216         i40e_fill_default_direct_cmd_desc(&desc,
2217                                           i40e_aqc_opc_set_phy_debug);
2218
2219         cmd->command_flags = cmd_flags;
2220
2221         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2222
2223         return status;
2224 }
2225
2226 /**
2227  * i40e_aq_add_vsi
2228  * @hw: pointer to the hw struct
2229  * @vsi_ctx: pointer to a vsi context struct
2230  * @cmd_details: pointer to command details structure or NULL
2231  *
2232  * Add a VSI context to the hardware.
2233 **/
2234 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2235                                 struct i40e_vsi_context *vsi_ctx,
2236                                 struct i40e_asq_cmd_details *cmd_details)
2237 {
2238         struct i40e_aq_desc desc;
2239         struct i40e_aqc_add_get_update_vsi *cmd =
2240                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2241         struct i40e_aqc_add_get_update_vsi_completion *resp =
2242                 (struct i40e_aqc_add_get_update_vsi_completion *)
2243                 &desc.params.raw;
2244         enum i40e_status_code status;
2245
2246         i40e_fill_default_direct_cmd_desc(&desc,
2247                                           i40e_aqc_opc_add_vsi);
2248
2249         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2250         cmd->connection_type = vsi_ctx->connection_type;
2251         cmd->vf_id = vsi_ctx->vf_num;
2252         cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2253
2254         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2255
2256         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2257                                     sizeof(vsi_ctx->info), cmd_details);
2258
2259         if (status != I40E_SUCCESS)
2260                 goto aq_add_vsi_exit;
2261
2262         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2263         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2264         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2265         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2266
2267 aq_add_vsi_exit:
2268         return status;
2269 }
2270
2271 /**
2272  * i40e_aq_set_default_vsi
2273  * @hw: pointer to the hw struct
2274  * @seid: vsi number
2275  * @cmd_details: pointer to command details structure or NULL
2276  **/
2277 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2278                                 u16 seid,
2279                                 struct i40e_asq_cmd_details *cmd_details)
2280 {
2281         struct i40e_aq_desc desc;
2282         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2283                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2284                 &desc.params.raw;
2285         enum i40e_status_code status;
2286
2287         i40e_fill_default_direct_cmd_desc(&desc,
2288                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2289
2290         cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2291         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2292         cmd->seid = CPU_TO_LE16(seid);
2293
2294         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2295
2296         return status;
2297 }
2298
2299 /**
2300  * i40e_aq_clear_default_vsi
2301  * @hw: pointer to the hw struct
2302  * @seid: vsi number
2303  * @cmd_details: pointer to command details structure or NULL
2304  **/
2305 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2306                                 u16 seid,
2307                                 struct i40e_asq_cmd_details *cmd_details)
2308 {
2309         struct i40e_aq_desc desc;
2310         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2311                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2312                 &desc.params.raw;
2313         enum i40e_status_code status;
2314
2315         i40e_fill_default_direct_cmd_desc(&desc,
2316                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2317
2318         cmd->promiscuous_flags = CPU_TO_LE16(0);
2319         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2320         cmd->seid = CPU_TO_LE16(seid);
2321
2322         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2323
2324         return status;
2325 }
2326
2327 /**
2328  * i40e_aq_set_vsi_unicast_promiscuous
2329  * @hw: pointer to the hw struct
2330  * @seid: vsi number
2331  * @set: set unicast promiscuous enable/disable
2332  * @cmd_details: pointer to command details structure or NULL
2333  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2334  **/
2335 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2336                                 u16 seid, bool set,
2337                                 struct i40e_asq_cmd_details *cmd_details,
2338                                 bool rx_only_promisc)
2339 {
2340         struct i40e_aq_desc desc;
2341         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2342                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2343         enum i40e_status_code status;
2344         u16 flags = 0;
2345
2346         i40e_fill_default_direct_cmd_desc(&desc,
2347                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2348
2349         if (set) {
2350                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2351                 if (rx_only_promisc &&
2352                     (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2353                      (hw->aq.api_maj_ver > 1)))
2354                         flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2355         }
2356
2357         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2358
2359         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2360         if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2361              (hw->aq.api_maj_ver > 1))
2362                 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2363
2364         cmd->seid = CPU_TO_LE16(seid);
2365         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2366
2367         return status;
2368 }
2369
2370 /**
2371  * i40e_aq_set_vsi_multicast_promiscuous
2372  * @hw: pointer to the hw struct
2373  * @seid: vsi number
2374  * @set: set multicast promiscuous enable/disable
2375  * @cmd_details: pointer to command details structure or NULL
2376  **/
2377 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2378                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2379 {
2380         struct i40e_aq_desc desc;
2381         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2382                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2383         enum i40e_status_code status;
2384         u16 flags = 0;
2385
2386         i40e_fill_default_direct_cmd_desc(&desc,
2387                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2388
2389         if (set)
2390                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2391
2392         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2393
2394         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2395
2396         cmd->seid = CPU_TO_LE16(seid);
2397         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2398
2399         return status;
2400 }
2401
2402 /**
2403 * i40e_aq_set_vsi_full_promiscuous
2404 * @hw: pointer to the hw struct
2405 * @seid: VSI number
2406 * @set: set promiscuous enable/disable
2407 * @cmd_details: pointer to command details structure or NULL
2408 **/
2409 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2410                                 u16 seid, bool set,
2411                                 struct i40e_asq_cmd_details *cmd_details)
2412 {
2413         struct i40e_aq_desc desc;
2414         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2415                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2416         enum i40e_status_code status;
2417         u16 flags = 0;
2418
2419         i40e_fill_default_direct_cmd_desc(&desc,
2420                 i40e_aqc_opc_set_vsi_promiscuous_modes);
2421
2422         if (set)
2423                 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2424                         I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2425                         I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2426
2427         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2428
2429         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST   |
2430                                        I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2431                                        I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2432
2433         cmd->seid = CPU_TO_LE16(seid);
2434         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2435
2436         return status;
2437 }
2438
2439 /**
2440  * i40e_aq_set_vsi_mc_promisc_on_vlan
2441  * @hw: pointer to the hw struct
2442  * @seid: vsi number
2443  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2444  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2445  * @cmd_details: pointer to command details structure or NULL
2446  **/
2447 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2448                                 u16 seid, bool enable, u16 vid,
2449                                 struct i40e_asq_cmd_details *cmd_details)
2450 {
2451         struct i40e_aq_desc desc;
2452         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2453                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2454         enum i40e_status_code status;
2455         u16 flags = 0;
2456
2457         i40e_fill_default_direct_cmd_desc(&desc,
2458                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2459
2460         if (enable)
2461                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2462
2463         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2464         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2465         cmd->seid = CPU_TO_LE16(seid);
2466         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2467
2468         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2469
2470         return status;
2471 }
2472
2473 /**
2474  * i40e_aq_set_vsi_uc_promisc_on_vlan
2475  * @hw: pointer to the hw struct
2476  * @seid: vsi number
2477  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2478  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2479  * @cmd_details: pointer to command details structure or NULL
2480  **/
2481 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2482                                 u16 seid, bool enable, u16 vid,
2483                                 struct i40e_asq_cmd_details *cmd_details)
2484 {
2485         struct i40e_aq_desc desc;
2486         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2487                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2488         enum i40e_status_code status;
2489         u16 flags = 0;
2490
2491         i40e_fill_default_direct_cmd_desc(&desc,
2492                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2493
2494         if (enable)
2495                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2496
2497         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2498         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2499         cmd->seid = CPU_TO_LE16(seid);
2500         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2501
2502         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2503
2504         return status;
2505 }
2506
2507 /**
2508  * i40e_aq_set_vsi_bc_promisc_on_vlan
2509  * @hw: pointer to the hw struct
2510  * @seid: vsi number
2511  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2512  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2513  * @cmd_details: pointer to command details structure or NULL
2514  **/
2515 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2516                                 u16 seid, bool enable, u16 vid,
2517                                 struct i40e_asq_cmd_details *cmd_details)
2518 {
2519         struct i40e_aq_desc desc;
2520         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2521                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2522         enum i40e_status_code status;
2523         u16 flags = 0;
2524
2525         i40e_fill_default_direct_cmd_desc(&desc,
2526                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2527
2528         if (enable)
2529                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2530
2531         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2532         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2533         cmd->seid = CPU_TO_LE16(seid);
2534         cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2535
2536         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2537
2538         return status;
2539 }
2540
2541 /**
2542  * i40e_aq_set_vsi_broadcast
2543  * @hw: pointer to the hw struct
2544  * @seid: vsi number
2545  * @set_filter: true to set filter, false to clear filter
2546  * @cmd_details: pointer to command details structure or NULL
2547  *
2548  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2549  **/
2550 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2551                                 u16 seid, bool set_filter,
2552                                 struct i40e_asq_cmd_details *cmd_details)
2553 {
2554         struct i40e_aq_desc desc;
2555         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2556                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2557         enum i40e_status_code status;
2558
2559         i40e_fill_default_direct_cmd_desc(&desc,
2560                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2561
2562         if (set_filter)
2563                 cmd->promiscuous_flags
2564                             |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2565         else
2566                 cmd->promiscuous_flags
2567                             &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2568
2569         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2570         cmd->seid = CPU_TO_LE16(seid);
2571         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2572
2573         return status;
2574 }
2575
2576 /**
2577  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2578  * @hw: pointer to the hw struct
2579  * @seid: vsi number
2580  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2581  * @cmd_details: pointer to command details structure or NULL
2582  **/
2583 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2584                                 u16 seid, bool enable,
2585                                 struct i40e_asq_cmd_details *cmd_details)
2586 {
2587         struct i40e_aq_desc desc;
2588         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2589                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2590         enum i40e_status_code status;
2591         u16 flags = 0;
2592
2593         i40e_fill_default_direct_cmd_desc(&desc,
2594                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2595         if (enable)
2596                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2597
2598         cmd->promiscuous_flags = CPU_TO_LE16(flags);
2599         cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2600         cmd->seid = CPU_TO_LE16(seid);
2601
2602         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2603
2604         return status;
2605 }
2606
2607 /**
2608  * i40e_get_vsi_params - get VSI configuration info
2609  * @hw: pointer to the hw struct
2610  * @vsi_ctx: pointer to a vsi context struct
2611  * @cmd_details: pointer to command details structure or NULL
2612  **/
2613 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2614                                 struct i40e_vsi_context *vsi_ctx,
2615                                 struct i40e_asq_cmd_details *cmd_details)
2616 {
2617         struct i40e_aq_desc desc;
2618         struct i40e_aqc_add_get_update_vsi *cmd =
2619                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2620         struct i40e_aqc_add_get_update_vsi_completion *resp =
2621                 (struct i40e_aqc_add_get_update_vsi_completion *)
2622                 &desc.params.raw;
2623         enum i40e_status_code status;
2624
2625         UNREFERENCED_1PARAMETER(cmd_details);
2626         i40e_fill_default_direct_cmd_desc(&desc,
2627                                           i40e_aqc_opc_get_vsi_parameters);
2628
2629         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2630
2631         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2632
2633         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2634                                     sizeof(vsi_ctx->info), NULL);
2635
2636         if (status != I40E_SUCCESS)
2637                 goto aq_get_vsi_params_exit;
2638
2639         vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2640         vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2641         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2642         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2643
2644 aq_get_vsi_params_exit:
2645         return status;
2646 }
2647
2648 /**
2649  * i40e_aq_update_vsi_params
2650  * @hw: pointer to the hw struct
2651  * @vsi_ctx: pointer to a vsi context struct
2652  * @cmd_details: pointer to command details structure or NULL
2653  *
2654  * Update a VSI context.
2655  **/
2656 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2657                                 struct i40e_vsi_context *vsi_ctx,
2658                                 struct i40e_asq_cmd_details *cmd_details)
2659 {
2660         struct i40e_aq_desc desc;
2661         struct i40e_aqc_add_get_update_vsi *cmd =
2662                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2663         struct i40e_aqc_add_get_update_vsi_completion *resp =
2664                 (struct i40e_aqc_add_get_update_vsi_completion *)
2665                 &desc.params.raw;
2666         enum i40e_status_code status;
2667
2668         i40e_fill_default_direct_cmd_desc(&desc,
2669                                           i40e_aqc_opc_update_vsi_parameters);
2670         cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2671
2672         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2673
2674         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2675                                     sizeof(vsi_ctx->info), cmd_details);
2676
2677         vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2678         vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2679
2680         return status;
2681 }
2682
2683 /**
2684  * i40e_aq_get_switch_config
2685  * @hw: pointer to the hardware structure
2686  * @buf: pointer to the result buffer
2687  * @buf_size: length of input buffer
2688  * @start_seid: seid to start for the report, 0 == beginning
2689  * @cmd_details: pointer to command details structure or NULL
2690  *
2691  * Fill the buf with switch configuration returned from AdminQ command
2692  **/
2693 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2694                                 struct i40e_aqc_get_switch_config_resp *buf,
2695                                 u16 buf_size, u16 *start_seid,
2696                                 struct i40e_asq_cmd_details *cmd_details)
2697 {
2698         struct i40e_aq_desc desc;
2699         struct i40e_aqc_switch_seid *scfg =
2700                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2701         enum i40e_status_code status;
2702
2703         i40e_fill_default_direct_cmd_desc(&desc,
2704                                           i40e_aqc_opc_get_switch_config);
2705         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2706         if (buf_size > I40E_AQ_LARGE_BUF)
2707                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2708         scfg->seid = CPU_TO_LE16(*start_seid);
2709
2710         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2711         *start_seid = LE16_TO_CPU(scfg->seid);
2712
2713         return status;
2714 }
2715
2716 /**
2717  * i40e_aq_set_switch_config
2718  * @hw: pointer to the hardware structure
2719  * @flags: bit flag values to set
2720  * @mode: cloud filter mode
2721  * @valid_flags: which bit flags to set
2722  * @cmd_details: pointer to command details structure or NULL
2723  *
2724  * Set switch configuration bits
2725  **/
2726 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2727                                 u16 flags, u16 valid_flags, u8 mode,
2728                                 struct i40e_asq_cmd_details *cmd_details)
2729 {
2730         struct i40e_aq_desc desc;
2731         struct i40e_aqc_set_switch_config *scfg =
2732                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2733         enum i40e_status_code status;
2734
2735         i40e_fill_default_direct_cmd_desc(&desc,
2736                                           i40e_aqc_opc_set_switch_config);
2737         scfg->flags = CPU_TO_LE16(flags);
2738         scfg->valid_flags = CPU_TO_LE16(valid_flags);
2739         scfg->mode = mode;
2740         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2741                 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2742                 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2743                 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2744         }
2745         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2746
2747         return status;
2748 }
2749
2750 /**
2751  * i40e_aq_get_firmware_version
2752  * @hw: pointer to the hw struct
2753  * @fw_major_version: firmware major version
2754  * @fw_minor_version: firmware minor version
2755  * @fw_build: firmware build number
2756  * @api_major_version: major queue version
2757  * @api_minor_version: minor queue version
2758  * @cmd_details: pointer to command details structure or NULL
2759  *
2760  * Get the firmware version from the admin queue commands
2761  **/
2762 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2763                                 u16 *fw_major_version, u16 *fw_minor_version,
2764                                 u32 *fw_build,
2765                                 u16 *api_major_version, u16 *api_minor_version,
2766                                 struct i40e_asq_cmd_details *cmd_details)
2767 {
2768         struct i40e_aq_desc desc;
2769         struct i40e_aqc_get_version *resp =
2770                 (struct i40e_aqc_get_version *)&desc.params.raw;
2771         enum i40e_status_code status;
2772
2773         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2774
2775         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2776
2777         if (status == I40E_SUCCESS) {
2778                 if (fw_major_version != NULL)
2779                         *fw_major_version = LE16_TO_CPU(resp->fw_major);
2780                 if (fw_minor_version != NULL)
2781                         *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2782                 if (fw_build != NULL)
2783                         *fw_build = LE32_TO_CPU(resp->fw_build);
2784                 if (api_major_version != NULL)
2785                         *api_major_version = LE16_TO_CPU(resp->api_major);
2786                 if (api_minor_version != NULL)
2787                         *api_minor_version = LE16_TO_CPU(resp->api_minor);
2788
2789                 /* A workaround to fix the API version in SW */
2790                 if (api_major_version && api_minor_version &&
2791                     fw_major_version && fw_minor_version &&
2792                     ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2793                     (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2794                      (*fw_major_version > 4)))
2795                         *api_minor_version = 2;
2796         }
2797
2798         return status;
2799 }
2800
2801 /**
2802  * i40e_aq_send_driver_version
2803  * @hw: pointer to the hw struct
2804  * @dv: driver's major, minor version
2805  * @cmd_details: pointer to command details structure or NULL
2806  *
2807  * Send the driver version to the firmware
2808  **/
2809 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2810                                 struct i40e_driver_version *dv,
2811                                 struct i40e_asq_cmd_details *cmd_details)
2812 {
2813         struct i40e_aq_desc desc;
2814         struct i40e_aqc_driver_version *cmd =
2815                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2816         enum i40e_status_code status;
2817         u16 len;
2818
2819         if (dv == NULL)
2820                 return I40E_ERR_PARAM;
2821
2822         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2823
2824         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2825         cmd->driver_major_ver = dv->major_version;
2826         cmd->driver_minor_ver = dv->minor_version;
2827         cmd->driver_build_ver = dv->build_version;
2828         cmd->driver_subbuild_ver = dv->subbuild_version;
2829
2830         len = 0;
2831         while (len < sizeof(dv->driver_string) &&
2832                (dv->driver_string[len] < 0x80) &&
2833                dv->driver_string[len])
2834                 len++;
2835         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2836                                        len, cmd_details);
2837
2838         return status;
2839 }
2840
2841 /**
2842  * i40e_get_link_status - get status of the HW network link
2843  * @hw: pointer to the hw struct
2844  * @link_up: pointer to bool (true/false = linkup/linkdown)
2845  *
2846  * Variable link_up true if link is up, false if link is down.
2847  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2848  *
2849  * Side effect: LinkStatusEvent reporting becomes enabled
2850  **/
2851 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2852 {
2853         enum i40e_status_code status = I40E_SUCCESS;
2854
2855         if (hw->phy.get_link_info) {
2856                 status = i40e_update_link_info(hw);
2857
2858                 if (status != I40E_SUCCESS)
2859                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2860                                    status);
2861         }
2862
2863         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2864
2865         return status;
2866 }
2867
2868 /**
2869  * i40e_updatelink_status - update status of the HW network link
2870  * @hw: pointer to the hw struct
2871  **/
2872 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2873 {
2874         struct i40e_aq_get_phy_abilities_resp abilities;
2875         enum i40e_status_code status = I40E_SUCCESS;
2876
2877         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2878         if (status)
2879                 return status;
2880
2881         /* extra checking needed to ensure link info to user is timely */
2882         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2883             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2884              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2885                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2886                                                       &abilities, NULL);
2887                 if (status)
2888                         return status;
2889
2890                 hw->phy.link_info.req_fec_info =
2891                         abilities.fec_cfg_curr_mod_ext_info &
2892                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2893
2894                 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2895                         sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2896         }
2897         return status;
2898 }
2899
2900
2901 /**
2902  * i40e_get_link_speed
2903  * @hw: pointer to the hw struct
2904  *
2905  * Returns the link speed of the adapter.
2906  **/
2907 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2908 {
2909         enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2910         enum i40e_status_code status = I40E_SUCCESS;
2911
2912         if (hw->phy.get_link_info) {
2913                 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2914
2915                 if (status != I40E_SUCCESS)
2916                         goto i40e_link_speed_exit;
2917         }
2918
2919         speed = hw->phy.link_info.link_speed;
2920
2921 i40e_link_speed_exit:
2922         return speed;
2923 }
2924
2925 /**
2926  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2927  * @hw: pointer to the hw struct
2928  * @uplink_seid: the MAC or other gizmo SEID
2929  * @downlink_seid: the VSI SEID
2930  * @enabled_tc: bitmap of TCs to be enabled
2931  * @default_port: true for default port VSI, false for control port
2932  * @veb_seid: pointer to where to put the resulting VEB SEID
2933  * @enable_stats: true to turn on VEB stats
2934  * @cmd_details: pointer to command details structure or NULL
2935  *
2936  * This asks the FW to add a VEB between the uplink and downlink
2937  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2938  **/
2939 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2940                                 u16 downlink_seid, u8 enabled_tc,
2941                                 bool default_port, u16 *veb_seid,
2942                                 bool enable_stats,
2943                                 struct i40e_asq_cmd_details *cmd_details)
2944 {
2945         struct i40e_aq_desc desc;
2946         struct i40e_aqc_add_veb *cmd =
2947                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2948         struct i40e_aqc_add_veb_completion *resp =
2949                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2950         enum i40e_status_code status;
2951         u16 veb_flags = 0;
2952
2953         /* SEIDs need to either both be set or both be 0 for floating VEB */
2954         if (!!uplink_seid != !!downlink_seid)
2955                 return I40E_ERR_PARAM;
2956
2957         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2958
2959         cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2960         cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2961         cmd->enable_tcs = enabled_tc;
2962         if (!uplink_seid)
2963                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2964         if (default_port)
2965                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2966         else
2967                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2968
2969         /* reverse logic here: set the bitflag to disable the stats */
2970         if (!enable_stats)
2971                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2972
2973         cmd->veb_flags = CPU_TO_LE16(veb_flags);
2974
2975         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2976
2977         if (!status && veb_seid)
2978                 *veb_seid = LE16_TO_CPU(resp->veb_seid);
2979
2980         return status;
2981 }
2982
2983 /**
2984  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2985  * @hw: pointer to the hw struct
2986  * @veb_seid: the SEID of the VEB to query
2987  * @switch_id: the uplink switch id
2988  * @floating: set to true if the VEB is floating
2989  * @statistic_index: index of the stats counter block for this VEB
2990  * @vebs_used: number of VEB's used by function
2991  * @vebs_free: total VEB's not reserved by any function
2992  * @cmd_details: pointer to command details structure or NULL
2993  *
2994  * This retrieves the parameters for a particular VEB, specified by
2995  * uplink_seid, and returns them to the caller.
2996  **/
2997 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2998                                 u16 veb_seid, u16 *switch_id,
2999                                 bool *floating, u16 *statistic_index,
3000                                 u16 *vebs_used, u16 *vebs_free,
3001                                 struct i40e_asq_cmd_details *cmd_details)
3002 {
3003         struct i40e_aq_desc desc;
3004         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
3005                 (struct i40e_aqc_get_veb_parameters_completion *)
3006                 &desc.params.raw;
3007         enum i40e_status_code status;
3008
3009         if (veb_seid == 0)
3010                 return I40E_ERR_PARAM;
3011
3012         i40e_fill_default_direct_cmd_desc(&desc,
3013                                           i40e_aqc_opc_get_veb_parameters);
3014         cmd_resp->seid = CPU_TO_LE16(veb_seid);
3015
3016         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3017         if (status)
3018                 goto get_veb_exit;
3019
3020         if (switch_id)
3021                 *switch_id = LE16_TO_CPU(cmd_resp->switch_id);
3022         if (statistic_index)
3023                 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
3024         if (vebs_used)
3025                 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
3026         if (vebs_free)
3027                 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
3028         if (floating) {
3029                 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
3030
3031                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
3032                         *floating = true;
3033                 else
3034                         *floating = false;
3035         }
3036
3037 get_veb_exit:
3038         return status;
3039 }
3040
3041 /**
3042  * i40e_aq_add_macvlan
3043  * @hw: pointer to the hw struct
3044  * @seid: VSI for the mac address
3045  * @mv_list: list of macvlans to be added
3046  * @count: length of the list
3047  * @cmd_details: pointer to command details structure or NULL
3048  *
3049  * Add MAC/VLAN addresses to the HW filtering
3050  **/
3051 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
3052                         struct i40e_aqc_add_macvlan_element_data *mv_list,
3053                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3054 {
3055         struct i40e_aq_desc desc;
3056         struct i40e_aqc_macvlan *cmd =
3057                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3058         enum i40e_status_code status;
3059         u16 buf_size;
3060         int i;
3061
3062         if (count == 0 || !mv_list || !hw)
3063                 return I40E_ERR_PARAM;
3064
3065         buf_size = count * sizeof(*mv_list);
3066
3067         /* prep the rest of the request */
3068         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
3069         cmd->num_addresses = CPU_TO_LE16(count);
3070         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3071         cmd->seid[1] = 0;
3072         cmd->seid[2] = 0;
3073
3074         for (i = 0; i < count; i++)
3075                 if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
3076                         mv_list[i].flags |=
3077                             CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
3078
3079         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3080         if (buf_size > I40E_AQ_LARGE_BUF)
3081                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3082
3083         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3084                                        cmd_details);
3085
3086         return status;
3087 }
3088
3089 /**
3090  * i40e_aq_remove_macvlan
3091  * @hw: pointer to the hw struct
3092  * @seid: VSI for the mac address
3093  * @mv_list: list of macvlans to be removed
3094  * @count: length of the list
3095  * @cmd_details: pointer to command details structure or NULL
3096  *
3097  * Remove MAC/VLAN addresses from the HW filtering
3098  **/
3099 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
3100                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
3101                         u16 count, struct i40e_asq_cmd_details *cmd_details)
3102 {
3103         struct i40e_aq_desc desc;
3104         struct i40e_aqc_macvlan *cmd =
3105                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3106         enum i40e_status_code status;
3107         u16 buf_size;
3108
3109         if (count == 0 || !mv_list || !hw)
3110                 return I40E_ERR_PARAM;
3111
3112         buf_size = count * sizeof(*mv_list);
3113
3114         /* prep the rest of the request */
3115         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3116         cmd->num_addresses = CPU_TO_LE16(count);
3117         cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3118         cmd->seid[1] = 0;
3119         cmd->seid[2] = 0;
3120
3121         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3122         if (buf_size > I40E_AQ_LARGE_BUF)
3123                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3124
3125         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3126                                        cmd_details);
3127
3128         return status;
3129 }
3130
3131 /**
3132  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3133  * @hw: pointer to the hw struct
3134  * @opcode: AQ opcode for add or delete mirror rule
3135  * @sw_seid: Switch SEID (to which rule refers)
3136  * @rule_type: Rule Type (ingress/egress/VLAN)
3137  * @id: Destination VSI SEID or Rule ID
3138  * @count: length of the list
3139  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3140  * @cmd_details: pointer to command details structure or NULL
3141  * @rule_id: Rule ID returned from FW
3142  * @rules_used: Number of rules used in internal switch
3143  * @rules_free: Number of rules free in internal switch
3144  *
3145  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3146  * VEBs/VEPA elements only
3147  **/
3148 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3149                         u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3150                         u16 count, __le16 *mr_list,
3151                         struct i40e_asq_cmd_details *cmd_details,
3152                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3153 {
3154         struct i40e_aq_desc desc;
3155         struct i40e_aqc_add_delete_mirror_rule *cmd =
3156                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
3157         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
3158         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
3159         enum i40e_status_code status;
3160         u16 buf_size;
3161
3162         buf_size = count * sizeof(*mr_list);
3163
3164         /* prep the rest of the request */
3165         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3166         cmd->seid = CPU_TO_LE16(sw_seid);
3167         cmd->rule_type = CPU_TO_LE16(rule_type &
3168                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
3169         cmd->num_entries = CPU_TO_LE16(count);
3170         /* Dest VSI for add, rule_id for delete */
3171         cmd->destination = CPU_TO_LE16(id);
3172         if (mr_list) {
3173                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3174                                                 I40E_AQ_FLAG_RD));
3175                 if (buf_size > I40E_AQ_LARGE_BUF)
3176                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3177         }
3178
3179         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
3180                                        cmd_details);
3181         if (status == I40E_SUCCESS ||
3182             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
3183                 if (rule_id)
3184                         *rule_id = LE16_TO_CPU(resp->rule_id);
3185                 if (rules_used)
3186                         *rules_used = LE16_TO_CPU(resp->mirror_rules_used);
3187                 if (rules_free)
3188                         *rules_free = LE16_TO_CPU(resp->mirror_rules_free);
3189         }
3190         return status;
3191 }
3192
3193 /**
3194  * i40e_aq_add_mirrorrule - add a mirror rule
3195  * @hw: pointer to the hw struct
3196  * @sw_seid: Switch SEID (to which rule refers)
3197  * @rule_type: Rule Type (ingress/egress/VLAN)
3198  * @dest_vsi: SEID of VSI to which packets will be mirrored
3199  * @count: length of the list
3200  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3201  * @cmd_details: pointer to command details structure or NULL
3202  * @rule_id: Rule ID returned from FW
3203  * @rules_used: Number of rules used in internal switch
3204  * @rules_free: Number of rules free in internal switch
3205  *
3206  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
3207  **/
3208 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3209                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
3210                         struct i40e_asq_cmd_details *cmd_details,
3211                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
3212 {
3213         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
3214             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
3215                 if (count == 0 || !mr_list)
3216                         return I40E_ERR_PARAM;
3217         }
3218
3219         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
3220                                   rule_type, dest_vsi, count, mr_list,
3221                                   cmd_details, rule_id, rules_used, rules_free);
3222 }
3223
3224 /**
3225  * i40e_aq_delete_mirrorrule - delete a mirror rule
3226  * @hw: pointer to the hw struct
3227  * @sw_seid: Switch SEID (to which rule refers)
3228  * @rule_type: Rule Type (ingress/egress/VLAN)
3229  * @count: length of the list
3230  * @rule_id: Rule ID that is returned in the receive desc as part of
3231  *              add_mirrorrule.
3232  * @mr_list: list of mirrored VLAN IDs to be removed
3233  * @cmd_details: pointer to command details structure or NULL
3234  * @rules_used: Number of rules used in internal switch
3235  * @rules_free: Number of rules free in internal switch
3236  *
3237  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
3238  **/
3239 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
3240                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
3241                         struct i40e_asq_cmd_details *cmd_details,
3242                         u16 *rules_used, u16 *rules_free)
3243 {
3244         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
3245         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
3246                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
3247                  * mirroring. For other rule_type, count and rule_type should
3248                  * not matter.
3249                  */
3250                 if (count == 0 || !mr_list)
3251                         return I40E_ERR_PARAM;
3252         }
3253
3254         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
3255                                   rule_type, rule_id, count, mr_list,
3256                                   cmd_details, NULL, rules_used, rules_free);
3257 }
3258
3259 /**
3260  * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
3261  * @hw: pointer to the hw struct
3262  * @seid: VSI for the vlan filters
3263  * @v_list: list of vlan filters to be added
3264  * @count: length of the list
3265  * @cmd_details: pointer to command details structure or NULL
3266  **/
3267 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
3268                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3269                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3270 {
3271         struct i40e_aq_desc desc;
3272         struct i40e_aqc_macvlan *cmd =
3273                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3274         enum i40e_status_code status;
3275         u16 buf_size;
3276
3277         if (count == 0 || !v_list || !hw)
3278                 return I40E_ERR_PARAM;
3279
3280         buf_size = count * sizeof(*v_list);
3281
3282         /* prep the rest of the request */
3283         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
3284         cmd->num_addresses = CPU_TO_LE16(count);
3285         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3286         cmd->seid[1] = 0;
3287         cmd->seid[2] = 0;
3288
3289         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3290         if (buf_size > I40E_AQ_LARGE_BUF)
3291                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3292
3293         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3294                                        cmd_details);
3295
3296         return status;
3297 }
3298
3299 /**
3300  * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
3301  * @hw: pointer to the hw struct
3302  * @seid: VSI for the vlan filters
3303  * @v_list: list of macvlans to be removed
3304  * @count: length of the list
3305  * @cmd_details: pointer to command details structure or NULL
3306  **/
3307 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
3308                         struct i40e_aqc_add_remove_vlan_element_data *v_list,
3309                         u8 count, struct i40e_asq_cmd_details *cmd_details)
3310 {
3311         struct i40e_aq_desc desc;
3312         struct i40e_aqc_macvlan *cmd =
3313                 (struct i40e_aqc_macvlan *)&desc.params.raw;
3314         enum i40e_status_code status;
3315         u16 buf_size;
3316
3317         if (count == 0 || !v_list || !hw)
3318                 return I40E_ERR_PARAM;
3319
3320         buf_size = count * sizeof(*v_list);
3321
3322         /* prep the rest of the request */
3323         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
3324         cmd->num_addresses = CPU_TO_LE16(count);
3325         cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
3326         cmd->seid[1] = 0;
3327         cmd->seid[2] = 0;
3328
3329         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3330         if (buf_size > I40E_AQ_LARGE_BUF)
3331                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3332
3333         status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
3334                                        cmd_details);
3335
3336         return status;
3337 }
3338
3339 /**
3340  * i40e_aq_send_msg_to_vf
3341  * @hw: pointer to the hardware structure
3342  * @vfid: vf id to send msg
3343  * @v_opcode: opcodes for VF-PF communication
3344  * @v_retval: return error code
3345  * @msg: pointer to the msg buffer
3346  * @msglen: msg length
3347  * @cmd_details: pointer to command details
3348  *
3349  * send msg to vf
3350  **/
3351 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
3352                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
3353                                 struct i40e_asq_cmd_details *cmd_details)
3354 {
3355         struct i40e_aq_desc desc;
3356         struct i40e_aqc_pf_vf_message *cmd =
3357                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
3358         enum i40e_status_code status;
3359
3360         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
3361         cmd->id = CPU_TO_LE32(vfid);
3362         desc.cookie_high = CPU_TO_LE32(v_opcode);
3363         desc.cookie_low = CPU_TO_LE32(v_retval);
3364         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
3365         if (msglen) {
3366                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
3367                                                 I40E_AQ_FLAG_RD));
3368                 if (msglen > I40E_AQ_LARGE_BUF)
3369                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3370                 desc.datalen = CPU_TO_LE16(msglen);
3371         }
3372         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
3373
3374         return status;
3375 }
3376
3377 /**
3378  * i40e_aq_debug_read_register
3379  * @hw: pointer to the hw struct
3380  * @reg_addr: register address
3381  * @reg_val: register value
3382  * @cmd_details: pointer to command details structure or NULL
3383  *
3384  * Read the register using the admin queue commands
3385  **/
3386 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
3387                                 u32 reg_addr, u64 *reg_val,
3388                                 struct i40e_asq_cmd_details *cmd_details)
3389 {
3390         struct i40e_aq_desc desc;
3391         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3392                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3393         enum i40e_status_code status;
3394
3395         if (reg_val == NULL)
3396                 return I40E_ERR_PARAM;
3397
3398         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3399
3400         cmd_resp->address = CPU_TO_LE32(reg_addr);
3401
3402         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3403
3404         if (status == I40E_SUCCESS) {
3405                 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |
3406                            (u64)LE32_TO_CPU(cmd_resp->value_low);
3407         }
3408
3409         return status;
3410 }
3411
3412 /**
3413  * i40e_aq_debug_write_register
3414  * @hw: pointer to the hw struct
3415  * @reg_addr: register address
3416  * @reg_val: register value
3417  * @cmd_details: pointer to command details structure or NULL
3418  *
3419  * Write to a register using the admin queue commands
3420  **/
3421 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
3422                                 u32 reg_addr, u64 reg_val,
3423                                 struct i40e_asq_cmd_details *cmd_details)
3424 {
3425         struct i40e_aq_desc desc;
3426         struct i40e_aqc_debug_reg_read_write *cmd =
3427                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3428         enum i40e_status_code status;
3429
3430         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3431
3432         cmd->address = CPU_TO_LE32(reg_addr);
3433         cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));
3434         cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));
3435
3436         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3437
3438         return status;
3439 }
3440
3441 /**
3442  * i40e_aq_request_resource
3443  * @hw: pointer to the hw struct
3444  * @resource: resource id
3445  * @access: access type
3446  * @sdp_number: resource number
3447  * @timeout: the maximum time in ms that the driver may hold the resource
3448  * @cmd_details: pointer to command details structure or NULL
3449  *
3450  * requests common resource using the admin queue commands
3451  **/
3452 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
3453                                 enum i40e_aq_resources_ids resource,
3454                                 enum i40e_aq_resource_access_type access,
3455                                 u8 sdp_number, u64 *timeout,
3456                                 struct i40e_asq_cmd_details *cmd_details)
3457 {
3458         struct i40e_aq_desc desc;
3459         struct i40e_aqc_request_resource *cmd_resp =
3460                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3461         enum i40e_status_code status;
3462
3463         DEBUGFUNC("i40e_aq_request_resource");
3464
3465         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3466
3467         cmd_resp->resource_id = CPU_TO_LE16(resource);
3468         cmd_resp->access_type = CPU_TO_LE16(access);
3469         cmd_resp->resource_number = CPU_TO_LE32(sdp_number);
3470
3471         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3472         /* The completion specifies the maximum time in ms that the driver
3473          * may hold the resource in the Timeout field.
3474          * If the resource is held by someone else, the command completes with
3475          * busy return value and the timeout field indicates the maximum time
3476          * the current owner of the resource has to free it.
3477          */
3478         if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3479                 *timeout = LE32_TO_CPU(cmd_resp->timeout);
3480
3481         return status;
3482 }
3483
3484 /**
3485  * i40e_aq_release_resource
3486  * @hw: pointer to the hw struct
3487  * @resource: resource id
3488  * @sdp_number: resource number
3489  * @cmd_details: pointer to command details structure or NULL
3490  *
3491  * release common resource using the admin queue commands
3492  **/
3493 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
3494                                 enum i40e_aq_resources_ids resource,
3495                                 u8 sdp_number,
3496                                 struct i40e_asq_cmd_details *cmd_details)
3497 {
3498         struct i40e_aq_desc desc;
3499         struct i40e_aqc_request_resource *cmd =
3500                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3501         enum i40e_status_code status;
3502
3503         DEBUGFUNC("i40e_aq_release_resource");
3504
3505         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3506
3507         cmd->resource_id = CPU_TO_LE16(resource);
3508         cmd->resource_number = CPU_TO_LE32(sdp_number);
3509
3510         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3511
3512         return status;
3513 }
3514
3515 /**
3516  * i40e_aq_read_nvm
3517  * @hw: pointer to the hw struct
3518  * @module_pointer: module pointer location in words from the NVM beginning
3519  * @offset: byte offset from the module beginning
3520  * @length: length of the section to be read (in bytes from the offset)
3521  * @data: command buffer (size [bytes] = length)
3522  * @last_command: tells if this is the last command in a series
3523  * @cmd_details: pointer to command details structure or NULL
3524  *
3525  * Read the NVM using the admin queue commands
3526  **/
3527 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3528                                 u32 offset, u16 length, void *data,
3529                                 bool last_command,
3530                                 struct i40e_asq_cmd_details *cmd_details)
3531 {
3532         struct i40e_aq_desc desc;
3533         struct i40e_aqc_nvm_update *cmd =
3534                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3535         enum i40e_status_code status;
3536
3537         DEBUGFUNC("i40e_aq_read_nvm");
3538
3539         /* In offset the highest byte must be zeroed. */
3540         if (offset & 0xFF000000) {
3541                 status = I40E_ERR_PARAM;
3542                 goto i40e_aq_read_nvm_exit;
3543         }
3544
3545         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3546
3547         /* If this is the last command in a series, set the proper flag. */
3548         if (last_command)
3549                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3550         cmd->module_pointer = module_pointer;
3551         cmd->offset = CPU_TO_LE32(offset);
3552         cmd->length = CPU_TO_LE16(length);
3553
3554         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
3555         if (length > I40E_AQ_LARGE_BUF)
3556                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3557
3558         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3559
3560 i40e_aq_read_nvm_exit:
3561         return status;
3562 }
3563
3564 /**
3565  * i40e_aq_read_nvm_config - read an nvm config block
3566  * @hw: pointer to the hw struct
3567  * @cmd_flags: NVM access admin command bits
3568  * @field_id: field or feature id
3569  * @data: buffer for result
3570  * @buf_size: buffer size
3571  * @element_count: pointer to count of elements read by FW
3572  * @cmd_details: pointer to command details structure or NULL
3573  **/
3574 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
3575                                 u8 cmd_flags, u32 field_id, void *data,
3576                                 u16 buf_size, u16 *element_count,
3577                                 struct i40e_asq_cmd_details *cmd_details)
3578 {
3579         struct i40e_aq_desc desc;
3580         struct i40e_aqc_nvm_config_read *cmd =
3581                 (struct i40e_aqc_nvm_config_read *)&desc.params.raw;
3582         enum i40e_status_code status;
3583
3584         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);
3585         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));
3586         if (buf_size > I40E_AQ_LARGE_BUF)
3587                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3588
3589         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3590         cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));
3591         if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)
3592                 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));
3593         else
3594                 cmd->element_id_msw = 0;
3595
3596         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3597
3598         if (!status && element_count)
3599                 *element_count = LE16_TO_CPU(cmd->element_count);
3600
3601         return status;
3602 }
3603
3604 /**
3605  * i40e_aq_write_nvm_config - write an nvm config block
3606  * @hw: pointer to the hw struct
3607  * @cmd_flags: NVM access admin command bits
3608  * @data: buffer for result
3609  * @buf_size: buffer size
3610  * @element_count: count of elements to be written
3611  * @cmd_details: pointer to command details structure or NULL
3612  **/
3613 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
3614                                 u8 cmd_flags, void *data, u16 buf_size,
3615                                 u16 element_count,
3616                                 struct i40e_asq_cmd_details *cmd_details)
3617 {
3618         struct i40e_aq_desc desc;
3619         struct i40e_aqc_nvm_config_write *cmd =
3620                 (struct i40e_aqc_nvm_config_write *)&desc.params.raw;
3621         enum i40e_status_code status;
3622
3623         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);
3624         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3625         if (buf_size > I40E_AQ_LARGE_BUF)
3626                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3627
3628         cmd->element_count = CPU_TO_LE16(element_count);
3629         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
3630         status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);
3631
3632         return status;
3633 }
3634
3635 /**
3636  * i40e_aq_oem_post_update - triggers an OEM specific flow after update
3637  * @hw: pointer to the hw struct
3638  * @buff: buffer for result
3639  * @buff_size: buffer size
3640  * @cmd_details: pointer to command details structure or NULL
3641  **/
3642 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
3643                                 void *buff, u16 buff_size,
3644                                 struct i40e_asq_cmd_details *cmd_details)
3645 {
3646         struct i40e_aq_desc desc;
3647         enum i40e_status_code status;
3648
3649         UNREFERENCED_2PARAMETER(buff, buff_size);
3650
3651         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update);
3652         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3653         if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH)
3654                 status = I40E_ERR_NOT_IMPLEMENTED;
3655
3656         return status;
3657 }
3658
3659 /**
3660  * i40e_aq_erase_nvm
3661  * @hw: pointer to the hw struct
3662  * @module_pointer: module pointer location in words from the NVM beginning
3663  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3664  * @length: length of the section to be erased (expressed in 4 KB)
3665  * @last_command: tells if this is the last command in a series
3666  * @cmd_details: pointer to command details structure or NULL
3667  *
3668  * Erase the NVM sector using the admin queue commands
3669  **/
3670 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3671                                 u32 offset, u16 length, bool last_command,
3672                                 struct i40e_asq_cmd_details *cmd_details)
3673 {
3674         struct i40e_aq_desc desc;
3675         struct i40e_aqc_nvm_update *cmd =
3676                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3677         enum i40e_status_code status;
3678
3679         DEBUGFUNC("i40e_aq_erase_nvm");
3680
3681         /* In offset the highest byte must be zeroed. */
3682         if (offset & 0xFF000000) {
3683                 status = I40E_ERR_PARAM;
3684                 goto i40e_aq_erase_nvm_exit;
3685         }
3686
3687         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3688
3689         /* If this is the last command in a series, set the proper flag. */
3690         if (last_command)
3691                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3692         cmd->module_pointer = module_pointer;
3693         cmd->offset = CPU_TO_LE32(offset);
3694         cmd->length = CPU_TO_LE16(length);
3695
3696         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3697
3698 i40e_aq_erase_nvm_exit:
3699         return status;
3700 }
3701
3702 /**
3703  * i40e_parse_discover_capabilities
3704  * @hw: pointer to the hw struct
3705  * @buff: pointer to a buffer containing device/function capability records
3706  * @cap_count: number of capability records in the list
3707  * @list_type_opc: type of capabilities list to parse
3708  *
3709  * Parse the device/function capabilities list.
3710  **/
3711 STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3712                                      u32 cap_count,
3713                                      enum i40e_admin_queue_opc list_type_opc)
3714 {
3715         struct i40e_aqc_list_capabilities_element_resp *cap;
3716         u32 valid_functions, num_functions;
3717         u32 number, logical_id, phys_id;
3718         struct i40e_hw_capabilities *p;
3719         enum i40e_status_code status;
3720         u16 id, ocp_cfg_word0;
3721         u8 major_rev;
3722         u32 i = 0;
3723
3724         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3725
3726         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3727                 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
3728         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3729                 p = (struct i40e_hw_capabilities *)&hw->func_caps;
3730         else
3731                 return;
3732
3733         for (i = 0; i < cap_count; i++, cap++) {
3734                 id = LE16_TO_CPU(cap->id);
3735                 number = LE32_TO_CPU(cap->number);
3736                 logical_id = LE32_TO_CPU(cap->logical_id);
3737                 phys_id = LE32_TO_CPU(cap->phys_id);
3738                 major_rev = cap->major_rev;
3739
3740                 switch (id) {
3741                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3742                         p->switch_mode = number;
3743                         i40e_debug(hw, I40E_DEBUG_INIT,
3744                                    "HW Capability: Switch mode = %d\n",
3745                                    p->switch_mode);
3746                         break;
3747                 case I40E_AQ_CAP_ID_MNG_MODE:
3748                         p->management_mode = number;
3749                         if (major_rev > 1) {
3750                                 p->mng_protocols_over_mctp = logical_id;
3751                                 i40e_debug(hw, I40E_DEBUG_INIT,
3752                                            "HW Capability: Protocols over MCTP = %d\n",
3753                                            p->mng_protocols_over_mctp);
3754                         } else {
3755                                 p->mng_protocols_over_mctp = 0;
3756                         }
3757                         i40e_debug(hw, I40E_DEBUG_INIT,
3758                                    "HW Capability: Management Mode = %d\n",
3759                                    p->management_mode);
3760                         break;
3761                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3762                         p->npar_enable = number;
3763                         i40e_debug(hw, I40E_DEBUG_INIT,
3764                                    "HW Capability: NPAR enable = %d\n",
3765                                    p->npar_enable);
3766                         break;
3767                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3768                         p->os2bmc = number;
3769                         i40e_debug(hw, I40E_DEBUG_INIT,
3770                                    "HW Capability: OS2BMC = %d\n", p->os2bmc);
3771                         break;
3772                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3773                         p->valid_functions = number;
3774                         i40e_debug(hw, I40E_DEBUG_INIT,
3775                                    "HW Capability: Valid Functions = %d\n",
3776                                    p->valid_functions);
3777                         break;
3778                 case I40E_AQ_CAP_ID_SRIOV:
3779                         if (number == 1)
3780                                 p->sr_iov_1_1 = true;
3781                         i40e_debug(hw, I40E_DEBUG_INIT,
3782                                    "HW Capability: SR-IOV = %d\n",
3783                                    p->sr_iov_1_1);
3784                         break;
3785                 case I40E_AQ_CAP_ID_VF:
3786                         p->num_vfs = number;
3787                         p->vf_base_id = logical_id;
3788                         i40e_debug(hw, I40E_DEBUG_INIT,
3789                                    "HW Capability: VF count = %d\n",
3790                                    p->num_vfs);
3791                         i40e_debug(hw, I40E_DEBUG_INIT,
3792                                    "HW Capability: VF base_id = %d\n",
3793                                    p->vf_base_id);
3794                         break;
3795                 case I40E_AQ_CAP_ID_VMDQ:
3796                         if (number == 1)
3797                                 p->vmdq = true;
3798                         i40e_debug(hw, I40E_DEBUG_INIT,
3799                                    "HW Capability: VMDQ = %d\n", p->vmdq);
3800                         break;
3801                 case I40E_AQ_CAP_ID_8021QBG:
3802                         if (number == 1)
3803                                 p->evb_802_1_qbg = true;
3804                         i40e_debug(hw, I40E_DEBUG_INIT,
3805                                    "HW Capability: 802.1Qbg = %d\n", number);
3806                         break;
3807                 case I40E_AQ_CAP_ID_8021QBR:
3808                         if (number == 1)
3809                                 p->evb_802_1_qbh = true;
3810                         i40e_debug(hw, I40E_DEBUG_INIT,
3811                                    "HW Capability: 802.1Qbh = %d\n", number);
3812                         break;
3813                 case I40E_AQ_CAP_ID_VSI:
3814                         p->num_vsis = number;
3815                         i40e_debug(hw, I40E_DEBUG_INIT,
3816                                    "HW Capability: VSI count = %d\n",
3817                                    p->num_vsis);
3818                         break;
3819                 case I40E_AQ_CAP_ID_DCB:
3820                         if (number == 1) {
3821                                 p->dcb = true;
3822                                 p->enabled_tcmap = logical_id;
3823                                 p->maxtc = phys_id;
3824                         }
3825                         i40e_debug(hw, I40E_DEBUG_INIT,
3826                                    "HW Capability: DCB = %d\n", p->dcb);
3827                         i40e_debug(hw, I40E_DEBUG_INIT,
3828                                    "HW Capability: TC Mapping = %d\n",
3829                                    logical_id);
3830                         i40e_debug(hw, I40E_DEBUG_INIT,
3831                                    "HW Capability: TC Max = %d\n", p->maxtc);
3832                         break;
3833                 case I40E_AQ_CAP_ID_FCOE:
3834                         if (number == 1)
3835                                 p->fcoe = true;
3836                         i40e_debug(hw, I40E_DEBUG_INIT,
3837                                    "HW Capability: FCOE = %d\n", p->fcoe);
3838                         break;
3839                 case I40E_AQ_CAP_ID_ISCSI:
3840                         if (number == 1)
3841                                 p->iscsi = true;
3842                         i40e_debug(hw, I40E_DEBUG_INIT,
3843                                    "HW Capability: iSCSI = %d\n", p->iscsi);
3844                         break;
3845                 case I40E_AQ_CAP_ID_RSS:
3846                         p->rss = true;
3847                         p->rss_table_size = number;
3848                         p->rss_table_entry_width = logical_id;
3849                         i40e_debug(hw, I40E_DEBUG_INIT,
3850                                    "HW Capability: RSS = %d\n", p->rss);
3851                         i40e_debug(hw, I40E_DEBUG_INIT,
3852                                    "HW Capability: RSS table size = %d\n",
3853                                    p->rss_table_size);
3854                         i40e_debug(hw, I40E_DEBUG_INIT,
3855                                    "HW Capability: RSS table width = %d\n",
3856                                    p->rss_table_entry_width);
3857                         break;
3858                 case I40E_AQ_CAP_ID_RXQ:
3859                         p->num_rx_qp = number;
3860                         p->base_queue = phys_id;
3861                         i40e_debug(hw, I40E_DEBUG_INIT,
3862                                    "HW Capability: Rx QP = %d\n", number);
3863                         i40e_debug(hw, I40E_DEBUG_INIT,
3864                                    "HW Capability: base_queue = %d\n",
3865                                    p->base_queue);
3866                         break;
3867                 case I40E_AQ_CAP_ID_TXQ:
3868                         p->num_tx_qp = number;
3869                         p->base_queue = phys_id;
3870                         i40e_debug(hw, I40E_DEBUG_INIT,
3871                                    "HW Capability: Tx QP = %d\n", number);
3872                         i40e_debug(hw, I40E_DEBUG_INIT,
3873                                    "HW Capability: base_queue = %d\n",
3874                                    p->base_queue);
3875                         break;
3876                 case I40E_AQ_CAP_ID_MSIX:
3877                         p->num_msix_vectors = number;
3878                         i40e_debug(hw, I40E_DEBUG_INIT,
3879                                    "HW Capability: MSIX vector count = %d\n",
3880                                    p->num_msix_vectors);
3881                         break;
3882                 case I40E_AQ_CAP_ID_VF_MSIX:
3883                         p->num_msix_vectors_vf = number;
3884                         i40e_debug(hw, I40E_DEBUG_INIT,
3885                                    "HW Capability: MSIX VF vector count = %d\n",
3886                                    p->num_msix_vectors_vf);
3887                         break;
3888                 case I40E_AQ_CAP_ID_FLEX10:
3889                         if (major_rev == 1) {
3890                                 if (number == 1) {
3891                                         p->flex10_enable = true;
3892                                         p->flex10_capable = true;
3893                                 }
3894                         } else {
3895                                 /* Capability revision >= 2 */
3896                                 if (number & 1)
3897                                         p->flex10_enable = true;
3898                                 if (number & 2)
3899                                         p->flex10_capable = true;
3900                         }
3901                         p->flex10_mode = logical_id;
3902                         p->flex10_status = phys_id;
3903                         i40e_debug(hw, I40E_DEBUG_INIT,
3904                                    "HW Capability: Flex10 mode = %d\n",
3905                                    p->flex10_mode);
3906                         i40e_debug(hw, I40E_DEBUG_INIT,
3907                                    "HW Capability: Flex10 status = %d\n",
3908                                    p->flex10_status);
3909                         break;
3910                 case I40E_AQ_CAP_ID_CEM:
3911                         if (number == 1)
3912                                 p->mgmt_cem = true;
3913                         i40e_debug(hw, I40E_DEBUG_INIT,
3914                                    "HW Capability: CEM = %d\n", p->mgmt_cem);
3915                         break;
3916                 case I40E_AQ_CAP_ID_IWARP:
3917                         if (number == 1)
3918                                 p->iwarp = true;
3919                         i40e_debug(hw, I40E_DEBUG_INIT,
3920                                    "HW Capability: iWARP = %d\n", p->iwarp);
3921                         break;
3922                 case I40E_AQ_CAP_ID_LED:
3923                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3924                                 p->led[phys_id] = true;
3925                         i40e_debug(hw, I40E_DEBUG_INIT,
3926                                    "HW Capability: LED - PIN %d\n", phys_id);
3927                         break;
3928                 case I40E_AQ_CAP_ID_SDP:
3929                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3930                                 p->sdp[phys_id] = true;
3931                         i40e_debug(hw, I40E_DEBUG_INIT,
3932                                    "HW Capability: SDP - PIN %d\n", phys_id);
3933                         break;
3934                 case I40E_AQ_CAP_ID_MDIO:
3935                         if (number == 1) {
3936                                 p->mdio_port_num = phys_id;
3937                                 p->mdio_port_mode = logical_id;
3938                         }
3939                         i40e_debug(hw, I40E_DEBUG_INIT,
3940                                    "HW Capability: MDIO port number = %d\n",
3941                                    p->mdio_port_num);
3942                         i40e_debug(hw, I40E_DEBUG_INIT,
3943                                    "HW Capability: MDIO port mode = %d\n",
3944                                    p->mdio_port_mode);
3945                         break;
3946                 case I40E_AQ_CAP_ID_1588:
3947                         if (number == 1)
3948                                 p->ieee_1588 = true;
3949                         i40e_debug(hw, I40E_DEBUG_INIT,
3950                                    "HW Capability: IEEE 1588 = %d\n",
3951                                    p->ieee_1588);
3952                         break;
3953                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3954                         p->fd = true;
3955                         p->fd_filters_guaranteed = number;
3956                         p->fd_filters_best_effort = logical_id;
3957                         i40e_debug(hw, I40E_DEBUG_INIT,
3958                                    "HW Capability: Flow Director = 1\n");
3959                         i40e_debug(hw, I40E_DEBUG_INIT,
3960                                    "HW Capability: Guaranteed FD filters = %d\n",
3961                                    p->fd_filters_guaranteed);
3962                         break;
3963                 case I40E_AQ_CAP_ID_WSR_PROT:
3964                         p->wr_csr_prot = (u64)number;
3965                         p->wr_csr_prot |= (u64)logical_id << 32;
3966                         i40e_debug(hw, I40E_DEBUG_INIT,
3967                                    "HW Capability: wr_csr_prot = 0x%llX\n\n",
3968                                    (p->wr_csr_prot & 0xffff));
3969                         break;
3970                 case I40E_AQ_CAP_ID_NVM_MGMT:
3971                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3972                                 p->sec_rev_disabled = true;
3973                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3974                                 p->update_disabled = true;
3975                         break;
3976                 case I40E_AQ_CAP_ID_WOL_AND_PROXY:
3977                         hw->num_wol_proxy_filters = (u16)number;
3978                         hw->wol_proxy_vsi_seid = (u16)logical_id;
3979                         p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
3980                         if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
3981                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
3982                         else
3983                                 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
3984                         p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
3985                         i40e_debug(hw, I40E_DEBUG_INIT,
3986                                    "HW Capability: WOL proxy filters = %d\n",
3987                                    hw->num_wol_proxy_filters);
3988                         break;
3989                 default:
3990                         break;
3991                 }
3992         }
3993
3994         if (p->fcoe)
3995                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3996
3997         /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */
3998         p->fcoe = false;
3999
4000         /* count the enabled ports (aka the "not disabled" ports) */
4001         hw->num_ports = 0;
4002         for (i = 0; i < 4; i++) {
4003                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
4004                 u64 port_cfg = 0;
4005
4006                 /* use AQ read to get the physical register offset instead
4007                  * of the port relative offset
4008                  */
4009                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
4010                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
4011                         hw->num_ports++;
4012         }
4013
4014         /* OCP cards case: if a mezz is removed the ethernet port is at
4015          * disabled state in PRTGEN_CNF register. Additional NVM read is
4016          * needed in order to check if we are dealing with OCP card.
4017          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
4018          * physical ports results in wrong partition id calculation and thus
4019          * not supporting WoL.
4020          */
4021         if (hw->mac.type == I40E_MAC_X722) {
4022                 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) {
4023                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
4024                                                   2 * I40E_SR_OCP_CFG_WORD0,
4025                                                   sizeof(ocp_cfg_word0),
4026                                                   &ocp_cfg_word0, true, NULL);
4027                         if (status == I40E_SUCCESS &&
4028                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
4029                                 hw->num_ports = 4;
4030                         i40e_release_nvm(hw);
4031                 }
4032         }
4033
4034         valid_functions = p->valid_functions;
4035         num_functions = 0;
4036         while (valid_functions) {
4037                 if (valid_functions & 1)
4038                         num_functions++;
4039                 valid_functions >>= 1;
4040         }
4041
4042         /* partition id is 1-based, and functions are evenly spread
4043          * across the ports as partitions
4044          */
4045         if (hw->num_ports != 0) {
4046                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
4047                 hw->num_partitions = num_functions / hw->num_ports;
4048         }
4049
4050         /* additional HW specific goodies that might
4051          * someday be HW version specific
4052          */
4053         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
4054 }
4055
4056 /**
4057  * i40e_aq_discover_capabilities
4058  * @hw: pointer to the hw struct
4059  * @buff: a virtual buffer to hold the capabilities
4060  * @buff_size: Size of the virtual buffer
4061  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
4062  * @list_type_opc: capabilities type to discover - pass in the command opcode
4063  * @cmd_details: pointer to command details structure or NULL
4064  *
4065  * Get the device capabilities descriptions from the firmware
4066  **/
4067 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
4068                                 void *buff, u16 buff_size, u16 *data_size,
4069                                 enum i40e_admin_queue_opc list_type_opc,
4070                                 struct i40e_asq_cmd_details *cmd_details)
4071 {
4072         struct i40e_aqc_list_capabilites *cmd;
4073         struct i40e_aq_desc desc;
4074         enum i40e_status_code status = I40E_SUCCESS;
4075
4076         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
4077
4078         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
4079                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
4080                 status = I40E_ERR_PARAM;
4081                 goto exit;
4082         }
4083
4084         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
4085
4086         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4087         if (buff_size > I40E_AQ_LARGE_BUF)
4088                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4089
4090         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4091         *data_size = LE16_TO_CPU(desc.datalen);
4092
4093         if (status)
4094                 goto exit;
4095
4096         i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),
4097                                          list_type_opc);
4098
4099 exit:
4100         return status;
4101 }
4102
4103 /**
4104  * i40e_aq_update_nvm
4105  * @hw: pointer to the hw struct
4106  * @module_pointer: module pointer location in words from the NVM beginning
4107  * @offset: byte offset from the module beginning
4108  * @length: length of the section to be written (in bytes from the offset)
4109  * @data: command buffer (size [bytes] = length)
4110  * @last_command: tells if this is the last command in a series
4111  * @preservation_flags: Preservation mode flags
4112  * @cmd_details: pointer to command details structure or NULL
4113  *
4114  * Update the NVM using the admin queue commands
4115  **/
4116 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
4117                                 u32 offset, u16 length, void *data,
4118                                 bool last_command, u8 preservation_flags,
4119                                 struct i40e_asq_cmd_details *cmd_details)
4120 {
4121         struct i40e_aq_desc desc;
4122         struct i40e_aqc_nvm_update *cmd =
4123                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
4124         enum i40e_status_code status;
4125
4126         DEBUGFUNC("i40e_aq_update_nvm");
4127
4128         /* In offset the highest byte must be zeroed. */
4129         if (offset & 0xFF000000) {
4130                 status = I40E_ERR_PARAM;
4131                 goto i40e_aq_update_nvm_exit;
4132         }
4133
4134         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4135
4136         /* If this is the last command in a series, set the proper flag. */
4137         if (last_command)
4138                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
4139         if (hw->mac.type == I40E_MAC_X722) {
4140                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
4141                         cmd->command_flags |=
4142                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
4143                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4144                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
4145                         cmd->command_flags |=
4146                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
4147                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
4148         }
4149         cmd->module_pointer = module_pointer;
4150         cmd->offset = CPU_TO_LE32(offset);
4151         cmd->length = CPU_TO_LE16(length);
4152
4153         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4154         if (length > I40E_AQ_LARGE_BUF)
4155                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4156
4157         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
4158
4159 i40e_aq_update_nvm_exit:
4160         return status;
4161 }
4162
4163 /**
4164  * i40e_aq_rearrange_nvm
4165  * @hw: pointer to the hw struct
4166  * @rearrange_nvm: defines direction of rearrangement
4167  * @cmd_details: pointer to command details structure or NULL
4168  *
4169  * Rearrange NVM structure, available only for transition FW
4170  **/
4171 enum i40e_status_code i40e_aq_rearrange_nvm(struct i40e_hw *hw,
4172                                 u8 rearrange_nvm,
4173                                 struct i40e_asq_cmd_details *cmd_details)
4174 {
4175         struct i40e_aqc_nvm_update *cmd;
4176         enum i40e_status_code status;
4177         struct i40e_aq_desc desc;
4178
4179         DEBUGFUNC("i40e_aq_rearrange_nvm");
4180
4181         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
4182
4183         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
4184
4185         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
4186                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
4187
4188         if (!rearrange_nvm) {
4189                 status = I40E_ERR_PARAM;
4190                 goto i40e_aq_rearrange_nvm_exit;
4191         }
4192
4193         cmd->command_flags |= rearrange_nvm;
4194         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4195
4196 i40e_aq_rearrange_nvm_exit:
4197         return status;
4198 }
4199
4200 /**
4201  * i40e_aq_nvm_progress
4202  * @hw: pointer to the hw struct
4203  * @progress: pointer to progress returned from AQ
4204  * @cmd_details: pointer to command details structure or NULL
4205  *
4206  * Gets progress of flash rearrangement process
4207  **/
4208 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress,
4209                                 struct i40e_asq_cmd_details *cmd_details)
4210 {
4211         enum i40e_status_code status;
4212         struct i40e_aq_desc desc;
4213
4214         DEBUGFUNC("i40e_aq_nvm_progress");
4215
4216         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress);
4217         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4218         *progress = desc.params.raw[0];
4219         return status;
4220 }
4221
4222 /**
4223  * i40e_aq_get_lldp_mib
4224  * @hw: pointer to the hw struct
4225  * @bridge_type: type of bridge requested
4226  * @mib_type: Local, Remote or both Local and Remote MIBs
4227  * @buff: pointer to a user supplied buffer to store the MIB block
4228  * @buff_size: size of the buffer (in bytes)
4229  * @local_len : length of the returned Local LLDP MIB
4230  * @remote_len: length of the returned Remote LLDP MIB
4231  * @cmd_details: pointer to command details structure or NULL
4232  *
4233  * Requests the complete LLDP MIB (entire packet).
4234  **/
4235 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
4236                                 u8 mib_type, void *buff, u16 buff_size,
4237                                 u16 *local_len, u16 *remote_len,
4238                                 struct i40e_asq_cmd_details *cmd_details)
4239 {
4240         struct i40e_aq_desc desc;
4241         struct i40e_aqc_lldp_get_mib *cmd =
4242                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4243         struct i40e_aqc_lldp_get_mib *resp =
4244                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
4245         enum i40e_status_code status;
4246
4247         if (buff_size == 0 || !buff)
4248                 return I40E_ERR_PARAM;
4249
4250         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
4251         /* Indirect Command */
4252         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4253
4254         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
4255         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4256                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4257
4258         desc.datalen = CPU_TO_LE16(buff_size);
4259
4260         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4261         if (buff_size > I40E_AQ_LARGE_BUF)
4262                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4263
4264         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4265         if (!status) {
4266                 if (local_len != NULL)
4267                         *local_len = LE16_TO_CPU(resp->local_len);
4268                 if (remote_len != NULL)
4269                         *remote_len = LE16_TO_CPU(resp->remote_len);
4270         }
4271
4272         return status;
4273 }
4274
4275  /**
4276  * i40e_aq_set_lldp_mib - Set the LLDP MIB
4277  * @hw: pointer to the hw struct
4278  * @mib_type: Local, Remote or both Local and Remote MIBs
4279  * @buff: pointer to a user supplied buffer to store the MIB block
4280  * @buff_size: size of the buffer (in bytes)
4281  * @cmd_details: pointer to command details structure or NULL
4282  *
4283  * Set the LLDP MIB.
4284  **/
4285 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
4286                                 u8 mib_type, void *buff, u16 buff_size,
4287                                 struct i40e_asq_cmd_details *cmd_details)
4288 {
4289         struct i40e_aq_desc desc;
4290         struct i40e_aqc_lldp_set_local_mib *cmd =
4291                 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
4292         enum i40e_status_code status;
4293
4294         if (buff_size == 0 || !buff)
4295                 return I40E_ERR_PARAM;
4296
4297         i40e_fill_default_direct_cmd_desc(&desc,
4298                                 i40e_aqc_opc_lldp_set_local_mib);
4299         /* Indirect Command */
4300         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4301         if (buff_size > I40E_AQ_LARGE_BUF)
4302                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4303         desc.datalen = CPU_TO_LE16(buff_size);
4304
4305         cmd->type = mib_type;
4306         cmd->length = CPU_TO_LE16(buff_size);
4307         cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));
4308         cmd->address_low =  CPU_TO_LE32(I40E_LO_DWORD((u64)buff));
4309
4310         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4311         return status;
4312 }
4313
4314 /**
4315  * i40e_aq_cfg_lldp_mib_change_event
4316  * @hw: pointer to the hw struct
4317  * @enable_update: Enable or Disable event posting
4318  * @cmd_details: pointer to command details structure or NULL
4319  *
4320  * Enable or Disable posting of an event on ARQ when LLDP MIB
4321  * associated with the interface changes
4322  **/
4323 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
4324                                 bool enable_update,
4325                                 struct i40e_asq_cmd_details *cmd_details)
4326 {
4327         struct i40e_aq_desc desc;
4328         struct i40e_aqc_lldp_update_mib *cmd =
4329                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
4330         enum i40e_status_code status;
4331
4332         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
4333
4334         if (!enable_update)
4335                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
4336
4337         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4338
4339         return status;
4340 }
4341
4342 /**
4343  * i40e_aq_add_lldp_tlv
4344  * @hw: pointer to the hw struct
4345  * @bridge_type: type of bridge
4346  * @buff: buffer with TLV to add
4347  * @buff_size: length of the buffer
4348  * @tlv_len: length of the TLV to be added
4349  * @mib_len: length of the LLDP MIB returned in response
4350  * @cmd_details: pointer to command details structure or NULL
4351  *
4352  * Add the specified TLV to LLDP Local MIB for the given bridge type,
4353  * it is responsibility of the caller to make sure that the TLV is not
4354  * already present in the LLDPDU.
4355  * In return firmware will write the complete LLDP MIB with the newly
4356  * added TLV in the response buffer.
4357  **/
4358 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
4359                                 void *buff, u16 buff_size, u16 tlv_len,
4360                                 u16 *mib_len,
4361                                 struct i40e_asq_cmd_details *cmd_details)
4362 {
4363         struct i40e_aq_desc desc;
4364         struct i40e_aqc_lldp_add_tlv *cmd =
4365                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4366         enum i40e_status_code status;
4367
4368         if (buff_size == 0 || !buff || tlv_len == 0)
4369                 return I40E_ERR_PARAM;
4370
4371         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);
4372
4373         /* Indirect Command */
4374         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4375         if (buff_size > I40E_AQ_LARGE_BUF)
4376                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4377         desc.datalen = CPU_TO_LE16(buff_size);
4378
4379         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4380                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4381         cmd->len = CPU_TO_LE16(tlv_len);
4382
4383         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4384         if (!status) {
4385                 if (mib_len != NULL)
4386                         *mib_len = LE16_TO_CPU(desc.datalen);
4387         }
4388
4389         return status;
4390 }
4391
4392 /**
4393  * i40e_aq_update_lldp_tlv
4394  * @hw: pointer to the hw struct
4395  * @bridge_type: type of bridge
4396  * @buff: buffer with TLV to update
4397  * @buff_size: size of the buffer holding original and updated TLVs
4398  * @old_len: Length of the Original TLV
4399  * @new_len: Length of the Updated TLV
4400  * @offset: offset of the updated TLV in the buff
4401  * @mib_len: length of the returned LLDP MIB
4402  * @cmd_details: pointer to command details structure or NULL
4403  *
4404  * Update the specified TLV to the LLDP Local MIB for the given bridge type.
4405  * Firmware will place the complete LLDP MIB in response buffer with the
4406  * updated TLV.
4407  **/
4408 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
4409                                 u8 bridge_type, void *buff, u16 buff_size,
4410                                 u16 old_len, u16 new_len, u16 offset,
4411                                 u16 *mib_len,
4412                                 struct i40e_asq_cmd_details *cmd_details)
4413 {
4414         struct i40e_aq_desc desc;
4415         struct i40e_aqc_lldp_update_tlv *cmd =
4416                 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
4417         enum i40e_status_code status;
4418
4419         if (buff_size == 0 || !buff || offset == 0 ||
4420             old_len == 0 || new_len == 0)
4421                 return I40E_ERR_PARAM;
4422
4423         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);
4424
4425         /* Indirect Command */
4426         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4427         if (buff_size > I40E_AQ_LARGE_BUF)
4428                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4429         desc.datalen = CPU_TO_LE16(buff_size);
4430
4431         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4432                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4433         cmd->old_len = CPU_TO_LE16(old_len);
4434         cmd->new_offset = CPU_TO_LE16(offset);
4435         cmd->new_len = CPU_TO_LE16(new_len);
4436
4437         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4438         if (!status) {
4439                 if (mib_len != NULL)
4440                         *mib_len = LE16_TO_CPU(desc.datalen);
4441         }
4442
4443         return status;
4444 }
4445
4446 /**
4447  * i40e_aq_delete_lldp_tlv
4448  * @hw: pointer to the hw struct
4449  * @bridge_type: type of bridge
4450  * @buff: pointer to a user supplied buffer that has the TLV
4451  * @buff_size: length of the buffer
4452  * @tlv_len: length of the TLV to be deleted
4453  * @mib_len: length of the returned LLDP MIB
4454  * @cmd_details: pointer to command details structure or NULL
4455  *
4456  * Delete the specified TLV from LLDP Local MIB for the given bridge type.
4457  * The firmware places the entire LLDP MIB in the response buffer.
4458  **/
4459 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
4460                                 u8 bridge_type, void *buff, u16 buff_size,
4461                                 u16 tlv_len, u16 *mib_len,
4462                                 struct i40e_asq_cmd_details *cmd_details)
4463 {
4464         struct i40e_aq_desc desc;
4465         struct i40e_aqc_lldp_add_tlv *cmd =
4466                 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
4467         enum i40e_status_code status;
4468
4469         if (buff_size == 0 || !buff)
4470                 return I40E_ERR_PARAM;
4471
4472         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);
4473
4474         /* Indirect Command */
4475         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4476         if (buff_size > I40E_AQ_LARGE_BUF)
4477                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4478         desc.datalen = CPU_TO_LE16(buff_size);
4479         cmd->len = CPU_TO_LE16(tlv_len);
4480         cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
4481                       I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
4482
4483         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4484         if (!status) {
4485                 if (mib_len != NULL)
4486                         *mib_len = LE16_TO_CPU(desc.datalen);
4487         }
4488
4489         return status;
4490 }
4491
4492 /**
4493  * i40e_aq_stop_lldp
4494  * @hw: pointer to the hw struct
4495  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
4496  * @cmd_details: pointer to command details structure or NULL
4497  *
4498  * Stop or Shutdown the embedded LLDP Agent
4499  **/
4500 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
4501                                 struct i40e_asq_cmd_details *cmd_details)
4502 {
4503         struct i40e_aq_desc desc;
4504         struct i40e_aqc_lldp_stop *cmd =
4505                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
4506         enum i40e_status_code status;
4507
4508         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
4509
4510         if (shutdown_agent)
4511                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
4512
4513         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4514
4515         return status;
4516 }
4517
4518 /**
4519  * i40e_aq_start_lldp
4520  * @hw: pointer to the hw struct
4521  * @cmd_details: pointer to command details structure or NULL
4522  *
4523  * Start the embedded LLDP Agent on all ports.
4524  **/
4525 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
4526                                 struct i40e_asq_cmd_details *cmd_details)
4527 {
4528         struct i40e_aq_desc desc;
4529         struct i40e_aqc_lldp_start *cmd =
4530                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
4531         enum i40e_status_code status;
4532
4533         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
4534
4535         cmd->command = I40E_AQ_LLDP_AGENT_START;
4536         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4537
4538         return status;
4539 }
4540
4541 /**
4542  * i40e_aq_set_dcb_parameters
4543  * @hw: pointer to the hw struct
4544  * @cmd_details: pointer to command details structure or NULL
4545  * @dcb_enable: True if DCB configuration needs to be applied
4546  *
4547  **/
4548 enum i40e_status_code
4549 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
4550                            struct i40e_asq_cmd_details *cmd_details)
4551 {
4552         struct i40e_aq_desc desc;
4553         struct i40e_aqc_set_dcb_parameters *cmd =
4554                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
4555         enum i40e_status_code status;
4556
4557         if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
4558                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
4559
4560         i40e_fill_default_direct_cmd_desc(&desc,
4561                                           i40e_aqc_opc_set_dcb_parameters);
4562
4563         if (dcb_enable) {
4564                 cmd->valid_flags = I40E_DCB_VALID;
4565                 cmd->command = I40E_AQ_DCB_SET_AGENT;
4566         }
4567         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4568
4569         return status;
4570 }
4571
4572 /**
4573  * i40e_aq_get_cee_dcb_config
4574  * @hw: pointer to the hw struct
4575  * @buff: response buffer that stores CEE operational configuration
4576  * @buff_size: size of the buffer passed
4577  * @cmd_details: pointer to command details structure or NULL
4578  *
4579  * Get CEE DCBX mode operational configuration from firmware
4580  **/
4581 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
4582                                 void *buff, u16 buff_size,
4583                                 struct i40e_asq_cmd_details *cmd_details)
4584 {
4585         struct i40e_aq_desc desc;
4586         enum i40e_status_code status;
4587
4588         if (buff_size == 0 || !buff)
4589                 return I40E_ERR_PARAM;
4590
4591         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
4592
4593         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4594         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
4595                                        cmd_details);
4596
4597         return status;
4598 }
4599
4600 /**
4601  * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW
4602  * @hw: pointer to the hw struct
4603  * @start_agent: True if DCBx Agent needs to be Started
4604  *                              False if DCBx Agent needs to be Stopped
4605  * @cmd_details: pointer to command details structure or NULL
4606  *
4607  * Start/Stop the embedded dcbx Agent
4608  **/
4609 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
4610                                 bool start_agent,
4611                                 struct i40e_asq_cmd_details *cmd_details)
4612 {
4613         struct i40e_aq_desc desc;
4614         struct i40e_aqc_lldp_stop_start_specific_agent *cmd =
4615                 (struct i40e_aqc_lldp_stop_start_specific_agent *)
4616                                 &desc.params.raw;
4617         enum i40e_status_code status;
4618
4619         i40e_fill_default_direct_cmd_desc(&desc,
4620                                 i40e_aqc_opc_lldp_stop_start_spec_agent);
4621
4622         if (start_agent)
4623                 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;
4624
4625         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4626
4627         return status;
4628 }
4629
4630 /**
4631  * i40e_aq_add_udp_tunnel
4632  * @hw: pointer to the hw struct
4633  * @udp_port: the UDP port to add in Host byte order
4634  * @protocol_index: protocol index type
4635  * @filter_index: pointer to filter index
4636  * @cmd_details: pointer to command details structure or NULL
4637  *
4638  * Note: Firmware expects the udp_port value to be in Little Endian format,
4639  * and this function will call CPU_TO_LE16 to convert from Host byte order to
4640  * Little Endian order.
4641  **/
4642 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
4643                                 u16 udp_port, u8 protocol_index,
4644                                 u8 *filter_index,
4645                                 struct i40e_asq_cmd_details *cmd_details)
4646 {
4647         struct i40e_aq_desc desc;
4648         struct i40e_aqc_add_udp_tunnel *cmd =
4649                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
4650         struct i40e_aqc_del_udp_tunnel_completion *resp =
4651                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
4652         enum i40e_status_code status;
4653
4654         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
4655
4656         cmd->udp_port = CPU_TO_LE16(udp_port);
4657         cmd->protocol_type = protocol_index;
4658
4659         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4660
4661         if (!status && filter_index)
4662                 *filter_index = resp->index;
4663
4664         return status;
4665 }
4666
4667 /**
4668  * i40e_aq_del_udp_tunnel
4669  * @hw: pointer to the hw struct
4670  * @index: filter index
4671  * @cmd_details: pointer to command details structure or NULL
4672  **/
4673 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
4674                                 struct i40e_asq_cmd_details *cmd_details)
4675 {
4676         struct i40e_aq_desc desc;
4677         struct i40e_aqc_remove_udp_tunnel *cmd =
4678                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
4679         enum i40e_status_code status;
4680
4681         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
4682
4683         cmd->index = index;
4684
4685         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4686
4687         return status;
4688 }
4689
4690 /**
4691  * i40e_aq_get_switch_resource_alloc (0x0204)
4692  * @hw: pointer to the hw struct
4693  * @num_entries: pointer to u8 to store the number of resource entries returned
4694  * @buf: pointer to a user supplied buffer.  This buffer must be large enough
4695  *        to store the resource information for all resource types.  Each
4696  *        resource type is a i40e_aqc_switch_resource_alloc_data structure.
4697  * @count: size, in bytes, of the buffer provided
4698  * @cmd_details: pointer to command details structure or NULL
4699  *
4700  * Query the resources allocated to a function.
4701  **/
4702 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
4703                         u8 *num_entries,
4704                         struct i40e_aqc_switch_resource_alloc_element_resp *buf,
4705                         u16 count,
4706                         struct i40e_asq_cmd_details *cmd_details)
4707 {
4708         struct i40e_aq_desc desc;
4709         struct i40e_aqc_get_switch_resource_alloc *cmd_resp =
4710                 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;
4711         enum i40e_status_code status;
4712         u16 length = count * sizeof(*buf);
4713
4714         i40e_fill_default_direct_cmd_desc(&desc,
4715                                         i40e_aqc_opc_get_switch_resource_alloc);
4716
4717         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
4718         if (length > I40E_AQ_LARGE_BUF)
4719                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4720
4721         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4722
4723         if (!status && num_entries)
4724                 *num_entries = cmd_resp->num_entries;
4725
4726         return status;
4727 }
4728
4729 /**
4730  * i40e_aq_delete_element - Delete switch element
4731  * @hw: pointer to the hw struct
4732  * @seid: the SEID to delete from the switch
4733  * @cmd_details: pointer to command details structure or NULL
4734  *
4735  * This deletes a switch element from the switch.
4736  **/
4737 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
4738                                 struct i40e_asq_cmd_details *cmd_details)
4739 {
4740         struct i40e_aq_desc desc;
4741         struct i40e_aqc_switch_seid *cmd =
4742                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
4743         enum i40e_status_code status;
4744
4745         if (seid == 0)
4746                 return I40E_ERR_PARAM;
4747
4748         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
4749
4750         cmd->seid = CPU_TO_LE16(seid);
4751
4752         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4753
4754         return status;
4755 }
4756
4757 /**
4758  * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
4759  * @hw: pointer to the hw struct
4760  * @flags: component flags
4761  * @mac_seid: uplink seid (MAC SEID)
4762  * @vsi_seid: connected vsi seid
4763  * @ret_seid: seid of create pv component
4764  *
4765  * This instantiates an i40e port virtualizer with specified flags.
4766  * Depending on specified flags the port virtualizer can act as a
4767  * 802.1Qbr port virtualizer or a 802.1Qbg S-component.
4768  */
4769 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
4770                                        u16 mac_seid, u16 vsi_seid,
4771                                        u16 *ret_seid)
4772 {
4773         struct i40e_aq_desc desc;
4774         struct i40e_aqc_add_update_pv *cmd =
4775                 (struct i40e_aqc_add_update_pv *)&desc.params.raw;
4776         struct i40e_aqc_add_update_pv_completion *resp =
4777                 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;
4778         enum i40e_status_code status;
4779
4780         if (vsi_seid == 0)
4781                 return I40E_ERR_PARAM;
4782
4783         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);
4784         cmd->command_flags = CPU_TO_LE16(flags);
4785         cmd->uplink_seid = CPU_TO_LE16(mac_seid);
4786         cmd->connected_seid = CPU_TO_LE16(vsi_seid);
4787
4788         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4789         if (!status && ret_seid)
4790                 *ret_seid = LE16_TO_CPU(resp->pv_seid);
4791
4792         return status;
4793 }
4794
4795 /**
4796  * i40e_aq_add_tag - Add an S/E-tag
4797  * @hw: pointer to the hw struct
4798  * @direct_to_queue: should s-tag direct flow to a specific queue
4799  * @vsi_seid: VSI SEID to use this tag
4800  * @tag: value of the tag
4801  * @queue_num: queue number, only valid is direct_to_queue is true
4802  * @tags_used: return value, number of tags in use by this PF
4803  * @tags_free: return value, number of unallocated tags
4804  * @cmd_details: pointer to command details structure or NULL
4805  *
4806  * This associates an S- or E-tag to a VSI in the switch complex.  It returns
4807  * the number of tags allocated by the PF, and the number of unallocated
4808  * tags available.
4809  **/
4810 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
4811                                 u16 vsi_seid, u16 tag, u16 queue_num,
4812                                 u16 *tags_used, u16 *tags_free,
4813                                 struct i40e_asq_cmd_details *cmd_details)
4814 {
4815         struct i40e_aq_desc desc;
4816         struct i40e_aqc_add_tag *cmd =
4817                 (struct i40e_aqc_add_tag *)&desc.params.raw;
4818         struct i40e_aqc_add_remove_tag_completion *resp =
4819                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4820         enum i40e_status_code status;
4821
4822         if (vsi_seid == 0)
4823                 return I40E_ERR_PARAM;
4824
4825         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);
4826
4827         cmd->seid = CPU_TO_LE16(vsi_seid);
4828         cmd->tag = CPU_TO_LE16(tag);
4829         if (direct_to_queue) {
4830                 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);
4831                 cmd->queue_number = CPU_TO_LE16(queue_num);
4832         }
4833
4834         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4835
4836         if (!status) {
4837                 if (tags_used != NULL)
4838                         *tags_used = LE16_TO_CPU(resp->tags_used);
4839                 if (tags_free != NULL)
4840                         *tags_free = LE16_TO_CPU(resp->tags_free);
4841         }
4842
4843         return status;
4844 }
4845
4846 /**
4847  * i40e_aq_remove_tag - Remove an S- or E-tag
4848  * @hw: pointer to the hw struct
4849  * @vsi_seid: VSI SEID this tag is associated with
4850  * @tag: value of the S-tag to delete
4851  * @tags_used: return value, number of tags in use by this PF
4852  * @tags_free: return value, number of unallocated tags
4853  * @cmd_details: pointer to command details structure or NULL
4854  *
4855  * This deletes an S- or E-tag from a VSI in the switch complex.  It returns
4856  * the number of tags allocated by the PF, and the number of unallocated
4857  * tags available.
4858  **/
4859 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
4860                                 u16 tag, u16 *tags_used, u16 *tags_free,
4861                                 struct i40e_asq_cmd_details *cmd_details)
4862 {
4863         struct i40e_aq_desc desc;
4864         struct i40e_aqc_remove_tag *cmd =
4865                 (struct i40e_aqc_remove_tag *)&desc.params.raw;
4866         struct i40e_aqc_add_remove_tag_completion *resp =
4867                 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;
4868         enum i40e_status_code status;
4869
4870         if (vsi_seid == 0)
4871                 return I40E_ERR_PARAM;
4872
4873         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);
4874
4875         cmd->seid = CPU_TO_LE16(vsi_seid);
4876         cmd->tag = CPU_TO_LE16(tag);
4877
4878         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4879
4880         if (!status) {
4881                 if (tags_used != NULL)
4882                         *tags_used = LE16_TO_CPU(resp->tags_used);
4883                 if (tags_free != NULL)
4884                         *tags_free = LE16_TO_CPU(resp->tags_free);
4885         }
4886
4887         return status;
4888 }
4889
4890 /**
4891  * i40e_aq_add_mcast_etag - Add a multicast E-tag
4892  * @hw: pointer to the hw struct
4893  * @pv_seid: Port Virtualizer of this SEID to associate E-tag with
4894  * @etag: value of E-tag to add
4895  * @num_tags_in_buf: number of unicast E-tags in indirect buffer
4896  * @buf: address of indirect buffer
4897  * @tags_used: return value, number of E-tags in use by this port
4898  * @tags_free: return value, number of unallocated M-tags
4899  * @cmd_details: pointer to command details structure or NULL
4900  *
4901  * This associates a multicast E-tag to a port virtualizer.  It will return
4902  * the number of tags allocated by the PF, and the number of unallocated
4903  * tags available.
4904  *
4905  * The indirect buffer pointed to by buf is a list of 2-byte E-tags,
4906  * num_tags_in_buf long.
4907  **/
4908 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4909                                 u16 etag, u8 num_tags_in_buf, void *buf,
4910                                 u16 *tags_used, u16 *tags_free,
4911                                 struct i40e_asq_cmd_details *cmd_details)
4912 {
4913         struct i40e_aq_desc desc;
4914         struct i40e_aqc_add_remove_mcast_etag *cmd =
4915                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4916         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4917            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4918         enum i40e_status_code status;
4919         u16 length = sizeof(u16) * num_tags_in_buf;
4920
4921         if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))
4922                 return I40E_ERR_PARAM;
4923
4924         i40e_fill_default_direct_cmd_desc(&desc,
4925                                           i40e_aqc_opc_add_multicast_etag);
4926
4927         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4928         cmd->etag = CPU_TO_LE16(etag);
4929         cmd->num_unicast_etags = num_tags_in_buf;
4930
4931         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
4932         if (length > I40E_AQ_LARGE_BUF)
4933                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
4934
4935         status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);
4936
4937         if (!status) {
4938                 if (tags_used != NULL)
4939                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4940                 if (tags_free != NULL)
4941                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4942         }
4943
4944         return status;
4945 }
4946
4947 /**
4948  * i40e_aq_remove_mcast_etag - Remove a multicast E-tag
4949  * @hw: pointer to the hw struct
4950  * @pv_seid: Port Virtualizer SEID this M-tag is associated with
4951  * @etag: value of the E-tag to remove
4952  * @tags_used: return value, number of tags in use by this port
4953  * @tags_free: return value, number of unallocated tags
4954  * @cmd_details: pointer to command details structure or NULL
4955  *
4956  * This deletes an E-tag from the port virtualizer.  It will return
4957  * the number of tags allocated by the port, and the number of unallocated
4958  * tags available.
4959  **/
4960 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
4961                                 u16 etag, u16 *tags_used, u16 *tags_free,
4962                                 struct i40e_asq_cmd_details *cmd_details)
4963 {
4964         struct i40e_aq_desc desc;
4965         struct i40e_aqc_add_remove_mcast_etag *cmd =
4966                 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;
4967         struct i40e_aqc_add_remove_mcast_etag_completion *resp =
4968            (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;
4969         enum i40e_status_code status;
4970
4971
4972         if (pv_seid == 0)
4973                 return I40E_ERR_PARAM;
4974
4975         i40e_fill_default_direct_cmd_desc(&desc,
4976                                           i40e_aqc_opc_remove_multicast_etag);
4977
4978         cmd->pv_seid = CPU_TO_LE16(pv_seid);
4979         cmd->etag = CPU_TO_LE16(etag);
4980
4981         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4982
4983         if (!status) {
4984                 if (tags_used != NULL)
4985                         *tags_used = LE16_TO_CPU(resp->mcast_etags_used);
4986                 if (tags_free != NULL)
4987                         *tags_free = LE16_TO_CPU(resp->mcast_etags_free);
4988         }
4989
4990         return status;
4991 }
4992
4993 /**
4994  * i40e_aq_update_tag - Update an S/E-tag
4995  * @hw: pointer to the hw struct
4996  * @vsi_seid: VSI SEID using this S-tag
4997  * @old_tag: old tag value
4998  * @new_tag: new tag value
4999  * @tags_used: return value, number of tags in use by this PF
5000  * @tags_free: return value, number of unallocated tags
5001  * @cmd_details: pointer to command details structure or NULL
5002  *
5003  * This updates the value of the tag currently attached to this VSI
5004  * in the switch complex.  It will return the number of tags allocated
5005  * by the PF, and the number of unallocated tags available.
5006  **/
5007 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
5008                                 u16 old_tag, u16 new_tag, u16 *tags_used,
5009                                 u16 *tags_free,
5010                                 struct i40e_asq_cmd_details *cmd_details)
5011 {
5012         struct i40e_aq_desc desc;
5013         struct i40e_aqc_update_tag *cmd =
5014                 (struct i40e_aqc_update_tag *)&desc.params.raw;
5015         struct i40e_aqc_update_tag_completion *resp =
5016                 (struct i40e_aqc_update_tag_completion *)&desc.params.raw;
5017         enum i40e_status_code status;
5018
5019         if (vsi_seid == 0)
5020                 return I40E_ERR_PARAM;
5021
5022         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);
5023
5024         cmd->seid = CPU_TO_LE16(vsi_seid);
5025         cmd->old_tag = CPU_TO_LE16(old_tag);
5026         cmd->new_tag = CPU_TO_LE16(new_tag);
5027
5028         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5029
5030         if (!status) {
5031                 if (tags_used != NULL)
5032                         *tags_used = LE16_TO_CPU(resp->tags_used);
5033                 if (tags_free != NULL)
5034                         *tags_free = LE16_TO_CPU(resp->tags_free);
5035         }
5036
5037         return status;
5038 }
5039
5040 /**
5041  * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs
5042  * @hw: pointer to the hw struct
5043  * @tcmap: TC map for request/release any ignore PFC condition
5044  * @request: request or release ignore PFC condition
5045  * @tcmap_ret: return TCs for which PFC is currently ignored
5046  * @cmd_details: pointer to command details structure or NULL
5047  *
5048  * This sends out request/release to ignore PFC condition for a TC.
5049  * It will return the TCs for which PFC is currently ignored.
5050  **/
5051 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,
5052                                 bool request, u8 *tcmap_ret,
5053                                 struct i40e_asq_cmd_details *cmd_details)
5054 {
5055         struct i40e_aq_desc desc;
5056         struct i40e_aqc_pfc_ignore *cmd_resp =
5057                 (struct i40e_aqc_pfc_ignore *)&desc.params.raw;
5058         enum i40e_status_code status;
5059
5060         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);
5061
5062         if (request)
5063                 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;
5064
5065         cmd_resp->tc_bitmap = tcmap;
5066
5067         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5068
5069         if (!status) {
5070                 if (tcmap_ret != NULL)
5071                         *tcmap_ret = cmd_resp->tc_bitmap;
5072         }
5073
5074         return status;
5075 }
5076
5077 /**
5078  * i40e_aq_dcb_updated - DCB Updated Command
5079  * @hw: pointer to the hw struct
5080  * @cmd_details: pointer to command details structure or NULL
5081  *
5082  * When LLDP is handled in PF this command is used by the PF
5083  * to notify EMP that a DCB setting is modified.
5084  * When LLDP is handled in EMP this command is used by the PF
5085  * to notify EMP whenever one of the following parameters get
5086  * modified:
5087  *   - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA
5088  *   - PCIRTT in PRTDCB_GENC.PCIRTT
5089  *   - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.
5090  * EMP will return when the shared RPB settings have been
5091  * recomputed and modified. The retval field in the descriptor
5092  * will be set to 0 when RPB is modified.
5093  **/
5094 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
5095                                 struct i40e_asq_cmd_details *cmd_details)
5096 {
5097         struct i40e_aq_desc desc;
5098         enum i40e_status_code status;
5099
5100         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
5101
5102         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5103
5104         return status;
5105 }
5106
5107 /**
5108  * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.
5109  * @hw: pointer to the hw struct
5110  * @seid: defines the SEID of the switch for which the stats are requested
5111  * @vlan_id: the VLAN ID for which the statistics are requested
5112  * @stat_index: index of the statistics counters block assigned to this VLAN
5113  * @cmd_details: pointer to command details structure or NULL
5114  *
5115  * XL710 supports 128 smonVlanStats counters.This command is used to
5116  * allocate a set of smonVlanStats counters to a specific VLAN in a specific
5117  * switch.
5118  **/
5119 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
5120                                 u16 vlan_id, u16 *stat_index,
5121                                 struct i40e_asq_cmd_details *cmd_details)
5122 {
5123         struct i40e_aq_desc desc;
5124         struct i40e_aqc_add_remove_statistics *cmd_resp =
5125                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5126         enum i40e_status_code status;
5127
5128         if ((seid == 0) || (stat_index == NULL))
5129                 return I40E_ERR_PARAM;
5130
5131         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);
5132
5133         cmd_resp->seid = CPU_TO_LE16(seid);
5134         cmd_resp->vlan = CPU_TO_LE16(vlan_id);
5135
5136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5137
5138         if (!status && stat_index)
5139                 *stat_index = LE16_TO_CPU(cmd_resp->stat_index);
5140
5141         return status;
5142 }
5143
5144 /**
5145  * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.
5146  * @hw: pointer to the hw struct
5147  * @seid: defines the SEID of the switch for which the stats are requested
5148  * @vlan_id: the VLAN ID for which the statistics are requested
5149  * @stat_index: index of the statistics counters block assigned to this VLAN
5150  * @cmd_details: pointer to command details structure or NULL
5151  *
5152  * XL710 supports 128 smonVlanStats counters.This command is used to
5153  * deallocate a set of smonVlanStats counters to a specific VLAN in a specific
5154  * switch.
5155  **/
5156 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
5157                                 u16 vlan_id, u16 stat_index,
5158                                 struct i40e_asq_cmd_details *cmd_details)
5159 {
5160         struct i40e_aq_desc desc;
5161         struct i40e_aqc_add_remove_statistics *cmd =
5162                 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw;
5163         enum i40e_status_code status;
5164
5165         if (seid == 0)
5166                 return I40E_ERR_PARAM;
5167
5168         i40e_fill_default_direct_cmd_desc(&desc,
5169                                           i40e_aqc_opc_remove_statistics);
5170
5171         cmd->seid = CPU_TO_LE16(seid);
5172         cmd->vlan  = CPU_TO_LE16(vlan_id);
5173         cmd->stat_index = CPU_TO_LE16(stat_index);
5174
5175         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5176
5177         return status;
5178 }
5179
5180 /**
5181  * i40e_aq_set_port_parameters - set physical port parameters.
5182  * @hw: pointer to the hw struct
5183  * @bad_frame_vsi: defines the VSI to which bad frames are forwarded
5184  * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI
5185  * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded
5186  * @double_vlan: if set double VLAN is enabled
5187  * @cmd_details: pointer to command details structure or NULL
5188  **/
5189 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
5190                                 u16 bad_frame_vsi, bool save_bad_pac,
5191                                 bool pad_short_pac, bool double_vlan,
5192                                 struct i40e_asq_cmd_details *cmd_details)
5193 {
5194         struct i40e_aqc_set_port_parameters *cmd;
5195         enum i40e_status_code status;
5196         struct i40e_aq_desc desc;
5197         u16 command_flags = 0;
5198
5199         cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;
5200
5201         i40e_fill_default_direct_cmd_desc(&desc,
5202                                           i40e_aqc_opc_set_port_parameters);
5203
5204         cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);
5205         if (save_bad_pac)
5206                 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;
5207         if (pad_short_pac)
5208                 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;
5209         if (double_vlan)
5210                 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;
5211         cmd->command_flags = CPU_TO_LE16(command_flags);
5212
5213         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5214
5215         return status;
5216 }
5217
5218 /**
5219  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
5220  * @hw: pointer to the hw struct
5221  * @seid: seid for the physical port/switching component/vsi
5222  * @buff: Indirect buffer to hold data parameters and response
5223  * @buff_size: Indirect buffer size
5224  * @opcode: Tx scheduler AQ command opcode
5225  * @cmd_details: pointer to command details structure or NULL
5226  *
5227  * Generic command handler for Tx scheduler AQ commands
5228  **/
5229 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
5230                                 void *buff, u16 buff_size,
5231                                  enum i40e_admin_queue_opc opcode,
5232                                 struct i40e_asq_cmd_details *cmd_details)
5233 {
5234         struct i40e_aq_desc desc;
5235         struct i40e_aqc_tx_sched_ind *cmd =
5236                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
5237         enum i40e_status_code status;
5238         bool cmd_param_flag = false;
5239
5240         switch (opcode) {
5241         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
5242         case i40e_aqc_opc_configure_vsi_tc_bw:
5243         case i40e_aqc_opc_enable_switching_comp_ets:
5244         case i40e_aqc_opc_modify_switching_comp_ets:
5245         case i40e_aqc_opc_disable_switching_comp_ets:
5246         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
5247         case i40e_aqc_opc_configure_switching_comp_bw_config:
5248                 cmd_param_flag = true;
5249                 break;
5250         case i40e_aqc_opc_query_vsi_bw_config:
5251         case i40e_aqc_opc_query_vsi_ets_sla_config:
5252         case i40e_aqc_opc_query_switching_comp_ets_config:
5253         case i40e_aqc_opc_query_port_ets_config:
5254         case i40e_aqc_opc_query_switching_comp_bw_config:
5255                 cmd_param_flag = false;
5256                 break;
5257         default:
5258                 return I40E_ERR_PARAM;
5259         }
5260
5261         i40e_fill_default_direct_cmd_desc(&desc, opcode);
5262
5263         /* Indirect command */
5264         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
5265         if (cmd_param_flag)
5266                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
5267         if (buff_size > I40E_AQ_LARGE_BUF)
5268                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
5269
5270         desc.datalen = CPU_TO_LE16(buff_size);
5271
5272         cmd->vsi_seid = CPU_TO_LE16(seid);
5273
5274         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5275
5276         return status;
5277 }
5278
5279 /**
5280  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
5281  * @hw: pointer to the hw struct
5282  * @seid: VSI seid
5283  * @credit: BW limit credits (0 = disabled)
5284  * @max_credit: Max BW limit credits
5285  * @cmd_details: pointer to command details structure or NULL
5286  **/
5287 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
5288                                 u16 seid, u16 credit, u8 max_credit,
5289                                 struct i40e_asq_cmd_details *cmd_details)
5290 {
5291         struct i40e_aq_desc desc;
5292         struct i40e_aqc_configure_vsi_bw_limit *cmd =
5293                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
5294         enum i40e_status_code status;
5295
5296         i40e_fill_default_direct_cmd_desc(&desc,
5297                                           i40e_aqc_opc_configure_vsi_bw_limit);
5298
5299         cmd->vsi_seid = CPU_TO_LE16(seid);
5300         cmd->credit = CPU_TO_LE16(credit);
5301         cmd->max_credit = max_credit;
5302
5303         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5304
5305         return status;
5306 }
5307
5308 /**
5309  * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit
5310  * @hw: pointer to the hw struct
5311  * @seid: switching component seid
5312  * @credit: BW limit credits (0 = disabled)
5313  * @max_bw: Max BW limit credits
5314  * @cmd_details: pointer to command details structure or NULL
5315  **/
5316 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
5317                                 u16 seid, u16 credit, u8 max_bw,
5318                                 struct i40e_asq_cmd_details *cmd_details)
5319 {
5320         struct i40e_aq_desc desc;
5321         struct i40e_aqc_configure_switching_comp_bw_limit *cmd =
5322           (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;
5323         enum i40e_status_code status;
5324
5325         i40e_fill_default_direct_cmd_desc(&desc,
5326                                 i40e_aqc_opc_configure_switching_comp_bw_limit);
5327
5328         cmd->seid = CPU_TO_LE16(seid);
5329         cmd->credit = CPU_TO_LE16(credit);
5330         cmd->max_bw = max_bw;
5331
5332         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5333
5334         return status;
5335 }
5336
5337 /**
5338  * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC
5339  * @hw: pointer to the hw struct
5340  * @seid: VSI seid
5341  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5342  * @cmd_details: pointer to command details structure or NULL
5343  **/
5344 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
5345                         u16 seid,
5346                         struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
5347                         struct i40e_asq_cmd_details *cmd_details)
5348 {
5349         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5350                                     i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,
5351                                     cmd_details);
5352 }
5353
5354 /**
5355  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
5356  * @hw: pointer to the hw struct
5357  * @seid: VSI seid
5358  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
5359  * @cmd_details: pointer to command details structure or NULL
5360  **/
5361 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
5362                         u16 seid,
5363                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
5364                         struct i40e_asq_cmd_details *cmd_details)
5365 {
5366         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5367                                     i40e_aqc_opc_configure_vsi_tc_bw,
5368                                     cmd_details);
5369 }
5370
5371 /**
5372  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
5373  * @hw: pointer to the hw struct
5374  * @seid: seid of the switching component connected to Physical Port
5375  * @ets_data: Buffer holding ETS parameters
5376  * @opcode: Tx scheduler AQ command opcode
5377  * @cmd_details: pointer to command details structure or NULL
5378  **/
5379 enum i40e_status_code i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
5380                 u16 seid,
5381                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
5382                 enum i40e_admin_queue_opc opcode,
5383                 struct i40e_asq_cmd_details *cmd_details)
5384 {
5385         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
5386                                     sizeof(*ets_data), opcode, cmd_details);
5387 }
5388
5389 /**
5390  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
5391  * @hw: pointer to the hw struct
5392  * @seid: seid of the switching component
5393  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
5394  * @cmd_details: pointer to command details structure or NULL
5395  **/
5396 enum i40e_status_code i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
5397         u16 seid,
5398         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
5399         struct i40e_asq_cmd_details *cmd_details)
5400 {
5401         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5402                             i40e_aqc_opc_configure_switching_comp_bw_config,
5403                             cmd_details);
5404 }
5405
5406 /**
5407  * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC
5408  * @hw: pointer to the hw struct
5409  * @seid: seid of the switching component
5410  * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits
5411  * @cmd_details: pointer to command details structure or NULL
5412  **/
5413 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
5414         struct i40e_hw *hw, u16 seid,
5415         struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
5416         struct i40e_asq_cmd_details *cmd_details)
5417 {
5418         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5419                             i40e_aqc_opc_configure_switching_comp_ets_bw_limit,
5420                             cmd_details);
5421 }
5422
5423 /**
5424  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
5425  * @hw: pointer to the hw struct
5426  * @seid: seid of the VSI
5427  * @bw_data: Buffer to hold VSI BW configuration
5428  * @cmd_details: pointer to command details structure or NULL
5429  **/
5430 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
5431                         u16 seid,
5432                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
5433                         struct i40e_asq_cmd_details *cmd_details)
5434 {
5435         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5436                                     i40e_aqc_opc_query_vsi_bw_config,
5437                                     cmd_details);
5438 }
5439
5440 /**
5441  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
5442  * @hw: pointer to the hw struct
5443  * @seid: seid of the VSI
5444  * @bw_data: Buffer to hold VSI BW configuration per TC
5445  * @cmd_details: pointer to command details structure or NULL
5446  **/
5447 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
5448                         u16 seid,
5449                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
5450                         struct i40e_asq_cmd_details *cmd_details)
5451 {
5452         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5453                                     i40e_aqc_opc_query_vsi_ets_sla_config,
5454                                     cmd_details);
5455 }
5456
5457 /**
5458  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
5459  * @hw: pointer to the hw struct
5460  * @seid: seid of the switching component
5461  * @bw_data: Buffer to hold switching component's per TC BW config
5462  * @cmd_details: pointer to command details structure or NULL
5463  **/
5464 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
5465                 u16 seid,
5466                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
5467                 struct i40e_asq_cmd_details *cmd_details)
5468 {
5469         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5470                                    i40e_aqc_opc_query_switching_comp_ets_config,
5471                                    cmd_details);
5472 }
5473
5474 /**
5475  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
5476  * @hw: pointer to the hw struct
5477  * @seid: seid of the VSI or switching component connected to Physical Port
5478  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
5479  * @cmd_details: pointer to command details structure or NULL
5480  **/
5481 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
5482                         u16 seid,
5483                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
5484                         struct i40e_asq_cmd_details *cmd_details)
5485 {
5486         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5487                                     i40e_aqc_opc_query_port_ets_config,
5488                                     cmd_details);
5489 }
5490
5491 /**
5492  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
5493  * @hw: pointer to the hw struct
5494  * @seid: seid of the switching component
5495  * @bw_data: Buffer to hold switching component's BW configuration
5496  * @cmd_details: pointer to command details structure or NULL
5497  **/
5498 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
5499                 u16 seid,
5500                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
5501                 struct i40e_asq_cmd_details *cmd_details)
5502 {
5503         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
5504                                     i40e_aqc_opc_query_switching_comp_bw_config,
5505                                     cmd_details);
5506 }
5507
5508 /**
5509  * i40e_validate_filter_settings
5510  * @hw: pointer to the hardware structure
5511  * @settings: Filter control settings
5512  *
5513  * Check and validate the filter control settings passed.
5514  * The function checks for the valid filter/context sizes being
5515  * passed for FCoE and PE.
5516  *
5517  * Returns I40E_SUCCESS if the values passed are valid and within
5518  * range else returns an error.
5519  **/
5520 STATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,
5521                                 struct i40e_filter_control_settings *settings)
5522 {
5523         u32 fcoe_cntx_size, fcoe_filt_size;
5524         u32 pe_cntx_size, pe_filt_size;
5525         u32 fcoe_fmax;
5526
5527         u32 val;
5528
5529         /* Validate FCoE settings passed */
5530         switch (settings->fcoe_filt_num) {
5531         case I40E_HASH_FILTER_SIZE_1K:
5532         case I40E_HASH_FILTER_SIZE_2K:
5533         case I40E_HASH_FILTER_SIZE_4K:
5534         case I40E_HASH_FILTER_SIZE_8K:
5535         case I40E_HASH_FILTER_SIZE_16K:
5536         case I40E_HASH_FILTER_SIZE_32K:
5537                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5538                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
5539                 break;
5540         default:
5541                 return I40E_ERR_PARAM;
5542         }
5543
5544         switch (settings->fcoe_cntx_num) {
5545         case I40E_DMA_CNTX_SIZE_512:
5546         case I40E_DMA_CNTX_SIZE_1K:
5547         case I40E_DMA_CNTX_SIZE_2K:
5548         case I40E_DMA_CNTX_SIZE_4K:
5549                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5550                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
5551                 break;
5552         default:
5553                 return I40E_ERR_PARAM;
5554         }
5555
5556         /* Validate PE settings passed */
5557         switch (settings->pe_filt_num) {
5558         case I40E_HASH_FILTER_SIZE_1K:
5559         case I40E_HASH_FILTER_SIZE_2K:
5560         case I40E_HASH_FILTER_SIZE_4K:
5561         case I40E_HASH_FILTER_SIZE_8K:
5562         case I40E_HASH_FILTER_SIZE_16K:
5563         case I40E_HASH_FILTER_SIZE_32K:
5564         case I40E_HASH_FILTER_SIZE_64K:
5565         case I40E_HASH_FILTER_SIZE_128K:
5566         case I40E_HASH_FILTER_SIZE_256K:
5567         case I40E_HASH_FILTER_SIZE_512K:
5568         case I40E_HASH_FILTER_SIZE_1M:
5569                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
5570                 pe_filt_size <<= (u32)settings->pe_filt_num;
5571                 break;
5572         default:
5573                 return I40E_ERR_PARAM;
5574         }
5575
5576         switch (settings->pe_cntx_num) {
5577         case I40E_DMA_CNTX_SIZE_512:
5578         case I40E_DMA_CNTX_SIZE_1K:
5579         case I40E_DMA_CNTX_SIZE_2K:
5580         case I40E_DMA_CNTX_SIZE_4K:
5581         case I40E_DMA_CNTX_SIZE_8K:
5582         case I40E_DMA_CNTX_SIZE_16K:
5583         case I40E_DMA_CNTX_SIZE_32K:
5584         case I40E_DMA_CNTX_SIZE_64K:
5585         case I40E_DMA_CNTX_SIZE_128K:
5586         case I40E_DMA_CNTX_SIZE_256K:
5587                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
5588                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
5589                 break;
5590         default:
5591                 return I40E_ERR_PARAM;
5592         }
5593
5594         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
5595         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
5596         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
5597                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
5598         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
5599                 return I40E_ERR_INVALID_SIZE;
5600
5601         return I40E_SUCCESS;
5602 }
5603
5604 /**
5605  * i40e_set_filter_control
5606  * @hw: pointer to the hardware structure
5607  * @settings: Filter control settings
5608  *
5609  * Set the Queue Filters for PE/FCoE and enable filters required
5610  * for a single PF. It is expected that these settings are programmed
5611  * at the driver initialization time.
5612  **/
5613 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
5614                                 struct i40e_filter_control_settings *settings)
5615 {
5616         enum i40e_status_code ret = I40E_SUCCESS;
5617         u32 hash_lut_size = 0;
5618         u32 val;
5619
5620         if (!settings)
5621                 return I40E_ERR_PARAM;
5622
5623         /* Validate the input settings */
5624         ret = i40e_validate_filter_settings(hw, settings);
5625         if (ret)
5626                 return ret;
5627
5628         /* Read the PF Queue Filter control register */
5629         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
5630
5631         /* Program required PE hash buckets for the PF */
5632         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
5633         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
5634                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
5635         /* Program required PE contexts for the PF */
5636         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
5637         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
5638                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
5639
5640         /* Program required FCoE hash buckets for the PF */
5641         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5642         val |= ((u32)settings->fcoe_filt_num <<
5643                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
5644                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
5645         /* Program required FCoE DDP contexts for the PF */
5646         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5647         val |= ((u32)settings->fcoe_cntx_num <<
5648                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
5649                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
5650
5651         /* Program Hash LUT size for the PF */
5652         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5653         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
5654                 hash_lut_size = 1;
5655         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
5656                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
5657
5658         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
5659         if (settings->enable_fdir)
5660                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
5661         if (settings->enable_ethtype)
5662                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
5663         if (settings->enable_macvlan)
5664                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
5665
5666         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
5667
5668         return I40E_SUCCESS;
5669 }
5670
5671 /**
5672  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
5673  * @hw: pointer to the hw struct
5674  * @mac_addr: MAC address to use in the filter
5675  * @ethtype: Ethertype to use in the filter
5676  * @flags: Flags that needs to be applied to the filter
5677  * @vsi_seid: seid of the control VSI
5678  * @queue: VSI queue number to send the packet to
5679  * @is_add: Add control packet filter if True else remove
5680  * @stats: Structure to hold information on control filter counts
5681  * @cmd_details: pointer to command details structure or NULL
5682  *
5683  * This command will Add or Remove control packet filter for a control VSI.
5684  * In return it will update the total number of perfect filter count in
5685  * the stats member.
5686  **/
5687 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
5688                                 u8 *mac_addr, u16 ethtype, u16 flags,
5689                                 u16 vsi_seid, u16 queue, bool is_add,
5690                                 struct i40e_control_filter_stats *stats,
5691                                 struct i40e_asq_cmd_details *cmd_details)
5692 {
5693         struct i40e_aq_desc desc;
5694         struct i40e_aqc_add_remove_control_packet_filter *cmd =
5695                 (struct i40e_aqc_add_remove_control_packet_filter *)
5696                 &desc.params.raw;
5697         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
5698                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
5699                 &desc.params.raw;
5700         enum i40e_status_code status;
5701
5702         if (vsi_seid == 0)
5703                 return I40E_ERR_PARAM;
5704
5705         if (is_add) {
5706                 i40e_fill_default_direct_cmd_desc(&desc,
5707                                 i40e_aqc_opc_add_control_packet_filter);
5708                 cmd->queue = CPU_TO_LE16(queue);
5709         } else {
5710                 i40e_fill_default_direct_cmd_desc(&desc,
5711                                 i40e_aqc_opc_remove_control_packet_filter);
5712         }
5713
5714         if (mac_addr)
5715                 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN,
5716                             I40E_NONDMA_TO_NONDMA);
5717
5718         cmd->etype = CPU_TO_LE16(ethtype);
5719         cmd->flags = CPU_TO_LE16(flags);
5720         cmd->seid = CPU_TO_LE16(vsi_seid);
5721
5722         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5723
5724         if (!status && stats) {
5725                 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);
5726                 stats->etype_used = LE16_TO_CPU(resp->etype_used);
5727                 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);
5728                 stats->etype_free = LE16_TO_CPU(resp->etype_free);
5729         }
5730
5731         return status;
5732 }
5733
5734 /**
5735  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
5736  * @hw: pointer to the hw struct
5737  * @seid: VSI seid to add ethertype filter from
5738  **/
5739 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
5740                                                     u16 seid)
5741 {
5742 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
5743         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
5744                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
5745                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
5746         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
5747         enum i40e_status_code status;
5748
5749         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
5750                                                        seid, 0, true, NULL,
5751                                                        NULL);
5752         if (status)
5753                 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
5754 }
5755
5756 /**
5757  * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
5758  * @filters: list of cloud filters
5759  * @filter_count: length of list
5760  *
5761  * There's an issue in the device where the Geneve VNI layout needs
5762  * to be shifted 1 byte over from the VxLAN VNI
5763  **/
5764 STATIC void i40e_fix_up_geneve_vni(
5765         struct i40e_aqc_cloud_filters_element_data *filters,
5766         u8 filter_count)
5767 {
5768         struct i40e_aqc_cloud_filters_element_data *f = filters;
5769         int i;
5770
5771         for (i = 0; i < filter_count; i++) {
5772                 u16 tnl_type;
5773                 u32 ti;
5774
5775                 tnl_type = (LE16_TO_CPU(f[i].flags) &
5776                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5777                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5778                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5779                         ti = LE32_TO_CPU(f[i].tenant_id);
5780                         f[i].tenant_id = CPU_TO_LE32(ti << 8);
5781                 }
5782         }
5783 }
5784
5785 /**
5786  * i40e_aq_add_cloud_filters
5787  * @hw: pointer to the hardware structure
5788  * @seid: VSI seid to add cloud filters from
5789  * @filters: Buffer which contains the filters to be added
5790  * @filter_count: number of filters contained in the buffer
5791  *
5792  * Set the cloud filters for a given VSI.  The contents of the
5793  * i40e_aqc_cloud_filters_element_data are filled
5794  * in by the caller of the function.
5795  *
5796  **/
5797 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
5798         u16 seid,
5799         struct i40e_aqc_cloud_filters_element_data *filters,
5800         u8 filter_count)
5801 {
5802         struct i40e_aq_desc desc;
5803         struct i40e_aqc_add_remove_cloud_filters *cmd =
5804         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5805         enum i40e_status_code status;
5806         u16 buff_len;
5807
5808         i40e_fill_default_direct_cmd_desc(&desc,
5809                                           i40e_aqc_opc_add_cloud_filters);
5810
5811         buff_len = filter_count * sizeof(*filters);
5812         desc.datalen = CPU_TO_LE16(buff_len);
5813         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5814         cmd->num_filters = filter_count;
5815         cmd->seid = CPU_TO_LE16(seid);
5816
5817         i40e_fix_up_geneve_vni(filters, filter_count);
5818
5819         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5820
5821         return status;
5822 }
5823
5824 /**
5825  * i40e_aq_add_cloud_filters_bb
5826  * @hw: pointer to the hardware structure
5827  * @seid: VSI seid to add cloud filters from
5828  * @filters: Buffer which contains the filters in big buffer to be added
5829  * @filter_count: number of filters contained in the buffer
5830  *
5831  * Set the cloud filters for a given VSI.  The contents of the
5832  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5833  * the function.
5834  *
5835  **/
5836 enum i40e_status_code
5837 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5838                              struct i40e_aqc_cloud_filters_element_bb *filters,
5839                              u8 filter_count)
5840 {
5841         struct i40e_aq_desc desc;
5842         struct i40e_aqc_add_remove_cloud_filters *cmd =
5843         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5844         enum i40e_status_code status;
5845         u16 buff_len;
5846         int i;
5847
5848         i40e_fill_default_direct_cmd_desc(&desc,
5849                                           i40e_aqc_opc_add_cloud_filters);
5850
5851         buff_len = filter_count * sizeof(*filters);
5852         desc.datalen = CPU_TO_LE16(buff_len);
5853         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5854         cmd->num_filters = filter_count;
5855         cmd->seid = CPU_TO_LE16(seid);
5856         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5857
5858         for (i = 0; i < filter_count; i++) {
5859                 u16 tnl_type;
5860                 u32 ti;
5861
5862                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5863                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5864                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5865
5866                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5867                  * one more byte further than normally used for Tenant ID in
5868                  * other tunnel types.
5869                  */
5870                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5871                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5872                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5873                 }
5874         }
5875
5876         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5877
5878         return status;
5879 }
5880
5881 /**
5882  * i40e_aq_rem_cloud_filters
5883  * @hw: pointer to the hardware structure
5884  * @seid: VSI seid to remove cloud filters from
5885  * @filters: Buffer which contains the filters to be removed
5886  * @filter_count: number of filters contained in the buffer
5887  *
5888  * Remove the cloud filters for a given VSI.  The contents of the
5889  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5890  * of the function.
5891  *
5892  **/
5893 enum i40e_status_code
5894 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5895                           struct i40e_aqc_cloud_filters_element_data *filters,
5896                           u8 filter_count)
5897 {
5898         struct i40e_aq_desc desc;
5899         struct i40e_aqc_add_remove_cloud_filters *cmd =
5900         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5901         enum i40e_status_code status;
5902         u16 buff_len;
5903
5904         i40e_fill_default_direct_cmd_desc(&desc,
5905                                           i40e_aqc_opc_remove_cloud_filters);
5906
5907         buff_len = filter_count * sizeof(*filters);
5908         desc.datalen = CPU_TO_LE16(buff_len);
5909         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5910         cmd->num_filters = filter_count;
5911         cmd->seid = CPU_TO_LE16(seid);
5912
5913         i40e_fix_up_geneve_vni(filters, filter_count);
5914
5915         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5916
5917         return status;
5918 }
5919
5920 /**
5921  * i40e_aq_rem_cloud_filters_bb
5922  * @hw: pointer to the hardware structure
5923  * @seid: VSI seid to remove cloud filters from
5924  * @filters: Buffer which contains the filters in big buffer to be removed
5925  * @filter_count: number of filters contained in the buffer
5926  *
5927  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5928  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5929  * function.
5930  *
5931  **/
5932 enum i40e_status_code
5933 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5934                              struct i40e_aqc_cloud_filters_element_bb *filters,
5935                              u8 filter_count)
5936 {
5937         struct i40e_aq_desc desc;
5938         struct i40e_aqc_add_remove_cloud_filters *cmd =
5939         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5940         enum i40e_status_code status;
5941         u16 buff_len;
5942         int i;
5943
5944         i40e_fill_default_direct_cmd_desc(&desc,
5945                                           i40e_aqc_opc_remove_cloud_filters);
5946
5947         buff_len = filter_count * sizeof(*filters);
5948         desc.datalen = CPU_TO_LE16(buff_len);
5949         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5950         cmd->num_filters = filter_count;
5951         cmd->seid = CPU_TO_LE16(seid);
5952         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5953
5954         for (i = 0; i < filter_count; i++) {
5955                 u16 tnl_type;
5956                 u32 ti;
5957
5958                 tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
5959                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5960                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5961
5962                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5963                  * one more byte further than normally used for Tenant ID in
5964                  * other tunnel types.
5965                  */
5966                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5967                         ti = LE32_TO_CPU(filters[i].element.tenant_id);
5968                         filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
5969                 }
5970         }
5971
5972         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5973
5974         return status;
5975 }
5976
5977 /**
5978  * i40e_aq_replace_cloud_filters - Replace cloud filter command
5979  * @hw: pointer to the hw struct
5980  * @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
5981  * @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
5982  *
5983  **/
5984 enum
5985 i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
5986         struct i40e_aqc_replace_cloud_filters_cmd *filters,
5987         struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
5988 {
5989         struct i40e_aq_desc desc;
5990         struct i40e_aqc_replace_cloud_filters_cmd *cmd =
5991                 (struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
5992         enum i40e_status_code status = I40E_SUCCESS;
5993         int i = 0;
5994
5995         /* X722 doesn't support this command */
5996         if (hw->mac.type == I40E_MAC_X722)
5997                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5998
5999         /* need FW version greater than 6.00 */
6000         if (hw->aq.fw_maj_ver < 6)
6001                 return I40E_NOT_SUPPORTED;
6002
6003         i40e_fill_default_direct_cmd_desc(&desc,
6004                                           i40e_aqc_opc_replace_cloud_filters);
6005
6006         desc.datalen = CPU_TO_LE16(32);
6007         desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6008         cmd->old_filter_type = filters->old_filter_type;
6009         cmd->new_filter_type = filters->new_filter_type;
6010         cmd->valid_flags = filters->valid_flags;
6011         cmd->tr_bit = filters->tr_bit;
6012         cmd->tr_bit2 = filters->tr_bit2;
6013
6014         status = i40e_asq_send_command(hw, &desc, cmd_buf,
6015                 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf),  NULL);
6016
6017         /* for get cloud filters command */
6018         for (i = 0; i < 32; i += 4) {
6019                 cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
6020                 cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
6021                 cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
6022                 cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
6023         }
6024
6025         return status;
6026 }
6027
6028
6029 /**
6030  * i40e_aq_alternate_write
6031  * @hw: pointer to the hardware structure
6032  * @reg_addr0: address of first dword to be read
6033  * @reg_val0: value to be written under 'reg_addr0'
6034  * @reg_addr1: address of second dword to be read
6035  * @reg_val1: value to be written under 'reg_addr1'
6036  *
6037  * Write one or two dwords to alternate structure. Fields are indicated
6038  * by 'reg_addr0' and 'reg_addr1' register numbers.
6039  *
6040  **/
6041 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
6042                                 u32 reg_addr0, u32 reg_val0,
6043                                 u32 reg_addr1, u32 reg_val1)
6044 {
6045         struct i40e_aq_desc desc;
6046         struct i40e_aqc_alternate_write *cmd_resp =
6047                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6048         enum i40e_status_code status;
6049
6050         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);
6051         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6052         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6053         cmd_resp->data0 = CPU_TO_LE32(reg_val0);
6054         cmd_resp->data1 = CPU_TO_LE32(reg_val1);
6055
6056         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6057
6058         return status;
6059 }
6060
6061 /**
6062  * i40e_aq_alternate_write_indirect
6063  * @hw: pointer to the hardware structure
6064  * @addr: address of a first register to be modified
6065  * @dw_count: number of alternate structure fields to write
6066  * @buffer: pointer to the command buffer
6067  *
6068  * Write 'dw_count' dwords from 'buffer' to alternate structure
6069  * starting at 'addr'.
6070  *
6071  **/
6072 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
6073                                 u32 addr, u32 dw_count, void *buffer)
6074 {
6075         struct i40e_aq_desc desc;
6076         struct i40e_aqc_alternate_ind_write *cmd_resp =
6077                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6078         enum i40e_status_code status;
6079
6080         if (buffer == NULL)
6081                 return I40E_ERR_PARAM;
6082
6083         /* Indirect command */
6084         i40e_fill_default_direct_cmd_desc(&desc,
6085                                          i40e_aqc_opc_alternate_write_indirect);
6086
6087         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6088         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6089         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6090                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6091
6092         cmd_resp->address = CPU_TO_LE32(addr);
6093         cmd_resp->length = CPU_TO_LE32(dw_count);
6094
6095         status = i40e_asq_send_command(hw, &desc, buffer,
6096                                        I40E_LO_DWORD(4*dw_count), NULL);
6097
6098         return status;
6099 }
6100
6101 /**
6102  * i40e_aq_alternate_read
6103  * @hw: pointer to the hardware structure
6104  * @reg_addr0: address of first dword to be read
6105  * @reg_val0: pointer for data read from 'reg_addr0'
6106  * @reg_addr1: address of second dword to be read
6107  * @reg_val1: pointer for data read from 'reg_addr1'
6108  *
6109  * Read one or two dwords from alternate structure. Fields are indicated
6110  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
6111  * is not passed then only register at 'reg_addr0' is read.
6112  *
6113  **/
6114 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
6115                                 u32 reg_addr0, u32 *reg_val0,
6116                                 u32 reg_addr1, u32 *reg_val1)
6117 {
6118         struct i40e_aq_desc desc;
6119         struct i40e_aqc_alternate_write *cmd_resp =
6120                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
6121         enum i40e_status_code status;
6122
6123         if (reg_val0 == NULL)
6124                 return I40E_ERR_PARAM;
6125
6126         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
6127         cmd_resp->address0 = CPU_TO_LE32(reg_addr0);
6128         cmd_resp->address1 = CPU_TO_LE32(reg_addr1);
6129
6130         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6131
6132         if (status == I40E_SUCCESS) {
6133                 *reg_val0 = LE32_TO_CPU(cmd_resp->data0);
6134
6135                 if (reg_val1 != NULL)
6136                         *reg_val1 = LE32_TO_CPU(cmd_resp->data1);
6137         }
6138
6139         return status;
6140 }
6141
6142 /**
6143  * i40e_aq_alternate_read_indirect
6144  * @hw: pointer to the hardware structure
6145  * @addr: address of the alternate structure field
6146  * @dw_count: number of alternate structure fields to read
6147  * @buffer: pointer to the command buffer
6148  *
6149  * Read 'dw_count' dwords from alternate structure starting at 'addr' and
6150  * place them in 'buffer'. The buffer should be allocated by caller.
6151  *
6152  **/
6153 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
6154                                 u32 addr, u32 dw_count, void *buffer)
6155 {
6156         struct i40e_aq_desc desc;
6157         struct i40e_aqc_alternate_ind_write *cmd_resp =
6158                 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw;
6159         enum i40e_status_code status;
6160
6161         if (buffer == NULL)
6162                 return I40E_ERR_PARAM;
6163
6164         /* Indirect command */
6165         i40e_fill_default_direct_cmd_desc(&desc,
6166                 i40e_aqc_opc_alternate_read_indirect);
6167
6168         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);
6169         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
6170         if (dw_count > (I40E_AQ_LARGE_BUF/4))
6171                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6172
6173         cmd_resp->address = CPU_TO_LE32(addr);
6174         cmd_resp->length = CPU_TO_LE32(dw_count);
6175
6176         status = i40e_asq_send_command(hw, &desc, buffer,
6177                                        I40E_LO_DWORD(4*dw_count), NULL);
6178
6179         return status;
6180 }
6181
6182 /**
6183  *  i40e_aq_alternate_clear
6184  *  @hw: pointer to the HW structure.
6185  *
6186  *  Clear the alternate structures of the port from which the function
6187  *  is called.
6188  *
6189  **/
6190 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)
6191 {
6192         struct i40e_aq_desc desc;
6193         enum i40e_status_code status;
6194
6195         i40e_fill_default_direct_cmd_desc(&desc,
6196                                           i40e_aqc_opc_alternate_clear_port);
6197
6198         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6199
6200         return status;
6201 }
6202
6203 /**
6204  *  i40e_aq_alternate_write_done
6205  *  @hw: pointer to the HW structure.
6206  *  @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS
6207  *  @reset_needed: indicates the SW should trigger GLOBAL reset
6208  *
6209  *  Indicates to the FW that alternate structures have been changed.
6210  *
6211  **/
6212 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
6213                 u8 bios_mode, bool *reset_needed)
6214 {
6215         struct i40e_aq_desc desc;
6216         struct i40e_aqc_alternate_write_done *cmd =
6217                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6218         enum i40e_status_code status;
6219
6220         if (reset_needed == NULL)
6221                 return I40E_ERR_PARAM;
6222
6223         i40e_fill_default_direct_cmd_desc(&desc,
6224                                           i40e_aqc_opc_alternate_write_done);
6225
6226         cmd->cmd_flags = CPU_TO_LE16(bios_mode);
6227
6228         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6229         if (!status && reset_needed)
6230                 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &
6231                                  I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);
6232
6233         return status;
6234 }
6235
6236 /**
6237  *  i40e_aq_set_oem_mode
6238  *  @hw: pointer to the HW structure.
6239  *  @oem_mode: the OEM mode to be used
6240  *
6241  *  Sets the device to a specific operating mode. Currently the only supported
6242  *  mode is no_clp, which causes FW to refrain from using Alternate RAM.
6243  *
6244  **/
6245 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
6246                 u8 oem_mode)
6247 {
6248         struct i40e_aq_desc desc;
6249         struct i40e_aqc_alternate_write_done *cmd =
6250                 (struct i40e_aqc_alternate_write_done *)&desc.params.raw;
6251         enum i40e_status_code status;
6252
6253         i40e_fill_default_direct_cmd_desc(&desc,
6254                                           i40e_aqc_opc_alternate_set_mode);
6255
6256         cmd->cmd_flags = CPU_TO_LE16(oem_mode);
6257
6258         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
6259
6260         return status;
6261 }
6262
6263 /**
6264  * i40e_aq_resume_port_tx
6265  * @hw: pointer to the hardware structure
6266  * @cmd_details: pointer to command details structure or NULL
6267  *
6268  * Resume port's Tx traffic
6269  **/
6270 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
6271                                 struct i40e_asq_cmd_details *cmd_details)
6272 {
6273         struct i40e_aq_desc desc;
6274         enum i40e_status_code status;
6275
6276         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
6277
6278         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
6279
6280         return status;
6281 }
6282
6283 /**
6284  * i40e_set_pci_config_data - store PCI bus info
6285  * @hw: pointer to hardware structure
6286  * @link_status: the link status word from PCI config space
6287  *
6288  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
6289  **/
6290 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
6291 {
6292         hw->bus.type = i40e_bus_type_pci_express;
6293
6294         switch (link_status & I40E_PCI_LINK_WIDTH) {
6295         case I40E_PCI_LINK_WIDTH_1:
6296                 hw->bus.width = i40e_bus_width_pcie_x1;
6297                 break;
6298         case I40E_PCI_LINK_WIDTH_2:
6299                 hw->bus.width = i40e_bus_width_pcie_x2;
6300                 break;
6301         case I40E_PCI_LINK_WIDTH_4:
6302                 hw->bus.width = i40e_bus_width_pcie_x4;
6303                 break;
6304         case I40E_PCI_LINK_WIDTH_8:
6305                 hw->bus.width = i40e_bus_width_pcie_x8;
6306                 break;
6307         default:
6308                 hw->bus.width = i40e_bus_width_unknown;
6309                 break;
6310         }
6311
6312         switch (link_status & I40E_PCI_LINK_SPEED) {
6313         case I40E_PCI_LINK_SPEED_2500:
6314                 hw->bus.speed = i40e_bus_speed_2500;
6315                 break;
6316         case I40E_PCI_LINK_SPEED_5000:
6317                 hw->bus.speed = i40e_bus_speed_5000;
6318                 break;
6319         case I40E_PCI_LINK_SPEED_8000:
6320                 hw->bus.speed = i40e_bus_speed_8000;
6321                 break;
6322         default:
6323                 hw->bus.speed = i40e_bus_speed_unknown;
6324                 break;
6325         }
6326 }
6327
6328 /**
6329  * i40e_aq_debug_dump
6330  * @hw: pointer to the hardware structure
6331  * @cluster_id: specific cluster to dump
6332  * @table_id: table id within cluster
6333  * @start_index: index of line in the block to read
6334  * @buff_size: dump buffer size
6335  * @buff: dump buffer
6336  * @ret_buff_size: actual buffer size returned
6337  * @ret_next_table: next block to read
6338  * @ret_next_index: next index to read
6339  * @cmd_details: pointer to command details structure or NULL
6340  *
6341  * Dump internal FW/HW data for debug purposes.
6342  *
6343  **/
6344 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
6345                                 u8 table_id, u32 start_index, u16 buff_size,
6346                                 void *buff, u16 *ret_buff_size,
6347                                 u8 *ret_next_table, u32 *ret_next_index,
6348                                 struct i40e_asq_cmd_details *cmd_details)
6349 {
6350         struct i40e_aq_desc desc;
6351         struct i40e_aqc_debug_dump_internals *cmd =
6352                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6353         struct i40e_aqc_debug_dump_internals *resp =
6354                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
6355         enum i40e_status_code status;
6356
6357         if (buff_size == 0 || !buff)
6358                 return I40E_ERR_PARAM;
6359
6360         i40e_fill_default_direct_cmd_desc(&desc,
6361                                           i40e_aqc_opc_debug_dump_internals);
6362         /* Indirect Command */
6363         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6364         if (buff_size > I40E_AQ_LARGE_BUF)
6365                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
6366
6367         cmd->cluster_id = cluster_id;
6368         cmd->table_id = table_id;
6369         cmd->idx = CPU_TO_LE32(start_index);
6370
6371         desc.datalen = CPU_TO_LE16(buff_size);
6372
6373         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
6374         if (!status) {
6375                 if (ret_buff_size != NULL)
6376                         *ret_buff_size = LE16_TO_CPU(desc.datalen);
6377                 if (ret_next_table != NULL)
6378                         *ret_next_table = resp->table_id;
6379                 if (ret_next_index != NULL)
6380                         *ret_next_index = LE32_TO_CPU(resp->idx);
6381         }
6382
6383         return status;
6384 }
6385
6386 /**
6387  * i40e_read_bw_from_alt_ram
6388  * @hw: pointer to the hardware structure
6389  * @max_bw: pointer for max_bw read
6390  * @min_bw: pointer for min_bw read
6391  * @min_valid: pointer for bool that is true if min_bw is a valid value
6392  * @max_valid: pointer for bool that is true if max_bw is a valid value
6393  *
6394  * Read bw from the alternate ram for the given pf
6395  **/
6396 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
6397                                         u32 *max_bw, u32 *min_bw,
6398                                         bool *min_valid, bool *max_valid)
6399 {
6400         enum i40e_status_code status;
6401         u32 max_bw_addr, min_bw_addr;
6402
6403         /* Calculate the address of the min/max bw registers */
6404         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6405                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
6406                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6407         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
6408                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
6409                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
6410
6411         /* Read the bandwidths from alt ram */
6412         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
6413                                         min_bw_addr, min_bw);
6414
6415         if (*min_bw & I40E_ALT_BW_VALID_MASK)
6416                 *min_valid = true;
6417         else
6418                 *min_valid = false;
6419
6420         if (*max_bw & I40E_ALT_BW_VALID_MASK)
6421                 *max_valid = true;
6422         else
6423                 *max_valid = false;
6424
6425         return status;
6426 }
6427
6428 /**
6429  * i40e_aq_configure_partition_bw
6430  * @hw: pointer to the hardware structure
6431  * @bw_data: Buffer holding valid pfs and bw limits
6432  * @cmd_details: pointer to command details
6433  *
6434  * Configure partitions guaranteed/max bw
6435  **/
6436 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
6437                         struct i40e_aqc_configure_partition_bw_data *bw_data,
6438                         struct i40e_asq_cmd_details *cmd_details)
6439 {
6440         enum i40e_status_code status;
6441         struct i40e_aq_desc desc;
6442         u16 bwd_size = sizeof(*bw_data);
6443
6444         i40e_fill_default_direct_cmd_desc(&desc,
6445                                 i40e_aqc_opc_configure_partition_bw);
6446
6447         /* Indirect command */
6448         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
6449         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
6450
6451         desc.datalen = CPU_TO_LE16(bwd_size);
6452
6453         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);
6454
6455         return status;
6456 }
6457
6458 /**
6459  * i40e_read_phy_register_clause22
6460  * @hw: pointer to the HW structure
6461  * @reg: register address in the page
6462  * @phy_addr: PHY address on MDIO interface
6463  * @value: PHY register value
6464  *
6465  * Reads specified PHY register value
6466  **/
6467 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
6468                                         u16 reg, u8 phy_addr, u16 *value)
6469 {
6470         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6471         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6472         u32 command = 0;
6473         u16 retry = 1000;
6474
6475         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6476                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6477                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
6478                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6479                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6480         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6481         do {
6482                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6483                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6484                         status = I40E_SUCCESS;
6485                         break;
6486                 }
6487                 i40e_usec_delay(10);
6488                 retry--;
6489         } while (retry);
6490
6491         if (status) {
6492                 i40e_debug(hw, I40E_DEBUG_PHY,
6493                            "PHY: Can't write command to external PHY.\n");
6494         } else {
6495                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6496                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6497                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6498         }
6499
6500         return status;
6501 }
6502
6503 /**
6504  * i40e_write_phy_register_clause22
6505  * @hw: pointer to the HW structure
6506  * @reg: register address in the page
6507  * @phy_addr: PHY address on MDIO interface
6508  * @value: PHY register value
6509  *
6510  * Writes specified PHY register value
6511  **/
6512 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
6513                                         u16 reg, u8 phy_addr, u16 value)
6514 {
6515         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6516         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6517         u32 command  = 0;
6518         u16 retry = 1000;
6519
6520         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6521         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6522
6523         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6524                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6525                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
6526                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
6527                   (I40E_GLGEN_MSCA_MDICMD_MASK);
6528
6529         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6530         do {
6531                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6532                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6533                         status = I40E_SUCCESS;
6534                         break;
6535                 }
6536                 i40e_usec_delay(10);
6537                 retry--;
6538         } while (retry);
6539
6540         return status;
6541 }
6542
6543 /**
6544  * i40e_read_phy_register_clause45
6545  * @hw: pointer to the HW structure
6546  * @page: registers page number
6547  * @reg: register address in the page
6548  * @phy_addr: PHY address on MDIO interface
6549  * @value: PHY register value
6550  *
6551  * Reads specified PHY register value
6552  **/
6553 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
6554                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6555 {
6556         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6557         u32 command  = 0;
6558         u16 retry = 1000;
6559         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6560
6561         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6562                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6563                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6564                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6565                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6566                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6567                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6568         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6569         do {
6570                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6571                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6572                         status = I40E_SUCCESS;
6573                         break;
6574                 }
6575                 i40e_usec_delay(10);
6576                 retry--;
6577         } while (retry);
6578
6579         if (status) {
6580                 i40e_debug(hw, I40E_DEBUG_PHY,
6581                            "PHY: Can't write command to external PHY.\n");
6582                 goto phy_read_end;
6583         }
6584
6585         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6586                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6587                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
6588                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6589                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6590                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6591         status = I40E_ERR_TIMEOUT;
6592         retry = 1000;
6593         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6594         do {
6595                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6596                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6597                         status = I40E_SUCCESS;
6598                         break;
6599                 }
6600                 i40e_usec_delay(10);
6601                 retry--;
6602         } while (retry);
6603
6604         if (!status) {
6605                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
6606                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
6607                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
6608         } else {
6609                 i40e_debug(hw, I40E_DEBUG_PHY,
6610                            "PHY: Can't read register value from external PHY.\n");
6611         }
6612
6613 phy_read_end:
6614         return status;
6615 }
6616
6617 /**
6618  * i40e_write_phy_register_clause45
6619  * @hw: pointer to the HW structure
6620  * @page: registers page number
6621  * @reg: register address in the page
6622  * @phy_addr: PHY address on MDIO interface
6623  * @value: PHY register value
6624  *
6625  * Writes value to specified PHY register
6626  **/
6627 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
6628                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6629 {
6630         enum i40e_status_code status = I40E_ERR_TIMEOUT;
6631         u32 command  = 0;
6632         u16 retry = 1000;
6633         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6634
6635         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
6636                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6637                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6638                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
6639                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6640                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6641                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6642         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6643         do {
6644                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6645                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6646                         status = I40E_SUCCESS;
6647                         break;
6648                 }
6649                 i40e_usec_delay(10);
6650                 retry--;
6651         } while (retry);
6652         if (status) {
6653                 i40e_debug(hw, I40E_DEBUG_PHY,
6654                            "PHY: Can't write command to external PHY.\n");
6655                 goto phy_write_end;
6656         }
6657
6658         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
6659         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
6660
6661         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
6662                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
6663                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
6664                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
6665                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
6666                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
6667         status = I40E_ERR_TIMEOUT;
6668         retry = 1000;
6669         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
6670         do {
6671                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
6672                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
6673                         status = I40E_SUCCESS;
6674                         break;
6675                 }
6676                 i40e_usec_delay(10);
6677                 retry--;
6678         } while (retry);
6679
6680 phy_write_end:
6681         return status;
6682 }
6683
6684 /**
6685  * i40e_write_phy_register
6686  * @hw: pointer to the HW structure
6687  * @page: registers page number
6688  * @reg: register address in the page
6689  * @phy_addr: PHY address on MDIO interface
6690  * @value: PHY register value
6691  *
6692  * Writes value to specified PHY register
6693  **/
6694 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
6695                                 u8 page, u16 reg, u8 phy_addr, u16 value)
6696 {
6697         enum i40e_status_code status;
6698
6699         switch (hw->device_id) {
6700         case I40E_DEV_ID_1G_BASE_T_X722:
6701                 status = i40e_write_phy_register_clause22(hw,
6702                         reg, phy_addr, value);
6703                 break;
6704         case I40E_DEV_ID_10G_BASE_T:
6705         case I40E_DEV_ID_10G_BASE_T4:
6706 #ifdef CARLSVILLE_HW
6707         case I40E_DEV_ID_10G_BASE_T_BC:
6708 #endif
6709         case I40E_DEV_ID_10G_BASE_T_X722:
6710         case I40E_DEV_ID_25G_B:
6711         case I40E_DEV_ID_25G_SFP28:
6712                 status = i40e_write_phy_register_clause45(hw,
6713                         page, reg, phy_addr, value);
6714                 break;
6715         default:
6716                 status = I40E_ERR_UNKNOWN_PHY;
6717                 break;
6718         }
6719
6720         return status;
6721 }
6722
6723 /**
6724  * i40e_read_phy_register
6725  * @hw: pointer to the HW structure
6726  * @page: registers page number
6727  * @reg: register address in the page
6728  * @phy_addr: PHY address on MDIO interface
6729  * @value: PHY register value
6730  *
6731  * Reads specified PHY register value
6732  **/
6733 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
6734                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
6735 {
6736         enum i40e_status_code status;
6737
6738         switch (hw->device_id) {
6739         case I40E_DEV_ID_1G_BASE_T_X722:
6740                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
6741                                                          value);
6742                 break;
6743         case I40E_DEV_ID_10G_BASE_T:
6744         case I40E_DEV_ID_10G_BASE_T4:
6745         case I40E_DEV_ID_10G_BASE_T_X722:
6746         case I40E_DEV_ID_25G_B:
6747         case I40E_DEV_ID_25G_SFP28:
6748                 status = i40e_read_phy_register_clause45(hw, page, reg,
6749                                                          phy_addr, value);
6750                 break;
6751         default:
6752                 status = I40E_ERR_UNKNOWN_PHY;
6753                 break;
6754         }
6755
6756         return status;
6757 }
6758
6759 /**
6760  * i40e_get_phy_address
6761  * @hw: pointer to the HW structure
6762  * @dev_num: PHY port num that address we want
6763  *
6764  * Gets PHY address for current port
6765  **/
6766 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
6767 {
6768         u8 port_num = (u8)hw->func_caps.mdio_port_num;
6769         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
6770
6771         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
6772 }
6773
6774 /**
6775  * i40e_blink_phy_led
6776  * @hw: pointer to the HW structure
6777  * @time: time how long led will blinks in secs
6778  * @interval: gap between LED on and off in msecs
6779  *
6780  * Blinks PHY link LED
6781  **/
6782 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
6783                                               u32 time, u32 interval)
6784 {
6785         enum i40e_status_code status = I40E_SUCCESS;
6786         u32 i;
6787         u16 led_ctl = 0;
6788         u16 gpio_led_port;
6789         u16 led_reg;
6790         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
6791         u8 phy_addr = 0;
6792         u8 port_num;
6793
6794         i = rd32(hw, I40E_PFGEN_PORTNUM);
6795         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
6796         phy_addr = i40e_get_phy_address(hw, port_num);
6797
6798         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6799              led_addr++) {
6800                 status = i40e_read_phy_register_clause45(hw,
6801                                                          I40E_PHY_COM_REG_PAGE,
6802                                                          led_addr, phy_addr,
6803                                                          &led_reg);
6804                 if (status)
6805                         goto phy_blinking_end;
6806                 led_ctl = led_reg;
6807                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6808                         led_reg = 0;
6809                         status = i40e_write_phy_register_clause45(hw,
6810                                                          I40E_PHY_COM_REG_PAGE,
6811                                                          led_addr, phy_addr,
6812                                                          led_reg);
6813                         if (status)
6814                                 goto phy_blinking_end;
6815                         break;
6816                 }
6817         }
6818
6819         if (time > 0 && interval > 0) {
6820                 for (i = 0; i < time * 1000; i += interval) {
6821                         status = i40e_read_phy_register_clause45(hw,
6822                                                 I40E_PHY_COM_REG_PAGE,
6823                                                 led_addr, phy_addr, &led_reg);
6824                         if (status)
6825                                 goto restore_config;
6826                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
6827                                 led_reg = 0;
6828                         else
6829                                 led_reg = I40E_PHY_LED_MANUAL_ON;
6830                         status = i40e_write_phy_register_clause45(hw,
6831                                                 I40E_PHY_COM_REG_PAGE,
6832                                                 led_addr, phy_addr, led_reg);
6833                         if (status)
6834                                 goto restore_config;
6835                         i40e_msec_delay(interval);
6836                 }
6837         }
6838
6839 restore_config:
6840         status = i40e_write_phy_register_clause45(hw,
6841                                                   I40E_PHY_COM_REG_PAGE,
6842                                                   led_addr, phy_addr, led_ctl);
6843
6844 phy_blinking_end:
6845         return status;
6846 }
6847
6848 /**
6849  * i40e_led_get_reg - read LED register
6850  * @hw: pointer to the HW structure
6851  * @led_addr: LED register address
6852  * @reg_val: read register value
6853  **/
6854 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
6855                                               u32 *reg_val)
6856 {
6857         enum i40e_status_code status;
6858         u8 phy_addr = 0;
6859
6860         *reg_val = 0;
6861         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6862                 status = i40e_aq_get_phy_register(hw,
6863                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6864                                                 I40E_PHY_COM_REG_PAGE, true,
6865                                                 I40E_PHY_LED_PROV_REG_1,
6866                                                 reg_val, NULL);
6867         } else {
6868                 phy_addr = i40e_get_phy_address(hw, hw->port);
6869                 status = i40e_read_phy_register_clause45(hw,
6870                                                          I40E_PHY_COM_REG_PAGE,
6871                                                          led_addr, phy_addr,
6872                                                          (u16 *)reg_val);
6873         }
6874         return status;
6875 }
6876
6877 /**
6878  * i40e_led_set_reg - write LED register
6879  * @hw: pointer to the HW structure
6880  * @led_addr: LED register address
6881  * @reg_val: register value to write
6882  **/
6883 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
6884                                               u32 reg_val)
6885 {
6886         enum i40e_status_code status;
6887         u8 phy_addr = 0;
6888
6889         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6890                 status = i40e_aq_set_phy_register(hw,
6891                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6892                                                 I40E_PHY_COM_REG_PAGE, true,
6893                                                 I40E_PHY_LED_PROV_REG_1,
6894                                                 reg_val, NULL);
6895         } else {
6896                 phy_addr = i40e_get_phy_address(hw, hw->port);
6897                 status = i40e_write_phy_register_clause45(hw,
6898                                                           I40E_PHY_COM_REG_PAGE,
6899                                                           led_addr, phy_addr,
6900                                                           (u16)reg_val);
6901         }
6902
6903         return status;
6904 }
6905
6906 /**
6907  * i40e_led_get_phy - return current on/off mode
6908  * @hw: pointer to the hw struct
6909  * @led_addr: address of led register to use
6910  * @val: original value of register to use
6911  *
6912  **/
6913 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
6914                                        u16 *val)
6915 {
6916         enum i40e_status_code status = I40E_SUCCESS;
6917         u16 gpio_led_port;
6918         u32 reg_val_aq;
6919         u16 temp_addr;
6920         u8 phy_addr = 0;
6921         u16 reg_val;
6922
6923         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
6924                 status = i40e_aq_get_phy_register(hw,
6925                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
6926                                                 I40E_PHY_COM_REG_PAGE, true,
6927                                                 I40E_PHY_LED_PROV_REG_1,
6928                                                 &reg_val_aq, NULL);
6929                 if (status == I40E_SUCCESS)
6930                         *val = (u16)reg_val_aq;
6931                 return status;
6932         }
6933         temp_addr = I40E_PHY_LED_PROV_REG_1;
6934         phy_addr = i40e_get_phy_address(hw, hw->port);
6935         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
6936              temp_addr++) {
6937                 status = i40e_read_phy_register_clause45(hw,
6938                                                          I40E_PHY_COM_REG_PAGE,
6939                                                          temp_addr, phy_addr,
6940                                                          &reg_val);
6941                 if (status)
6942                         return status;
6943                 *val = reg_val;
6944                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
6945                         *led_addr = temp_addr;
6946                         break;
6947                 }
6948         }
6949         return status;
6950 }
6951
6952 /**
6953  * i40e_led_set_phy
6954  * @hw: pointer to the HW structure
6955  * @on: true or false
6956  * @led_addr: address of led register to use
6957  * @mode: original val plus bit for set or ignore
6958  *
6959  * Set led's on or off when controlled by the PHY
6960  *
6961  **/
6962 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
6963                                        u16 led_addr, u32 mode)
6964 {
6965         enum i40e_status_code status = I40E_SUCCESS;
6966         u32 led_ctl = 0;
6967         u32 led_reg = 0;
6968
6969         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6970         if (status)
6971                 return status;
6972         led_ctl = led_reg;
6973         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
6974                 led_reg = 0;
6975                 status = i40e_led_set_reg(hw, led_addr, led_reg);
6976                 if (status)
6977                         return status;
6978         }
6979         status = i40e_led_get_reg(hw, led_addr, &led_reg);
6980         if (status)
6981                 goto restore_config;
6982         if (on)
6983                 led_reg = I40E_PHY_LED_MANUAL_ON;
6984         else
6985                 led_reg = 0;
6986         status = i40e_led_set_reg(hw, led_addr, led_reg);
6987         if (status)
6988                 goto restore_config;
6989         if (mode & I40E_PHY_LED_MODE_ORIG) {
6990                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
6991                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
6992         }
6993         return status;
6994
6995 restore_config:
6996         status = i40e_led_set_reg(hw, led_addr, led_ctl);
6997         return status;
6998 }
6999 #endif /* PF_DRIVER */
7000
7001 /**
7002  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
7003  * @hw: pointer to the hw struct
7004  * @reg_addr: register address
7005  * @reg_val: ptr to register value
7006  * @cmd_details: pointer to command details structure or NULL
7007  *
7008  * Use the firmware to read the Rx control register,
7009  * especially useful if the Rx unit is under heavy pressure
7010  **/
7011 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
7012                                 u32 reg_addr, u32 *reg_val,
7013                                 struct i40e_asq_cmd_details *cmd_details)
7014 {
7015         struct i40e_aq_desc desc;
7016         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
7017                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7018         enum i40e_status_code status;
7019
7020         if (reg_val == NULL)
7021                 return I40E_ERR_PARAM;
7022
7023         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
7024
7025         cmd_resp->address = CPU_TO_LE32(reg_addr);
7026
7027         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7028
7029         if (status == I40E_SUCCESS)
7030                 *reg_val = LE32_TO_CPU(cmd_resp->value);
7031
7032         return status;
7033 }
7034
7035 /**
7036  * i40e_read_rx_ctl - read from an Rx control register
7037  * @hw: pointer to the hw struct
7038  * @reg_addr: register address
7039  **/
7040 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
7041 {
7042         enum i40e_status_code status = I40E_SUCCESS;
7043         bool use_register;
7044         int retry = 5;
7045         u32 val = 0;
7046
7047         use_register = (((hw->aq.api_maj_ver == 1) &&
7048                         (hw->aq.api_min_ver < 5)) ||
7049                         (hw->mac.type == I40E_MAC_X722));
7050         if (!use_register) {
7051 do_retry:
7052                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
7053                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7054                         i40e_msec_delay(1);
7055                         retry--;
7056                         goto do_retry;
7057                 }
7058         }
7059
7060         /* if the AQ access failed, try the old-fashioned way */
7061         if (status || use_register)
7062                 val = rd32(hw, reg_addr);
7063
7064         return val;
7065 }
7066
7067 /**
7068  * i40e_aq_rx_ctl_write_register
7069  * @hw: pointer to the hw struct
7070  * @reg_addr: register address
7071  * @reg_val: register value
7072  * @cmd_details: pointer to command details structure or NULL
7073  *
7074  * Use the firmware to write to an Rx control register,
7075  * especially useful if the Rx unit is under heavy pressure
7076  **/
7077 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
7078                                 u32 reg_addr, u32 reg_val,
7079                                 struct i40e_asq_cmd_details *cmd_details)
7080 {
7081         struct i40e_aq_desc desc;
7082         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
7083                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
7084         enum i40e_status_code status;
7085
7086         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
7087
7088         cmd->address = CPU_TO_LE32(reg_addr);
7089         cmd->value = CPU_TO_LE32(reg_val);
7090
7091         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7092
7093         return status;
7094 }
7095
7096 /**
7097  * i40e_write_rx_ctl - write to an Rx control register
7098  * @hw: pointer to the hw struct
7099  * @reg_addr: register address
7100  * @reg_val: register value
7101  **/
7102 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
7103 {
7104         enum i40e_status_code status = I40E_SUCCESS;
7105         bool use_register;
7106         int retry = 5;
7107
7108         use_register = (((hw->aq.api_maj_ver == 1) &&
7109                         (hw->aq.api_min_ver < 5)) ||
7110                         (hw->mac.type == I40E_MAC_X722));
7111         if (!use_register) {
7112 do_retry:
7113                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
7114                                                        reg_val, NULL);
7115                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
7116                         i40e_msec_delay(1);
7117                         retry--;
7118                         goto do_retry;
7119                 }
7120         }
7121
7122         /* if the AQ access failed, try the old-fashioned way */
7123         if (status || use_register)
7124                 wr32(hw, reg_addr, reg_val);
7125 }
7126
7127 #ifdef PF_DRIVER
7128 /**
7129  * i40e_aq_set_phy_register
7130  * @hw: pointer to the hw struct
7131  * @phy_select: select which phy should be accessed
7132  * @dev_addr: PHY device address
7133  * @page_change: enable auto page change
7134  * @reg_addr: PHY register address
7135  * @reg_val: new register value
7136  * @cmd_details: pointer to command details structure or NULL
7137  *
7138  * Write the external PHY register.
7139  **/
7140 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,
7141                                 u8 phy_select, u8 dev_addr, bool page_change,
7142                                 u32 reg_addr, u32 reg_val,
7143                                 struct i40e_asq_cmd_details *cmd_details)
7144 {
7145         struct i40e_aq_desc desc;
7146         struct i40e_aqc_phy_register_access *cmd =
7147                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7148         enum i40e_status_code status;
7149
7150         i40e_fill_default_direct_cmd_desc(&desc,
7151                                           i40e_aqc_opc_set_phy_register);
7152
7153         cmd->phy_interface = phy_select;
7154         cmd->dev_addres = dev_addr;
7155         cmd->reg_address = CPU_TO_LE32(reg_addr);
7156         cmd->reg_value = CPU_TO_LE32(reg_val);
7157
7158         if (!page_change)
7159                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7160
7161         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7162
7163         return status;
7164 }
7165
7166 /**
7167  * i40e_aq_get_phy_register
7168  * @hw: pointer to the hw struct
7169  * @phy_select: select which phy should be accessed
7170  * @dev_addr: PHY device address
7171  * @page_change: enable auto page change
7172  * @reg_addr: PHY register address
7173  * @reg_val: read register value
7174  * @cmd_details: pointer to command details structure or NULL
7175  *
7176  * Read the external PHY register.
7177  **/
7178 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,
7179                                 u8 phy_select, u8 dev_addr, bool page_change,
7180                                 u32 reg_addr, u32 *reg_val,
7181                                 struct i40e_asq_cmd_details *cmd_details)
7182 {
7183         struct i40e_aq_desc desc;
7184         struct i40e_aqc_phy_register_access *cmd =
7185                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
7186         enum i40e_status_code status;
7187
7188         i40e_fill_default_direct_cmd_desc(&desc,
7189                                           i40e_aqc_opc_get_phy_register);
7190
7191         cmd->phy_interface = phy_select;
7192         cmd->dev_addres = dev_addr;
7193         cmd->reg_address = CPU_TO_LE32(reg_addr);
7194
7195         if (!page_change)
7196                 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
7197
7198         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7199         if (!status)
7200                 *reg_val = LE32_TO_CPU(cmd->reg_value);
7201
7202         return status;
7203 }
7204
7205 #endif /* PF_DRIVER */
7206 #ifdef VF_DRIVER
7207
7208 /**
7209  * i40e_aq_send_msg_to_pf
7210  * @hw: pointer to the hardware structure
7211  * @v_opcode: opcodes for VF-PF communication
7212  * @v_retval: return error code
7213  * @msg: pointer to the msg buffer
7214  * @msglen: msg length
7215  * @cmd_details: pointer to command details
7216  *
7217  * Send message to PF driver using admin queue. By default, this message
7218  * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for
7219  * completion before returning.
7220  **/
7221 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
7222                                 enum virtchnl_ops v_opcode,
7223                                 enum i40e_status_code v_retval,
7224                                 u8 *msg, u16 msglen,
7225                                 struct i40e_asq_cmd_details *cmd_details)
7226 {
7227         struct i40e_aq_desc desc;
7228         struct i40e_asq_cmd_details details;
7229         enum i40e_status_code status;
7230
7231         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
7232         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);
7233         desc.cookie_high = CPU_TO_LE32(v_opcode);
7234         desc.cookie_low = CPU_TO_LE32(v_retval);
7235         if (msglen) {
7236                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF
7237                                                 | I40E_AQ_FLAG_RD));
7238                 if (msglen > I40E_AQ_LARGE_BUF)
7239                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7240                 desc.datalen = CPU_TO_LE16(msglen);
7241         }
7242         if (!cmd_details) {
7243                 i40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);
7244                 details.async = true;
7245                 cmd_details = &details;
7246         }
7247         status = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,
7248                                        msglen, cmd_details);
7249         return status;
7250 }
7251
7252 /**
7253  * i40e_vf_parse_hw_config
7254  * @hw: pointer to the hardware structure
7255  * @msg: pointer to the virtual channel VF resource structure
7256  *
7257  * Given a VF resource message from the PF, populate the hw struct
7258  * with appropriate information.
7259  **/
7260 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
7261                              struct virtchnl_vf_resource *msg)
7262 {
7263         struct virtchnl_vsi_resource *vsi_res;
7264         int i;
7265
7266         vsi_res = &msg->vsi_res[0];
7267
7268         hw->dev_caps.num_vsis = msg->num_vsis;
7269         hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
7270         hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
7271         hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
7272         hw->dev_caps.dcb = msg->vf_cap_flags &
7273                            VIRTCHNL_VF_OFFLOAD_L2;
7274         hw->dev_caps.iwarp = (msg->vf_cap_flags &
7275                               VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
7276         for (i = 0; i < msg->num_vsis; i++) {
7277                 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
7278                         i40e_memcpy(hw->mac.perm_addr,
7279                                     vsi_res->default_mac_addr,
7280                                     ETH_ALEN,
7281                                     I40E_NONDMA_TO_NONDMA);
7282                         i40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,
7283                                     ETH_ALEN,
7284                                     I40E_NONDMA_TO_NONDMA);
7285                 }
7286                 vsi_res++;
7287         }
7288 }
7289
7290 /**
7291  * i40e_vf_reset
7292  * @hw: pointer to the hardware structure
7293  *
7294  * Send a VF_RESET message to the PF. Does not wait for response from PF
7295  * as none will be forthcoming. Immediately after calling this function,
7296  * the admin queue should be shut down and (optionally) reinitialized.
7297  **/
7298 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)
7299 {
7300         return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
7301                                       I40E_SUCCESS, NULL, 0, NULL);
7302 }
7303 #endif /* VF_DRIVER */
7304
7305 /**
7306  * i40e_aq_set_arp_proxy_config
7307  * @hw: pointer to the HW structure
7308  * @proxy_config: pointer to proxy config command table struct
7309  * @cmd_details: pointer to command details
7310  *
7311  * Set ARP offload parameters from pre-populated
7312  * i40e_aqc_arp_proxy_data struct
7313  **/
7314 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
7315                                 struct i40e_aqc_arp_proxy_data *proxy_config,
7316                                 struct i40e_asq_cmd_details *cmd_details)
7317 {
7318         struct i40e_aq_desc desc;
7319         enum i40e_status_code status;
7320
7321         if (!proxy_config)
7322                 return I40E_ERR_PARAM;
7323
7324         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);
7325
7326         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7327         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7328         desc.params.external.addr_high =
7329                                   CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
7330         desc.params.external.addr_low =
7331                                   CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
7332         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));
7333
7334         status = i40e_asq_send_command(hw, &desc, proxy_config,
7335                                        sizeof(struct i40e_aqc_arp_proxy_data),
7336                                        cmd_details);
7337
7338         return status;
7339 }
7340
7341 /**
7342  * i40e_aq_opc_set_ns_proxy_table_entry
7343  * @hw: pointer to the HW structure
7344  * @ns_proxy_table_entry: pointer to NS table entry command struct
7345  * @cmd_details: pointer to command details
7346  *
7347  * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
7348  * from pre-populated i40e_aqc_ns_proxy_data struct
7349  **/
7350 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
7351                         struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
7352                         struct i40e_asq_cmd_details *cmd_details)
7353 {
7354         struct i40e_aq_desc desc;
7355         enum i40e_status_code status;
7356
7357         if (!ns_proxy_table_entry)
7358                 return I40E_ERR_PARAM;
7359
7360         i40e_fill_default_direct_cmd_desc(&desc,
7361                                 i40e_aqc_opc_set_ns_proxy_table_entry);
7362
7363         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7364         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7365         desc.params.external.addr_high =
7366                 CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
7367         desc.params.external.addr_low =
7368                 CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
7369         desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));
7370
7371         status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
7372                                        sizeof(struct i40e_aqc_ns_proxy_data),
7373                                        cmd_details);
7374
7375         return status;
7376 }
7377
7378 /**
7379  * i40e_aq_set_clear_wol_filter
7380  * @hw: pointer to the hw struct
7381  * @filter_index: index of filter to modify (0-7)
7382  * @filter: buffer containing filter to be set
7383  * @set_filter: true to set filter, false to clear filter
7384  * @no_wol_tco: if true, pass through packets cannot cause wake-up
7385  *              if false, pass through packets may cause wake-up
7386  * @filter_valid: true if filter action is valid
7387  * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
7388  * @cmd_details: pointer to command details structure or NULL
7389  *
7390  * Set or clear WoL filter for port attached to the PF
7391  **/
7392 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
7393                                 u8 filter_index,
7394                                 struct i40e_aqc_set_wol_filter_data *filter,
7395                                 bool set_filter, bool no_wol_tco,
7396                                 bool filter_valid, bool no_wol_tco_valid,
7397                                 struct i40e_asq_cmd_details *cmd_details)
7398 {
7399         struct i40e_aq_desc desc;
7400         struct i40e_aqc_set_wol_filter *cmd =
7401                 (struct i40e_aqc_set_wol_filter *)&desc.params.raw;
7402         enum i40e_status_code status;
7403         u16 cmd_flags = 0;
7404         u16 valid_flags = 0;
7405         u16 buff_len = 0;
7406
7407         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter);
7408
7409         if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
7410                 return  I40E_ERR_PARAM;
7411         cmd->filter_index = CPU_TO_LE16(filter_index);
7412
7413         if (set_filter) {
7414                 if (!filter)
7415                         return  I40E_ERR_PARAM;
7416
7417                 cmd_flags |= I40E_AQC_SET_WOL_FILTER;
7418                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
7419         }
7420
7421         if (no_wol_tco)
7422                 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
7423         cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
7424
7425         if (filter_valid)
7426                 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
7427         if (no_wol_tco_valid)
7428                 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
7429         cmd->valid_flags = CPU_TO_LE16(valid_flags);
7430
7431         buff_len = sizeof(*filter);
7432         desc.datalen = CPU_TO_LE16(buff_len);
7433
7434         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7435         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
7436
7437         cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
7438         cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));
7439
7440         status = i40e_asq_send_command(hw, &desc, filter,
7441                                        buff_len, cmd_details);
7442
7443         return status;
7444 }
7445
7446 /**
7447  * i40e_aq_get_wake_event_reason
7448  * @hw: pointer to the hw struct
7449  * @wake_reason: return value, index of matching filter
7450  * @cmd_details: pointer to command details structure or NULL
7451  *
7452  * Get information for the reason of a Wake Up event
7453  **/
7454 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
7455                                 u16 *wake_reason,
7456                                 struct i40e_asq_cmd_details *cmd_details)
7457 {
7458         struct i40e_aq_desc desc;
7459         struct i40e_aqc_get_wake_reason_completion *resp =
7460                 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw;
7461         enum i40e_status_code status;
7462
7463         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);
7464
7465         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7466
7467         if (status == I40E_SUCCESS)
7468                 *wake_reason = LE16_TO_CPU(resp->wake_reason);
7469
7470         return status;
7471 }
7472
7473 /**
7474 * i40e_aq_clear_all_wol_filters
7475 * @hw: pointer to the hw struct
7476 * @cmd_details: pointer to command details structure or NULL
7477 *
7478 * Get information for the reason of a Wake Up event
7479 **/
7480 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
7481         struct i40e_asq_cmd_details *cmd_details)
7482 {
7483         struct i40e_aq_desc desc;
7484         enum i40e_status_code status;
7485
7486         i40e_fill_default_direct_cmd_desc(&desc,
7487                                           i40e_aqc_opc_clear_all_wol_filters);
7488
7489         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
7490
7491         return status;
7492 }
7493
7494 /**
7495  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
7496  * @hw: pointer to the hw struct
7497  * @buff: command buffer (size in bytes = buff_size)
7498  * @buff_size: buffer size in bytes
7499  * @track_id: package tracking id
7500  * @error_offset: returns error offset
7501  * @error_info: returns error information
7502  * @cmd_details: pointer to command details structure or NULL
7503  **/
7504 enum
7505 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
7506                                    u16 buff_size, u32 track_id,
7507                                    u32 *error_offset, u32 *error_info,
7508                                    struct i40e_asq_cmd_details *cmd_details)
7509 {
7510         struct i40e_aq_desc desc;
7511         struct i40e_aqc_write_personalization_profile *cmd =
7512                 (struct i40e_aqc_write_personalization_profile *)
7513                 &desc.params.raw;
7514         struct i40e_aqc_write_ddp_resp *resp;
7515         enum i40e_status_code status;
7516
7517         i40e_fill_default_direct_cmd_desc(&desc,
7518                                   i40e_aqc_opc_write_personalization_profile);
7519
7520         desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
7521         if (buff_size > I40E_AQ_LARGE_BUF)
7522                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7523
7524         desc.datalen = CPU_TO_LE16(buff_size);
7525
7526         cmd->profile_track_id = CPU_TO_LE32(track_id);
7527
7528         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7529         if (!status) {
7530                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
7531                 if (error_offset)
7532                         *error_offset = LE32_TO_CPU(resp->error_offset);
7533                 if (error_info)
7534                         *error_info = LE32_TO_CPU(resp->error_info);
7535         }
7536
7537         return status;
7538 }
7539
7540 /**
7541  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
7542  * @hw: pointer to the hw struct
7543  * @buff: command buffer (size in bytes = buff_size)
7544  * @buff_size: buffer size in bytes
7545  * @flags: AdminQ command flags
7546  * @cmd_details: pointer to command details structure or NULL
7547  **/
7548 enum
7549 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
7550                                       u16 buff_size, u8 flags,
7551                                       struct i40e_asq_cmd_details *cmd_details)
7552 {
7553         struct i40e_aq_desc desc;
7554         struct i40e_aqc_get_applied_profiles *cmd =
7555                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
7556         enum i40e_status_code status;
7557
7558         i40e_fill_default_direct_cmd_desc(&desc,
7559                           i40e_aqc_opc_get_personalization_profile_list);
7560
7561         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
7562         if (buff_size > I40E_AQ_LARGE_BUF)
7563                 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7564         desc.datalen = CPU_TO_LE16(buff_size);
7565
7566         cmd->flags = flags;
7567
7568         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
7569
7570         return status;
7571 }
7572
7573 /**
7574  * i40e_find_segment_in_package
7575  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
7576  * @pkg_hdr: pointer to the package header to be searched
7577  *
7578  * This function searches a package file for a particular segment type. On
7579  * success it returns a pointer to the segment header, otherwise it will
7580  * return NULL.
7581  **/
7582 struct i40e_generic_seg_header *
7583 i40e_find_segment_in_package(u32 segment_type,
7584                              struct i40e_package_header *pkg_hdr)
7585 {
7586         struct i40e_generic_seg_header *segment;
7587         u32 i;
7588
7589         /* Search all package segments for the requested segment type */
7590         for (i = 0; i < pkg_hdr->segment_count; i++) {
7591                 segment =
7592                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
7593                          pkg_hdr->segment_offset[i]);
7594
7595                 if (segment->type == segment_type)
7596                         return segment;
7597         }
7598
7599         return NULL;
7600 }
7601
7602 /* Get section table in profile */
7603 #define I40E_SECTION_TABLE(profile, sec_tbl)                            \
7604         do {                                                            \
7605                 struct i40e_profile_segment *p = (profile);             \
7606                 u32 count;                                              \
7607                 u32 *nvm;                                               \
7608                 count = p->device_table_count;                          \
7609                 nvm = (u32 *)&p->device_table[count];                   \
7610                 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
7611         } while (0)
7612
7613 /* Get section header in profile */
7614 #define I40E_SECTION_HEADER(profile, offset)                            \
7615         (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
7616
7617 /**
7618  * i40e_find_section_in_profile
7619  * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
7620  * @profile: pointer to the i40e segment header to be searched
7621  *
7622  * This function searches i40e segment for a particular section type. On
7623  * success it returns a pointer to the section header, otherwise it will
7624  * return NULL.
7625  **/
7626 struct i40e_profile_section_header *
7627 i40e_find_section_in_profile(u32 section_type,
7628                              struct i40e_profile_segment *profile)
7629 {
7630         struct i40e_profile_section_header *sec;
7631         struct i40e_section_table *sec_tbl;
7632         u32 sec_off;
7633         u32 i;
7634
7635         if (profile->header.type != SEGMENT_TYPE_I40E)
7636                 return NULL;
7637
7638         I40E_SECTION_TABLE(profile, sec_tbl);
7639
7640         for (i = 0; i < sec_tbl->section_count; i++) {
7641                 sec_off = sec_tbl->section_offset[i];
7642                 sec = I40E_SECTION_HEADER(profile, sec_off);
7643                 if (sec->section.type == section_type)
7644                         return sec;
7645         }
7646
7647         return NULL;
7648 }
7649
7650 /**
7651  * i40e_ddp_exec_aq_section - Execute generic AQ for DDP
7652  * @hw: pointer to the hw struct
7653  * @aq: command buffer containing all data to execute AQ
7654  **/
7655 STATIC enum
7656 i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
7657                                           struct i40e_profile_aq_section *aq)
7658 {
7659         enum i40e_status_code status;
7660         struct i40e_aq_desc desc;
7661         u8 *msg = NULL;
7662         u16 msglen;
7663
7664         i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
7665         desc.flags |= CPU_TO_LE16(aq->flags);
7666         i40e_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
7667                     I40E_NONDMA_TO_NONDMA);
7668
7669         msglen = aq->datalen;
7670         if (msglen) {
7671                 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |
7672                                                 I40E_AQ_FLAG_RD));
7673                 if (msglen > I40E_AQ_LARGE_BUF)
7674                         desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
7675                 desc.datalen = CPU_TO_LE16(msglen);
7676                 msg = &aq->data[0];
7677         }
7678
7679         status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
7680
7681         if (status != I40E_SUCCESS) {
7682                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7683                            "unable to exec DDP AQ opcode %u, error %d\n",
7684                            aq->opcode, status);
7685                 return status;
7686         }
7687
7688         /* copy returned desc to aq_buf */
7689         i40e_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
7690                     I40E_NONDMA_TO_NONDMA);
7691
7692         return I40E_SUCCESS;
7693 }
7694
7695 /**
7696  * i40e_validate_profile
7697  * @hw: pointer to the hardware structure
7698  * @profile: pointer to the profile segment of the package to be validated
7699  * @track_id: package tracking id
7700  * @rollback: flag if the profile is for rollback.
7701  *
7702  * Validates supported devices and profile's sections.
7703  */
7704 STATIC enum i40e_status_code
7705 i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7706                       u32 track_id, bool rollback)
7707 {
7708         struct i40e_profile_section_header *sec = NULL;
7709         enum i40e_status_code status = I40E_SUCCESS;
7710         struct i40e_section_table *sec_tbl;
7711         u32 vendor_dev_id;
7712         u32 dev_cnt;
7713         u32 sec_off;
7714         u32 i;
7715
7716         if (track_id == I40E_DDP_TRACKID_INVALID) {
7717                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
7718                 return I40E_NOT_SUPPORTED;
7719         }
7720
7721         dev_cnt = profile->device_table_count;
7722         for (i = 0; i < dev_cnt; i++) {
7723                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
7724                 if ((vendor_dev_id >> 16) == I40E_INTEL_VENDOR_ID &&
7725                     hw->device_id == (vendor_dev_id & 0xFFFF))
7726                         break;
7727         }
7728         if (dev_cnt && (i == dev_cnt)) {
7729                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7730                            "Device doesn't support DDP\n");
7731                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
7732         }
7733
7734         I40E_SECTION_TABLE(profile, sec_tbl);
7735
7736         /* Validate sections types */
7737         for (i = 0; i < sec_tbl->section_count; i++) {
7738                 sec_off = sec_tbl->section_offset[i];
7739                 sec = I40E_SECTION_HEADER(profile, sec_off);
7740                 if (rollback) {
7741                         if (sec->section.type == SECTION_TYPE_MMIO ||
7742                             sec->section.type == SECTION_TYPE_AQ ||
7743                             sec->section.type == SECTION_TYPE_RB_AQ) {
7744                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7745                                            "Not a roll-back package\n");
7746                                 return I40E_NOT_SUPPORTED;
7747                         }
7748                 } else {
7749                         if (sec->section.type == SECTION_TYPE_RB_AQ ||
7750                             sec->section.type == SECTION_TYPE_RB_MMIO) {
7751                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7752                                            "Not an original package\n");
7753                                 return I40E_NOT_SUPPORTED;
7754                         }
7755                 }
7756         }
7757
7758         return status;
7759 }
7760
7761 /**
7762  * i40e_write_profile
7763  * @hw: pointer to the hardware structure
7764  * @profile: pointer to the profile segment of the package to be downloaded
7765  * @track_id: package tracking id
7766  *
7767  * Handles the download of a complete package.
7768  */
7769 enum i40e_status_code
7770 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7771                    u32 track_id)
7772 {
7773         enum i40e_status_code status = I40E_SUCCESS;
7774         struct i40e_section_table *sec_tbl;
7775         struct i40e_profile_section_header *sec = NULL;
7776         struct i40e_profile_aq_section *ddp_aq;
7777         u32 section_size = 0;
7778         u32 offset = 0, info = 0;
7779         u32 sec_off;
7780         u32 i;
7781
7782         status = i40e_validate_profile(hw, profile, track_id, false);
7783         if (status)
7784                 return status;
7785
7786         I40E_SECTION_TABLE(profile, sec_tbl);
7787
7788         for (i = 0; i < sec_tbl->section_count; i++) {
7789                 sec_off = sec_tbl->section_offset[i];
7790                 sec = I40E_SECTION_HEADER(profile, sec_off);
7791                 /* Process generic admin command */
7792                 if (sec->section.type == SECTION_TYPE_AQ) {
7793                         ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
7794                         status = i40e_ddp_exec_aq_section(hw, ddp_aq);
7795                         if (status) {
7796                                 i40e_debug(hw, I40E_DEBUG_PACKAGE,
7797                                            "Failed to execute aq: section %d, opcode %u\n",
7798                                            i, ddp_aq->opcode);
7799                                 break;
7800                         }
7801                         sec->section.type = SECTION_TYPE_RB_AQ;
7802                 }
7803
7804                 /* Skip any non-mmio sections */
7805                 if (sec->section.type != SECTION_TYPE_MMIO)
7806                         continue;
7807
7808                 section_size = sec->section.size +
7809                         sizeof(struct i40e_profile_section_header);
7810
7811                 /* Write MMIO section */
7812                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7813                                            track_id, &offset, &info, NULL);
7814                 if (status) {
7815                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7816                                    "Failed to write profile: section %d, offset %d, info %d\n",
7817                                    i, offset, info);
7818                         break;
7819                 }
7820         }
7821         return status;
7822 }
7823
7824 /**
7825  * i40e_rollback_profile
7826  * @hw: pointer to the hardware structure
7827  * @profile: pointer to the profile segment of the package to be removed
7828  * @track_id: package tracking id
7829  *
7830  * Rolls back previously loaded package.
7831  */
7832 enum i40e_status_code
7833 i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
7834                       u32 track_id)
7835 {
7836         struct i40e_profile_section_header *sec = NULL;
7837         enum i40e_status_code status = I40E_SUCCESS;
7838         struct i40e_section_table *sec_tbl;
7839         u32 offset = 0, info = 0;
7840         u32 section_size = 0;
7841         u32 sec_off;
7842         int i;
7843
7844         status = i40e_validate_profile(hw, profile, track_id, true);
7845         if (status)
7846                 return status;
7847
7848         I40E_SECTION_TABLE(profile, sec_tbl);
7849
7850         /* For rollback write sections in reverse */
7851         for (i = sec_tbl->section_count - 1; i >= 0; i--) {
7852                 sec_off = sec_tbl->section_offset[i];
7853                 sec = I40E_SECTION_HEADER(profile, sec_off);
7854
7855                 /* Skip any non-rollback sections */
7856                 if (sec->section.type != SECTION_TYPE_RB_MMIO)
7857                         continue;
7858
7859                 section_size = sec->section.size +
7860                         sizeof(struct i40e_profile_section_header);
7861
7862                 /* Write roll-back MMIO section */
7863                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
7864                                            track_id, &offset, &info, NULL);
7865                 if (status) {
7866                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
7867                                    "Failed to write profile: section %d, offset %d, info %d\n",
7868                                    i, offset, info);
7869                         break;
7870                 }
7871         }
7872         return status;
7873 }
7874
7875 /**
7876  * i40e_add_pinfo_to_list
7877  * @hw: pointer to the hardware structure
7878  * @profile: pointer to the profile segment of the package
7879  * @profile_info_sec: buffer for information section
7880  * @track_id: package tracking id
7881  *
7882  * Register a profile to the list of loaded profiles.
7883  */
7884 enum i40e_status_code
7885 i40e_add_pinfo_to_list(struct i40e_hw *hw,
7886                        struct i40e_profile_segment *profile,
7887                        u8 *profile_info_sec, u32 track_id)
7888 {
7889         enum i40e_status_code status = I40E_SUCCESS;
7890         struct i40e_profile_section_header *sec = NULL;
7891         struct i40e_profile_info *pinfo;
7892         u32 offset = 0, info = 0;
7893
7894         sec = (struct i40e_profile_section_header *)profile_info_sec;
7895         sec->tbl_size = 1;
7896         sec->data_end = sizeof(struct i40e_profile_section_header) +
7897                         sizeof(struct i40e_profile_info);
7898         sec->section.type = SECTION_TYPE_INFO;
7899         sec->section.offset = sizeof(struct i40e_profile_section_header);
7900         sec->section.size = sizeof(struct i40e_profile_info);
7901         pinfo = (struct i40e_profile_info *)(profile_info_sec +
7902                                              sec->section.offset);
7903         pinfo->track_id = track_id;
7904         pinfo->version = profile->version;
7905         pinfo->op = I40E_DDP_ADD_TRACKID;
7906         i40e_memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE,
7907                     I40E_NONDMA_TO_NONDMA);
7908
7909         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
7910                                    track_id, &offset, &info, NULL);
7911         return status;
7912 }