drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51
  52 /* Maximun number of capability elements */
  53 #define I40E_MAX_CAP_ELE_NUM       128
  54
  55 /* Wait count and interval */
  56 #define I40E_CHK_Q_ENA_COUNT       1000
  57 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  58
  59 /* Maximun number of VSI */
  60 #define I40E_MAX_NUM_VSIS          (384UL)
  61
  62 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  63
  64 /* Flow control default timer */
  65 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  66
  67 /* Flow control enable fwd bit */
  68 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  69
  70 /* Receive Packet Buffer size */
  71 #define I40E_RXPBSIZE (968 * 1024)
  72
  73 /* Kilobytes shift */
  74 #define I40E_KILOSHIFT 10
  75
  76 /* Flow control default high water */
  77 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  78
  79 /* Flow control default low water */
  80 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Receive Average Packet Size in Byte*/
  83 #define I40E_PACKET_AVERAGE_SIZE 128
  84
  85 /* Mask of PF interrupt causes */
  86 #define I40E_PFINT_ICR0_ENA_MASK ( \
  87                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  89                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  90                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  91                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  96
  97 #define I40E_FLOW_TYPES ( \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 108         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 109
 110 /* Additional timesync values. */
 111 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 112 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 113 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 114 #define I40E_PRTTSYN_TSYNENA     0x80000000
 115 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 116 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 /**
 119  * Below are values for writing un-exposed registers suggested
 120  * by silicon experts
 121  */
 122 /* Destination MAC address */
 123 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 124 /* Source MAC address */
 125 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 126 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 128 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 130 /* Single VLAN tag in the inner L2 header */
 131 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 132 /* Source IPv4 address */
 133 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 134 /* Destination IPv4 address */
 135 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 136 /* Source IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 138 /* Destination IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 140 /* IPv4 Protocol for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 142 /* IPv4 Time to Live for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 144 /* IPv4 Type of Service (TOS) */
 145 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 146 /* IPv4 Protocol */
 147 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 148 /* IPv4 Time to Live */
 149 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 150 /* Source IPv6 address */
 151 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 152 /* Destination IPv6 address */
 153 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 154 /* IPv6 Traffic Class (TC) */
 155 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 156 /* IPv6 Next Header */
 157 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 158 /* IPv6 Hop Limit */
 159 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 160 /* Source L4 port */
 161 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 162 /* Destination L4 port */
 163 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 164 /* SCTP verification tag */
 165 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 166 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 167 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 168 /* Source port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 170 /* Destination port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 172 /* UDP Tunneling ID, NVGRE/GRE key */
 173 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 174 /* Last ether type */
 175 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 176 /* Tunneling outer destination IPv4 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 178 /* Tunneling outer destination IPv6 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 180 /* 1st word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 182 /* 2nd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 184 /* 3rd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 186 /* 4th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 188 /* 5th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 190 /* 6th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 192 /* 7th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 194 /* 8th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 196 /* all 8 words flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 198 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 199
 200 #define I40E_TRANSLATE_INSET 0
 201 #define I40E_TRANSLATE_REG   1
 202
 203 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 204 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 205 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 206 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 207 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 208 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 209
 210 /* PCI offset for querying capability */
 211 #define PCI_DEV_CAP_REG            0xA4
 212 /* PCI offset for enabling/disabling Extended Tag */
 213 #define PCI_DEV_CTRL_REG           0xA8
 214 /* Bit mask of Extended Tag capability */
 215 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 216 /* Bit shift of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 218 /* Bit mask of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 220
 221 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 222 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 223 static int i40e_dev_configure(struct rte_eth_dev *dev);
 224 static int i40e_dev_start(struct rte_eth_dev *dev);
 225 static void i40e_dev_stop(struct rte_eth_dev *dev);
 226 static void i40e_dev_close(struct rte_eth_dev *dev);
 227 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 229 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 233 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 234 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_stats *stats);
 236 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_xstat *xstats, unsigned n);
 238 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 239                                      struct rte_eth_xstat_name *xstats_names,
 240                                      unsigned limit);
 241 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 245                              struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct rte_ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static void i40e_dev_alarm_handler(void *param);
 294 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 295                                 uint32_t base, uint32_t num);
 296 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 297 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 298                         uint32_t base);
 299 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 300                         uint16_t num);
 301 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 302 static int i40e_veb_release(struct i40e_veb *veb);
 303 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 304                                                 struct i40e_vsi *vsi);
 305 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 306 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 307 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 308                                              struct i40e_macvlan_filter *mv_f,
 309                                              int num,
 310                                              uint16_t vlan);
 311 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 312 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 313                                     struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 315                                       struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 321 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 325                                 enum rte_filter_type filter_type,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 329                                   struct rte_eth_dcb_info *dcb_info);
 330 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 331 static void i40e_configure_registers(struct i40e_hw *hw);
 332 static void i40e_hw_init(struct rte_eth_dev *dev);
 333 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 334 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 335                                                      uint16_t seid,
 336                                                      uint16_t rule_type,
 337                                                      uint16_t *entries,
 338                                                      uint16_t count,
 339                                                      uint16_t rule_id);
 340 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 341                         struct rte_eth_mirror_conf *mirror_conf,
 342                         uint8_t sw_id, uint8_t on);
 343 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 344
 345 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 347 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 348                                            struct timespec *timestamp,
 349                                            uint32_t flags);
 350 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 351                                            struct timespec *timestamp);
 352 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 353
 354 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 355
 356 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 357                                    struct timespec *timestamp);
 358 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 359                                     const struct timespec *timestamp);
 360
 361 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 362                                          uint16_t queue_id);
 363 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 364                                           uint16_t queue_id);
 365
 366 static int i40e_get_regs(struct rte_eth_dev *dev,
 367                          struct rte_dev_reg_info *regs);
 368
 369 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 370
 371 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 372                            struct rte_dev_eeprom_info *eeprom);
 373
 374 static int i40e_get_module_info(struct rte_eth_dev *dev,
 375                                 struct rte_eth_dev_module_info *modinfo);
 376 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 377                                   struct rte_dev_eeprom_info *info);
 378
 379 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 380                                       struct rte_ether_addr *mac_addr);
 381
 382 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 383
 384 static int i40e_ethertype_filter_convert(
 385         const struct rte_eth_ethertype_filter *input,
 386         struct i40e_ethertype_filter *filter);
 387 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 388                                    struct i40e_ethertype_filter *filter);
 389
 390 static int i40e_tunnel_filter_convert(
 391         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 392         struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 394                                 struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 396
 397 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 398 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 399 static void i40e_filter_restore(struct i40e_pf *pf);
 400 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 401
 402 static const char *const valid_keys[] = {
 403         ETH_I40E_FLOATING_VEB_ARG,
 404         ETH_I40E_FLOATING_VEB_LIST_ARG,
 405         ETH_I40E_SUPPORT_MULTI_DRIVER,
 406         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 407         ETH_I40E_USE_LATEST_VEC,
 408         ETH_I40E_VF_MSG_CFG,
 409         NULL};
 410
 411 static const struct rte_pci_id pci_id_i40e_map[] = {
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 438         { .vendor_id = 0, /* sentinel */ },
 439 };
 440
 441 static const struct eth_dev_ops i40e_eth_dev_ops = {
 442         .dev_configure                = i40e_dev_configure,
 443         .dev_start                    = i40e_dev_start,
 444         .dev_stop                     = i40e_dev_stop,
 445         .dev_close                    = i40e_dev_close,
 446         .dev_reset                    = i40e_dev_reset,
 447         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 448         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 449         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 450         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 451         .dev_set_link_up              = i40e_dev_set_link_up,
 452         .dev_set_link_down            = i40e_dev_set_link_down,
 453         .link_update                  = i40e_dev_link_update,
 454         .stats_get                    = i40e_dev_stats_get,
 455         .xstats_get                   = i40e_dev_xstats_get,
 456         .xstats_get_names             = i40e_dev_xstats_get_names,
 457         .stats_reset                  = i40e_dev_stats_reset,
 458         .xstats_reset                 = i40e_dev_stats_reset,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 498         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517         .tx_done_cleanup              = i40e_tx_done_cleanup,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         unsigned offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 534         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 535         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 536         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 537 };
 538
 539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 540                 sizeof(rte_i40e_stats_strings[0]))
 541
 542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 543         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 544                 tx_dropped_link_down)},
 545         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 546         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 547                 illegal_bytes)},
 548         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 549         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_local_faults)},
 551         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_remote_faults)},
 553         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 554                 rx_length_errors)},
 555         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 556         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 557         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 558         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 559         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 560         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_127)},
 562         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_255)},
 564         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_511)},
 566         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1023)},
 568         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1522)},
 570         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_big)},
 572         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_undersize)},
 574         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_oversize)},
 576         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 577                 mac_short_packet_dropped)},
 578         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_fragments)},
 580         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 581         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 582         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_127)},
 584         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_255)},
 586         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_511)},
 588         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1023)},
 590         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1522)},
 592         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_big)},
 594         {"rx_flow_director_atr_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 596         {"rx_flow_director_sb_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 598         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_status)},
 600         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_status)},
 602         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_count)},
 604         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_count)},
 606 };
 607
 608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 609                 sizeof(rte_i40e_hw_port_strings[0]))
 610
 611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 612         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xon_rx)},
 614         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xoff_rx)},
 616 };
 617
 618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 619                 sizeof(rte_i40e_rxq_prio_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_tx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_tx)},
 626         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_2_xoff)},
 628 };
 629
 630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 631                 sizeof(rte_i40e_txq_prio_strings[0]))
 632
 633 static int
 634 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         char name[RTE_ETH_NAME_MAX_LEN];
 638         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 639         int i, retval;
 640
 641         if (pci_dev->device.devargs) {
 642                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 643                                 &eth_da);
 644                 if (retval)
 645                         return retval;
 646         }
 647
 648         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 649                 sizeof(struct i40e_adapter),
 650                 eth_dev_pci_specific_init, pci_dev,
 651                 eth_i40e_dev_init, NULL);
 652
 653         if (retval || eth_da.nb_representor_ports < 1)
 654                 return retval;
 655
 656         /* probe VF representor ports */
 657         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 658                 pci_dev->device.name);
 659
 660         if (pf_ethdev == NULL)
 661                 return -ENODEV;
 662
 663         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 664                 struct i40e_vf_representor representor = {
 665                         .vf_id = eth_da.representor_ports[i],
 666                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 667                                 pf_ethdev->data->dev_private)->switch_domain_id,
 668                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 669                                 pf_ethdev->data->dev_private)
 670                 };
 671
 672                 /* representor port net_bdf_port */
 673                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 674                         pci_dev->device.name, eth_da.representor_ports[i]);
 675
 676                 retval = rte_eth_dev_create(&pci_dev->device, name,
 677                         sizeof(struct i40e_vf_representor), NULL, NULL,
 678                         i40e_vf_representor_init, &representor);
 679
 680                 if (retval)
 681                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 682                                 "representor %s.", name);
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 689 {
 690         struct rte_eth_dev *ethdev;
 691
 692         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 693         if (!ethdev)
 694                 return 0;
 695
 696         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 697                 return rte_eth_dev_pci_generic_remove(pci_dev,
 698                                         i40e_vf_representor_uninit);
 699         else
 700                 return rte_eth_dev_pci_generic_remove(pci_dev,
 701                                                 eth_i40e_dev_uninit);
 702 }
 703
 704 static struct rte_pci_driver rte_i40e_pmd = {
 705         .id_table = pci_id_i40e_map,
 706         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 707         .probe = eth_i40e_pci_probe,
 708         .remove = eth_i40e_pci_remove,
 709 };
 710
 711 static inline void
 712 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 713                          uint32_t reg_val)
 714 {
 715         uint32_t ori_reg_val;
 716         struct rte_eth_dev *dev;
 717
 718         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 719         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 720         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 721         if (ori_reg_val != reg_val)
 722                 PMD_DRV_LOG(WARNING,
 723                             "i40e device %s changed global register [0x%08x]."
 724                             " original: 0x%08x, new: 0x%08x",
 725                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 726 }
 727
 728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 730 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 731
 732 #ifndef I40E_GLQF_ORT
 733 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_PIT
 736 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 737 #endif
 738 #ifndef I40E_GLQF_L3_MAP
 739 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 740 #endif
 741
 742 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 743 {
 744         /*
 745          * Initialize registers for parsing packet type of QinQ
 746          * This should be removed from code once proper
 747          * configuration API is added to avoid configuration conflicts
 748          * between ports of the same device.
 749          */
 750         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 751         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 752 }
 753
 754 static inline void i40e_config_automask(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint32_t val;
 758
 759         /* INTENA flag is not auto-cleared for interrupt */
 760         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 761         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 762                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 763
 764         /* If support multi-driver, PF will use INT0. */
 765         if (!pf->support_multi_driver)
 766                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 767
 768         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 769 }
 770
 771 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 772
 773 /*
 774  * Add a ethertype filter to drop all flow control frames transmitted
 775  * from VSIs.
 776 */
 777 static void
 778 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 779 {
 780         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 781         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 782                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 783                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 784         int ret;
 785
 786         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 787                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 788                                 pf->main_vsi_seid, 0,
 789                                 TRUE, NULL, NULL);
 790         if (ret)
 791                 PMD_INIT_LOG(ERR,
 792                         "Failed to add filter to drop flow control frames from VSIs.");
 793 }
 794
 795 static int
 796 floating_veb_list_handler(__rte_unused const char *key,
 797                           const char *floating_veb_value,
 798                           void *opaque)
 799 {
 800         int idx = 0;
 801         unsigned int count = 0;
 802         char *end = NULL;
 803         int min, max;
 804         bool *vf_floating_veb = opaque;
 805
 806         while (isblank(*floating_veb_value))
 807                 floating_veb_value++;
 808
 809         /* Reset floating VEB configuration for VFs */
 810         for (idx = 0; idx < I40E_MAX_VF; idx++)
 811                 vf_floating_veb[idx] = false;
 812
 813         min = I40E_MAX_VF;
 814         do {
 815                 while (isblank(*floating_veb_value))
 816                         floating_veb_value++;
 817                 if (*floating_veb_value == '\0')
 818                         return -1;
 819                 errno = 0;
 820                 idx = strtoul(floating_veb_value, &end, 10);
 821                 if (errno || end == NULL)
 822                         return -1;
 823                 while (isblank(*end))
 824                         end++;
 825                 if (*end == '-') {
 826                         min = idx;
 827                 } else if ((*end == ';') || (*end == '\0')) {
 828                         max = idx;
 829                         if (min == I40E_MAX_VF)
 830                                 min = idx;
 831                         if (max >= I40E_MAX_VF)
 832                                 max = I40E_MAX_VF - 1;
 833                         for (idx = min; idx <= max; idx++) {
 834                                 vf_floating_veb[idx] = true;
 835                                 count++;
 836                         }
 837                         min = I40E_MAX_VF;
 838                 } else {
 839                         return -1;
 840                 }
 841                 floating_veb_value = end + 1;
 842         } while (*end != '\0');
 843
 844         if (count == 0)
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static void
 851 config_vf_floating_veb(struct rte_devargs *devargs,
 852                        uint16_t floating_veb,
 853                        bool *vf_floating_veb)
 854 {
 855         struct rte_kvargs *kvlist;
 856         int i;
 857         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 858
 859         if (!floating_veb)
 860                 return;
 861         /* All the VFs attach to the floating VEB by default
 862          * when the floating VEB is enabled.
 863          */
 864         for (i = 0; i < I40E_MAX_VF; i++)
 865                 vf_floating_veb[i] = true;
 866
 867         if (devargs == NULL)
 868                 return;
 869
 870         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 871         if (kvlist == NULL)
 872                 return;
 873
 874         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 875                 rte_kvargs_free(kvlist);
 876                 return;
 877         }
 878         /* When the floating_veb_list parameter exists, all the VFs
 879          * will attach to the legacy VEB firstly, then configure VFs
 880          * to the floating VEB according to the floating_veb_list.
 881          */
 882         if (rte_kvargs_process(kvlist, floating_veb_list,
 883                                floating_veb_list_handler,
 884                                vf_floating_veb) < 0) {
 885                 rte_kvargs_free(kvlist);
 886                 return;
 887         }
 888         rte_kvargs_free(kvlist);
 889 }
 890
 891 static int
 892 i40e_check_floating_handler(__rte_unused const char *key,
 893                             const char *value,
 894                             __rte_unused void *opaque)
 895 {
 896         if (strcmp(value, "1"))
 897                 return -1;
 898
 899         return 0;
 900 }
 901
 902 static int
 903 is_floating_veb_supported(struct rte_devargs *devargs)
 904 {
 905         struct rte_kvargs *kvlist;
 906         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 907
 908         if (devargs == NULL)
 909                 return 0;
 910
 911         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 912         if (kvlist == NULL)
 913                 return 0;
 914
 915         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 916                 rte_kvargs_free(kvlist);
 917                 return 0;
 918         }
 919         /* Floating VEB is enabled when there's key-value:
 920          * enable_floating_veb=1
 921          */
 922         if (rte_kvargs_process(kvlist, floating_veb_key,
 923                                i40e_check_floating_handler, NULL) < 0) {
 924                 rte_kvargs_free(kvlist);
 925                 return 0;
 926         }
 927         rte_kvargs_free(kvlist);
 928
 929         return 1;
 930 }
 931
 932 static void
 933 config_floating_veb(struct rte_eth_dev *dev)
 934 {
 935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938
 939         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 940
 941         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 942                 pf->floating_veb =
 943                         is_floating_veb_supported(pci_dev->device.devargs);
 944                 config_vf_floating_veb(pci_dev->device.devargs,
 945                                        pf->floating_veb,
 946                                        pf->floating_veb_list);
 947         } else {
 948                 pf->floating_veb = false;
 949         }
 950 }
 951
 952 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 953 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 954
 955 static int
 956 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 957 {
 958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 959         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 960         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 961         int ret;
 962
 963         struct rte_hash_parameters ethertype_hash_params = {
 964                 .name = ethertype_hash_name,
 965                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 966                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 967                 .hash_func = rte_hash_crc,
 968                 .hash_func_init_val = 0,
 969                 .socket_id = rte_socket_id(),
 970         };
 971
 972         /* Initialize ethertype filter rule list and hash */
 973         TAILQ_INIT(&ethertype_rule->ethertype_list);
 974         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 975                  "ethertype_%s", dev->device->name);
 976         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 977         if (!ethertype_rule->hash_table) {
 978                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 979                 return -EINVAL;
 980         }
 981         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 982                                        sizeof(struct i40e_ethertype_filter *) *
 983                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 984                                        0);
 985         if (!ethertype_rule->hash_map) {
 986                 PMD_INIT_LOG(ERR,
 987                              "Failed to allocate memory for ethertype hash map!");
 988                 ret = -ENOMEM;
 989                 goto err_ethertype_hash_map_alloc;
 990         }
 991
 992         return 0;
 993
 994 err_ethertype_hash_map_alloc:
 995         rte_hash_free(ethertype_rule->hash_table);
 996
 997         return ret;
 998 }
 999
1000 static int
1001 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1002 {
1003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1005         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1006         int ret;
1007
1008         struct rte_hash_parameters tunnel_hash_params = {
1009                 .name = tunnel_hash_name,
1010                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1011                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1012                 .hash_func = rte_hash_crc,
1013                 .hash_func_init_val = 0,
1014                 .socket_id = rte_socket_id(),
1015         };
1016
1017         /* Initialize tunnel filter rule list and hash */
1018         TAILQ_INIT(&tunnel_rule->tunnel_list);
1019         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1020                  "tunnel_%s", dev->device->name);
1021         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1022         if (!tunnel_rule->hash_table) {
1023                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1024                 return -EINVAL;
1025         }
1026         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1027                                     sizeof(struct i40e_tunnel_filter *) *
1028                                     I40E_MAX_TUNNEL_FILTER_NUM,
1029                                     0);
1030         if (!tunnel_rule->hash_map) {
1031                 PMD_INIT_LOG(ERR,
1032                              "Failed to allocate memory for tunnel hash map!");
1033                 ret = -ENOMEM;
1034                 goto err_tunnel_hash_map_alloc;
1035         }
1036
1037         return 0;
1038
1039 err_tunnel_hash_map_alloc:
1040         rte_hash_free(tunnel_rule->hash_table);
1041
1042         return ret;
1043 }
1044
1045 static int
1046 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1050         struct i40e_fdir_info *fdir_info = &pf->fdir;
1051         char fdir_hash_name[RTE_HASH_NAMESIZE];
1052         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1053         uint32_t best = hw->func_caps.fd_filters_best_effort;
1054         struct rte_bitmap *bmp = NULL;
1055         uint32_t bmp_size;
1056         void *mem = NULL;
1057         uint32_t i = 0;
1058         int ret;
1059
1060         struct rte_hash_parameters fdir_hash_params = {
1061                 .name = fdir_hash_name,
1062                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1063                 .key_len = sizeof(struct i40e_fdir_input),
1064                 .hash_func = rte_hash_crc,
1065                 .hash_func_init_val = 0,
1066                 .socket_id = rte_socket_id(),
1067         };
1068
1069         /* Initialize flow director filter rule list and hash */
1070         TAILQ_INIT(&fdir_info->fdir_list);
1071         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1072                  "fdir_%s", dev->device->name);
1073         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1074         if (!fdir_info->hash_table) {
1075                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1076                 return -EINVAL;
1077         }
1078
1079         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1080                                           sizeof(struct i40e_fdir_filter *) *
1081                                           I40E_MAX_FDIR_FILTER_NUM,
1082                                           0);
1083         if (!fdir_info->hash_map) {
1084                 PMD_INIT_LOG(ERR,
1085                              "Failed to allocate memory for fdir hash map!");
1086                 ret = -ENOMEM;
1087                 goto err_fdir_hash_map_alloc;
1088         }
1089
1090         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1091                         sizeof(struct i40e_fdir_filter) *
1092                         I40E_MAX_FDIR_FILTER_NUM,
1093                         0);
1094
1095         if (!fdir_info->fdir_filter_array) {
1096                 PMD_INIT_LOG(ERR,
1097                              "Failed to allocate memory for fdir filter array!");
1098                 ret = -ENOMEM;
1099                 goto err_fdir_filter_array_alloc;
1100         }
1101
1102         fdir_info->fdir_space_size = alloc + best;
1103         fdir_info->fdir_actual_cnt = 0;
1104         fdir_info->fdir_guarantee_total_space = alloc;
1105         fdir_info->fdir_guarantee_free_space =
1106                 fdir_info->fdir_guarantee_total_space;
1107
1108         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1109
1110         fdir_info->fdir_flow_pool.pool =
1111                         rte_zmalloc("i40e_fdir_entry",
1112                                 sizeof(struct i40e_fdir_entry) *
1113                                 fdir_info->fdir_space_size,
1114                                 0);
1115
1116         if (!fdir_info->fdir_flow_pool.pool) {
1117                 PMD_INIT_LOG(ERR,
1118                              "Failed to allocate memory for bitmap flow!");
1119                 ret = -ENOMEM;
1120                 goto err_fdir_bitmap_flow_alloc;
1121         }
1122
1123         for (i = 0; i < fdir_info->fdir_space_size; i++)
1124                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1125
1126         bmp_size =
1127                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1128         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1129         if (mem == NULL) {
1130                 PMD_INIT_LOG(ERR,
1131                              "Failed to allocate memory for fdir bitmap!");
1132                 ret = -ENOMEM;
1133                 goto err_fdir_mem_alloc;
1134         }
1135         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1136         if (bmp == NULL) {
1137                 PMD_INIT_LOG(ERR,
1138                              "Failed to initialization fdir bitmap!");
1139                 ret = -ENOMEM;
1140                 goto err_fdir_bmp_alloc;
1141         }
1142         for (i = 0; i < fdir_info->fdir_space_size; i++)
1143                 rte_bitmap_set(bmp, i);
1144
1145         fdir_info->fdir_flow_pool.bitmap = bmp;
1146
1147         return 0;
1148
1149 err_fdir_bmp_alloc:
1150         rte_free(mem);
1151 err_fdir_mem_alloc:
1152         rte_free(fdir_info->fdir_flow_pool.pool);
1153 err_fdir_bitmap_flow_alloc:
1154         rte_free(fdir_info->fdir_filter_array);
1155 err_fdir_filter_array_alloc:
1156         rte_free(fdir_info->hash_map);
1157 err_fdir_hash_map_alloc:
1158         rte_hash_free(fdir_info->hash_table);
1159
1160         return ret;
1161 }
1162
1163 static void
1164 i40e_init_customized_info(struct i40e_pf *pf)
1165 {
1166         int i;
1167
1168         /* Initialize customized pctype */
1169         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1170                 pf->customized_pctype[i].index = i;
1171                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1172                 pf->customized_pctype[i].valid = false;
1173         }
1174
1175         pf->gtp_support = false;
1176         pf->esp_support = false;
1177 }
1178
1179 static void
1180 i40e_init_filter_invalidation(struct i40e_pf *pf)
1181 {
1182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1183         struct i40e_fdir_info *fdir_info = &pf->fdir;
1184         uint32_t glqf_ctl_reg = 0;
1185
1186         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1187         if (!pf->support_multi_driver) {
1188                 fdir_info->fdir_invalprio = 1;
1189                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1190                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1191                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1192         } else {
1193                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1194                         fdir_info->fdir_invalprio = 1;
1195                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1196                 } else {
1197                         fdir_info->fdir_invalprio = 0;
1198                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1199                 }
1200         }
1201 }
1202
1203 void
1204 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1205 {
1206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1208         struct i40e_queue_regions *info = &pf->queue_region;
1209         uint16_t i;
1210
1211         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1212                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1213
1214         memset(info, 0, sizeof(struct i40e_queue_regions));
1215 }
1216
1217 static int
1218 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1219                                const char *value,
1220                                void *opaque)
1221 {
1222         struct i40e_pf *pf;
1223         unsigned long support_multi_driver;
1224         char *end;
1225
1226         pf = (struct i40e_pf *)opaque;
1227
1228         errno = 0;
1229         support_multi_driver = strtoul(value, &end, 10);
1230         if (errno != 0 || end == value || *end != 0) {
1231                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1232                 return -(EINVAL);
1233         }
1234
1235         if (support_multi_driver == 1 || support_multi_driver == 0)
1236                 pf->support_multi_driver = (bool)support_multi_driver;
1237         else
1238                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1239                             "enable global configuration by default."
1240                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1241         return 0;
1242 }
1243
1244 static int
1245 i40e_support_multi_driver(struct rte_eth_dev *dev)
1246 {
1247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1248         struct rte_kvargs *kvlist;
1249         int kvargs_count;
1250
1251         /* Enable global configuration by default */
1252         pf->support_multi_driver = false;
1253
1254         if (!dev->device->devargs)
1255                 return 0;
1256
1257         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1258         if (!kvlist)
1259                 return -EINVAL;
1260
1261         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1262         if (!kvargs_count) {
1263                 rte_kvargs_free(kvlist);
1264                 return 0;
1265         }
1266
1267         if (kvargs_count > 1)
1268                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1269                             "the first invalid or last valid one is used !",
1270                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1271
1272         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1273                                i40e_parse_multi_drv_handler, pf) < 0) {
1274                 rte_kvargs_free(kvlist);
1275                 return -EINVAL;
1276         }
1277
1278         rte_kvargs_free(kvlist);
1279         return 0;
1280 }
1281
1282 static int
1283 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1284                                     uint32_t reg_addr, uint64_t reg_val,
1285                                     struct i40e_asq_cmd_details *cmd_details)
1286 {
1287         uint64_t ori_reg_val;
1288         struct rte_eth_dev *dev;
1289         int ret;
1290
1291         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1292         if (ret != I40E_SUCCESS) {
1293                 PMD_DRV_LOG(ERR,
1294                             "Fail to debug read from 0x%08x",
1295                             reg_addr);
1296                 return -EIO;
1297         }
1298         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1299
1300         if (ori_reg_val != reg_val)
1301                 PMD_DRV_LOG(WARNING,
1302                             "i40e device %s changed global register [0x%08x]."
1303                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1304                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1305
1306         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1307 }
1308
1309 static int
1310 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1311                                 const char *value,
1312                                 void *opaque)
1313 {
1314         struct i40e_adapter *ad = opaque;
1315         int use_latest_vec;
1316
1317         use_latest_vec = atoi(value);
1318
1319         if (use_latest_vec != 0 && use_latest_vec != 1)
1320                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1321
1322         ad->use_latest_vec = (uint8_t)use_latest_vec;
1323
1324         return 0;
1325 }
1326
1327 static int
1328 i40e_use_latest_vec(struct rte_eth_dev *dev)
1329 {
1330         struct i40e_adapter *ad =
1331                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1332         struct rte_kvargs *kvlist;
1333         int kvargs_count;
1334
1335         ad->use_latest_vec = false;
1336
1337         if (!dev->device->devargs)
1338                 return 0;
1339
1340         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1341         if (!kvlist)
1342                 return -EINVAL;
1343
1344         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1345         if (!kvargs_count) {
1346                 rte_kvargs_free(kvlist);
1347                 return 0;
1348         }
1349
1350         if (kvargs_count > 1)
1351                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1352                             "the first invalid or last valid one is used !",
1353                             ETH_I40E_USE_LATEST_VEC);
1354
1355         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1356                                 i40e_parse_latest_vec_handler, ad) < 0) {
1357                 rte_kvargs_free(kvlist);
1358                 return -EINVAL;
1359         }
1360
1361         rte_kvargs_free(kvlist);
1362         return 0;
1363 }
1364
1365 static int
1366 read_vf_msg_config(__rte_unused const char *key,
1367                                const char *value,
1368                                void *opaque)
1369 {
1370         struct i40e_vf_msg_cfg *cfg = opaque;
1371
1372         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1373                         &cfg->ignore_second) != 3) {
1374                 memset(cfg, 0, sizeof(*cfg));
1375                 PMD_DRV_LOG(ERR, "format error! example: "
1376                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1377                 return -EINVAL;
1378         }
1379
1380         /*
1381          * If the message validation function been enabled, the 'period'
1382          * and 'ignore_second' must greater than 0.
1383          */
1384         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1385                 memset(cfg, 0, sizeof(*cfg));
1386                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1387                                 " number must be greater than 0!",
1388                                 ETH_I40E_VF_MSG_CFG);
1389                 return -EINVAL;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int
1396 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1397                 struct i40e_vf_msg_cfg *msg_cfg)
1398 {
1399         struct rte_kvargs *kvlist;
1400         int kvargs_count;
1401         int ret = 0;
1402
1403         memset(msg_cfg, 0, sizeof(*msg_cfg));
1404
1405         if (!dev->device->devargs)
1406                 return ret;
1407
1408         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1409         if (!kvlist)
1410                 return -EINVAL;
1411
1412         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1413         if (!kvargs_count)
1414                 goto free_end;
1415
1416         if (kvargs_count > 1) {
1417                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1418                                 ETH_I40E_VF_MSG_CFG);
1419                 ret = -EINVAL;
1420                 goto free_end;
1421         }
1422
1423         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1424                         read_vf_msg_config, msg_cfg) < 0)
1425                 ret = -EINVAL;
1426
1427 free_end:
1428         rte_kvargs_free(kvlist);
1429         return ret;
1430 }
1431
1432 #define I40E_ALARM_INTERVAL 50000 /* us */
1433
1434 static int
1435 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1436 {
1437         struct rte_pci_device *pci_dev;
1438         struct rte_intr_handle *intr_handle;
1439         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441         struct i40e_vsi *vsi;
1442         int ret;
1443         uint32_t len, val;
1444         uint8_t aq_fail = 0;
1445
1446         PMD_INIT_FUNC_TRACE();
1447
1448         dev->dev_ops = &i40e_eth_dev_ops;
1449         dev->rx_pkt_burst = i40e_recv_pkts;
1450         dev->tx_pkt_burst = i40e_xmit_pkts;
1451         dev->tx_pkt_prepare = i40e_prep_pkts;
1452
1453         /* for secondary processes, we don't initialise any further as primary
1454          * has already done this work. Only check we don't need a different
1455          * RX function */
1456         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457                 i40e_set_rx_function(dev);
1458                 i40e_set_tx_function(dev);
1459                 return 0;
1460         }
1461         i40e_set_default_ptype_table(dev);
1462         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463         intr_handle = &pci_dev->intr_handle;
1464
1465         rte_eth_copy_pci_info(dev, pci_dev);
1466
1467         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468         pf->adapter->eth_dev = dev;
1469         pf->dev_data = dev->data;
1470
1471         hw->back = I40E_PF_TO_ADAPTER(pf);
1472         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1473         if (!hw->hw_addr) {
1474                 PMD_INIT_LOG(ERR,
1475                         "Hardware is not available, as address is NULL");
1476                 return -ENODEV;
1477         }
1478
1479         hw->vendor_id = pci_dev->id.vendor_id;
1480         hw->device_id = pci_dev->id.device_id;
1481         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1482         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1483         hw->bus.device = pci_dev->addr.devid;
1484         hw->bus.func = pci_dev->addr.function;
1485         hw->adapter_stopped = 0;
1486         hw->adapter_closed = 0;
1487
1488         /* Init switch device pointer */
1489         hw->switch_dev = NULL;
1490
1491         /*
1492          * Switch Tag value should not be identical to either the First Tag
1493          * or Second Tag values. So set something other than common Ethertype
1494          * for internal switching.
1495          */
1496         hw->switch_tag = 0xffff;
1497
1498         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1499         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1500                 PMD_INIT_LOG(ERR, "\nERROR: "
1501                         "Firmware recovery mode detected. Limiting functionality.\n"
1502                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1503                         "User Guide for details on firmware recovery mode.");
1504                 return -EIO;
1505         }
1506
1507         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1508         /* Check if need to support multi-driver */
1509         i40e_support_multi_driver(dev);
1510         /* Check if users want the latest supported vec path */
1511         i40e_use_latest_vec(dev);
1512
1513         /* Make sure all is clean before doing PF reset */
1514         i40e_clear_hw(hw);
1515
1516         /* Reset here to make sure all is clean for each PF */
1517         ret = i40e_pf_reset(hw);
1518         if (ret) {
1519                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1520                 return ret;
1521         }
1522
1523         /* Initialize the shared code (base driver) */
1524         ret = i40e_init_shared_code(hw);
1525         if (ret) {
1526                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1527                 return ret;
1528         }
1529
1530         /* Initialize the parameters for adminq */
1531         i40e_init_adminq_parameter(hw);
1532         ret = i40e_init_adminq(hw);
1533         if (ret != I40E_SUCCESS) {
1534                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1535                 return -EIO;
1536         }
1537         /* Firmware of SFP x722 does not support adminq option */
1538         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1539                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1540
1541         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1542                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1543                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1544                      ((hw->nvm.version >> 12) & 0xf),
1545                      ((hw->nvm.version >> 4) & 0xff),
1546                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1547
1548         /* Initialize the hardware */
1549         i40e_hw_init(dev);
1550
1551         i40e_config_automask(pf);
1552
1553         i40e_set_default_pctype_table(dev);
1554
1555         /*
1556          * To work around the NVM issue, initialize registers
1557          * for packet type of QinQ by software.
1558          * It should be removed once issues are fixed in NVM.
1559          */
1560         if (!pf->support_multi_driver)
1561                 i40e_GLQF_reg_init(hw);
1562
1563         /* Initialize the input set for filters (hash and fd) to default value */
1564         i40e_filter_input_set_init(pf);
1565
1566         /* initialise the L3_MAP register */
1567         if (!pf->support_multi_driver) {
1568                 ret = i40e_aq_debug_write_global_register(hw,
1569                                                    I40E_GLQF_L3_MAP(40),
1570                                                    0x00000028,  NULL);
1571                 if (ret)
1572                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1573                                      ret);
1574                 PMD_INIT_LOG(DEBUG,
1575                              "Global register 0x%08x is changed with 0x28",
1576                              I40E_GLQF_L3_MAP(40));
1577         }
1578
1579         /* Need the special FW version to support floating VEB */
1580         config_floating_veb(dev);
1581         /* Clear PXE mode */
1582         i40e_clear_pxe_mode(hw);
1583         i40e_dev_sync_phy_type(hw);
1584
1585         /*
1586          * On X710, performance number is far from the expectation on recent
1587          * firmware versions. The fix for this issue may not be integrated in
1588          * the following firmware version. So the workaround in software driver
1589          * is needed. It needs to modify the initial values of 3 internal only
1590          * registers. Note that the workaround can be removed when it is fixed
1591          * in firmware in the future.
1592          */
1593         i40e_configure_registers(hw);
1594
1595         /* Get hw capabilities */
1596         ret = i40e_get_cap(hw);
1597         if (ret != I40E_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1599                 goto err_get_capabilities;
1600         }
1601
1602         /* Initialize parameters for PF */
1603         ret = i40e_pf_parameter_init(dev);
1604         if (ret != 0) {
1605                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1606                 goto err_parameter_init;
1607         }
1608
1609         /* Initialize the queue management */
1610         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1611         if (ret < 0) {
1612                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1613                 goto err_qp_pool_init;
1614         }
1615         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1616                                 hw->func_caps.num_msix_vectors - 1);
1617         if (ret < 0) {
1618                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1619                 goto err_msix_pool_init;
1620         }
1621
1622         /* Initialize lan hmc */
1623         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1624                                 hw->func_caps.num_rx_qp, 0, 0);
1625         if (ret != I40E_SUCCESS) {
1626                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1627                 goto err_init_lan_hmc;
1628         }
1629
1630         /* Configure lan hmc */
1631         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1632         if (ret != I40E_SUCCESS) {
1633                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1634                 goto err_configure_lan_hmc;
1635         }
1636
1637         /* Get and check the mac address */
1638         i40e_get_mac_addr(hw, hw->mac.addr);
1639         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1640                 PMD_INIT_LOG(ERR, "mac address is not valid");
1641                 ret = -EIO;
1642                 goto err_get_mac_addr;
1643         }
1644         /* Copy the permanent MAC address */
1645         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1646                         (struct rte_ether_addr *)hw->mac.perm_addr);
1647
1648         /* Disable flow control */
1649         hw->fc.requested_mode = I40E_FC_NONE;
1650         i40e_set_fc(hw, &aq_fail, TRUE);
1651
1652         /* Set the global registers with default ether type value */
1653         if (!pf->support_multi_driver) {
1654                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1655                                          RTE_ETHER_TYPE_VLAN);
1656                 if (ret != I40E_SUCCESS) {
1657                         PMD_INIT_LOG(ERR,
1658                                      "Failed to set the default outer "
1659                                      "VLAN ether type");
1660                         goto err_setup_pf_switch;
1661                 }
1662         }
1663
1664         /* PF setup, which includes VSI setup */
1665         ret = i40e_pf_setup(pf);
1666         if (ret) {
1667                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1668                 goto err_setup_pf_switch;
1669         }
1670
1671         vsi = pf->main_vsi;
1672
1673         /* Disable double vlan by default */
1674         i40e_vsi_config_double_vlan(vsi, FALSE);
1675
1676         /* Disable S-TAG identification when floating_veb is disabled */
1677         if (!pf->floating_veb) {
1678                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1679                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1680                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1681                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1682                 }
1683         }
1684
1685         if (!vsi->max_macaddrs)
1686                 len = RTE_ETHER_ADDR_LEN;
1687         else
1688                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1689
1690         /* Should be after VSI initialized */
1691         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1692         if (!dev->data->mac_addrs) {
1693                 PMD_INIT_LOG(ERR,
1694                         "Failed to allocated memory for storing mac address");
1695                 goto err_mac_alloc;
1696         }
1697         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1698                                         &dev->data->mac_addrs[0]);
1699
1700         /* Pass the information to the rte_eth_dev_close() that it should also
1701          * release the private port resources.
1702          */
1703         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1704
1705         /* Init dcb to sw mode by default */
1706         ret = i40e_dcb_init_configure(dev, TRUE);
1707         if (ret != I40E_SUCCESS) {
1708                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1709                 pf->flags &= ~I40E_FLAG_DCB;
1710         }
1711         /* Update HW struct after DCB configuration */
1712         i40e_get_cap(hw);
1713
1714         /* initialize pf host driver to setup SRIOV resource if applicable */
1715         i40e_pf_host_init(dev);
1716
1717         /* register callback func to eal lib */
1718         rte_intr_callback_register(intr_handle,
1719                                    i40e_dev_interrupt_handler, dev);
1720
1721         /* configure and enable device interrupt */
1722         i40e_pf_config_irq0(hw, TRUE);
1723         i40e_pf_enable_irq0(hw);
1724
1725         /* enable uio intr after callback register */
1726         rte_intr_enable(intr_handle);
1727
1728         /* By default disable flexible payload in global configuration */
1729         if (!pf->support_multi_driver)
1730                 i40e_flex_payload_reg_set_default(hw);
1731
1732         /*
1733          * Add an ethertype filter to drop all flow control frames transmitted
1734          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1735          * frames to wire.
1736          */
1737         i40e_add_tx_flow_control_drop_filter(pf);
1738
1739         /* Set the max frame size to 0x2600 by default,
1740          * in case other drivers changed the default value.
1741          */
1742         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1743
1744         /* initialize mirror rule list */
1745         TAILQ_INIT(&pf->mirror_list);
1746
1747         /* initialize RSS rule list */
1748         TAILQ_INIT(&pf->rss_config_list);
1749
1750         /* initialize Traffic Manager configuration */
1751         i40e_tm_conf_init(dev);
1752
1753         /* Initialize customized information */
1754         i40e_init_customized_info(pf);
1755
1756         /* Initialize the filter invalidation configuration */
1757         i40e_init_filter_invalidation(pf);
1758
1759         ret = i40e_init_ethtype_filter_list(dev);
1760         if (ret < 0)
1761                 goto err_init_ethtype_filter_list;
1762         ret = i40e_init_tunnel_filter_list(dev);
1763         if (ret < 0)
1764                 goto err_init_tunnel_filter_list;
1765         ret = i40e_init_fdir_filter_list(dev);
1766         if (ret < 0)
1767                 goto err_init_fdir_filter_list;
1768
1769         /* initialize queue region configuration */
1770         i40e_init_queue_region_conf(dev);
1771
1772         /* initialize RSS configuration from rte_flow */
1773         memset(&pf->rss_info, 0,
1774                 sizeof(struct i40e_rte_flow_rss_conf));
1775
1776         /* reset all stats of the device, including pf and main vsi */
1777         i40e_dev_stats_reset(dev);
1778
1779         return 0;
1780
1781 err_init_fdir_filter_list:
1782         rte_free(pf->tunnel.hash_table);
1783         rte_free(pf->tunnel.hash_map);
1784 err_init_tunnel_filter_list:
1785         rte_free(pf->ethertype.hash_table);
1786         rte_free(pf->ethertype.hash_map);
1787 err_init_ethtype_filter_list:
1788         rte_free(dev->data->mac_addrs);
1789         dev->data->mac_addrs = NULL;
1790 err_mac_alloc:
1791         i40e_vsi_release(pf->main_vsi);
1792 err_setup_pf_switch:
1793 err_get_mac_addr:
1794 err_configure_lan_hmc:
1795         (void)i40e_shutdown_lan_hmc(hw);
1796 err_init_lan_hmc:
1797         i40e_res_pool_destroy(&pf->msix_pool);
1798 err_msix_pool_init:
1799         i40e_res_pool_destroy(&pf->qp_pool);
1800 err_qp_pool_init:
1801 err_parameter_init:
1802 err_get_capabilities:
1803         (void)i40e_shutdown_adminq(hw);
1804
1805         return ret;
1806 }
1807
1808 static void
1809 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1810 {
1811         struct i40e_ethertype_filter *p_ethertype;
1812         struct i40e_ethertype_rule *ethertype_rule;
1813
1814         ethertype_rule = &pf->ethertype;
1815         /* Remove all ethertype filter rules and hash */
1816         if (ethertype_rule->hash_map)
1817                 rte_free(ethertype_rule->hash_map);
1818         if (ethertype_rule->hash_table)
1819                 rte_hash_free(ethertype_rule->hash_table);
1820
1821         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1822                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1823                              p_ethertype, rules);
1824                 rte_free(p_ethertype);
1825         }
1826 }
1827
1828 static void
1829 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1830 {
1831         struct i40e_tunnel_filter *p_tunnel;
1832         struct i40e_tunnel_rule *tunnel_rule;
1833
1834         tunnel_rule = &pf->tunnel;
1835         /* Remove all tunnel director rules and hash */
1836         if (tunnel_rule->hash_map)
1837                 rte_free(tunnel_rule->hash_map);
1838         if (tunnel_rule->hash_table)
1839                 rte_hash_free(tunnel_rule->hash_table);
1840
1841         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1842                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1843                 rte_free(p_tunnel);
1844         }
1845 }
1846
1847 static void
1848 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1849 {
1850         struct i40e_fdir_filter *p_fdir;
1851         struct i40e_fdir_info *fdir_info;
1852
1853         fdir_info = &pf->fdir;
1854
1855         /* Remove all flow director rules */
1856         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1857                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1858 }
1859
1860 static void
1861 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1862 {
1863         struct i40e_fdir_info *fdir_info;
1864
1865         fdir_info = &pf->fdir;
1866
1867         /* flow director memory cleanup */
1868         if (fdir_info->hash_map)
1869                 rte_free(fdir_info->hash_map);
1870         if (fdir_info->hash_table)
1871                 rte_hash_free(fdir_info->hash_table);
1872         if (fdir_info->fdir_flow_pool.bitmap)
1873                 rte_bitmap_free(fdir_info->fdir_flow_pool.bitmap);
1874         if (fdir_info->fdir_flow_pool.pool)
1875                 rte_free(fdir_info->fdir_flow_pool.pool);
1876         if (fdir_info->fdir_filter_array)
1877                 rte_free(fdir_info->fdir_filter_array);
1878 }
1879
1880 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1881 {
1882         /*
1883          * Disable by default flexible payload
1884          * for corresponding L2/L3/L4 layers.
1885          */
1886         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1887         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1888         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1889 }
1890
1891 static int
1892 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1893 {
1894         struct i40e_hw *hw;
1895
1896         PMD_INIT_FUNC_TRACE();
1897
1898         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1899                 return 0;
1900
1901         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902
1903         if (hw->adapter_closed == 0)
1904                 i40e_dev_close(dev);
1905
1906         return 0;
1907 }
1908
1909 static int
1910 i40e_dev_configure(struct rte_eth_dev *dev)
1911 {
1912         struct i40e_adapter *ad =
1913                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1917         int i, ret;
1918
1919         ret = i40e_dev_sync_phy_type(hw);
1920         if (ret)
1921                 return ret;
1922
1923         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1924          * bulk allocation or vector Rx preconditions we will reset it.
1925          */
1926         ad->rx_bulk_alloc_allowed = true;
1927         ad->rx_vec_allowed = true;
1928         ad->tx_simple_allowed = true;
1929         ad->tx_vec_allowed = true;
1930
1931         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1932                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1933
1934         /* Only legacy filter API needs the following fdir config. So when the
1935          * legacy filter API is deprecated, the following codes should also be
1936          * removed.
1937          */
1938         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1939                 ret = i40e_fdir_setup(pf);
1940                 if (ret != I40E_SUCCESS) {
1941                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1942                         return -ENOTSUP;
1943                 }
1944                 ret = i40e_fdir_configure(dev);
1945                 if (ret < 0) {
1946                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1947                         goto err;
1948                 }
1949         } else
1950                 i40e_fdir_teardown(pf);
1951
1952         ret = i40e_dev_init_vlan(dev);
1953         if (ret < 0)
1954                 goto err;
1955
1956         /* VMDQ setup.
1957          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1958          *  RSS setting have different requirements.
1959          *  General PMD driver call sequence are NIC init, configure,
1960          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1961          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1962          *  applicable. So, VMDQ setting has to be done before
1963          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1964          *  For RSS setting, it will try to calculate actual configured RX queue
1965          *  number, which will be available after rx_queue_setup(). dev_start()
1966          *  function is good to place RSS setup.
1967          */
1968         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1969                 ret = i40e_vmdq_setup(dev);
1970                 if (ret)
1971                         goto err;
1972         }
1973
1974         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1975                 ret = i40e_dcb_setup(dev);
1976                 if (ret) {
1977                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1978                         goto err_dcb;
1979                 }
1980         }
1981
1982         TAILQ_INIT(&pf->flow_list);
1983
1984         return 0;
1985
1986 err_dcb:
1987         /* need to release vmdq resource if exists */
1988         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989                 i40e_vsi_release(pf->vmdq[i].vsi);
1990                 pf->vmdq[i].vsi = NULL;
1991         }
1992         rte_free(pf->vmdq);
1993         pf->vmdq = NULL;
1994 err:
1995         /* Need to release fdir resource if exists.
1996          * Only legacy filter API needs the following fdir config. So when the
1997          * legacy filter API is deprecated, the following code should also be
1998          * removed.
1999          */
2000         i40e_fdir_teardown(pf);
2001         return ret;
2002 }
2003
2004 void
2005 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2006 {
2007         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011         uint16_t msix_vect = vsi->msix_intr;
2012         uint16_t i;
2013
2014         for (i = 0; i < vsi->nb_qps; i++) {
2015                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2017                 rte_wmb();
2018         }
2019
2020         if (vsi->type != I40E_VSI_SRIOV) {
2021                 if (!rte_intr_allow_others(intr_handle)) {
2022                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2023                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2024                         I40E_WRITE_REG(hw,
2025                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2026                                        0);
2027                 } else {
2028                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2029                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2030                         I40E_WRITE_REG(hw,
2031                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2032                                                        msix_vect - 1), 0);
2033                 }
2034         } else {
2035                 uint32_t reg;
2036                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2037                         vsi->user_param + (msix_vect - 1);
2038
2039                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2040                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2041         }
2042         I40E_WRITE_FLUSH(hw);
2043 }
2044
2045 static void
2046 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2047                        int base_queue, int nb_queue,
2048                        uint16_t itr_idx)
2049 {
2050         int i;
2051         uint32_t val;
2052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2054
2055         /* Bind all RX queues to allocated MSIX interrupt */
2056         for (i = 0; i < nb_queue; i++) {
2057                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2058                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2059                         ((base_queue + i + 1) <<
2060                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2061                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2062                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2063
2064                 if (i == nb_queue - 1)
2065                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2066                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2067         }
2068
2069         /* Write first RX queue to Link list register as the head element */
2070         if (vsi->type != I40E_VSI_SRIOV) {
2071                 uint16_t interval =
2072                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2073
2074                 if (msix_vect == I40E_MISC_VEC_ID) {
2075                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2076                                        (base_queue <<
2077                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2078                                        (0x0 <<
2079                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2080                         I40E_WRITE_REG(hw,
2081                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2082                                        interval);
2083                 } else {
2084                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2085                                        (base_queue <<
2086                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2087                                        (0x0 <<
2088                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2089                         I40E_WRITE_REG(hw,
2090                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2091                                                        msix_vect - 1),
2092                                        interval);
2093                 }
2094         } else {
2095                 uint32_t reg;
2096
2097                 if (msix_vect == I40E_MISC_VEC_ID) {
2098                         I40E_WRITE_REG(hw,
2099                                        I40E_VPINT_LNKLST0(vsi->user_param),
2100                                        (base_queue <<
2101                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2102                                        (0x0 <<
2103                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2104                 } else {
2105                         /* num_msix_vectors_vf needs to minus irq0 */
2106                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2107                                 vsi->user_param + (msix_vect - 1);
2108
2109                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2110                                        (base_queue <<
2111                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2112                                        (0x0 <<
2113                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2114                 }
2115         }
2116
2117         I40E_WRITE_FLUSH(hw);
2118 }
2119
2120 void
2121 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2122 {
2123         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2124         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2125         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2126         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2127         uint16_t msix_vect = vsi->msix_intr;
2128         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2129         uint16_t queue_idx = 0;
2130         int record = 0;
2131         int i;
2132
2133         for (i = 0; i < vsi->nb_qps; i++) {
2134                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2135                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2136         }
2137
2138         /* VF bind interrupt */
2139         if (vsi->type == I40E_VSI_SRIOV) {
2140                 __vsi_queues_bind_intr(vsi, msix_vect,
2141                                        vsi->base_queue, vsi->nb_qps,
2142                                        itr_idx);
2143                 return;
2144         }
2145
2146         /* PF & VMDq bind interrupt */
2147         if (rte_intr_dp_is_en(intr_handle)) {
2148                 if (vsi->type == I40E_VSI_MAIN) {
2149                         queue_idx = 0;
2150                         record = 1;
2151                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2152                         struct i40e_vsi *main_vsi =
2153                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2154                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2155                         record = 1;
2156                 }
2157         }
2158
2159         for (i = 0; i < vsi->nb_used_qps; i++) {
2160                 if (nb_msix <= 1) {
2161                         if (!rte_intr_allow_others(intr_handle))
2162                                 /* allow to share MISC_VEC_ID */
2163                                 msix_vect = I40E_MISC_VEC_ID;
2164
2165                         /* no enough msix_vect, map all to one */
2166                         __vsi_queues_bind_intr(vsi, msix_vect,
2167                                                vsi->base_queue + i,
2168                                                vsi->nb_used_qps - i,
2169                                                itr_idx);
2170                         for (; !!record && i < vsi->nb_used_qps; i++)
2171                                 intr_handle->intr_vec[queue_idx + i] =
2172                                         msix_vect;
2173                         break;
2174                 }
2175                 /* 1:1 queue/msix_vect mapping */
2176                 __vsi_queues_bind_intr(vsi, msix_vect,
2177                                        vsi->base_queue + i, 1,
2178                                        itr_idx);
2179                 if (!!record)
2180                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2181
2182                 msix_vect++;
2183                 nb_msix--;
2184         }
2185 }
2186
2187 void
2188 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2189 {
2190         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2191         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2192         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2193         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2194         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2195         uint16_t msix_intr, i;
2196
2197         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2198                 for (i = 0; i < vsi->nb_msix; i++) {
2199                         msix_intr = vsi->msix_intr + i;
2200                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2201                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2202                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2203                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2204                 }
2205         else
2206                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2207                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2208                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2209                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2210
2211         I40E_WRITE_FLUSH(hw);
2212 }
2213
2214 void
2215 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2216 {
2217         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2218         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2219         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2220         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2221         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2222         uint16_t msix_intr, i;
2223
2224         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2225                 for (i = 0; i < vsi->nb_msix; i++) {
2226                         msix_intr = vsi->msix_intr + i;
2227                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2228                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2229                 }
2230         else
2231                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2232                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2233
2234         I40E_WRITE_FLUSH(hw);
2235 }
2236
2237 static inline uint8_t
2238 i40e_parse_link_speeds(uint16_t link_speeds)
2239 {
2240         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2241
2242         if (link_speeds & ETH_LINK_SPEED_40G)
2243                 link_speed |= I40E_LINK_SPEED_40GB;
2244         if (link_speeds & ETH_LINK_SPEED_25G)
2245                 link_speed |= I40E_LINK_SPEED_25GB;
2246         if (link_speeds & ETH_LINK_SPEED_20G)
2247                 link_speed |= I40E_LINK_SPEED_20GB;
2248         if (link_speeds & ETH_LINK_SPEED_10G)
2249                 link_speed |= I40E_LINK_SPEED_10GB;
2250         if (link_speeds & ETH_LINK_SPEED_1G)
2251                 link_speed |= I40E_LINK_SPEED_1GB;
2252         if (link_speeds & ETH_LINK_SPEED_100M)
2253                 link_speed |= I40E_LINK_SPEED_100MB;
2254
2255         return link_speed;
2256 }
2257
2258 static int
2259 i40e_phy_conf_link(struct i40e_hw *hw,
2260                    uint8_t abilities,
2261                    uint8_t force_speed,
2262                    bool is_up)
2263 {
2264         enum i40e_status_code status;
2265         struct i40e_aq_get_phy_abilities_resp phy_ab;
2266         struct i40e_aq_set_phy_config phy_conf;
2267         enum i40e_aq_phy_type cnt;
2268         uint8_t avail_speed;
2269         uint32_t phy_type_mask = 0;
2270
2271         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2272                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2273                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2274                         I40E_AQ_PHY_FLAG_LOW_POWER;
2275         int ret = -ENOTSUP;
2276
2277         /* To get phy capabilities of available speeds. */
2278         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2279                                               NULL);
2280         if (status) {
2281                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2282                                 status);
2283                 return ret;
2284         }
2285         avail_speed = phy_ab.link_speed;
2286
2287         /* To get the current phy config. */
2288         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2289                                               NULL);
2290         if (status) {
2291                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2292                                 status);
2293                 return ret;
2294         }
2295
2296         /* If link needs to go up and it is in autoneg mode the speed is OK,
2297          * no need to set up again.
2298          */
2299         if (is_up && phy_ab.phy_type != 0 &&
2300                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2301                      phy_ab.link_speed != 0)
2302                 return I40E_SUCCESS;
2303
2304         memset(&phy_conf, 0, sizeof(phy_conf));
2305
2306         /* bits 0-2 use the values from get_phy_abilities_resp */
2307         abilities &= ~mask;
2308         abilities |= phy_ab.abilities & mask;
2309
2310         phy_conf.abilities = abilities;
2311
2312         /* If link needs to go up, but the force speed is not supported,
2313          * Warn users and config the default available speeds.
2314          */
2315         if (is_up && !(force_speed & avail_speed)) {
2316                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2317                 phy_conf.link_speed = avail_speed;
2318         } else {
2319                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2320         }
2321
2322         /* PHY type mask needs to include each type except PHY type extension */
2323         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2324                 phy_type_mask |= 1 << cnt;
2325
2326         /* use get_phy_abilities_resp value for the rest */
2327         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2328         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2329                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2330                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2331         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2332         phy_conf.eee_capability = phy_ab.eee_capability;
2333         phy_conf.eeer = phy_ab.eeer_val;
2334         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2335
2336         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2337                     phy_ab.abilities, phy_ab.link_speed);
2338         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2339                     phy_conf.abilities, phy_conf.link_speed);
2340
2341         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2342         if (status)
2343                 return ret;
2344
2345         return I40E_SUCCESS;
2346 }
2347
2348 static int
2349 i40e_apply_link_speed(struct rte_eth_dev *dev)
2350 {
2351         uint8_t speed;
2352         uint8_t abilities = 0;
2353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2354         struct rte_eth_conf *conf = &dev->data->dev_conf;
2355
2356         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2357                      I40E_AQ_PHY_LINK_ENABLED;
2358
2359         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2360                 conf->link_speeds = ETH_LINK_SPEED_40G |
2361                                     ETH_LINK_SPEED_25G |
2362                                     ETH_LINK_SPEED_20G |
2363                                     ETH_LINK_SPEED_10G |
2364                                     ETH_LINK_SPEED_1G |
2365                                     ETH_LINK_SPEED_100M;
2366
2367                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2368         } else {
2369                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2370         }
2371         speed = i40e_parse_link_speeds(conf->link_speeds);
2372
2373         return i40e_phy_conf_link(hw, abilities, speed, true);
2374 }
2375
2376 static int
2377 i40e_dev_start(struct rte_eth_dev *dev)
2378 {
2379         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2381         struct i40e_vsi *main_vsi = pf->main_vsi;
2382         int ret, i;
2383         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2384         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2385         uint32_t intr_vector = 0;
2386         struct i40e_vsi *vsi;
2387         uint16_t nb_rxq, nb_txq;
2388
2389         hw->adapter_stopped = 0;
2390
2391         rte_intr_disable(intr_handle);
2392
2393         if ((rte_intr_cap_multiple(intr_handle) ||
2394              !RTE_ETH_DEV_SRIOV(dev).active) &&
2395             dev->data->dev_conf.intr_conf.rxq != 0) {
2396                 intr_vector = dev->data->nb_rx_queues;
2397                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2398                 if (ret)
2399                         return ret;
2400         }
2401
2402         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2403                 intr_handle->intr_vec =
2404                         rte_zmalloc("intr_vec",
2405                                     dev->data->nb_rx_queues * sizeof(int),
2406                                     0);
2407                 if (!intr_handle->intr_vec) {
2408                         PMD_INIT_LOG(ERR,
2409                                 "Failed to allocate %d rx_queues intr_vec",
2410                                 dev->data->nb_rx_queues);
2411                         return -ENOMEM;
2412                 }
2413         }
2414
2415         /* Initialize VSI */
2416         ret = i40e_dev_rxtx_init(pf);
2417         if (ret != I40E_SUCCESS) {
2418                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2419                 return ret;
2420         }
2421
2422         /* Map queues with MSIX interrupt */
2423         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2424                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2425         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2426         i40e_vsi_enable_queues_intr(main_vsi);
2427
2428         /* Map VMDQ VSI queues with MSIX interrupt */
2429         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2430                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2431                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2432                                           I40E_ITR_INDEX_DEFAULT);
2433                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2434         }
2435
2436         /* Enable all queues which have been configured */
2437         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2438                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2439                 if (ret)
2440                         goto rx_err;
2441         }
2442
2443         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2444                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2445                 if (ret)
2446                         goto tx_err;
2447         }
2448
2449         /* Enable receiving broadcast packets */
2450         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2451         if (ret != I40E_SUCCESS)
2452                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2453
2454         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2455                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2456                                                 true, NULL);
2457                 if (ret != I40E_SUCCESS)
2458                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2459         }
2460
2461         /* Enable the VLAN promiscuous mode. */
2462         if (pf->vfs) {
2463                 for (i = 0; i < pf->vf_num; i++) {
2464                         vsi = pf->vfs[i].vsi;
2465                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2466                                                      true, NULL);
2467                 }
2468         }
2469
2470         /* Enable mac loopback mode */
2471         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2472             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2473                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2474                 if (ret != I40E_SUCCESS) {
2475                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2476                         goto tx_err;
2477                 }
2478         }
2479
2480         /* Apply link configure */
2481         ret = i40e_apply_link_speed(dev);
2482         if (I40E_SUCCESS != ret) {
2483                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2484                 goto tx_err;
2485         }
2486
2487         if (!rte_intr_allow_others(intr_handle)) {
2488                 rte_intr_callback_unregister(intr_handle,
2489                                              i40e_dev_interrupt_handler,
2490                                              (void *)dev);
2491                 /* configure and enable device interrupt */
2492                 i40e_pf_config_irq0(hw, FALSE);
2493                 i40e_pf_enable_irq0(hw);
2494
2495                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2496                         PMD_INIT_LOG(INFO,
2497                                 "lsc won't enable because of no intr multiplex");
2498         } else {
2499                 ret = i40e_aq_set_phy_int_mask(hw,
2500                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2501                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2502                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2503                 if (ret != I40E_SUCCESS)
2504                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2505
2506                 /* Call get_link_info aq commond to enable/disable LSE */
2507                 i40e_dev_link_update(dev, 0);
2508         }
2509
2510         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2511                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2512                                   i40e_dev_alarm_handler, dev);
2513         } else {
2514                 /* enable uio intr after callback register */
2515                 rte_intr_enable(intr_handle);
2516         }
2517
2518         i40e_filter_restore(pf);
2519
2520         if (pf->tm_conf.root && !pf->tm_conf.committed)
2521                 PMD_DRV_LOG(WARNING,
2522                             "please call hierarchy_commit() "
2523                             "before starting the port");
2524
2525         return I40E_SUCCESS;
2526
2527 tx_err:
2528         for (i = 0; i < nb_txq; i++)
2529                 i40e_dev_tx_queue_stop(dev, i);
2530 rx_err:
2531         for (i = 0; i < nb_rxq; i++)
2532                 i40e_dev_rx_queue_stop(dev, i);
2533
2534         return ret;
2535 }
2536
2537 static void
2538 i40e_dev_stop(struct rte_eth_dev *dev)
2539 {
2540         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2542         struct i40e_vsi *main_vsi = pf->main_vsi;
2543         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2544         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2545         int i;
2546
2547         if (hw->adapter_stopped == 1)
2548                 return;
2549
2550         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2551                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2552                 rte_intr_enable(intr_handle);
2553         }
2554
2555         /* Disable all queues */
2556         for (i = 0; i < dev->data->nb_tx_queues; i++)
2557                 i40e_dev_tx_queue_stop(dev, i);
2558
2559         for (i = 0; i < dev->data->nb_rx_queues; i++)
2560                 i40e_dev_rx_queue_stop(dev, i);
2561
2562         /* un-map queues with interrupt registers */
2563         i40e_vsi_disable_queues_intr(main_vsi);
2564         i40e_vsi_queues_unbind_intr(main_vsi);
2565
2566         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2567                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2568                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2569         }
2570
2571         /* Clear all queues and release memory */
2572         i40e_dev_clear_queues(dev);
2573
2574         /* Set link down */
2575         i40e_dev_set_link_down(dev);
2576
2577         if (!rte_intr_allow_others(intr_handle))
2578                 /* resume to the default handler */
2579                 rte_intr_callback_register(intr_handle,
2580                                            i40e_dev_interrupt_handler,
2581                                            (void *)dev);
2582
2583         /* Clean datapath event and queue/vec mapping */
2584         rte_intr_efd_disable(intr_handle);
2585         if (intr_handle->intr_vec) {
2586                 rte_free(intr_handle->intr_vec);
2587                 intr_handle->intr_vec = NULL;
2588         }
2589
2590         /* reset hierarchy commit */
2591         pf->tm_conf.committed = false;
2592
2593         hw->adapter_stopped = 1;
2594
2595         pf->adapter->rss_reta_updated = 0;
2596 }
2597
2598 static void
2599 i40e_dev_close(struct rte_eth_dev *dev)
2600 {
2601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2602         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2603         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2604         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2605         struct i40e_mirror_rule *p_mirror;
2606         struct i40e_filter_control_settings settings;
2607         struct rte_flow *p_flow;
2608         uint32_t reg;
2609         int i;
2610         int ret;
2611         uint8_t aq_fail = 0;
2612         int retries = 0;
2613
2614         PMD_INIT_FUNC_TRACE();
2615
2616         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2617         if (ret)
2618                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2619
2620
2621         i40e_dev_stop(dev);
2622
2623         /* Remove all mirror rules */
2624         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2625                 ret = i40e_aq_del_mirror_rule(hw,
2626                                               pf->main_vsi->veb->seid,
2627                                               p_mirror->rule_type,
2628                                               p_mirror->entries,
2629                                               p_mirror->num_entries,
2630                                               p_mirror->id);
2631                 if (ret < 0)
2632                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2633                                     "status = %d, aq_err = %d.", ret,
2634                                     hw->aq.asq_last_status);
2635
2636                 /* remove mirror software resource anyway */
2637                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2638                 rte_free(p_mirror);
2639                 pf->nb_mirror_rule--;
2640         }
2641
2642         i40e_dev_free_queues(dev);
2643
2644         /* Disable interrupt */
2645         i40e_pf_disable_irq0(hw);
2646         rte_intr_disable(intr_handle);
2647
2648         /*
2649          * Only legacy filter API needs the following fdir config. So when the
2650          * legacy filter API is deprecated, the following code should also be
2651          * removed.
2652          */
2653         i40e_fdir_teardown(pf);
2654
2655         /* shutdown and destroy the HMC */
2656         i40e_shutdown_lan_hmc(hw);
2657
2658         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2659                 i40e_vsi_release(pf->vmdq[i].vsi);
2660                 pf->vmdq[i].vsi = NULL;
2661         }
2662         rte_free(pf->vmdq);
2663         pf->vmdq = NULL;
2664
2665         /* release all the existing VSIs and VEBs */
2666         i40e_vsi_release(pf->main_vsi);
2667
2668         /* shutdown the adminq */
2669         i40e_aq_queue_shutdown(hw, true);
2670         i40e_shutdown_adminq(hw);
2671
2672         i40e_res_pool_destroy(&pf->qp_pool);
2673         i40e_res_pool_destroy(&pf->msix_pool);
2674
2675         /* Disable flexible payload in global configuration */
2676         if (!pf->support_multi_driver)
2677                 i40e_flex_payload_reg_set_default(hw);
2678
2679         /* force a PF reset to clean anything leftover */
2680         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2681         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2682                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2683         I40E_WRITE_FLUSH(hw);
2684
2685         dev->dev_ops = NULL;
2686         dev->rx_pkt_burst = NULL;
2687         dev->tx_pkt_burst = NULL;
2688
2689         /* Clear PXE mode */
2690         i40e_clear_pxe_mode(hw);
2691
2692         /* Unconfigure filter control */
2693         memset(&settings, 0, sizeof(settings));
2694         ret = i40e_set_filter_control(hw, &settings);
2695         if (ret)
2696                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2697                                         ret);
2698
2699         /* Disable flow control */
2700         hw->fc.requested_mode = I40E_FC_NONE;
2701         i40e_set_fc(hw, &aq_fail, TRUE);
2702
2703         /* uninitialize pf host driver */
2704         i40e_pf_host_uninit(dev);
2705
2706         do {
2707                 ret = rte_intr_callback_unregister(intr_handle,
2708                                 i40e_dev_interrupt_handler, dev);
2709                 if (ret >= 0 || ret == -ENOENT) {
2710                         break;
2711                 } else if (ret != -EAGAIN) {
2712                         PMD_INIT_LOG(ERR,
2713                                  "intr callback unregister failed: %d",
2714                                  ret);
2715                 }
2716                 i40e_msec_delay(500);
2717         } while (retries++ < 5);
2718
2719         i40e_rm_ethtype_filter_list(pf);
2720         i40e_rm_tunnel_filter_list(pf);
2721         i40e_rm_fdir_filter_list(pf);
2722
2723         /* Remove all flows */
2724         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2725                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2726                 /* Do not free FDIR flows since they are static allocated */
2727                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2728                         rte_free(p_flow);
2729         }
2730
2731         /* release the fdir static allocated memory */
2732         i40e_fdir_memory_cleanup(pf);
2733
2734         /* Remove all Traffic Manager configuration */
2735         i40e_tm_conf_uninit(dev);
2736
2737         hw->adapter_closed = 1;
2738 }
2739
2740 /*
2741  * Reset PF device only to re-initialize resources in PMD layer
2742  */
2743 static int
2744 i40e_dev_reset(struct rte_eth_dev *dev)
2745 {
2746         int ret;
2747
2748         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2749          * its VF to make them align with it. The detailed notification
2750          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2751          * To avoid unexpected behavior in VF, currently reset of PF with
2752          * SR-IOV activation is not supported. It might be supported later.
2753          */
2754         if (dev->data->sriov.active)
2755                 return -ENOTSUP;
2756
2757         ret = eth_i40e_dev_uninit(dev);
2758         if (ret)
2759                 return ret;
2760
2761         ret = eth_i40e_dev_init(dev, NULL);
2762
2763         return ret;
2764 }
2765
2766 static int
2767 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2768 {
2769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771         struct i40e_vsi *vsi = pf->main_vsi;
2772         int status;
2773
2774         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2775                                                      true, NULL, true);
2776         if (status != I40E_SUCCESS) {
2777                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2778                 return -EAGAIN;
2779         }
2780
2781         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2782                                                         TRUE, NULL);
2783         if (status != I40E_SUCCESS) {
2784                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2785                 /* Rollback unicast promiscuous mode */
2786                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2787                                                     false, NULL, true);
2788                 return -EAGAIN;
2789         }
2790
2791         return 0;
2792 }
2793
2794 static int
2795 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2796 {
2797         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2799         struct i40e_vsi *vsi = pf->main_vsi;
2800         int status;
2801
2802         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2803                                                      false, NULL, true);
2804         if (status != I40E_SUCCESS) {
2805                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2806                 return -EAGAIN;
2807         }
2808
2809         /* must remain in all_multicast mode */
2810         if (dev->data->all_multicast == 1)
2811                 return 0;
2812
2813         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2814                                                         false, NULL);
2815         if (status != I40E_SUCCESS) {
2816                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2817                 /* Rollback unicast promiscuous mode */
2818                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2819                                                     true, NULL, true);
2820                 return -EAGAIN;
2821         }
2822
2823         return 0;
2824 }
2825
2826 static int
2827 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2828 {
2829         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2831         struct i40e_vsi *vsi = pf->main_vsi;
2832         int ret;
2833
2834         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2835         if (ret != I40E_SUCCESS) {
2836                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2837                 return -EAGAIN;
2838         }
2839
2840         return 0;
2841 }
2842
2843 static int
2844 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2845 {
2846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848         struct i40e_vsi *vsi = pf->main_vsi;
2849         int ret;
2850
2851         if (dev->data->promiscuous == 1)
2852                 return 0; /* must remain in all_multicast mode */
2853
2854         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2855                                 vsi->seid, FALSE, NULL);
2856         if (ret != I40E_SUCCESS) {
2857                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2858                 return -EAGAIN;
2859         }
2860
2861         return 0;
2862 }
2863
2864 /*
2865  * Set device link up.
2866  */
2867 static int
2868 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2869 {
2870         /* re-apply link speed setting */
2871         return i40e_apply_link_speed(dev);
2872 }
2873
2874 /*
2875  * Set device link down.
2876  */
2877 static int
2878 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2879 {
2880         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2881         uint8_t abilities = 0;
2882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883
2884         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2885         return i40e_phy_conf_link(hw, abilities, speed, false);
2886 }
2887
2888 static __rte_always_inline void
2889 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2890 {
2891 /* Link status registers and values*/
2892 #define I40E_PRTMAC_LINKSTA             0x001E2420
2893 #define I40E_REG_LINK_UP                0x40000080
2894 #define I40E_PRTMAC_MACC                0x001E24E0
2895 #define I40E_REG_MACC_25GB              0x00020000
2896 #define I40E_REG_SPEED_MASK             0x38000000
2897 #define I40E_REG_SPEED_0                0x00000000
2898 #define I40E_REG_SPEED_1                0x08000000
2899 #define I40E_REG_SPEED_2                0x10000000
2900 #define I40E_REG_SPEED_3                0x18000000
2901 #define I40E_REG_SPEED_4                0x20000000
2902         uint32_t link_speed;
2903         uint32_t reg_val;
2904
2905         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2906         link_speed = reg_val & I40E_REG_SPEED_MASK;
2907         reg_val &= I40E_REG_LINK_UP;
2908         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2909
2910         if (unlikely(link->link_status == 0))
2911                 return;
2912
2913         /* Parse the link status */
2914         switch (link_speed) {
2915         case I40E_REG_SPEED_0:
2916                 link->link_speed = ETH_SPEED_NUM_100M;
2917                 break;
2918         case I40E_REG_SPEED_1:
2919                 link->link_speed = ETH_SPEED_NUM_1G;
2920                 break;
2921         case I40E_REG_SPEED_2:
2922                 if (hw->mac.type == I40E_MAC_X722)
2923                         link->link_speed = ETH_SPEED_NUM_2_5G;
2924                 else
2925                         link->link_speed = ETH_SPEED_NUM_10G;
2926                 break;
2927         case I40E_REG_SPEED_3:
2928                 if (hw->mac.type == I40E_MAC_X722) {
2929                         link->link_speed = ETH_SPEED_NUM_5G;
2930                 } else {
2931                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2932
2933                         if (reg_val & I40E_REG_MACC_25GB)
2934                                 link->link_speed = ETH_SPEED_NUM_25G;
2935                         else
2936                                 link->link_speed = ETH_SPEED_NUM_40G;
2937                 }
2938                 break;
2939         case I40E_REG_SPEED_4:
2940                 if (hw->mac.type == I40E_MAC_X722)
2941                         link->link_speed = ETH_SPEED_NUM_10G;
2942                 else
2943                         link->link_speed = ETH_SPEED_NUM_20G;
2944                 break;
2945         default:
2946                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2947                 break;
2948         }
2949 }
2950
2951 static __rte_always_inline void
2952 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2953         bool enable_lse, int wait_to_complete)
2954 {
2955 #define CHECK_INTERVAL             100  /* 100ms */
2956 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2957         uint32_t rep_cnt = MAX_REPEAT_TIME;
2958         struct i40e_link_status link_status;
2959         int status;
2960
2961         memset(&link_status, 0, sizeof(link_status));
2962
2963         do {
2964                 memset(&link_status, 0, sizeof(link_status));
2965
2966                 /* Get link status information from hardware */
2967                 status = i40e_aq_get_link_info(hw, enable_lse,
2968                                                 &link_status, NULL);
2969                 if (unlikely(status != I40E_SUCCESS)) {
2970                         link->link_speed = ETH_SPEED_NUM_NONE;
2971                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2972                         PMD_DRV_LOG(ERR, "Failed to get link info");
2973                         return;
2974                 }
2975
2976                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2977                 if (!wait_to_complete || link->link_status)
2978                         break;
2979
2980                 rte_delay_ms(CHECK_INTERVAL);
2981         } while (--rep_cnt);
2982
2983         /* Parse the link status */
2984         switch (link_status.link_speed) {
2985         case I40E_LINK_SPEED_100MB:
2986                 link->link_speed = ETH_SPEED_NUM_100M;
2987                 break;
2988         case I40E_LINK_SPEED_1GB:
2989                 link->link_speed = ETH_SPEED_NUM_1G;
2990                 break;
2991         case I40E_LINK_SPEED_10GB:
2992                 link->link_speed = ETH_SPEED_NUM_10G;
2993                 break;
2994         case I40E_LINK_SPEED_20GB:
2995                 link->link_speed = ETH_SPEED_NUM_20G;
2996                 break;
2997         case I40E_LINK_SPEED_25GB:
2998                 link->link_speed = ETH_SPEED_NUM_25G;
2999                 break;
3000         case I40E_LINK_SPEED_40GB:
3001                 link->link_speed = ETH_SPEED_NUM_40G;
3002                 break;
3003         default:
3004                 link->link_speed = ETH_SPEED_NUM_NONE;
3005                 break;
3006         }
3007 }
3008
3009 int
3010 i40e_dev_link_update(struct rte_eth_dev *dev,
3011                      int wait_to_complete)
3012 {
3013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3014         struct rte_eth_link link;
3015         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3016         int ret;
3017
3018         memset(&link, 0, sizeof(link));
3019
3020         /* i40e uses full duplex only */
3021         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3022         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3023                         ETH_LINK_SPEED_FIXED);
3024
3025         if (!wait_to_complete && !enable_lse)
3026                 update_link_reg(hw, &link);
3027         else
3028                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3029
3030         if (hw->switch_dev)
3031                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3032
3033         ret = rte_eth_linkstatus_set(dev, &link);
3034         i40e_notify_all_vfs_link_status(dev);
3035
3036         return ret;
3037 }
3038
3039 /* Get all the statistics of a VSI */
3040 void
3041 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3042 {
3043         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3044         struct i40e_eth_stats *nes = &vsi->eth_stats;
3045         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3046         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3047
3048         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3049                             vsi->offset_loaded, &oes->rx_bytes,
3050                             &nes->rx_bytes);
3051         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3052                             vsi->offset_loaded, &oes->rx_unicast,
3053                             &nes->rx_unicast);
3054         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3055                             vsi->offset_loaded, &oes->rx_multicast,
3056                             &nes->rx_multicast);
3057         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3058                             vsi->offset_loaded, &oes->rx_broadcast,
3059                             &nes->rx_broadcast);
3060         /* exclude CRC bytes */
3061         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3062                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3063
3064         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3065                             &oes->rx_discards, &nes->rx_discards);
3066         /* GLV_REPC not supported */
3067         /* GLV_RMPC not supported */
3068         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3069                             &oes->rx_unknown_protocol,
3070                             &nes->rx_unknown_protocol);
3071         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3072                             vsi->offset_loaded, &oes->tx_bytes,
3073                             &nes->tx_bytes);
3074         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3075                             vsi->offset_loaded, &oes->tx_unicast,
3076                             &nes->tx_unicast);
3077         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3078                             vsi->offset_loaded, &oes->tx_multicast,
3079                             &nes->tx_multicast);
3080         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3081                             vsi->offset_loaded,  &oes->tx_broadcast,
3082                             &nes->tx_broadcast);
3083         /* GLV_TDPC not supported */
3084         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3085                             &oes->tx_errors, &nes->tx_errors);
3086         vsi->offset_loaded = true;
3087
3088         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3089                     vsi->vsi_id);
3090         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3091         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3092         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3093         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3094         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3095         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3096                     nes->rx_unknown_protocol);
3097         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3098         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3099         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3100         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3101         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3102         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3103         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3104                     vsi->vsi_id);
3105 }
3106
3107 static void
3108 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3109 {
3110         unsigned int i;
3111         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3112         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3113
3114         /* Get rx/tx bytes of internal transfer packets */
3115         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3116                         I40E_GLV_GORCL(hw->port),
3117                         pf->offset_loaded,
3118                         &pf->internal_stats_offset.rx_bytes,
3119                         &pf->internal_stats.rx_bytes);
3120
3121         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3122                         I40E_GLV_GOTCL(hw->port),
3123                         pf->offset_loaded,
3124                         &pf->internal_stats_offset.tx_bytes,
3125                         &pf->internal_stats.tx_bytes);
3126         /* Get total internal rx packet count */
3127         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3128                             I40E_GLV_UPRCL(hw->port),
3129                             pf->offset_loaded,
3130                             &pf->internal_stats_offset.rx_unicast,
3131                             &pf->internal_stats.rx_unicast);
3132         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3133                             I40E_GLV_MPRCL(hw->port),
3134                             pf->offset_loaded,
3135                             &pf->internal_stats_offset.rx_multicast,
3136                             &pf->internal_stats.rx_multicast);
3137         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3138                             I40E_GLV_BPRCL(hw->port),
3139                             pf->offset_loaded,
3140                             &pf->internal_stats_offset.rx_broadcast,
3141                             &pf->internal_stats.rx_broadcast);
3142         /* Get total internal tx packet count */
3143         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3144                             I40E_GLV_UPTCL(hw->port),
3145                             pf->offset_loaded,
3146                             &pf->internal_stats_offset.tx_unicast,
3147                             &pf->internal_stats.tx_unicast);
3148         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3149                             I40E_GLV_MPTCL(hw->port),
3150                             pf->offset_loaded,
3151                             &pf->internal_stats_offset.tx_multicast,
3152                             &pf->internal_stats.tx_multicast);
3153         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3154                             I40E_GLV_BPTCL(hw->port),
3155                             pf->offset_loaded,
3156                             &pf->internal_stats_offset.tx_broadcast,
3157                             &pf->internal_stats.tx_broadcast);
3158
3159         /* exclude CRC size */
3160         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3161                 pf->internal_stats.rx_multicast +
3162                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3163
3164         /* Get statistics of struct i40e_eth_stats */
3165         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3166                             I40E_GLPRT_GORCL(hw->port),
3167                             pf->offset_loaded, &os->eth.rx_bytes,
3168                             &ns->eth.rx_bytes);
3169         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3170                             I40E_GLPRT_UPRCL(hw->port),
3171                             pf->offset_loaded, &os->eth.rx_unicast,
3172                             &ns->eth.rx_unicast);
3173         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3174                             I40E_GLPRT_MPRCL(hw->port),
3175                             pf->offset_loaded, &os->eth.rx_multicast,
3176                             &ns->eth.rx_multicast);
3177         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3178                             I40E_GLPRT_BPRCL(hw->port),
3179                             pf->offset_loaded, &os->eth.rx_broadcast,
3180                             &ns->eth.rx_broadcast);
3181         /* Workaround: CRC size should not be included in byte statistics,
3182          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3183          * packet.
3184          */
3185         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3186                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3187
3188         /* exclude internal rx bytes
3189          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3190          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3191          * value.
3192          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3193          */
3194         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3195                 ns->eth.rx_bytes = 0;
3196         else
3197                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3198
3199         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3200                 ns->eth.rx_unicast = 0;
3201         else
3202                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3203
3204         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3205                 ns->eth.rx_multicast = 0;
3206         else
3207                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3208
3209         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3210                 ns->eth.rx_broadcast = 0;
3211         else
3212                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3213
3214         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3215                             pf->offset_loaded, &os->eth.rx_discards,
3216                             &ns->eth.rx_discards);
3217         /* GLPRT_REPC not supported */
3218         /* GLPRT_RMPC not supported */
3219         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3220                             pf->offset_loaded,
3221                             &os->eth.rx_unknown_protocol,
3222                             &ns->eth.rx_unknown_protocol);
3223         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3224                             I40E_GLPRT_GOTCL(hw->port),
3225                             pf->offset_loaded, &os->eth.tx_bytes,
3226                             &ns->eth.tx_bytes);
3227         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3228                             I40E_GLPRT_UPTCL(hw->port),
3229                             pf->offset_loaded, &os->eth.tx_unicast,
3230                             &ns->eth.tx_unicast);
3231         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3232                             I40E_GLPRT_MPTCL(hw->port),
3233                             pf->offset_loaded, &os->eth.tx_multicast,
3234                             &ns->eth.tx_multicast);
3235         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3236                             I40E_GLPRT_BPTCL(hw->port),
3237                             pf->offset_loaded, &os->eth.tx_broadcast,
3238                             &ns->eth.tx_broadcast);
3239         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3240                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3241
3242         /* exclude internal tx bytes
3243          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3244          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3245          * value.
3246          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3247          */
3248         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3249                 ns->eth.tx_bytes = 0;
3250         else
3251                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3252
3253         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3254                 ns->eth.tx_unicast = 0;
3255         else
3256                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3257
3258         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3259                 ns->eth.tx_multicast = 0;
3260         else
3261                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3262
3263         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3264                 ns->eth.tx_broadcast = 0;
3265         else
3266                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3267
3268         /* GLPRT_TEPC not supported */
3269
3270         /* additional port specific stats */
3271         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3272                             pf->offset_loaded, &os->tx_dropped_link_down,
3273                             &ns->tx_dropped_link_down);
3274         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3275                             pf->offset_loaded, &os->crc_errors,
3276                             &ns->crc_errors);
3277         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3278                             pf->offset_loaded, &os->illegal_bytes,
3279                             &ns->illegal_bytes);
3280         /* GLPRT_ERRBC not supported */
3281         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3282                             pf->offset_loaded, &os->mac_local_faults,
3283                             &ns->mac_local_faults);
3284         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3285                             pf->offset_loaded, &os->mac_remote_faults,
3286                             &ns->mac_remote_faults);
3287         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3288                             pf->offset_loaded, &os->rx_length_errors,
3289                             &ns->rx_length_errors);
3290         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3291                             pf->offset_loaded, &os->link_xon_rx,
3292                             &ns->link_xon_rx);
3293         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3294                             pf->offset_loaded, &os->link_xoff_rx,
3295                             &ns->link_xoff_rx);
3296         for (i = 0; i < 8; i++) {
3297                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3298                                     pf->offset_loaded,
3299                                     &os->priority_xon_rx[i],
3300                                     &ns->priority_xon_rx[i]);
3301                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3302                                     pf->offset_loaded,
3303                                     &os->priority_xoff_rx[i],
3304                                     &ns->priority_xoff_rx[i]);
3305         }
3306         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3307                             pf->offset_loaded, &os->link_xon_tx,
3308                             &ns->link_xon_tx);
3309         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3310                             pf->offset_loaded, &os->link_xoff_tx,
3311                             &ns->link_xoff_tx);
3312         for (i = 0; i < 8; i++) {
3313                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3314                                     pf->offset_loaded,
3315                                     &os->priority_xon_tx[i],
3316                                     &ns->priority_xon_tx[i]);
3317                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3318                                     pf->offset_loaded,
3319                                     &os->priority_xoff_tx[i],
3320                                     &ns->priority_xoff_tx[i]);
3321                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3322                                     pf->offset_loaded,
3323                                     &os->priority_xon_2_xoff[i],
3324                                     &ns->priority_xon_2_xoff[i]);
3325         }
3326         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3327                             I40E_GLPRT_PRC64L(hw->port),
3328                             pf->offset_loaded, &os->rx_size_64,
3329                             &ns->rx_size_64);
3330         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3331                             I40E_GLPRT_PRC127L(hw->port),
3332                             pf->offset_loaded, &os->rx_size_127,
3333                             &ns->rx_size_127);
3334         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3335                             I40E_GLPRT_PRC255L(hw->port),
3336                             pf->offset_loaded, &os->rx_size_255,
3337                             &ns->rx_size_255);
3338         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3339                             I40E_GLPRT_PRC511L(hw->port),
3340                             pf->offset_loaded, &os->rx_size_511,
3341                             &ns->rx_size_511);
3342         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3343                             I40E_GLPRT_PRC1023L(hw->port),
3344                             pf->offset_loaded, &os->rx_size_1023,
3345                             &ns->rx_size_1023);
3346         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3347                             I40E_GLPRT_PRC1522L(hw->port),
3348                             pf->offset_loaded, &os->rx_size_1522,
3349                             &ns->rx_size_1522);
3350         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3351                             I40E_GLPRT_PRC9522L(hw->port),
3352                             pf->offset_loaded, &os->rx_size_big,
3353                             &ns->rx_size_big);
3354         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3355                             pf->offset_loaded, &os->rx_undersize,
3356                             &ns->rx_undersize);
3357         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3358                             pf->offset_loaded, &os->rx_fragments,
3359                             &ns->rx_fragments);
3360         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3361                             pf->offset_loaded, &os->rx_oversize,
3362                             &ns->rx_oversize);
3363         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3364                             pf->offset_loaded, &os->rx_jabber,
3365                             &ns->rx_jabber);
3366         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3367                             I40E_GLPRT_PTC64L(hw->port),
3368                             pf->offset_loaded, &os->tx_size_64,
3369                             &ns->tx_size_64);
3370         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3371                             I40E_GLPRT_PTC127L(hw->port),
3372                             pf->offset_loaded, &os->tx_size_127,
3373                             &ns->tx_size_127);
3374         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3375                             I40E_GLPRT_PTC255L(hw->port),
3376                             pf->offset_loaded, &os->tx_size_255,
3377                             &ns->tx_size_255);
3378         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3379                             I40E_GLPRT_PTC511L(hw->port),
3380                             pf->offset_loaded, &os->tx_size_511,
3381                             &ns->tx_size_511);
3382         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3383                             I40E_GLPRT_PTC1023L(hw->port),
3384                             pf->offset_loaded, &os->tx_size_1023,
3385                             &ns->tx_size_1023);
3386         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3387                             I40E_GLPRT_PTC1522L(hw->port),
3388                             pf->offset_loaded, &os->tx_size_1522,
3389                             &ns->tx_size_1522);
3390         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3391                             I40E_GLPRT_PTC9522L(hw->port),
3392                             pf->offset_loaded, &os->tx_size_big,
3393                             &ns->tx_size_big);
3394         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3395                            pf->offset_loaded,
3396                            &os->fd_sb_match, &ns->fd_sb_match);
3397         /* GLPRT_MSPDC not supported */
3398         /* GLPRT_XEC not supported */
3399
3400         pf->offset_loaded = true;
3401
3402         if (pf->main_vsi)
3403                 i40e_update_vsi_stats(pf->main_vsi);
3404 }
3405
3406 /* Get all statistics of a port */
3407 static int
3408 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3409 {
3410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3412         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3413         struct i40e_vsi *vsi;
3414         unsigned i;
3415
3416         /* call read registers - updates values, now write them to struct */
3417         i40e_read_stats_registers(pf, hw);
3418
3419         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3420                         pf->main_vsi->eth_stats.rx_multicast +
3421                         pf->main_vsi->eth_stats.rx_broadcast -
3422                         pf->main_vsi->eth_stats.rx_discards;
3423         stats->opackets = ns->eth.tx_unicast +
3424                         ns->eth.tx_multicast +
3425                         ns->eth.tx_broadcast;
3426         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3427         stats->obytes   = ns->eth.tx_bytes;
3428         stats->oerrors  = ns->eth.tx_errors +
3429                         pf->main_vsi->eth_stats.tx_errors;
3430
3431         /* Rx Errors */
3432         stats->imissed  = ns->eth.rx_discards +
3433                         pf->main_vsi->eth_stats.rx_discards;
3434         stats->ierrors  = ns->crc_errors +
3435                         ns->rx_length_errors + ns->rx_undersize +
3436                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3437
3438         if (pf->vfs) {
3439                 for (i = 0; i < pf->vf_num; i++) {
3440                         vsi = pf->vfs[i].vsi;
3441                         i40e_update_vsi_stats(vsi);
3442
3443                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3444                                         vsi->eth_stats.rx_multicast +
3445                                         vsi->eth_stats.rx_broadcast -
3446                                         vsi->eth_stats.rx_discards);
3447                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3448                         stats->oerrors  += vsi->eth_stats.tx_errors;
3449                         stats->imissed  += vsi->eth_stats.rx_discards;
3450                 }
3451         }
3452
3453         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3454         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3455         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3456         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3457         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3458         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3459         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3460                     ns->eth.rx_unknown_protocol);
3461         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3462         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3463         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3464         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3465         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3466         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3467
3468         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3469                     ns->tx_dropped_link_down);
3470         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3471         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3472                     ns->illegal_bytes);
3473         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3474         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3475                     ns->mac_local_faults);
3476         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3477                     ns->mac_remote_faults);
3478         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3479                     ns->rx_length_errors);
3480         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3481         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3482         for (i = 0; i < 8; i++) {
3483                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3484                                 i, ns->priority_xon_rx[i]);
3485                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3486                                 i, ns->priority_xoff_rx[i]);
3487         }
3488         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3489         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3490         for (i = 0; i < 8; i++) {
3491                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3492                                 i, ns->priority_xon_tx[i]);
3493                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3494                                 i, ns->priority_xoff_tx[i]);
3495                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3496                                 i, ns->priority_xon_2_xoff[i]);
3497         }
3498         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3499         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3500         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3501         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3502         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3503         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3504         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3505         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3506         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3507         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3508         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3509         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3510         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3511         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3512         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3513         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3514         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3515         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3516         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3517                         ns->mac_short_packet_dropped);
3518         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3519                     ns->checksum_error);
3520         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3521         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3522         return 0;
3523 }
3524
3525 /* Reset the statistics */
3526 static int
3527 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3528 {
3529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3531
3532         /* Mark PF and VSI stats to update the offset, aka "reset" */
3533         pf->offset_loaded = false;
3534         if (pf->main_vsi)
3535                 pf->main_vsi->offset_loaded = false;
3536
3537         /* read the stats, reading current register values into offset */
3538         i40e_read_stats_registers(pf, hw);
3539
3540         return 0;
3541 }
3542
3543 static uint32_t
3544 i40e_xstats_calc_num(void)
3545 {
3546         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3547                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3548                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3549 }
3550
3551 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3552                                      struct rte_eth_xstat_name *xstats_names,
3553                                      __rte_unused unsigned limit)
3554 {
3555         unsigned count = 0;
3556         unsigned i, prio;
3557
3558         if (xstats_names == NULL)
3559                 return i40e_xstats_calc_num();
3560
3561         /* Note: limit checked in rte_eth_xstats_names() */
3562
3563         /* Get stats from i40e_eth_stats struct */
3564         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3565                 strlcpy(xstats_names[count].name,
3566                         rte_i40e_stats_strings[i].name,
3567                         sizeof(xstats_names[count].name));
3568                 count++;
3569         }
3570
3571         /* Get individiual stats from i40e_hw_port struct */
3572         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3573                 strlcpy(xstats_names[count].name,
3574                         rte_i40e_hw_port_strings[i].name,
3575                         sizeof(xstats_names[count].name));
3576                 count++;
3577         }
3578
3579         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3580                 for (prio = 0; prio < 8; prio++) {
3581                         snprintf(xstats_names[count].name,
3582                                  sizeof(xstats_names[count].name),
3583                                  "rx_priority%u_%s", prio,
3584                                  rte_i40e_rxq_prio_strings[i].name);
3585                         count++;
3586                 }
3587         }
3588
3589         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3590                 for (prio = 0; prio < 8; prio++) {
3591                         snprintf(xstats_names[count].name,
3592                                  sizeof(xstats_names[count].name),
3593                                  "tx_priority%u_%s", prio,
3594                                  rte_i40e_txq_prio_strings[i].name);
3595                         count++;
3596                 }
3597         }
3598         return count;
3599 }
3600
3601 static int
3602 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3603                     unsigned n)
3604 {
3605         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3606         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607         unsigned i, count, prio;
3608         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3609
3610         count = i40e_xstats_calc_num();
3611         if (n < count)
3612                 return count;
3613
3614         i40e_read_stats_registers(pf, hw);
3615
3616         if (xstats == NULL)
3617                 return 0;
3618
3619         count = 0;
3620
3621         /* Get stats from i40e_eth_stats struct */
3622         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3623                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3624                         rte_i40e_stats_strings[i].offset);
3625                 xstats[count].id = count;
3626                 count++;
3627         }
3628
3629         /* Get individiual stats from i40e_hw_port struct */
3630         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3631                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3632                         rte_i40e_hw_port_strings[i].offset);
3633                 xstats[count].id = count;
3634                 count++;
3635         }
3636
3637         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3638                 for (prio = 0; prio < 8; prio++) {
3639                         xstats[count].value =
3640                                 *(uint64_t *)(((char *)hw_stats) +
3641                                 rte_i40e_rxq_prio_strings[i].offset +
3642                                 (sizeof(uint64_t) * prio));
3643                         xstats[count].id = count;
3644                         count++;
3645                 }
3646         }
3647
3648         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3649                 for (prio = 0; prio < 8; prio++) {
3650                         xstats[count].value =
3651                                 *(uint64_t *)(((char *)hw_stats) +
3652                                 rte_i40e_txq_prio_strings[i].offset +
3653                                 (sizeof(uint64_t) * prio));
3654                         xstats[count].id = count;
3655                         count++;
3656                 }
3657         }
3658
3659         return count;
3660 }
3661
3662 static int
3663 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3664 {
3665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3666         u32 full_ver;
3667         u8 ver, patch;
3668         u16 build;
3669         int ret;
3670
3671         full_ver = hw->nvm.oem_ver;
3672         ver = (u8)(full_ver >> 24);
3673         build = (u16)((full_ver >> 8) & 0xffff);
3674         patch = (u8)(full_ver & 0xff);
3675
3676         ret = snprintf(fw_version, fw_size,
3677                  "%d.%d%d 0x%08x %d.%d.%d",
3678                  ((hw->nvm.version >> 12) & 0xf),
3679                  ((hw->nvm.version >> 4) & 0xff),
3680                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3681                  ver, build, patch);
3682
3683         ret += 1; /* add the size of '\0' */
3684         if (fw_size < (u32)ret)
3685                 return ret;
3686         else
3687                 return 0;
3688 }
3689
3690 /*
3691  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3692  * the Rx data path does not hang if the FW LLDP is stopped.
3693  * return true if lldp need to stop
3694  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3695  */
3696 static bool
3697 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3698 {
3699         double nvm_ver;
3700         char ver_str[64] = {0};
3701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3702
3703         i40e_fw_version_get(dev, ver_str, 64);
3704         nvm_ver = atof(ver_str);
3705         if ((hw->mac.type == I40E_MAC_X722 ||
3706              hw->mac.type == I40E_MAC_X722_VF) &&
3707              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3708                 return true;
3709         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3710                 return true;
3711
3712         return false;
3713 }
3714
3715 static int
3716 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3717 {
3718         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3720         struct i40e_vsi *vsi = pf->main_vsi;
3721         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3722
3723         dev_info->max_rx_queues = vsi->nb_qps;
3724         dev_info->max_tx_queues = vsi->nb_qps;
3725         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3726         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3727         dev_info->max_mac_addrs = vsi->max_macaddrs;
3728         dev_info->max_vfs = pci_dev->max_vfs;
3729         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3730         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3731         dev_info->rx_queue_offload_capa = 0;
3732         dev_info->rx_offload_capa =
3733                 DEV_RX_OFFLOAD_VLAN_STRIP |
3734                 DEV_RX_OFFLOAD_QINQ_STRIP |
3735                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3736                 DEV_RX_OFFLOAD_UDP_CKSUM |
3737                 DEV_RX_OFFLOAD_TCP_CKSUM |
3738                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3739                 DEV_RX_OFFLOAD_KEEP_CRC |
3740                 DEV_RX_OFFLOAD_SCATTER |
3741                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3742                 DEV_RX_OFFLOAD_VLAN_FILTER |
3743                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3744                 DEV_RX_OFFLOAD_RSS_HASH;
3745
3746         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3747         dev_info->tx_offload_capa =
3748                 DEV_TX_OFFLOAD_VLAN_INSERT |
3749                 DEV_TX_OFFLOAD_QINQ_INSERT |
3750                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3751                 DEV_TX_OFFLOAD_UDP_CKSUM |
3752                 DEV_TX_OFFLOAD_TCP_CKSUM |
3753                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3754                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3755                 DEV_TX_OFFLOAD_TCP_TSO |
3756                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3757                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3758                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3759                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3760                 DEV_TX_OFFLOAD_MULTI_SEGS |
3761                 dev_info->tx_queue_offload_capa;
3762         dev_info->dev_capa =
3763                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3764                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3765
3766         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3767                                                 sizeof(uint32_t);
3768         dev_info->reta_size = pf->hash_lut_size;
3769         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3770
3771         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3772                 .rx_thresh = {
3773                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3774                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3775                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3776                 },
3777                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3778                 .rx_drop_en = 0,
3779                 .offloads = 0,
3780         };
3781
3782         dev_info->default_txconf = (struct rte_eth_txconf) {
3783                 .tx_thresh = {
3784                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3785                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3786                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3787                 },
3788                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3789                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3790                 .offloads = 0,
3791         };
3792
3793         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3794                 .nb_max = I40E_MAX_RING_DESC,
3795                 .nb_min = I40E_MIN_RING_DESC,
3796                 .nb_align = I40E_ALIGN_RING_DESC,
3797         };
3798
3799         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3800                 .nb_max = I40E_MAX_RING_DESC,
3801                 .nb_min = I40E_MIN_RING_DESC,
3802                 .nb_align = I40E_ALIGN_RING_DESC,
3803                 .nb_seg_max = I40E_TX_MAX_SEG,
3804                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3805         };
3806
3807         if (pf->flags & I40E_FLAG_VMDQ) {
3808                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3809                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3810                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3811                                                 pf->max_nb_vmdq_vsi;
3812                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3813                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3814                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3815         }
3816
3817         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3818                 /* For XL710 */
3819                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3820                 dev_info->default_rxportconf.nb_queues = 2;
3821                 dev_info->default_txportconf.nb_queues = 2;
3822                 if (dev->data->nb_rx_queues == 1)
3823                         dev_info->default_rxportconf.ring_size = 2048;
3824                 else
3825                         dev_info->default_rxportconf.ring_size = 1024;
3826                 if (dev->data->nb_tx_queues == 1)
3827                         dev_info->default_txportconf.ring_size = 1024;
3828                 else
3829                         dev_info->default_txportconf.ring_size = 512;
3830
3831         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3832                 /* For XXV710 */
3833                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3834                 dev_info->default_rxportconf.nb_queues = 1;
3835                 dev_info->default_txportconf.nb_queues = 1;
3836                 dev_info->default_rxportconf.ring_size = 256;
3837                 dev_info->default_txportconf.ring_size = 256;
3838         } else {
3839                 /* For X710 */
3840                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3841                 dev_info->default_rxportconf.nb_queues = 1;
3842                 dev_info->default_txportconf.nb_queues = 1;
3843                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3844                         dev_info->default_rxportconf.ring_size = 512;
3845                         dev_info->default_txportconf.ring_size = 256;
3846                 } else {
3847                         dev_info->default_rxportconf.ring_size = 256;
3848                         dev_info->default_txportconf.ring_size = 256;
3849                 }
3850         }
3851         dev_info->default_rxportconf.burst_size = 32;
3852         dev_info->default_txportconf.burst_size = 32;
3853
3854         return 0;
3855 }
3856
3857 static int
3858 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3859 {
3860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3861         struct i40e_vsi *vsi = pf->main_vsi;
3862         PMD_INIT_FUNC_TRACE();
3863
3864         if (on)
3865                 return i40e_vsi_add_vlan(vsi, vlan_id);
3866         else
3867                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3868 }
3869
3870 static int
3871 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3872                                 enum rte_vlan_type vlan_type,
3873                                 uint16_t tpid, int qinq)
3874 {
3875         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876         uint64_t reg_r = 0;
3877         uint64_t reg_w = 0;
3878         uint16_t reg_id = 3;
3879         int ret;
3880
3881         if (qinq) {
3882                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3883                         reg_id = 2;
3884         }
3885
3886         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3887                                           &reg_r, NULL);
3888         if (ret != I40E_SUCCESS) {
3889                 PMD_DRV_LOG(ERR,
3890                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3891                            reg_id);
3892                 return -EIO;
3893         }
3894         PMD_DRV_LOG(DEBUG,
3895                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3896                     reg_id, reg_r);
3897
3898         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3899         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3900         if (reg_r == reg_w) {
3901                 PMD_DRV_LOG(DEBUG, "No need to write");
3902                 return 0;
3903         }
3904
3905         ret = i40e_aq_debug_write_global_register(hw,
3906                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3907                                            reg_w, NULL);
3908         if (ret != I40E_SUCCESS) {
3909                 PMD_DRV_LOG(ERR,
3910                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3911                             reg_id);
3912                 return -EIO;
3913         }
3914         PMD_DRV_LOG(DEBUG,
3915                     "Global register 0x%08x is changed with value 0x%08x",
3916                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3917
3918         return 0;
3919 }
3920
3921 static int
3922 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3923                    enum rte_vlan_type vlan_type,
3924                    uint16_t tpid)
3925 {
3926         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3928         int qinq = dev->data->dev_conf.rxmode.offloads &
3929                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3930         int ret = 0;
3931
3932         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3933              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3934             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3935                 PMD_DRV_LOG(ERR,
3936                             "Unsupported vlan type.");
3937                 return -EINVAL;
3938         }
3939
3940         if (pf->support_multi_driver) {
3941                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3942                 return -ENOTSUP;
3943         }
3944
3945         /* 802.1ad frames ability is added in NVM API 1.7*/
3946         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3947                 if (qinq) {
3948                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3949                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3950                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3951                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3952                 } else {
3953                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3954                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3955                 }
3956                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3957                 if (ret != I40E_SUCCESS) {
3958                         PMD_DRV_LOG(ERR,
3959                                     "Set switch config failed aq_err: %d",
3960                                     hw->aq.asq_last_status);
3961                         ret = -EIO;
3962                 }
3963         } else
3964                 /* If NVM API < 1.7, keep the register setting */
3965                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3966                                                       tpid, qinq);
3967
3968         return ret;
3969 }
3970
3971 static int
3972 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3973 {
3974         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3975         struct i40e_vsi *vsi = pf->main_vsi;
3976         struct rte_eth_rxmode *rxmode;
3977
3978         rxmode = &dev->data->dev_conf.rxmode;
3979         if (mask & ETH_VLAN_FILTER_MASK) {
3980                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3981                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3982                 else
3983                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3984         }
3985
3986         if (mask & ETH_VLAN_STRIP_MASK) {
3987                 /* Enable or disable VLAN stripping */
3988                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3989                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3990                 else
3991                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3992         }
3993
3994         if (mask & ETH_VLAN_EXTEND_MASK) {
3995                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3996                         i40e_vsi_config_double_vlan(vsi, TRUE);
3997                         /* Set global registers with default ethertype. */
3998                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3999                                            RTE_ETHER_TYPE_VLAN);
4000                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4001                                            RTE_ETHER_TYPE_VLAN);
4002                 }
4003                 else
4004                         i40e_vsi_config_double_vlan(vsi, FALSE);
4005         }
4006
4007         return 0;
4008 }
4009
4010 static void
4011 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4012                           __rte_unused uint16_t queue,
4013                           __rte_unused int on)
4014 {
4015         PMD_INIT_FUNC_TRACE();
4016 }
4017
4018 static int
4019 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4020 {
4021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4022         struct i40e_vsi *vsi = pf->main_vsi;
4023         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4024         struct i40e_vsi_vlan_pvid_info info;
4025
4026         memset(&info, 0, sizeof(info));
4027         info.on = on;
4028         if (info.on)
4029                 info.config.pvid = pvid;
4030         else {
4031                 info.config.reject.tagged =
4032                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4033                 info.config.reject.untagged =
4034                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4035         }
4036
4037         return i40e_vsi_vlan_pvid_set(vsi, &info);
4038 }
4039
4040 static int
4041 i40e_dev_led_on(struct rte_eth_dev *dev)
4042 {
4043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4044         uint32_t mode = i40e_led_get(hw);
4045
4046         if (mode == 0)
4047                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4048
4049         return 0;
4050 }
4051
4052 static int
4053 i40e_dev_led_off(struct rte_eth_dev *dev)
4054 {
4055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4056         uint32_t mode = i40e_led_get(hw);
4057
4058         if (mode != 0)
4059                 i40e_led_set(hw, 0, false);
4060
4061         return 0;
4062 }
4063
4064 static int
4065 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4066 {
4067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4069
4070         fc_conf->pause_time = pf->fc_conf.pause_time;
4071
4072         /* read out from register, in case they are modified by other port */
4073         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4074                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4075         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4076                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4077
4078         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4079         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4080
4081          /* Return current mode according to actual setting*/
4082         switch (hw->fc.current_mode) {
4083         case I40E_FC_FULL:
4084                 fc_conf->mode = RTE_FC_FULL;
4085                 break;
4086         case I40E_FC_TX_PAUSE:
4087                 fc_conf->mode = RTE_FC_TX_PAUSE;
4088                 break;
4089         case I40E_FC_RX_PAUSE:
4090                 fc_conf->mode = RTE_FC_RX_PAUSE;
4091                 break;
4092         case I40E_FC_NONE:
4093         default:
4094                 fc_conf->mode = RTE_FC_NONE;
4095         };
4096
4097         return 0;
4098 }
4099
4100 static int
4101 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4102 {
4103         uint32_t mflcn_reg, fctrl_reg, reg;
4104         uint32_t max_high_water;
4105         uint8_t i, aq_failure;
4106         int err;
4107         struct i40e_hw *hw;
4108         struct i40e_pf *pf;
4109         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4110                 [RTE_FC_NONE] = I40E_FC_NONE,
4111                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4112                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4113                 [RTE_FC_FULL] = I40E_FC_FULL
4114         };
4115
4116         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4117
4118         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4119         if ((fc_conf->high_water > max_high_water) ||
4120                         (fc_conf->high_water < fc_conf->low_water)) {
4121                 PMD_INIT_LOG(ERR,
4122                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4123                         max_high_water);
4124                 return -EINVAL;
4125         }
4126
4127         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4128         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4129         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4130
4131         pf->fc_conf.pause_time = fc_conf->pause_time;
4132         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4133         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4134
4135         PMD_INIT_FUNC_TRACE();
4136
4137         /* All the link flow control related enable/disable register
4138          * configuration is handle by the F/W
4139          */
4140         err = i40e_set_fc(hw, &aq_failure, true);
4141         if (err < 0)
4142                 return -ENOSYS;
4143
4144         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4145                 /* Configure flow control refresh threshold,
4146                  * the value for stat_tx_pause_refresh_timer[8]
4147                  * is used for global pause operation.
4148                  */
4149
4150                 I40E_WRITE_REG(hw,
4151                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4152                                pf->fc_conf.pause_time);
4153
4154                 /* configure the timer value included in transmitted pause
4155                  * frame,
4156                  * the value for stat_tx_pause_quanta[8] is used for global
4157                  * pause operation
4158                  */
4159                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4160                                pf->fc_conf.pause_time);
4161
4162                 fctrl_reg = I40E_READ_REG(hw,
4163                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4164
4165                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4166                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4167                 else
4168                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4169
4170                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4171                                fctrl_reg);
4172         } else {
4173                 /* Configure pause time (2 TCs per register) */
4174                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4175                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4176                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4177
4178                 /* Configure flow control refresh threshold value */
4179                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4180                                pf->fc_conf.pause_time / 2);
4181
4182                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4183
4184                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4185                  *depending on configuration
4186                  */
4187                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4188                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4189                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4190                 } else {
4191                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4192                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4193                 }
4194
4195                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4196         }
4197
4198         if (!pf->support_multi_driver) {
4199                 /* config water marker both based on the packets and bytes */
4200                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4201                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4202                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4203                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4204                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4205                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4206                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4207                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4208                                   << I40E_KILOSHIFT);
4209                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4210                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4211                                    << I40E_KILOSHIFT);
4212         } else {
4213                 PMD_DRV_LOG(ERR,
4214                             "Water marker configuration is not supported.");
4215         }
4216
4217         I40E_WRITE_FLUSH(hw);
4218
4219         return 0;
4220 }
4221
4222 static int
4223 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4224                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4225 {
4226         PMD_INIT_FUNC_TRACE();
4227
4228         return -ENOSYS;
4229 }
4230
4231 /* Add a MAC address, and update filters */
4232 static int
4233 i40e_macaddr_add(struct rte_eth_dev *dev,
4234                  struct rte_ether_addr *mac_addr,
4235                  __rte_unused uint32_t index,
4236                  uint32_t pool)
4237 {
4238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4239         struct i40e_mac_filter_info mac_filter;
4240         struct i40e_vsi *vsi;
4241         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4242         int ret;
4243
4244         /* If VMDQ not enabled or configured, return */
4245         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4246                           !pf->nb_cfg_vmdq_vsi)) {
4247                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4248                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4249                         pool);
4250                 return -ENOTSUP;
4251         }
4252
4253         if (pool > pf->nb_cfg_vmdq_vsi) {
4254                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4255                                 pool, pf->nb_cfg_vmdq_vsi);
4256                 return -EINVAL;
4257         }
4258
4259         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4260         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4261                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4262         else
4263                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4264
4265         if (pool == 0)
4266                 vsi = pf->main_vsi;
4267         else
4268                 vsi = pf->vmdq[pool - 1].vsi;
4269
4270         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4271         if (ret != I40E_SUCCESS) {
4272                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4273                 return -ENODEV;
4274         }
4275         return 0;
4276 }
4277
4278 /* Remove a MAC address, and update filters */
4279 static void
4280 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4281 {
4282         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4283         struct i40e_vsi *vsi;
4284         struct rte_eth_dev_data *data = dev->data;
4285         struct rte_ether_addr *macaddr;
4286         int ret;
4287         uint32_t i;
4288         uint64_t pool_sel;
4289
4290         macaddr = &(data->mac_addrs[index]);
4291
4292         pool_sel = dev->data->mac_pool_sel[index];
4293
4294         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4295                 if (pool_sel & (1ULL << i)) {
4296                         if (i == 0)
4297                                 vsi = pf->main_vsi;
4298                         else {
4299                                 /* No VMDQ pool enabled or configured */
4300                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4301                                         (i > pf->nb_cfg_vmdq_vsi)) {
4302                                         PMD_DRV_LOG(ERR,
4303                                                 "No VMDQ pool enabled/configured");
4304                                         return;
4305                                 }
4306                                 vsi = pf->vmdq[i - 1].vsi;
4307                         }
4308                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4309
4310                         if (ret) {
4311                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4312                                 return;
4313                         }
4314                 }
4315         }
4316 }
4317
4318 /* Set perfect match or hash match of MAC and VLAN for a VF */
4319 static int
4320 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4321                  struct rte_eth_mac_filter *filter,
4322                  bool add)
4323 {
4324         struct i40e_hw *hw;
4325         struct i40e_mac_filter_info mac_filter;
4326         struct rte_ether_addr old_mac;
4327         struct rte_ether_addr *new_mac;
4328         struct i40e_pf_vf *vf = NULL;
4329         uint16_t vf_id;
4330         int ret;
4331
4332         if (pf == NULL) {
4333                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4334                 return -EINVAL;
4335         }
4336         hw = I40E_PF_TO_HW(pf);
4337
4338         if (filter == NULL) {
4339                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4340                 return -EINVAL;
4341         }
4342
4343         new_mac = &filter->mac_addr;
4344
4345         if (rte_is_zero_ether_addr(new_mac)) {
4346                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4347                 return -EINVAL;
4348         }
4349
4350         vf_id = filter->dst_id;
4351
4352         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4353                 PMD_DRV_LOG(ERR, "Invalid argument.");
4354                 return -EINVAL;
4355         }
4356         vf = &pf->vfs[vf_id];
4357
4358         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4359                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4360                 return -EINVAL;
4361         }
4362
4363         if (add) {
4364                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4365                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4366                                 RTE_ETHER_ADDR_LEN);
4367                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4368                                  RTE_ETHER_ADDR_LEN);
4369
4370                 mac_filter.filter_type = filter->filter_type;
4371                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4372                 if (ret != I40E_SUCCESS) {
4373                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4374                         return -1;
4375                 }
4376                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4377         } else {
4378                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4379                                 RTE_ETHER_ADDR_LEN);
4380                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4381                 if (ret != I40E_SUCCESS) {
4382                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4383                         return -1;
4384                 }
4385
4386                 /* Clear device address as it has been removed */
4387                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4388                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4389         }
4390
4391         return 0;
4392 }
4393
4394 /* MAC filter handle */
4395 static int
4396 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4397                 void *arg)
4398 {
4399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4400         struct rte_eth_mac_filter *filter;
4401         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4402         int ret = I40E_NOT_SUPPORTED;
4403
4404         filter = (struct rte_eth_mac_filter *)(arg);
4405
4406         switch (filter_op) {
4407         case RTE_ETH_FILTER_NOP:
4408                 ret = I40E_SUCCESS;
4409                 break;
4410         case RTE_ETH_FILTER_ADD:
4411                 i40e_pf_disable_irq0(hw);
4412                 if (filter->is_vf)
4413                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4414                 i40e_pf_enable_irq0(hw);
4415                 break;
4416         case RTE_ETH_FILTER_DELETE:
4417                 i40e_pf_disable_irq0(hw);
4418                 if (filter->is_vf)
4419                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4420                 i40e_pf_enable_irq0(hw);
4421                 break;
4422         default:
4423                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4424                 ret = I40E_ERR_PARAM;
4425                 break;
4426         }
4427
4428         return ret;
4429 }
4430
4431 static int
4432 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4433 {
4434         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4435         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4436         uint32_t reg;
4437         int ret;
4438
4439         if (!lut)
4440                 return -EINVAL;
4441
4442         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4443                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4444                                           vsi->type != I40E_VSI_SRIOV,
4445                                           lut, lut_size);
4446                 if (ret) {
4447                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4448                         return ret;
4449                 }
4450         } else {
4451                 uint32_t *lut_dw = (uint32_t *)lut;
4452                 uint16_t i, lut_size_dw = lut_size / 4;
4453
4454                 if (vsi->type == I40E_VSI_SRIOV) {
4455                         for (i = 0; i <= lut_size_dw; i++) {
4456                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4457                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4458                         }
4459                 } else {
4460                         for (i = 0; i < lut_size_dw; i++)
4461                                 lut_dw[i] = I40E_READ_REG(hw,
4462                                                           I40E_PFQF_HLUT(i));
4463                 }
4464         }
4465
4466         return 0;
4467 }
4468
4469 int
4470 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4471 {
4472         struct i40e_pf *pf;
4473         struct i40e_hw *hw;
4474         int ret;
4475
4476         if (!vsi || !lut)
4477                 return -EINVAL;
4478
4479         pf = I40E_VSI_TO_PF(vsi);
4480         hw = I40E_VSI_TO_HW(vsi);
4481
4482         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4483                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4484                                           vsi->type != I40E_VSI_SRIOV,
4485                                           lut, lut_size);
4486                 if (ret) {
4487                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4488                         return ret;
4489                 }
4490         } else {
4491                 uint32_t *lut_dw = (uint32_t *)lut;
4492                 uint16_t i, lut_size_dw = lut_size / 4;
4493
4494                 if (vsi->type == I40E_VSI_SRIOV) {
4495                         for (i = 0; i < lut_size_dw; i++)
4496                                 I40E_WRITE_REG(
4497                                         hw,
4498                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4499                                         lut_dw[i]);
4500                 } else {
4501                         for (i = 0; i < lut_size_dw; i++)
4502                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4503                                                lut_dw[i]);
4504                 }
4505                 I40E_WRITE_FLUSH(hw);
4506         }
4507
4508         return 0;
4509 }
4510
4511 static int
4512 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4513                          struct rte_eth_rss_reta_entry64 *reta_conf,
4514                          uint16_t reta_size)
4515 {
4516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4517         uint16_t i, lut_size = pf->hash_lut_size;
4518         uint16_t idx, shift;
4519         uint8_t *lut;
4520         int ret;
4521
4522         if (reta_size != lut_size ||
4523                 reta_size > ETH_RSS_RETA_SIZE_512) {
4524                 PMD_DRV_LOG(ERR,
4525                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4526                         reta_size, lut_size);
4527                 return -EINVAL;
4528         }
4529
4530         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4531         if (!lut) {
4532                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4533                 return -ENOMEM;
4534         }
4535         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4536         if (ret)
4537                 goto out;
4538         for (i = 0; i < reta_size; i++) {
4539                 idx = i / RTE_RETA_GROUP_SIZE;
4540                 shift = i % RTE_RETA_GROUP_SIZE;
4541                 if (reta_conf[idx].mask & (1ULL << shift))
4542                         lut[i] = reta_conf[idx].reta[shift];
4543         }
4544         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4545
4546         pf->adapter->rss_reta_updated = 1;
4547
4548 out:
4549         rte_free(lut);
4550
4551         return ret;
4552 }
4553
4554 static int
4555 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4556                         struct rte_eth_rss_reta_entry64 *reta_conf,
4557                         uint16_t reta_size)
4558 {
4559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4560         uint16_t i, lut_size = pf->hash_lut_size;
4561         uint16_t idx, shift;
4562         uint8_t *lut;
4563         int ret;
4564
4565         if (reta_size != lut_size ||
4566                 reta_size > ETH_RSS_RETA_SIZE_512) {
4567                 PMD_DRV_LOG(ERR,
4568                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4569                         reta_size, lut_size);
4570                 return -EINVAL;
4571         }
4572
4573         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4574         if (!lut) {
4575                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4576                 return -ENOMEM;
4577         }
4578
4579         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4580         if (ret)
4581                 goto out;
4582         for (i = 0; i < reta_size; i++) {
4583                 idx = i / RTE_RETA_GROUP_SIZE;
4584                 shift = i % RTE_RETA_GROUP_SIZE;
4585                 if (reta_conf[idx].mask & (1ULL << shift))
4586                         reta_conf[idx].reta[shift] = lut[i];
4587         }
4588
4589 out:
4590         rte_free(lut);
4591
4592         return ret;
4593 }
4594
4595 /**
4596  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4597  * @hw:   pointer to the HW structure
4598  * @mem:  pointer to mem struct to fill out
4599  * @size: size of memory requested
4600  * @alignment: what to align the allocation to
4601  **/
4602 enum i40e_status_code
4603 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4604                         struct i40e_dma_mem *mem,
4605                         u64 size,
4606                         u32 alignment)
4607 {
4608         const struct rte_memzone *mz = NULL;
4609         char z_name[RTE_MEMZONE_NAMESIZE];
4610
4611         if (!mem)
4612                 return I40E_ERR_PARAM;
4613
4614         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4615         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4616                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4617         if (!mz)
4618                 return I40E_ERR_NO_MEMORY;
4619
4620         mem->size = size;
4621         mem->va = mz->addr;
4622         mem->pa = mz->iova;
4623         mem->zone = (const void *)mz;
4624         PMD_DRV_LOG(DEBUG,
4625                 "memzone %s allocated with physical address: %"PRIu64,
4626                 mz->name, mem->pa);
4627
4628         return I40E_SUCCESS;
4629 }
4630
4631 /**
4632  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4633  * @hw:   pointer to the HW structure
4634  * @mem:  ptr to mem struct to free
4635  **/
4636 enum i40e_status_code
4637 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4638                     struct i40e_dma_mem *mem)
4639 {
4640         if (!mem)
4641                 return I40E_ERR_PARAM;
4642
4643         PMD_DRV_LOG(DEBUG,
4644                 "memzone %s to be freed with physical address: %"PRIu64,
4645                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4646         rte_memzone_free((const struct rte_memzone *)mem->zone);
4647         mem->zone = NULL;
4648         mem->va = NULL;
4649         mem->pa = (u64)0;
4650
4651         return I40E_SUCCESS;
4652 }
4653
4654 /**
4655  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4656  * @hw:   pointer to the HW structure
4657  * @mem:  pointer to mem struct to fill out
4658  * @size: size of memory requested
4659  **/
4660 enum i40e_status_code
4661 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4662                          struct i40e_virt_mem *mem,
4663                          u32 size)
4664 {
4665         if (!mem)
4666                 return I40E_ERR_PARAM;
4667
4668         mem->size = size;
4669         mem->va = rte_zmalloc("i40e", size, 0);
4670
4671         if (mem->va)
4672                 return I40E_SUCCESS;
4673         else
4674                 return I40E_ERR_NO_MEMORY;
4675 }
4676
4677 /**
4678  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4679  * @hw:   pointer to the HW structure
4680  * @mem:  pointer to mem struct to free
4681  **/
4682 enum i40e_status_code
4683 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4684                      struct i40e_virt_mem *mem)
4685 {
4686         if (!mem)
4687                 return I40E_ERR_PARAM;
4688
4689         rte_free(mem->va);
4690         mem->va = NULL;
4691
4692         return I40E_SUCCESS;
4693 }
4694
4695 void
4696 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4697 {
4698         rte_spinlock_init(&sp->spinlock);
4699 }
4700
4701 void
4702 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4703 {
4704         rte_spinlock_lock(&sp->spinlock);
4705 }
4706
4707 void
4708 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4709 {
4710         rte_spinlock_unlock(&sp->spinlock);
4711 }
4712
4713 void
4714 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4715 {
4716         return;
4717 }
4718
4719 /**
4720  * Get the hardware capabilities, which will be parsed
4721  * and saved into struct i40e_hw.
4722  */
4723 static int
4724 i40e_get_cap(struct i40e_hw *hw)
4725 {
4726         struct i40e_aqc_list_capabilities_element_resp *buf;
4727         uint16_t len, size = 0;
4728         int ret;
4729
4730         /* Calculate a huge enough buff for saving response data temporarily */
4731         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4732                                                 I40E_MAX_CAP_ELE_NUM;
4733         buf = rte_zmalloc("i40e", len, 0);
4734         if (!buf) {
4735                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4736                 return I40E_ERR_NO_MEMORY;
4737         }
4738
4739         /* Get, parse the capabilities and save it to hw */
4740         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4741                         i40e_aqc_opc_list_func_capabilities, NULL);
4742         if (ret != I40E_SUCCESS)
4743                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4744
4745         /* Free the temporary buffer after being used */
4746         rte_free(buf);
4747
4748         return ret;
4749 }
4750
4751 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4752
4753 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4754                 const char *value,
4755                 void *opaque)
4756 {
4757         struct i40e_pf *pf;
4758         unsigned long num;
4759         char *end;
4760
4761         pf = (struct i40e_pf *)opaque;
4762         RTE_SET_USED(key);
4763
4764         errno = 0;
4765         num = strtoul(value, &end, 0);
4766         if (errno != 0 || end == value || *end != 0) {
4767                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4768                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4769                 return -(EINVAL);
4770         }
4771
4772         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4773                 pf->vf_nb_qp_max = (uint16_t)num;
4774         else
4775                 /* here return 0 to make next valid same argument work */
4776                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4777                             "power of 2 and equal or less than 16 !, Now it is "
4778                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4779
4780         return 0;
4781 }
4782
4783 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4784 {
4785         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4786         struct rte_kvargs *kvlist;
4787         int kvargs_count;
4788
4789         /* set default queue number per VF as 4 */
4790         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4791
4792         if (dev->device->devargs == NULL)
4793                 return 0;
4794
4795         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4796         if (kvlist == NULL)
4797                 return -(EINVAL);
4798
4799         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4800         if (!kvargs_count) {
4801                 rte_kvargs_free(kvlist);
4802                 return 0;
4803         }
4804
4805         if (kvargs_count > 1)
4806                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4807                             "the first invalid or last valid one is used !",
4808                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4809
4810         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4811                            i40e_pf_parse_vf_queue_number_handler, pf);
4812
4813         rte_kvargs_free(kvlist);
4814
4815         return 0;
4816 }
4817
4818 static int
4819 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4820 {
4821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4822         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4823         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4824         uint16_t qp_count = 0, vsi_count = 0;
4825
4826         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4827                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4828                 return -EINVAL;
4829         }
4830
4831         i40e_pf_config_vf_rxq_number(dev);
4832
4833         /* Add the parameter init for LFC */
4834         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4835         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4836         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4837
4838         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4839         pf->max_num_vsi = hw->func_caps.num_vsis;
4840         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4841         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4842
4843         /* FDir queue/VSI allocation */
4844         pf->fdir_qp_offset = 0;
4845         if (hw->func_caps.fd) {
4846                 pf->flags |= I40E_FLAG_FDIR;
4847                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4848         } else {
4849                 pf->fdir_nb_qps = 0;
4850         }
4851         qp_count += pf->fdir_nb_qps;
4852         vsi_count += 1;
4853
4854         /* LAN queue/VSI allocation */
4855         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4856         if (!hw->func_caps.rss) {
4857                 pf->lan_nb_qps = 1;
4858         } else {
4859                 pf->flags |= I40E_FLAG_RSS;
4860                 if (hw->mac.type == I40E_MAC_X722)
4861                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4862                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4863         }
4864         qp_count += pf->lan_nb_qps;
4865         vsi_count += 1;
4866
4867         /* VF queue/VSI allocation */
4868         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4869         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4870                 pf->flags |= I40E_FLAG_SRIOV;
4871                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4872                 pf->vf_num = pci_dev->max_vfs;
4873                 PMD_DRV_LOG(DEBUG,
4874                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4875                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4876         } else {
4877                 pf->vf_nb_qps = 0;
4878                 pf->vf_num = 0;
4879         }
4880         qp_count += pf->vf_nb_qps * pf->vf_num;
4881         vsi_count += pf->vf_num;
4882
4883         /* VMDq queue/VSI allocation */
4884         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4885         pf->vmdq_nb_qps = 0;
4886         pf->max_nb_vmdq_vsi = 0;
4887         if (hw->func_caps.vmdq) {
4888                 if (qp_count < hw->func_caps.num_tx_qp &&
4889                         vsi_count < hw->func_caps.num_vsis) {
4890                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4891                                 qp_count) / pf->vmdq_nb_qp_max;
4892
4893                         /* Limit the maximum number of VMDq vsi to the maximum
4894                          * ethdev can support
4895                          */
4896                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4897                                 hw->func_caps.num_vsis - vsi_count);
4898                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4899                                 ETH_64_POOLS);
4900                         if (pf->max_nb_vmdq_vsi) {
4901                                 pf->flags |= I40E_FLAG_VMDQ;
4902                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4903                                 PMD_DRV_LOG(DEBUG,
4904                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4905                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4906                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4907                         } else {
4908                                 PMD_DRV_LOG(INFO,
4909                                         "No enough queues left for VMDq");
4910                         }
4911                 } else {
4912                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4913                 }
4914         }
4915         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4916         vsi_count += pf->max_nb_vmdq_vsi;
4917
4918         if (hw->func_caps.dcb)
4919                 pf->flags |= I40E_FLAG_DCB;
4920
4921         if (qp_count > hw->func_caps.num_tx_qp) {
4922                 PMD_DRV_LOG(ERR,
4923                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4924                         qp_count, hw->func_caps.num_tx_qp);
4925                 return -EINVAL;
4926         }
4927         if (vsi_count > hw->func_caps.num_vsis) {
4928                 PMD_DRV_LOG(ERR,
4929                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4930                         vsi_count, hw->func_caps.num_vsis);
4931                 return -EINVAL;
4932         }
4933
4934         return 0;
4935 }
4936
4937 static int
4938 i40e_pf_get_switch_config(struct i40e_pf *pf)
4939 {
4940         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4941         struct i40e_aqc_get_switch_config_resp *switch_config;
4942         struct i40e_aqc_switch_config_element_resp *element;
4943         uint16_t start_seid = 0, num_reported;
4944         int ret;
4945
4946         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4947                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4948         if (!switch_config) {
4949                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4950                 return -ENOMEM;
4951         }
4952
4953         /* Get the switch configurations */
4954         ret = i40e_aq_get_switch_config(hw, switch_config,
4955                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4956         if (ret != I40E_SUCCESS) {
4957                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4958                 goto fail;
4959         }
4960         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4961         if (num_reported != 1) { /* The number should be 1 */
4962                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4963                 goto fail;
4964         }
4965
4966         /* Parse the switch configuration elements */
4967         element = &(switch_config->element[0]);
4968         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4969                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4970                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4971         } else
4972                 PMD_DRV_LOG(INFO, "Unknown element type");
4973
4974 fail:
4975         rte_free(switch_config);
4976
4977         return ret;
4978 }
4979
4980 static int
4981 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4982                         uint32_t num)
4983 {
4984         struct pool_entry *entry;
4985
4986         if (pool == NULL || num == 0)
4987                 return -EINVAL;
4988
4989         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4990         if (entry == NULL) {
4991                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4992                 return -ENOMEM;
4993         }
4994
4995         /* queue heap initialize */
4996         pool->num_free = num;
4997         pool->num_alloc = 0;
4998         pool->base = base;
4999         LIST_INIT(&pool->alloc_list);
5000         LIST_INIT(&pool->free_list);
5001
5002         /* Initialize element  */
5003         entry->base = 0;
5004         entry->len = num;
5005
5006         LIST_INSERT_HEAD(&pool->free_list, entry, next);
5007         return 0;
5008 }
5009
5010 static void
5011 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5012 {
5013         struct pool_entry *entry, *next_entry;
5014
5015         if (pool == NULL)
5016                 return;
5017
5018         for (entry = LIST_FIRST(&pool->alloc_list);
5019                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5020                         entry = next_entry) {
5021                 LIST_REMOVE(entry, next);
5022                 rte_free(entry);
5023         }
5024
5025         for (entry = LIST_FIRST(&pool->free_list);
5026                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5027                         entry = next_entry) {
5028                 LIST_REMOVE(entry, next);
5029                 rte_free(entry);
5030         }
5031
5032         pool->num_free = 0;
5033         pool->num_alloc = 0;
5034         pool->base = 0;
5035         LIST_INIT(&pool->alloc_list);
5036         LIST_INIT(&pool->free_list);
5037 }
5038
5039 static int
5040 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5041                        uint32_t base)
5042 {
5043         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5044         uint32_t pool_offset;
5045         uint16_t len;
5046         int insert;
5047
5048         if (pool == NULL) {
5049                 PMD_DRV_LOG(ERR, "Invalid parameter");
5050                 return -EINVAL;
5051         }
5052
5053         pool_offset = base - pool->base;
5054         /* Lookup in alloc list */
5055         LIST_FOREACH(entry, &pool->alloc_list, next) {
5056                 if (entry->base == pool_offset) {
5057                         valid_entry = entry;
5058                         LIST_REMOVE(entry, next);
5059                         break;
5060                 }
5061         }
5062
5063         /* Not find, return */
5064         if (valid_entry == NULL) {
5065                 PMD_DRV_LOG(ERR, "Failed to find entry");
5066                 return -EINVAL;
5067         }
5068
5069         /**
5070          * Found it, move it to free list  and try to merge.
5071          * In order to make merge easier, always sort it by qbase.
5072          * Find adjacent prev and last entries.
5073          */
5074         prev = next = NULL;
5075         LIST_FOREACH(entry, &pool->free_list, next) {
5076                 if (entry->base > valid_entry->base) {
5077                         next = entry;
5078                         break;
5079                 }
5080                 prev = entry;
5081         }
5082
5083         insert = 0;
5084         len = valid_entry->len;
5085         /* Try to merge with next one*/
5086         if (next != NULL) {
5087                 /* Merge with next one */
5088                 if (valid_entry->base + len == next->base) {
5089                         next->base = valid_entry->base;
5090                         next->len += len;
5091                         rte_free(valid_entry);
5092                         valid_entry = next;
5093                         insert = 1;
5094                 }
5095         }
5096
5097         if (prev != NULL) {
5098                 /* Merge with previous one */
5099                 if (prev->base + prev->len == valid_entry->base) {
5100                         prev->len += len;
5101                         /* If it merge with next one, remove next node */
5102                         if (insert == 1) {
5103                                 LIST_REMOVE(valid_entry, next);
5104                                 rte_free(valid_entry);
5105                                 valid_entry = NULL;
5106                         } else {
5107                                 rte_free(valid_entry);
5108                                 valid_entry = NULL;
5109                                 insert = 1;
5110                         }
5111                 }
5112         }
5113
5114         /* Not find any entry to merge, insert */
5115         if (insert == 0) {
5116                 if (prev != NULL)
5117                         LIST_INSERT_AFTER(prev, valid_entry, next);
5118                 else if (next != NULL)
5119                         LIST_INSERT_BEFORE(next, valid_entry, next);
5120                 else /* It's empty list, insert to head */
5121                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5122         }
5123
5124         pool->num_free += len;
5125         pool->num_alloc -= len;
5126
5127         return 0;
5128 }
5129
5130 static int
5131 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5132                        uint16_t num)
5133 {
5134         struct pool_entry *entry, *valid_entry;
5135
5136         if (pool == NULL || num == 0) {
5137                 PMD_DRV_LOG(ERR, "Invalid parameter");
5138                 return -EINVAL;
5139         }
5140
5141         if (pool->num_free < num) {
5142                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5143                             num, pool->num_free);
5144                 return -ENOMEM;
5145         }
5146
5147         valid_entry = NULL;
5148         /* Lookup  in free list and find most fit one */
5149         LIST_FOREACH(entry, &pool->free_list, next) {
5150                 if (entry->len >= num) {
5151                         /* Find best one */
5152                         if (entry->len == num) {
5153                                 valid_entry = entry;
5154                                 break;
5155                         }
5156                         if (valid_entry == NULL || valid_entry->len > entry->len)
5157                                 valid_entry = entry;
5158                 }
5159         }
5160
5161         /* Not find one to satisfy the request, return */
5162         if (valid_entry == NULL) {
5163                 PMD_DRV_LOG(ERR, "No valid entry found");
5164                 return -ENOMEM;
5165         }
5166         /**
5167          * The entry have equal queue number as requested,
5168          * remove it from alloc_list.
5169          */
5170         if (valid_entry->len == num) {
5171                 LIST_REMOVE(valid_entry, next);
5172         } else {
5173                 /**
5174                  * The entry have more numbers than requested,
5175                  * create a new entry for alloc_list and minus its
5176                  * queue base and number in free_list.
5177                  */
5178                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5179                 if (entry == NULL) {
5180                         PMD_DRV_LOG(ERR,
5181                                 "Failed to allocate memory for resource pool");
5182                         return -ENOMEM;
5183                 }
5184                 entry->base = valid_entry->base;
5185                 entry->len = num;
5186                 valid_entry->base += num;
5187                 valid_entry->len -= num;
5188                 valid_entry = entry;
5189         }
5190
5191         /* Insert it into alloc list, not sorted */
5192         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5193
5194         pool->num_free -= valid_entry->len;
5195         pool->num_alloc += valid_entry->len;
5196
5197         return valid_entry->base + pool->base;
5198 }
5199
5200 /**
5201  * bitmap_is_subset - Check whether src2 is subset of src1
5202  **/
5203 static inline int
5204 bitmap_is_subset(uint8_t src1, uint8_t src2)
5205 {
5206         return !((src1 ^ src2) & src2);
5207 }
5208
5209 static enum i40e_status_code
5210 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5211 {
5212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5213
5214         /* If DCB is not supported, only default TC is supported */
5215         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5216                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5217                 return I40E_NOT_SUPPORTED;
5218         }
5219
5220         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5221                 PMD_DRV_LOG(ERR,
5222                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5223                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5224                 return I40E_NOT_SUPPORTED;
5225         }
5226         return I40E_SUCCESS;
5227 }
5228
5229 int
5230 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5231                                 struct i40e_vsi_vlan_pvid_info *info)
5232 {
5233         struct i40e_hw *hw;
5234         struct i40e_vsi_context ctxt;
5235         uint8_t vlan_flags = 0;
5236         int ret;
5237
5238         if (vsi == NULL || info == NULL) {
5239                 PMD_DRV_LOG(ERR, "invalid parameters");
5240                 return I40E_ERR_PARAM;
5241         }
5242
5243         if (info->on) {
5244                 vsi->info.pvid = info->config.pvid;
5245                 /**
5246                  * If insert pvid is enabled, only tagged pkts are
5247                  * allowed to be sent out.
5248                  */
5249                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5250                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5251         } else {
5252                 vsi->info.pvid = 0;
5253                 if (info->config.reject.tagged == 0)
5254                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5255
5256                 if (info->config.reject.untagged == 0)
5257                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5258         }
5259         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5260                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5261         vsi->info.port_vlan_flags |= vlan_flags;
5262         vsi->info.valid_sections =
5263                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5264         memset(&ctxt, 0, sizeof(ctxt));
5265         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5266         ctxt.seid = vsi->seid;
5267
5268         hw = I40E_VSI_TO_HW(vsi);
5269         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5270         if (ret != I40E_SUCCESS)
5271                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5272
5273         return ret;
5274 }
5275
5276 static int
5277 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5278 {
5279         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5280         int i, ret;
5281         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5282
5283         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5284         if (ret != I40E_SUCCESS)
5285                 return ret;
5286
5287         if (!vsi->seid) {
5288                 PMD_DRV_LOG(ERR, "seid not valid");
5289                 return -EINVAL;
5290         }
5291
5292         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5293         tc_bw_data.tc_valid_bits = enabled_tcmap;
5294         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5295                 tc_bw_data.tc_bw_credits[i] =
5296                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5297
5298         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5299         if (ret != I40E_SUCCESS) {
5300                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5301                 return ret;
5302         }
5303
5304         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5305                                         sizeof(vsi->info.qs_handle));
5306         return I40E_SUCCESS;
5307 }
5308
5309 static enum i40e_status_code
5310 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5311                                  struct i40e_aqc_vsi_properties_data *info,
5312                                  uint8_t enabled_tcmap)
5313 {
5314         enum i40e_status_code ret;
5315         int i, total_tc = 0;
5316         uint16_t qpnum_per_tc, bsf, qp_idx;
5317
5318         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5319         if (ret != I40E_SUCCESS)
5320                 return ret;
5321
5322         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5323                 if (enabled_tcmap & (1 << i))
5324                         total_tc++;
5325         if (total_tc == 0)
5326                 total_tc = 1;
5327         vsi->enabled_tc = enabled_tcmap;
5328
5329         /* Number of queues per enabled TC */
5330         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5331         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5332         bsf = rte_bsf32(qpnum_per_tc);
5333
5334         /* Adjust the queue number to actual queues that can be applied */
5335         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5336                 vsi->nb_qps = qpnum_per_tc * total_tc;
5337
5338         /**
5339          * Configure TC and queue mapping parameters, for enabled TC,
5340          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5341          * default queue will serve it.
5342          */
5343         qp_idx = 0;
5344         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5345                 if (vsi->enabled_tc & (1 << i)) {
5346                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5347                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5348                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5349                         qp_idx += qpnum_per_tc;
5350                 } else
5351                         info->tc_mapping[i] = 0;
5352         }
5353
5354         /* Associate queue number with VSI */
5355         if (vsi->type == I40E_VSI_SRIOV) {
5356                 info->mapping_flags |=
5357                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5358                 for (i = 0; i < vsi->nb_qps; i++)
5359                         info->queue_mapping[i] =
5360                                 rte_cpu_to_le_16(vsi->base_queue + i);
5361         } else {
5362                 info->mapping_flags |=
5363                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5364                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5365         }
5366         info->valid_sections |=
5367                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5368
5369         return I40E_SUCCESS;
5370 }
5371
5372 static int
5373 i40e_veb_release(struct i40e_veb *veb)
5374 {
5375         struct i40e_vsi *vsi;
5376         struct i40e_hw *hw;
5377
5378         if (veb == NULL)
5379                 return -EINVAL;
5380
5381         if (!TAILQ_EMPTY(&veb->head)) {
5382                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5383                 return -EACCES;
5384         }
5385         /* associate_vsi field is NULL for floating VEB */
5386         if (veb->associate_vsi != NULL) {
5387                 vsi = veb->associate_vsi;
5388                 hw = I40E_VSI_TO_HW(vsi);
5389
5390                 vsi->uplink_seid = veb->uplink_seid;
5391                 vsi->veb = NULL;
5392         } else {
5393                 veb->associate_pf->main_vsi->floating_veb = NULL;
5394                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5395         }
5396
5397         i40e_aq_delete_element(hw, veb->seid, NULL);
5398         rte_free(veb);
5399         return I40E_SUCCESS;
5400 }
5401
5402 /* Setup a veb */
5403 static struct i40e_veb *
5404 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5405 {
5406         struct i40e_veb *veb;
5407         int ret;
5408         struct i40e_hw *hw;
5409
5410         if (pf == NULL) {
5411                 PMD_DRV_LOG(ERR,
5412                             "veb setup failed, associated PF shouldn't null");
5413                 return NULL;
5414         }
5415         hw = I40E_PF_TO_HW(pf);
5416
5417         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5418         if (!veb) {
5419                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5420                 goto fail;
5421         }
5422
5423         veb->associate_vsi = vsi;
5424         veb->associate_pf = pf;
5425         TAILQ_INIT(&veb->head);
5426         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5427
5428         /* create floating veb if vsi is NULL */
5429         if (vsi != NULL) {
5430                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5431                                       I40E_DEFAULT_TCMAP, false,
5432                                       &veb->seid, false, NULL);
5433         } else {
5434                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5435                                       true, &veb->seid, false, NULL);
5436         }
5437
5438         if (ret != I40E_SUCCESS) {
5439                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5440                             hw->aq.asq_last_status);
5441                 goto fail;
5442         }
5443         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5444
5445         /* get statistics index */
5446         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5447                                 &veb->stats_idx, NULL, NULL, NULL);
5448         if (ret != I40E_SUCCESS) {
5449                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5450                             hw->aq.asq_last_status);
5451                 goto fail;
5452         }
5453         /* Get VEB bandwidth, to be implemented */
5454         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5455         if (vsi)
5456                 vsi->uplink_seid = veb->seid;
5457
5458         return veb;
5459 fail:
5460         rte_free(veb);
5461         return NULL;
5462 }
5463
5464 int
5465 i40e_vsi_release(struct i40e_vsi *vsi)
5466 {
5467         struct i40e_pf *pf;
5468         struct i40e_hw *hw;
5469         struct i40e_vsi_list *vsi_list;
5470         void *temp;
5471         int ret;
5472         struct i40e_mac_filter *f;
5473         uint16_t user_param;
5474
5475         if (!vsi)
5476                 return I40E_SUCCESS;
5477
5478         if (!vsi->adapter)
5479                 return -EFAULT;
5480
5481         user_param = vsi->user_param;
5482
5483         pf = I40E_VSI_TO_PF(vsi);
5484         hw = I40E_VSI_TO_HW(vsi);
5485
5486         /* VSI has child to attach, release child first */
5487         if (vsi->veb) {
5488                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5489                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5490                                 return -1;
5491                 }
5492                 i40e_veb_release(vsi->veb);
5493         }
5494
5495         if (vsi->floating_veb) {
5496                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5497                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5498                                 return -1;
5499                 }
5500         }
5501
5502         /* Remove all macvlan filters of the VSI */
5503         i40e_vsi_remove_all_macvlan_filter(vsi);
5504         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5505                 rte_free(f);
5506
5507         if (vsi->type != I40E_VSI_MAIN &&
5508             ((vsi->type != I40E_VSI_SRIOV) ||
5509             !pf->floating_veb_list[user_param])) {
5510                 /* Remove vsi from parent's sibling list */
5511                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5512                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5513                         return I40E_ERR_PARAM;
5514                 }
5515                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5516                                 &vsi->sib_vsi_list, list);
5517
5518                 /* Remove all switch element of the VSI */
5519                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5520                 if (ret != I40E_SUCCESS)
5521                         PMD_DRV_LOG(ERR, "Failed to delete element");
5522         }
5523
5524         if ((vsi->type == I40E_VSI_SRIOV) &&
5525             pf->floating_veb_list[user_param]) {
5526                 /* Remove vsi from parent's sibling list */
5527                 if (vsi->parent_vsi == NULL ||
5528                     vsi->parent_vsi->floating_veb == NULL) {
5529                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5530                         return I40E_ERR_PARAM;
5531                 }
5532                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5533                              &vsi->sib_vsi_list, list);
5534
5535                 /* Remove all switch element of the VSI */
5536                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5537                 if (ret != I40E_SUCCESS)
5538                         PMD_DRV_LOG(ERR, "Failed to delete element");
5539         }
5540
5541         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5542
5543         if (vsi->type != I40E_VSI_SRIOV)
5544                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5545         rte_free(vsi);
5546
5547         return I40E_SUCCESS;
5548 }
5549
5550 static int
5551 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5552 {
5553         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5554         struct i40e_aqc_remove_macvlan_element_data def_filter;
5555         struct i40e_mac_filter_info filter;
5556         int ret;
5557
5558         if (vsi->type != I40E_VSI_MAIN)
5559                 return I40E_ERR_CONFIG;
5560         memset(&def_filter, 0, sizeof(def_filter));
5561         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5562                                         ETH_ADDR_LEN);
5563         def_filter.vlan_tag = 0;
5564         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5565                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5566         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5567         if (ret != I40E_SUCCESS) {
5568                 struct i40e_mac_filter *f;
5569                 struct rte_ether_addr *mac;
5570
5571                 PMD_DRV_LOG(DEBUG,
5572                             "Cannot remove the default macvlan filter");
5573                 /* It needs to add the permanent mac into mac list */
5574                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5575                 if (f == NULL) {
5576                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5577                         return I40E_ERR_NO_MEMORY;
5578                 }
5579                 mac = &f->mac_info.mac_addr;
5580                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5581                                 ETH_ADDR_LEN);
5582                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5583                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5584                 vsi->mac_num++;
5585
5586                 return ret;
5587         }
5588         rte_memcpy(&filter.mac_addr,
5589                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5590         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5591         return i40e_vsi_add_mac(vsi, &filter);
5592 }
5593
5594 /*
5595  * i40e_vsi_get_bw_config - Query VSI BW Information
5596  * @vsi: the VSI to be queried
5597  *
5598  * Returns 0 on success, negative value on failure
5599  */
5600 static enum i40e_status_code
5601 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5602 {
5603         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5604         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5605         struct i40e_hw *hw = &vsi->adapter->hw;
5606         i40e_status ret;
5607         int i;
5608         uint32_t bw_max;
5609
5610         memset(&bw_config, 0, sizeof(bw_config));
5611         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5612         if (ret != I40E_SUCCESS) {
5613                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5614                             hw->aq.asq_last_status);
5615                 return ret;
5616         }
5617
5618         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5619         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5620                                         &ets_sla_config, NULL);
5621         if (ret != I40E_SUCCESS) {
5622                 PMD_DRV_LOG(ERR,
5623                         "VSI failed to get TC bandwdith configuration %u",
5624                         hw->aq.asq_last_status);
5625                 return ret;
5626         }
5627
5628         /* store and print out BW info */
5629         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5630         vsi->bw_info.bw_max = bw_config.max_bw;
5631         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5632         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5633         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5634                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5635                      I40E_16_BIT_WIDTH);
5636         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5637                 vsi->bw_info.bw_ets_share_credits[i] =
5638                                 ets_sla_config.share_credits[i];
5639                 vsi->bw_info.bw_ets_credits[i] =
5640                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5641                 /* 4 bits per TC, 4th bit is reserved */
5642                 vsi->bw_info.bw_ets_max[i] =
5643                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5644                                   RTE_LEN2MASK(3, uint8_t));
5645                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5646                             vsi->bw_info.bw_ets_share_credits[i]);
5647                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5648                             vsi->bw_info.bw_ets_credits[i]);
5649                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5650                             vsi->bw_info.bw_ets_max[i]);
5651         }
5652
5653         return I40E_SUCCESS;
5654 }
5655
5656 /* i40e_enable_pf_lb
5657  * @pf: pointer to the pf structure
5658  *
5659  * allow loopback on pf
5660  */
5661 static inline void
5662 i40e_enable_pf_lb(struct i40e_pf *pf)
5663 {
5664         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5665         struct i40e_vsi_context ctxt;
5666         int ret;
5667
5668         /* Use the FW API if FW >= v5.0 */
5669         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5670                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5671                 return;
5672         }
5673
5674         memset(&ctxt, 0, sizeof(ctxt));
5675         ctxt.seid = pf->main_vsi_seid;
5676         ctxt.pf_num = hw->pf_id;
5677         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5678         if (ret) {
5679                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5680                             ret, hw->aq.asq_last_status);
5681                 return;
5682         }
5683         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5684         ctxt.info.valid_sections =
5685                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5686         ctxt.info.switch_id |=
5687                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5688
5689         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5690         if (ret)
5691                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5692                             hw->aq.asq_last_status);
5693 }
5694
5695 /* Setup a VSI */
5696 struct i40e_vsi *
5697 i40e_vsi_setup(struct i40e_pf *pf,
5698                enum i40e_vsi_type type,
5699                struct i40e_vsi *uplink_vsi,
5700                uint16_t user_param)
5701 {
5702         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5703         struct i40e_vsi *vsi;
5704         struct i40e_mac_filter_info filter;
5705         int ret;
5706         struct i40e_vsi_context ctxt;
5707         struct rte_ether_addr broadcast =
5708                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5709
5710         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5711             uplink_vsi == NULL) {
5712                 PMD_DRV_LOG(ERR,
5713                         "VSI setup failed, VSI link shouldn't be NULL");
5714                 return NULL;
5715         }
5716
5717         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5718                 PMD_DRV_LOG(ERR,
5719                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5720                 return NULL;
5721         }
5722
5723         /* two situations
5724          * 1.type is not MAIN and uplink vsi is not NULL
5725          * If uplink vsi didn't setup VEB, create one first under veb field
5726          * 2.type is SRIOV and the uplink is NULL
5727          * If floating VEB is NULL, create one veb under floating veb field
5728          */
5729
5730         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5731             uplink_vsi->veb == NULL) {
5732                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5733
5734                 if (uplink_vsi->veb == NULL) {
5735                         PMD_DRV_LOG(ERR, "VEB setup failed");
5736                         return NULL;
5737                 }
5738                 /* set ALLOWLOOPBACk on pf, when veb is created */
5739                 i40e_enable_pf_lb(pf);
5740         }
5741
5742         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5743             pf->main_vsi->floating_veb == NULL) {
5744                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5745
5746                 if (pf->main_vsi->floating_veb == NULL) {
5747                         PMD_DRV_LOG(ERR, "VEB setup failed");
5748                         return NULL;
5749                 }
5750         }
5751
5752         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5753         if (!vsi) {
5754                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5755                 return NULL;
5756         }
5757         TAILQ_INIT(&vsi->mac_list);
5758         vsi->type = type;
5759         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5760         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5761         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5762         vsi->user_param = user_param;
5763         vsi->vlan_anti_spoof_on = 0;
5764         vsi->vlan_filter_on = 0;
5765         /* Allocate queues */
5766         switch (vsi->type) {
5767         case I40E_VSI_MAIN  :
5768                 vsi->nb_qps = pf->lan_nb_qps;
5769                 break;
5770         case I40E_VSI_SRIOV :
5771                 vsi->nb_qps = pf->vf_nb_qps;
5772                 break;
5773         case I40E_VSI_VMDQ2:
5774                 vsi->nb_qps = pf->vmdq_nb_qps;
5775                 break;
5776         case I40E_VSI_FDIR:
5777                 vsi->nb_qps = pf->fdir_nb_qps;
5778                 break;
5779         default:
5780                 goto fail_mem;
5781         }
5782         /*
5783          * The filter status descriptor is reported in rx queue 0,
5784          * while the tx queue for fdir filter programming has no
5785          * such constraints, can be non-zero queues.
5786          * To simplify it, choose FDIR vsi use queue 0 pair.
5787          * To make sure it will use queue 0 pair, queue allocation
5788          * need be done before this function is called
5789          */
5790         if (type != I40E_VSI_FDIR) {
5791                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5792                         if (ret < 0) {
5793                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5794                                                 vsi->seid, ret);
5795                                 goto fail_mem;
5796                         }
5797                         vsi->base_queue = ret;
5798         } else
5799                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5800
5801         /* VF has MSIX interrupt in VF range, don't allocate here */
5802         if (type == I40E_VSI_MAIN) {
5803                 if (pf->support_multi_driver) {
5804                         /* If support multi-driver, need to use INT0 instead of
5805                          * allocating from msix pool. The Msix pool is init from
5806                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5807                          * to 1 without calling i40e_res_pool_alloc.
5808                          */
5809                         vsi->msix_intr = 0;
5810                         vsi->nb_msix = 1;
5811                 } else {
5812                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5813                                                   RTE_MIN(vsi->nb_qps,
5814                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5815                         if (ret < 0) {
5816                                 PMD_DRV_LOG(ERR,
5817                                             "VSI MAIN %d get heap failed %d",
5818                                             vsi->seid, ret);
5819                                 goto fail_queue_alloc;
5820                         }
5821                         vsi->msix_intr = ret;
5822                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5823                                                RTE_MAX_RXTX_INTR_VEC_ID);
5824                 }
5825         } else if (type != I40E_VSI_SRIOV) {
5826                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5827                 if (ret < 0) {
5828                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5829                         goto fail_queue_alloc;
5830                 }
5831                 vsi->msix_intr = ret;
5832                 vsi->nb_msix = 1;
5833         } else {
5834                 vsi->msix_intr = 0;
5835                 vsi->nb_msix = 0;
5836         }
5837
5838         /* Add VSI */
5839         if (type == I40E_VSI_MAIN) {
5840                 /* For main VSI, no need to add since it's default one */
5841                 vsi->uplink_seid = pf->mac_seid;
5842                 vsi->seid = pf->main_vsi_seid;
5843                 /* Bind queues with specific MSIX interrupt */
5844                 /**
5845                  * Needs 2 interrupt at least, one for misc cause which will
5846                  * enabled from OS side, Another for queues binding the
5847                  * interrupt from device side only.
5848                  */
5849
5850                 /* Get default VSI parameters from hardware */
5851                 memset(&ctxt, 0, sizeof(ctxt));
5852                 ctxt.seid = vsi->seid;
5853                 ctxt.pf_num = hw->pf_id;
5854                 ctxt.uplink_seid = vsi->uplink_seid;
5855                 ctxt.vf_num = 0;
5856                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5857                 if (ret != I40E_SUCCESS) {
5858                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5859                         goto fail_msix_alloc;
5860                 }
5861                 rte_memcpy(&vsi->info, &ctxt.info,
5862                         sizeof(struct i40e_aqc_vsi_properties_data));
5863                 vsi->vsi_id = ctxt.vsi_number;
5864                 vsi->info.valid_sections = 0;
5865
5866                 /* Configure tc, enabled TC0 only */
5867                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5868                         I40E_SUCCESS) {
5869                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5870                         goto fail_msix_alloc;
5871                 }
5872
5873                 /* TC, queue mapping */
5874                 memset(&ctxt, 0, sizeof(ctxt));
5875                 vsi->info.valid_sections |=
5876                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5877                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5878                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5879                 rte_memcpy(&ctxt.info, &vsi->info,
5880                         sizeof(struct i40e_aqc_vsi_properties_data));
5881                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5882                                                 I40E_DEFAULT_TCMAP);
5883                 if (ret != I40E_SUCCESS) {
5884                         PMD_DRV_LOG(ERR,
5885                                 "Failed to configure TC queue mapping");
5886                         goto fail_msix_alloc;
5887                 }
5888                 ctxt.seid = vsi->seid;
5889                 ctxt.pf_num = hw->pf_id;
5890                 ctxt.uplink_seid = vsi->uplink_seid;
5891                 ctxt.vf_num = 0;
5892
5893                 /* Update VSI parameters */
5894                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5895                 if (ret != I40E_SUCCESS) {
5896                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5897                         goto fail_msix_alloc;
5898                 }
5899
5900                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5901                                                 sizeof(vsi->info.tc_mapping));
5902                 rte_memcpy(&vsi->info.queue_mapping,
5903                                 &ctxt.info.queue_mapping,
5904                         sizeof(vsi->info.queue_mapping));
5905                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5906                 vsi->info.valid_sections = 0;
5907
5908                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5909                                 ETH_ADDR_LEN);
5910
5911                 /**
5912                  * Updating default filter settings are necessary to prevent
5913                  * reception of tagged packets.
5914                  * Some old firmware configurations load a default macvlan
5915                  * filter which accepts both tagged and untagged packets.
5916                  * The updating is to use a normal filter instead if needed.
5917                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5918                  * The firmware with correct configurations load the default
5919                  * macvlan filter which is expected and cannot be removed.
5920                  */
5921                 i40e_update_default_filter_setting(vsi);
5922                 i40e_config_qinq(hw, vsi);
5923         } else if (type == I40E_VSI_SRIOV) {
5924                 memset(&ctxt, 0, sizeof(ctxt));
5925                 /**
5926                  * For other VSI, the uplink_seid equals to uplink VSI's
5927                  * uplink_seid since they share same VEB
5928                  */
5929                 if (uplink_vsi == NULL)
5930                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5931                 else
5932                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5933                 ctxt.pf_num = hw->pf_id;
5934                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5935                 ctxt.uplink_seid = vsi->uplink_seid;
5936                 ctxt.connection_type = 0x1;
5937                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5938
5939                 /* Use the VEB configuration if FW >= v5.0 */
5940                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5941                         /* Configure switch ID */
5942                         ctxt.info.valid_sections |=
5943                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5944                         ctxt.info.switch_id =
5945                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5946                 }
5947
5948                 /* Configure port/vlan */
5949                 ctxt.info.valid_sections |=
5950                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5951                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5952                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5953                                                 hw->func_caps.enabled_tcmap);
5954                 if (ret != I40E_SUCCESS) {
5955                         PMD_DRV_LOG(ERR,
5956                                 "Failed to configure TC queue mapping");
5957                         goto fail_msix_alloc;
5958                 }
5959
5960                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5961                 ctxt.info.valid_sections |=
5962                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5963                 /**
5964                  * Since VSI is not created yet, only configure parameter,
5965                  * will add vsi below.
5966                  */
5967
5968                 i40e_config_qinq(hw, vsi);
5969         } else if (type == I40E_VSI_VMDQ2) {
5970                 memset(&ctxt, 0, sizeof(ctxt));
5971                 /*
5972                  * For other VSI, the uplink_seid equals to uplink VSI's
5973                  * uplink_seid since they share same VEB
5974                  */
5975                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5976                 ctxt.pf_num = hw->pf_id;
5977                 ctxt.vf_num = 0;
5978                 ctxt.uplink_seid = vsi->uplink_seid;
5979                 ctxt.connection_type = 0x1;
5980                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5981
5982                 ctxt.info.valid_sections |=
5983                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5984                 /* user_param carries flag to enable loop back */
5985                 if (user_param) {
5986                         ctxt.info.switch_id =
5987                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5988                         ctxt.info.switch_id |=
5989                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5990                 }
5991
5992                 /* Configure port/vlan */
5993                 ctxt.info.valid_sections |=
5994                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5995                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5996                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5997                                                 I40E_DEFAULT_TCMAP);
5998                 if (ret != I40E_SUCCESS) {
5999                         PMD_DRV_LOG(ERR,
6000                                 "Failed to configure TC queue mapping");
6001                         goto fail_msix_alloc;
6002                 }
6003                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6004                 ctxt.info.valid_sections |=
6005                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6006         } else if (type == I40E_VSI_FDIR) {
6007                 memset(&ctxt, 0, sizeof(ctxt));
6008                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6009                 ctxt.pf_num = hw->pf_id;
6010                 ctxt.vf_num = 0;
6011                 ctxt.uplink_seid = vsi->uplink_seid;
6012                 ctxt.connection_type = 0x1;     /* regular data port */
6013                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6014                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6015                                                 I40E_DEFAULT_TCMAP);
6016                 if (ret != I40E_SUCCESS) {
6017                         PMD_DRV_LOG(ERR,
6018                                 "Failed to configure TC queue mapping.");
6019                         goto fail_msix_alloc;
6020                 }
6021                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6022                 ctxt.info.valid_sections |=
6023                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6024         } else {
6025                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6026                 goto fail_msix_alloc;
6027         }
6028
6029         if (vsi->type != I40E_VSI_MAIN) {
6030                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6031                 if (ret != I40E_SUCCESS) {
6032                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6033                                     hw->aq.asq_last_status);
6034                         goto fail_msix_alloc;
6035                 }
6036                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6037                 vsi->info.valid_sections = 0;
6038                 vsi->seid = ctxt.seid;
6039                 vsi->vsi_id = ctxt.vsi_number;
6040                 vsi->sib_vsi_list.vsi = vsi;
6041                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6042                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6043                                           &vsi->sib_vsi_list, list);
6044                 } else {
6045                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6046                                           &vsi->sib_vsi_list, list);
6047                 }
6048         }
6049
6050         /* MAC/VLAN configuration */
6051         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6052         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6053
6054         ret = i40e_vsi_add_mac(vsi, &filter);
6055         if (ret != I40E_SUCCESS) {
6056                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6057                 goto fail_msix_alloc;
6058         }
6059
6060         /* Get VSI BW information */
6061         i40e_vsi_get_bw_config(vsi);
6062         return vsi;
6063 fail_msix_alloc:
6064         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6065 fail_queue_alloc:
6066         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6067 fail_mem:
6068         rte_free(vsi);
6069         return NULL;
6070 }
6071
6072 /* Configure vlan filter on or off */
6073 int
6074 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6075 {
6076         int i, num;
6077         struct i40e_mac_filter *f;
6078         void *temp;
6079         struct i40e_mac_filter_info *mac_filter;
6080         enum rte_mac_filter_type desired_filter;
6081         int ret = I40E_SUCCESS;
6082
6083         if (on) {
6084                 /* Filter to match MAC and VLAN */
6085                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6086         } else {
6087                 /* Filter to match only MAC */
6088                 desired_filter = RTE_MAC_PERFECT_MATCH;
6089         }
6090
6091         num = vsi->mac_num;
6092
6093         mac_filter = rte_zmalloc("mac_filter_info_data",
6094                                  num * sizeof(*mac_filter), 0);
6095         if (mac_filter == NULL) {
6096                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6097                 return I40E_ERR_NO_MEMORY;
6098         }
6099
6100         i = 0;
6101
6102         /* Remove all existing mac */
6103         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6104                 mac_filter[i] = f->mac_info;
6105                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6106                 if (ret) {
6107                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6108                                     on ? "enable" : "disable");
6109                         goto DONE;
6110                 }
6111                 i++;
6112         }
6113
6114         /* Override with new filter */
6115         for (i = 0; i < num; i++) {
6116                 mac_filter[i].filter_type = desired_filter;
6117                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6118                 if (ret) {
6119                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6120                                     on ? "enable" : "disable");
6121                         goto DONE;
6122                 }
6123         }
6124
6125 DONE:
6126         rte_free(mac_filter);
6127         return ret;
6128 }
6129
6130 /* Configure vlan stripping on or off */
6131 int
6132 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6133 {
6134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6135         struct i40e_vsi_context ctxt;
6136         uint8_t vlan_flags;
6137         int ret = I40E_SUCCESS;
6138
6139         /* Check if it has been already on or off */
6140         if (vsi->info.valid_sections &
6141                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6142                 if (on) {
6143                         if ((vsi->info.port_vlan_flags &
6144                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6145                                 return 0; /* already on */
6146                 } else {
6147                         if ((vsi->info.port_vlan_flags &
6148                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6149                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6150                                 return 0; /* already off */
6151                 }
6152         }
6153
6154         if (on)
6155                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6156         else
6157                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6158         vsi->info.valid_sections =
6159                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6160         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6161         vsi->info.port_vlan_flags |= vlan_flags;
6162         ctxt.seid = vsi->seid;
6163         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6164         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6165         if (ret)
6166                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6167                             on ? "enable" : "disable");
6168
6169         return ret;
6170 }
6171
6172 static int
6173 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6174 {
6175         struct rte_eth_dev_data *data = dev->data;
6176         int ret;
6177         int mask = 0;
6178
6179         /* Apply vlan offload setting */
6180         mask = ETH_VLAN_STRIP_MASK |
6181                ETH_VLAN_FILTER_MASK |
6182                ETH_VLAN_EXTEND_MASK;
6183         ret = i40e_vlan_offload_set(dev, mask);
6184         if (ret) {
6185                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6186                 return ret;
6187         }
6188
6189         /* Apply pvid setting */
6190         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6191                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6192         if (ret)
6193                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6194
6195         return ret;
6196 }
6197
6198 static int
6199 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6200 {
6201         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6202
6203         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6204 }
6205
6206 static int
6207 i40e_update_flow_control(struct i40e_hw *hw)
6208 {
6209 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6210         struct i40e_link_status link_status;
6211         uint32_t rxfc = 0, txfc = 0, reg;
6212         uint8_t an_info;
6213         int ret;
6214
6215         memset(&link_status, 0, sizeof(link_status));
6216         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6217         if (ret != I40E_SUCCESS) {
6218                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6219                 goto write_reg; /* Disable flow control */
6220         }
6221
6222         an_info = hw->phy.link_info.an_info;
6223         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6224                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6225                 ret = I40E_ERR_NOT_READY;
6226                 goto write_reg; /* Disable flow control */
6227         }
6228         /**
6229          * If link auto negotiation is enabled, flow control needs to
6230          * be configured according to it
6231          */
6232         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6233         case I40E_LINK_PAUSE_RXTX:
6234                 rxfc = 1;
6235                 txfc = 1;
6236                 hw->fc.current_mode = I40E_FC_FULL;
6237                 break;
6238         case I40E_AQ_LINK_PAUSE_RX:
6239                 rxfc = 1;
6240                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6241                 break;
6242         case I40E_AQ_LINK_PAUSE_TX:
6243                 txfc = 1;
6244                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6245                 break;
6246         default:
6247                 hw->fc.current_mode = I40E_FC_NONE;
6248                 break;
6249         }
6250
6251 write_reg:
6252         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6253                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6254         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6255         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6256         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6257         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6258
6259         return ret;
6260 }
6261
6262 /* PF setup */
6263 static int
6264 i40e_pf_setup(struct i40e_pf *pf)
6265 {
6266         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6267         struct i40e_filter_control_settings settings;
6268         struct i40e_vsi *vsi;
6269         int ret;
6270
6271         /* Clear all stats counters */
6272         pf->offset_loaded = FALSE;
6273         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6274         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6275         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6276         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6277
6278         ret = i40e_pf_get_switch_config(pf);
6279         if (ret != I40E_SUCCESS) {
6280                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6281                 return ret;
6282         }
6283
6284         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6285         if (ret)
6286                 PMD_INIT_LOG(WARNING,
6287                         "failed to allocate switch domain for device %d", ret);
6288
6289         if (pf->flags & I40E_FLAG_FDIR) {
6290                 /* make queue allocated first, let FDIR use queue pair 0*/
6291                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6292                 if (ret != I40E_FDIR_QUEUE_ID) {
6293                         PMD_DRV_LOG(ERR,
6294                                 "queue allocation fails for FDIR: ret =%d",
6295                                 ret);
6296                         pf->flags &= ~I40E_FLAG_FDIR;
6297                 }
6298         }
6299         /*  main VSI setup */
6300         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6301         if (!vsi) {
6302                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6303                 return I40E_ERR_NOT_READY;
6304         }
6305         pf->main_vsi = vsi;
6306
6307         /* Configure filter control */
6308         memset(&settings, 0, sizeof(settings));
6309         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6310                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6311         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6312                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6313         else {
6314                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6315                         hw->func_caps.rss_table_size);
6316                 return I40E_ERR_PARAM;
6317         }
6318         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6319                 hw->func_caps.rss_table_size);
6320         pf->hash_lut_size = hw->func_caps.rss_table_size;
6321
6322         /* Enable ethtype and macvlan filters */
6323         settings.enable_ethtype = TRUE;
6324         settings.enable_macvlan = TRUE;
6325         ret = i40e_set_filter_control(hw, &settings);
6326         if (ret)
6327                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6328                                                                 ret);
6329
6330         /* Update flow control according to the auto negotiation */
6331         i40e_update_flow_control(hw);
6332
6333         return I40E_SUCCESS;
6334 }
6335
6336 int
6337 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6338 {
6339         uint32_t reg;
6340         uint16_t j;
6341
6342         /**
6343          * Set or clear TX Queue Disable flags,
6344          * which is required by hardware.
6345          */
6346         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6347         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6348
6349         /* Wait until the request is finished */
6350         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6351                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6352                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6353                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6354                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6355                                                         & 0x1))) {
6356                         break;
6357                 }
6358         }
6359         if (on) {
6360                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6361                         return I40E_SUCCESS; /* already on, skip next steps */
6362
6363                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6364                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6365         } else {
6366                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6367                         return I40E_SUCCESS; /* already off, skip next steps */
6368                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6369         }
6370         /* Write the register */
6371         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6372         /* Check the result */
6373         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6374                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6375                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6376                 if (on) {
6377                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6378                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6379                                 break;
6380                 } else {
6381                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6382                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6383                                 break;
6384                 }
6385         }
6386         /* Check if it is timeout */
6387         if (j >= I40E_CHK_Q_ENA_COUNT) {
6388                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6389                             (on ? "enable" : "disable"), q_idx);
6390                 return I40E_ERR_TIMEOUT;
6391         }
6392
6393         return I40E_SUCCESS;
6394 }
6395
6396 int
6397 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6398 {
6399         uint32_t reg;
6400         uint16_t j;
6401
6402         /* Wait until the request is finished */
6403         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6404                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6405                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6406                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6407                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6408                         break;
6409         }
6410
6411         if (on) {
6412                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6413                         return I40E_SUCCESS; /* Already on, skip next steps */
6414                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6415         } else {
6416                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6417                         return I40E_SUCCESS; /* Already off, skip next steps */
6418                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6419         }
6420
6421         /* Write the register */
6422         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6423         /* Check the result */
6424         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6425                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6426                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6427                 if (on) {
6428                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6429                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6430                                 break;
6431                 } else {
6432                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6433                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6434                                 break;
6435                 }
6436         }
6437
6438         /* Check if it is timeout */
6439         if (j >= I40E_CHK_Q_ENA_COUNT) {
6440                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6441                             (on ? "enable" : "disable"), q_idx);
6442                 return I40E_ERR_TIMEOUT;
6443         }
6444
6445         return I40E_SUCCESS;
6446 }
6447
6448 /* Initialize VSI for TX */
6449 static int
6450 i40e_dev_tx_init(struct i40e_pf *pf)
6451 {
6452         struct rte_eth_dev_data *data = pf->dev_data;
6453         uint16_t i;
6454         uint32_t ret = I40E_SUCCESS;
6455         struct i40e_tx_queue *txq;
6456
6457         for (i = 0; i < data->nb_tx_queues; i++) {
6458                 txq = data->tx_queues[i];
6459                 if (!txq || !txq->q_set)
6460                         continue;
6461                 ret = i40e_tx_queue_init(txq);
6462                 if (ret != I40E_SUCCESS)
6463                         break;
6464         }
6465         if (ret == I40E_SUCCESS)
6466                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6467                                      ->eth_dev);
6468
6469         return ret;
6470 }
6471
6472 /* Initialize VSI for RX */
6473 static int
6474 i40e_dev_rx_init(struct i40e_pf *pf)
6475 {
6476         struct rte_eth_dev_data *data = pf->dev_data;
6477         int ret = I40E_SUCCESS;
6478         uint16_t i;
6479         struct i40e_rx_queue *rxq;
6480
6481         i40e_pf_config_mq_rx(pf);
6482         for (i = 0; i < data->nb_rx_queues; i++) {
6483                 rxq = data->rx_queues[i];
6484                 if (!rxq || !rxq->q_set)
6485                         continue;
6486
6487                 ret = i40e_rx_queue_init(rxq);
6488                 if (ret != I40E_SUCCESS) {
6489                         PMD_DRV_LOG(ERR,
6490                                 "Failed to do RX queue initialization");
6491                         break;
6492                 }
6493         }
6494         if (ret == I40E_SUCCESS)
6495                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6496                                      ->eth_dev);
6497
6498         return ret;
6499 }
6500
6501 static int
6502 i40e_dev_rxtx_init(struct i40e_pf *pf)
6503 {
6504         int err;
6505
6506         err = i40e_dev_tx_init(pf);
6507         if (err) {
6508                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6509                 return err;
6510         }
6511         err = i40e_dev_rx_init(pf);
6512         if (err) {
6513                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6514                 return err;
6515         }
6516
6517         return err;
6518 }
6519
6520 static int
6521 i40e_vmdq_setup(struct rte_eth_dev *dev)
6522 {
6523         struct rte_eth_conf *conf = &dev->data->dev_conf;
6524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6525         int i, err, conf_vsis, j, loop;
6526         struct i40e_vsi *vsi;
6527         struct i40e_vmdq_info *vmdq_info;
6528         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6529         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6530
6531         /*
6532          * Disable interrupt to avoid message from VF. Furthermore, it will
6533          * avoid race condition in VSI creation/destroy.
6534          */
6535         i40e_pf_disable_irq0(hw);
6536
6537         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6538                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6539                 return -ENOTSUP;
6540         }
6541
6542         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6543         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6544                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6545                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6546                         pf->max_nb_vmdq_vsi);
6547                 return -ENOTSUP;
6548         }
6549
6550         if (pf->vmdq != NULL) {
6551                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6552                 return 0;
6553         }
6554
6555         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6556                                 sizeof(*vmdq_info) * conf_vsis, 0);
6557
6558         if (pf->vmdq == NULL) {
6559                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6560                 return -ENOMEM;
6561         }
6562
6563         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6564
6565         /* Create VMDQ VSI */
6566         for (i = 0; i < conf_vsis; i++) {
6567                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6568                                 vmdq_conf->enable_loop_back);
6569                 if (vsi == NULL) {
6570                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6571                         err = -1;
6572                         goto err_vsi_setup;
6573                 }
6574                 vmdq_info = &pf->vmdq[i];
6575                 vmdq_info->pf = pf;
6576                 vmdq_info->vsi = vsi;
6577         }
6578         pf->nb_cfg_vmdq_vsi = conf_vsis;
6579
6580         /* Configure Vlan */
6581         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6582         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6583                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6584                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6585                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6586                                         vmdq_conf->pool_map[i].vlan_id, j);
6587
6588                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6589                                                 vmdq_conf->pool_map[i].vlan_id);
6590                                 if (err) {
6591                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6592                                         err = -1;
6593                                         goto err_vsi_setup;
6594                                 }
6595                         }
6596                 }
6597         }
6598
6599         i40e_pf_enable_irq0(hw);
6600
6601         return 0;
6602
6603 err_vsi_setup:
6604         for (i = 0; i < conf_vsis; i++)
6605                 if (pf->vmdq[i].vsi == NULL)
6606                         break;
6607                 else
6608                         i40e_vsi_release(pf->vmdq[i].vsi);
6609
6610         rte_free(pf->vmdq);
6611         pf->vmdq = NULL;
6612         i40e_pf_enable_irq0(hw);
6613         return err;
6614 }
6615
6616 static void
6617 i40e_stat_update_32(struct i40e_hw *hw,
6618                    uint32_t reg,
6619                    bool offset_loaded,
6620                    uint64_t *offset,
6621                    uint64_t *stat)
6622 {
6623         uint64_t new_data;
6624
6625         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6626         if (!offset_loaded)
6627                 *offset = new_data;
6628
6629         if (new_data >= *offset)
6630                 *stat = (uint64_t)(new_data - *offset);
6631         else
6632                 *stat = (uint64_t)((new_data +
6633                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6634 }
6635
6636 static void
6637 i40e_stat_update_48(struct i40e_hw *hw,
6638                    uint32_t hireg,
6639                    uint32_t loreg,
6640                    bool offset_loaded,
6641                    uint64_t *offset,
6642                    uint64_t *stat)
6643 {
6644         uint64_t new_data;
6645
6646         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6647         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6648                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6649
6650         if (!offset_loaded)
6651                 *offset = new_data;
6652
6653         if (new_data >= *offset)
6654                 *stat = new_data - *offset;
6655         else
6656                 *stat = (uint64_t)((new_data +
6657                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6658
6659         *stat &= I40E_48_BIT_MASK;
6660 }
6661
6662 /* Disable IRQ0 */
6663 void
6664 i40e_pf_disable_irq0(struct i40e_hw *hw)
6665 {
6666         /* Disable all interrupt types */
6667         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6668                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6669         I40E_WRITE_FLUSH(hw);
6670 }
6671
6672 /* Enable IRQ0 */
6673 void
6674 i40e_pf_enable_irq0(struct i40e_hw *hw)
6675 {
6676         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6677                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6678                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6679                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6680         I40E_WRITE_FLUSH(hw);
6681 }
6682
6683 static void
6684 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6685 {
6686         /* read pending request and disable first */
6687         i40e_pf_disable_irq0(hw);
6688         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6689         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6690                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6691
6692         if (no_queue)
6693                 /* Link no queues with irq0 */
6694                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6695                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6696 }
6697
6698 static void
6699 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6700 {
6701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6703         int i;
6704         uint16_t abs_vf_id;
6705         uint32_t index, offset, val;
6706
6707         if (!pf->vfs)
6708                 return;
6709         /**
6710          * Try to find which VF trigger a reset, use absolute VF id to access
6711          * since the reg is global register.
6712          */
6713         for (i = 0; i < pf->vf_num; i++) {
6714                 abs_vf_id = hw->func_caps.vf_base_id + i;
6715                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6716                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6717                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6718                 /* VFR event occurred */
6719                 if (val & (0x1 << offset)) {
6720                         int ret;
6721
6722                         /* Clear the event first */
6723                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6724                                                         (0x1 << offset));
6725                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6726                         /**
6727                          * Only notify a VF reset event occurred,
6728                          * don't trigger another SW reset
6729                          */
6730                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6731                         if (ret != I40E_SUCCESS)
6732                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6733                 }
6734         }
6735 }
6736
6737 static void
6738 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6739 {
6740         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6741         int i;
6742
6743         for (i = 0; i < pf->vf_num; i++)
6744                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6745 }
6746
6747 static void
6748 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6749 {
6750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751         struct i40e_arq_event_info info;
6752         uint16_t pending, opcode;
6753         int ret;
6754
6755         info.buf_len = I40E_AQ_BUF_SZ;
6756         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6757         if (!info.msg_buf) {
6758                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6759                 return;
6760         }
6761
6762         pending = 1;
6763         while (pending) {
6764                 ret = i40e_clean_arq_element(hw, &info, &pending);
6765
6766                 if (ret != I40E_SUCCESS) {
6767                         PMD_DRV_LOG(INFO,
6768                                 "Failed to read msg from AdminQ, aq_err: %u",
6769                                 hw->aq.asq_last_status);
6770                         break;
6771                 }
6772                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6773
6774                 switch (opcode) {
6775                 case i40e_aqc_opc_send_msg_to_pf:
6776                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6777                         i40e_pf_host_handle_vf_msg(dev,
6778                                         rte_le_to_cpu_16(info.desc.retval),
6779                                         rte_le_to_cpu_32(info.desc.cookie_high),
6780                                         rte_le_to_cpu_32(info.desc.cookie_low),
6781                                         info.msg_buf,
6782                                         info.msg_len);
6783                         break;
6784                 case i40e_aqc_opc_get_link_status:
6785                         ret = i40e_dev_link_update(dev, 0);
6786                         if (!ret)
6787                                 _rte_eth_dev_callback_process(dev,
6788                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6789                         break;
6790                 default:
6791                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6792                                     opcode);
6793                         break;
6794                 }
6795         }
6796         rte_free(info.msg_buf);
6797 }
6798
6799 static void
6800 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6801 {
6802 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6803 #define I40E_MDD_CLEAR16 0xFFFF
6804         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6806         bool mdd_detected = false;
6807         struct i40e_pf_vf *vf;
6808         uint32_t reg;
6809         int i;
6810
6811         /* find what triggered the MDD event */
6812         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6813         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6814                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6815                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6816                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6817                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6818                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6819                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6820                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6821                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6822                                         hw->func_caps.base_queue;
6823                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6824                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6825                                 event, queue, pf_num, vf_num, dev->data->name);
6826                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6827                 mdd_detected = true;
6828         }
6829         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6830         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6831                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6832                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6833                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6834                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6835                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6836                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6837                                         hw->func_caps.base_queue;
6838
6839                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6840                                 "queue %d of function 0x%02x device %s\n",
6841                                         event, queue, func, dev->data->name);
6842                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6843                 mdd_detected = true;
6844         }
6845
6846         if (mdd_detected) {
6847                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6848                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6849                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6850                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6851                 }
6852                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6853                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6854                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6855                                         I40E_MDD_CLEAR16);
6856                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6857                 }
6858         }
6859
6860         /* see if one of the VFs needs its hand slapped */
6861         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6862                 vf = &pf->vfs[i];
6863                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6864                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6865                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6866                                         I40E_MDD_CLEAR16);
6867                         vf->num_mdd_events++;
6868                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6869                                         PRIu64 "times\n",
6870                                         i, vf->num_mdd_events);
6871                 }
6872
6873                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6874                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6875                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6876                                         I40E_MDD_CLEAR16);
6877                         vf->num_mdd_events++;
6878                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6879                                         PRIu64 "times\n",
6880                                         i, vf->num_mdd_events);
6881                 }
6882         }
6883 }
6884
6885 /**
6886  * Interrupt handler triggered by NIC  for handling
6887  * specific interrupt.
6888  *
6889  * @param handle
6890  *  Pointer to interrupt handle.
6891  * @param param
6892  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6893  *
6894  * @return
6895  *  void
6896  */
6897 static void
6898 i40e_dev_interrupt_handler(void *param)
6899 {
6900         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6902         uint32_t icr0;
6903
6904         /* Disable interrupt */
6905         i40e_pf_disable_irq0(hw);
6906
6907         /* read out interrupt causes */
6908         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6909
6910         /* No interrupt event indicated */
6911         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6912                 PMD_DRV_LOG(INFO, "No interrupt event");
6913                 goto done;
6914         }
6915         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6916                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6917         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6918                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6919                 i40e_handle_mdd_event(dev);
6920         }
6921         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6922                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6923         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6924                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6925         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6926                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6927         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6928                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6929         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6930                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6931
6932         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6933                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6934                 i40e_dev_handle_vfr_event(dev);
6935         }
6936         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6937                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6938                 i40e_dev_handle_aq_msg(dev);
6939         }
6940
6941 done:
6942         /* Enable interrupt */
6943         i40e_pf_enable_irq0(hw);
6944 }
6945
6946 static void
6947 i40e_dev_alarm_handler(void *param)
6948 {
6949         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6951         uint32_t icr0;
6952
6953         /* Disable interrupt */
6954         i40e_pf_disable_irq0(hw);
6955
6956         /* read out interrupt causes */
6957         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6958
6959         /* No interrupt event indicated */
6960         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6961                 goto done;
6962         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6963                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6964         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6965                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6966                 i40e_handle_mdd_event(dev);
6967         }
6968         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6969                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6970         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6971                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6972         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6973                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6974         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6975                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6976         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6977                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6978
6979         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6980                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6981                 i40e_dev_handle_vfr_event(dev);
6982         }
6983         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6984                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6985                 i40e_dev_handle_aq_msg(dev);
6986         }
6987
6988 done:
6989         /* Enable interrupt */
6990         i40e_pf_enable_irq0(hw);
6991         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6992                           i40e_dev_alarm_handler, dev);
6993 }
6994
6995 int
6996 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6997                          struct i40e_macvlan_filter *filter,
6998                          int total)
6999 {
7000         int ele_num, ele_buff_size;
7001         int num, actual_num, i;
7002         uint16_t flags;
7003         int ret = I40E_SUCCESS;
7004         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7005         struct i40e_aqc_add_macvlan_element_data *req_list;
7006
7007         if (filter == NULL  || total == 0)
7008                 return I40E_ERR_PARAM;
7009         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7010         ele_buff_size = hw->aq.asq_buf_size;
7011
7012         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7013         if (req_list == NULL) {
7014                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7015                 return I40E_ERR_NO_MEMORY;
7016         }
7017
7018         num = 0;
7019         do {
7020                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7021                 memset(req_list, 0, ele_buff_size);
7022
7023                 for (i = 0; i < actual_num; i++) {
7024                         rte_memcpy(req_list[i].mac_addr,
7025                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7026                         req_list[i].vlan_tag =
7027                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7028
7029                         switch (filter[num + i].filter_type) {
7030                         case RTE_MAC_PERFECT_MATCH:
7031                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7032                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7033                                 break;
7034                         case RTE_MACVLAN_PERFECT_MATCH:
7035                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7036                                 break;
7037                         case RTE_MAC_HASH_MATCH:
7038                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7039                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7040                                 break;
7041                         case RTE_MACVLAN_HASH_MATCH:
7042                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7043                                 break;
7044                         default:
7045                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7046                                 ret = I40E_ERR_PARAM;
7047                                 goto DONE;
7048                         }
7049
7050                         req_list[i].queue_number = 0;
7051
7052                         req_list[i].flags = rte_cpu_to_le_16(flags);
7053                 }
7054
7055                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7056                                                 actual_num, NULL);
7057                 if (ret != I40E_SUCCESS) {
7058                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7059                         goto DONE;
7060                 }
7061                 num += actual_num;
7062         } while (num < total);
7063
7064 DONE:
7065         rte_free(req_list);
7066         return ret;
7067 }
7068
7069 int
7070 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7071                             struct i40e_macvlan_filter *filter,
7072                             int total)
7073 {
7074         int ele_num, ele_buff_size;
7075         int num, actual_num, i;
7076         uint16_t flags;
7077         int ret = I40E_SUCCESS;
7078         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7079         struct i40e_aqc_remove_macvlan_element_data *req_list;
7080
7081         if (filter == NULL  || total == 0)
7082                 return I40E_ERR_PARAM;
7083
7084         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7085         ele_buff_size = hw->aq.asq_buf_size;
7086
7087         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7088         if (req_list == NULL) {
7089                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7090                 return I40E_ERR_NO_MEMORY;
7091         }
7092
7093         num = 0;
7094         do {
7095                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7096                 memset(req_list, 0, ele_buff_size);
7097
7098                 for (i = 0; i < actual_num; i++) {
7099                         rte_memcpy(req_list[i].mac_addr,
7100                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7101                         req_list[i].vlan_tag =
7102                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7103
7104                         switch (filter[num + i].filter_type) {
7105                         case RTE_MAC_PERFECT_MATCH:
7106                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7107                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7108                                 break;
7109                         case RTE_MACVLAN_PERFECT_MATCH:
7110                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7111                                 break;
7112                         case RTE_MAC_HASH_MATCH:
7113                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7114                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7115                                 break;
7116                         case RTE_MACVLAN_HASH_MATCH:
7117                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7118                                 break;
7119                         default:
7120                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7121                                 ret = I40E_ERR_PARAM;
7122                                 goto DONE;
7123                         }
7124                         req_list[i].flags = rte_cpu_to_le_16(flags);
7125                 }
7126
7127                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7128                                                 actual_num, NULL);
7129                 if (ret != I40E_SUCCESS) {
7130                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7131                         goto DONE;
7132                 }
7133                 num += actual_num;
7134         } while (num < total);
7135
7136 DONE:
7137         rte_free(req_list);
7138         return ret;
7139 }
7140
7141 /* Find out specific MAC filter */
7142 static struct i40e_mac_filter *
7143 i40e_find_mac_filter(struct i40e_vsi *vsi,
7144                          struct rte_ether_addr *macaddr)
7145 {
7146         struct i40e_mac_filter *f;
7147
7148         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7149                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7150                         return f;
7151         }
7152
7153         return NULL;
7154 }
7155
7156 static bool
7157 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7158                          uint16_t vlan_id)
7159 {
7160         uint32_t vid_idx, vid_bit;
7161
7162         if (vlan_id > ETH_VLAN_ID_MAX)
7163                 return 0;
7164
7165         vid_idx = I40E_VFTA_IDX(vlan_id);
7166         vid_bit = I40E_VFTA_BIT(vlan_id);
7167
7168         if (vsi->vfta[vid_idx] & vid_bit)
7169                 return 1;
7170         else
7171                 return 0;
7172 }
7173
7174 static void
7175 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7176                        uint16_t vlan_id, bool on)
7177 {
7178         uint32_t vid_idx, vid_bit;
7179
7180         vid_idx = I40E_VFTA_IDX(vlan_id);
7181         vid_bit = I40E_VFTA_BIT(vlan_id);
7182
7183         if (on)
7184                 vsi->vfta[vid_idx] |= vid_bit;
7185         else
7186                 vsi->vfta[vid_idx] &= ~vid_bit;
7187 }
7188
7189 void
7190 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7191                      uint16_t vlan_id, bool on)
7192 {
7193         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7194         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7195         int ret;
7196
7197         if (vlan_id > ETH_VLAN_ID_MAX)
7198                 return;
7199
7200         i40e_store_vlan_filter(vsi, vlan_id, on);
7201
7202         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7203                 return;
7204
7205         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7206
7207         if (on) {
7208                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7209                                        &vlan_data, 1, NULL);
7210                 if (ret != I40E_SUCCESS)
7211                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7212         } else {
7213                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7214                                           &vlan_data, 1, NULL);
7215                 if (ret != I40E_SUCCESS)
7216                         PMD_DRV_LOG(ERR,
7217                                     "Failed to remove vlan filter");
7218         }
7219 }
7220
7221 /**
7222  * Find all vlan options for specific mac addr,
7223  * return with actual vlan found.
7224  */
7225 int
7226 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7227                            struct i40e_macvlan_filter *mv_f,
7228                            int num, struct rte_ether_addr *addr)
7229 {
7230         int i;
7231         uint32_t j, k;
7232
7233         /**
7234          * Not to use i40e_find_vlan_filter to decrease the loop time,
7235          * although the code looks complex.
7236           */
7237         if (num < vsi->vlan_num)
7238                 return I40E_ERR_PARAM;
7239
7240         i = 0;
7241         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7242                 if (vsi->vfta[j]) {
7243                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7244                                 if (vsi->vfta[j] & (1 << k)) {
7245                                         if (i > num - 1) {
7246                                                 PMD_DRV_LOG(ERR,
7247                                                         "vlan number doesn't match");
7248                                                 return I40E_ERR_PARAM;
7249                                         }
7250                                         rte_memcpy(&mv_f[i].macaddr,
7251                                                         addr, ETH_ADDR_LEN);
7252                                         mv_f[i].vlan_id =
7253                                                 j * I40E_UINT32_BIT_SIZE + k;
7254                                         i++;
7255                                 }
7256                         }
7257                 }
7258         }
7259         return I40E_SUCCESS;
7260 }
7261
7262 static inline int
7263 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7264                            struct i40e_macvlan_filter *mv_f,
7265                            int num,
7266                            uint16_t vlan)
7267 {
7268         int i = 0;
7269         struct i40e_mac_filter *f;
7270
7271         if (num < vsi->mac_num)
7272                 return I40E_ERR_PARAM;
7273
7274         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7275                 if (i > num - 1) {
7276                         PMD_DRV_LOG(ERR, "buffer number not match");
7277                         return I40E_ERR_PARAM;
7278                 }
7279                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7280                                 ETH_ADDR_LEN);
7281                 mv_f[i].vlan_id = vlan;
7282                 mv_f[i].filter_type = f->mac_info.filter_type;
7283                 i++;
7284         }
7285
7286         return I40E_SUCCESS;
7287 }
7288
7289 static int
7290 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7291 {
7292         int i, j, num;
7293         struct i40e_mac_filter *f;
7294         struct i40e_macvlan_filter *mv_f;
7295         int ret = I40E_SUCCESS;
7296
7297         if (vsi == NULL || vsi->mac_num == 0)
7298                 return I40E_ERR_PARAM;
7299
7300         /* Case that no vlan is set */
7301         if (vsi->vlan_num == 0)
7302                 num = vsi->mac_num;
7303         else
7304                 num = vsi->mac_num * vsi->vlan_num;
7305
7306         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7307         if (mv_f == NULL) {
7308                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7309                 return I40E_ERR_NO_MEMORY;
7310         }
7311
7312         i = 0;
7313         if (vsi->vlan_num == 0) {
7314                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7315                         rte_memcpy(&mv_f[i].macaddr,
7316                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7317                         mv_f[i].filter_type = f->mac_info.filter_type;
7318                         mv_f[i].vlan_id = 0;
7319                         i++;
7320                 }
7321         } else {
7322                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7323                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7324                                         vsi->vlan_num, &f->mac_info.mac_addr);
7325                         if (ret != I40E_SUCCESS)
7326                                 goto DONE;
7327                         for (j = i; j < i + vsi->vlan_num; j++)
7328                                 mv_f[j].filter_type = f->mac_info.filter_type;
7329                         i += vsi->vlan_num;
7330                 }
7331         }
7332
7333         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7334 DONE:
7335         rte_free(mv_f);
7336
7337         return ret;
7338 }
7339
7340 int
7341 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7342 {
7343         struct i40e_macvlan_filter *mv_f;
7344         int mac_num;
7345         int ret = I40E_SUCCESS;
7346
7347         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7348                 return I40E_ERR_PARAM;
7349
7350         /* If it's already set, just return */
7351         if (i40e_find_vlan_filter(vsi,vlan))
7352                 return I40E_SUCCESS;
7353
7354         mac_num = vsi->mac_num;
7355
7356         if (mac_num == 0) {
7357                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7358                 return I40E_ERR_PARAM;
7359         }
7360
7361         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7362
7363         if (mv_f == NULL) {
7364                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7365                 return I40E_ERR_NO_MEMORY;
7366         }
7367
7368         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7369
7370         if (ret != I40E_SUCCESS)
7371                 goto DONE;
7372
7373         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7374
7375         if (ret != I40E_SUCCESS)
7376                 goto DONE;
7377
7378         i40e_set_vlan_filter(vsi, vlan, 1);
7379
7380         vsi->vlan_num++;
7381         ret = I40E_SUCCESS;
7382 DONE:
7383         rte_free(mv_f);
7384         return ret;
7385 }
7386
7387 int
7388 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7389 {
7390         struct i40e_macvlan_filter *mv_f;
7391         int mac_num;
7392         int ret = I40E_SUCCESS;
7393
7394         /**
7395          * Vlan 0 is the generic filter for untagged packets
7396          * and can't be removed.
7397          */
7398         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7399                 return I40E_ERR_PARAM;
7400
7401         /* If can't find it, just return */
7402         if (!i40e_find_vlan_filter(vsi, vlan))
7403                 return I40E_ERR_PARAM;
7404
7405         mac_num = vsi->mac_num;
7406
7407         if (mac_num == 0) {
7408                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7409                 return I40E_ERR_PARAM;
7410         }
7411
7412         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7413
7414         if (mv_f == NULL) {
7415                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7416                 return I40E_ERR_NO_MEMORY;
7417         }
7418
7419         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7420
7421         if (ret != I40E_SUCCESS)
7422                 goto DONE;
7423
7424         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7425
7426         if (ret != I40E_SUCCESS)
7427                 goto DONE;
7428
7429         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7430         if (vsi->vlan_num == 1) {
7431                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7432                 if (ret != I40E_SUCCESS)
7433                         goto DONE;
7434
7435                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7436                 if (ret != I40E_SUCCESS)
7437                         goto DONE;
7438         }
7439
7440         i40e_set_vlan_filter(vsi, vlan, 0);
7441
7442         vsi->vlan_num--;
7443         ret = I40E_SUCCESS;
7444 DONE:
7445         rte_free(mv_f);
7446         return ret;
7447 }
7448
7449 int
7450 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7451 {
7452         struct i40e_mac_filter *f;
7453         struct i40e_macvlan_filter *mv_f;
7454         int i, vlan_num = 0;
7455         int ret = I40E_SUCCESS;
7456
7457         /* If it's add and we've config it, return */
7458         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7459         if (f != NULL)
7460                 return I40E_SUCCESS;
7461         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7462                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7463
7464                 /**
7465                  * If vlan_num is 0, that's the first time to add mac,
7466                  * set mask for vlan_id 0.
7467                  */
7468                 if (vsi->vlan_num == 0) {
7469                         i40e_set_vlan_filter(vsi, 0, 1);
7470                         vsi->vlan_num = 1;
7471                 }
7472                 vlan_num = vsi->vlan_num;
7473         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7474                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7475                 vlan_num = 1;
7476
7477         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7478         if (mv_f == NULL) {
7479                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7480                 return I40E_ERR_NO_MEMORY;
7481         }
7482
7483         for (i = 0; i < vlan_num; i++) {
7484                 mv_f[i].filter_type = mac_filter->filter_type;
7485                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7486                                 ETH_ADDR_LEN);
7487         }
7488
7489         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7490                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7491                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7492                                         &mac_filter->mac_addr);
7493                 if (ret != I40E_SUCCESS)
7494                         goto DONE;
7495         }
7496
7497         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7498         if (ret != I40E_SUCCESS)
7499                 goto DONE;
7500
7501         /* Add the mac addr into mac list */
7502         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7503         if (f == NULL) {
7504                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7505                 ret = I40E_ERR_NO_MEMORY;
7506                 goto DONE;
7507         }
7508         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7509                         ETH_ADDR_LEN);
7510         f->mac_info.filter_type = mac_filter->filter_type;
7511         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7512         vsi->mac_num++;
7513
7514         ret = I40E_SUCCESS;
7515 DONE:
7516         rte_free(mv_f);
7517
7518         return ret;
7519 }
7520
7521 int
7522 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7523 {
7524         struct i40e_mac_filter *f;
7525         struct i40e_macvlan_filter *mv_f;
7526         int i, vlan_num;
7527         enum rte_mac_filter_type filter_type;
7528         int ret = I40E_SUCCESS;
7529
7530         /* Can't find it, return an error */
7531         f = i40e_find_mac_filter(vsi, addr);
7532         if (f == NULL)
7533                 return I40E_ERR_PARAM;
7534
7535         vlan_num = vsi->vlan_num;
7536         filter_type = f->mac_info.filter_type;
7537         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7538                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7539                 if (vlan_num == 0) {
7540                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7541                         return I40E_ERR_PARAM;
7542                 }
7543         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7544                         filter_type == RTE_MAC_HASH_MATCH)
7545                 vlan_num = 1;
7546
7547         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7548         if (mv_f == NULL) {
7549                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7550                 return I40E_ERR_NO_MEMORY;
7551         }
7552
7553         for (i = 0; i < vlan_num; i++) {
7554                 mv_f[i].filter_type = filter_type;
7555                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7556                                 ETH_ADDR_LEN);
7557         }
7558         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7559                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7560                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7561                 if (ret != I40E_SUCCESS)
7562                         goto DONE;
7563         }
7564
7565         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7566         if (ret != I40E_SUCCESS)
7567                 goto DONE;
7568
7569         /* Remove the mac addr into mac list */
7570         TAILQ_REMOVE(&vsi->mac_list, f, next);
7571         rte_free(f);
7572         vsi->mac_num--;
7573
7574         ret = I40E_SUCCESS;
7575 DONE:
7576         rte_free(mv_f);
7577         return ret;
7578 }
7579
7580 /* Configure hash enable flags for RSS */
7581 uint64_t
7582 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7583 {
7584         uint64_t hena = 0;
7585         int i;
7586
7587         if (!flags)
7588                 return hena;
7589
7590         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7591                 if (flags & (1ULL << i))
7592                         hena |= adapter->pctypes_tbl[i];
7593         }
7594
7595         return hena;
7596 }
7597
7598 /* Parse the hash enable flags */
7599 uint64_t
7600 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7601 {
7602         uint64_t rss_hf = 0;
7603
7604         if (!flags)
7605                 return rss_hf;
7606         int i;
7607
7608         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7609                 if (flags & adapter->pctypes_tbl[i])
7610                         rss_hf |= (1ULL << i);
7611         }
7612         return rss_hf;
7613 }
7614
7615 /* Disable RSS */
7616 static void
7617 i40e_pf_disable_rss(struct i40e_pf *pf)
7618 {
7619         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7620
7621         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7622         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7623         I40E_WRITE_FLUSH(hw);
7624 }
7625
7626 int
7627 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7628 {
7629         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7630         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7631         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7632                            I40E_VFQF_HKEY_MAX_INDEX :
7633                            I40E_PFQF_HKEY_MAX_INDEX;
7634         int ret = 0;
7635
7636         if (!key || key_len == 0) {
7637                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7638                 return 0;
7639         } else if (key_len != (key_idx + 1) *
7640                 sizeof(uint32_t)) {
7641                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7642                 return -EINVAL;
7643         }
7644
7645         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7646                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7647                         (struct i40e_aqc_get_set_rss_key_data *)key;
7648
7649                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7650                 if (ret)
7651                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7652         } else {
7653                 uint32_t *hash_key = (uint32_t *)key;
7654                 uint16_t i;
7655
7656                 if (vsi->type == I40E_VSI_SRIOV) {
7657                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7658                                 I40E_WRITE_REG(
7659                                         hw,
7660                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7661                                         hash_key[i]);
7662
7663                 } else {
7664                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7665                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7666                                                hash_key[i]);
7667                 }
7668                 I40E_WRITE_FLUSH(hw);
7669         }
7670
7671         return ret;
7672 }
7673
7674 static int
7675 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7676 {
7677         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7679         uint32_t reg;
7680         int ret;
7681
7682         if (!key || !key_len)
7683                 return 0;
7684
7685         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7686                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7687                         (struct i40e_aqc_get_set_rss_key_data *)key);
7688                 if (ret) {
7689                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7690                         return ret;
7691                 }
7692         } else {
7693                 uint32_t *key_dw = (uint32_t *)key;
7694                 uint16_t i;
7695
7696                 if (vsi->type == I40E_VSI_SRIOV) {
7697                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7698                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7699                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7700                         }
7701                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7702                                    sizeof(uint32_t);
7703                 } else {
7704                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7705                                 reg = I40E_PFQF_HKEY(i);
7706                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7707                         }
7708                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7709                                    sizeof(uint32_t);
7710                 }
7711         }
7712         return 0;
7713 }
7714
7715 static int
7716 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7717 {
7718         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7719         uint64_t hena;
7720         int ret;
7721
7722         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7723                                rss_conf->rss_key_len);
7724         if (ret)
7725                 return ret;
7726
7727         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7728         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7729         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7730         I40E_WRITE_FLUSH(hw);
7731
7732         return 0;
7733 }
7734
7735 static int
7736 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7737                          struct rte_eth_rss_conf *rss_conf)
7738 {
7739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7740         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7741         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7742         uint64_t hena;
7743
7744         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7745         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7746
7747         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7748                 if (rss_hf != 0) /* Enable RSS */
7749                         return -EINVAL;
7750                 return 0; /* Nothing to do */
7751         }
7752         /* RSS enabled */
7753         if (rss_hf == 0) /* Disable RSS */
7754                 return -EINVAL;
7755
7756         return i40e_hw_rss_hash_set(pf, rss_conf);
7757 }
7758
7759 static int
7760 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7761                            struct rte_eth_rss_conf *rss_conf)
7762 {
7763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7764         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7765         uint64_t hena;
7766         int ret;
7767
7768         if (!rss_conf)
7769                 return -EINVAL;
7770
7771         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7772                          &rss_conf->rss_key_len);
7773         if (ret)
7774                 return ret;
7775
7776         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7777         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7778         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7779
7780         return 0;
7781 }
7782
7783 static int
7784 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7785 {
7786         switch (filter_type) {
7787         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7788                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7789                 break;
7790         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7791                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7792                 break;
7793         case RTE_TUNNEL_FILTER_IMAC_TENID:
7794                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7795                 break;
7796         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7797                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7798                 break;
7799         case ETH_TUNNEL_FILTER_IMAC:
7800                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7801                 break;
7802         case ETH_TUNNEL_FILTER_OIP:
7803                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7804                 break;
7805         case ETH_TUNNEL_FILTER_IIP:
7806                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7807                 break;
7808         default:
7809                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7810                 return -EINVAL;
7811         }
7812
7813         return 0;
7814 }
7815
7816 /* Convert tunnel filter structure */
7817 static int
7818 i40e_tunnel_filter_convert(
7819         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7820         struct i40e_tunnel_filter *tunnel_filter)
7821 {
7822         rte_ether_addr_copy((struct rte_ether_addr *)
7823                         &cld_filter->element.outer_mac,
7824                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7825         rte_ether_addr_copy((struct rte_ether_addr *)
7826                         &cld_filter->element.inner_mac,
7827                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7828         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7829         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7830              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7831             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7832                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7833         else
7834                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7835         tunnel_filter->input.flags = cld_filter->element.flags;
7836         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7837         tunnel_filter->queue = cld_filter->element.queue_number;
7838         rte_memcpy(tunnel_filter->input.general_fields,
7839                    cld_filter->general_fields,
7840                    sizeof(cld_filter->general_fields));
7841
7842         return 0;
7843 }
7844
7845 /* Check if there exists the tunnel filter */
7846 struct i40e_tunnel_filter *
7847 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7848                              const struct i40e_tunnel_filter_input *input)
7849 {
7850         int ret;
7851
7852         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7853         if (ret < 0)
7854                 return NULL;
7855
7856         return tunnel_rule->hash_map[ret];
7857 }
7858
7859 /* Add a tunnel filter into the SW list */
7860 static int
7861 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7862                              struct i40e_tunnel_filter *tunnel_filter)
7863 {
7864         struct i40e_tunnel_rule *rule = &pf->tunnel;
7865         int ret;
7866
7867         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7868         if (ret < 0) {
7869                 PMD_DRV_LOG(ERR,
7870                             "Failed to insert tunnel filter to hash table %d!",
7871                             ret);
7872                 return ret;
7873         }
7874         rule->hash_map[ret] = tunnel_filter;
7875
7876         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7877
7878         return 0;
7879 }
7880
7881 /* Delete a tunnel filter from the SW list */
7882 int
7883 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7884                           struct i40e_tunnel_filter_input *input)
7885 {
7886         struct i40e_tunnel_rule *rule = &pf->tunnel;
7887         struct i40e_tunnel_filter *tunnel_filter;
7888         int ret;
7889
7890         ret = rte_hash_del_key(rule->hash_table, input);
7891         if (ret < 0) {
7892                 PMD_DRV_LOG(ERR,
7893                             "Failed to delete tunnel filter to hash table %d!",
7894                             ret);
7895                 return ret;
7896         }
7897         tunnel_filter = rule->hash_map[ret];
7898         rule->hash_map[ret] = NULL;
7899
7900         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7901         rte_free(tunnel_filter);
7902
7903         return 0;
7904 }
7905
7906 int
7907 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7908                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7909                         uint8_t add)
7910 {
7911         uint16_t ip_type;
7912         uint32_t ipv4_addr, ipv4_addr_le;
7913         uint8_t i, tun_type = 0;
7914         /* internal varialbe to convert ipv6 byte order */
7915         uint32_t convert_ipv6[4];
7916         int val, ret = 0;
7917         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7918         struct i40e_vsi *vsi = pf->main_vsi;
7919         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7920         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7921         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7922         struct i40e_tunnel_filter *tunnel, *node;
7923         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7924
7925         cld_filter = rte_zmalloc("tunnel_filter",
7926                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7927         0);
7928
7929         if (NULL == cld_filter) {
7930                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7931                 return -ENOMEM;
7932         }
7933         pfilter = cld_filter;
7934
7935         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7936                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7937         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7938                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7939
7940         pfilter->element.inner_vlan =
7941                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7942         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7943                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7944                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7945                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7946                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7947                                 &ipv4_addr_le,
7948                                 sizeof(pfilter->element.ipaddr.v4.data));
7949         } else {
7950                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7951                 for (i = 0; i < 4; i++) {
7952                         convert_ipv6[i] =
7953                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7954                 }
7955                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7956                            &convert_ipv6,
7957                            sizeof(pfilter->element.ipaddr.v6.data));
7958         }
7959
7960         /* check tunneled type */
7961         switch (tunnel_filter->tunnel_type) {
7962         case RTE_TUNNEL_TYPE_VXLAN:
7963                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7964                 break;
7965         case RTE_TUNNEL_TYPE_NVGRE:
7966                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7967                 break;
7968         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7969                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7970                 break;
7971         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7972                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7973                 break;
7974         default:
7975                 /* Other tunnel types is not supported. */
7976                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7977                 rte_free(cld_filter);
7978                 return -EINVAL;
7979         }
7980
7981         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7982                                        &pfilter->element.flags);
7983         if (val < 0) {
7984                 rte_free(cld_filter);
7985                 return -EINVAL;
7986         }
7987
7988         pfilter->element.flags |= rte_cpu_to_le_16(
7989                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7990                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7991         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7992         pfilter->element.queue_number =
7993                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7994
7995         /* Check if there is the filter in SW list */
7996         memset(&check_filter, 0, sizeof(check_filter));
7997         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7998         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7999         if (add && node) {
8000                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8001                 rte_free(cld_filter);
8002                 return -EINVAL;
8003         }
8004
8005         if (!add && !node) {
8006                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8007                 rte_free(cld_filter);
8008                 return -EINVAL;
8009         }
8010
8011         if (add) {
8012                 ret = i40e_aq_add_cloud_filters(hw,
8013                                         vsi->seid, &cld_filter->element, 1);
8014                 if (ret < 0) {
8015                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8016                         rte_free(cld_filter);
8017                         return -ENOTSUP;
8018                 }
8019                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8020                 if (tunnel == NULL) {
8021                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8022                         rte_free(cld_filter);
8023                         return -ENOMEM;
8024                 }
8025
8026                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8027                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8028                 if (ret < 0)
8029                         rte_free(tunnel);
8030         } else {
8031                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8032                                                    &cld_filter->element, 1);
8033                 if (ret < 0) {
8034                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8035                         rte_free(cld_filter);
8036                         return -ENOTSUP;
8037                 }
8038                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8039         }
8040
8041         rte_free(cld_filter);
8042         return ret;
8043 }
8044
8045 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8046 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8047 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8048 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8049 #define I40E_TR_GRE_KEY_MASK                    0x400
8050 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8051 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8052 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8053 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8054 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8055 #define I40E_DIRECTION_INGRESS_KEY              0x8000
8056 #define I40E_TR_L4_TYPE_TCP                     0x2
8057 #define I40E_TR_L4_TYPE_UDP                     0x4
8058 #define I40E_TR_L4_TYPE_SCTP                    0x8
8059
8060 static enum
8061 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8062 {
8063         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8064         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8065         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8066         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8067         enum i40e_status_code status = I40E_SUCCESS;
8068
8069         if (pf->support_multi_driver) {
8070                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8071                 return I40E_NOT_SUPPORTED;
8072         }
8073
8074         memset(&filter_replace, 0,
8075                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8076         memset(&filter_replace_buf, 0,
8077                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8078
8079         /* create L1 filter */
8080         filter_replace.old_filter_type =
8081                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8082         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8083         filter_replace.tr_bit = 0;
8084
8085         /* Prepare the buffer, 3 entries */
8086         filter_replace_buf.data[0] =
8087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8088         filter_replace_buf.data[0] |=
8089                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8090         filter_replace_buf.data[2] = 0xFF;
8091         filter_replace_buf.data[3] = 0xFF;
8092         filter_replace_buf.data[4] =
8093                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8094         filter_replace_buf.data[4] |=
8095                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8096         filter_replace_buf.data[7] = 0xF0;
8097         filter_replace_buf.data[8]
8098                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8099         filter_replace_buf.data[8] |=
8100                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8101         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8102                 I40E_TR_GENEVE_KEY_MASK |
8103                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8104         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8105                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8106                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8107
8108         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8109                                                &filter_replace_buf);
8110         if (!status && (filter_replace.old_filter_type !=
8111                         filter_replace.new_filter_type))
8112                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8113                             " original: 0x%x, new: 0x%x",
8114                             dev->device->name,
8115                             filter_replace.old_filter_type,
8116                             filter_replace.new_filter_type);
8117
8118         return status;
8119 }
8120
8121 static enum
8122 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8123 {
8124         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8125         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8126         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8127         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8128         enum i40e_status_code status = I40E_SUCCESS;
8129
8130         if (pf->support_multi_driver) {
8131                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8132                 return I40E_NOT_SUPPORTED;
8133         }
8134
8135         /* For MPLSoUDP */
8136         memset(&filter_replace, 0,
8137                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8138         memset(&filter_replace_buf, 0,
8139                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8140         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8141                 I40E_AQC_MIRROR_CLOUD_FILTER;
8142         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8143         filter_replace.new_filter_type =
8144                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8145         /* Prepare the buffer, 2 entries */
8146         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8147         filter_replace_buf.data[0] |=
8148                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8149         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8150         filter_replace_buf.data[4] |=
8151                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8152         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8153                                                &filter_replace_buf);
8154         if (status < 0)
8155                 return status;
8156         if (filter_replace.old_filter_type !=
8157             filter_replace.new_filter_type)
8158                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8159                             " original: 0x%x, new: 0x%x",
8160                             dev->device->name,
8161                             filter_replace.old_filter_type,
8162                             filter_replace.new_filter_type);
8163
8164         /* For MPLSoGRE */
8165         memset(&filter_replace, 0,
8166                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8167         memset(&filter_replace_buf, 0,
8168                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8169
8170         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8171                 I40E_AQC_MIRROR_CLOUD_FILTER;
8172         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8173         filter_replace.new_filter_type =
8174                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8175         /* Prepare the buffer, 2 entries */
8176         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8177         filter_replace_buf.data[0] |=
8178                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8179         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8180         filter_replace_buf.data[4] |=
8181                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8182
8183         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8184                                                &filter_replace_buf);
8185         if (!status && (filter_replace.old_filter_type !=
8186                         filter_replace.new_filter_type))
8187                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8188                             " original: 0x%x, new: 0x%x",
8189                             dev->device->name,
8190                             filter_replace.old_filter_type,
8191                             filter_replace.new_filter_type);
8192
8193         return status;
8194 }
8195
8196 static enum i40e_status_code
8197 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8198 {
8199         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8200         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8201         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8202         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8203         enum i40e_status_code status = I40E_SUCCESS;
8204
8205         if (pf->support_multi_driver) {
8206                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8207                 return I40E_NOT_SUPPORTED;
8208         }
8209
8210         /* For GTP-C */
8211         memset(&filter_replace, 0,
8212                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8213         memset(&filter_replace_buf, 0,
8214                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8215         /* create L1 filter */
8216         filter_replace.old_filter_type =
8217                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8218         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8219         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8220                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8221         /* Prepare the buffer, 2 entries */
8222         filter_replace_buf.data[0] =
8223                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8224         filter_replace_buf.data[0] |=
8225                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8226         filter_replace_buf.data[2] = 0xFF;
8227         filter_replace_buf.data[3] = 0xFF;
8228         filter_replace_buf.data[4] =
8229                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8230         filter_replace_buf.data[4] |=
8231                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8232         filter_replace_buf.data[6] = 0xFF;
8233         filter_replace_buf.data[7] = 0xFF;
8234         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8235                                                &filter_replace_buf);
8236         if (status < 0)
8237                 return status;
8238         if (filter_replace.old_filter_type !=
8239             filter_replace.new_filter_type)
8240                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8241                             " original: 0x%x, new: 0x%x",
8242                             dev->device->name,
8243                             filter_replace.old_filter_type,
8244                             filter_replace.new_filter_type);
8245
8246         /* for GTP-U */
8247         memset(&filter_replace, 0,
8248                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8249         memset(&filter_replace_buf, 0,
8250                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8251         /* create L1 filter */
8252         filter_replace.old_filter_type =
8253                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8254         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8255         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8256                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8257         /* Prepare the buffer, 2 entries */
8258         filter_replace_buf.data[0] =
8259                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8260         filter_replace_buf.data[0] |=
8261                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8262         filter_replace_buf.data[2] = 0xFF;
8263         filter_replace_buf.data[3] = 0xFF;
8264         filter_replace_buf.data[4] =
8265                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8266         filter_replace_buf.data[4] |=
8267                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8268         filter_replace_buf.data[6] = 0xFF;
8269         filter_replace_buf.data[7] = 0xFF;
8270
8271         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8272                                                &filter_replace_buf);
8273         if (!status && (filter_replace.old_filter_type !=
8274                         filter_replace.new_filter_type))
8275                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8276                             " original: 0x%x, new: 0x%x",
8277                             dev->device->name,
8278                             filter_replace.old_filter_type,
8279                             filter_replace.new_filter_type);
8280
8281         return status;
8282 }
8283
8284 static enum
8285 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8286 {
8287         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8288         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8289         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8290         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8291         enum i40e_status_code status = I40E_SUCCESS;
8292
8293         if (pf->support_multi_driver) {
8294                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8295                 return I40E_NOT_SUPPORTED;
8296         }
8297
8298         /* for GTP-C */
8299         memset(&filter_replace, 0,
8300                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8301         memset(&filter_replace_buf, 0,
8302                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8303         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8304         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8305         filter_replace.new_filter_type =
8306                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8307         /* Prepare the buffer, 2 entries */
8308         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8309         filter_replace_buf.data[0] |=
8310                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8311         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8312         filter_replace_buf.data[4] |=
8313                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8314         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8315                                                &filter_replace_buf);
8316         if (status < 0)
8317                 return status;
8318         if (filter_replace.old_filter_type !=
8319             filter_replace.new_filter_type)
8320                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8321                             " original: 0x%x, new: 0x%x",
8322                             dev->device->name,
8323                             filter_replace.old_filter_type,
8324                             filter_replace.new_filter_type);
8325
8326         /* for GTP-U */
8327         memset(&filter_replace, 0,
8328                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8329         memset(&filter_replace_buf, 0,
8330                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8331         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8332         filter_replace.old_filter_type =
8333                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8334         filter_replace.new_filter_type =
8335                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8336         /* Prepare the buffer, 2 entries */
8337         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8338         filter_replace_buf.data[0] |=
8339                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8340         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8341         filter_replace_buf.data[4] |=
8342                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8343
8344         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8345                                                &filter_replace_buf);
8346         if (!status && (filter_replace.old_filter_type !=
8347                         filter_replace.new_filter_type))
8348                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8349                             " original: 0x%x, new: 0x%x",
8350                             dev->device->name,
8351                             filter_replace.old_filter_type,
8352                             filter_replace.new_filter_type);
8353
8354         return status;
8355 }
8356
8357 static enum i40e_status_code
8358 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8359                             enum i40e_l4_port_type l4_port_type)
8360 {
8361         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8362         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8363         enum i40e_status_code status = I40E_SUCCESS;
8364         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8365         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8366
8367         if (pf->support_multi_driver) {
8368                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8369                 return I40E_NOT_SUPPORTED;
8370         }
8371
8372         memset(&filter_replace, 0,
8373                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8374         memset(&filter_replace_buf, 0,
8375                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8376
8377         /* create L1 filter */
8378         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8379                 filter_replace.old_filter_type =
8380                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8381                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8382                 filter_replace_buf.data[8] =
8383                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8384         } else {
8385                 filter_replace.old_filter_type =
8386                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8387                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8388                 filter_replace_buf.data[8] =
8389                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8390         }
8391
8392         filter_replace.tr_bit = 0;
8393         /* Prepare the buffer, 3 entries */
8394         filter_replace_buf.data[0] =
8395                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8396         filter_replace_buf.data[0] |=
8397                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8398         filter_replace_buf.data[2] = 0x00;
8399         filter_replace_buf.data[3] =
8400                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8401         filter_replace_buf.data[4] =
8402                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8403         filter_replace_buf.data[4] |=
8404                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8405         filter_replace_buf.data[5] = 0x00;
8406         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8407                 I40E_TR_L4_TYPE_TCP |
8408                 I40E_TR_L4_TYPE_SCTP;
8409         filter_replace_buf.data[7] = 0x00;
8410         filter_replace_buf.data[8] |=
8411                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8412         filter_replace_buf.data[9] = 0x00;
8413         filter_replace_buf.data[10] = 0xFF;
8414         filter_replace_buf.data[11] = 0xFF;
8415
8416         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8417                                                &filter_replace_buf);
8418         if (!status && filter_replace.old_filter_type !=
8419             filter_replace.new_filter_type)
8420                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8421                             " original: 0x%x, new: 0x%x",
8422                             dev->device->name,
8423                             filter_replace.old_filter_type,
8424                             filter_replace.new_filter_type);
8425
8426         return status;
8427 }
8428
8429 static enum i40e_status_code
8430 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8431                                enum i40e_l4_port_type l4_port_type)
8432 {
8433         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8434         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8435         enum i40e_status_code status = I40E_SUCCESS;
8436         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8437         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8438
8439         if (pf->support_multi_driver) {
8440                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8441                 return I40E_NOT_SUPPORTED;
8442         }
8443
8444         memset(&filter_replace, 0,
8445                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8446         memset(&filter_replace_buf, 0,
8447                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8448
8449         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8450                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8451                 filter_replace.new_filter_type =
8452                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8453                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8454         } else {
8455                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8456                 filter_replace.new_filter_type =
8457                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8458                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8459         }
8460
8461         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8462         filter_replace.tr_bit = 0;
8463         /* Prepare the buffer, 2 entries */
8464         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8465         filter_replace_buf.data[0] |=
8466                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8467         filter_replace_buf.data[4] |=
8468                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8469         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8470                                                &filter_replace_buf);
8471
8472         if (!status && filter_replace.old_filter_type !=
8473             filter_replace.new_filter_type)
8474                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8475                             " original: 0x%x, new: 0x%x",
8476                             dev->device->name,
8477                             filter_replace.old_filter_type,
8478                             filter_replace.new_filter_type);
8479
8480         return status;
8481 }
8482
8483 int
8484 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8485                       struct i40e_tunnel_filter_conf *tunnel_filter,
8486                       uint8_t add)
8487 {
8488         uint16_t ip_type;
8489         uint32_t ipv4_addr, ipv4_addr_le;
8490         uint8_t i, tun_type = 0;
8491         /* internal variable to convert ipv6 byte order */
8492         uint32_t convert_ipv6[4];
8493         int val, ret = 0;
8494         struct i40e_pf_vf *vf = NULL;
8495         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8496         struct i40e_vsi *vsi;
8497         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8498         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8499         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8500         struct i40e_tunnel_filter *tunnel, *node;
8501         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8502         uint32_t teid_le;
8503         bool big_buffer = 0;
8504
8505         cld_filter = rte_zmalloc("tunnel_filter",
8506                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8507                          0);
8508
8509         if (cld_filter == NULL) {
8510                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8511                 return -ENOMEM;
8512         }
8513         pfilter = cld_filter;
8514
8515         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8516                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8517         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8518                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8519
8520         pfilter->element.inner_vlan =
8521                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8522         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8523                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8524                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8525                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8526                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8527                                 &ipv4_addr_le,
8528                                 sizeof(pfilter->element.ipaddr.v4.data));
8529         } else {
8530                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8531                 for (i = 0; i < 4; i++) {
8532                         convert_ipv6[i] =
8533                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8534                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8535                 }
8536                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8537                            &convert_ipv6,
8538                            sizeof(pfilter->element.ipaddr.v6.data));
8539         }
8540
8541         /* check tunneled type */
8542         switch (tunnel_filter->tunnel_type) {
8543         case I40E_TUNNEL_TYPE_VXLAN:
8544                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8545                 break;
8546         case I40E_TUNNEL_TYPE_NVGRE:
8547                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8548                 break;
8549         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8550                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8551                 break;
8552         case I40E_TUNNEL_TYPE_MPLSoUDP:
8553                 if (!pf->mpls_replace_flag) {
8554                         i40e_replace_mpls_l1_filter(pf);
8555                         i40e_replace_mpls_cloud_filter(pf);
8556                         pf->mpls_replace_flag = 1;
8557                 }
8558                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8559                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8560                         teid_le >> 4;
8561                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8562                         (teid_le & 0xF) << 12;
8563                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8564                         0x40;
8565                 big_buffer = 1;
8566                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8567                 break;
8568         case I40E_TUNNEL_TYPE_MPLSoGRE:
8569                 if (!pf->mpls_replace_flag) {
8570                         i40e_replace_mpls_l1_filter(pf);
8571                         i40e_replace_mpls_cloud_filter(pf);
8572                         pf->mpls_replace_flag = 1;
8573                 }
8574                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8575                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8576                         teid_le >> 4;
8577                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8578                         (teid_le & 0xF) << 12;
8579                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8580                         0x0;
8581                 big_buffer = 1;
8582                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8583                 break;
8584         case I40E_TUNNEL_TYPE_GTPC:
8585                 if (!pf->gtp_replace_flag) {
8586                         i40e_replace_gtp_l1_filter(pf);
8587                         i40e_replace_gtp_cloud_filter(pf);
8588                         pf->gtp_replace_flag = 1;
8589                 }
8590                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8591                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8592                         (teid_le >> 16) & 0xFFFF;
8593                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8594                         teid_le & 0xFFFF;
8595                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8596                         0x0;
8597                 big_buffer = 1;
8598                 break;
8599         case I40E_TUNNEL_TYPE_GTPU:
8600                 if (!pf->gtp_replace_flag) {
8601                         i40e_replace_gtp_l1_filter(pf);
8602                         i40e_replace_gtp_cloud_filter(pf);
8603                         pf->gtp_replace_flag = 1;
8604                 }
8605                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8606                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8607                         (teid_le >> 16) & 0xFFFF;
8608                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8609                         teid_le & 0xFFFF;
8610                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8611                         0x0;
8612                 big_buffer = 1;
8613                 break;
8614         case I40E_TUNNEL_TYPE_QINQ:
8615                 if (!pf->qinq_replace_flag) {
8616                         ret = i40e_cloud_filter_qinq_create(pf);
8617                         if (ret < 0)
8618                                 PMD_DRV_LOG(DEBUG,
8619                                             "QinQ tunnel filter already created.");
8620                         pf->qinq_replace_flag = 1;
8621                 }
8622                 /*      Add in the General fields the values of
8623                  *      the Outer and Inner VLAN
8624                  *      Big Buffer should be set, see changes in
8625                  *      i40e_aq_add_cloud_filters
8626                  */
8627                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8628                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8629                 big_buffer = 1;
8630                 break;
8631         case I40E_CLOUD_TYPE_UDP:
8632         case I40E_CLOUD_TYPE_TCP:
8633         case I40E_CLOUD_TYPE_SCTP:
8634                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8635                         if (!pf->sport_replace_flag) {
8636                                 i40e_replace_port_l1_filter(pf,
8637                                                 tunnel_filter->l4_port_type);
8638                                 i40e_replace_port_cloud_filter(pf,
8639                                                 tunnel_filter->l4_port_type);
8640                                 pf->sport_replace_flag = 1;
8641                         }
8642                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8643                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8644                                 I40E_DIRECTION_INGRESS_KEY;
8645
8646                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8647                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8648                                         I40E_TR_L4_TYPE_UDP;
8649                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8650                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8651                                         I40E_TR_L4_TYPE_TCP;
8652                         else
8653                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8654                                         I40E_TR_L4_TYPE_SCTP;
8655
8656                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8657                                 (teid_le >> 16) & 0xFFFF;
8658                         big_buffer = 1;
8659                 } else {
8660                         if (!pf->dport_replace_flag) {
8661                                 i40e_replace_port_l1_filter(pf,
8662                                                 tunnel_filter->l4_port_type);
8663                                 i40e_replace_port_cloud_filter(pf,
8664                                                 tunnel_filter->l4_port_type);
8665                                 pf->dport_replace_flag = 1;
8666                         }
8667                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8668                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8669                                 I40E_DIRECTION_INGRESS_KEY;
8670
8671                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8672                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8673                                         I40E_TR_L4_TYPE_UDP;
8674                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8675                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8676                                         I40E_TR_L4_TYPE_TCP;
8677                         else
8678                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8679                                         I40E_TR_L4_TYPE_SCTP;
8680
8681                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8682                                 (teid_le >> 16) & 0xFFFF;
8683                         big_buffer = 1;
8684                 }
8685
8686                 break;
8687         default:
8688                 /* Other tunnel types is not supported. */
8689                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8690                 rte_free(cld_filter);
8691                 return -EINVAL;
8692         }
8693
8694         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8695                 pfilter->element.flags =
8696                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8697         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8698                 pfilter->element.flags =
8699                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8700         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8701                 pfilter->element.flags =
8702                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8703         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8704                 pfilter->element.flags =
8705                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8706         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8707                 pfilter->element.flags |=
8708                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8709         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8710                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8711                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8712                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8713                         pfilter->element.flags |=
8714                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8715                 else
8716                         pfilter->element.flags |=
8717                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8718         } else {
8719                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8720                                                 &pfilter->element.flags);
8721                 if (val < 0) {
8722                         rte_free(cld_filter);
8723                         return -EINVAL;
8724                 }
8725         }
8726
8727         pfilter->element.flags |= rte_cpu_to_le_16(
8728                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8729                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8730         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8731         pfilter->element.queue_number =
8732                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8733
8734         if (!tunnel_filter->is_to_vf)
8735                 vsi = pf->main_vsi;
8736         else {
8737                 if (tunnel_filter->vf_id >= pf->vf_num) {
8738                         PMD_DRV_LOG(ERR, "Invalid argument.");
8739                         rte_free(cld_filter);
8740                         return -EINVAL;
8741                 }
8742                 vf = &pf->vfs[tunnel_filter->vf_id];
8743                 vsi = vf->vsi;
8744         }
8745
8746         /* Check if there is the filter in SW list */
8747         memset(&check_filter, 0, sizeof(check_filter));
8748         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8749         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8750         check_filter.vf_id = tunnel_filter->vf_id;
8751         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8752         if (add && node) {
8753                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8754                 rte_free(cld_filter);
8755                 return -EINVAL;
8756         }
8757
8758         if (!add && !node) {
8759                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8760                 rte_free(cld_filter);
8761                 return -EINVAL;
8762         }
8763
8764         if (add) {
8765                 if (big_buffer)
8766                         ret = i40e_aq_add_cloud_filters_bb(hw,
8767                                                    vsi->seid, cld_filter, 1);
8768                 else
8769                         ret = i40e_aq_add_cloud_filters(hw,
8770                                         vsi->seid, &cld_filter->element, 1);
8771                 if (ret < 0) {
8772                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8773                         rte_free(cld_filter);
8774                         return -ENOTSUP;
8775                 }
8776                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8777                 if (tunnel == NULL) {
8778                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8779                         rte_free(cld_filter);
8780                         return -ENOMEM;
8781                 }
8782
8783                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8784                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8785                 if (ret < 0)
8786                         rte_free(tunnel);
8787         } else {
8788                 if (big_buffer)
8789                         ret = i40e_aq_rem_cloud_filters_bb(
8790                                 hw, vsi->seid, cld_filter, 1);
8791                 else
8792                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8793                                                 &cld_filter->element, 1);
8794                 if (ret < 0) {
8795                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8796                         rte_free(cld_filter);
8797                         return -ENOTSUP;
8798                 }
8799                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8800         }
8801
8802         rte_free(cld_filter);
8803         return ret;
8804 }
8805
8806 static int
8807 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8808 {
8809         uint8_t i;
8810
8811         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8812                 if (pf->vxlan_ports[i] == port)
8813                         return i;
8814         }
8815
8816         return -1;
8817 }
8818
8819 static int
8820 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8821 {
8822         int  idx, ret;
8823         uint8_t filter_idx = 0;
8824         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8825
8826         idx = i40e_get_vxlan_port_idx(pf, port);
8827
8828         /* Check if port already exists */
8829         if (idx >= 0) {
8830                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8831                 return -EINVAL;
8832         }
8833
8834         /* Now check if there is space to add the new port */
8835         idx = i40e_get_vxlan_port_idx(pf, 0);
8836         if (idx < 0) {
8837                 PMD_DRV_LOG(ERR,
8838                         "Maximum number of UDP ports reached, not adding port %d",
8839                         port);
8840                 return -ENOSPC;
8841         }
8842
8843         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8844                                         &filter_idx, NULL);
8845         if (ret < 0) {
8846                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8847                 return -1;
8848         }
8849
8850         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8851                          port,  filter_idx);
8852
8853         /* New port: add it and mark its index in the bitmap */
8854         pf->vxlan_ports[idx] = port;
8855         pf->vxlan_bitmap |= (1 << idx);
8856
8857         if (!(pf->flags & I40E_FLAG_VXLAN))
8858                 pf->flags |= I40E_FLAG_VXLAN;
8859
8860         return 0;
8861 }
8862
8863 static int
8864 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8865 {
8866         int idx;
8867         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8868
8869         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8870                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8871                 return -EINVAL;
8872         }
8873
8874         idx = i40e_get_vxlan_port_idx(pf, port);
8875
8876         if (idx < 0) {
8877                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8878                 return -EINVAL;
8879         }
8880
8881         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8882                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8883                 return -1;
8884         }
8885
8886         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8887                         port, idx);
8888
8889         pf->vxlan_ports[idx] = 0;
8890         pf->vxlan_bitmap &= ~(1 << idx);
8891
8892         if (!pf->vxlan_bitmap)
8893                 pf->flags &= ~I40E_FLAG_VXLAN;
8894
8895         return 0;
8896 }
8897
8898 /* Add UDP tunneling port */
8899 static int
8900 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8901                              struct rte_eth_udp_tunnel *udp_tunnel)
8902 {
8903         int ret = 0;
8904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8905
8906         if (udp_tunnel == NULL)
8907                 return -EINVAL;
8908
8909         switch (udp_tunnel->prot_type) {
8910         case RTE_TUNNEL_TYPE_VXLAN:
8911                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8912                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8913                 break;
8914         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8915                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8916                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8917                 break;
8918         case RTE_TUNNEL_TYPE_GENEVE:
8919         case RTE_TUNNEL_TYPE_TEREDO:
8920                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8921                 ret = -1;
8922                 break;
8923
8924         default:
8925                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8926                 ret = -1;
8927                 break;
8928         }
8929
8930         return ret;
8931 }
8932
8933 /* Remove UDP tunneling port */
8934 static int
8935 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8936                              struct rte_eth_udp_tunnel *udp_tunnel)
8937 {
8938         int ret = 0;
8939         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8940
8941         if (udp_tunnel == NULL)
8942                 return -EINVAL;
8943
8944         switch (udp_tunnel->prot_type) {
8945         case RTE_TUNNEL_TYPE_VXLAN:
8946         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8947                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8948                 break;
8949         case RTE_TUNNEL_TYPE_GENEVE:
8950         case RTE_TUNNEL_TYPE_TEREDO:
8951                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8952                 ret = -1;
8953                 break;
8954         default:
8955                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8956                 ret = -1;
8957                 break;
8958         }
8959
8960         return ret;
8961 }
8962
8963 /* Calculate the maximum number of contiguous PF queues that are configured */
8964 static int
8965 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8966 {
8967         struct rte_eth_dev_data *data = pf->dev_data;
8968         int i, num;
8969         struct i40e_rx_queue *rxq;
8970
8971         num = 0;
8972         for (i = 0; i < pf->lan_nb_qps; i++) {
8973                 rxq = data->rx_queues[i];
8974                 if (rxq && rxq->q_set)
8975                         num++;
8976                 else
8977                         break;
8978         }
8979
8980         return num;
8981 }
8982
8983 /* Configure RSS */
8984 static int
8985 i40e_pf_config_rss(struct i40e_pf *pf)
8986 {
8987         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8988         struct rte_eth_rss_conf rss_conf;
8989         uint32_t i, lut = 0;
8990         uint16_t j, num;
8991
8992         /*
8993          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8994          * It's necessary to calculate the actual PF queues that are configured.
8995          */
8996         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8997                 num = i40e_pf_calc_configured_queues_num(pf);
8998         else
8999                 num = pf->dev_data->nb_rx_queues;
9000
9001         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9002         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9003                         num);
9004
9005         if (num == 0) {
9006                 PMD_INIT_LOG(ERR,
9007                         "No PF queues are configured to enable RSS for port %u",
9008                         pf->dev_data->port_id);
9009                 return -ENOTSUP;
9010         }
9011
9012         if (pf->adapter->rss_reta_updated == 0) {
9013                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9014                         if (j == num)
9015                                 j = 0;
9016                         lut = (lut << 8) | (j & ((0x1 <<
9017                                 hw->func_caps.rss_table_entry_width) - 1));
9018                         if ((i & 3) == 3)
9019                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9020                                                rte_bswap32(lut));
9021                 }
9022         }
9023
9024         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9025         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
9026                 i40e_pf_disable_rss(pf);
9027                 return 0;
9028         }
9029         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9030                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9031                 /* Random default keys */
9032                 static uint32_t rss_key_default[] = {0x6b793944,
9033                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9034                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9035                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9036
9037                 rss_conf.rss_key = (uint8_t *)rss_key_default;
9038                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9039                                                         sizeof(uint32_t);
9040         }
9041
9042         return i40e_hw_rss_hash_set(pf, &rss_conf);
9043 }
9044
9045 static int
9046 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9047                                struct rte_eth_tunnel_filter_conf *filter)
9048 {
9049         if (pf == NULL || filter == NULL) {
9050                 PMD_DRV_LOG(ERR, "Invalid parameter");
9051                 return -EINVAL;
9052         }
9053
9054         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9055                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9056                 return -EINVAL;
9057         }
9058
9059         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9060                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9061                 return -EINVAL;
9062         }
9063
9064         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9065                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9066                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9067                 return -EINVAL;
9068         }
9069
9070         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9071                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9072                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9073                 return -EINVAL;
9074         }
9075
9076         return 0;
9077 }
9078
9079 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9080 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9081 int
9082 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9083 {
9084         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9085         uint32_t val, reg;
9086         int ret = -EINVAL;
9087
9088         if (pf->support_multi_driver) {
9089                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9090                 return -ENOTSUP;
9091         }
9092
9093         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9094         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9095
9096         if (len == 3) {
9097                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9098         } else if (len == 4) {
9099                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9100         } else {
9101                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9102                 return ret;
9103         }
9104
9105         if (reg != val) {
9106                 ret = i40e_aq_debug_write_global_register(hw,
9107                                                    I40E_GL_PRS_FVBM(2),
9108                                                    reg, NULL);
9109                 if (ret != 0)
9110                         return ret;
9111                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9112                             "with value 0x%08x",
9113                             I40E_GL_PRS_FVBM(2), reg);
9114         } else {
9115                 ret = 0;
9116         }
9117         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9118                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9119
9120         return ret;
9121 }
9122
9123 static int
9124 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9125 {
9126         int ret = -EINVAL;
9127
9128         if (!hw || !cfg)
9129                 return -EINVAL;
9130
9131         switch (cfg->cfg_type) {
9132         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9133                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9134                 break;
9135         default:
9136                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9137                 break;
9138         }
9139
9140         return ret;
9141 }
9142
9143 static int
9144 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9145                                enum rte_filter_op filter_op,
9146                                void *arg)
9147 {
9148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9149         int ret = I40E_ERR_PARAM;
9150
9151         switch (filter_op) {
9152         case RTE_ETH_FILTER_SET:
9153                 ret = i40e_dev_global_config_set(hw,
9154                         (struct rte_eth_global_cfg *)arg);
9155                 break;
9156         default:
9157                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9158                 break;
9159         }
9160
9161         return ret;
9162 }
9163
9164 static int
9165 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9166                           enum rte_filter_op filter_op,
9167                           void *arg)
9168 {
9169         struct rte_eth_tunnel_filter_conf *filter;
9170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9171         int ret = I40E_SUCCESS;
9172
9173         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9174
9175         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9176                 return I40E_ERR_PARAM;
9177
9178         switch (filter_op) {
9179         case RTE_ETH_FILTER_NOP:
9180                 if (!(pf->flags & I40E_FLAG_VXLAN))
9181                         ret = I40E_NOT_SUPPORTED;
9182                 break;
9183         case RTE_ETH_FILTER_ADD:
9184                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9185                 break;
9186         case RTE_ETH_FILTER_DELETE:
9187                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9188                 break;
9189         default:
9190                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9191                 ret = I40E_ERR_PARAM;
9192                 break;
9193         }
9194
9195         return ret;
9196 }
9197
9198 static int
9199 i40e_pf_config_mq_rx(struct i40e_pf *pf)
9200 {
9201         int ret = 0;
9202         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9203
9204         /* RSS setup */
9205         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
9206                 ret = i40e_pf_config_rss(pf);
9207         else
9208                 i40e_pf_disable_rss(pf);
9209
9210         return ret;
9211 }
9212
9213 /* Get the symmetric hash enable configurations per port */
9214 static void
9215 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9216 {
9217         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9218
9219         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9220 }
9221
9222 /* Set the symmetric hash enable configurations per port */
9223 static void
9224 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9225 {
9226         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9227
9228         if (enable > 0) {
9229                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9230                         PMD_DRV_LOG(INFO,
9231                                 "Symmetric hash has already been enabled");
9232                         return;
9233                 }
9234                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9235         } else {
9236                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9237                         PMD_DRV_LOG(INFO,
9238                                 "Symmetric hash has already been disabled");
9239                         return;
9240                 }
9241                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9242         }
9243         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9244         I40E_WRITE_FLUSH(hw);
9245 }
9246
9247 /*
9248  * Get global configurations of hash function type and symmetric hash enable
9249  * per flow type (pctype). Note that global configuration means it affects all
9250  * the ports on the same NIC.
9251  */
9252 static int
9253 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9254                                    struct rte_eth_hash_global_conf *g_cfg)
9255 {
9256         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9257         uint32_t reg;
9258         uint16_t i, j;
9259
9260         memset(g_cfg, 0, sizeof(*g_cfg));
9261         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9262         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9263                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9264         else
9265                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9266         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9267                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9268
9269         /*
9270          * As i40e supports less than 64 flow types, only first 64 bits need to
9271          * be checked.
9272          */
9273         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9274                 g_cfg->valid_bit_mask[i] = 0ULL;
9275                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9276         }
9277
9278         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9279
9280         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9281                 if (!adapter->pctypes_tbl[i])
9282                         continue;
9283                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9284                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9285                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9286                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9287                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9288                                         g_cfg->sym_hash_enable_mask[0] |=
9289                                                                 (1ULL << i);
9290                                 }
9291                         }
9292                 }
9293         }
9294
9295         return 0;
9296 }
9297
9298 static int
9299 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9300                               const struct rte_eth_hash_global_conf *g_cfg)
9301 {
9302         uint32_t i;
9303         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9304
9305         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9306                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9307                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9308                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9309                                                 g_cfg->hash_func);
9310                 return -EINVAL;
9311         }
9312
9313         /*
9314          * As i40e supports less than 64 flow types, only first 64 bits need to
9315          * be checked.
9316          */
9317         mask0 = g_cfg->valid_bit_mask[0];
9318         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9319                 if (i == 0) {
9320                         /* Check if any unsupported flow type configured */
9321                         if ((mask0 | i40e_mask) ^ i40e_mask)
9322                                 goto mask_err;
9323                 } else {
9324                         if (g_cfg->valid_bit_mask[i])
9325                                 goto mask_err;
9326                 }
9327         }
9328
9329         return 0;
9330
9331 mask_err:
9332         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9333
9334         return -EINVAL;
9335 }
9336
9337 /*
9338  * Set global configurations of hash function type and symmetric hash enable
9339  * per flow type (pctype). Note any modifying global configuration will affect
9340  * all the ports on the same NIC.
9341  */
9342 static int
9343 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9344                                    struct rte_eth_hash_global_conf *g_cfg)
9345 {
9346         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9347         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9348         int ret;
9349         uint16_t i, j;
9350         uint32_t reg;
9351         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9352
9353         if (pf->support_multi_driver) {
9354                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9355                 return -ENOTSUP;
9356         }
9357
9358         /* Check the input parameters */
9359         ret = i40e_hash_global_config_check(adapter, g_cfg);
9360         if (ret < 0)
9361                 return ret;
9362
9363         /*
9364          * As i40e supports less than 64 flow types, only first 64 bits need to
9365          * be configured.
9366          */
9367         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9368                 if (mask0 & (1UL << i)) {
9369                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9370                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9371
9372                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9373                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9374                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9375                                         i40e_write_global_rx_ctl(hw,
9376                                                           I40E_GLQF_HSYM(j),
9377                                                           reg);
9378                         }
9379                 }
9380         }
9381
9382         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9383         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9384                 /* Toeplitz */
9385                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9386                         PMD_DRV_LOG(DEBUG,
9387                                 "Hash function already set to Toeplitz");
9388                         goto out;
9389                 }
9390                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9391         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9392                 /* Simple XOR */
9393                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9394                         PMD_DRV_LOG(DEBUG,
9395                                 "Hash function already set to Simple XOR");
9396                         goto out;
9397                 }
9398                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9399         } else
9400                 /* Use the default, and keep it as it is */
9401                 goto out;
9402
9403         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9404
9405 out:
9406         I40E_WRITE_FLUSH(hw);
9407
9408         return 0;
9409 }
9410
9411 /**
9412  * Valid input sets for hash and flow director filters per PCTYPE
9413  */
9414 static uint64_t
9415 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9416                 enum rte_filter_type filter)
9417 {
9418         uint64_t valid;
9419
9420         static const uint64_t valid_hash_inset_table[] = {
9421                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9422                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9423                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9424                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9425                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9426                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9427                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9428                         I40E_INSET_FLEX_PAYLOAD,
9429                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9430                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9431                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9432                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9433                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9434                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9435                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9436                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9437                         I40E_INSET_FLEX_PAYLOAD,
9438                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9439                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9440                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9441                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9442                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9443                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9444                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9445                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9446                         I40E_INSET_FLEX_PAYLOAD,
9447                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9448                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9449                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9450                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9451                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9452                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9453                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9454                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9455                         I40E_INSET_FLEX_PAYLOAD,
9456                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9457                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9458                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9459                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9460                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9461                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9462                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9463                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9464                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9465                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9466                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9467                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9468                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9469                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9470                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9471                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9472                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9473                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9474                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9475                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9476                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9477                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9478                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9479                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9480                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9481                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9482                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9483                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9484                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9485                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9486                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9487                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9488                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9489                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9490                         I40E_INSET_FLEX_PAYLOAD,
9491                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9492                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9493                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9494                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9495                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9496                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9497                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9498                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9499                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9503                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9504                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9505                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9506                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9507                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9508                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9509                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9510                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9511                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9512                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9513                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9514                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9515                         I40E_INSET_FLEX_PAYLOAD,
9516                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9517                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9518                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9519                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9520                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9521                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9522                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9523                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9524                         I40E_INSET_FLEX_PAYLOAD,
9525                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9526                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9527                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9528                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9529                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9530                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9531                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9532                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9533                         I40E_INSET_FLEX_PAYLOAD,
9534                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9535                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9536                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9537                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9538                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9539                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9540                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9541                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9542                         I40E_INSET_FLEX_PAYLOAD,
9543                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9544                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9545                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9546                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9547                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9548                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9549                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9550                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9551                         I40E_INSET_FLEX_PAYLOAD,
9552                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9553                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9554                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9555                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9556                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9557                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9558                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9559                         I40E_INSET_FLEX_PAYLOAD,
9560                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9561                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9562                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9563                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9564                         I40E_INSET_FLEX_PAYLOAD,
9565         };
9566
9567         /**
9568          * Flow director supports only fields defined in
9569          * union rte_eth_fdir_flow.
9570          */
9571         static const uint64_t valid_fdir_inset_table[] = {
9572                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9573                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9574                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9575                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9576                 I40E_INSET_IPV4_TTL,
9577                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9578                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9579                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9580                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9581                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9582                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9583                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9584                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9585                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9586                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9587                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9588                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9589                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9590                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9591                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9592                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9593                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9594                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9595                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9596                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9597                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9598                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9599                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9601                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9602                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9603                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9604                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9605                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9606                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9607                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9608                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9609                 I40E_INSET_SCTP_VT,
9610                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9611                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9612                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9613                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9614                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9615                 I40E_INSET_IPV4_TTL,
9616                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9617                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9618                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9619                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9620                 I40E_INSET_IPV6_HOP_LIMIT,
9621                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9622                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9623                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9624                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9625                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9626                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9627                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9628                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9629                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9630                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9631                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9632                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9633                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9634                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9635                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9636                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9637                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9638                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9639                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9640                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9641                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9642                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9643                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9644                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9645                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9646                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9647                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9648                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9649                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9650                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9651                 I40E_INSET_SCTP_VT,
9652                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9653                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9654                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9655                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9656                 I40E_INSET_IPV6_HOP_LIMIT,
9657                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9658                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9659                 I40E_INSET_LAST_ETHER_TYPE,
9660         };
9661
9662         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9663                 return 0;
9664         if (filter == RTE_ETH_FILTER_HASH)
9665                 valid = valid_hash_inset_table[pctype];
9666         else
9667                 valid = valid_fdir_inset_table[pctype];
9668
9669         return valid;
9670 }
9671
9672 /**
9673  * Validate if the input set is allowed for a specific PCTYPE
9674  */
9675 int
9676 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9677                 enum rte_filter_type filter, uint64_t inset)
9678 {
9679         uint64_t valid;
9680
9681         valid = i40e_get_valid_input_set(pctype, filter);
9682         if (inset & (~valid))
9683                 return -EINVAL;
9684
9685         return 0;
9686 }
9687
9688 /* default input set fields combination per pctype */
9689 uint64_t
9690 i40e_get_default_input_set(uint16_t pctype)
9691 {
9692         static const uint64_t default_inset_table[] = {
9693                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9694                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9695                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9696                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9697                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9698                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9699                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9700                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9701                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9702                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9703                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9704                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9705                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9706                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9707                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9708                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9709                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9710                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9711                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9712                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9713                         I40E_INSET_SCTP_VT,
9714                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9715                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9716                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9717                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9718                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9719                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9720                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9721                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9722                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9723                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9724                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9725                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9726                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9727                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9728                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9729                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9730                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9731                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9732                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9733                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9734                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9735                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9736                         I40E_INSET_SCTP_VT,
9737                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9738                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9739                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9740                         I40E_INSET_LAST_ETHER_TYPE,
9741         };
9742
9743         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9744                 return 0;
9745
9746         return default_inset_table[pctype];
9747 }
9748
9749 /**
9750  * Parse the input set from index to logical bit masks
9751  */
9752 static int
9753 i40e_parse_input_set(uint64_t *inset,
9754                      enum i40e_filter_pctype pctype,
9755                      enum rte_eth_input_set_field *field,
9756                      uint16_t size)
9757 {
9758         uint16_t i, j;
9759         int ret = -EINVAL;
9760
9761         static const struct {
9762                 enum rte_eth_input_set_field field;
9763                 uint64_t inset;
9764         } inset_convert_table[] = {
9765                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9766                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9767                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9768                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9769                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9770                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9771                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9772                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9773                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9774                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9775                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9776                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9777                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9778                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9779                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9780                         I40E_INSET_IPV6_NEXT_HDR},
9781                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9782                         I40E_INSET_IPV6_HOP_LIMIT},
9783                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9784                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9785                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9786                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9787                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9788                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9789                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9790                         I40E_INSET_SCTP_VT},
9791                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9792                         I40E_INSET_TUNNEL_DMAC},
9793                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9794                         I40E_INSET_VLAN_TUNNEL},
9795                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9796                         I40E_INSET_TUNNEL_ID},
9797                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9798                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9799                         I40E_INSET_FLEX_PAYLOAD_W1},
9800                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9801                         I40E_INSET_FLEX_PAYLOAD_W2},
9802                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9803                         I40E_INSET_FLEX_PAYLOAD_W3},
9804                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9805                         I40E_INSET_FLEX_PAYLOAD_W4},
9806                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9807                         I40E_INSET_FLEX_PAYLOAD_W5},
9808                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9809                         I40E_INSET_FLEX_PAYLOAD_W6},
9810                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9811                         I40E_INSET_FLEX_PAYLOAD_W7},
9812                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9813                         I40E_INSET_FLEX_PAYLOAD_W8},
9814         };
9815
9816         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9817                 return ret;
9818
9819         /* Only one item allowed for default or all */
9820         if (size == 1) {
9821                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9822                         *inset = i40e_get_default_input_set(pctype);
9823                         return 0;
9824                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9825                         *inset = I40E_INSET_NONE;
9826                         return 0;
9827                 }
9828         }
9829
9830         for (i = 0, *inset = 0; i < size; i++) {
9831                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9832                         if (field[i] == inset_convert_table[j].field) {
9833                                 *inset |= inset_convert_table[j].inset;
9834                                 break;
9835                         }
9836                 }
9837
9838                 /* It contains unsupported input set, return immediately */
9839                 if (j == RTE_DIM(inset_convert_table))
9840                         return ret;
9841         }
9842
9843         return 0;
9844 }
9845
9846 /**
9847  * Translate the input set from bit masks to register aware bit masks
9848  * and vice versa
9849  */
9850 uint64_t
9851 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9852 {
9853         uint64_t val = 0;
9854         uint16_t i;
9855
9856         struct inset_map {
9857                 uint64_t inset;
9858                 uint64_t inset_reg;
9859         };
9860
9861         static const struct inset_map inset_map_common[] = {
9862                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9863                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9864                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9865                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9866                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9867                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9868                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9869                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9870                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9871                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9872                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9873                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9874                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9875                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9876                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9877                 {I40E_INSET_TUNNEL_DMAC,
9878                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9879                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9880                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9881                 {I40E_INSET_TUNNEL_SRC_PORT,
9882                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9883                 {I40E_INSET_TUNNEL_DST_PORT,
9884                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9885                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9886                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9887                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9888                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9889                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9890                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9891                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9892                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9893                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9894         };
9895
9896     /* some different registers map in x722*/
9897         static const struct inset_map inset_map_diff_x722[] = {
9898                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9899                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9900                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9901                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9902         };
9903
9904         static const struct inset_map inset_map_diff_not_x722[] = {
9905                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9906                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9907                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9908                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9909         };
9910
9911         if (input == 0)
9912                 return val;
9913
9914         /* Translate input set to register aware inset */
9915         if (type == I40E_MAC_X722) {
9916                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9917                         if (input & inset_map_diff_x722[i].inset)
9918                                 val |= inset_map_diff_x722[i].inset_reg;
9919                 }
9920         } else {
9921                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9922                         if (input & inset_map_diff_not_x722[i].inset)
9923                                 val |= inset_map_diff_not_x722[i].inset_reg;
9924                 }
9925         }
9926
9927         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9928                 if (input & inset_map_common[i].inset)
9929                         val |= inset_map_common[i].inset_reg;
9930         }
9931
9932         return val;
9933 }
9934
9935 int
9936 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9937 {
9938         uint8_t i, idx = 0;
9939         uint64_t inset_need_mask = inset;
9940
9941         static const struct {
9942                 uint64_t inset;
9943                 uint32_t mask;
9944         } inset_mask_map[] = {
9945                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9946                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9947                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9948                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9949                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9950                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9951                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9952                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9953         };
9954
9955         if (!inset || !mask || !nb_elem)
9956                 return 0;
9957
9958         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9959                 /* Clear the inset bit, if no MASK is required,
9960                  * for example proto + ttl
9961                  */
9962                 if ((inset & inset_mask_map[i].inset) ==
9963                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9964                         inset_need_mask &= ~inset_mask_map[i].inset;
9965                 if (!inset_need_mask)
9966                         return 0;
9967         }
9968         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9969                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9970                     inset_mask_map[i].inset) {
9971                         if (idx >= nb_elem) {
9972                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9973                                 return -EINVAL;
9974                         }
9975                         mask[idx] = inset_mask_map[i].mask;
9976                         idx++;
9977                 }
9978         }
9979
9980         return idx;
9981 }
9982
9983 void
9984 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9985 {
9986         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9987
9988         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9989         if (reg != val)
9990                 i40e_write_rx_ctl(hw, addr, val);
9991         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9992                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9993 }
9994
9995 void
9996 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9997 {
9998         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9999         struct rte_eth_dev *dev;
10000
10001         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10002         if (reg != val) {
10003                 i40e_write_rx_ctl(hw, addr, val);
10004                 PMD_DRV_LOG(WARNING,
10005                             "i40e device %s changed global register [0x%08x]."
10006                             " original: 0x%08x, new: 0x%08x",
10007                             dev->device->name, addr, reg,
10008                             (uint32_t)i40e_read_rx_ctl(hw, addr));
10009         }
10010 }
10011
10012 static void
10013 i40e_filter_input_set_init(struct i40e_pf *pf)
10014 {
10015         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10016         enum i40e_filter_pctype pctype;
10017         uint64_t input_set, inset_reg;
10018         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10019         int num, i;
10020         uint16_t flow_type;
10021
10022         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10023              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10024                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10025
10026                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10027                         continue;
10028
10029                 input_set = i40e_get_default_input_set(pctype);
10030
10031                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10032                                                    I40E_INSET_MASK_NUM_REG);
10033                 if (num < 0)
10034                         return;
10035                 if (pf->support_multi_driver && num > 0) {
10036                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10037                         return;
10038                 }
10039                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10040                                         input_set);
10041
10042                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10043                                       (uint32_t)(inset_reg & UINT32_MAX));
10044                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10045                                      (uint32_t)((inset_reg >>
10046                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
10047                 if (!pf->support_multi_driver) {
10048                         i40e_check_write_global_reg(hw,
10049                                             I40E_GLQF_HASH_INSET(0, pctype),
10050                                             (uint32_t)(inset_reg & UINT32_MAX));
10051                         i40e_check_write_global_reg(hw,
10052                                              I40E_GLQF_HASH_INSET(1, pctype),
10053                                              (uint32_t)((inset_reg >>
10054                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
10055
10056                         for (i = 0; i < num; i++) {
10057                                 i40e_check_write_global_reg(hw,
10058                                                     I40E_GLQF_FD_MSK(i, pctype),
10059                                                     mask_reg[i]);
10060                                 i40e_check_write_global_reg(hw,
10061                                                   I40E_GLQF_HASH_MSK(i, pctype),
10062                                                   mask_reg[i]);
10063                         }
10064                         /*clear unused mask registers of the pctype */
10065                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10066                                 i40e_check_write_global_reg(hw,
10067                                                     I40E_GLQF_FD_MSK(i, pctype),
10068                                                     0);
10069                                 i40e_check_write_global_reg(hw,
10070                                                   I40E_GLQF_HASH_MSK(i, pctype),
10071                                                   0);
10072                         }
10073                 } else {
10074                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10075                 }
10076                 I40E_WRITE_FLUSH(hw);
10077
10078                 /* store the default input set */
10079                 if (!pf->support_multi_driver)
10080                         pf->hash_input_set[pctype] = input_set;
10081                 pf->fdir.input_set[pctype] = input_set;
10082         }
10083 }
10084
10085 int
10086 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10087                          struct rte_eth_input_set_conf *conf)
10088 {
10089         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10090         enum i40e_filter_pctype pctype;
10091         uint64_t input_set, inset_reg = 0;
10092         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10093         int ret, i, num;
10094
10095         if (!conf) {
10096                 PMD_DRV_LOG(ERR, "Invalid pointer");
10097                 return -EFAULT;
10098         }
10099         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10100             conf->op != RTE_ETH_INPUT_SET_ADD) {
10101                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10102                 return -EINVAL;
10103         }
10104
10105         if (pf->support_multi_driver) {
10106                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10107                 return -ENOTSUP;
10108         }
10109
10110         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10111         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10112                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10113                 return -EINVAL;
10114         }
10115
10116         if (hw->mac.type == I40E_MAC_X722) {
10117                 /* get translated pctype value in fd pctype register */
10118                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10119                         I40E_GLQF_FD_PCTYPES((int)pctype));
10120         }
10121
10122         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10123                                    conf->inset_size);
10124         if (ret) {
10125                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10126                 return -EINVAL;
10127         }
10128
10129         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10130                 /* get inset value in register */
10131                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10132                 inset_reg <<= I40E_32_BIT_WIDTH;
10133                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10134                 input_set |= pf->hash_input_set[pctype];
10135         }
10136         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10137                                            I40E_INSET_MASK_NUM_REG);
10138         if (num < 0)
10139                 return -EINVAL;
10140
10141         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10142
10143         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10144                                     (uint32_t)(inset_reg & UINT32_MAX));
10145         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10146                                     (uint32_t)((inset_reg >>
10147                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10148
10149         for (i = 0; i < num; i++)
10150                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10151                                             mask_reg[i]);
10152         /*clear unused mask registers of the pctype */
10153         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10154                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10155                                             0);
10156         I40E_WRITE_FLUSH(hw);
10157
10158         pf->hash_input_set[pctype] = input_set;
10159         return 0;
10160 }
10161
10162 int
10163 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10164                          struct rte_eth_input_set_conf *conf)
10165 {
10166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10167         enum i40e_filter_pctype pctype;
10168         uint64_t input_set, inset_reg = 0;
10169         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10170         int ret, i, num;
10171
10172         if (!hw || !conf) {
10173                 PMD_DRV_LOG(ERR, "Invalid pointer");
10174                 return -EFAULT;
10175         }
10176         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10177             conf->op != RTE_ETH_INPUT_SET_ADD) {
10178                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10179                 return -EINVAL;
10180         }
10181
10182         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10183
10184         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10185                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10186                 return -EINVAL;
10187         }
10188
10189         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10190                                    conf->inset_size);
10191         if (ret) {
10192                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10193                 return -EINVAL;
10194         }
10195
10196         /* get inset value in register */
10197         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10198         inset_reg <<= I40E_32_BIT_WIDTH;
10199         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10200
10201         /* Can not change the inset reg for flex payload for fdir,
10202          * it is done by writing I40E_PRTQF_FD_FLXINSET
10203          * in i40e_set_flex_mask_on_pctype.
10204          */
10205         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10206                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10207         else
10208                 input_set |= pf->fdir.input_set[pctype];
10209         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10210                                            I40E_INSET_MASK_NUM_REG);
10211         if (num < 0)
10212                 return -EINVAL;
10213         if (pf->support_multi_driver && num > 0) {
10214                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10215                 return -ENOTSUP;
10216         }
10217
10218         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10219
10220         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10221                               (uint32_t)(inset_reg & UINT32_MAX));
10222         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10223                              (uint32_t)((inset_reg >>
10224                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10225
10226         if (!pf->support_multi_driver) {
10227                 for (i = 0; i < num; i++)
10228                         i40e_check_write_global_reg(hw,
10229                                                     I40E_GLQF_FD_MSK(i, pctype),
10230                                                     mask_reg[i]);
10231                 /*clear unused mask registers of the pctype */
10232                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10233                         i40e_check_write_global_reg(hw,
10234                                                     I40E_GLQF_FD_MSK(i, pctype),
10235                                                     0);
10236         } else {
10237                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10238         }
10239         I40E_WRITE_FLUSH(hw);
10240
10241         pf->fdir.input_set[pctype] = input_set;
10242         return 0;
10243 }
10244
10245 static int
10246 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10247 {
10248         int ret = 0;
10249
10250         if (!hw || !info) {
10251                 PMD_DRV_LOG(ERR, "Invalid pointer");
10252                 return -EFAULT;
10253         }
10254
10255         switch (info->info_type) {
10256         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10257                 i40e_get_symmetric_hash_enable_per_port(hw,
10258                                         &(info->info.enable));
10259                 break;
10260         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10261                 ret = i40e_get_hash_filter_global_config(hw,
10262                                 &(info->info.global_conf));
10263                 break;
10264         default:
10265                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10266                                                         info->info_type);
10267                 ret = -EINVAL;
10268                 break;
10269         }
10270
10271         return ret;
10272 }
10273
10274 static int
10275 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10276 {
10277         int ret = 0;
10278
10279         if (!hw || !info) {
10280                 PMD_DRV_LOG(ERR, "Invalid pointer");
10281                 return -EFAULT;
10282         }
10283
10284         switch (info->info_type) {
10285         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10286                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10287                 break;
10288         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10289                 ret = i40e_set_hash_filter_global_config(hw,
10290                                 &(info->info.global_conf));
10291                 break;
10292         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10293                 ret = i40e_hash_filter_inset_select(hw,
10294                                                &(info->info.input_set_conf));
10295                 break;
10296
10297         default:
10298                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10299                                                         info->info_type);
10300                 ret = -EINVAL;
10301                 break;
10302         }
10303
10304         return ret;
10305 }
10306
10307 /* Operations for hash function */
10308 static int
10309 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10310                       enum rte_filter_op filter_op,
10311                       void *arg)
10312 {
10313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10314         int ret = 0;
10315
10316         switch (filter_op) {
10317         case RTE_ETH_FILTER_NOP:
10318                 break;
10319         case RTE_ETH_FILTER_GET:
10320                 ret = i40e_hash_filter_get(hw,
10321                         (struct rte_eth_hash_filter_info *)arg);
10322                 break;
10323         case RTE_ETH_FILTER_SET:
10324                 ret = i40e_hash_filter_set(hw,
10325                         (struct rte_eth_hash_filter_info *)arg);
10326                 break;
10327         default:
10328                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10329                                                                 filter_op);
10330                 ret = -ENOTSUP;
10331                 break;
10332         }
10333
10334         return ret;
10335 }
10336
10337 /* Convert ethertype filter structure */
10338 static int
10339 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10340                               struct i40e_ethertype_filter *filter)
10341 {
10342         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10343                 RTE_ETHER_ADDR_LEN);
10344         filter->input.ether_type = input->ether_type;
10345         filter->flags = input->flags;
10346         filter->queue = input->queue;
10347
10348         return 0;
10349 }
10350
10351 /* Check if there exists the ehtertype filter */
10352 struct i40e_ethertype_filter *
10353 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10354                                 const struct i40e_ethertype_filter_input *input)
10355 {
10356         int ret;
10357
10358         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10359         if (ret < 0)
10360                 return NULL;
10361
10362         return ethertype_rule->hash_map[ret];
10363 }
10364
10365 /* Add ethertype filter in SW list */
10366 static int
10367 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10368                                 struct i40e_ethertype_filter *filter)
10369 {
10370         struct i40e_ethertype_rule *rule = &pf->ethertype;
10371         int ret;
10372
10373         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10374         if (ret < 0) {
10375                 PMD_DRV_LOG(ERR,
10376                             "Failed to insert ethertype filter"
10377                             " to hash table %d!",
10378                             ret);
10379                 return ret;
10380         }
10381         rule->hash_map[ret] = filter;
10382
10383         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10384
10385         return 0;
10386 }
10387
10388 /* Delete ethertype filter in SW list */
10389 int
10390 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10391                              struct i40e_ethertype_filter_input *input)
10392 {
10393         struct i40e_ethertype_rule *rule = &pf->ethertype;
10394         struct i40e_ethertype_filter *filter;
10395         int ret;
10396
10397         ret = rte_hash_del_key(rule->hash_table, input);
10398         if (ret < 0) {
10399                 PMD_DRV_LOG(ERR,
10400                             "Failed to delete ethertype filter"
10401                             " to hash table %d!",
10402                             ret);
10403                 return ret;
10404         }
10405         filter = rule->hash_map[ret];
10406         rule->hash_map[ret] = NULL;
10407
10408         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10409         rte_free(filter);
10410
10411         return 0;
10412 }
10413
10414 /*
10415  * Configure ethertype filter, which can director packet by filtering
10416  * with mac address and ether_type or only ether_type
10417  */
10418 int
10419 i40e_ethertype_filter_set(struct i40e_pf *pf,
10420                         struct rte_eth_ethertype_filter *filter,
10421                         bool add)
10422 {
10423         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10424         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10425         struct i40e_ethertype_filter *ethertype_filter, *node;
10426         struct i40e_ethertype_filter check_filter;
10427         struct i40e_control_filter_stats stats;
10428         uint16_t flags = 0;
10429         int ret;
10430
10431         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10432                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10433                 return -EINVAL;
10434         }
10435         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10436                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10437                 PMD_DRV_LOG(ERR,
10438                         "unsupported ether_type(0x%04x) in control packet filter.",
10439                         filter->ether_type);
10440                 return -EINVAL;
10441         }
10442         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10443                 PMD_DRV_LOG(WARNING,
10444                         "filter vlan ether_type in first tag is not supported.");
10445
10446         /* Check if there is the filter in SW list */
10447         memset(&check_filter, 0, sizeof(check_filter));
10448         i40e_ethertype_filter_convert(filter, &check_filter);
10449         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10450                                                &check_filter.input);
10451         if (add && node) {
10452                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10453                 return -EINVAL;
10454         }
10455
10456         if (!add && !node) {
10457                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10458                 return -EINVAL;
10459         }
10460
10461         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10462                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10463         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10464                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10465         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10466
10467         memset(&stats, 0, sizeof(stats));
10468         ret = i40e_aq_add_rem_control_packet_filter(hw,
10469                         filter->mac_addr.addr_bytes,
10470                         filter->ether_type, flags,
10471                         pf->main_vsi->seid,
10472                         filter->queue, add, &stats, NULL);
10473
10474         PMD_DRV_LOG(INFO,
10475                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10476                 ret, stats.mac_etype_used, stats.etype_used,
10477                 stats.mac_etype_free, stats.etype_free);
10478         if (ret < 0)
10479                 return -ENOSYS;
10480
10481         /* Add or delete a filter in SW list */
10482         if (add) {
10483                 ethertype_filter = rte_zmalloc("ethertype_filter",
10484                                        sizeof(*ethertype_filter), 0);
10485                 if (ethertype_filter == NULL) {
10486                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10487                         return -ENOMEM;
10488                 }
10489
10490                 rte_memcpy(ethertype_filter, &check_filter,
10491                            sizeof(check_filter));
10492                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10493                 if (ret < 0)
10494                         rte_free(ethertype_filter);
10495         } else {
10496                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10497         }
10498
10499         return ret;
10500 }
10501
10502 /*
10503  * Handle operations for ethertype filter.
10504  */
10505 static int
10506 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10507                                 enum rte_filter_op filter_op,
10508                                 void *arg)
10509 {
10510         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10511         int ret = 0;
10512
10513         if (filter_op == RTE_ETH_FILTER_NOP)
10514                 return ret;
10515
10516         if (arg == NULL) {
10517                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10518                             filter_op);
10519                 return -EINVAL;
10520         }
10521
10522         switch (filter_op) {
10523         case RTE_ETH_FILTER_ADD:
10524                 ret = i40e_ethertype_filter_set(pf,
10525                         (struct rte_eth_ethertype_filter *)arg,
10526                         TRUE);
10527                 break;
10528         case RTE_ETH_FILTER_DELETE:
10529                 ret = i40e_ethertype_filter_set(pf,
10530                         (struct rte_eth_ethertype_filter *)arg,
10531                         FALSE);
10532                 break;
10533         default:
10534                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10535                 ret = -ENOSYS;
10536                 break;
10537         }
10538         return ret;
10539 }
10540
10541 static int
10542 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10543                      enum rte_filter_type filter_type,
10544                      enum rte_filter_op filter_op,
10545                      void *arg)
10546 {
10547         int ret = 0;
10548
10549         if (dev == NULL)
10550                 return -EINVAL;
10551
10552         switch (filter_type) {
10553         case RTE_ETH_FILTER_NONE:
10554                 /* For global configuration */
10555                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10556                 break;
10557         case RTE_ETH_FILTER_HASH:
10558                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10559                 break;
10560         case RTE_ETH_FILTER_MACVLAN:
10561                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10562                 break;
10563         case RTE_ETH_FILTER_ETHERTYPE:
10564                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10565                 break;
10566         case RTE_ETH_FILTER_TUNNEL:
10567                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10568                 break;
10569         case RTE_ETH_FILTER_FDIR:
10570                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10571                 break;
10572         case RTE_ETH_FILTER_GENERIC:
10573                 if (filter_op != RTE_ETH_FILTER_GET)
10574                         return -EINVAL;
10575                 *(const void **)arg = &i40e_flow_ops;
10576                 break;
10577         default:
10578                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10579                                                         filter_type);
10580                 ret = -EINVAL;
10581                 break;
10582         }
10583
10584         return ret;
10585 }
10586
10587 /*
10588  * Check and enable Extended Tag.
10589  * Enabling Extended Tag is important for 40G performance.
10590  */
10591 static void
10592 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10593 {
10594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10595         uint32_t buf = 0;
10596         int ret;
10597
10598         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10599                                       PCI_DEV_CAP_REG);
10600         if (ret < 0) {
10601                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10602                             PCI_DEV_CAP_REG);
10603                 return;
10604         }
10605         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10606                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10607                 return;
10608         }
10609
10610         buf = 0;
10611         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10612                                       PCI_DEV_CTRL_REG);
10613         if (ret < 0) {
10614                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10615                             PCI_DEV_CTRL_REG);
10616                 return;
10617         }
10618         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10619                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10620                 return;
10621         }
10622         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10623         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10624                                        PCI_DEV_CTRL_REG);
10625         if (ret < 0) {
10626                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10627                             PCI_DEV_CTRL_REG);
10628                 return;
10629         }
10630 }
10631
10632 /*
10633  * As some registers wouldn't be reset unless a global hardware reset,
10634  * hardware initialization is needed to put those registers into an
10635  * expected initial state.
10636  */
10637 static void
10638 i40e_hw_init(struct rte_eth_dev *dev)
10639 {
10640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10641
10642         i40e_enable_extended_tag(dev);
10643
10644         /* clear the PF Queue Filter control register */
10645         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10646
10647         /* Disable symmetric hash per port */
10648         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10649 }
10650
10651 /*
10652  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10653  * however this function will return only one highest pctype index,
10654  * which is not quite correct. This is known problem of i40e driver
10655  * and needs to be fixed later.
10656  */
10657 enum i40e_filter_pctype
10658 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10659 {
10660         int i;
10661         uint64_t pctype_mask;
10662
10663         if (flow_type < I40E_FLOW_TYPE_MAX) {
10664                 pctype_mask = adapter->pctypes_tbl[flow_type];
10665                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10666                         if (pctype_mask & (1ULL << i))
10667                                 return (enum i40e_filter_pctype)i;
10668                 }
10669         }
10670         return I40E_FILTER_PCTYPE_INVALID;
10671 }
10672
10673 uint16_t
10674 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10675                         enum i40e_filter_pctype pctype)
10676 {
10677         uint16_t flowtype;
10678         uint64_t pctype_mask = 1ULL << pctype;
10679
10680         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10681              flowtype++) {
10682                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10683                         return flowtype;
10684         }
10685
10686         return RTE_ETH_FLOW_UNKNOWN;
10687 }
10688
10689 /*
10690  * On X710, performance number is far from the expectation on recent firmware
10691  * versions; on XL710, performance number is also far from the expectation on
10692  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10693  * mode is enabled and port MAC address is equal to the packet destination MAC
10694  * address. The fix for this issue may not be integrated in the following
10695  * firmware version. So the workaround in software driver is needed. It needs
10696  * to modify the initial values of 3 internal only registers for both X710 and
10697  * XL710. Note that the values for X710 or XL710 could be different, and the
10698  * workaround can be removed when it is fixed in firmware in the future.
10699  */
10700
10701 /* For both X710 and XL710 */
10702 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10703 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10704 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10705
10706 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10707 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10708
10709 /* For X722 */
10710 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10711 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10712
10713 /* For X710 */
10714 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10715 /* For XL710 */
10716 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10717 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10718
10719 /*
10720  * GL_SWR_PM_UP_THR:
10721  * The value is not impacted from the link speed, its value is set according
10722  * to the total number of ports for a better pipe-monitor configuration.
10723  */
10724 static bool
10725 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10726 {
10727 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10728                 .device_id = (dev),   \
10729                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10730
10731 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10732                 .device_id = (dev),   \
10733                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10734
10735         static const struct {
10736                 uint16_t device_id;
10737                 uint32_t val;
10738         } swr_pm_table[] = {
10739                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10740                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10741                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10742                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10743                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10744
10745                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10746                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10747                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10748                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10749                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10750                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10751                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10752         };
10753         uint32_t i;
10754
10755         if (value == NULL) {
10756                 PMD_DRV_LOG(ERR, "value is NULL");
10757                 return false;
10758         }
10759
10760         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10761                 if (hw->device_id == swr_pm_table[i].device_id) {
10762                         *value = swr_pm_table[i].val;
10763
10764                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10765                                     "value - 0x%08x",
10766                                     hw->device_id, *value);
10767                         return true;
10768                 }
10769         }
10770
10771         return false;
10772 }
10773
10774 static int
10775 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10776 {
10777         enum i40e_status_code status;
10778         struct i40e_aq_get_phy_abilities_resp phy_ab;
10779         int ret = -ENOTSUP;
10780         int retries = 0;
10781
10782         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10783                                               NULL);
10784
10785         while (status) {
10786                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10787                         status);
10788                 retries++;
10789                 rte_delay_us(100000);
10790                 if  (retries < 5)
10791                         status = i40e_aq_get_phy_capabilities(hw, false,
10792                                         true, &phy_ab, NULL);
10793                 else
10794                         return ret;
10795         }
10796         return 0;
10797 }
10798
10799 static void
10800 i40e_configure_registers(struct i40e_hw *hw)
10801 {
10802         static struct {
10803                 uint32_t addr;
10804                 uint64_t val;
10805         } reg_table[] = {
10806                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10807                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10808                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10809         };
10810         uint64_t reg;
10811         uint32_t i;
10812         int ret;
10813
10814         for (i = 0; i < RTE_DIM(reg_table); i++) {
10815                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10816                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10817                                 reg_table[i].val =
10818                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10819                         else /* For X710/XL710/XXV710 */
10820                                 if (hw->aq.fw_maj_ver < 6)
10821                                         reg_table[i].val =
10822                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10823                                 else
10824                                         reg_table[i].val =
10825                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10826                 }
10827
10828                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10829                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10830                                 reg_table[i].val =
10831                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10832                         else /* For X710/XL710/XXV710 */
10833                                 reg_table[i].val =
10834                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10835                 }
10836
10837                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10838                         uint32_t cfg_val;
10839
10840                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10841                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10842                                             "GL_SWR_PM_UP_THR value fixup",
10843                                             hw->device_id);
10844                                 continue;
10845                         }
10846
10847                         reg_table[i].val = cfg_val;
10848                 }
10849
10850                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10851                                                         &reg, NULL);
10852                 if (ret < 0) {
10853                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10854                                                         reg_table[i].addr);
10855                         break;
10856                 }
10857                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10858                                                 reg_table[i].addr, reg);
10859                 if (reg == reg_table[i].val)
10860                         continue;
10861
10862                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10863                                                 reg_table[i].val, NULL);
10864                 if (ret < 0) {
10865                         PMD_DRV_LOG(ERR,
10866                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10867                                 reg_table[i].val, reg_table[i].addr);
10868                         break;
10869                 }
10870                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10871                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10872         }
10873 }
10874
10875 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10876 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10877 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10878 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10879 static int
10880 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10881 {
10882         uint32_t reg;
10883         int ret;
10884
10885         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10886                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10887                 return -EINVAL;
10888         }
10889
10890         /* Configure for double VLAN RX stripping */
10891         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10892         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10893                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10894                 ret = i40e_aq_debug_write_register(hw,
10895                                                    I40E_VSI_TSR(vsi->vsi_id),
10896                                                    reg, NULL);
10897                 if (ret < 0) {
10898                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10899                                     vsi->vsi_id);
10900                         return I40E_ERR_CONFIG;
10901                 }
10902         }
10903
10904         /* Configure for double VLAN TX insertion */
10905         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10906         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10907                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10908                 ret = i40e_aq_debug_write_register(hw,
10909                                                    I40E_VSI_L2TAGSTXVALID(
10910                                                    vsi->vsi_id), reg, NULL);
10911                 if (ret < 0) {
10912                         PMD_DRV_LOG(ERR,
10913                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10914                                 vsi->vsi_id);
10915                         return I40E_ERR_CONFIG;
10916                 }
10917         }
10918
10919         return 0;
10920 }
10921
10922 /**
10923  * i40e_aq_add_mirror_rule
10924  * @hw: pointer to the hardware structure
10925  * @seid: VEB seid to add mirror rule to
10926  * @dst_id: destination vsi seid
10927  * @entries: Buffer which contains the entities to be mirrored
10928  * @count: number of entities contained in the buffer
10929  * @rule_id:the rule_id of the rule to be added
10930  *
10931  * Add a mirror rule for a given veb.
10932  *
10933  **/
10934 static enum i40e_status_code
10935 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10936                         uint16_t seid, uint16_t dst_id,
10937                         uint16_t rule_type, uint16_t *entries,
10938                         uint16_t count, uint16_t *rule_id)
10939 {
10940         struct i40e_aq_desc desc;
10941         struct i40e_aqc_add_delete_mirror_rule cmd;
10942         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10943                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10944                 &desc.params.raw;
10945         uint16_t buff_len;
10946         enum i40e_status_code status;
10947
10948         i40e_fill_default_direct_cmd_desc(&desc,
10949                                           i40e_aqc_opc_add_mirror_rule);
10950         memset(&cmd, 0, sizeof(cmd));
10951
10952         buff_len = sizeof(uint16_t) * count;
10953         desc.datalen = rte_cpu_to_le_16(buff_len);
10954         if (buff_len > 0)
10955                 desc.flags |= rte_cpu_to_le_16(
10956                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10957         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10958                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10959         cmd.num_entries = rte_cpu_to_le_16(count);
10960         cmd.seid = rte_cpu_to_le_16(seid);
10961         cmd.destination = rte_cpu_to_le_16(dst_id);
10962
10963         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10964         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10965         PMD_DRV_LOG(INFO,
10966                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10967                 hw->aq.asq_last_status, resp->rule_id,
10968                 resp->mirror_rules_used, resp->mirror_rules_free);
10969         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10970
10971         return status;
10972 }
10973
10974 /**
10975  * i40e_aq_del_mirror_rule
10976  * @hw: pointer to the hardware structure
10977  * @seid: VEB seid to add mirror rule to
10978  * @entries: Buffer which contains the entities to be mirrored
10979  * @count: number of entities contained in the buffer
10980  * @rule_id:the rule_id of the rule to be delete
10981  *
10982  * Delete a mirror rule for a given veb.
10983  *
10984  **/
10985 static enum i40e_status_code
10986 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10987                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10988                 uint16_t count, uint16_t rule_id)
10989 {
10990         struct i40e_aq_desc desc;
10991         struct i40e_aqc_add_delete_mirror_rule cmd;
10992         uint16_t buff_len = 0;
10993         enum i40e_status_code status;
10994         void *buff = NULL;
10995
10996         i40e_fill_default_direct_cmd_desc(&desc,
10997                                           i40e_aqc_opc_delete_mirror_rule);
10998         memset(&cmd, 0, sizeof(cmd));
10999         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11000                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11001                                                           I40E_AQ_FLAG_RD));
11002                 cmd.num_entries = count;
11003                 buff_len = sizeof(uint16_t) * count;
11004                 desc.datalen = rte_cpu_to_le_16(buff_len);
11005                 buff = (void *)entries;
11006         } else
11007                 /* rule id is filled in destination field for deleting mirror rule */
11008                 cmd.destination = rte_cpu_to_le_16(rule_id);
11009
11010         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11011                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11012         cmd.seid = rte_cpu_to_le_16(seid);
11013
11014         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11015         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11016
11017         return status;
11018 }
11019
11020 /**
11021  * i40e_mirror_rule_set
11022  * @dev: pointer to the hardware structure
11023  * @mirror_conf: mirror rule info
11024  * @sw_id: mirror rule's sw_id
11025  * @on: enable/disable
11026  *
11027  * set a mirror rule.
11028  *
11029  **/
11030 static int
11031 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11032                         struct rte_eth_mirror_conf *mirror_conf,
11033                         uint8_t sw_id, uint8_t on)
11034 {
11035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11037         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11038         struct i40e_mirror_rule *parent = NULL;
11039         uint16_t seid, dst_seid, rule_id;
11040         uint16_t i, j = 0;
11041         int ret;
11042
11043         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11044
11045         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11046                 PMD_DRV_LOG(ERR,
11047                         "mirror rule can not be configured without veb or vfs.");
11048                 return -ENOSYS;
11049         }
11050         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11051                 PMD_DRV_LOG(ERR, "mirror table is full.");
11052                 return -ENOSPC;
11053         }
11054         if (mirror_conf->dst_pool > pf->vf_num) {
11055                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11056                                  mirror_conf->dst_pool);
11057                 return -EINVAL;
11058         }
11059
11060         seid = pf->main_vsi->veb->seid;
11061
11062         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11063                 if (sw_id <= it->index) {
11064                         mirr_rule = it;
11065                         break;
11066                 }
11067                 parent = it;
11068         }
11069         if (mirr_rule && sw_id == mirr_rule->index) {
11070                 if (on) {
11071                         PMD_DRV_LOG(ERR, "mirror rule exists.");
11072                         return -EEXIST;
11073                 } else {
11074                         ret = i40e_aq_del_mirror_rule(hw, seid,
11075                                         mirr_rule->rule_type,
11076                                         mirr_rule->entries,
11077                                         mirr_rule->num_entries, mirr_rule->id);
11078                         if (ret < 0) {
11079                                 PMD_DRV_LOG(ERR,
11080                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
11081                                         ret, hw->aq.asq_last_status);
11082                                 return -ENOSYS;
11083                         }
11084                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11085                         rte_free(mirr_rule);
11086                         pf->nb_mirror_rule--;
11087                         return 0;
11088                 }
11089         } else if (!on) {
11090                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11091                 return -ENOENT;
11092         }
11093
11094         mirr_rule = rte_zmalloc("i40e_mirror_rule",
11095                                 sizeof(struct i40e_mirror_rule) , 0);
11096         if (!mirr_rule) {
11097                 PMD_DRV_LOG(ERR, "failed to allocate memory");
11098                 return I40E_ERR_NO_MEMORY;
11099         }
11100         switch (mirror_conf->rule_type) {
11101         case ETH_MIRROR_VLAN:
11102                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11103                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11104                                 mirr_rule->entries[j] =
11105                                         mirror_conf->vlan.vlan_id[i];
11106                                 j++;
11107                         }
11108                 }
11109                 if (j == 0) {
11110                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11111                         rte_free(mirr_rule);
11112                         return -EINVAL;
11113                 }
11114                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11115                 break;
11116         case ETH_MIRROR_VIRTUAL_POOL_UP:
11117         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11118                 /* check if the specified pool bit is out of range */
11119                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11120                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11121                         rte_free(mirr_rule);
11122                         return -EINVAL;
11123                 }
11124                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11125                         if (mirror_conf->pool_mask & (1ULL << i)) {
11126                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11127                                 j++;
11128                         }
11129                 }
11130                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11131                         /* add pf vsi to entries */
11132                         mirr_rule->entries[j] = pf->main_vsi_seid;
11133                         j++;
11134                 }
11135                 if (j == 0) {
11136                         PMD_DRV_LOG(ERR, "pool is not specified.");
11137                         rte_free(mirr_rule);
11138                         return -EINVAL;
11139                 }
11140                 /* egress and ingress in aq commands means from switch but not port */
11141                 mirr_rule->rule_type =
11142                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11143                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11144                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11145                 break;
11146         case ETH_MIRROR_UPLINK_PORT:
11147                 /* egress and ingress in aq commands means from switch but not port*/
11148                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11149                 break;
11150         case ETH_MIRROR_DOWNLINK_PORT:
11151                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11152                 break;
11153         default:
11154                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11155                         mirror_conf->rule_type);
11156                 rte_free(mirr_rule);
11157                 return -EINVAL;
11158         }
11159
11160         /* If the dst_pool is equal to vf_num, consider it as PF */
11161         if (mirror_conf->dst_pool == pf->vf_num)
11162                 dst_seid = pf->main_vsi_seid;
11163         else
11164                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11165
11166         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11167                                       mirr_rule->rule_type, mirr_rule->entries,
11168                                       j, &rule_id);
11169         if (ret < 0) {
11170                 PMD_DRV_LOG(ERR,
11171                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11172                         ret, hw->aq.asq_last_status);
11173                 rte_free(mirr_rule);
11174                 return -ENOSYS;
11175         }
11176
11177         mirr_rule->index = sw_id;
11178         mirr_rule->num_entries = j;
11179         mirr_rule->id = rule_id;
11180         mirr_rule->dst_vsi_seid = dst_seid;
11181
11182         if (parent)
11183                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11184         else
11185                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11186
11187         pf->nb_mirror_rule++;
11188         return 0;
11189 }
11190
11191 /**
11192  * i40e_mirror_rule_reset
11193  * @dev: pointer to the device
11194  * @sw_id: mirror rule's sw_id
11195  *
11196  * reset a mirror rule.
11197  *
11198  **/
11199 static int
11200 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11201 {
11202         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11203         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11204         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11205         uint16_t seid;
11206         int ret;
11207
11208         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11209
11210         seid = pf->main_vsi->veb->seid;
11211
11212         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11213                 if (sw_id == it->index) {
11214                         mirr_rule = it;
11215                         break;
11216                 }
11217         }
11218         if (mirr_rule) {
11219                 ret = i40e_aq_del_mirror_rule(hw, seid,
11220                                 mirr_rule->rule_type,
11221                                 mirr_rule->entries,
11222                                 mirr_rule->num_entries, mirr_rule->id);
11223                 if (ret < 0) {
11224                         PMD_DRV_LOG(ERR,
11225                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11226                                 ret, hw->aq.asq_last_status);
11227                         return -ENOSYS;
11228                 }
11229                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11230                 rte_free(mirr_rule);
11231                 pf->nb_mirror_rule--;
11232         } else {
11233                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11234                 return -ENOENT;
11235         }
11236         return 0;
11237 }
11238
11239 static uint64_t
11240 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11241 {
11242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11243         uint64_t systim_cycles;
11244
11245         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11246         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11247                         << 32;
11248
11249         return systim_cycles;
11250 }
11251
11252 static uint64_t
11253 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11254 {
11255         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11256         uint64_t rx_tstamp;
11257
11258         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11259         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11260                         << 32;
11261
11262         return rx_tstamp;
11263 }
11264
11265 static uint64_t
11266 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11267 {
11268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11269         uint64_t tx_tstamp;
11270
11271         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11272         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11273                         << 32;
11274
11275         return tx_tstamp;
11276 }
11277
11278 static void
11279 i40e_start_timecounters(struct rte_eth_dev *dev)
11280 {
11281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11282         struct i40e_adapter *adapter = dev->data->dev_private;
11283         struct rte_eth_link link;
11284         uint32_t tsync_inc_l;
11285         uint32_t tsync_inc_h;
11286
11287         /* Get current link speed. */
11288         i40e_dev_link_update(dev, 1);
11289         rte_eth_linkstatus_get(dev, &link);
11290
11291         switch (link.link_speed) {
11292         case ETH_SPEED_NUM_40G:
11293         case ETH_SPEED_NUM_25G:
11294                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11295                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11296                 break;
11297         case ETH_SPEED_NUM_10G:
11298                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11299                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11300                 break;
11301         case ETH_SPEED_NUM_1G:
11302                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11303                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11304                 break;
11305         default:
11306                 tsync_inc_l = 0x0;
11307                 tsync_inc_h = 0x0;
11308         }
11309
11310         /* Set the timesync increment value. */
11311         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11312         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11313
11314         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11315         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11316         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11317
11318         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11319         adapter->systime_tc.cc_shift = 0;
11320         adapter->systime_tc.nsec_mask = 0;
11321
11322         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11323         adapter->rx_tstamp_tc.cc_shift = 0;
11324         adapter->rx_tstamp_tc.nsec_mask = 0;
11325
11326         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11327         adapter->tx_tstamp_tc.cc_shift = 0;
11328         adapter->tx_tstamp_tc.nsec_mask = 0;
11329 }
11330
11331 static int
11332 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11333 {
11334         struct i40e_adapter *adapter = dev->data->dev_private;
11335
11336         adapter->systime_tc.nsec += delta;
11337         adapter->rx_tstamp_tc.nsec += delta;
11338         adapter->tx_tstamp_tc.nsec += delta;
11339
11340         return 0;
11341 }
11342
11343 static int
11344 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11345 {
11346         uint64_t ns;
11347         struct i40e_adapter *adapter = dev->data->dev_private;
11348
11349         ns = rte_timespec_to_ns(ts);
11350
11351         /* Set the timecounters to a new value. */
11352         adapter->systime_tc.nsec = ns;
11353         adapter->rx_tstamp_tc.nsec = ns;
11354         adapter->tx_tstamp_tc.nsec = ns;
11355
11356         return 0;
11357 }
11358
11359 static int
11360 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11361 {
11362         uint64_t ns, systime_cycles;
11363         struct i40e_adapter *adapter = dev->data->dev_private;
11364
11365         systime_cycles = i40e_read_systime_cyclecounter(dev);
11366         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11367         *ts = rte_ns_to_timespec(ns);
11368
11369         return 0;
11370 }
11371
11372 static int
11373 i40e_timesync_enable(struct rte_eth_dev *dev)
11374 {
11375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11376         uint32_t tsync_ctl_l;
11377         uint32_t tsync_ctl_h;
11378
11379         /* Stop the timesync system time. */
11380         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11381         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11382         /* Reset the timesync system time value. */
11383         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11384         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11385
11386         i40e_start_timecounters(dev);
11387
11388         /* Clear timesync registers. */
11389         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11390         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11391         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11392         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11393         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11394         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11395
11396         /* Enable timestamping of PTP packets. */
11397         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11398         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11399
11400         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11401         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11402         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11403
11404         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11405         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11406
11407         return 0;
11408 }
11409
11410 static int
11411 i40e_timesync_disable(struct rte_eth_dev *dev)
11412 {
11413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11414         uint32_t tsync_ctl_l;
11415         uint32_t tsync_ctl_h;
11416
11417         /* Disable timestamping of transmitted PTP packets. */
11418         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11419         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11420
11421         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11422         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11423
11424         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11425         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11426
11427         /* Reset the timesync increment value. */
11428         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11429         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11430
11431         return 0;
11432 }
11433
11434 static int
11435 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11436                                 struct timespec *timestamp, uint32_t flags)
11437 {
11438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11439         struct i40e_adapter *adapter = dev->data->dev_private;
11440         uint32_t sync_status;
11441         uint32_t index = flags & 0x03;
11442         uint64_t rx_tstamp_cycles;
11443         uint64_t ns;
11444
11445         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11446         if ((sync_status & (1 << index)) == 0)
11447                 return -EINVAL;
11448
11449         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11450         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11451         *timestamp = rte_ns_to_timespec(ns);
11452
11453         return 0;
11454 }
11455
11456 static int
11457 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11458                                 struct timespec *timestamp)
11459 {
11460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11461         struct i40e_adapter *adapter = dev->data->dev_private;
11462         uint32_t sync_status;
11463         uint64_t tx_tstamp_cycles;
11464         uint64_t ns;
11465
11466         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11467         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11468                 return -EINVAL;
11469
11470         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11471         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11472         *timestamp = rte_ns_to_timespec(ns);
11473
11474         return 0;
11475 }
11476
11477 /*
11478  * i40e_parse_dcb_configure - parse dcb configure from user
11479  * @dev: the device being configured
11480  * @dcb_cfg: pointer of the result of parse
11481  * @*tc_map: bit map of enabled traffic classes
11482  *
11483  * Returns 0 on success, negative value on failure
11484  */
11485 static int
11486 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11487                          struct i40e_dcbx_config *dcb_cfg,
11488                          uint8_t *tc_map)
11489 {
11490         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11491         uint8_t i, tc_bw, bw_lf;
11492
11493         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11494
11495         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11496         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11497                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11498                 return -EINVAL;
11499         }
11500
11501         /* assume each tc has the same bw */
11502         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11503         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11504                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11505         /* to ensure the sum of tcbw is equal to 100 */
11506         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11507         for (i = 0; i < bw_lf; i++)
11508                 dcb_cfg->etscfg.tcbwtable[i]++;
11509
11510         /* assume each tc has the same Transmission Selection Algorithm */
11511         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11512                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11513
11514         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11515                 dcb_cfg->etscfg.prioritytable[i] =
11516                                 dcb_rx_conf->dcb_tc[i];
11517
11518         /* FW needs one App to configure HW */
11519         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11520         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11521         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11522         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11523
11524         if (dcb_rx_conf->nb_tcs == 0)
11525                 *tc_map = 1; /* tc0 only */
11526         else
11527                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11528
11529         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11530                 dcb_cfg->pfc.willing = 0;
11531                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11532                 dcb_cfg->pfc.pfcenable = *tc_map;
11533         }
11534         return 0;
11535 }
11536
11537
11538 static enum i40e_status_code
11539 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11540                               struct i40e_aqc_vsi_properties_data *info,
11541                               uint8_t enabled_tcmap)
11542 {
11543         enum i40e_status_code ret;
11544         int i, total_tc = 0;
11545         uint16_t qpnum_per_tc, bsf, qp_idx;
11546         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11547         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11548         uint16_t used_queues;
11549
11550         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11551         if (ret != I40E_SUCCESS)
11552                 return ret;
11553
11554         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11555                 if (enabled_tcmap & (1 << i))
11556                         total_tc++;
11557         }
11558         if (total_tc == 0)
11559                 total_tc = 1;
11560         vsi->enabled_tc = enabled_tcmap;
11561
11562         /* different VSI has different queues assigned */
11563         if (vsi->type == I40E_VSI_MAIN)
11564                 used_queues = dev_data->nb_rx_queues -
11565                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11566         else if (vsi->type == I40E_VSI_VMDQ2)
11567                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11568         else {
11569                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11570                 return I40E_ERR_NO_AVAILABLE_VSI;
11571         }
11572
11573         qpnum_per_tc = used_queues / total_tc;
11574         /* Number of queues per enabled TC */
11575         if (qpnum_per_tc == 0) {
11576                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11577                 return I40E_ERR_INVALID_QP_ID;
11578         }
11579         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11580                                 I40E_MAX_Q_PER_TC);
11581         bsf = rte_bsf32(qpnum_per_tc);
11582
11583         /**
11584          * Configure TC and queue mapping parameters, for enabled TC,
11585          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11586          * default queue will serve it.
11587          */
11588         qp_idx = 0;
11589         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11590                 if (vsi->enabled_tc & (1 << i)) {
11591                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11592                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11593                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11594                         qp_idx += qpnum_per_tc;
11595                 } else
11596                         info->tc_mapping[i] = 0;
11597         }
11598
11599         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11600         if (vsi->type == I40E_VSI_SRIOV) {
11601                 info->mapping_flags |=
11602                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11603                 for (i = 0; i < vsi->nb_qps; i++)
11604                         info->queue_mapping[i] =
11605                                 rte_cpu_to_le_16(vsi->base_queue + i);
11606         } else {
11607                 info->mapping_flags |=
11608                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11609                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11610         }
11611         info->valid_sections |=
11612                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11613
11614         return I40E_SUCCESS;
11615 }
11616
11617 /*
11618  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11619  * @veb: VEB to be configured
11620  * @tc_map: enabled TC bitmap
11621  *
11622  * Returns 0 on success, negative value on failure
11623  */
11624 static enum i40e_status_code
11625 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11626 {
11627         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11628         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11629         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11630         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11631         enum i40e_status_code ret = I40E_SUCCESS;
11632         int i;
11633         uint32_t bw_max;
11634
11635         /* Check if enabled_tc is same as existing or new TCs */
11636         if (veb->enabled_tc == tc_map)
11637                 return ret;
11638
11639         /* configure tc bandwidth */
11640         memset(&veb_bw, 0, sizeof(veb_bw));
11641         veb_bw.tc_valid_bits = tc_map;
11642         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11643         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11644                 if (tc_map & BIT_ULL(i))
11645                         veb_bw.tc_bw_share_credits[i] = 1;
11646         }
11647         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11648                                                    &veb_bw, NULL);
11649         if (ret) {
11650                 PMD_INIT_LOG(ERR,
11651                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11652                         hw->aq.asq_last_status);
11653                 return ret;
11654         }
11655
11656         memset(&ets_query, 0, sizeof(ets_query));
11657         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11658                                                    &ets_query, NULL);
11659         if (ret != I40E_SUCCESS) {
11660                 PMD_DRV_LOG(ERR,
11661                         "Failed to get switch_comp ETS configuration %u",
11662                         hw->aq.asq_last_status);
11663                 return ret;
11664         }
11665         memset(&bw_query, 0, sizeof(bw_query));
11666         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11667                                                   &bw_query, NULL);
11668         if (ret != I40E_SUCCESS) {
11669                 PMD_DRV_LOG(ERR,
11670                         "Failed to get switch_comp bandwidth configuration %u",
11671                         hw->aq.asq_last_status);
11672                 return ret;
11673         }
11674
11675         /* store and print out BW info */
11676         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11677         veb->bw_info.bw_max = ets_query.tc_bw_max;
11678         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11679         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11680         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11681                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11682                      I40E_16_BIT_WIDTH);
11683         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11684                 veb->bw_info.bw_ets_share_credits[i] =
11685                                 bw_query.tc_bw_share_credits[i];
11686                 veb->bw_info.bw_ets_credits[i] =
11687                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11688                 /* 4 bits per TC, 4th bit is reserved */
11689                 veb->bw_info.bw_ets_max[i] =
11690                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11691                                   RTE_LEN2MASK(3, uint8_t));
11692                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11693                             veb->bw_info.bw_ets_share_credits[i]);
11694                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11695                             veb->bw_info.bw_ets_credits[i]);
11696                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11697                             veb->bw_info.bw_ets_max[i]);
11698         }
11699
11700         veb->enabled_tc = tc_map;
11701
11702         return ret;
11703 }
11704
11705
11706 /*
11707  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11708  * @vsi: VSI to be configured
11709  * @tc_map: enabled TC bitmap
11710  *
11711  * Returns 0 on success, negative value on failure
11712  */
11713 static enum i40e_status_code
11714 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11715 {
11716         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11717         struct i40e_vsi_context ctxt;
11718         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11719         enum i40e_status_code ret = I40E_SUCCESS;
11720         int i;
11721
11722         /* Check if enabled_tc is same as existing or new TCs */
11723         if (vsi->enabled_tc == tc_map)
11724                 return ret;
11725
11726         /* configure tc bandwidth */
11727         memset(&bw_data, 0, sizeof(bw_data));
11728         bw_data.tc_valid_bits = tc_map;
11729         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11730         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11731                 if (tc_map & BIT_ULL(i))
11732                         bw_data.tc_bw_credits[i] = 1;
11733         }
11734         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11735         if (ret) {
11736                 PMD_INIT_LOG(ERR,
11737                         "AQ command Config VSI BW allocation per TC failed = %d",
11738                         hw->aq.asq_last_status);
11739                 goto out;
11740         }
11741         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11742                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11743
11744         /* Update Queue Pairs Mapping for currently enabled UPs */
11745         ctxt.seid = vsi->seid;
11746         ctxt.pf_num = hw->pf_id;
11747         ctxt.vf_num = 0;
11748         ctxt.uplink_seid = vsi->uplink_seid;
11749         ctxt.info = vsi->info;
11750         i40e_get_cap(hw);
11751         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11752         if (ret)
11753                 goto out;
11754
11755         /* Update the VSI after updating the VSI queue-mapping information */
11756         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11757         if (ret) {
11758                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11759                         hw->aq.asq_last_status);
11760                 goto out;
11761         }
11762         /* update the local VSI info with updated queue map */
11763         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11764                                         sizeof(vsi->info.tc_mapping));
11765         rte_memcpy(&vsi->info.queue_mapping,
11766                         &ctxt.info.queue_mapping,
11767                 sizeof(vsi->info.queue_mapping));
11768         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11769         vsi->info.valid_sections = 0;
11770
11771         /* query and update current VSI BW information */
11772         ret = i40e_vsi_get_bw_config(vsi);
11773         if (ret) {
11774                 PMD_INIT_LOG(ERR,
11775                          "Failed updating vsi bw info, err %s aq_err %s",
11776                          i40e_stat_str(hw, ret),
11777                          i40e_aq_str(hw, hw->aq.asq_last_status));
11778                 goto out;
11779         }
11780
11781         vsi->enabled_tc = tc_map;
11782
11783 out:
11784         return ret;
11785 }
11786
11787 /*
11788  * i40e_dcb_hw_configure - program the dcb setting to hw
11789  * @pf: pf the configuration is taken on
11790  * @new_cfg: new configuration
11791  * @tc_map: enabled TC bitmap
11792  *
11793  * Returns 0 on success, negative value on failure
11794  */
11795 static enum i40e_status_code
11796 i40e_dcb_hw_configure(struct i40e_pf *pf,
11797                       struct i40e_dcbx_config *new_cfg,
11798                       uint8_t tc_map)
11799 {
11800         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11801         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11802         struct i40e_vsi *main_vsi = pf->main_vsi;
11803         struct i40e_vsi_list *vsi_list;
11804         enum i40e_status_code ret;
11805         int i;
11806         uint32_t val;
11807
11808         /* Use the FW API if FW > v4.4*/
11809         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11810               (hw->aq.fw_maj_ver >= 5))) {
11811                 PMD_INIT_LOG(ERR,
11812                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11813                 return I40E_ERR_FIRMWARE_API_VERSION;
11814         }
11815
11816         /* Check if need reconfiguration */
11817         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11818                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11819                 return I40E_SUCCESS;
11820         }
11821
11822         /* Copy the new config to the current config */
11823         *old_cfg = *new_cfg;
11824         old_cfg->etsrec = old_cfg->etscfg;
11825         ret = i40e_set_dcb_config(hw);
11826         if (ret) {
11827                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11828                          i40e_stat_str(hw, ret),
11829                          i40e_aq_str(hw, hw->aq.asq_last_status));
11830                 return ret;
11831         }
11832         /* set receive Arbiter to RR mode and ETS scheme by default */
11833         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11834                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11835                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11836                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11837                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11838                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11839                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11840                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11841                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11842                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11843                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11844                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11845                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11846         }
11847         /* get local mib to check whether it is configured correctly */
11848         /* IEEE mode */
11849         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11850         /* Get Local DCB Config */
11851         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11852                                      &hw->local_dcbx_config);
11853
11854         /* if Veb is created, need to update TC of it at first */
11855         if (main_vsi->veb) {
11856                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11857                 if (ret)
11858                         PMD_INIT_LOG(WARNING,
11859                                  "Failed configuring TC for VEB seid=%d",
11860                                  main_vsi->veb->seid);
11861         }
11862         /* Update each VSI */
11863         i40e_vsi_config_tc(main_vsi, tc_map);
11864         if (main_vsi->veb) {
11865                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11866                         /* Beside main VSI and VMDQ VSIs, only enable default
11867                          * TC for other VSIs
11868                          */
11869                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11870                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11871                                                          tc_map);
11872                         else
11873                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11874                                                          I40E_DEFAULT_TCMAP);
11875                         if (ret)
11876                                 PMD_INIT_LOG(WARNING,
11877                                         "Failed configuring TC for VSI seid=%d",
11878                                         vsi_list->vsi->seid);
11879                         /* continue */
11880                 }
11881         }
11882         return I40E_SUCCESS;
11883 }
11884
11885 /*
11886  * i40e_dcb_init_configure - initial dcb config
11887  * @dev: device being configured
11888  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11889  *
11890  * Returns 0 on success, negative value on failure
11891  */
11892 int
11893 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11894 {
11895         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11897         int i, ret = 0;
11898
11899         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11900                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11901                 return -ENOTSUP;
11902         }
11903
11904         /* DCB initialization:
11905          * Update DCB configuration from the Firmware and configure
11906          * LLDP MIB change event.
11907          */
11908         if (sw_dcb == TRUE) {
11909                 /* Stopping lldp is necessary for DPDK, but it will cause
11910                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11911                  * for successful initialization of DCB is that LLDP is
11912                  * enabled. So it is needed to start lldp before DCB init
11913                  * and stop it after initialization.
11914                  */
11915                 ret = i40e_aq_start_lldp(hw, true, NULL);
11916                 if (ret != I40E_SUCCESS)
11917                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11918
11919                 ret = i40e_init_dcb(hw, true);
11920                 /* If lldp agent is stopped, the return value from
11921                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11922                  * adminq status. Otherwise, it should return success.
11923                  */
11924                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11925                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11926                         memset(&hw->local_dcbx_config, 0,
11927                                 sizeof(struct i40e_dcbx_config));
11928                         /* set dcb default configuration */
11929                         hw->local_dcbx_config.etscfg.willing = 0;
11930                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11931                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11932                         hw->local_dcbx_config.etscfg.tsatable[0] =
11933                                                 I40E_IEEE_TSA_ETS;
11934                         /* all UPs mapping to TC0 */
11935                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11936                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11937                         hw->local_dcbx_config.etsrec =
11938                                 hw->local_dcbx_config.etscfg;
11939                         hw->local_dcbx_config.pfc.willing = 0;
11940                         hw->local_dcbx_config.pfc.pfccap =
11941                                                 I40E_MAX_TRAFFIC_CLASS;
11942                         /* FW needs one App to configure HW */
11943                         hw->local_dcbx_config.numapps = 1;
11944                         hw->local_dcbx_config.app[0].selector =
11945                                                 I40E_APP_SEL_ETHTYPE;
11946                         hw->local_dcbx_config.app[0].priority = 3;
11947                         hw->local_dcbx_config.app[0].protocolid =
11948                                                 I40E_APP_PROTOID_FCOE;
11949                         ret = i40e_set_dcb_config(hw);
11950                         if (ret) {
11951                                 PMD_INIT_LOG(ERR,
11952                                         "default dcb config fails. err = %d, aq_err = %d.",
11953                                         ret, hw->aq.asq_last_status);
11954                                 return -ENOSYS;
11955                         }
11956                 } else {
11957                         PMD_INIT_LOG(ERR,
11958                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11959                                 ret, hw->aq.asq_last_status);
11960                         return -ENOTSUP;
11961                 }
11962
11963                 if (i40e_need_stop_lldp(dev)) {
11964                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11965                         if (ret != I40E_SUCCESS)
11966                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11967                 }
11968         } else {
11969                 ret = i40e_aq_start_lldp(hw, true, NULL);
11970                 if (ret != I40E_SUCCESS)
11971                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11972
11973                 ret = i40e_init_dcb(hw, true);
11974                 if (!ret) {
11975                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11976                                 PMD_INIT_LOG(ERR,
11977                                         "HW doesn't support DCBX offload.");
11978                                 return -ENOTSUP;
11979                         }
11980                 } else {
11981                         PMD_INIT_LOG(ERR,
11982                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11983                                 ret, hw->aq.asq_last_status);
11984                         return -ENOTSUP;
11985                 }
11986         }
11987         return 0;
11988 }
11989
11990 /*
11991  * i40e_dcb_setup - setup dcb related config
11992  * @dev: device being configured
11993  *
11994  * Returns 0 on success, negative value on failure
11995  */
11996 static int
11997 i40e_dcb_setup(struct rte_eth_dev *dev)
11998 {
11999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12000         struct i40e_dcbx_config dcb_cfg;
12001         uint8_t tc_map = 0;
12002         int ret = 0;
12003
12004         if ((pf->flags & I40E_FLAG_DCB) == 0) {
12005                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12006                 return -ENOTSUP;
12007         }
12008
12009         if (pf->vf_num != 0)
12010                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12011
12012         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12013         if (ret) {
12014                 PMD_INIT_LOG(ERR, "invalid dcb config");
12015                 return -EINVAL;
12016         }
12017         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12018         if (ret) {
12019                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12020                 return -ENOSYS;
12021         }
12022
12023         return 0;
12024 }
12025
12026 static int
12027 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12028                       struct rte_eth_dcb_info *dcb_info)
12029 {
12030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12031         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12032         struct i40e_vsi *vsi = pf->main_vsi;
12033         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12034         uint16_t bsf, tc_mapping;
12035         int i, j = 0;
12036
12037         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12038                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12039         else
12040                 dcb_info->nb_tcs = 1;
12041         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12042                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12043         for (i = 0; i < dcb_info->nb_tcs; i++)
12044                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12045
12046         /* get queue mapping if vmdq is disabled */
12047         if (!pf->nb_cfg_vmdq_vsi) {
12048                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12049                         if (!(vsi->enabled_tc & (1 << i)))
12050                                 continue;
12051                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12052                         dcb_info->tc_queue.tc_rxq[j][i].base =
12053                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12054                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12055                         dcb_info->tc_queue.tc_txq[j][i].base =
12056                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12057                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12058                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12059                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12060                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12061                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12062                 }
12063                 return 0;
12064         }
12065
12066         /* get queue mapping if vmdq is enabled */
12067         do {
12068                 vsi = pf->vmdq[j].vsi;
12069                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12070                         if (!(vsi->enabled_tc & (1 << i)))
12071                                 continue;
12072                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12073                         dcb_info->tc_queue.tc_rxq[j][i].base =
12074                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12075                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12076                         dcb_info->tc_queue.tc_txq[j][i].base =
12077                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12078                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12079                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12080                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12081                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12082                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12083                 }
12084                 j++;
12085         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12086         return 0;
12087 }
12088
12089 static int
12090 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12091 {
12092         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12093         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12095         uint16_t msix_intr;
12096
12097         msix_intr = intr_handle->intr_vec[queue_id];
12098         if (msix_intr == I40E_MISC_VEC_ID)
12099                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12100                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12101                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12102                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12103         else
12104                 I40E_WRITE_REG(hw,
12105                                I40E_PFINT_DYN_CTLN(msix_intr -
12106                                                    I40E_RX_VEC_START),
12107                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12108                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12109                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12110
12111         I40E_WRITE_FLUSH(hw);
12112         rte_intr_ack(&pci_dev->intr_handle);
12113
12114         return 0;
12115 }
12116
12117 static int
12118 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12119 {
12120         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12121         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12122         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12123         uint16_t msix_intr;
12124
12125         msix_intr = intr_handle->intr_vec[queue_id];
12126         if (msix_intr == I40E_MISC_VEC_ID)
12127                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12128                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12129         else
12130                 I40E_WRITE_REG(hw,
12131                                I40E_PFINT_DYN_CTLN(msix_intr -
12132                                                    I40E_RX_VEC_START),
12133                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12134         I40E_WRITE_FLUSH(hw);
12135
12136         return 0;
12137 }
12138
12139 /**
12140  * This function is used to check if the register is valid.
12141  * Below is the valid registers list for X722 only:
12142  * 0x2b800--0x2bb00
12143  * 0x38700--0x38a00
12144  * 0x3d800--0x3db00
12145  * 0x208e00--0x209000
12146  * 0x20be00--0x20c000
12147  * 0x263c00--0x264000
12148  * 0x265c00--0x266000
12149  */
12150 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12151 {
12152         if ((type != I40E_MAC_X722) &&
12153             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12154              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12155              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12156              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12157              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12158              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12159              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12160                 return 0;
12161         else
12162                 return 1;
12163 }
12164
12165 static int i40e_get_regs(struct rte_eth_dev *dev,
12166                          struct rte_dev_reg_info *regs)
12167 {
12168         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12169         uint32_t *ptr_data = regs->data;
12170         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12171         const struct i40e_reg_info *reg_info;
12172
12173         if (ptr_data == NULL) {
12174                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12175                 regs->width = sizeof(uint32_t);
12176                 return 0;
12177         }
12178
12179         /* The first few registers have to be read using AQ operations */
12180         reg_idx = 0;
12181         while (i40e_regs_adminq[reg_idx].name) {
12182                 reg_info = &i40e_regs_adminq[reg_idx++];
12183                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12184                         for (arr_idx2 = 0;
12185                                         arr_idx2 <= reg_info->count2;
12186                                         arr_idx2++) {
12187                                 reg_offset = arr_idx * reg_info->stride1 +
12188                                         arr_idx2 * reg_info->stride2;
12189                                 reg_offset += reg_info->base_addr;
12190                                 ptr_data[reg_offset >> 2] =
12191                                         i40e_read_rx_ctl(hw, reg_offset);
12192                         }
12193         }
12194
12195         /* The remaining registers can be read using primitives */
12196         reg_idx = 0;
12197         while (i40e_regs_others[reg_idx].name) {
12198                 reg_info = &i40e_regs_others[reg_idx++];
12199                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12200                         for (arr_idx2 = 0;
12201                                         arr_idx2 <= reg_info->count2;
12202                                         arr_idx2++) {
12203                                 reg_offset = arr_idx * reg_info->stride1 +
12204                                         arr_idx2 * reg_info->stride2;
12205                                 reg_offset += reg_info->base_addr;
12206                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12207                                         ptr_data[reg_offset >> 2] = 0;
12208                                 else
12209                                         ptr_data[reg_offset >> 2] =
12210                                                 I40E_READ_REG(hw, reg_offset);
12211                         }
12212         }
12213
12214         return 0;
12215 }
12216
12217 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12218 {
12219         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12220
12221         /* Convert word count to byte count */
12222         return hw->nvm.sr_size << 1;
12223 }
12224
12225 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12226                            struct rte_dev_eeprom_info *eeprom)
12227 {
12228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12229         uint16_t *data = eeprom->data;
12230         uint16_t offset, length, cnt_words;
12231         int ret_code;
12232
12233         offset = eeprom->offset >> 1;
12234         length = eeprom->length >> 1;
12235         cnt_words = length;
12236
12237         if (offset > hw->nvm.sr_size ||
12238                 offset + length > hw->nvm.sr_size) {
12239                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12240                 return -EINVAL;
12241         }
12242
12243         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12244
12245         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12246         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12247                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12248                 return -EIO;
12249         }
12250
12251         return 0;
12252 }
12253
12254 static int i40e_get_module_info(struct rte_eth_dev *dev,
12255                                 struct rte_eth_dev_module_info *modinfo)
12256 {
12257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12258         uint32_t sff8472_comp = 0;
12259         uint32_t sff8472_swap = 0;
12260         uint32_t sff8636_rev = 0;
12261         i40e_status status;
12262         uint32_t type = 0;
12263
12264         /* Check if firmware supports reading module EEPROM. */
12265         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12266                 PMD_DRV_LOG(ERR,
12267                             "Module EEPROM memory read not supported. "
12268                             "Please update the NVM image.\n");
12269                 return -EINVAL;
12270         }
12271
12272         status = i40e_update_link_info(hw);
12273         if (status)
12274                 return -EIO;
12275
12276         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12277                 PMD_DRV_LOG(ERR,
12278                             "Cannot read module EEPROM memory. "
12279                             "No module connected.\n");
12280                 return -EINVAL;
12281         }
12282
12283         type = hw->phy.link_info.module_type[0];
12284
12285         switch (type) {
12286         case I40E_MODULE_TYPE_SFP:
12287                 status = i40e_aq_get_phy_register(hw,
12288                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12289                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12290                                 I40E_MODULE_SFF_8472_COMP,
12291                                 &sff8472_comp, NULL);
12292                 if (status)
12293                         return -EIO;
12294
12295                 status = i40e_aq_get_phy_register(hw,
12296                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12297                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12298                                 I40E_MODULE_SFF_8472_SWAP,
12299                                 &sff8472_swap, NULL);
12300                 if (status)
12301                         return -EIO;
12302
12303                 /* Check if the module requires address swap to access
12304                  * the other EEPROM memory page.
12305                  */
12306                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12307                         PMD_DRV_LOG(WARNING,
12308                                     "Module address swap to access "
12309                                     "page 0xA2 is not supported.\n");
12310                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12311                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12312                 } else if (sff8472_comp == 0x00) {
12313                         /* Module is not SFF-8472 compliant */
12314                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12315                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12316                 } else {
12317                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12318                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12319                 }
12320                 break;
12321         case I40E_MODULE_TYPE_QSFP_PLUS:
12322                 /* Read from memory page 0. */
12323                 status = i40e_aq_get_phy_register(hw,
12324                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12325                                 0, 1,
12326                                 I40E_MODULE_REVISION_ADDR,
12327                                 &sff8636_rev, NULL);
12328                 if (status)
12329                         return -EIO;
12330                 /* Determine revision compliance byte */
12331                 if (sff8636_rev > 0x02) {
12332                         /* Module is SFF-8636 compliant */
12333                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12334                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12335                 } else {
12336                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12337                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12338                 }
12339                 break;
12340         case I40E_MODULE_TYPE_QSFP28:
12341                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12342                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12343                 break;
12344         default:
12345                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12346                 return -EINVAL;
12347         }
12348         return 0;
12349 }
12350
12351 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12352                                   struct rte_dev_eeprom_info *info)
12353 {
12354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12355         bool is_sfp = false;
12356         i40e_status status;
12357         uint8_t *data;
12358         uint32_t value = 0;
12359         uint32_t i;
12360
12361         if (!info || !info->length || !info->data)
12362                 return -EINVAL;
12363
12364         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12365                 is_sfp = true;
12366
12367         data = info->data;
12368         for (i = 0; i < info->length; i++) {
12369                 u32 offset = i + info->offset;
12370                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12371
12372                 /* Check if we need to access the other memory page */
12373                 if (is_sfp) {
12374                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12375                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12376                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12377                         }
12378                 } else {
12379                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12380                                 /* Compute memory page number and offset. */
12381                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12382                                 addr++;
12383                         }
12384                 }
12385                 status = i40e_aq_get_phy_register(hw,
12386                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12387                                 addr, 1, offset, &value, NULL);
12388                 if (status)
12389                         return -EIO;
12390                 data[i] = (uint8_t)value;
12391         }
12392         return 0;
12393 }
12394
12395 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12396                                      struct rte_ether_addr *mac_addr)
12397 {
12398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12400         struct i40e_vsi *vsi = pf->main_vsi;
12401         struct i40e_mac_filter_info mac_filter;
12402         struct i40e_mac_filter *f;
12403         int ret;
12404
12405         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12406                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12407                 return -EINVAL;
12408         }
12409
12410         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12411                 if (rte_is_same_ether_addr(&pf->dev_addr,
12412                                                 &f->mac_info.mac_addr))
12413                         break;
12414         }
12415
12416         if (f == NULL) {
12417                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12418                 return -EIO;
12419         }
12420
12421         mac_filter = f->mac_info;
12422         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12423         if (ret != I40E_SUCCESS) {
12424                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12425                 return -EIO;
12426         }
12427         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12428         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12429         if (ret != I40E_SUCCESS) {
12430                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12431                 return -EIO;
12432         }
12433         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12434
12435         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12436                                         mac_addr->addr_bytes, NULL);
12437         if (ret != I40E_SUCCESS) {
12438                 PMD_DRV_LOG(ERR, "Failed to change mac");
12439                 return -EIO;
12440         }
12441
12442         return 0;
12443 }
12444
12445 static int
12446 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12447 {
12448         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12449         struct rte_eth_dev_data *dev_data = pf->dev_data;
12450         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12451         int ret = 0;
12452
12453         /* check if mtu is within the allowed range */
12454         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12455                 return -EINVAL;
12456
12457         /* mtu setting is forbidden if port is start */
12458         if (dev_data->dev_started) {
12459                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12460                             dev_data->port_id);
12461                 return -EBUSY;
12462         }
12463
12464         if (frame_size > RTE_ETHER_MAX_LEN)
12465                 dev_data->dev_conf.rxmode.offloads |=
12466                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12467         else
12468                 dev_data->dev_conf.rxmode.offloads &=
12469                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12470
12471         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12472
12473         return ret;
12474 }
12475
12476 /* Restore ethertype filter */
12477 static void
12478 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12479 {
12480         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12481         struct i40e_ethertype_filter_list
12482                 *ethertype_list = &pf->ethertype.ethertype_list;
12483         struct i40e_ethertype_filter *f;
12484         struct i40e_control_filter_stats stats;
12485         uint16_t flags;
12486
12487         TAILQ_FOREACH(f, ethertype_list, rules) {
12488                 flags = 0;
12489                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12490                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12491                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12492                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12493                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12494
12495                 memset(&stats, 0, sizeof(stats));
12496                 i40e_aq_add_rem_control_packet_filter(hw,
12497                                             f->input.mac_addr.addr_bytes,
12498                                             f->input.ether_type,
12499                                             flags, pf->main_vsi->seid,
12500                                             f->queue, 1, &stats, NULL);
12501         }
12502         PMD_DRV_LOG(INFO, "Ethertype filter:"
12503                     " mac_etype_used = %u, etype_used = %u,"
12504                     " mac_etype_free = %u, etype_free = %u",
12505                     stats.mac_etype_used, stats.etype_used,
12506                     stats.mac_etype_free, stats.etype_free);
12507 }
12508
12509 /* Restore tunnel filter */
12510 static void
12511 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12512 {
12513         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12514         struct i40e_vsi *vsi;
12515         struct i40e_pf_vf *vf;
12516         struct i40e_tunnel_filter_list
12517                 *tunnel_list = &pf->tunnel.tunnel_list;
12518         struct i40e_tunnel_filter *f;
12519         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12520         bool big_buffer = 0;
12521
12522         TAILQ_FOREACH(f, tunnel_list, rules) {
12523                 if (!f->is_to_vf)
12524                         vsi = pf->main_vsi;
12525                 else {
12526                         vf = &pf->vfs[f->vf_id];
12527                         vsi = vf->vsi;
12528                 }
12529                 memset(&cld_filter, 0, sizeof(cld_filter));
12530                 rte_ether_addr_copy((struct rte_ether_addr *)
12531                                 &f->input.outer_mac,
12532                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12533                 rte_ether_addr_copy((struct rte_ether_addr *)
12534                                 &f->input.inner_mac,
12535                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12536                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12537                 cld_filter.element.flags = f->input.flags;
12538                 cld_filter.element.tenant_id = f->input.tenant_id;
12539                 cld_filter.element.queue_number = f->queue;
12540                 rte_memcpy(cld_filter.general_fields,
12541                            f->input.general_fields,
12542                            sizeof(f->input.general_fields));
12543
12544                 if (((f->input.flags &
12545                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12546                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12547                     ((f->input.flags &
12548                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12549                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12550                     ((f->input.flags &
12551                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12552                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12553                         big_buffer = 1;
12554
12555                 if (big_buffer)
12556                         i40e_aq_add_cloud_filters_bb(hw,
12557                                         vsi->seid, &cld_filter, 1);
12558                 else
12559                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12560                                                   &cld_filter.element, 1);
12561         }
12562 }
12563
12564 /* Restore RSS filter */
12565 static inline void
12566 i40e_rss_filter_restore(struct i40e_pf *pf)
12567 {
12568         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12569         struct i40e_rss_filter *filter;
12570
12571         TAILQ_FOREACH(filter, list, next) {
12572                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12573         }
12574 }
12575
12576 static void
12577 i40e_filter_restore(struct i40e_pf *pf)
12578 {
12579         i40e_ethertype_filter_restore(pf);
12580         i40e_tunnel_filter_restore(pf);
12581         i40e_fdir_filter_restore(pf);
12582         i40e_rss_filter_restore(pf);
12583 }
12584
12585 bool
12586 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12587 {
12588         if (strcmp(dev->device->driver->name, drv->driver.name))
12589                 return false;
12590
12591         return true;
12592 }
12593
12594 bool
12595 is_i40e_supported(struct rte_eth_dev *dev)
12596 {
12597         return is_device_supported(dev, &rte_i40e_pmd);
12598 }
12599
12600 struct i40e_customized_pctype*
12601 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12602 {
12603         int i;
12604
12605         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12606                 if (pf->customized_pctype[i].index == index)
12607                         return &pf->customized_pctype[i];
12608         }
12609         return NULL;
12610 }
12611
12612 static int
12613 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12614                               uint32_t pkg_size, uint32_t proto_num,
12615                               struct rte_pmd_i40e_proto_info *proto,
12616                               enum rte_pmd_i40e_package_op op)
12617 {
12618         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12619         uint32_t pctype_num;
12620         struct rte_pmd_i40e_ptype_info *pctype;
12621         uint32_t buff_size;
12622         struct i40e_customized_pctype *new_pctype = NULL;
12623         uint8_t proto_id;
12624         uint8_t pctype_value;
12625         char name[64];
12626         uint32_t i, j, n;
12627         int ret;
12628
12629         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12630             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12631                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12632                 return -1;
12633         }
12634
12635         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12636                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12637                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12638         if (ret) {
12639                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12640                 return -1;
12641         }
12642         if (!pctype_num) {
12643                 PMD_DRV_LOG(INFO, "No new pctype added");
12644                 return -1;
12645         }
12646
12647         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12648         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12649         if (!pctype) {
12650                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12651                 return -1;
12652         }
12653         /* get information about new pctype list */
12654         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12655                                         (uint8_t *)pctype, buff_size,
12656                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12657         if (ret) {
12658                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12659                 rte_free(pctype);
12660                 return -1;
12661         }
12662
12663         /* Update customized pctype. */
12664         for (i = 0; i < pctype_num; i++) {
12665                 pctype_value = pctype[i].ptype_id;
12666                 memset(name, 0, sizeof(name));
12667                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12668                         proto_id = pctype[i].protocols[j];
12669                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12670                                 continue;
12671                         for (n = 0; n < proto_num; n++) {
12672                                 if (proto[n].proto_id != proto_id)
12673                                         continue;
12674                                 strlcat(name, proto[n].name, sizeof(name));
12675                                 strlcat(name, "_", sizeof(name));
12676                                 break;
12677                         }
12678                 }
12679                 name[strlen(name) - 1] = '\0';
12680                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12681                 if (!strcmp(name, "GTPC"))
12682                         new_pctype =
12683                                 i40e_find_customized_pctype(pf,
12684                                                       I40E_CUSTOMIZED_GTPC);
12685                 else if (!strcmp(name, "GTPU_IPV4"))
12686                         new_pctype =
12687                                 i40e_find_customized_pctype(pf,
12688                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12689                 else if (!strcmp(name, "GTPU_IPV6"))
12690                         new_pctype =
12691                                 i40e_find_customized_pctype(pf,
12692                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12693                 else if (!strcmp(name, "GTPU"))
12694                         new_pctype =
12695                                 i40e_find_customized_pctype(pf,
12696                                                       I40E_CUSTOMIZED_GTPU);
12697                 else if (!strcmp(name, "IPV4_L2TPV3"))
12698                         new_pctype =
12699                                 i40e_find_customized_pctype(pf,
12700                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12701                 else if (!strcmp(name, "IPV6_L2TPV3"))
12702                         new_pctype =
12703                                 i40e_find_customized_pctype(pf,
12704                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12705                 else if (!strcmp(name, "IPV4_ESP"))
12706                         new_pctype =
12707                                 i40e_find_customized_pctype(pf,
12708                                                 I40E_CUSTOMIZED_ESP_IPV4);
12709                 else if (!strcmp(name, "IPV6_ESP"))
12710                         new_pctype =
12711                                 i40e_find_customized_pctype(pf,
12712                                                 I40E_CUSTOMIZED_ESP_IPV6);
12713                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12714                         new_pctype =
12715                                 i40e_find_customized_pctype(pf,
12716                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12717                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12718                         new_pctype =
12719                                 i40e_find_customized_pctype(pf,
12720                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12721                 else if (!strcmp(name, "IPV4_AH"))
12722                         new_pctype =
12723                                 i40e_find_customized_pctype(pf,
12724                                                 I40E_CUSTOMIZED_AH_IPV4);
12725                 else if (!strcmp(name, "IPV6_AH"))
12726                         new_pctype =
12727                                 i40e_find_customized_pctype(pf,
12728                                                 I40E_CUSTOMIZED_AH_IPV6);
12729                 if (new_pctype) {
12730                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12731                                 new_pctype->pctype = pctype_value;
12732                                 new_pctype->valid = true;
12733                         } else {
12734                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12735                                 new_pctype->valid = false;
12736                         }
12737                 }
12738         }
12739
12740         rte_free(pctype);
12741         return 0;
12742 }
12743
12744 static int
12745 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12746                              uint32_t pkg_size, uint32_t proto_num,
12747                              struct rte_pmd_i40e_proto_info *proto,
12748                              enum rte_pmd_i40e_package_op op)
12749 {
12750         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12751         uint16_t port_id = dev->data->port_id;
12752         uint32_t ptype_num;
12753         struct rte_pmd_i40e_ptype_info *ptype;
12754         uint32_t buff_size;
12755         uint8_t proto_id;
12756         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12757         uint32_t i, j, n;
12758         bool in_tunnel;
12759         int ret;
12760
12761         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12762             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12763                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12764                 return -1;
12765         }
12766
12767         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12768                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12769                 return 0;
12770         }
12771
12772         /* get information about new ptype num */
12773         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12774                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12775                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12776         if (ret) {
12777                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12778                 return ret;
12779         }
12780         if (!ptype_num) {
12781                 PMD_DRV_LOG(INFO, "No new ptype added");
12782                 return -1;
12783         }
12784
12785         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12786         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12787         if (!ptype) {
12788                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12789                 return -1;
12790         }
12791
12792         /* get information about new ptype list */
12793         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12794                                         (uint8_t *)ptype, buff_size,
12795                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12796         if (ret) {
12797                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12798                 rte_free(ptype);
12799                 return ret;
12800         }
12801
12802         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12803         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12804         if (!ptype_mapping) {
12805                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12806                 rte_free(ptype);
12807                 return -1;
12808         }
12809
12810         /* Update ptype mapping table. */
12811         for (i = 0; i < ptype_num; i++) {
12812                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12813                 ptype_mapping[i].sw_ptype = 0;
12814                 in_tunnel = false;
12815                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12816                         proto_id = ptype[i].protocols[j];
12817                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12818                                 continue;
12819                         for (n = 0; n < proto_num; n++) {
12820                                 if (proto[n].proto_id != proto_id)
12821                                         continue;
12822                                 memset(name, 0, sizeof(name));
12823                                 strcpy(name, proto[n].name);
12824                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12825                                 if (!strncasecmp(name, "PPPOE", 5))
12826                                         ptype_mapping[i].sw_ptype |=
12827                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12828                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12829                                          !in_tunnel) {
12830                                         ptype_mapping[i].sw_ptype |=
12831                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12832                                         ptype_mapping[i].sw_ptype |=
12833                                                 RTE_PTYPE_L4_FRAG;
12834                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12835                                            in_tunnel) {
12836                                         ptype_mapping[i].sw_ptype |=
12837                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12838                                         ptype_mapping[i].sw_ptype |=
12839                                                 RTE_PTYPE_INNER_L4_FRAG;
12840                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12841                                         ptype_mapping[i].sw_ptype |=
12842                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12843                                         in_tunnel = true;
12844                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12845                                            !in_tunnel)
12846                                         ptype_mapping[i].sw_ptype |=
12847                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12848                                 else if (!strncasecmp(name, "IPV4", 4) &&
12849                                          in_tunnel)
12850                                         ptype_mapping[i].sw_ptype |=
12851                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12852                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12853                                          !in_tunnel) {
12854                                         ptype_mapping[i].sw_ptype |=
12855                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12856                                         ptype_mapping[i].sw_ptype |=
12857                                                 RTE_PTYPE_L4_FRAG;
12858                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12859                                            in_tunnel) {
12860                                         ptype_mapping[i].sw_ptype |=
12861                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12862                                         ptype_mapping[i].sw_ptype |=
12863                                                 RTE_PTYPE_INNER_L4_FRAG;
12864                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12865                                         ptype_mapping[i].sw_ptype |=
12866                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12867                                         in_tunnel = true;
12868                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12869                                            !in_tunnel)
12870                                         ptype_mapping[i].sw_ptype |=
12871                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12872                                 else if (!strncasecmp(name, "IPV6", 4) &&
12873                                          in_tunnel)
12874                                         ptype_mapping[i].sw_ptype |=
12875                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12876                                 else if (!strncasecmp(name, "UDP", 3) &&
12877                                          !in_tunnel)
12878                                         ptype_mapping[i].sw_ptype |=
12879                                                 RTE_PTYPE_L4_UDP;
12880                                 else if (!strncasecmp(name, "UDP", 3) &&
12881                                          in_tunnel)
12882                                         ptype_mapping[i].sw_ptype |=
12883                                                 RTE_PTYPE_INNER_L4_UDP;
12884                                 else if (!strncasecmp(name, "TCP", 3) &&
12885                                          !in_tunnel)
12886                                         ptype_mapping[i].sw_ptype |=
12887                                                 RTE_PTYPE_L4_TCP;
12888                                 else if (!strncasecmp(name, "TCP", 3) &&
12889                                          in_tunnel)
12890                                         ptype_mapping[i].sw_ptype |=
12891                                                 RTE_PTYPE_INNER_L4_TCP;
12892                                 else if (!strncasecmp(name, "SCTP", 4) &&
12893                                          !in_tunnel)
12894                                         ptype_mapping[i].sw_ptype |=
12895                                                 RTE_PTYPE_L4_SCTP;
12896                                 else if (!strncasecmp(name, "SCTP", 4) &&
12897                                          in_tunnel)
12898                                         ptype_mapping[i].sw_ptype |=
12899                                                 RTE_PTYPE_INNER_L4_SCTP;
12900                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12901                                           !strncasecmp(name, "ICMPV6", 6)) &&
12902                                          !in_tunnel)
12903                                         ptype_mapping[i].sw_ptype |=
12904                                                 RTE_PTYPE_L4_ICMP;
12905                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12906                                           !strncasecmp(name, "ICMPV6", 6)) &&
12907                                          in_tunnel)
12908                                         ptype_mapping[i].sw_ptype |=
12909                                                 RTE_PTYPE_INNER_L4_ICMP;
12910                                 else if (!strncasecmp(name, "GTPC", 4)) {
12911                                         ptype_mapping[i].sw_ptype |=
12912                                                 RTE_PTYPE_TUNNEL_GTPC;
12913                                         in_tunnel = true;
12914                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12915                                         ptype_mapping[i].sw_ptype |=
12916                                                 RTE_PTYPE_TUNNEL_GTPU;
12917                                         in_tunnel = true;
12918                                 } else if (!strncasecmp(name, "ESP", 3)) {
12919                                         ptype_mapping[i].sw_ptype |=
12920                                                 RTE_PTYPE_TUNNEL_ESP;
12921                                         in_tunnel = true;
12922                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12923                                         ptype_mapping[i].sw_ptype |=
12924                                                 RTE_PTYPE_TUNNEL_GRENAT;
12925                                         in_tunnel = true;
12926                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12927                                            !strncasecmp(name, "L2TPV2", 6) ||
12928                                            !strncasecmp(name, "L2TPV3", 6)) {
12929                                         ptype_mapping[i].sw_ptype |=
12930                                                 RTE_PTYPE_TUNNEL_L2TP;
12931                                         in_tunnel = true;
12932                                 }
12933
12934                                 break;
12935                         }
12936                 }
12937         }
12938
12939         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12940                                                 ptype_num, 0);
12941         if (ret)
12942                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12943
12944         rte_free(ptype_mapping);
12945         rte_free(ptype);
12946         return ret;
12947 }
12948
12949 void
12950 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12951                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12952 {
12953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12954         uint32_t proto_num;
12955         struct rte_pmd_i40e_proto_info *proto;
12956         uint32_t buff_size;
12957         uint32_t i;
12958         int ret;
12959
12960         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12961             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12962                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12963                 return;
12964         }
12965
12966         /* get information about protocol number */
12967         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12968                                        (uint8_t *)&proto_num, sizeof(proto_num),
12969                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12970         if (ret) {
12971                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12972                 return;
12973         }
12974         if (!proto_num) {
12975                 PMD_DRV_LOG(INFO, "No new protocol added");
12976                 return;
12977         }
12978
12979         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12980         proto = rte_zmalloc("new_proto", buff_size, 0);
12981         if (!proto) {
12982                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12983                 return;
12984         }
12985
12986         /* get information about protocol list */
12987         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12988                                         (uint8_t *)proto, buff_size,
12989                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12990         if (ret) {
12991                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12992                 rte_free(proto);
12993                 return;
12994         }
12995
12996         /* Check if GTP is supported. */
12997         for (i = 0; i < proto_num; i++) {
12998                 if (!strncmp(proto[i].name, "GTP", 3)) {
12999                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13000                                 pf->gtp_support = true;
13001                         else
13002                                 pf->gtp_support = false;
13003                         break;
13004                 }
13005         }
13006
13007         /* Check if ESP is supported. */
13008         for (i = 0; i < proto_num; i++) {
13009                 if (!strncmp(proto[i].name, "ESP", 3)) {
13010                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13011                                 pf->esp_support = true;
13012                         else
13013                                 pf->esp_support = false;
13014                         break;
13015                 }
13016         }
13017
13018         /* Update customized pctype info */
13019         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13020                                             proto_num, proto, op);
13021         if (ret)
13022                 PMD_DRV_LOG(INFO, "No pctype is updated.");
13023
13024         /* Update customized ptype info */
13025         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13026                                            proto_num, proto, op);
13027         if (ret)
13028                 PMD_DRV_LOG(INFO, "No ptype is updated.");
13029
13030         rte_free(proto);
13031 }
13032
13033 /* Create a QinQ cloud filter
13034  *
13035  * The Fortville NIC has limited resources for tunnel filters,
13036  * so we can only reuse existing filters.
13037  *
13038  * In step 1 we define which Field Vector fields can be used for
13039  * filter types.
13040  * As we do not have the inner tag defined as a field,
13041  * we have to define it first, by reusing one of L1 entries.
13042  *
13043  * In step 2 we are replacing one of existing filter types with
13044  * a new one for QinQ.
13045  * As we reusing L1 and replacing L2, some of the default filter
13046  * types will disappear,which depends on L1 and L2 entries we reuse.
13047  *
13048  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13049  *
13050  * 1.   Create L1 filter of outer vlan (12b) which will be in use
13051  *              later when we define the cloud filter.
13052  *      a.      Valid_flags.replace_cloud = 0
13053  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
13054  *      c.      New_filter = 0x10
13055  *      d.      TR bit = 0xff (optional, not used here)
13056  *      e.      Buffer – 2 entries:
13057  *              i.      Byte 0 = 8 (outer vlan FV index).
13058  *                      Byte 1 = 0 (rsv)
13059  *                      Byte 2-3 = 0x0fff
13060  *              ii.     Byte 0 = 37 (inner vlan FV index).
13061  *                      Byte 1 =0 (rsv)
13062  *                      Byte 2-3 = 0x0fff
13063  *
13064  * Step 2:
13065  * 2.   Create cloud filter using two L1 filters entries: stag and
13066  *              new filter(outer vlan+ inner vlan)
13067  *      a.      Valid_flags.replace_cloud = 1
13068  *      b.      Old_filter = 1 (instead of outer IP)
13069  *      c.      New_filter = 0x10
13070  *      d.      Buffer – 2 entries:
13071  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
13072  *                      Byte 1-3 = 0 (rsv)
13073  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13074  *                      Byte 9-11 = 0 (rsv)
13075  */
13076 static int
13077 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13078 {
13079         int ret = -ENOTSUP;
13080         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
13081         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
13082         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13083         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13084
13085         if (pf->support_multi_driver) {
13086                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13087                 return ret;
13088         }
13089
13090         /* Init */
13091         memset(&filter_replace, 0,
13092                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13093         memset(&filter_replace_buf, 0,
13094                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13095
13096         /* create L1 filter */
13097         filter_replace.old_filter_type =
13098                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13099         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13100         filter_replace.tr_bit = 0;
13101
13102         /* Prepare the buffer, 2 entries */
13103         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13104         filter_replace_buf.data[0] |=
13105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13106         /* Field Vector 12b mask */
13107         filter_replace_buf.data[2] = 0xff;
13108         filter_replace_buf.data[3] = 0x0f;
13109         filter_replace_buf.data[4] =
13110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13111         filter_replace_buf.data[4] |=
13112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13113         /* Field Vector 12b mask */
13114         filter_replace_buf.data[6] = 0xff;
13115         filter_replace_buf.data[7] = 0x0f;
13116         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13117                         &filter_replace_buf);
13118         if (ret != I40E_SUCCESS)
13119                 return ret;
13120
13121         if (filter_replace.old_filter_type !=
13122             filter_replace.new_filter_type)
13123                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13124                             " original: 0x%x, new: 0x%x",
13125                             dev->device->name,
13126                             filter_replace.old_filter_type,
13127                             filter_replace.new_filter_type);
13128
13129         /* Apply the second L2 cloud filter */
13130         memset(&filter_replace, 0,
13131                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13132         memset(&filter_replace_buf, 0,
13133                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13134
13135         /* create L2 filter, input for L2 filter will be L1 filter  */
13136         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13137         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13138         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13139
13140         /* Prepare the buffer, 2 entries */
13141         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13142         filter_replace_buf.data[0] |=
13143                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13144         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13145         filter_replace_buf.data[4] |=
13146                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13147         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13148                         &filter_replace_buf);
13149         if (!ret && (filter_replace.old_filter_type !=
13150                      filter_replace.new_filter_type))
13151                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13152                             " original: 0x%x, new: 0x%x",
13153                             dev->device->name,
13154                             filter_replace.old_filter_type,
13155                             filter_replace.new_filter_type);
13156
13157         return ret;
13158 }
13159
13160 int
13161 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13162                    const struct rte_flow_action_rss *in)
13163 {
13164         if (in->key_len > RTE_DIM(out->key) ||
13165             in->queue_num > RTE_DIM(out->queue))
13166                 return -EINVAL;
13167         if (!in->key && in->key_len)
13168                 return -EINVAL;
13169         out->conf = (struct rte_flow_action_rss){
13170                 .func = in->func,
13171                 .level = in->level,
13172                 .types = in->types,
13173                 .key_len = in->key_len,
13174                 .queue_num = in->queue_num,
13175                 .queue = memcpy(out->queue, in->queue,
13176                                 sizeof(*in->queue) * in->queue_num),
13177         };
13178         if (in->key)
13179                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13180         return 0;
13181 }
13182
13183 /* Write HENA register to enable hash */
13184 static int
13185 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13186 {
13187         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13188         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13189         uint64_t hena;
13190         int ret;
13191
13192         ret = i40e_set_rss_key(pf->main_vsi, key,
13193                                rss_conf->conf.key_len);
13194         if (ret)
13195                 return ret;
13196
13197         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13198         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13199         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13200         I40E_WRITE_FLUSH(hw);
13201
13202         return 0;
13203 }
13204
13205 /* Configure hash input set */
13206 static int
13207 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13208 {
13209         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13210         struct rte_eth_input_set_conf conf;
13211         uint64_t mask0;
13212         int ret = 0;
13213         uint32_t j;
13214         int i;
13215         static const struct {
13216                 uint64_t type;
13217                 enum rte_eth_input_set_field field;
13218         } inset_match_table[] = {
13219                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13220                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13221                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13222                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13223                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13224                         RTE_ETH_INPUT_SET_UNKNOWN},
13225                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13226                         RTE_ETH_INPUT_SET_UNKNOWN},
13227
13228                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13229                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13230                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13231                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13232                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13233                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13234                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13235                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13236
13237                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13238                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13239                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13240                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13241                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13242                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13243                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13244                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13245
13246                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13247                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13248                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13249                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13250                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13251                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13252                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13253                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13254
13255                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13256                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13257                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13258                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13259                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13260                         RTE_ETH_INPUT_SET_UNKNOWN},
13261                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13262                         RTE_ETH_INPUT_SET_UNKNOWN},
13263
13264                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13265                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13266                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13267                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13268                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13269                         RTE_ETH_INPUT_SET_UNKNOWN},
13270                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13271                         RTE_ETH_INPUT_SET_UNKNOWN},
13272
13273                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13274                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13275                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13276                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13277                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13278                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13279                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13280                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13281
13282                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13283                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13284                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13285                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13286                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13287                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13288                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13289                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13290
13291                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13292                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13293                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13294                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13295                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13296                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13297                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13298                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13299
13300                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13301                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13302                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13303                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13304                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13305                         RTE_ETH_INPUT_SET_UNKNOWN},
13306                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13307                         RTE_ETH_INPUT_SET_UNKNOWN},
13308         };
13309
13310         mask0 = types & pf->adapter->flow_types_mask;
13311         conf.op = RTE_ETH_INPUT_SET_SELECT;
13312         conf.inset_size = 0;
13313         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13314                 if (mask0 & (1ULL << i)) {
13315                         conf.flow_type = i;
13316                         break;
13317                 }
13318         }
13319
13320         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13321                 if ((types & inset_match_table[j].type) ==
13322                     inset_match_table[j].type) {
13323                         if (inset_match_table[j].field ==
13324                             RTE_ETH_INPUT_SET_UNKNOWN)
13325                                 return -EINVAL;
13326
13327                         conf.field[conf.inset_size] =
13328                                 inset_match_table[j].field;
13329                         conf.inset_size++;
13330                 }
13331         }
13332
13333         if (conf.inset_size) {
13334                 ret = i40e_hash_filter_inset_select(hw, &conf);
13335                 if (ret)
13336                         return ret;
13337         }
13338
13339         return ret;
13340 }
13341
13342 /* Look up the conflicted rule then mark it as invalid */
13343 static void
13344 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13345                 struct i40e_rte_flow_rss_conf *conf)
13346 {
13347         struct i40e_rss_filter *rss_item;
13348         uint64_t rss_inset;
13349
13350         /* Clear input set bits before comparing the pctype */
13351         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13352                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13353
13354         /* Look up the conflicted rule then mark it as invalid */
13355         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13356                 if (!rss_item->rss_filter_info.valid)
13357                         continue;
13358
13359                 if (conf->conf.queue_num &&
13360                     rss_item->rss_filter_info.conf.queue_num)
13361                         rss_item->rss_filter_info.valid = false;
13362
13363                 if (conf->conf.types &&
13364                     (rss_item->rss_filter_info.conf.types &
13365                     rss_inset) ==
13366                     (conf->conf.types & rss_inset))
13367                         rss_item->rss_filter_info.valid = false;
13368
13369                 if (conf->conf.func ==
13370                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13371                     rss_item->rss_filter_info.conf.func ==
13372                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13373                         rss_item->rss_filter_info.valid = false;
13374         }
13375 }
13376
13377 /* Configure RSS hash function */
13378 static int
13379 i40e_rss_config_hash_function(struct i40e_pf *pf,
13380                 struct i40e_rte_flow_rss_conf *conf)
13381 {
13382         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13383         uint32_t reg, i;
13384         uint64_t mask0;
13385         uint16_t j;
13386
13387         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13388                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13389                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13390                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13391                         I40E_WRITE_FLUSH(hw);
13392                         i40e_rss_mark_invalid_rule(pf, conf);
13393
13394                         return 0;
13395                 }
13396                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13397
13398                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13399                 I40E_WRITE_FLUSH(hw);
13400                 i40e_rss_mark_invalid_rule(pf, conf);
13401         } else if (conf->conf.func ==
13402                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13403                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13404
13405                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13406                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13407                         if (mask0 & (1UL << i))
13408                                 break;
13409                 }
13410
13411                 if (i == UINT64_BIT)
13412                         return -EINVAL;
13413
13414                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13415                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13416                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13417                                 i40e_write_global_rx_ctl(hw,
13418                                         I40E_GLQF_HSYM(j),
13419                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13420                 }
13421         }
13422
13423         return 0;
13424 }
13425
13426 /* Enable RSS according to the configuration */
13427 static int
13428 i40e_rss_enable_hash(struct i40e_pf *pf,
13429                 struct i40e_rte_flow_rss_conf *conf)
13430 {
13431         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13432         struct i40e_rte_flow_rss_conf rss_conf;
13433
13434         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13435                 return -ENOTSUP;
13436
13437         memset(&rss_conf, 0, sizeof(rss_conf));
13438         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13439
13440         /* Configure hash input set */
13441         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13442                 return -EINVAL;
13443
13444         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13445             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13446                 /* Random default keys */
13447                 static uint32_t rss_key_default[] = {0x6b793944,
13448                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13449                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13450                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13451
13452                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13453                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13454                                 sizeof(uint32_t);
13455                 PMD_DRV_LOG(INFO,
13456                         "No valid RSS key config for i40e, using default\n");
13457         }
13458
13459         rss_conf.conf.types |= rss_info->conf.types;
13460         i40e_rss_hash_set(pf, &rss_conf);
13461
13462         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13463                 i40e_rss_config_hash_function(pf, conf);
13464
13465         i40e_rss_mark_invalid_rule(pf, conf);
13466
13467         return 0;
13468 }
13469
13470 /* Configure RSS queue region */
13471 static int
13472 i40e_rss_config_queue_region(struct i40e_pf *pf,
13473                 struct i40e_rte_flow_rss_conf *conf)
13474 {
13475         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13476         uint32_t lut = 0;
13477         uint16_t j, num;
13478         uint32_t i;
13479
13480         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13481          * It's necessary to calculate the actual PF queues that are configured.
13482          */
13483         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13484                 num = i40e_pf_calc_configured_queues_num(pf);
13485         else
13486                 num = pf->dev_data->nb_rx_queues;
13487
13488         num = RTE_MIN(num, conf->conf.queue_num);
13489         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13490                         num);
13491
13492         if (num == 0) {
13493                 PMD_DRV_LOG(ERR,
13494                         "No PF queues are configured to enable RSS for port %u",
13495                         pf->dev_data->port_id);
13496                 return -ENOTSUP;
13497         }
13498
13499         /* Fill in redirection table */
13500         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13501                 if (j == num)
13502                         j = 0;
13503                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13504                         hw->func_caps.rss_table_entry_width) - 1));
13505                 if ((i & 3) == 3)
13506                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13507         }
13508
13509         i40e_rss_mark_invalid_rule(pf, conf);
13510
13511         return 0;
13512 }
13513
13514 /* Configure RSS hash function to default */
13515 static int
13516 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13517                 struct i40e_rte_flow_rss_conf *conf)
13518 {
13519         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13520         uint32_t i, reg;
13521         uint64_t mask0;
13522         uint16_t j;
13523
13524         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13525                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13526                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13527                         PMD_DRV_LOG(DEBUG,
13528                                 "Hash function already set to Toeplitz");
13529                         I40E_WRITE_FLUSH(hw);
13530
13531                         return 0;
13532                 }
13533                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13534
13535                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13536                 I40E_WRITE_FLUSH(hw);
13537         } else if (conf->conf.func ==
13538                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13539                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13540
13541                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13542                         if (mask0 & (1UL << i))
13543                                 break;
13544                 }
13545
13546                 if (i == UINT64_BIT)
13547                         return -EINVAL;
13548
13549                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13550                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13551                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13552                                 i40e_write_global_rx_ctl(hw,
13553                                         I40E_GLQF_HSYM(j),
13554                                         0);
13555                 }
13556         }
13557
13558         return 0;
13559 }
13560
13561 /* Disable RSS hash and configure default input set */
13562 static int
13563 i40e_rss_disable_hash(struct i40e_pf *pf,
13564                 struct i40e_rte_flow_rss_conf *conf)
13565 {
13566         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13567         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13568         struct i40e_rte_flow_rss_conf rss_conf;
13569         uint32_t i;
13570
13571         memset(&rss_conf, 0, sizeof(rss_conf));
13572         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13573
13574         /* Disable RSS hash */
13575         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13576         i40e_rss_hash_set(pf, &rss_conf);
13577
13578         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13579                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13580                     !(conf->conf.types & (1ULL << i)))
13581                         continue;
13582
13583                 /* Configure default input set */
13584                 struct rte_eth_input_set_conf input_conf = {
13585                         .op = RTE_ETH_INPUT_SET_SELECT,
13586                         .flow_type = i,
13587                         .inset_size = 1,
13588                 };
13589                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13590                 i40e_hash_filter_inset_select(hw, &input_conf);
13591         }
13592
13593         rss_info->conf.types = rss_conf.conf.types;
13594
13595         i40e_rss_clear_hash_function(pf, conf);
13596
13597         return 0;
13598 }
13599
13600 /* Configure RSS queue region to default */
13601 static int
13602 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13603 {
13604         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13605         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13606         uint16_t queue[I40E_MAX_Q_PER_TC];
13607         uint32_t num_rxq, i;
13608         uint32_t lut = 0;
13609         uint16_t j, num;
13610
13611         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13612
13613         for (j = 0; j < num_rxq; j++)
13614                 queue[j] = j;
13615
13616         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13617          * It's necessary to calculate the actual PF queues that are configured.
13618          */
13619         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13620                 num = i40e_pf_calc_configured_queues_num(pf);
13621         else
13622                 num = pf->dev_data->nb_rx_queues;
13623
13624         num = RTE_MIN(num, num_rxq);
13625         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13626                         num);
13627
13628         if (num == 0) {
13629                 PMD_DRV_LOG(ERR,
13630                         "No PF queues are configured to enable RSS for port %u",
13631                         pf->dev_data->port_id);
13632                 return -ENOTSUP;
13633         }
13634
13635         /* Fill in redirection table */
13636         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13637                 if (j == num)
13638                         j = 0;
13639                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13640                         hw->func_caps.rss_table_entry_width) - 1));
13641                 if ((i & 3) == 3)
13642                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13643         }
13644
13645         rss_info->conf.queue_num = 0;
13646         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13647
13648         return 0;
13649 }
13650
13651 int
13652 i40e_config_rss_filter(struct i40e_pf *pf,
13653                 struct i40e_rte_flow_rss_conf *conf, bool add)
13654 {
13655         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13656         struct rte_flow_action_rss update_conf = rss_info->conf;
13657         int ret = 0;
13658
13659         if (add) {
13660                 if (conf->conf.queue_num) {
13661                         /* Configure RSS queue region */
13662                         ret = i40e_rss_config_queue_region(pf, conf);
13663                         if (ret)
13664                                 return ret;
13665
13666                         update_conf.queue_num = conf->conf.queue_num;
13667                         update_conf.queue = conf->conf.queue;
13668                 } else if (conf->conf.func ==
13669                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13670                         /* Configure hash function */
13671                         ret = i40e_rss_config_hash_function(pf, conf);
13672                         if (ret)
13673                                 return ret;
13674
13675                         update_conf.func = conf->conf.func;
13676                 } else {
13677                         /* Configure hash enable and input set */
13678                         ret = i40e_rss_enable_hash(pf, conf);
13679                         if (ret)
13680                                 return ret;
13681
13682                         update_conf.types |= conf->conf.types;
13683                         update_conf.key = conf->conf.key;
13684                         update_conf.key_len = conf->conf.key_len;
13685                 }
13686
13687                 /* Update RSS info in pf */
13688                 if (i40e_rss_conf_init(rss_info, &update_conf))
13689                         return -EINVAL;
13690         } else {
13691                 if (!conf->valid)
13692                         return 0;
13693
13694                 if (conf->conf.queue_num)
13695                         i40e_rss_clear_queue_region(pf);
13696                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13697                         i40e_rss_clear_hash_function(pf, conf);
13698                 else
13699                         i40e_rss_disable_hash(pf, conf);
13700         }
13701
13702         return 0;
13703 }
13704
13705 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13706 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13707 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13708 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13709 #endif
13710 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13711 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13712 #endif
13713 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13714 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13715 #endif
13716
13717 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13718                               ETH_I40E_FLOATING_VEB_ARG "=1"
13719                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13720                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13721                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13722                               ETH_I40E_USE_LATEST_VEC "=0|1");