drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline void
 631 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 632 {
 633         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 634         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 635                     "with value 0x%08x",
 636                     reg_addr, reg_val);
 637 }
 638
 639 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 640 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 641 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 642
 643 #ifndef I40E_GLQF_ORT
 644 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 645 #endif
 646 #ifndef I40E_GLQF_PIT
 647 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 648 #endif
 649 #ifndef I40E_GLQF_L3_MAP
 650 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 651 #endif
 652
 653 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 654 {
 655         /*
 656          * Initialize registers for parsing packet type of QinQ
 657          * This should be removed from code once proper
 658          * configuration API is added to avoid configuration conflicts
 659          * between ports of the same device.
 660          */
 661         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 662         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 663         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 664 }
 665
 666 static inline void i40e_config_automask(struct i40e_pf *pf)
 667 {
 668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 669         uint32_t val;
 670
 671         /* INTENA flag is not auto-cleared for interrupt */
 672         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 673         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 674                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 675
 676         /* If support multi-driver, PF will use INT0. */
 677         if (!pf->support_multi_driver)
 678                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 679
 680         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 681 }
 682
 683 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 684
 685 /*
 686  * Add a ethertype filter to drop all flow control frames transmitted
 687  * from VSIs.
 688 */
 689 static void
 690 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 691 {
 692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 693         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 694                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 695                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 696         int ret;
 697
 698         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 699                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 700                                 pf->main_vsi_seid, 0,
 701                                 TRUE, NULL, NULL);
 702         if (ret)
 703                 PMD_INIT_LOG(ERR,
 704                         "Failed to add filter to drop flow control frames from VSIs.");
 705 }
 706
 707 static int
 708 floating_veb_list_handler(__rte_unused const char *key,
 709                           const char *floating_veb_value,
 710                           void *opaque)
 711 {
 712         int idx = 0;
 713         unsigned int count = 0;
 714         char *end = NULL;
 715         int min, max;
 716         bool *vf_floating_veb = opaque;
 717
 718         while (isblank(*floating_veb_value))
 719                 floating_veb_value++;
 720
 721         /* Reset floating VEB configuration for VFs */
 722         for (idx = 0; idx < I40E_MAX_VF; idx++)
 723                 vf_floating_veb[idx] = false;
 724
 725         min = I40E_MAX_VF;
 726         do {
 727                 while (isblank(*floating_veb_value))
 728                         floating_veb_value++;
 729                 if (*floating_veb_value == '\0')
 730                         return -1;
 731                 errno = 0;
 732                 idx = strtoul(floating_veb_value, &end, 10);
 733                 if (errno || end == NULL)
 734                         return -1;
 735                 while (isblank(*end))
 736                         end++;
 737                 if (*end == '-') {
 738                         min = idx;
 739                 } else if ((*end == ';') || (*end == '\0')) {
 740                         max = idx;
 741                         if (min == I40E_MAX_VF)
 742                                 min = idx;
 743                         if (max >= I40E_MAX_VF)
 744                                 max = I40E_MAX_VF - 1;
 745                         for (idx = min; idx <= max; idx++) {
 746                                 vf_floating_veb[idx] = true;
 747                                 count++;
 748                         }
 749                         min = I40E_MAX_VF;
 750                 } else {
 751                         return -1;
 752                 }
 753                 floating_veb_value = end + 1;
 754         } while (*end != '\0');
 755
 756         if (count == 0)
 757                 return -1;
 758
 759         return 0;
 760 }
 761
 762 static void
 763 config_vf_floating_veb(struct rte_devargs *devargs,
 764                        uint16_t floating_veb,
 765                        bool *vf_floating_veb)
 766 {
 767         struct rte_kvargs *kvlist;
 768         int i;
 769         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 770
 771         if (!floating_veb)
 772                 return;
 773         /* All the VFs attach to the floating VEB by default
 774          * when the floating VEB is enabled.
 775          */
 776         for (i = 0; i < I40E_MAX_VF; i++)
 777                 vf_floating_veb[i] = true;
 778
 779         if (devargs == NULL)
 780                 return;
 781
 782         kvlist = rte_kvargs_parse(devargs->args, NULL);
 783         if (kvlist == NULL)
 784                 return;
 785
 786         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 787                 rte_kvargs_free(kvlist);
 788                 return;
 789         }
 790         /* When the floating_veb_list parameter exists, all the VFs
 791          * will attach to the legacy VEB firstly, then configure VFs
 792          * to the floating VEB according to the floating_veb_list.
 793          */
 794         if (rte_kvargs_process(kvlist, floating_veb_list,
 795                                floating_veb_list_handler,
 796                                vf_floating_veb) < 0) {
 797                 rte_kvargs_free(kvlist);
 798                 return;
 799         }
 800         rte_kvargs_free(kvlist);
 801 }
 802
 803 static int
 804 i40e_check_floating_handler(__rte_unused const char *key,
 805                             const char *value,
 806                             __rte_unused void *opaque)
 807 {
 808         if (strcmp(value, "1"))
 809                 return -1;
 810
 811         return 0;
 812 }
 813
 814 static int
 815 is_floating_veb_supported(struct rte_devargs *devargs)
 816 {
 817         struct rte_kvargs *kvlist;
 818         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 819
 820         if (devargs == NULL)
 821                 return 0;
 822
 823         kvlist = rte_kvargs_parse(devargs->args, NULL);
 824         if (kvlist == NULL)
 825                 return 0;
 826
 827         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 828                 rte_kvargs_free(kvlist);
 829                 return 0;
 830         }
 831         /* Floating VEB is enabled when there's key-value:
 832          * enable_floating_veb=1
 833          */
 834         if (rte_kvargs_process(kvlist, floating_veb_key,
 835                                i40e_check_floating_handler, NULL) < 0) {
 836                 rte_kvargs_free(kvlist);
 837                 return 0;
 838         }
 839         rte_kvargs_free(kvlist);
 840
 841         return 1;
 842 }
 843
 844 static void
 845 config_floating_veb(struct rte_eth_dev *dev)
 846 {
 847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850
 851         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 852
 853         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 854                 pf->floating_veb =
 855                         is_floating_veb_supported(pci_dev->device.devargs);
 856                 config_vf_floating_veb(pci_dev->device.devargs,
 857                                        pf->floating_veb,
 858                                        pf->floating_veb_list);
 859         } else {
 860                 pf->floating_veb = false;
 861         }
 862 }
 863
 864 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 865 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 866
 867 static int
 868 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 869 {
 870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 871         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 872         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 873         int ret;
 874
 875         struct rte_hash_parameters ethertype_hash_params = {
 876                 .name = ethertype_hash_name,
 877                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 878                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 879                 .hash_func = rte_hash_crc,
 880                 .hash_func_init_val = 0,
 881                 .socket_id = rte_socket_id(),
 882         };
 883
 884         /* Initialize ethertype filter rule list and hash */
 885         TAILQ_INIT(&ethertype_rule->ethertype_list);
 886         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 887                  "ethertype_%s", dev->device->name);
 888         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 889         if (!ethertype_rule->hash_table) {
 890                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 891                 return -EINVAL;
 892         }
 893         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 894                                        sizeof(struct i40e_ethertype_filter *) *
 895                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 896                                        0);
 897         if (!ethertype_rule->hash_map) {
 898                 PMD_INIT_LOG(ERR,
 899                              "Failed to allocate memory for ethertype hash map!");
 900                 ret = -ENOMEM;
 901                 goto err_ethertype_hash_map_alloc;
 902         }
 903
 904         return 0;
 905
 906 err_ethertype_hash_map_alloc:
 907         rte_hash_free(ethertype_rule->hash_table);
 908
 909         return ret;
 910 }
 911
 912 static int
 913 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 917         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 918         int ret;
 919
 920         struct rte_hash_parameters tunnel_hash_params = {
 921                 .name = tunnel_hash_name,
 922                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 923                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 924                 .hash_func = rte_hash_crc,
 925                 .hash_func_init_val = 0,
 926                 .socket_id = rte_socket_id(),
 927         };
 928
 929         /* Initialize tunnel filter rule list and hash */
 930         TAILQ_INIT(&tunnel_rule->tunnel_list);
 931         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 932                  "tunnel_%s", dev->device->name);
 933         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 934         if (!tunnel_rule->hash_table) {
 935                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 936                 return -EINVAL;
 937         }
 938         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 939                                     sizeof(struct i40e_tunnel_filter *) *
 940                                     I40E_MAX_TUNNEL_FILTER_NUM,
 941                                     0);
 942         if (!tunnel_rule->hash_map) {
 943                 PMD_INIT_LOG(ERR,
 944                              "Failed to allocate memory for tunnel hash map!");
 945                 ret = -ENOMEM;
 946                 goto err_tunnel_hash_map_alloc;
 947         }
 948
 949         return 0;
 950
 951 err_tunnel_hash_map_alloc:
 952         rte_hash_free(tunnel_rule->hash_table);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_fdir_info *fdir_info = &pf->fdir;
 962         char fdir_hash_name[RTE_HASH_NAMESIZE];
 963         int ret;
 964
 965         struct rte_hash_parameters fdir_hash_params = {
 966                 .name = fdir_hash_name,
 967                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 968                 .key_len = sizeof(struct i40e_fdir_input),
 969                 .hash_func = rte_hash_crc,
 970                 .hash_func_init_val = 0,
 971                 .socket_id = rte_socket_id(),
 972         };
 973
 974         /* Initialize flow director filter rule list and hash */
 975         TAILQ_INIT(&fdir_info->fdir_list);
 976         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 977                  "fdir_%s", dev->device->name);
 978         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 979         if (!fdir_info->hash_table) {
 980                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 981                 return -EINVAL;
 982         }
 983         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 984                                           sizeof(struct i40e_fdir_filter *) *
 985                                           I40E_MAX_FDIR_FILTER_NUM,
 986                                           0);
 987         if (!fdir_info->hash_map) {
 988                 PMD_INIT_LOG(ERR,
 989                              "Failed to allocate memory for fdir hash map!");
 990                 ret = -ENOMEM;
 991                 goto err_fdir_hash_map_alloc;
 992         }
 993         return 0;
 994
 995 err_fdir_hash_map_alloc:
 996         rte_hash_free(fdir_info->hash_table);
 997
 998         return ret;
 999 }
1000
1001 static void
1002 i40e_init_customized_info(struct i40e_pf *pf)
1003 {
1004         int i;
1005
1006         /* Initialize customized pctype */
1007         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1008                 pf->customized_pctype[i].index = i;
1009                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1010                 pf->customized_pctype[i].valid = false;
1011         }
1012
1013         pf->gtp_support = false;
1014 }
1015
1016 void
1017 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1018 {
1019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1021         struct i40e_queue_regions *info = &pf->queue_region;
1022         uint16_t i;
1023
1024         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1025                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1026
1027         memset(info, 0, sizeof(struct i40e_queue_regions));
1028 }
1029
1030 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1031
1032 static int
1033 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1034                                const char *value,
1035                                void *opaque)
1036 {
1037         struct i40e_pf *pf;
1038         unsigned long support_multi_driver;
1039         char *end;
1040
1041         pf = (struct i40e_pf *)opaque;
1042
1043         errno = 0;
1044         support_multi_driver = strtoul(value, &end, 10);
1045         if (errno != 0 || end == value || *end != 0) {
1046                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1047                 return -(EINVAL);
1048         }
1049
1050         if (support_multi_driver == 1 || support_multi_driver == 0)
1051                 pf->support_multi_driver = (bool)support_multi_driver;
1052         else
1053                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1054                             "enable global configuration by default."
1055                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1056         return 0;
1057 }
1058
1059 static int
1060 i40e_support_multi_driver(struct rte_eth_dev *dev)
1061 {
1062         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1063         static const char *const valid_keys[] = {
1064                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1065         struct rte_kvargs *kvlist;
1066
1067         /* Enable global configuration by default */
1068         pf->support_multi_driver = false;
1069
1070         if (!dev->device->devargs)
1071                 return 0;
1072
1073         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1074         if (!kvlist)
1075                 return -EINVAL;
1076
1077         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1078                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1079                             "the first invalid or last valid one is used !",
1080                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1081
1082         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1083                                i40e_parse_multi_drv_handler, pf) < 0) {
1084                 rte_kvargs_free(kvlist);
1085                 return -EINVAL;
1086         }
1087
1088         rte_kvargs_free(kvlist);
1089         return 0;
1090 }
1091
1092 static int
1093 eth_i40e_dev_init(struct rte_eth_dev *dev)
1094 {
1095         struct rte_pci_device *pci_dev;
1096         struct rte_intr_handle *intr_handle;
1097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1098         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1099         struct i40e_vsi *vsi;
1100         int ret;
1101         uint32_t len;
1102         uint8_t aq_fail = 0;
1103
1104         PMD_INIT_FUNC_TRACE();
1105
1106         dev->dev_ops = &i40e_eth_dev_ops;
1107         dev->rx_pkt_burst = i40e_recv_pkts;
1108         dev->tx_pkt_burst = i40e_xmit_pkts;
1109         dev->tx_pkt_prepare = i40e_prep_pkts;
1110
1111         /* for secondary processes, we don't initialise any further as primary
1112          * has already done this work. Only check we don't need a different
1113          * RX function */
1114         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1115                 i40e_set_rx_function(dev);
1116                 i40e_set_tx_function(dev);
1117                 return 0;
1118         }
1119         i40e_set_default_ptype_table(dev);
1120         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1121         intr_handle = &pci_dev->intr_handle;
1122
1123         rte_eth_copy_pci_info(dev, pci_dev);
1124
1125         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1126         pf->adapter->eth_dev = dev;
1127         pf->dev_data = dev->data;
1128
1129         hw->back = I40E_PF_TO_ADAPTER(pf);
1130         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1131         if (!hw->hw_addr) {
1132                 PMD_INIT_LOG(ERR,
1133                         "Hardware is not available, as address is NULL");
1134                 return -ENODEV;
1135         }
1136
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->device_id = pci_dev->id.device_id;
1139         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1140         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1141         hw->bus.device = pci_dev->addr.devid;
1142         hw->bus.func = pci_dev->addr.function;
1143         hw->adapter_stopped = 0;
1144
1145         /* Check if need to support multi-driver */
1146         i40e_support_multi_driver(dev);
1147
1148         /* Make sure all is clean before doing PF reset */
1149         i40e_clear_hw(hw);
1150
1151         /* Initialize the hardware */
1152         i40e_hw_init(dev);
1153
1154         /* Reset here to make sure all is clean for each PF */
1155         ret = i40e_pf_reset(hw);
1156         if (ret) {
1157                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1158                 return ret;
1159         }
1160
1161         /* Initialize the shared code (base driver) */
1162         ret = i40e_init_shared_code(hw);
1163         if (ret) {
1164                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1165                 return ret;
1166         }
1167
1168         i40e_config_automask(pf);
1169
1170         i40e_set_default_pctype_table(dev);
1171
1172         /*
1173          * To work around the NVM issue, initialize registers
1174          * for packet type of QinQ by software.
1175          * It should be removed once issues are fixed in NVM.
1176          */
1177         if (!pf->support_multi_driver)
1178                 i40e_GLQF_reg_init(hw);
1179
1180         /* Initialize the input set for filters (hash and fd) to default value */
1181         i40e_filter_input_set_init(pf);
1182
1183         /* Initialize the parameters for adminq */
1184         i40e_init_adminq_parameter(hw);
1185         ret = i40e_init_adminq(hw);
1186         if (ret != I40E_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1188                 return -EIO;
1189         }
1190         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1191                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1192                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1193                      ((hw->nvm.version >> 12) & 0xf),
1194                      ((hw->nvm.version >> 4) & 0xff),
1195                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1196
1197         /* initialise the L3_MAP register */
1198         if (!pf->support_multi_driver) {
1199                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1200                                                    0x00000028,  NULL);
1201                 if (ret)
1202                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1203                                      ret);
1204                 PMD_INIT_LOG(DEBUG,
1205                              "Global register 0x%08x is changed with 0x28",
1206                              I40E_GLQF_L3_MAP(40));
1207                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1208         }
1209
1210         /* Need the special FW version to support floating VEB */
1211         config_floating_veb(dev);
1212         /* Clear PXE mode */
1213         i40e_clear_pxe_mode(hw);
1214         i40e_dev_sync_phy_type(hw);
1215
1216         /*
1217          * On X710, performance number is far from the expectation on recent
1218          * firmware versions. The fix for this issue may not be integrated in
1219          * the following firmware version. So the workaround in software driver
1220          * is needed. It needs to modify the initial values of 3 internal only
1221          * registers. Note that the workaround can be removed when it is fixed
1222          * in firmware in the future.
1223          */
1224         i40e_configure_registers(hw);
1225
1226         /* Get hw capabilities */
1227         ret = i40e_get_cap(hw);
1228         if (ret != I40E_SUCCESS) {
1229                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1230                 goto err_get_capabilities;
1231         }
1232
1233         /* Initialize parameters for PF */
1234         ret = i40e_pf_parameter_init(dev);
1235         if (ret != 0) {
1236                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1237                 goto err_parameter_init;
1238         }
1239
1240         /* Initialize the queue management */
1241         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1242         if (ret < 0) {
1243                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1244                 goto err_qp_pool_init;
1245         }
1246         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1247                                 hw->func_caps.num_msix_vectors - 1);
1248         if (ret < 0) {
1249                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1250                 goto err_msix_pool_init;
1251         }
1252
1253         /* Initialize lan hmc */
1254         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1255                                 hw->func_caps.num_rx_qp, 0, 0);
1256         if (ret != I40E_SUCCESS) {
1257                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1258                 goto err_init_lan_hmc;
1259         }
1260
1261         /* Configure lan hmc */
1262         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1263         if (ret != I40E_SUCCESS) {
1264                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1265                 goto err_configure_lan_hmc;
1266         }
1267
1268         /* Get and check the mac address */
1269         i40e_get_mac_addr(hw, hw->mac.addr);
1270         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(ERR, "mac address is not valid");
1272                 ret = -EIO;
1273                 goto err_get_mac_addr;
1274         }
1275         /* Copy the permanent MAC address */
1276         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1277                         (struct ether_addr *) hw->mac.perm_addr);
1278
1279         /* Disable flow control */
1280         hw->fc.requested_mode = I40E_FC_NONE;
1281         i40e_set_fc(hw, &aq_fail, TRUE);
1282
1283         /* Set the global registers with default ether type value */
1284         if (!pf->support_multi_driver) {
1285                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1286                                          ETHER_TYPE_VLAN);
1287                 if (ret != I40E_SUCCESS) {
1288                         PMD_INIT_LOG(ERR,
1289                                      "Failed to set the default outer "
1290                                      "VLAN ether type");
1291                         goto err_setup_pf_switch;
1292                 }
1293         }
1294
1295         /* PF setup, which includes VSI setup */
1296         ret = i40e_pf_setup(pf);
1297         if (ret) {
1298                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1299                 goto err_setup_pf_switch;
1300         }
1301
1302         /* reset all stats of the device, including pf and main vsi */
1303         i40e_dev_stats_reset(dev);
1304
1305         vsi = pf->main_vsi;
1306
1307         /* Disable double vlan by default */
1308         i40e_vsi_config_double_vlan(vsi, FALSE);
1309
1310         /* Disable S-TAG identification when floating_veb is disabled */
1311         if (!pf->floating_veb) {
1312                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1313                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1314                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1315                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1316                 }
1317         }
1318
1319         if (!vsi->max_macaddrs)
1320                 len = ETHER_ADDR_LEN;
1321         else
1322                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1323
1324         /* Should be after VSI initialized */
1325         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1326         if (!dev->data->mac_addrs) {
1327                 PMD_INIT_LOG(ERR,
1328                         "Failed to allocated memory for storing mac address");
1329                 goto err_mac_alloc;
1330         }
1331         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1332                                         &dev->data->mac_addrs[0]);
1333
1334         /* Init dcb to sw mode by default */
1335         ret = i40e_dcb_init_configure(dev, TRUE);
1336         if (ret != I40E_SUCCESS) {
1337                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1338                 pf->flags &= ~I40E_FLAG_DCB;
1339         }
1340         /* Update HW struct after DCB configuration */
1341         i40e_get_cap(hw);
1342
1343         /* initialize pf host driver to setup SRIOV resource if applicable */
1344         i40e_pf_host_init(dev);
1345
1346         /* register callback func to eal lib */
1347         rte_intr_callback_register(intr_handle,
1348                                    i40e_dev_interrupt_handler, dev);
1349
1350         /* configure and enable device interrupt */
1351         i40e_pf_config_irq0(hw, TRUE);
1352         i40e_pf_enable_irq0(hw);
1353
1354         /* enable uio intr after callback register */
1355         rte_intr_enable(intr_handle);
1356
1357         /* By default disable flexible payload in global configuration */
1358         if (!pf->support_multi_driver)
1359                 i40e_flex_payload_reg_set_default(hw);
1360
1361         /*
1362          * Add an ethertype filter to drop all flow control frames transmitted
1363          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1364          * frames to wire.
1365          */
1366         i40e_add_tx_flow_control_drop_filter(pf);
1367
1368         /* Set the max frame size to 0x2600 by default,
1369          * in case other drivers changed the default value.
1370          */
1371         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1372
1373         /* initialize mirror rule list */
1374         TAILQ_INIT(&pf->mirror_list);
1375
1376         /* initialize Traffic Manager configuration */
1377         i40e_tm_conf_init(dev);
1378
1379         /* Initialize customized information */
1380         i40e_init_customized_info(pf);
1381
1382         ret = i40e_init_ethtype_filter_list(dev);
1383         if (ret < 0)
1384                 goto err_init_ethtype_filter_list;
1385         ret = i40e_init_tunnel_filter_list(dev);
1386         if (ret < 0)
1387                 goto err_init_tunnel_filter_list;
1388         ret = i40e_init_fdir_filter_list(dev);
1389         if (ret < 0)
1390                 goto err_init_fdir_filter_list;
1391
1392         /* initialize queue region configuration */
1393         i40e_init_queue_region_conf(dev);
1394
1395         /* initialize rss configuration from rte_flow */
1396         memset(&pf->rss_info, 0,
1397                 sizeof(struct i40e_rte_flow_rss_conf));
1398
1399         return 0;
1400
1401 err_init_fdir_filter_list:
1402         rte_free(pf->tunnel.hash_table);
1403         rte_free(pf->tunnel.hash_map);
1404 err_init_tunnel_filter_list:
1405         rte_free(pf->ethertype.hash_table);
1406         rte_free(pf->ethertype.hash_map);
1407 err_init_ethtype_filter_list:
1408         rte_free(dev->data->mac_addrs);
1409 err_mac_alloc:
1410         i40e_vsi_release(pf->main_vsi);
1411 err_setup_pf_switch:
1412 err_get_mac_addr:
1413 err_configure_lan_hmc:
1414         (void)i40e_shutdown_lan_hmc(hw);
1415 err_init_lan_hmc:
1416         i40e_res_pool_destroy(&pf->msix_pool);
1417 err_msix_pool_init:
1418         i40e_res_pool_destroy(&pf->qp_pool);
1419 err_qp_pool_init:
1420 err_parameter_init:
1421 err_get_capabilities:
1422         (void)i40e_shutdown_adminq(hw);
1423
1424         return ret;
1425 }
1426
1427 static void
1428 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1429 {
1430         struct i40e_ethertype_filter *p_ethertype;
1431         struct i40e_ethertype_rule *ethertype_rule;
1432
1433         ethertype_rule = &pf->ethertype;
1434         /* Remove all ethertype filter rules and hash */
1435         if (ethertype_rule->hash_map)
1436                 rte_free(ethertype_rule->hash_map);
1437         if (ethertype_rule->hash_table)
1438                 rte_hash_free(ethertype_rule->hash_table);
1439
1440         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1441                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1442                              p_ethertype, rules);
1443                 rte_free(p_ethertype);
1444         }
1445 }
1446
1447 static void
1448 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1449 {
1450         struct i40e_tunnel_filter *p_tunnel;
1451         struct i40e_tunnel_rule *tunnel_rule;
1452
1453         tunnel_rule = &pf->tunnel;
1454         /* Remove all tunnel director rules and hash */
1455         if (tunnel_rule->hash_map)
1456                 rte_free(tunnel_rule->hash_map);
1457         if (tunnel_rule->hash_table)
1458                 rte_hash_free(tunnel_rule->hash_table);
1459
1460         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1461                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1462                 rte_free(p_tunnel);
1463         }
1464 }
1465
1466 static void
1467 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1468 {
1469         struct i40e_fdir_filter *p_fdir;
1470         struct i40e_fdir_info *fdir_info;
1471
1472         fdir_info = &pf->fdir;
1473         /* Remove all flow director rules and hash */
1474         if (fdir_info->hash_map)
1475                 rte_free(fdir_info->hash_map);
1476         if (fdir_info->hash_table)
1477                 rte_hash_free(fdir_info->hash_table);
1478
1479         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1480                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1481                 rte_free(p_fdir);
1482         }
1483 }
1484
1485 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1486 {
1487         /*
1488          * Disable by default flexible payload
1489          * for corresponding L2/L3/L4 layers.
1490          */
1491         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1492         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1493         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1494         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1495 }
1496
1497 static int
1498 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1499 {
1500         struct i40e_pf *pf;
1501         struct rte_pci_device *pci_dev;
1502         struct rte_intr_handle *intr_handle;
1503         struct i40e_hw *hw;
1504         struct i40e_filter_control_settings settings;
1505         struct rte_flow *p_flow;
1506         int ret;
1507         uint8_t aq_fail = 0;
1508         int retries = 0;
1509
1510         PMD_INIT_FUNC_TRACE();
1511
1512         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1513                 return 0;
1514
1515         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1518         intr_handle = &pci_dev->intr_handle;
1519
1520         if (hw->adapter_stopped == 0)
1521                 i40e_dev_close(dev);
1522
1523         dev->dev_ops = NULL;
1524         dev->rx_pkt_burst = NULL;
1525         dev->tx_pkt_burst = NULL;
1526
1527         /* Clear PXE mode */
1528         i40e_clear_pxe_mode(hw);
1529
1530         /* Unconfigure filter control */
1531         memset(&settings, 0, sizeof(settings));
1532         ret = i40e_set_filter_control(hw, &settings);
1533         if (ret)
1534                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1535                                         ret);
1536
1537         /* Disable flow control */
1538         hw->fc.requested_mode = I40E_FC_NONE;
1539         i40e_set_fc(hw, &aq_fail, TRUE);
1540
1541         /* uninitialize pf host driver */
1542         i40e_pf_host_uninit(dev);
1543
1544         rte_free(dev->data->mac_addrs);
1545         dev->data->mac_addrs = NULL;
1546
1547         /* disable uio intr before callback unregister */
1548         rte_intr_disable(intr_handle);
1549
1550         /* unregister callback func to eal lib */
1551         do {
1552                 ret = rte_intr_callback_unregister(intr_handle,
1553                                 i40e_dev_interrupt_handler, dev);
1554                 if (ret >= 0) {
1555                         break;
1556                 } else if (ret != -EAGAIN) {
1557                         PMD_INIT_LOG(ERR,
1558                                  "intr callback unregister failed: %d",
1559                                  ret);
1560                         return ret;
1561                 }
1562                 i40e_msec_delay(500);
1563         } while (retries++ < 5);
1564
1565         i40e_rm_ethtype_filter_list(pf);
1566         i40e_rm_tunnel_filter_list(pf);
1567         i40e_rm_fdir_filter_list(pf);
1568
1569         /* Remove all flows */
1570         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1571                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1572                 rte_free(p_flow);
1573         }
1574
1575         /* Remove all Traffic Manager configuration */
1576         i40e_tm_conf_uninit(dev);
1577
1578         return 0;
1579 }
1580
1581 static int
1582 i40e_dev_configure(struct rte_eth_dev *dev)
1583 {
1584         struct i40e_adapter *ad =
1585                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1589         int i, ret;
1590
1591         ret = i40e_dev_sync_phy_type(hw);
1592         if (ret)
1593                 return ret;
1594
1595         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1596          * bulk allocation or vector Rx preconditions we will reset it.
1597          */
1598         ad->rx_bulk_alloc_allowed = true;
1599         ad->rx_vec_allowed = true;
1600         ad->tx_simple_allowed = true;
1601         ad->tx_vec_allowed = true;
1602
1603         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1604                 ret = i40e_fdir_setup(pf);
1605                 if (ret != I40E_SUCCESS) {
1606                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1607                         return -ENOTSUP;
1608                 }
1609                 ret = i40e_fdir_configure(dev);
1610                 if (ret < 0) {
1611                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1612                         goto err;
1613                 }
1614         } else
1615                 i40e_fdir_teardown(pf);
1616
1617         ret = i40e_dev_init_vlan(dev);
1618         if (ret < 0)
1619                 goto err;
1620
1621         /* VMDQ setup.
1622          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1623          *  RSS setting have different requirements.
1624          *  General PMD driver call sequence are NIC init, configure,
1625          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1626          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1627          *  applicable. So, VMDQ setting has to be done before
1628          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1629          *  For RSS setting, it will try to calculate actual configured RX queue
1630          *  number, which will be available after rx_queue_setup(). dev_start()
1631          *  function is good to place RSS setup.
1632          */
1633         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1634                 ret = i40e_vmdq_setup(dev);
1635                 if (ret)
1636                         goto err;
1637         }
1638
1639         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1640                 ret = i40e_dcb_setup(dev);
1641                 if (ret) {
1642                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1643                         goto err_dcb;
1644                 }
1645         }
1646
1647         TAILQ_INIT(&pf->flow_list);
1648
1649         return 0;
1650
1651 err_dcb:
1652         /* need to release vmdq resource if exists */
1653         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1654                 i40e_vsi_release(pf->vmdq[i].vsi);
1655                 pf->vmdq[i].vsi = NULL;
1656         }
1657         rte_free(pf->vmdq);
1658         pf->vmdq = NULL;
1659 err:
1660         /* need to release fdir resource if exists */
1661         i40e_fdir_teardown(pf);
1662         return ret;
1663 }
1664
1665 void
1666 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1667 {
1668         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1670         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1671         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1672         uint16_t msix_vect = vsi->msix_intr;
1673         uint16_t i;
1674
1675         for (i = 0; i < vsi->nb_qps; i++) {
1676                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1677                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1678                 rte_wmb();
1679         }
1680
1681         if (vsi->type != I40E_VSI_SRIOV) {
1682                 if (!rte_intr_allow_others(intr_handle)) {
1683                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1684                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1685                         I40E_WRITE_REG(hw,
1686                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1687                                        0);
1688                 } else {
1689                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1690                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1691                         I40E_WRITE_REG(hw,
1692                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1693                                                        msix_vect - 1), 0);
1694                 }
1695         } else {
1696                 uint32_t reg;
1697                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1698                         vsi->user_param + (msix_vect - 1);
1699
1700                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1701                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1702         }
1703         I40E_WRITE_FLUSH(hw);
1704 }
1705
1706 static void
1707 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1708                        int base_queue, int nb_queue,
1709                        uint16_t itr_idx)
1710 {
1711         int i;
1712         uint32_t val;
1713         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1714         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1715
1716         /* Bind all RX queues to allocated MSIX interrupt */
1717         for (i = 0; i < nb_queue; i++) {
1718                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1719                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1720                         ((base_queue + i + 1) <<
1721                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1722                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1723                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1724
1725                 if (i == nb_queue - 1)
1726                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1727                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1728         }
1729
1730         /* Write first RX queue to Link list register as the head element */
1731         if (vsi->type != I40E_VSI_SRIOV) {
1732                 uint16_t interval =
1733                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1734                                                pf->support_multi_driver);
1735
1736                 if (msix_vect == I40E_MISC_VEC_ID) {
1737                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1738                                        (base_queue <<
1739                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1740                                        (0x0 <<
1741                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1742                         I40E_WRITE_REG(hw,
1743                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1744                                        interval);
1745                 } else {
1746                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1747                                        (base_queue <<
1748                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1749                                        (0x0 <<
1750                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1751                         I40E_WRITE_REG(hw,
1752                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1753                                                        msix_vect - 1),
1754                                        interval);
1755                 }
1756         } else {
1757                 uint32_t reg;
1758
1759                 if (msix_vect == I40E_MISC_VEC_ID) {
1760                         I40E_WRITE_REG(hw,
1761                                        I40E_VPINT_LNKLST0(vsi->user_param),
1762                                        (base_queue <<
1763                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1764                                        (0x0 <<
1765                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1766                 } else {
1767                         /* num_msix_vectors_vf needs to minus irq0 */
1768                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1769                                 vsi->user_param + (msix_vect - 1);
1770
1771                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1772                                        (base_queue <<
1773                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1774                                        (0x0 <<
1775                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1776                 }
1777         }
1778
1779         I40E_WRITE_FLUSH(hw);
1780 }
1781
1782 void
1783 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1784 {
1785         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1788         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1789         uint16_t msix_vect = vsi->msix_intr;
1790         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1791         uint16_t queue_idx = 0;
1792         int record = 0;
1793         int i;
1794
1795         for (i = 0; i < vsi->nb_qps; i++) {
1796                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1797                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1798         }
1799
1800         /* VF bind interrupt */
1801         if (vsi->type == I40E_VSI_SRIOV) {
1802                 __vsi_queues_bind_intr(vsi, msix_vect,
1803                                        vsi->base_queue, vsi->nb_qps,
1804                                        itr_idx);
1805                 return;
1806         }
1807
1808         /* PF & VMDq bind interrupt */
1809         if (rte_intr_dp_is_en(intr_handle)) {
1810                 if (vsi->type == I40E_VSI_MAIN) {
1811                         queue_idx = 0;
1812                         record = 1;
1813                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1814                         struct i40e_vsi *main_vsi =
1815                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1816                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1817                         record = 1;
1818                 }
1819         }
1820
1821         for (i = 0; i < vsi->nb_used_qps; i++) {
1822                 if (nb_msix <= 1) {
1823                         if (!rte_intr_allow_others(intr_handle))
1824                                 /* allow to share MISC_VEC_ID */
1825                                 msix_vect = I40E_MISC_VEC_ID;
1826
1827                         /* no enough msix_vect, map all to one */
1828                         __vsi_queues_bind_intr(vsi, msix_vect,
1829                                                vsi->base_queue + i,
1830                                                vsi->nb_used_qps - i,
1831                                                itr_idx);
1832                         for (; !!record && i < vsi->nb_used_qps; i++)
1833                                 intr_handle->intr_vec[queue_idx + i] =
1834                                         msix_vect;
1835                         break;
1836                 }
1837                 /* 1:1 queue/msix_vect mapping */
1838                 __vsi_queues_bind_intr(vsi, msix_vect,
1839                                        vsi->base_queue + i, 1,
1840                                        itr_idx);
1841                 if (!!record)
1842                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1843
1844                 msix_vect++;
1845                 nb_msix--;
1846         }
1847 }
1848
1849 static void
1850 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1851 {
1852         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1853         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1854         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1855         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1856         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1857         uint16_t msix_intr, i;
1858
1859         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1860                 for (i = 0; i < vsi->nb_msix; i++) {
1861                         msix_intr = vsi->msix_intr + i;
1862                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1863                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1864                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1865                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1866                 }
1867         else
1868                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1869                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1870                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1871                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1872
1873         I40E_WRITE_FLUSH(hw);
1874 }
1875
1876 static void
1877 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1878 {
1879         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1881         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1882         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1883         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1884         uint16_t msix_intr, i;
1885
1886         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1887                 for (i = 0; i < vsi->nb_msix; i++) {
1888                         msix_intr = vsi->msix_intr + i;
1889                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1890                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1891                 }
1892         else
1893                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1894                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1895
1896         I40E_WRITE_FLUSH(hw);
1897 }
1898
1899 static inline uint8_t
1900 i40e_parse_link_speeds(uint16_t link_speeds)
1901 {
1902         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1903
1904         if (link_speeds & ETH_LINK_SPEED_40G)
1905                 link_speed |= I40E_LINK_SPEED_40GB;
1906         if (link_speeds & ETH_LINK_SPEED_25G)
1907                 link_speed |= I40E_LINK_SPEED_25GB;
1908         if (link_speeds & ETH_LINK_SPEED_20G)
1909                 link_speed |= I40E_LINK_SPEED_20GB;
1910         if (link_speeds & ETH_LINK_SPEED_10G)
1911                 link_speed |= I40E_LINK_SPEED_10GB;
1912         if (link_speeds & ETH_LINK_SPEED_1G)
1913                 link_speed |= I40E_LINK_SPEED_1GB;
1914         if (link_speeds & ETH_LINK_SPEED_100M)
1915                 link_speed |= I40E_LINK_SPEED_100MB;
1916
1917         return link_speed;
1918 }
1919
1920 static int
1921 i40e_phy_conf_link(struct i40e_hw *hw,
1922                    uint8_t abilities,
1923                    uint8_t force_speed,
1924                    bool is_up)
1925 {
1926         enum i40e_status_code status;
1927         struct i40e_aq_get_phy_abilities_resp phy_ab;
1928         struct i40e_aq_set_phy_config phy_conf;
1929         enum i40e_aq_phy_type cnt;
1930         uint32_t phy_type_mask = 0;
1931
1932         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1933                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1934                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1935                         I40E_AQ_PHY_FLAG_LOW_POWER;
1936         const uint8_t advt = I40E_LINK_SPEED_40GB |
1937                         I40E_LINK_SPEED_25GB |
1938                         I40E_LINK_SPEED_10GB |
1939                         I40E_LINK_SPEED_1GB |
1940                         I40E_LINK_SPEED_100MB;
1941         int ret = -ENOTSUP;
1942
1943
1944         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1945                                               NULL);
1946         if (status)
1947                 return ret;
1948
1949         /* If link already up, no need to set up again */
1950         if (is_up && phy_ab.phy_type != 0)
1951                 return I40E_SUCCESS;
1952
1953         memset(&phy_conf, 0, sizeof(phy_conf));
1954
1955         /* bits 0-2 use the values from get_phy_abilities_resp */
1956         abilities &= ~mask;
1957         abilities |= phy_ab.abilities & mask;
1958
1959         /* update ablities and speed */
1960         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1961                 phy_conf.link_speed = advt;
1962         else
1963                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1964
1965         phy_conf.abilities = abilities;
1966
1967
1968
1969         /* To enable link, phy_type mask needs to include each type */
1970         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1971                 phy_type_mask |= 1 << cnt;
1972
1973         /* use get_phy_abilities_resp value for the rest */
1974         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1975         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1976                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1977                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1978         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1979         phy_conf.eee_capability = phy_ab.eee_capability;
1980         phy_conf.eeer = phy_ab.eeer_val;
1981         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1982
1983         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1984                     phy_ab.abilities, phy_ab.link_speed);
1985         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1986                     phy_conf.abilities, phy_conf.link_speed);
1987
1988         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1989         if (status)
1990                 return ret;
1991
1992         return I40E_SUCCESS;
1993 }
1994
1995 static int
1996 i40e_apply_link_speed(struct rte_eth_dev *dev)
1997 {
1998         uint8_t speed;
1999         uint8_t abilities = 0;
2000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         struct rte_eth_conf *conf = &dev->data->dev_conf;
2002
2003         speed = i40e_parse_link_speeds(conf->link_speeds);
2004         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2005         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2006                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2007         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2008
2009         return i40e_phy_conf_link(hw, abilities, speed, true);
2010 }
2011
2012 static int
2013 i40e_dev_start(struct rte_eth_dev *dev)
2014 {
2015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct i40e_vsi *main_vsi = pf->main_vsi;
2018         int ret, i;
2019         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2020         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2021         uint32_t intr_vector = 0;
2022         struct i40e_vsi *vsi;
2023
2024         hw->adapter_stopped = 0;
2025
2026         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2027                 PMD_INIT_LOG(ERR,
2028                 "Invalid link_speeds for port %u, autonegotiation disabled",
2029                               dev->data->port_id);
2030                 return -EINVAL;
2031         }
2032
2033         rte_intr_disable(intr_handle);
2034
2035         if ((rte_intr_cap_multiple(intr_handle) ||
2036              !RTE_ETH_DEV_SRIOV(dev).active) &&
2037             dev->data->dev_conf.intr_conf.rxq != 0) {
2038                 intr_vector = dev->data->nb_rx_queues;
2039                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2040                 if (ret)
2041                         return ret;
2042         }
2043
2044         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2045                 intr_handle->intr_vec =
2046                         rte_zmalloc("intr_vec",
2047                                     dev->data->nb_rx_queues * sizeof(int),
2048                                     0);
2049                 if (!intr_handle->intr_vec) {
2050                         PMD_INIT_LOG(ERR,
2051                                 "Failed to allocate %d rx_queues intr_vec",
2052                                 dev->data->nb_rx_queues);
2053                         return -ENOMEM;
2054                 }
2055         }
2056
2057         /* Initialize VSI */
2058         ret = i40e_dev_rxtx_init(pf);
2059         if (ret != I40E_SUCCESS) {
2060                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2061                 goto err_up;
2062         }
2063
2064         /* Map queues with MSIX interrupt */
2065         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2066                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2067         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2068         i40e_vsi_enable_queues_intr(main_vsi);
2069
2070         /* Map VMDQ VSI queues with MSIX interrupt */
2071         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2072                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2073                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2074                                           I40E_ITR_INDEX_DEFAULT);
2075                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2076         }
2077
2078         /* enable FDIR MSIX interrupt */
2079         if (pf->fdir.fdir_vsi) {
2080                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2081                                           I40E_ITR_INDEX_NONE);
2082                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2083         }
2084
2085         /* Enable all queues which have been configured */
2086         ret = i40e_dev_switch_queues(pf, TRUE);
2087         if (ret != I40E_SUCCESS) {
2088                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2089                 goto err_up;
2090         }
2091
2092         /* Enable receiving broadcast packets */
2093         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2094         if (ret != I40E_SUCCESS)
2095                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2096
2097         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2098                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2099                                                 true, NULL);
2100                 if (ret != I40E_SUCCESS)
2101                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2102         }
2103
2104         /* Enable the VLAN promiscuous mode. */
2105         if (pf->vfs) {
2106                 for (i = 0; i < pf->vf_num; i++) {
2107                         vsi = pf->vfs[i].vsi;
2108                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2109                                                      true, NULL);
2110                 }
2111         }
2112
2113         /* Enable mac loopback mode */
2114         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2115             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2116                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2117                 if (ret != I40E_SUCCESS) {
2118                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2119                         goto err_up;
2120                 }
2121         }
2122
2123         /* Apply link configure */
2124         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2125                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2126                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2127                                 ETH_LINK_SPEED_40G)) {
2128                 PMD_DRV_LOG(ERR, "Invalid link setting");
2129                 goto err_up;
2130         }
2131         ret = i40e_apply_link_speed(dev);
2132         if (I40E_SUCCESS != ret) {
2133                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2134                 goto err_up;
2135         }
2136
2137         if (!rte_intr_allow_others(intr_handle)) {
2138                 rte_intr_callback_unregister(intr_handle,
2139                                              i40e_dev_interrupt_handler,
2140                                              (void *)dev);
2141                 /* configure and enable device interrupt */
2142                 i40e_pf_config_irq0(hw, FALSE);
2143                 i40e_pf_enable_irq0(hw);
2144
2145                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2146                         PMD_INIT_LOG(INFO,
2147                                 "lsc won't enable because of no intr multiplex");
2148         } else {
2149                 ret = i40e_aq_set_phy_int_mask(hw,
2150                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2151                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2152                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2153                 if (ret != I40E_SUCCESS)
2154                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2155
2156                 /* Call get_link_info aq commond to enable/disable LSE */
2157                 i40e_dev_link_update(dev, 0);
2158         }
2159
2160         /* enable uio intr after callback register */
2161         rte_intr_enable(intr_handle);
2162
2163         i40e_filter_restore(pf);
2164
2165         if (pf->tm_conf.root && !pf->tm_conf.committed)
2166                 PMD_DRV_LOG(WARNING,
2167                             "please call hierarchy_commit() "
2168                             "before starting the port");
2169
2170         return I40E_SUCCESS;
2171
2172 err_up:
2173         i40e_dev_switch_queues(pf, FALSE);
2174         i40e_dev_clear_queues(dev);
2175
2176         return ret;
2177 }
2178
2179 static void
2180 i40e_dev_stop(struct rte_eth_dev *dev)
2181 {
2182         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2183         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184         struct i40e_vsi *main_vsi = pf->main_vsi;
2185         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2186         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2187         int i;
2188
2189         if (hw->adapter_stopped == 1)
2190                 return;
2191         /* Disable all queues */
2192         i40e_dev_switch_queues(pf, FALSE);
2193
2194         /* un-map queues with interrupt registers */
2195         i40e_vsi_disable_queues_intr(main_vsi);
2196         i40e_vsi_queues_unbind_intr(main_vsi);
2197
2198         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2199                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2200                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2201         }
2202
2203         if (pf->fdir.fdir_vsi) {
2204                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2205                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2206         }
2207         /* Clear all queues and release memory */
2208         i40e_dev_clear_queues(dev);
2209
2210         /* Set link down */
2211         i40e_dev_set_link_down(dev);
2212
2213         if (!rte_intr_allow_others(intr_handle))
2214                 /* resume to the default handler */
2215                 rte_intr_callback_register(intr_handle,
2216                                            i40e_dev_interrupt_handler,
2217                                            (void *)dev);
2218
2219         /* Clean datapath event and queue/vec mapping */
2220         rte_intr_efd_disable(intr_handle);
2221         if (intr_handle->intr_vec) {
2222                 rte_free(intr_handle->intr_vec);
2223                 intr_handle->intr_vec = NULL;
2224         }
2225
2226         /* reset hierarchy commit */
2227         pf->tm_conf.committed = false;
2228
2229         hw->adapter_stopped = 1;
2230 }
2231
2232 static void
2233 i40e_dev_close(struct rte_eth_dev *dev)
2234 {
2235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2238         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2239         struct i40e_mirror_rule *p_mirror;
2240         uint32_t reg;
2241         int i;
2242         int ret;
2243
2244         PMD_INIT_FUNC_TRACE();
2245
2246         i40e_dev_stop(dev);
2247
2248         /* Remove all mirror rules */
2249         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2250                 ret = i40e_aq_del_mirror_rule(hw,
2251                                               pf->main_vsi->veb->seid,
2252                                               p_mirror->rule_type,
2253                                               p_mirror->entries,
2254                                               p_mirror->num_entries,
2255                                               p_mirror->id);
2256                 if (ret < 0)
2257                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2258                                     "status = %d, aq_err = %d.", ret,
2259                                     hw->aq.asq_last_status);
2260
2261                 /* remove mirror software resource anyway */
2262                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2263                 rte_free(p_mirror);
2264                 pf->nb_mirror_rule--;
2265         }
2266
2267         i40e_dev_free_queues(dev);
2268
2269         /* Disable interrupt */
2270         i40e_pf_disable_irq0(hw);
2271         rte_intr_disable(intr_handle);
2272
2273         /* shutdown and destroy the HMC */
2274         i40e_shutdown_lan_hmc(hw);
2275
2276         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2277                 i40e_vsi_release(pf->vmdq[i].vsi);
2278                 pf->vmdq[i].vsi = NULL;
2279         }
2280         rte_free(pf->vmdq);
2281         pf->vmdq = NULL;
2282
2283         /* release all the existing VSIs and VEBs */
2284         i40e_fdir_teardown(pf);
2285         i40e_vsi_release(pf->main_vsi);
2286
2287         /* shutdown the adminq */
2288         i40e_aq_queue_shutdown(hw, true);
2289         i40e_shutdown_adminq(hw);
2290
2291         i40e_res_pool_destroy(&pf->qp_pool);
2292         i40e_res_pool_destroy(&pf->msix_pool);
2293
2294         /* Disable flexible payload in global configuration */
2295         if (!pf->support_multi_driver)
2296                 i40e_flex_payload_reg_set_default(hw);
2297
2298         /* force a PF reset to clean anything leftover */
2299         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2300         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2301                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2302         I40E_WRITE_FLUSH(hw);
2303 }
2304
2305 /*
2306  * Reset PF device only to re-initialize resources in PMD layer
2307  */
2308 static int
2309 i40e_dev_reset(struct rte_eth_dev *dev)
2310 {
2311         int ret;
2312
2313         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2314          * its VF to make them align with it. The detailed notification
2315          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2316          * To avoid unexpected behavior in VF, currently reset of PF with
2317          * SR-IOV activation is not supported. It might be supported later.
2318          */
2319         if (dev->data->sriov.active)
2320                 return -ENOTSUP;
2321
2322         ret = eth_i40e_dev_uninit(dev);
2323         if (ret)
2324                 return ret;
2325
2326         ret = eth_i40e_dev_init(dev);
2327
2328         return ret;
2329 }
2330
2331 static void
2332 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2333 {
2334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336         struct i40e_vsi *vsi = pf->main_vsi;
2337         int status;
2338
2339         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2340                                                      true, NULL, true);
2341         if (status != I40E_SUCCESS)
2342                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2343
2344         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2345                                                         TRUE, NULL);
2346         if (status != I40E_SUCCESS)
2347                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2348
2349 }
2350
2351 static void
2352 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2353 {
2354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         struct i40e_vsi *vsi = pf->main_vsi;
2357         int status;
2358
2359         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2360                                                      false, NULL, true);
2361         if (status != I40E_SUCCESS)
2362                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2363
2364         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2365                                                         false, NULL);
2366         if (status != I40E_SUCCESS)
2367                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2368 }
2369
2370 static void
2371 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2372 {
2373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         struct i40e_vsi *vsi = pf->main_vsi;
2376         int ret;
2377
2378         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2379         if (ret != I40E_SUCCESS)
2380                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2381 }
2382
2383 static void
2384 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2385 {
2386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct i40e_vsi *vsi = pf->main_vsi;
2389         int ret;
2390
2391         if (dev->data->promiscuous == 1)
2392                 return; /* must remain in all_multicast mode */
2393
2394         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2395                                 vsi->seid, FALSE, NULL);
2396         if (ret != I40E_SUCCESS)
2397                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2398 }
2399
2400 /*
2401  * Set device link up.
2402  */
2403 static int
2404 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2405 {
2406         /* re-apply link speed setting */
2407         return i40e_apply_link_speed(dev);
2408 }
2409
2410 /*
2411  * Set device link down.
2412  */
2413 static int
2414 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2415 {
2416         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2417         uint8_t abilities = 0;
2418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419
2420         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2421         return i40e_phy_conf_link(hw, abilities, speed, false);
2422 }
2423
2424 static __rte_always_inline void
2425 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2426 {
2427 /* Link status registers and values*/
2428 #define I40E_PRTMAC_LINKSTA             0x001E2420
2429 #define I40E_REG_LINK_UP                0x40000080
2430 #define I40E_PRTMAC_MACC                0x001E24E0
2431 #define I40E_REG_MACC_25GB              0x00020000
2432 #define I40E_REG_SPEED_MASK             0x38000000
2433 #define I40E_REG_SPEED_100MB            0x00000000
2434 #define I40E_REG_SPEED_1GB              0x08000000
2435 #define I40E_REG_SPEED_10GB             0x10000000
2436 #define I40E_REG_SPEED_20GB             0x20000000
2437 #define I40E_REG_SPEED_25_40GB          0x18000000
2438         uint32_t link_speed;
2439         uint32_t reg_val;
2440
2441         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2442         link_speed = reg_val & I40E_REG_SPEED_MASK;
2443         reg_val &= I40E_REG_LINK_UP;
2444         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2445
2446         if (unlikely(link->link_status != 0))
2447                 return;
2448
2449         /* Parse the link status */
2450         switch (link_speed) {
2451         case I40E_REG_SPEED_100MB:
2452                 link->link_speed = ETH_SPEED_NUM_100M;
2453                 break;
2454         case I40E_REG_SPEED_1GB:
2455                 link->link_speed = ETH_SPEED_NUM_1G;
2456                 break;
2457         case I40E_REG_SPEED_10GB:
2458                 link->link_speed = ETH_SPEED_NUM_10G;
2459                 break;
2460         case I40E_REG_SPEED_20GB:
2461                 link->link_speed = ETH_SPEED_NUM_20G;
2462                 break;
2463         case I40E_REG_SPEED_25_40GB:
2464                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2465
2466                 if (reg_val & I40E_REG_MACC_25GB)
2467                         link->link_speed = ETH_SPEED_NUM_25G;
2468                 else
2469                         link->link_speed = ETH_SPEED_NUM_40G;
2470
2471                 break;
2472         default:
2473                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2474                 break;
2475         }
2476 }
2477
2478 static __rte_always_inline void
2479 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2480         bool enable_lse)
2481 {
2482 #define CHECK_INTERVAL             100  /* 100ms */
2483 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2484         uint32_t rep_cnt = MAX_REPEAT_TIME;
2485         struct i40e_link_status link_status;
2486         int status;
2487
2488         memset(&link_status, 0, sizeof(link_status));
2489
2490         do {
2491                 memset(&link_status, 0, sizeof(link_status));
2492
2493                 /* Get link status information from hardware */
2494                 status = i40e_aq_get_link_info(hw, enable_lse,
2495                                                 &link_status, NULL);
2496                 if (unlikely(status != I40E_SUCCESS)) {
2497                         link->link_speed = ETH_SPEED_NUM_100M;
2498                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2499                         PMD_DRV_LOG(ERR, "Failed to get link info");
2500                         return;
2501                 }
2502
2503                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2504                 if (unlikely(link->link_status != 0))
2505                         return;
2506
2507                 rte_delay_ms(CHECK_INTERVAL);
2508         } while (--rep_cnt);
2509
2510         /* Parse the link status */
2511         switch (link_status.link_speed) {
2512         case I40E_LINK_SPEED_100MB:
2513                 link->link_speed = ETH_SPEED_NUM_100M;
2514                 break;
2515         case I40E_LINK_SPEED_1GB:
2516                 link->link_speed = ETH_SPEED_NUM_1G;
2517                 break;
2518         case I40E_LINK_SPEED_10GB:
2519                 link->link_speed = ETH_SPEED_NUM_10G;
2520                 break;
2521         case I40E_LINK_SPEED_20GB:
2522                 link->link_speed = ETH_SPEED_NUM_20G;
2523                 break;
2524         case I40E_LINK_SPEED_25GB:
2525                 link->link_speed = ETH_SPEED_NUM_25G;
2526                 break;
2527         case I40E_LINK_SPEED_40GB:
2528                 link->link_speed = ETH_SPEED_NUM_40G;
2529                 break;
2530         default:
2531                 link->link_speed = ETH_SPEED_NUM_100M;
2532                 break;
2533         }
2534 }
2535
2536 int
2537 i40e_dev_link_update(struct rte_eth_dev *dev,
2538                      int wait_to_complete)
2539 {
2540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         struct rte_eth_link link;
2542         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2543         int ret;
2544
2545         memset(&link, 0, sizeof(link));
2546
2547         /* i40e uses full duplex only */
2548         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2549         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2550                         ETH_LINK_SPEED_FIXED);
2551
2552         if (!wait_to_complete)
2553                 update_link_no_wait(hw, &link);
2554         else
2555                 update_link_wait(hw, &link, enable_lse);
2556
2557         ret = rte_eth_linkstatus_set(dev, &link);
2558         i40e_notify_all_vfs_link_status(dev);
2559
2560         return ret;
2561 }
2562
2563 /* Get all the statistics of a VSI */
2564 void
2565 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2566 {
2567         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2568         struct i40e_eth_stats *nes = &vsi->eth_stats;
2569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2570         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2571
2572         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2573                             vsi->offset_loaded, &oes->rx_bytes,
2574                             &nes->rx_bytes);
2575         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2576                             vsi->offset_loaded, &oes->rx_unicast,
2577                             &nes->rx_unicast);
2578         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2579                             vsi->offset_loaded, &oes->rx_multicast,
2580                             &nes->rx_multicast);
2581         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2582                             vsi->offset_loaded, &oes->rx_broadcast,
2583                             &nes->rx_broadcast);
2584         /* exclude CRC bytes */
2585         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2586                 nes->rx_broadcast) * ETHER_CRC_LEN;
2587
2588         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2589                             &oes->rx_discards, &nes->rx_discards);
2590         /* GLV_REPC not supported */
2591         /* GLV_RMPC not supported */
2592         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2593                             &oes->rx_unknown_protocol,
2594                             &nes->rx_unknown_protocol);
2595         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2596                             vsi->offset_loaded, &oes->tx_bytes,
2597                             &nes->tx_bytes);
2598         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2599                             vsi->offset_loaded, &oes->tx_unicast,
2600                             &nes->tx_unicast);
2601         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2602                             vsi->offset_loaded, &oes->tx_multicast,
2603                             &nes->tx_multicast);
2604         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2605                             vsi->offset_loaded,  &oes->tx_broadcast,
2606                             &nes->tx_broadcast);
2607         /* GLV_TDPC not supported */
2608         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2609                             &oes->tx_errors, &nes->tx_errors);
2610         vsi->offset_loaded = true;
2611
2612         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2613                     vsi->vsi_id);
2614         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2615         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2616         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2617         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2618         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2619         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2620                     nes->rx_unknown_protocol);
2621         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2622         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2623         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2624         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2625         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2626         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2627         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2628                     vsi->vsi_id);
2629 }
2630
2631 static void
2632 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2633 {
2634         unsigned int i;
2635         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2636         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2637
2638         /* Get rx/tx bytes of internal transfer packets */
2639         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2640                         I40E_GLV_GORCL(hw->port),
2641                         pf->offset_loaded,
2642                         &pf->internal_stats_offset.rx_bytes,
2643                         &pf->internal_stats.rx_bytes);
2644
2645         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2646                         I40E_GLV_GOTCL(hw->port),
2647                         pf->offset_loaded,
2648                         &pf->internal_stats_offset.tx_bytes,
2649                         &pf->internal_stats.tx_bytes);
2650         /* Get total internal rx packet count */
2651         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2652                             I40E_GLV_UPRCL(hw->port),
2653                             pf->offset_loaded,
2654                             &pf->internal_stats_offset.rx_unicast,
2655                             &pf->internal_stats.rx_unicast);
2656         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2657                             I40E_GLV_MPRCL(hw->port),
2658                             pf->offset_loaded,
2659                             &pf->internal_stats_offset.rx_multicast,
2660                             &pf->internal_stats.rx_multicast);
2661         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2662                             I40E_GLV_BPRCL(hw->port),
2663                             pf->offset_loaded,
2664                             &pf->internal_stats_offset.rx_broadcast,
2665                             &pf->internal_stats.rx_broadcast);
2666         /* Get total internal tx packet count */
2667         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2668                             I40E_GLV_UPTCL(hw->port),
2669                             pf->offset_loaded,
2670                             &pf->internal_stats_offset.tx_unicast,
2671                             &pf->internal_stats.tx_unicast);
2672         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2673                             I40E_GLV_MPTCL(hw->port),
2674                             pf->offset_loaded,
2675                             &pf->internal_stats_offset.tx_multicast,
2676                             &pf->internal_stats.tx_multicast);
2677         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2678                             I40E_GLV_BPTCL(hw->port),
2679                             pf->offset_loaded,
2680                             &pf->internal_stats_offset.tx_broadcast,
2681                             &pf->internal_stats.tx_broadcast);
2682
2683         /* exclude CRC size */
2684         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2685                 pf->internal_stats.rx_multicast +
2686                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2687
2688         /* Get statistics of struct i40e_eth_stats */
2689         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2690                             I40E_GLPRT_GORCL(hw->port),
2691                             pf->offset_loaded, &os->eth.rx_bytes,
2692                             &ns->eth.rx_bytes);
2693         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2694                             I40E_GLPRT_UPRCL(hw->port),
2695                             pf->offset_loaded, &os->eth.rx_unicast,
2696                             &ns->eth.rx_unicast);
2697         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2698                             I40E_GLPRT_MPRCL(hw->port),
2699                             pf->offset_loaded, &os->eth.rx_multicast,
2700                             &ns->eth.rx_multicast);
2701         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2702                             I40E_GLPRT_BPRCL(hw->port),
2703                             pf->offset_loaded, &os->eth.rx_broadcast,
2704                             &ns->eth.rx_broadcast);
2705         /* Workaround: CRC size should not be included in byte statistics,
2706          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2707          */
2708         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2709                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2710
2711         /* exclude internal rx bytes
2712          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2713          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2714          * value.
2715          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2716          */
2717         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2718                 ns->eth.rx_bytes = 0;
2719         else
2720                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2721
2722         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2723                 ns->eth.rx_unicast = 0;
2724         else
2725                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2726
2727         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2728                 ns->eth.rx_multicast = 0;
2729         else
2730                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2731
2732         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2733                 ns->eth.rx_broadcast = 0;
2734         else
2735                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2736
2737         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2738                             pf->offset_loaded, &os->eth.rx_discards,
2739                             &ns->eth.rx_discards);
2740         /* GLPRT_REPC not supported */
2741         /* GLPRT_RMPC not supported */
2742         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2743                             pf->offset_loaded,
2744                             &os->eth.rx_unknown_protocol,
2745                             &ns->eth.rx_unknown_protocol);
2746         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2747                             I40E_GLPRT_GOTCL(hw->port),
2748                             pf->offset_loaded, &os->eth.tx_bytes,
2749                             &ns->eth.tx_bytes);
2750         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2751                             I40E_GLPRT_UPTCL(hw->port),
2752                             pf->offset_loaded, &os->eth.tx_unicast,
2753                             &ns->eth.tx_unicast);
2754         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2755                             I40E_GLPRT_MPTCL(hw->port),
2756                             pf->offset_loaded, &os->eth.tx_multicast,
2757                             &ns->eth.tx_multicast);
2758         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2759                             I40E_GLPRT_BPTCL(hw->port),
2760                             pf->offset_loaded, &os->eth.tx_broadcast,
2761                             &ns->eth.tx_broadcast);
2762         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2763                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2764
2765         /* exclude internal tx bytes
2766          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2767          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2768          * value.
2769          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2770          */
2771         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2772                 ns->eth.tx_bytes = 0;
2773         else
2774                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2775
2776         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2777                 ns->eth.tx_unicast = 0;
2778         else
2779                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2780
2781         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2782                 ns->eth.tx_multicast = 0;
2783         else
2784                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2785
2786         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2787                 ns->eth.tx_broadcast = 0;
2788         else
2789                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2790
2791         /* GLPRT_TEPC not supported */
2792
2793         /* additional port specific stats */
2794         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2795                             pf->offset_loaded, &os->tx_dropped_link_down,
2796                             &ns->tx_dropped_link_down);
2797         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2798                             pf->offset_loaded, &os->crc_errors,
2799                             &ns->crc_errors);
2800         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2801                             pf->offset_loaded, &os->illegal_bytes,
2802                             &ns->illegal_bytes);
2803         /* GLPRT_ERRBC not supported */
2804         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2805                             pf->offset_loaded, &os->mac_local_faults,
2806                             &ns->mac_local_faults);
2807         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2808                             pf->offset_loaded, &os->mac_remote_faults,
2809                             &ns->mac_remote_faults);
2810         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2811                             pf->offset_loaded, &os->rx_length_errors,
2812                             &ns->rx_length_errors);
2813         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2814                             pf->offset_loaded, &os->link_xon_rx,
2815                             &ns->link_xon_rx);
2816         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2817                             pf->offset_loaded, &os->link_xoff_rx,
2818                             &ns->link_xoff_rx);
2819         for (i = 0; i < 8; i++) {
2820                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2821                                     pf->offset_loaded,
2822                                     &os->priority_xon_rx[i],
2823                                     &ns->priority_xon_rx[i]);
2824                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2825                                     pf->offset_loaded,
2826                                     &os->priority_xoff_rx[i],
2827                                     &ns->priority_xoff_rx[i]);
2828         }
2829         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2830                             pf->offset_loaded, &os->link_xon_tx,
2831                             &ns->link_xon_tx);
2832         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2833                             pf->offset_loaded, &os->link_xoff_tx,
2834                             &ns->link_xoff_tx);
2835         for (i = 0; i < 8; i++) {
2836                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2837                                     pf->offset_loaded,
2838                                     &os->priority_xon_tx[i],
2839                                     &ns->priority_xon_tx[i]);
2840                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2841                                     pf->offset_loaded,
2842                                     &os->priority_xoff_tx[i],
2843                                     &ns->priority_xoff_tx[i]);
2844                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2845                                     pf->offset_loaded,
2846                                     &os->priority_xon_2_xoff[i],
2847                                     &ns->priority_xon_2_xoff[i]);
2848         }
2849         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2850                             I40E_GLPRT_PRC64L(hw->port),
2851                             pf->offset_loaded, &os->rx_size_64,
2852                             &ns->rx_size_64);
2853         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2854                             I40E_GLPRT_PRC127L(hw->port),
2855                             pf->offset_loaded, &os->rx_size_127,
2856                             &ns->rx_size_127);
2857         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2858                             I40E_GLPRT_PRC255L(hw->port),
2859                             pf->offset_loaded, &os->rx_size_255,
2860                             &ns->rx_size_255);
2861         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2862                             I40E_GLPRT_PRC511L(hw->port),
2863                             pf->offset_loaded, &os->rx_size_511,
2864                             &ns->rx_size_511);
2865         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2866                             I40E_GLPRT_PRC1023L(hw->port),
2867                             pf->offset_loaded, &os->rx_size_1023,
2868                             &ns->rx_size_1023);
2869         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2870                             I40E_GLPRT_PRC1522L(hw->port),
2871                             pf->offset_loaded, &os->rx_size_1522,
2872                             &ns->rx_size_1522);
2873         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2874                             I40E_GLPRT_PRC9522L(hw->port),
2875                             pf->offset_loaded, &os->rx_size_big,
2876                             &ns->rx_size_big);
2877         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2878                             pf->offset_loaded, &os->rx_undersize,
2879                             &ns->rx_undersize);
2880         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2881                             pf->offset_loaded, &os->rx_fragments,
2882                             &ns->rx_fragments);
2883         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2884                             pf->offset_loaded, &os->rx_oversize,
2885                             &ns->rx_oversize);
2886         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2887                             pf->offset_loaded, &os->rx_jabber,
2888                             &ns->rx_jabber);
2889         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2890                             I40E_GLPRT_PTC64L(hw->port),
2891                             pf->offset_loaded, &os->tx_size_64,
2892                             &ns->tx_size_64);
2893         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2894                             I40E_GLPRT_PTC127L(hw->port),
2895                             pf->offset_loaded, &os->tx_size_127,
2896                             &ns->tx_size_127);
2897         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2898                             I40E_GLPRT_PTC255L(hw->port),
2899                             pf->offset_loaded, &os->tx_size_255,
2900                             &ns->tx_size_255);
2901         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2902                             I40E_GLPRT_PTC511L(hw->port),
2903                             pf->offset_loaded, &os->tx_size_511,
2904                             &ns->tx_size_511);
2905         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2906                             I40E_GLPRT_PTC1023L(hw->port),
2907                             pf->offset_loaded, &os->tx_size_1023,
2908                             &ns->tx_size_1023);
2909         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2910                             I40E_GLPRT_PTC1522L(hw->port),
2911                             pf->offset_loaded, &os->tx_size_1522,
2912                             &ns->tx_size_1522);
2913         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2914                             I40E_GLPRT_PTC9522L(hw->port),
2915                             pf->offset_loaded, &os->tx_size_big,
2916                             &ns->tx_size_big);
2917         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2918                            pf->offset_loaded,
2919                            &os->fd_sb_match, &ns->fd_sb_match);
2920         /* GLPRT_MSPDC not supported */
2921         /* GLPRT_XEC not supported */
2922
2923         pf->offset_loaded = true;
2924
2925         if (pf->main_vsi)
2926                 i40e_update_vsi_stats(pf->main_vsi);
2927 }
2928
2929 /* Get all statistics of a port */
2930 static int
2931 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2932 {
2933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2936         unsigned i;
2937
2938         /* call read registers - updates values, now write them to struct */
2939         i40e_read_stats_registers(pf, hw);
2940
2941         stats->ipackets = ns->eth.rx_unicast +
2942                         ns->eth.rx_multicast +
2943                         ns->eth.rx_broadcast -
2944                         ns->eth.rx_discards -
2945                         pf->main_vsi->eth_stats.rx_discards;
2946         stats->opackets = ns->eth.tx_unicast +
2947                         ns->eth.tx_multicast +
2948                         ns->eth.tx_broadcast;
2949         stats->ibytes   = ns->eth.rx_bytes;
2950         stats->obytes   = ns->eth.tx_bytes;
2951         stats->oerrors  = ns->eth.tx_errors +
2952                         pf->main_vsi->eth_stats.tx_errors;
2953
2954         /* Rx Errors */
2955         stats->imissed  = ns->eth.rx_discards +
2956                         pf->main_vsi->eth_stats.rx_discards;
2957         stats->ierrors  = ns->crc_errors +
2958                         ns->rx_length_errors + ns->rx_undersize +
2959                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2960
2961         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2962         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2963         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2964         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2965         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2966         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2967         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2968                     ns->eth.rx_unknown_protocol);
2969         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2970         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2971         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2972         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2973         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2974         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2975
2976         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2977                     ns->tx_dropped_link_down);
2978         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2979         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2980                     ns->illegal_bytes);
2981         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2982         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2983                     ns->mac_local_faults);
2984         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2985                     ns->mac_remote_faults);
2986         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2987                     ns->rx_length_errors);
2988         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2989         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2990         for (i = 0; i < 8; i++) {
2991                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2992                                 i, ns->priority_xon_rx[i]);
2993                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2994                                 i, ns->priority_xoff_rx[i]);
2995         }
2996         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2997         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2998         for (i = 0; i < 8; i++) {
2999                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3000                                 i, ns->priority_xon_tx[i]);
3001                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3002                                 i, ns->priority_xoff_tx[i]);
3003                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3004                                 i, ns->priority_xon_2_xoff[i]);
3005         }
3006         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3007         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3008         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3009         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3010         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3011         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3012         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3013         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3014         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3015         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3016         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3017         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3018         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3019         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3020         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3021         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3022         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3023         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3024         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3025                         ns->mac_short_packet_dropped);
3026         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3027                     ns->checksum_error);
3028         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3029         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3030         return 0;
3031 }
3032
3033 /* Reset the statistics */
3034 static void
3035 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3036 {
3037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039
3040         /* Mark PF and VSI stats to update the offset, aka "reset" */
3041         pf->offset_loaded = false;
3042         if (pf->main_vsi)
3043                 pf->main_vsi->offset_loaded = false;
3044
3045         /* read the stats, reading current register values into offset */
3046         i40e_read_stats_registers(pf, hw);
3047 }
3048
3049 static uint32_t
3050 i40e_xstats_calc_num(void)
3051 {
3052         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3053                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3054                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3055 }
3056
3057 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3058                                      struct rte_eth_xstat_name *xstats_names,
3059                                      __rte_unused unsigned limit)
3060 {
3061         unsigned count = 0;
3062         unsigned i, prio;
3063
3064         if (xstats_names == NULL)
3065                 return i40e_xstats_calc_num();
3066
3067         /* Note: limit checked in rte_eth_xstats_names() */
3068
3069         /* Get stats from i40e_eth_stats struct */
3070         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3071                 snprintf(xstats_names[count].name,
3072                          sizeof(xstats_names[count].name),
3073                          "%s", rte_i40e_stats_strings[i].name);
3074                 count++;
3075         }
3076
3077         /* Get individiual stats from i40e_hw_port struct */
3078         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3079                 snprintf(xstats_names[count].name,
3080                         sizeof(xstats_names[count].name),
3081                          "%s", rte_i40e_hw_port_strings[i].name);
3082                 count++;
3083         }
3084
3085         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3086                 for (prio = 0; prio < 8; prio++) {
3087                         snprintf(xstats_names[count].name,
3088                                  sizeof(xstats_names[count].name),
3089                                  "rx_priority%u_%s", prio,
3090                                  rte_i40e_rxq_prio_strings[i].name);
3091                         count++;
3092                 }
3093         }
3094
3095         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3096                 for (prio = 0; prio < 8; prio++) {
3097                         snprintf(xstats_names[count].name,
3098                                  sizeof(xstats_names[count].name),
3099                                  "tx_priority%u_%s", prio,
3100                                  rte_i40e_txq_prio_strings[i].name);
3101                         count++;
3102                 }
3103         }
3104         return count;
3105 }
3106
3107 static int
3108 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3109                     unsigned n)
3110 {
3111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         unsigned i, count, prio;
3114         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3115
3116         count = i40e_xstats_calc_num();
3117         if (n < count)
3118                 return count;
3119
3120         i40e_read_stats_registers(pf, hw);
3121
3122         if (xstats == NULL)
3123                 return 0;
3124
3125         count = 0;
3126
3127         /* Get stats from i40e_eth_stats struct */
3128         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3129                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3130                         rte_i40e_stats_strings[i].offset);
3131                 xstats[count].id = count;
3132                 count++;
3133         }
3134
3135         /* Get individiual stats from i40e_hw_port struct */
3136         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3137                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3138                         rte_i40e_hw_port_strings[i].offset);
3139                 xstats[count].id = count;
3140                 count++;
3141         }
3142
3143         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3144                 for (prio = 0; prio < 8; prio++) {
3145                         xstats[count].value =
3146                                 *(uint64_t *)(((char *)hw_stats) +
3147                                 rte_i40e_rxq_prio_strings[i].offset +
3148                                 (sizeof(uint64_t) * prio));
3149                         xstats[count].id = count;
3150                         count++;
3151                 }
3152         }
3153
3154         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3155                 for (prio = 0; prio < 8; prio++) {
3156                         xstats[count].value =
3157                                 *(uint64_t *)(((char *)hw_stats) +
3158                                 rte_i40e_txq_prio_strings[i].offset +
3159                                 (sizeof(uint64_t) * prio));
3160                         xstats[count].id = count;
3161                         count++;
3162                 }
3163         }
3164
3165         return count;
3166 }
3167
3168 static int
3169 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3170                                  __rte_unused uint16_t queue_id,
3171                                  __rte_unused uint8_t stat_idx,
3172                                  __rte_unused uint8_t is_rx)
3173 {
3174         PMD_INIT_FUNC_TRACE();
3175
3176         return -ENOSYS;
3177 }
3178
3179 static int
3180 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3181 {
3182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         u32 full_ver;
3184         u8 ver, patch;
3185         u16 build;
3186         int ret;
3187
3188         full_ver = hw->nvm.oem_ver;
3189         ver = (u8)(full_ver >> 24);
3190         build = (u16)((full_ver >> 8) & 0xffff);
3191         patch = (u8)(full_ver & 0xff);
3192
3193         ret = snprintf(fw_version, fw_size,
3194                  "%d.%d%d 0x%08x %d.%d.%d",
3195                  ((hw->nvm.version >> 12) & 0xf),
3196                  ((hw->nvm.version >> 4) & 0xff),
3197                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3198                  ver, build, patch);
3199
3200         ret += 1; /* add the size of '\0' */
3201         if (fw_size < (u32)ret)
3202                 return ret;
3203         else
3204                 return 0;
3205 }
3206
3207 static void
3208 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3209 {
3210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         struct i40e_vsi *vsi = pf->main_vsi;
3213         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3214
3215         dev_info->max_rx_queues = vsi->nb_qps;
3216         dev_info->max_tx_queues = vsi->nb_qps;
3217         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3218         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3219         dev_info->max_mac_addrs = vsi->max_macaddrs;
3220         dev_info->max_vfs = pci_dev->max_vfs;
3221         dev_info->rx_queue_offload_capa = 0;
3222         dev_info->rx_offload_capa =
3223                 DEV_RX_OFFLOAD_VLAN_STRIP |
3224                 DEV_RX_OFFLOAD_QINQ_STRIP |
3225                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3226                 DEV_RX_OFFLOAD_UDP_CKSUM |
3227                 DEV_RX_OFFLOAD_TCP_CKSUM |
3228                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3229                 DEV_RX_OFFLOAD_CRC_STRIP |
3230                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3231                 DEV_RX_OFFLOAD_VLAN_FILTER;
3232
3233         dev_info->tx_queue_offload_capa = 0;
3234         dev_info->tx_offload_capa =
3235                 DEV_TX_OFFLOAD_VLAN_INSERT |
3236                 DEV_TX_OFFLOAD_QINQ_INSERT |
3237                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3238                 DEV_TX_OFFLOAD_UDP_CKSUM |
3239                 DEV_TX_OFFLOAD_TCP_CKSUM |
3240                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3241                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3242                 DEV_TX_OFFLOAD_TCP_TSO |
3243                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3244                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3245                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3246                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3247         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3248                                                 sizeof(uint32_t);
3249         dev_info->reta_size = pf->hash_lut_size;
3250         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3251
3252         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3253                 .rx_thresh = {
3254                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3255                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3256                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3257                 },
3258                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3259                 .rx_drop_en = 0,
3260                 .offloads = 0,
3261         };
3262
3263         dev_info->default_txconf = (struct rte_eth_txconf) {
3264                 .tx_thresh = {
3265                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3266                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3267                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3268                 },
3269                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3270                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3271                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3272                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3273         };
3274
3275         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3276                 .nb_max = I40E_MAX_RING_DESC,
3277                 .nb_min = I40E_MIN_RING_DESC,
3278                 .nb_align = I40E_ALIGN_RING_DESC,
3279         };
3280
3281         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3282                 .nb_max = I40E_MAX_RING_DESC,
3283                 .nb_min = I40E_MIN_RING_DESC,
3284                 .nb_align = I40E_ALIGN_RING_DESC,
3285                 .nb_seg_max = I40E_TX_MAX_SEG,
3286                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3287         };
3288
3289         if (pf->flags & I40E_FLAG_VMDQ) {
3290                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3291                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3292                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3293                                                 pf->max_nb_vmdq_vsi;
3294                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3295                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3296                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3297         }
3298
3299         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3300                 /* For XL710 */
3301                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3302                 dev_info->default_rxportconf.nb_queues = 2;
3303                 dev_info->default_txportconf.nb_queues = 2;
3304                 if (dev->data->nb_rx_queues == 1)
3305                         dev_info->default_rxportconf.ring_size = 2048;
3306                 else
3307                         dev_info->default_rxportconf.ring_size = 1024;
3308                 if (dev->data->nb_tx_queues == 1)
3309                         dev_info->default_txportconf.ring_size = 1024;
3310                 else
3311                         dev_info->default_txportconf.ring_size = 512;
3312
3313         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3314                 /* For XXV710 */
3315                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3316                 dev_info->default_rxportconf.nb_queues = 1;
3317                 dev_info->default_txportconf.nb_queues = 1;
3318                 dev_info->default_rxportconf.ring_size = 256;
3319                 dev_info->default_txportconf.ring_size = 256;
3320         } else {
3321                 /* For X710 */
3322                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3323                 dev_info->default_rxportconf.nb_queues = 1;
3324                 dev_info->default_txportconf.nb_queues = 1;
3325                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3326                         dev_info->default_rxportconf.ring_size = 512;
3327                         dev_info->default_txportconf.ring_size = 256;
3328                 } else {
3329                         dev_info->default_rxportconf.ring_size = 256;
3330                         dev_info->default_txportconf.ring_size = 256;
3331                 }
3332         }
3333         dev_info->default_rxportconf.burst_size = 32;
3334         dev_info->default_txportconf.burst_size = 32;
3335 }
3336
3337 static int
3338 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3339 {
3340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3341         struct i40e_vsi *vsi = pf->main_vsi;
3342         PMD_INIT_FUNC_TRACE();
3343
3344         if (on)
3345                 return i40e_vsi_add_vlan(vsi, vlan_id);
3346         else
3347                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3348 }
3349
3350 static int
3351 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3352                                 enum rte_vlan_type vlan_type,
3353                                 uint16_t tpid, int qinq)
3354 {
3355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356         uint64_t reg_r = 0;
3357         uint64_t reg_w = 0;
3358         uint16_t reg_id = 3;
3359         int ret;
3360
3361         if (qinq) {
3362                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3363                         reg_id = 2;
3364         }
3365
3366         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3367                                           &reg_r, NULL);
3368         if (ret != I40E_SUCCESS) {
3369                 PMD_DRV_LOG(ERR,
3370                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3371                            reg_id);
3372                 return -EIO;
3373         }
3374         PMD_DRV_LOG(DEBUG,
3375                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3376                     reg_id, reg_r);
3377
3378         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3379         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3380         if (reg_r == reg_w) {
3381                 PMD_DRV_LOG(DEBUG, "No need to write");
3382                 return 0;
3383         }
3384
3385         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3386                                            reg_w, NULL);
3387         if (ret != I40E_SUCCESS) {
3388                 PMD_DRV_LOG(ERR,
3389                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3390                             reg_id);
3391                 return -EIO;
3392         }
3393         PMD_DRV_LOG(DEBUG,
3394                     "Global register 0x%08x is changed with value 0x%08x",
3395                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3396
3397         return 0;
3398 }
3399
3400 static int
3401 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3402                    enum rte_vlan_type vlan_type,
3403                    uint16_t tpid)
3404 {
3405         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3406         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3407         int qinq = dev->data->dev_conf.rxmode.offloads &
3408                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3409         int ret = 0;
3410
3411         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3412              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3413             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3414                 PMD_DRV_LOG(ERR,
3415                             "Unsupported vlan type.");
3416                 return -EINVAL;
3417         }
3418
3419         if (pf->support_multi_driver) {
3420                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3421                 return -ENOTSUP;
3422         }
3423
3424         /* 802.1ad frames ability is added in NVM API 1.7*/
3425         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3426                 if (qinq) {
3427                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3428                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3429                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3430                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3431                 } else {
3432                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3433                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3434                 }
3435                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3436                 if (ret != I40E_SUCCESS) {
3437                         PMD_DRV_LOG(ERR,
3438                                     "Set switch config failed aq_err: %d",
3439                                     hw->aq.asq_last_status);
3440                         ret = -EIO;
3441                 }
3442         } else
3443                 /* If NVM API < 1.7, keep the register setting */
3444                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3445                                                       tpid, qinq);
3446         i40e_global_cfg_warning(I40E_WARNING_TPID);
3447
3448         return ret;
3449 }
3450
3451 static int
3452 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3453 {
3454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3455         struct i40e_vsi *vsi = pf->main_vsi;
3456         struct rte_eth_rxmode *rxmode;
3457
3458         rxmode = &dev->data->dev_conf.rxmode;
3459         if (mask & ETH_VLAN_FILTER_MASK) {
3460                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3461                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3462                 else
3463                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3464         }
3465
3466         if (mask & ETH_VLAN_STRIP_MASK) {
3467                 /* Enable or disable VLAN stripping */
3468                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3469                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3470                 else
3471                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3472         }
3473
3474         if (mask & ETH_VLAN_EXTEND_MASK) {
3475                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3476                         i40e_vsi_config_double_vlan(vsi, TRUE);
3477                         /* Set global registers with default ethertype. */
3478                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3479                                            ETHER_TYPE_VLAN);
3480                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3481                                            ETHER_TYPE_VLAN);
3482                 }
3483                 else
3484                         i40e_vsi_config_double_vlan(vsi, FALSE);
3485         }
3486
3487         return 0;
3488 }
3489
3490 static void
3491 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3492                           __rte_unused uint16_t queue,
3493                           __rte_unused int on)
3494 {
3495         PMD_INIT_FUNC_TRACE();
3496 }
3497
3498 static int
3499 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3500 {
3501         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3502         struct i40e_vsi *vsi = pf->main_vsi;
3503         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3504         struct i40e_vsi_vlan_pvid_info info;
3505
3506         memset(&info, 0, sizeof(info));
3507         info.on = on;
3508         if (info.on)
3509                 info.config.pvid = pvid;
3510         else {
3511                 info.config.reject.tagged =
3512                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3513                 info.config.reject.untagged =
3514                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3515         }
3516
3517         return i40e_vsi_vlan_pvid_set(vsi, &info);
3518 }
3519
3520 static int
3521 i40e_dev_led_on(struct rte_eth_dev *dev)
3522 {
3523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3524         uint32_t mode = i40e_led_get(hw);
3525
3526         if (mode == 0)
3527                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3528
3529         return 0;
3530 }
3531
3532 static int
3533 i40e_dev_led_off(struct rte_eth_dev *dev)
3534 {
3535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3536         uint32_t mode = i40e_led_get(hw);
3537
3538         if (mode != 0)
3539                 i40e_led_set(hw, 0, false);
3540
3541         return 0;
3542 }
3543
3544 static int
3545 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3546 {
3547         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3549
3550         fc_conf->pause_time = pf->fc_conf.pause_time;
3551
3552         /* read out from register, in case they are modified by other port */
3553         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3554                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3555         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3556                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3557
3558         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3559         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3560
3561          /* Return current mode according to actual setting*/
3562         switch (hw->fc.current_mode) {
3563         case I40E_FC_FULL:
3564                 fc_conf->mode = RTE_FC_FULL;
3565                 break;
3566         case I40E_FC_TX_PAUSE:
3567                 fc_conf->mode = RTE_FC_TX_PAUSE;
3568                 break;
3569         case I40E_FC_RX_PAUSE:
3570                 fc_conf->mode = RTE_FC_RX_PAUSE;
3571                 break;
3572         case I40E_FC_NONE:
3573         default:
3574                 fc_conf->mode = RTE_FC_NONE;
3575         };
3576
3577         return 0;
3578 }
3579
3580 static int
3581 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3582 {
3583         uint32_t mflcn_reg, fctrl_reg, reg;
3584         uint32_t max_high_water;
3585         uint8_t i, aq_failure;
3586         int err;
3587         struct i40e_hw *hw;
3588         struct i40e_pf *pf;
3589         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3590                 [RTE_FC_NONE] = I40E_FC_NONE,
3591                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3592                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3593                 [RTE_FC_FULL] = I40E_FC_FULL
3594         };
3595
3596         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3597
3598         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3599         if ((fc_conf->high_water > max_high_water) ||
3600                         (fc_conf->high_water < fc_conf->low_water)) {
3601                 PMD_INIT_LOG(ERR,
3602                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3603                         max_high_water);
3604                 return -EINVAL;
3605         }
3606
3607         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3609         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3610
3611         pf->fc_conf.pause_time = fc_conf->pause_time;
3612         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3613         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3614
3615         PMD_INIT_FUNC_TRACE();
3616
3617         /* All the link flow control related enable/disable register
3618          * configuration is handle by the F/W
3619          */
3620         err = i40e_set_fc(hw, &aq_failure, true);
3621         if (err < 0)
3622                 return -ENOSYS;
3623
3624         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3625                 /* Configure flow control refresh threshold,
3626                  * the value for stat_tx_pause_refresh_timer[8]
3627                  * is used for global pause operation.
3628                  */
3629
3630                 I40E_WRITE_REG(hw,
3631                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3632                                pf->fc_conf.pause_time);
3633
3634                 /* configure the timer value included in transmitted pause
3635                  * frame,
3636                  * the value for stat_tx_pause_quanta[8] is used for global
3637                  * pause operation
3638                  */
3639                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3640                                pf->fc_conf.pause_time);
3641
3642                 fctrl_reg = I40E_READ_REG(hw,
3643                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3644
3645                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3646                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3647                 else
3648                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3649
3650                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3651                                fctrl_reg);
3652         } else {
3653                 /* Configure pause time (2 TCs per register) */
3654                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3655                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3656                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3657
3658                 /* Configure flow control refresh threshold value */
3659                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3660                                pf->fc_conf.pause_time / 2);
3661
3662                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3663
3664                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3665                  *depending on configuration
3666                  */
3667                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3668                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3669                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3670                 } else {
3671                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3672                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3673                 }
3674
3675                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3676         }
3677
3678         if (!pf->support_multi_driver) {
3679                 /* config water marker both based on the packets and bytes */
3680                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3681                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3682                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3683                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3684                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3685                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3686                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3687                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3688                                   << I40E_KILOSHIFT);
3689                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3690                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3691                                    << I40E_KILOSHIFT);
3692                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3693         } else {
3694                 PMD_DRV_LOG(ERR,
3695                             "Water marker configuration is not supported.");
3696         }
3697
3698         I40E_WRITE_FLUSH(hw);
3699
3700         return 0;
3701 }
3702
3703 static int
3704 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3705                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3706 {
3707         PMD_INIT_FUNC_TRACE();
3708
3709         return -ENOSYS;
3710 }
3711
3712 /* Add a MAC address, and update filters */
3713 static int
3714 i40e_macaddr_add(struct rte_eth_dev *dev,
3715                  struct ether_addr *mac_addr,
3716                  __rte_unused uint32_t index,
3717                  uint32_t pool)
3718 {
3719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3720         struct i40e_mac_filter_info mac_filter;
3721         struct i40e_vsi *vsi;
3722         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3723         int ret;
3724
3725         /* If VMDQ not enabled or configured, return */
3726         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3727                           !pf->nb_cfg_vmdq_vsi)) {
3728                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3729                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3730                         pool);
3731                 return -ENOTSUP;
3732         }
3733
3734         if (pool > pf->nb_cfg_vmdq_vsi) {
3735                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3736                                 pool, pf->nb_cfg_vmdq_vsi);
3737                 return -EINVAL;
3738         }
3739
3740         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3741         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3742                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3743         else
3744                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3745
3746         if (pool == 0)
3747                 vsi = pf->main_vsi;
3748         else
3749                 vsi = pf->vmdq[pool - 1].vsi;
3750
3751         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3752         if (ret != I40E_SUCCESS) {
3753                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3754                 return -ENODEV;
3755         }
3756         return 0;
3757 }
3758
3759 /* Remove a MAC address, and update filters */
3760 static void
3761 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3762 {
3763         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764         struct i40e_vsi *vsi;
3765         struct rte_eth_dev_data *data = dev->data;
3766         struct ether_addr *macaddr;
3767         int ret;
3768         uint32_t i;
3769         uint64_t pool_sel;
3770
3771         macaddr = &(data->mac_addrs[index]);
3772
3773         pool_sel = dev->data->mac_pool_sel[index];
3774
3775         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3776                 if (pool_sel & (1ULL << i)) {
3777                         if (i == 0)
3778                                 vsi = pf->main_vsi;
3779                         else {
3780                                 /* No VMDQ pool enabled or configured */
3781                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3782                                         (i > pf->nb_cfg_vmdq_vsi)) {
3783                                         PMD_DRV_LOG(ERR,
3784                                                 "No VMDQ pool enabled/configured");
3785                                         return;
3786                                 }
3787                                 vsi = pf->vmdq[i - 1].vsi;
3788                         }
3789                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3790
3791                         if (ret) {
3792                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3793                                 return;
3794                         }
3795                 }
3796         }
3797 }
3798
3799 /* Set perfect match or hash match of MAC and VLAN for a VF */
3800 static int
3801 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3802                  struct rte_eth_mac_filter *filter,
3803                  bool add)
3804 {
3805         struct i40e_hw *hw;
3806         struct i40e_mac_filter_info mac_filter;
3807         struct ether_addr old_mac;
3808         struct ether_addr *new_mac;
3809         struct i40e_pf_vf *vf = NULL;
3810         uint16_t vf_id;
3811         int ret;
3812
3813         if (pf == NULL) {
3814                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3815                 return -EINVAL;
3816         }
3817         hw = I40E_PF_TO_HW(pf);
3818
3819         if (filter == NULL) {
3820                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3821                 return -EINVAL;
3822         }
3823
3824         new_mac = &filter->mac_addr;
3825
3826         if (is_zero_ether_addr(new_mac)) {
3827                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3828                 return -EINVAL;
3829         }
3830
3831         vf_id = filter->dst_id;
3832
3833         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3834                 PMD_DRV_LOG(ERR, "Invalid argument.");
3835                 return -EINVAL;
3836         }
3837         vf = &pf->vfs[vf_id];
3838
3839         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3840                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3841                 return -EINVAL;
3842         }
3843
3844         if (add) {
3845                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3846                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3847                                 ETHER_ADDR_LEN);
3848                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3849                                  ETHER_ADDR_LEN);
3850
3851                 mac_filter.filter_type = filter->filter_type;
3852                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3853                 if (ret != I40E_SUCCESS) {
3854                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3855                         return -1;
3856                 }
3857                 ether_addr_copy(new_mac, &pf->dev_addr);
3858         } else {
3859                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3860                                 ETHER_ADDR_LEN);
3861                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3862                 if (ret != I40E_SUCCESS) {
3863                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3864                         return -1;
3865                 }
3866
3867                 /* Clear device address as it has been removed */
3868                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3869                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3870         }
3871
3872         return 0;
3873 }
3874
3875 /* MAC filter handle */
3876 static int
3877 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3878                 void *arg)
3879 {
3880         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3881         struct rte_eth_mac_filter *filter;
3882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3883         int ret = I40E_NOT_SUPPORTED;
3884
3885         filter = (struct rte_eth_mac_filter *)(arg);
3886
3887         switch (filter_op) {
3888         case RTE_ETH_FILTER_NOP:
3889                 ret = I40E_SUCCESS;
3890                 break;
3891         case RTE_ETH_FILTER_ADD:
3892                 i40e_pf_disable_irq0(hw);
3893                 if (filter->is_vf)
3894                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3895                 i40e_pf_enable_irq0(hw);
3896                 break;
3897         case RTE_ETH_FILTER_DELETE:
3898                 i40e_pf_disable_irq0(hw);
3899                 if (filter->is_vf)
3900                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3901                 i40e_pf_enable_irq0(hw);
3902                 break;
3903         default:
3904                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3905                 ret = I40E_ERR_PARAM;
3906                 break;
3907         }
3908
3909         return ret;
3910 }
3911
3912 static int
3913 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3914 {
3915         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3916         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3917         uint32_t reg;
3918         int ret;
3919
3920         if (!lut)
3921                 return -EINVAL;
3922
3923         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3924                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3925                                           lut, lut_size);
3926                 if (ret) {
3927                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3928                         return ret;
3929                 }
3930         } else {
3931                 uint32_t *lut_dw = (uint32_t *)lut;
3932                 uint16_t i, lut_size_dw = lut_size / 4;
3933
3934                 if (vsi->type == I40E_VSI_SRIOV) {
3935                         for (i = 0; i <= lut_size_dw; i++) {
3936                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3937                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3938                         }
3939                 } else {
3940                         for (i = 0; i < lut_size_dw; i++)
3941                                 lut_dw[i] = I40E_READ_REG(hw,
3942                                                           I40E_PFQF_HLUT(i));
3943                 }
3944         }
3945
3946         return 0;
3947 }
3948
3949 int
3950 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3951 {
3952         struct i40e_pf *pf;
3953         struct i40e_hw *hw;
3954         int ret;
3955
3956         if (!vsi || !lut)
3957                 return -EINVAL;
3958
3959         pf = I40E_VSI_TO_PF(vsi);
3960         hw = I40E_VSI_TO_HW(vsi);
3961
3962         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3963                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3964                                           lut, lut_size);
3965                 if (ret) {
3966                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3967                         return ret;
3968                 }
3969         } else {
3970                 uint32_t *lut_dw = (uint32_t *)lut;
3971                 uint16_t i, lut_size_dw = lut_size / 4;
3972
3973                 if (vsi->type == I40E_VSI_SRIOV) {
3974                         for (i = 0; i < lut_size_dw; i++)
3975                                 I40E_WRITE_REG(
3976                                         hw,
3977                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3978                                         lut_dw[i]);
3979                 } else {
3980                         for (i = 0; i < lut_size_dw; i++)
3981                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3982                                                lut_dw[i]);
3983                 }
3984                 I40E_WRITE_FLUSH(hw);
3985         }
3986
3987         return 0;
3988 }
3989
3990 static int
3991 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3992                          struct rte_eth_rss_reta_entry64 *reta_conf,
3993                          uint16_t reta_size)
3994 {
3995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3996         uint16_t i, lut_size = pf->hash_lut_size;
3997         uint16_t idx, shift;
3998         uint8_t *lut;
3999         int ret;
4000
4001         if (reta_size != lut_size ||
4002                 reta_size > ETH_RSS_RETA_SIZE_512) {
4003                 PMD_DRV_LOG(ERR,
4004                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4005                         reta_size, lut_size);
4006                 return -EINVAL;
4007         }
4008
4009         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4010         if (!lut) {
4011                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4012                 return -ENOMEM;
4013         }
4014         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4015         if (ret)
4016                 goto out;
4017         for (i = 0; i < reta_size; i++) {
4018                 idx = i / RTE_RETA_GROUP_SIZE;
4019                 shift = i % RTE_RETA_GROUP_SIZE;
4020                 if (reta_conf[idx].mask & (1ULL << shift))
4021                         lut[i] = reta_conf[idx].reta[shift];
4022         }
4023         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4024
4025 out:
4026         rte_free(lut);
4027
4028         return ret;
4029 }
4030
4031 static int
4032 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4033                         struct rte_eth_rss_reta_entry64 *reta_conf,
4034                         uint16_t reta_size)
4035 {
4036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4037         uint16_t i, lut_size = pf->hash_lut_size;
4038         uint16_t idx, shift;
4039         uint8_t *lut;
4040         int ret;
4041
4042         if (reta_size != lut_size ||
4043                 reta_size > ETH_RSS_RETA_SIZE_512) {
4044                 PMD_DRV_LOG(ERR,
4045                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4046                         reta_size, lut_size);
4047                 return -EINVAL;
4048         }
4049
4050         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4051         if (!lut) {
4052                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4053                 return -ENOMEM;
4054         }
4055
4056         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4057         if (ret)
4058                 goto out;
4059         for (i = 0; i < reta_size; i++) {
4060                 idx = i / RTE_RETA_GROUP_SIZE;
4061                 shift = i % RTE_RETA_GROUP_SIZE;
4062                 if (reta_conf[idx].mask & (1ULL << shift))
4063                         reta_conf[idx].reta[shift] = lut[i];
4064         }
4065
4066 out:
4067         rte_free(lut);
4068
4069         return ret;
4070 }
4071
4072 /**
4073  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4074  * @hw:   pointer to the HW structure
4075  * @mem:  pointer to mem struct to fill out
4076  * @size: size of memory requested
4077  * @alignment: what to align the allocation to
4078  **/
4079 enum i40e_status_code
4080 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4081                         struct i40e_dma_mem *mem,
4082                         u64 size,
4083                         u32 alignment)
4084 {
4085         const struct rte_memzone *mz = NULL;
4086         char z_name[RTE_MEMZONE_NAMESIZE];
4087
4088         if (!mem)
4089                 return I40E_ERR_PARAM;
4090
4091         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4092         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4093                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4094         if (!mz)
4095                 return I40E_ERR_NO_MEMORY;
4096
4097         mem->size = size;
4098         mem->va = mz->addr;
4099         mem->pa = mz->iova;
4100         mem->zone = (const void *)mz;
4101         PMD_DRV_LOG(DEBUG,
4102                 "memzone %s allocated with physical address: %"PRIu64,
4103                 mz->name, mem->pa);
4104
4105         return I40E_SUCCESS;
4106 }
4107
4108 /**
4109  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4110  * @hw:   pointer to the HW structure
4111  * @mem:  ptr to mem struct to free
4112  **/
4113 enum i40e_status_code
4114 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4115                     struct i40e_dma_mem *mem)
4116 {
4117         if (!mem)
4118                 return I40E_ERR_PARAM;
4119
4120         PMD_DRV_LOG(DEBUG,
4121                 "memzone %s to be freed with physical address: %"PRIu64,
4122                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4123         rte_memzone_free((const struct rte_memzone *)mem->zone);
4124         mem->zone = NULL;
4125         mem->va = NULL;
4126         mem->pa = (u64)0;
4127
4128         return I40E_SUCCESS;
4129 }
4130
4131 /**
4132  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4133  * @hw:   pointer to the HW structure
4134  * @mem:  pointer to mem struct to fill out
4135  * @size: size of memory requested
4136  **/
4137 enum i40e_status_code
4138 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4139                          struct i40e_virt_mem *mem,
4140                          u32 size)
4141 {
4142         if (!mem)
4143                 return I40E_ERR_PARAM;
4144
4145         mem->size = size;
4146         mem->va = rte_zmalloc("i40e", size, 0);
4147
4148         if (mem->va)
4149                 return I40E_SUCCESS;
4150         else
4151                 return I40E_ERR_NO_MEMORY;
4152 }
4153
4154 /**
4155  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4156  * @hw:   pointer to the HW structure
4157  * @mem:  pointer to mem struct to free
4158  **/
4159 enum i40e_status_code
4160 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4161                      struct i40e_virt_mem *mem)
4162 {
4163         if (!mem)
4164                 return I40E_ERR_PARAM;
4165
4166         rte_free(mem->va);
4167         mem->va = NULL;
4168
4169         return I40E_SUCCESS;
4170 }
4171
4172 void
4173 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4174 {
4175         rte_spinlock_init(&sp->spinlock);
4176 }
4177
4178 void
4179 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4180 {
4181         rte_spinlock_lock(&sp->spinlock);
4182 }
4183
4184 void
4185 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4186 {
4187         rte_spinlock_unlock(&sp->spinlock);
4188 }
4189
4190 void
4191 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4192 {
4193         return;
4194 }
4195
4196 /**
4197  * Get the hardware capabilities, which will be parsed
4198  * and saved into struct i40e_hw.
4199  */
4200 static int
4201 i40e_get_cap(struct i40e_hw *hw)
4202 {
4203         struct i40e_aqc_list_capabilities_element_resp *buf;
4204         uint16_t len, size = 0;
4205         int ret;
4206
4207         /* Calculate a huge enough buff for saving response data temporarily */
4208         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4209                                                 I40E_MAX_CAP_ELE_NUM;
4210         buf = rte_zmalloc("i40e", len, 0);
4211         if (!buf) {
4212                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4213                 return I40E_ERR_NO_MEMORY;
4214         }
4215
4216         /* Get, parse the capabilities and save it to hw */
4217         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4218                         i40e_aqc_opc_list_func_capabilities, NULL);
4219         if (ret != I40E_SUCCESS)
4220                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4221
4222         /* Free the temporary buffer after being used */
4223         rte_free(buf);
4224
4225         return ret;
4226 }
4227
4228 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4229 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4230
4231 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4232                 const char *value,
4233                 void *opaque)
4234 {
4235         struct i40e_pf *pf;
4236         unsigned long num;
4237         char *end;
4238
4239         pf = (struct i40e_pf *)opaque;
4240         RTE_SET_USED(key);
4241
4242         errno = 0;
4243         num = strtoul(value, &end, 0);
4244         if (errno != 0 || end == value || *end != 0) {
4245                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4246                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4247                 return -(EINVAL);
4248         }
4249
4250         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4251                 pf->vf_nb_qp_max = (uint16_t)num;
4252         else
4253                 /* here return 0 to make next valid same argument work */
4254                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4255                             "power of 2 and equal or less than 16 !, Now it is "
4256                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4257
4258         return 0;
4259 }
4260
4261 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4262 {
4263         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4264         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4265         struct rte_kvargs *kvlist;
4266
4267         /* set default queue number per VF as 4 */
4268         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4269
4270         if (dev->device->devargs == NULL)
4271                 return 0;
4272
4273         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4274         if (kvlist == NULL)
4275                 return -(EINVAL);
4276
4277         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4278                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4279                             "the first invalid or last valid one is used !",
4280                             QUEUE_NUM_PER_VF_ARG);
4281
4282         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4283                            i40e_pf_parse_vf_queue_number_handler, pf);
4284
4285         rte_kvargs_free(kvlist);
4286
4287         return 0;
4288 }
4289
4290 static int
4291 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4292 {
4293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4295         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4296         uint16_t qp_count = 0, vsi_count = 0;
4297
4298         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4299                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4300                 return -EINVAL;
4301         }
4302
4303         i40e_pf_config_vf_rxq_number(dev);
4304
4305         /* Add the parameter init for LFC */
4306         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4307         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4308         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4309
4310         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4311         pf->max_num_vsi = hw->func_caps.num_vsis;
4312         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4313         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4314
4315         /* FDir queue/VSI allocation */
4316         pf->fdir_qp_offset = 0;
4317         if (hw->func_caps.fd) {
4318                 pf->flags |= I40E_FLAG_FDIR;
4319                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4320         } else {
4321                 pf->fdir_nb_qps = 0;
4322         }
4323         qp_count += pf->fdir_nb_qps;
4324         vsi_count += 1;
4325
4326         /* LAN queue/VSI allocation */
4327         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4328         if (!hw->func_caps.rss) {
4329                 pf->lan_nb_qps = 1;
4330         } else {
4331                 pf->flags |= I40E_FLAG_RSS;
4332                 if (hw->mac.type == I40E_MAC_X722)
4333                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4334                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4335         }
4336         qp_count += pf->lan_nb_qps;
4337         vsi_count += 1;
4338
4339         /* VF queue/VSI allocation */
4340         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4341         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4342                 pf->flags |= I40E_FLAG_SRIOV;
4343                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4344                 pf->vf_num = pci_dev->max_vfs;
4345                 PMD_DRV_LOG(DEBUG,
4346                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4347                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4348         } else {
4349                 pf->vf_nb_qps = 0;
4350                 pf->vf_num = 0;
4351         }
4352         qp_count += pf->vf_nb_qps * pf->vf_num;
4353         vsi_count += pf->vf_num;
4354
4355         /* VMDq queue/VSI allocation */
4356         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4357         pf->vmdq_nb_qps = 0;
4358         pf->max_nb_vmdq_vsi = 0;
4359         if (hw->func_caps.vmdq) {
4360                 if (qp_count < hw->func_caps.num_tx_qp &&
4361                         vsi_count < hw->func_caps.num_vsis) {
4362                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4363                                 qp_count) / pf->vmdq_nb_qp_max;
4364
4365                         /* Limit the maximum number of VMDq vsi to the maximum
4366                          * ethdev can support
4367                          */
4368                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4369                                 hw->func_caps.num_vsis - vsi_count);
4370                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4371                                 ETH_64_POOLS);
4372                         if (pf->max_nb_vmdq_vsi) {
4373                                 pf->flags |= I40E_FLAG_VMDQ;
4374                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4375                                 PMD_DRV_LOG(DEBUG,
4376                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4377                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4378                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4379                         } else {
4380                                 PMD_DRV_LOG(INFO,
4381                                         "No enough queues left for VMDq");
4382                         }
4383                 } else {
4384                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4385                 }
4386         }
4387         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4388         vsi_count += pf->max_nb_vmdq_vsi;
4389
4390         if (hw->func_caps.dcb)
4391                 pf->flags |= I40E_FLAG_DCB;
4392
4393         if (qp_count > hw->func_caps.num_tx_qp) {
4394                 PMD_DRV_LOG(ERR,
4395                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4396                         qp_count, hw->func_caps.num_tx_qp);
4397                 return -EINVAL;
4398         }
4399         if (vsi_count > hw->func_caps.num_vsis) {
4400                 PMD_DRV_LOG(ERR,
4401                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4402                         vsi_count, hw->func_caps.num_vsis);
4403                 return -EINVAL;
4404         }
4405
4406         return 0;
4407 }
4408
4409 static int
4410 i40e_pf_get_switch_config(struct i40e_pf *pf)
4411 {
4412         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4413         struct i40e_aqc_get_switch_config_resp *switch_config;
4414         struct i40e_aqc_switch_config_element_resp *element;
4415         uint16_t start_seid = 0, num_reported;
4416         int ret;
4417
4418         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4419                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4420         if (!switch_config) {
4421                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4422                 return -ENOMEM;
4423         }
4424
4425         /* Get the switch configurations */
4426         ret = i40e_aq_get_switch_config(hw, switch_config,
4427                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4428         if (ret != I40E_SUCCESS) {
4429                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4430                 goto fail;
4431         }
4432         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4433         if (num_reported != 1) { /* The number should be 1 */
4434                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4435                 goto fail;
4436         }
4437
4438         /* Parse the switch configuration elements */
4439         element = &(switch_config->element[0]);
4440         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4441                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4442                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4443         } else
4444                 PMD_DRV_LOG(INFO, "Unknown element type");
4445
4446 fail:
4447         rte_free(switch_config);
4448
4449         return ret;
4450 }
4451
4452 static int
4453 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4454                         uint32_t num)
4455 {
4456         struct pool_entry *entry;
4457
4458         if (pool == NULL || num == 0)
4459                 return -EINVAL;
4460
4461         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4462         if (entry == NULL) {
4463                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4464                 return -ENOMEM;
4465         }
4466
4467         /* queue heap initialize */
4468         pool->num_free = num;
4469         pool->num_alloc = 0;
4470         pool->base = base;
4471         LIST_INIT(&pool->alloc_list);
4472         LIST_INIT(&pool->free_list);
4473
4474         /* Initialize element  */
4475         entry->base = 0;
4476         entry->len = num;
4477
4478         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4479         return 0;
4480 }
4481
4482 static void
4483 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4484 {
4485         struct pool_entry *entry, *next_entry;
4486
4487         if (pool == NULL)
4488                 return;
4489
4490         for (entry = LIST_FIRST(&pool->alloc_list);
4491                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4492                         entry = next_entry) {
4493                 LIST_REMOVE(entry, next);
4494                 rte_free(entry);
4495         }
4496
4497         for (entry = LIST_FIRST(&pool->free_list);
4498                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4499                         entry = next_entry) {
4500                 LIST_REMOVE(entry, next);
4501                 rte_free(entry);
4502         }
4503
4504         pool->num_free = 0;
4505         pool->num_alloc = 0;
4506         pool->base = 0;
4507         LIST_INIT(&pool->alloc_list);
4508         LIST_INIT(&pool->free_list);
4509 }
4510
4511 static int
4512 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4513                        uint32_t base)
4514 {
4515         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4516         uint32_t pool_offset;
4517         int insert;
4518
4519         if (pool == NULL) {
4520                 PMD_DRV_LOG(ERR, "Invalid parameter");
4521                 return -EINVAL;
4522         }
4523
4524         pool_offset = base - pool->base;
4525         /* Lookup in alloc list */
4526         LIST_FOREACH(entry, &pool->alloc_list, next) {
4527                 if (entry->base == pool_offset) {
4528                         valid_entry = entry;
4529                         LIST_REMOVE(entry, next);
4530                         break;
4531                 }
4532         }
4533
4534         /* Not find, return */
4535         if (valid_entry == NULL) {
4536                 PMD_DRV_LOG(ERR, "Failed to find entry");
4537                 return -EINVAL;
4538         }
4539
4540         /**
4541          * Found it, move it to free list  and try to merge.
4542          * In order to make merge easier, always sort it by qbase.
4543          * Find adjacent prev and last entries.
4544          */
4545         prev = next = NULL;
4546         LIST_FOREACH(entry, &pool->free_list, next) {
4547                 if (entry->base > valid_entry->base) {
4548                         next = entry;
4549                         break;
4550                 }
4551                 prev = entry;
4552         }
4553
4554         insert = 0;
4555         /* Try to merge with next one*/
4556         if (next != NULL) {
4557                 /* Merge with next one */
4558                 if (valid_entry->base + valid_entry->len == next->base) {
4559                         next->base = valid_entry->base;
4560                         next->len += valid_entry->len;
4561                         rte_free(valid_entry);
4562                         valid_entry = next;
4563                         insert = 1;
4564                 }
4565         }
4566
4567         if (prev != NULL) {
4568                 /* Merge with previous one */
4569                 if (prev->base + prev->len == valid_entry->base) {
4570                         prev->len += valid_entry->len;
4571                         /* If it merge with next one, remove next node */
4572                         if (insert == 1) {
4573                                 LIST_REMOVE(valid_entry, next);
4574                                 rte_free(valid_entry);
4575                         } else {
4576                                 rte_free(valid_entry);
4577                                 insert = 1;
4578                         }
4579                 }
4580         }
4581
4582         /* Not find any entry to merge, insert */
4583         if (insert == 0) {
4584                 if (prev != NULL)
4585                         LIST_INSERT_AFTER(prev, valid_entry, next);
4586                 else if (next != NULL)
4587                         LIST_INSERT_BEFORE(next, valid_entry, next);
4588                 else /* It's empty list, insert to head */
4589                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4590         }
4591
4592         pool->num_free += valid_entry->len;
4593         pool->num_alloc -= valid_entry->len;
4594
4595         return 0;
4596 }
4597
4598 static int
4599 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4600                        uint16_t num)
4601 {
4602         struct pool_entry *entry, *valid_entry;
4603
4604         if (pool == NULL || num == 0) {
4605                 PMD_DRV_LOG(ERR, "Invalid parameter");
4606                 return -EINVAL;
4607         }
4608
4609         if (pool->num_free < num) {
4610                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4611                             num, pool->num_free);
4612                 return -ENOMEM;
4613         }
4614
4615         valid_entry = NULL;
4616         /* Lookup  in free list and find most fit one */
4617         LIST_FOREACH(entry, &pool->free_list, next) {
4618                 if (entry->len >= num) {
4619                         /* Find best one */
4620                         if (entry->len == num) {
4621                                 valid_entry = entry;
4622                                 break;
4623                         }
4624                         if (valid_entry == NULL || valid_entry->len > entry->len)
4625                                 valid_entry = entry;
4626                 }
4627         }
4628
4629         /* Not find one to satisfy the request, return */
4630         if (valid_entry == NULL) {
4631                 PMD_DRV_LOG(ERR, "No valid entry found");
4632                 return -ENOMEM;
4633         }
4634         /**
4635          * The entry have equal queue number as requested,
4636          * remove it from alloc_list.
4637          */
4638         if (valid_entry->len == num) {
4639                 LIST_REMOVE(valid_entry, next);
4640         } else {
4641                 /**
4642                  * The entry have more numbers than requested,
4643                  * create a new entry for alloc_list and minus its
4644                  * queue base and number in free_list.
4645                  */
4646                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4647                 if (entry == NULL) {
4648                         PMD_DRV_LOG(ERR,
4649                                 "Failed to allocate memory for resource pool");
4650                         return -ENOMEM;
4651                 }
4652                 entry->base = valid_entry->base;
4653                 entry->len = num;
4654                 valid_entry->base += num;
4655                 valid_entry->len -= num;
4656                 valid_entry = entry;
4657         }
4658
4659         /* Insert it into alloc list, not sorted */
4660         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4661
4662         pool->num_free -= valid_entry->len;
4663         pool->num_alloc += valid_entry->len;
4664
4665         return valid_entry->base + pool->base;
4666 }
4667
4668 /**
4669  * bitmap_is_subset - Check whether src2 is subset of src1
4670  **/
4671 static inline int
4672 bitmap_is_subset(uint8_t src1, uint8_t src2)
4673 {
4674         return !((src1 ^ src2) & src2);
4675 }
4676
4677 static enum i40e_status_code
4678 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4679 {
4680         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4681
4682         /* If DCB is not supported, only default TC is supported */
4683         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4684                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4685                 return I40E_NOT_SUPPORTED;
4686         }
4687
4688         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4689                 PMD_DRV_LOG(ERR,
4690                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4691                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4692                 return I40E_NOT_SUPPORTED;
4693         }
4694         return I40E_SUCCESS;
4695 }
4696
4697 int
4698 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4699                                 struct i40e_vsi_vlan_pvid_info *info)
4700 {
4701         struct i40e_hw *hw;
4702         struct i40e_vsi_context ctxt;
4703         uint8_t vlan_flags = 0;
4704         int ret;
4705
4706         if (vsi == NULL || info == NULL) {
4707                 PMD_DRV_LOG(ERR, "invalid parameters");
4708                 return I40E_ERR_PARAM;
4709         }
4710
4711         if (info->on) {
4712                 vsi->info.pvid = info->config.pvid;
4713                 /**
4714                  * If insert pvid is enabled, only tagged pkts are
4715                  * allowed to be sent out.
4716                  */
4717                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4718                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4719         } else {
4720                 vsi->info.pvid = 0;
4721                 if (info->config.reject.tagged == 0)
4722                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4723
4724                 if (info->config.reject.untagged == 0)
4725                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4726         }
4727         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4728                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4729         vsi->info.port_vlan_flags |= vlan_flags;
4730         vsi->info.valid_sections =
4731                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4732         memset(&ctxt, 0, sizeof(ctxt));
4733         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4734         ctxt.seid = vsi->seid;
4735
4736         hw = I40E_VSI_TO_HW(vsi);
4737         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4738         if (ret != I40E_SUCCESS)
4739                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4740
4741         return ret;
4742 }
4743
4744 static int
4745 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4746 {
4747         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4748         int i, ret;
4749         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4750
4751         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4752         if (ret != I40E_SUCCESS)
4753                 return ret;
4754
4755         if (!vsi->seid) {
4756                 PMD_DRV_LOG(ERR, "seid not valid");
4757                 return -EINVAL;
4758         }
4759
4760         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4761         tc_bw_data.tc_valid_bits = enabled_tcmap;
4762         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4763                 tc_bw_data.tc_bw_credits[i] =
4764                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4765
4766         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4767         if (ret != I40E_SUCCESS) {
4768                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4769                 return ret;
4770         }
4771
4772         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4773                                         sizeof(vsi->info.qs_handle));
4774         return I40E_SUCCESS;
4775 }
4776
4777 static enum i40e_status_code
4778 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4779                                  struct i40e_aqc_vsi_properties_data *info,
4780                                  uint8_t enabled_tcmap)
4781 {
4782         enum i40e_status_code ret;
4783         int i, total_tc = 0;
4784         uint16_t qpnum_per_tc, bsf, qp_idx;
4785
4786         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4787         if (ret != I40E_SUCCESS)
4788                 return ret;
4789
4790         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4791                 if (enabled_tcmap & (1 << i))
4792                         total_tc++;
4793         if (total_tc == 0)
4794                 total_tc = 1;
4795         vsi->enabled_tc = enabled_tcmap;
4796
4797         /* Number of queues per enabled TC */
4798         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4799         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4800         bsf = rte_bsf32(qpnum_per_tc);
4801
4802         /* Adjust the queue number to actual queues that can be applied */
4803         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4804                 vsi->nb_qps = qpnum_per_tc * total_tc;
4805
4806         /**
4807          * Configure TC and queue mapping parameters, for enabled TC,
4808          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4809          * default queue will serve it.
4810          */
4811         qp_idx = 0;
4812         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4813                 if (vsi->enabled_tc & (1 << i)) {
4814                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4815                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4816                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4817                         qp_idx += qpnum_per_tc;
4818                 } else
4819                         info->tc_mapping[i] = 0;
4820         }
4821
4822         /* Associate queue number with VSI */
4823         if (vsi->type == I40E_VSI_SRIOV) {
4824                 info->mapping_flags |=
4825                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4826                 for (i = 0; i < vsi->nb_qps; i++)
4827                         info->queue_mapping[i] =
4828                                 rte_cpu_to_le_16(vsi->base_queue + i);
4829         } else {
4830                 info->mapping_flags |=
4831                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4832                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4833         }
4834         info->valid_sections |=
4835                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4836
4837         return I40E_SUCCESS;
4838 }
4839
4840 static int
4841 i40e_veb_release(struct i40e_veb *veb)
4842 {
4843         struct i40e_vsi *vsi;
4844         struct i40e_hw *hw;
4845
4846         if (veb == NULL)
4847                 return -EINVAL;
4848
4849         if (!TAILQ_EMPTY(&veb->head)) {
4850                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4851                 return -EACCES;
4852         }
4853         /* associate_vsi field is NULL for floating VEB */
4854         if (veb->associate_vsi != NULL) {
4855                 vsi = veb->associate_vsi;
4856                 hw = I40E_VSI_TO_HW(vsi);
4857
4858                 vsi->uplink_seid = veb->uplink_seid;
4859                 vsi->veb = NULL;
4860         } else {
4861                 veb->associate_pf->main_vsi->floating_veb = NULL;
4862                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4863         }
4864
4865         i40e_aq_delete_element(hw, veb->seid, NULL);
4866         rte_free(veb);
4867         return I40E_SUCCESS;
4868 }
4869
4870 /* Setup a veb */
4871 static struct i40e_veb *
4872 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4873 {
4874         struct i40e_veb *veb;
4875         int ret;
4876         struct i40e_hw *hw;
4877
4878         if (pf == NULL) {
4879                 PMD_DRV_LOG(ERR,
4880                             "veb setup failed, associated PF shouldn't null");
4881                 return NULL;
4882         }
4883         hw = I40E_PF_TO_HW(pf);
4884
4885         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4886         if (!veb) {
4887                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4888                 goto fail;
4889         }
4890
4891         veb->associate_vsi = vsi;
4892         veb->associate_pf = pf;
4893         TAILQ_INIT(&veb->head);
4894         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4895
4896         /* create floating veb if vsi is NULL */
4897         if (vsi != NULL) {
4898                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4899                                       I40E_DEFAULT_TCMAP, false,
4900                                       &veb->seid, false, NULL);
4901         } else {
4902                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4903                                       true, &veb->seid, false, NULL);
4904         }
4905
4906         if (ret != I40E_SUCCESS) {
4907                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4908                             hw->aq.asq_last_status);
4909                 goto fail;
4910         }
4911         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4912
4913         /* get statistics index */
4914         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4915                                 &veb->stats_idx, NULL, NULL, NULL);
4916         if (ret != I40E_SUCCESS) {
4917                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4918                             hw->aq.asq_last_status);
4919                 goto fail;
4920         }
4921         /* Get VEB bandwidth, to be implemented */
4922         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4923         if (vsi)
4924                 vsi->uplink_seid = veb->seid;
4925
4926         return veb;
4927 fail:
4928         rte_free(veb);
4929         return NULL;
4930 }
4931
4932 int
4933 i40e_vsi_release(struct i40e_vsi *vsi)
4934 {
4935         struct i40e_pf *pf;
4936         struct i40e_hw *hw;
4937         struct i40e_vsi_list *vsi_list;
4938         void *temp;
4939         int ret;
4940         struct i40e_mac_filter *f;
4941         uint16_t user_param;
4942
4943         if (!vsi)
4944                 return I40E_SUCCESS;
4945
4946         if (!vsi->adapter)
4947                 return -EFAULT;
4948
4949         user_param = vsi->user_param;
4950
4951         pf = I40E_VSI_TO_PF(vsi);
4952         hw = I40E_VSI_TO_HW(vsi);
4953
4954         /* VSI has child to attach, release child first */
4955         if (vsi->veb) {
4956                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4957                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4958                                 return -1;
4959                 }
4960                 i40e_veb_release(vsi->veb);
4961         }
4962
4963         if (vsi->floating_veb) {
4964                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4965                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4966                                 return -1;
4967                 }
4968         }
4969
4970         /* Remove all macvlan filters of the VSI */
4971         i40e_vsi_remove_all_macvlan_filter(vsi);
4972         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4973                 rte_free(f);
4974
4975         if (vsi->type != I40E_VSI_MAIN &&
4976             ((vsi->type != I40E_VSI_SRIOV) ||
4977             !pf->floating_veb_list[user_param])) {
4978                 /* Remove vsi from parent's sibling list */
4979                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4980                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4981                         return I40E_ERR_PARAM;
4982                 }
4983                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4984                                 &vsi->sib_vsi_list, list);
4985
4986                 /* Remove all switch element of the VSI */
4987                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4988                 if (ret != I40E_SUCCESS)
4989                         PMD_DRV_LOG(ERR, "Failed to delete element");
4990         }
4991
4992         if ((vsi->type == I40E_VSI_SRIOV) &&
4993             pf->floating_veb_list[user_param]) {
4994                 /* Remove vsi from parent's sibling list */
4995                 if (vsi->parent_vsi == NULL ||
4996                     vsi->parent_vsi->floating_veb == NULL) {
4997                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4998                         return I40E_ERR_PARAM;
4999                 }
5000                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5001                              &vsi->sib_vsi_list, list);
5002
5003                 /* Remove all switch element of the VSI */
5004                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5005                 if (ret != I40E_SUCCESS)
5006                         PMD_DRV_LOG(ERR, "Failed to delete element");
5007         }
5008
5009         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5010
5011         if (vsi->type != I40E_VSI_SRIOV)
5012                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5013         rte_free(vsi);
5014
5015         return I40E_SUCCESS;
5016 }
5017
5018 static int
5019 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5020 {
5021         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5022         struct i40e_aqc_remove_macvlan_element_data def_filter;
5023         struct i40e_mac_filter_info filter;
5024         int ret;
5025
5026         if (vsi->type != I40E_VSI_MAIN)
5027                 return I40E_ERR_CONFIG;
5028         memset(&def_filter, 0, sizeof(def_filter));
5029         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5030                                         ETH_ADDR_LEN);
5031         def_filter.vlan_tag = 0;
5032         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5033                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5034         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5035         if (ret != I40E_SUCCESS) {
5036                 struct i40e_mac_filter *f;
5037                 struct ether_addr *mac;
5038
5039                 PMD_DRV_LOG(DEBUG,
5040                             "Cannot remove the default macvlan filter");
5041                 /* It needs to add the permanent mac into mac list */
5042                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5043                 if (f == NULL) {
5044                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5045                         return I40E_ERR_NO_MEMORY;
5046                 }
5047                 mac = &f->mac_info.mac_addr;
5048                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5049                                 ETH_ADDR_LEN);
5050                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5051                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5052                 vsi->mac_num++;
5053
5054                 return ret;
5055         }
5056         rte_memcpy(&filter.mac_addr,
5057                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5058         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5059         return i40e_vsi_add_mac(vsi, &filter);
5060 }
5061
5062 /*
5063  * i40e_vsi_get_bw_config - Query VSI BW Information
5064  * @vsi: the VSI to be queried
5065  *
5066  * Returns 0 on success, negative value on failure
5067  */
5068 static enum i40e_status_code
5069 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5070 {
5071         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5072         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5073         struct i40e_hw *hw = &vsi->adapter->hw;
5074         i40e_status ret;
5075         int i;
5076         uint32_t bw_max;
5077
5078         memset(&bw_config, 0, sizeof(bw_config));
5079         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5080         if (ret != I40E_SUCCESS) {
5081                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5082                             hw->aq.asq_last_status);
5083                 return ret;
5084         }
5085
5086         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5087         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5088                                         &ets_sla_config, NULL);
5089         if (ret != I40E_SUCCESS) {
5090                 PMD_DRV_LOG(ERR,
5091                         "VSI failed to get TC bandwdith configuration %u",
5092                         hw->aq.asq_last_status);
5093                 return ret;
5094         }
5095
5096         /* store and print out BW info */
5097         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5098         vsi->bw_info.bw_max = bw_config.max_bw;
5099         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5100         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5101         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5102                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5103                      I40E_16_BIT_WIDTH);
5104         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5105                 vsi->bw_info.bw_ets_share_credits[i] =
5106                                 ets_sla_config.share_credits[i];
5107                 vsi->bw_info.bw_ets_credits[i] =
5108                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5109                 /* 4 bits per TC, 4th bit is reserved */
5110                 vsi->bw_info.bw_ets_max[i] =
5111                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5112                                   RTE_LEN2MASK(3, uint8_t));
5113                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5114                             vsi->bw_info.bw_ets_share_credits[i]);
5115                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5116                             vsi->bw_info.bw_ets_credits[i]);
5117                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5118                             vsi->bw_info.bw_ets_max[i]);
5119         }
5120
5121         return I40E_SUCCESS;
5122 }
5123
5124 /* i40e_enable_pf_lb
5125  * @pf: pointer to the pf structure
5126  *
5127  * allow loopback on pf
5128  */
5129 static inline void
5130 i40e_enable_pf_lb(struct i40e_pf *pf)
5131 {
5132         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5133         struct i40e_vsi_context ctxt;
5134         int ret;
5135
5136         /* Use the FW API if FW >= v5.0 */
5137         if (hw->aq.fw_maj_ver < 5) {
5138                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5139                 return;
5140         }
5141
5142         memset(&ctxt, 0, sizeof(ctxt));
5143         ctxt.seid = pf->main_vsi_seid;
5144         ctxt.pf_num = hw->pf_id;
5145         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5146         if (ret) {
5147                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5148                             ret, hw->aq.asq_last_status);
5149                 return;
5150         }
5151         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5152         ctxt.info.valid_sections =
5153                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5154         ctxt.info.switch_id |=
5155                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5156
5157         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5158         if (ret)
5159                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5160                             hw->aq.asq_last_status);
5161 }
5162
5163 /* Setup a VSI */
5164 struct i40e_vsi *
5165 i40e_vsi_setup(struct i40e_pf *pf,
5166                enum i40e_vsi_type type,
5167                struct i40e_vsi *uplink_vsi,
5168                uint16_t user_param)
5169 {
5170         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5171         struct i40e_vsi *vsi;
5172         struct i40e_mac_filter_info filter;
5173         int ret;
5174         struct i40e_vsi_context ctxt;
5175         struct ether_addr broadcast =
5176                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5177
5178         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5179             uplink_vsi == NULL) {
5180                 PMD_DRV_LOG(ERR,
5181                         "VSI setup failed, VSI link shouldn't be NULL");
5182                 return NULL;
5183         }
5184
5185         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5186                 PMD_DRV_LOG(ERR,
5187                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5188                 return NULL;
5189         }
5190
5191         /* two situations
5192          * 1.type is not MAIN and uplink vsi is not NULL
5193          * If uplink vsi didn't setup VEB, create one first under veb field
5194          * 2.type is SRIOV and the uplink is NULL
5195          * If floating VEB is NULL, create one veb under floating veb field
5196          */
5197
5198         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5199             uplink_vsi->veb == NULL) {
5200                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5201
5202                 if (uplink_vsi->veb == NULL) {
5203                         PMD_DRV_LOG(ERR, "VEB setup failed");
5204                         return NULL;
5205                 }
5206                 /* set ALLOWLOOPBACk on pf, when veb is created */
5207                 i40e_enable_pf_lb(pf);
5208         }
5209
5210         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5211             pf->main_vsi->floating_veb == NULL) {
5212                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5213
5214                 if (pf->main_vsi->floating_veb == NULL) {
5215                         PMD_DRV_LOG(ERR, "VEB setup failed");
5216                         return NULL;
5217                 }
5218         }
5219
5220         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5221         if (!vsi) {
5222                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5223                 return NULL;
5224         }
5225         TAILQ_INIT(&vsi->mac_list);
5226         vsi->type = type;
5227         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5228         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5229         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5230         vsi->user_param = user_param;
5231         vsi->vlan_anti_spoof_on = 0;
5232         vsi->vlan_filter_on = 0;
5233         /* Allocate queues */
5234         switch (vsi->type) {
5235         case I40E_VSI_MAIN  :
5236                 vsi->nb_qps = pf->lan_nb_qps;
5237                 break;
5238         case I40E_VSI_SRIOV :
5239                 vsi->nb_qps = pf->vf_nb_qps;
5240                 break;
5241         case I40E_VSI_VMDQ2:
5242                 vsi->nb_qps = pf->vmdq_nb_qps;
5243                 break;
5244         case I40E_VSI_FDIR:
5245                 vsi->nb_qps = pf->fdir_nb_qps;
5246                 break;
5247         default:
5248                 goto fail_mem;
5249         }
5250         /*
5251          * The filter status descriptor is reported in rx queue 0,
5252          * while the tx queue for fdir filter programming has no
5253          * such constraints, can be non-zero queues.
5254          * To simplify it, choose FDIR vsi use queue 0 pair.
5255          * To make sure it will use queue 0 pair, queue allocation
5256          * need be done before this function is called
5257          */
5258         if (type != I40E_VSI_FDIR) {
5259                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5260                         if (ret < 0) {
5261                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5262                                                 vsi->seid, ret);
5263                                 goto fail_mem;
5264                         }
5265                         vsi->base_queue = ret;
5266         } else
5267                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5268
5269         /* VF has MSIX interrupt in VF range, don't allocate here */
5270         if (type == I40E_VSI_MAIN) {
5271                 if (pf->support_multi_driver) {
5272                         /* If support multi-driver, need to use INT0 instead of
5273                          * allocating from msix pool. The Msix pool is init from
5274                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5275                          * to 1 without calling i40e_res_pool_alloc.
5276                          */
5277                         vsi->msix_intr = 0;
5278                         vsi->nb_msix = 1;
5279                 } else {
5280                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5281                                                   RTE_MIN(vsi->nb_qps,
5282                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5283                         if (ret < 0) {
5284                                 PMD_DRV_LOG(ERR,
5285                                             "VSI MAIN %d get heap failed %d",
5286                                             vsi->seid, ret);
5287                                 goto fail_queue_alloc;
5288                         }
5289                         vsi->msix_intr = ret;
5290                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5291                                                RTE_MAX_RXTX_INTR_VEC_ID);
5292                 }
5293         } else if (type != I40E_VSI_SRIOV) {
5294                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5295                 if (ret < 0) {
5296                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5297                         goto fail_queue_alloc;
5298                 }
5299                 vsi->msix_intr = ret;
5300                 vsi->nb_msix = 1;
5301         } else {
5302                 vsi->msix_intr = 0;
5303                 vsi->nb_msix = 0;
5304         }
5305
5306         /* Add VSI */
5307         if (type == I40E_VSI_MAIN) {
5308                 /* For main VSI, no need to add since it's default one */
5309                 vsi->uplink_seid = pf->mac_seid;
5310                 vsi->seid = pf->main_vsi_seid;
5311                 /* Bind queues with specific MSIX interrupt */
5312                 /**
5313                  * Needs 2 interrupt at least, one for misc cause which will
5314                  * enabled from OS side, Another for queues binding the
5315                  * interrupt from device side only.
5316                  */
5317
5318                 /* Get default VSI parameters from hardware */
5319                 memset(&ctxt, 0, sizeof(ctxt));
5320                 ctxt.seid = vsi->seid;
5321                 ctxt.pf_num = hw->pf_id;
5322                 ctxt.uplink_seid = vsi->uplink_seid;
5323                 ctxt.vf_num = 0;
5324                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5325                 if (ret != I40E_SUCCESS) {
5326                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5327                         goto fail_msix_alloc;
5328                 }
5329                 rte_memcpy(&vsi->info, &ctxt.info,
5330                         sizeof(struct i40e_aqc_vsi_properties_data));
5331                 vsi->vsi_id = ctxt.vsi_number;
5332                 vsi->info.valid_sections = 0;
5333
5334                 /* Configure tc, enabled TC0 only */
5335                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5336                         I40E_SUCCESS) {
5337                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5338                         goto fail_msix_alloc;
5339                 }
5340
5341                 /* TC, queue mapping */
5342                 memset(&ctxt, 0, sizeof(ctxt));
5343                 vsi->info.valid_sections |=
5344                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5345                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5346                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5347                 rte_memcpy(&ctxt.info, &vsi->info,
5348                         sizeof(struct i40e_aqc_vsi_properties_data));
5349                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5350                                                 I40E_DEFAULT_TCMAP);
5351                 if (ret != I40E_SUCCESS) {
5352                         PMD_DRV_LOG(ERR,
5353                                 "Failed to configure TC queue mapping");
5354                         goto fail_msix_alloc;
5355                 }
5356                 ctxt.seid = vsi->seid;
5357                 ctxt.pf_num = hw->pf_id;
5358                 ctxt.uplink_seid = vsi->uplink_seid;
5359                 ctxt.vf_num = 0;
5360
5361                 /* Update VSI parameters */
5362                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5363                 if (ret != I40E_SUCCESS) {
5364                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5365                         goto fail_msix_alloc;
5366                 }
5367
5368                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5369                                                 sizeof(vsi->info.tc_mapping));
5370                 rte_memcpy(&vsi->info.queue_mapping,
5371                                 &ctxt.info.queue_mapping,
5372                         sizeof(vsi->info.queue_mapping));
5373                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5374                 vsi->info.valid_sections = 0;
5375
5376                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5377                                 ETH_ADDR_LEN);
5378
5379                 /**
5380                  * Updating default filter settings are necessary to prevent
5381                  * reception of tagged packets.
5382                  * Some old firmware configurations load a default macvlan
5383                  * filter which accepts both tagged and untagged packets.
5384                  * The updating is to use a normal filter instead if needed.
5385                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5386                  * The firmware with correct configurations load the default
5387                  * macvlan filter which is expected and cannot be removed.
5388                  */
5389                 i40e_update_default_filter_setting(vsi);
5390                 i40e_config_qinq(hw, vsi);
5391         } else if (type == I40E_VSI_SRIOV) {
5392                 memset(&ctxt, 0, sizeof(ctxt));
5393                 /**
5394                  * For other VSI, the uplink_seid equals to uplink VSI's
5395                  * uplink_seid since they share same VEB
5396                  */
5397                 if (uplink_vsi == NULL)
5398                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5399                 else
5400                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5401                 ctxt.pf_num = hw->pf_id;
5402                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5403                 ctxt.uplink_seid = vsi->uplink_seid;
5404                 ctxt.connection_type = 0x1;
5405                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5406
5407                 /* Use the VEB configuration if FW >= v5.0 */
5408                 if (hw->aq.fw_maj_ver >= 5) {
5409                         /* Configure switch ID */
5410                         ctxt.info.valid_sections |=
5411                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5412                         ctxt.info.switch_id =
5413                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5414                 }
5415
5416                 /* Configure port/vlan */
5417                 ctxt.info.valid_sections |=
5418                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5419                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5420                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5421                                                 hw->func_caps.enabled_tcmap);
5422                 if (ret != I40E_SUCCESS) {
5423                         PMD_DRV_LOG(ERR,
5424                                 "Failed to configure TC queue mapping");
5425                         goto fail_msix_alloc;
5426                 }
5427
5428                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5429                 ctxt.info.valid_sections |=
5430                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5431                 /**
5432                  * Since VSI is not created yet, only configure parameter,
5433                  * will add vsi below.
5434                  */
5435
5436                 i40e_config_qinq(hw, vsi);
5437         } else if (type == I40E_VSI_VMDQ2) {
5438                 memset(&ctxt, 0, sizeof(ctxt));
5439                 /*
5440                  * For other VSI, the uplink_seid equals to uplink VSI's
5441                  * uplink_seid since they share same VEB
5442                  */
5443                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5444                 ctxt.pf_num = hw->pf_id;
5445                 ctxt.vf_num = 0;
5446                 ctxt.uplink_seid = vsi->uplink_seid;
5447                 ctxt.connection_type = 0x1;
5448                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5449
5450                 ctxt.info.valid_sections |=
5451                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5452                 /* user_param carries flag to enable loop back */
5453                 if (user_param) {
5454                         ctxt.info.switch_id =
5455                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5456                         ctxt.info.switch_id |=
5457                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5458                 }
5459
5460                 /* Configure port/vlan */
5461                 ctxt.info.valid_sections |=
5462                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5463                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5464                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5465                                                 I40E_DEFAULT_TCMAP);
5466                 if (ret != I40E_SUCCESS) {
5467                         PMD_DRV_LOG(ERR,
5468                                 "Failed to configure TC queue mapping");
5469                         goto fail_msix_alloc;
5470                 }
5471                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5472                 ctxt.info.valid_sections |=
5473                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5474         } else if (type == I40E_VSI_FDIR) {
5475                 memset(&ctxt, 0, sizeof(ctxt));
5476                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5477                 ctxt.pf_num = hw->pf_id;
5478                 ctxt.vf_num = 0;
5479                 ctxt.uplink_seid = vsi->uplink_seid;
5480                 ctxt.connection_type = 0x1;     /* regular data port */
5481                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5482                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5483                                                 I40E_DEFAULT_TCMAP);
5484                 if (ret != I40E_SUCCESS) {
5485                         PMD_DRV_LOG(ERR,
5486                                 "Failed to configure TC queue mapping.");
5487                         goto fail_msix_alloc;
5488                 }
5489                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5490                 ctxt.info.valid_sections |=
5491                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5492         } else {
5493                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5494                 goto fail_msix_alloc;
5495         }
5496
5497         if (vsi->type != I40E_VSI_MAIN) {
5498                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5499                 if (ret != I40E_SUCCESS) {
5500                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5501                                     hw->aq.asq_last_status);
5502                         goto fail_msix_alloc;
5503                 }
5504                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5505                 vsi->info.valid_sections = 0;
5506                 vsi->seid = ctxt.seid;
5507                 vsi->vsi_id = ctxt.vsi_number;
5508                 vsi->sib_vsi_list.vsi = vsi;
5509                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5510                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5511                                           &vsi->sib_vsi_list, list);
5512                 } else {
5513                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5514                                           &vsi->sib_vsi_list, list);
5515                 }
5516         }
5517
5518         /* MAC/VLAN configuration */
5519         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5520         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5521
5522         ret = i40e_vsi_add_mac(vsi, &filter);
5523         if (ret != I40E_SUCCESS) {
5524                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5525                 goto fail_msix_alloc;
5526         }
5527
5528         /* Get VSI BW information */
5529         i40e_vsi_get_bw_config(vsi);
5530         return vsi;
5531 fail_msix_alloc:
5532         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5533 fail_queue_alloc:
5534         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5535 fail_mem:
5536         rte_free(vsi);
5537         return NULL;
5538 }
5539
5540 /* Configure vlan filter on or off */
5541 int
5542 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5543 {
5544         int i, num;
5545         struct i40e_mac_filter *f;
5546         void *temp;
5547         struct i40e_mac_filter_info *mac_filter;
5548         enum rte_mac_filter_type desired_filter;
5549         int ret = I40E_SUCCESS;
5550
5551         if (on) {
5552                 /* Filter to match MAC and VLAN */
5553                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5554         } else {
5555                 /* Filter to match only MAC */
5556                 desired_filter = RTE_MAC_PERFECT_MATCH;
5557         }
5558
5559         num = vsi->mac_num;
5560
5561         mac_filter = rte_zmalloc("mac_filter_info_data",
5562                                  num * sizeof(*mac_filter), 0);
5563         if (mac_filter == NULL) {
5564                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5565                 return I40E_ERR_NO_MEMORY;
5566         }
5567
5568         i = 0;
5569
5570         /* Remove all existing mac */
5571         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5572                 mac_filter[i] = f->mac_info;
5573                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5574                 if (ret) {
5575                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5576                                     on ? "enable" : "disable");
5577                         goto DONE;
5578                 }
5579                 i++;
5580         }
5581
5582         /* Override with new filter */
5583         for (i = 0; i < num; i++) {
5584                 mac_filter[i].filter_type = desired_filter;
5585                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5586                 if (ret) {
5587                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5588                                     on ? "enable" : "disable");
5589                         goto DONE;
5590                 }
5591         }
5592
5593 DONE:
5594         rte_free(mac_filter);
5595         return ret;
5596 }
5597
5598 /* Configure vlan stripping on or off */
5599 int
5600 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5601 {
5602         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5603         struct i40e_vsi_context ctxt;
5604         uint8_t vlan_flags;
5605         int ret = I40E_SUCCESS;
5606
5607         /* Check if it has been already on or off */
5608         if (vsi->info.valid_sections &
5609                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5610                 if (on) {
5611                         if ((vsi->info.port_vlan_flags &
5612                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5613                                 return 0; /* already on */
5614                 } else {
5615                         if ((vsi->info.port_vlan_flags &
5616                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5617                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5618                                 return 0; /* already off */
5619                 }
5620         }
5621
5622         if (on)
5623                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5624         else
5625                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5626         vsi->info.valid_sections =
5627                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5628         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5629         vsi->info.port_vlan_flags |= vlan_flags;
5630         ctxt.seid = vsi->seid;
5631         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5632         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5633         if (ret)
5634                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5635                             on ? "enable" : "disable");
5636
5637         return ret;
5638 }
5639
5640 static int
5641 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5642 {
5643         struct rte_eth_dev_data *data = dev->data;
5644         int ret;
5645         int mask = 0;
5646
5647         /* Apply vlan offload setting */
5648         mask = ETH_VLAN_STRIP_MASK |
5649                ETH_VLAN_FILTER_MASK |
5650                ETH_VLAN_EXTEND_MASK;
5651         ret = i40e_vlan_offload_set(dev, mask);
5652         if (ret) {
5653                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5654                 return ret;
5655         }
5656
5657         /* Apply pvid setting */
5658         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5659                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5660         if (ret)
5661                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5662
5663         return ret;
5664 }
5665
5666 static int
5667 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5668 {
5669         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5670
5671         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5672 }
5673
5674 static int
5675 i40e_update_flow_control(struct i40e_hw *hw)
5676 {
5677 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5678         struct i40e_link_status link_status;
5679         uint32_t rxfc = 0, txfc = 0, reg;
5680         uint8_t an_info;
5681         int ret;
5682
5683         memset(&link_status, 0, sizeof(link_status));
5684         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5685         if (ret != I40E_SUCCESS) {
5686                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5687                 goto write_reg; /* Disable flow control */
5688         }
5689
5690         an_info = hw->phy.link_info.an_info;
5691         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5692                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5693                 ret = I40E_ERR_NOT_READY;
5694                 goto write_reg; /* Disable flow control */
5695         }
5696         /**
5697          * If link auto negotiation is enabled, flow control needs to
5698          * be configured according to it
5699          */
5700         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5701         case I40E_LINK_PAUSE_RXTX:
5702                 rxfc = 1;
5703                 txfc = 1;
5704                 hw->fc.current_mode = I40E_FC_FULL;
5705                 break;
5706         case I40E_AQ_LINK_PAUSE_RX:
5707                 rxfc = 1;
5708                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5709                 break;
5710         case I40E_AQ_LINK_PAUSE_TX:
5711                 txfc = 1;
5712                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5713                 break;
5714         default:
5715                 hw->fc.current_mode = I40E_FC_NONE;
5716                 break;
5717         }
5718
5719 write_reg:
5720         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5721                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5722         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5723         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5724         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5725         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5726
5727         return ret;
5728 }
5729
5730 /* PF setup */
5731 static int
5732 i40e_pf_setup(struct i40e_pf *pf)
5733 {
5734         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5735         struct i40e_filter_control_settings settings;
5736         struct i40e_vsi *vsi;
5737         int ret;
5738
5739         /* Clear all stats counters */
5740         pf->offset_loaded = FALSE;
5741         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5742         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5743         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5744         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5745
5746         ret = i40e_pf_get_switch_config(pf);
5747         if (ret != I40E_SUCCESS) {
5748                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5749                 return ret;
5750         }
5751         if (pf->flags & I40E_FLAG_FDIR) {
5752                 /* make queue allocated first, let FDIR use queue pair 0*/
5753                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5754                 if (ret != I40E_FDIR_QUEUE_ID) {
5755                         PMD_DRV_LOG(ERR,
5756                                 "queue allocation fails for FDIR: ret =%d",
5757                                 ret);
5758                         pf->flags &= ~I40E_FLAG_FDIR;
5759                 }
5760         }
5761         /*  main VSI setup */
5762         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5763         if (!vsi) {
5764                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5765                 return I40E_ERR_NOT_READY;
5766         }
5767         pf->main_vsi = vsi;
5768
5769         /* Configure filter control */
5770         memset(&settings, 0, sizeof(settings));
5771         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5772                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5773         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5774                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5775         else {
5776                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5777                         hw->func_caps.rss_table_size);
5778                 return I40E_ERR_PARAM;
5779         }
5780         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5781                 hw->func_caps.rss_table_size);
5782         pf->hash_lut_size = hw->func_caps.rss_table_size;
5783
5784         /* Enable ethtype and macvlan filters */
5785         settings.enable_ethtype = TRUE;
5786         settings.enable_macvlan = TRUE;
5787         ret = i40e_set_filter_control(hw, &settings);
5788         if (ret)
5789                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5790                                                                 ret);
5791
5792         /* Update flow control according to the auto negotiation */
5793         i40e_update_flow_control(hw);
5794
5795         return I40E_SUCCESS;
5796 }
5797
5798 int
5799 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5800 {
5801         uint32_t reg;
5802         uint16_t j;
5803
5804         /**
5805          * Set or clear TX Queue Disable flags,
5806          * which is required by hardware.
5807          */
5808         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5809         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5810
5811         /* Wait until the request is finished */
5812         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5813                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5814                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5815                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5816                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5817                                                         & 0x1))) {
5818                         break;
5819                 }
5820         }
5821         if (on) {
5822                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5823                         return I40E_SUCCESS; /* already on, skip next steps */
5824
5825                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5826                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5827         } else {
5828                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5829                         return I40E_SUCCESS; /* already off, skip next steps */
5830                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5831         }
5832         /* Write the register */
5833         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5834         /* Check the result */
5835         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5836                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5837                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5838                 if (on) {
5839                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5840                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5841                                 break;
5842                 } else {
5843                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5844                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5845                                 break;
5846                 }
5847         }
5848         /* Check if it is timeout */
5849         if (j >= I40E_CHK_Q_ENA_COUNT) {
5850                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5851                             (on ? "enable" : "disable"), q_idx);
5852                 return I40E_ERR_TIMEOUT;
5853         }
5854
5855         return I40E_SUCCESS;
5856 }
5857
5858 /* Swith on or off the tx queues */
5859 static int
5860 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5861 {
5862         struct rte_eth_dev_data *dev_data = pf->dev_data;
5863         struct i40e_tx_queue *txq;
5864         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5865         uint16_t i;
5866         int ret;
5867
5868         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5869                 txq = dev_data->tx_queues[i];
5870                 /* Don't operate the queue if not configured or
5871                  * if starting only per queue */
5872                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5873                         continue;
5874                 if (on)
5875                         ret = i40e_dev_tx_queue_start(dev, i);
5876                 else
5877                         ret = i40e_dev_tx_queue_stop(dev, i);
5878                 if ( ret != I40E_SUCCESS)
5879                         return ret;
5880         }
5881
5882         return I40E_SUCCESS;
5883 }
5884
5885 int
5886 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5887 {
5888         uint32_t reg;
5889         uint16_t j;
5890
5891         /* Wait until the request is finished */
5892         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5893                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5894                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5895                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5896                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5897                         break;
5898         }
5899
5900         if (on) {
5901                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5902                         return I40E_SUCCESS; /* Already on, skip next steps */
5903                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5904         } else {
5905                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5906                         return I40E_SUCCESS; /* Already off, skip next steps */
5907                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5908         }
5909
5910         /* Write the register */
5911         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5912         /* Check the result */
5913         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5914                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5915                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5916                 if (on) {
5917                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5918                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5919                                 break;
5920                 } else {
5921                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5922                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5923                                 break;
5924                 }
5925         }
5926
5927         /* Check if it is timeout */
5928         if (j >= I40E_CHK_Q_ENA_COUNT) {
5929                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5930                             (on ? "enable" : "disable"), q_idx);
5931                 return I40E_ERR_TIMEOUT;
5932         }
5933
5934         return I40E_SUCCESS;
5935 }
5936 /* Switch on or off the rx queues */
5937 static int
5938 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5939 {
5940         struct rte_eth_dev_data *dev_data = pf->dev_data;
5941         struct i40e_rx_queue *rxq;
5942         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5943         uint16_t i;
5944         int ret;
5945
5946         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5947                 rxq = dev_data->rx_queues[i];
5948                 /* Don't operate the queue if not configured or
5949                  * if starting only per queue */
5950                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5951                         continue;
5952                 if (on)
5953                         ret = i40e_dev_rx_queue_start(dev, i);
5954                 else
5955                         ret = i40e_dev_rx_queue_stop(dev, i);
5956                 if (ret != I40E_SUCCESS)
5957                         return ret;
5958         }
5959
5960         return I40E_SUCCESS;
5961 }
5962
5963 /* Switch on or off all the rx/tx queues */
5964 int
5965 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5966 {
5967         int ret;
5968
5969         if (on) {
5970                 /* enable rx queues before enabling tx queues */
5971                 ret = i40e_dev_switch_rx_queues(pf, on);
5972                 if (ret) {
5973                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5974                         return ret;
5975                 }
5976                 ret = i40e_dev_switch_tx_queues(pf, on);
5977         } else {
5978                 /* Stop tx queues before stopping rx queues */
5979                 ret = i40e_dev_switch_tx_queues(pf, on);
5980                 if (ret) {
5981                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5982                         return ret;
5983                 }
5984                 ret = i40e_dev_switch_rx_queues(pf, on);
5985         }
5986
5987         return ret;
5988 }
5989
5990 /* Initialize VSI for TX */
5991 static int
5992 i40e_dev_tx_init(struct i40e_pf *pf)
5993 {
5994         struct rte_eth_dev_data *data = pf->dev_data;
5995         uint16_t i;
5996         uint32_t ret = I40E_SUCCESS;
5997         struct i40e_tx_queue *txq;
5998
5999         for (i = 0; i < data->nb_tx_queues; i++) {
6000                 txq = data->tx_queues[i];
6001                 if (!txq || !txq->q_set)
6002                         continue;
6003                 ret = i40e_tx_queue_init(txq);
6004                 if (ret != I40E_SUCCESS)
6005                         break;
6006         }
6007         if (ret == I40E_SUCCESS)
6008                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6009                                      ->eth_dev);
6010
6011         return ret;
6012 }
6013
6014 /* Initialize VSI for RX */
6015 static int
6016 i40e_dev_rx_init(struct i40e_pf *pf)
6017 {
6018         struct rte_eth_dev_data *data = pf->dev_data;
6019         int ret = I40E_SUCCESS;
6020         uint16_t i;
6021         struct i40e_rx_queue *rxq;
6022
6023         i40e_pf_config_mq_rx(pf);
6024         for (i = 0; i < data->nb_rx_queues; i++) {
6025                 rxq = data->rx_queues[i];
6026                 if (!rxq || !rxq->q_set)
6027                         continue;
6028
6029                 ret = i40e_rx_queue_init(rxq);
6030                 if (ret != I40E_SUCCESS) {
6031                         PMD_DRV_LOG(ERR,
6032                                 "Failed to do RX queue initialization");
6033                         break;
6034                 }
6035         }
6036         if (ret == I40E_SUCCESS)
6037                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6038                                      ->eth_dev);
6039
6040         return ret;
6041 }
6042
6043 static int
6044 i40e_dev_rxtx_init(struct i40e_pf *pf)
6045 {
6046         int err;
6047
6048         err = i40e_dev_tx_init(pf);
6049         if (err) {
6050                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6051                 return err;
6052         }
6053         err = i40e_dev_rx_init(pf);
6054         if (err) {
6055                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6056                 return err;
6057         }
6058
6059         return err;
6060 }
6061
6062 static int
6063 i40e_vmdq_setup(struct rte_eth_dev *dev)
6064 {
6065         struct rte_eth_conf *conf = &dev->data->dev_conf;
6066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6067         int i, err, conf_vsis, j, loop;
6068         struct i40e_vsi *vsi;
6069         struct i40e_vmdq_info *vmdq_info;
6070         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6071         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6072
6073         /*
6074          * Disable interrupt to avoid message from VF. Furthermore, it will
6075          * avoid race condition in VSI creation/destroy.
6076          */
6077         i40e_pf_disable_irq0(hw);
6078
6079         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6080                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6081                 return -ENOTSUP;
6082         }
6083
6084         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6085         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6086                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6087                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6088                         pf->max_nb_vmdq_vsi);
6089                 return -ENOTSUP;
6090         }
6091
6092         if (pf->vmdq != NULL) {
6093                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6094                 return 0;
6095         }
6096
6097         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6098                                 sizeof(*vmdq_info) * conf_vsis, 0);
6099
6100         if (pf->vmdq == NULL) {
6101                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6102                 return -ENOMEM;
6103         }
6104
6105         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6106
6107         /* Create VMDQ VSI */
6108         for (i = 0; i < conf_vsis; i++) {
6109                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6110                                 vmdq_conf->enable_loop_back);
6111                 if (vsi == NULL) {
6112                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6113                         err = -1;
6114                         goto err_vsi_setup;
6115                 }
6116                 vmdq_info = &pf->vmdq[i];
6117                 vmdq_info->pf = pf;
6118                 vmdq_info->vsi = vsi;
6119         }
6120         pf->nb_cfg_vmdq_vsi = conf_vsis;
6121
6122         /* Configure Vlan */
6123         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6124         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6125                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6126                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6127                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6128                                         vmdq_conf->pool_map[i].vlan_id, j);
6129
6130                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6131                                                 vmdq_conf->pool_map[i].vlan_id);
6132                                 if (err) {
6133                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6134                                         err = -1;
6135                                         goto err_vsi_setup;
6136                                 }
6137                         }
6138                 }
6139         }
6140
6141         i40e_pf_enable_irq0(hw);
6142
6143         return 0;
6144
6145 err_vsi_setup:
6146         for (i = 0; i < conf_vsis; i++)
6147                 if (pf->vmdq[i].vsi == NULL)
6148                         break;
6149                 else
6150                         i40e_vsi_release(pf->vmdq[i].vsi);
6151
6152         rte_free(pf->vmdq);
6153         pf->vmdq = NULL;
6154         i40e_pf_enable_irq0(hw);
6155         return err;
6156 }
6157
6158 static void
6159 i40e_stat_update_32(struct i40e_hw *hw,
6160                    uint32_t reg,
6161                    bool offset_loaded,
6162                    uint64_t *offset,
6163                    uint64_t *stat)
6164 {
6165         uint64_t new_data;
6166
6167         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6168         if (!offset_loaded)
6169                 *offset = new_data;
6170
6171         if (new_data >= *offset)
6172                 *stat = (uint64_t)(new_data - *offset);
6173         else
6174                 *stat = (uint64_t)((new_data +
6175                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6176 }
6177
6178 static void
6179 i40e_stat_update_48(struct i40e_hw *hw,
6180                    uint32_t hireg,
6181                    uint32_t loreg,
6182                    bool offset_loaded,
6183                    uint64_t *offset,
6184                    uint64_t *stat)
6185 {
6186         uint64_t new_data;
6187
6188         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6189         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6190                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6191
6192         if (!offset_loaded)
6193                 *offset = new_data;
6194
6195         if (new_data >= *offset)
6196                 *stat = new_data - *offset;
6197         else
6198                 *stat = (uint64_t)((new_data +
6199                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6200
6201         *stat &= I40E_48_BIT_MASK;
6202 }
6203
6204 /* Disable IRQ0 */
6205 void
6206 i40e_pf_disable_irq0(struct i40e_hw *hw)
6207 {
6208         /* Disable all interrupt types */
6209         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6210                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6211         I40E_WRITE_FLUSH(hw);
6212 }
6213
6214 /* Enable IRQ0 */
6215 void
6216 i40e_pf_enable_irq0(struct i40e_hw *hw)
6217 {
6218         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6219                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6220                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6221                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6222         I40E_WRITE_FLUSH(hw);
6223 }
6224
6225 static void
6226 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6227 {
6228         /* read pending request and disable first */
6229         i40e_pf_disable_irq0(hw);
6230         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6231         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6232                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6233
6234         if (no_queue)
6235                 /* Link no queues with irq0 */
6236                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6237                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6238 }
6239
6240 static void
6241 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6242 {
6243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6244         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6245         int i;
6246         uint16_t abs_vf_id;
6247         uint32_t index, offset, val;
6248
6249         if (!pf->vfs)
6250                 return;
6251         /**
6252          * Try to find which VF trigger a reset, use absolute VF id to access
6253          * since the reg is global register.
6254          */
6255         for (i = 0; i < pf->vf_num; i++) {
6256                 abs_vf_id = hw->func_caps.vf_base_id + i;
6257                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6258                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6259                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6260                 /* VFR event occurred */
6261                 if (val & (0x1 << offset)) {
6262                         int ret;
6263
6264                         /* Clear the event first */
6265                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6266                                                         (0x1 << offset));
6267                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6268                         /**
6269                          * Only notify a VF reset event occurred,
6270                          * don't trigger another SW reset
6271                          */
6272                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6273                         if (ret != I40E_SUCCESS)
6274                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6275                 }
6276         }
6277 }
6278
6279 static void
6280 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6281 {
6282         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6283         int i;
6284
6285         for (i = 0; i < pf->vf_num; i++)
6286                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6287 }
6288
6289 static void
6290 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6291 {
6292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6293         struct i40e_arq_event_info info;
6294         uint16_t pending, opcode;
6295         int ret;
6296
6297         info.buf_len = I40E_AQ_BUF_SZ;
6298         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6299         if (!info.msg_buf) {
6300                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6301                 return;
6302         }
6303
6304         pending = 1;
6305         while (pending) {
6306                 ret = i40e_clean_arq_element(hw, &info, &pending);
6307
6308                 if (ret != I40E_SUCCESS) {
6309                         PMD_DRV_LOG(INFO,
6310                                 "Failed to read msg from AdminQ, aq_err: %u",
6311                                 hw->aq.asq_last_status);
6312                         break;
6313                 }
6314                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6315
6316                 switch (opcode) {
6317                 case i40e_aqc_opc_send_msg_to_pf:
6318                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6319                         i40e_pf_host_handle_vf_msg(dev,
6320                                         rte_le_to_cpu_16(info.desc.retval),
6321                                         rte_le_to_cpu_32(info.desc.cookie_high),
6322                                         rte_le_to_cpu_32(info.desc.cookie_low),
6323                                         info.msg_buf,
6324                                         info.msg_len);
6325                         break;
6326                 case i40e_aqc_opc_get_link_status:
6327                         ret = i40e_dev_link_update(dev, 0);
6328                         if (!ret)
6329                                 _rte_eth_dev_callback_process(dev,
6330                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6331                         break;
6332                 default:
6333                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6334                                     opcode);
6335                         break;
6336                 }
6337         }
6338         rte_free(info.msg_buf);
6339 }
6340
6341 /**
6342  * Interrupt handler triggered by NIC  for handling
6343  * specific interrupt.
6344  *
6345  * @param handle
6346  *  Pointer to interrupt handle.
6347  * @param param
6348  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6349  *
6350  * @return
6351  *  void
6352  */
6353 static void
6354 i40e_dev_interrupt_handler(void *param)
6355 {
6356         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6357         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6358         uint32_t icr0;
6359
6360         /* Disable interrupt */
6361         i40e_pf_disable_irq0(hw);
6362
6363         /* read out interrupt causes */
6364         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6365
6366         /* No interrupt event indicated */
6367         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6368                 PMD_DRV_LOG(INFO, "No interrupt event");
6369                 goto done;
6370         }
6371         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6372                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6373         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6374                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6375         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6376                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6377         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6378                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6379         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6380                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6381         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6382                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6383         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6384                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6385
6386         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6387                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6388                 i40e_dev_handle_vfr_event(dev);
6389         }
6390         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6391                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6392                 i40e_dev_handle_aq_msg(dev);
6393         }
6394
6395 done:
6396         /* Enable interrupt */
6397         i40e_pf_enable_irq0(hw);
6398         rte_intr_enable(dev->intr_handle);
6399 }
6400
6401 int
6402 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6403                          struct i40e_macvlan_filter *filter,
6404                          int total)
6405 {
6406         int ele_num, ele_buff_size;
6407         int num, actual_num, i;
6408         uint16_t flags;
6409         int ret = I40E_SUCCESS;
6410         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6411         struct i40e_aqc_add_macvlan_element_data *req_list;
6412
6413         if (filter == NULL  || total == 0)
6414                 return I40E_ERR_PARAM;
6415         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6416         ele_buff_size = hw->aq.asq_buf_size;
6417
6418         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6419         if (req_list == NULL) {
6420                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6421                 return I40E_ERR_NO_MEMORY;
6422         }
6423
6424         num = 0;
6425         do {
6426                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6427                 memset(req_list, 0, ele_buff_size);
6428
6429                 for (i = 0; i < actual_num; i++) {
6430                         rte_memcpy(req_list[i].mac_addr,
6431                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6432                         req_list[i].vlan_tag =
6433                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6434
6435                         switch (filter[num + i].filter_type) {
6436                         case RTE_MAC_PERFECT_MATCH:
6437                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6438                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6439                                 break;
6440                         case RTE_MACVLAN_PERFECT_MATCH:
6441                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6442                                 break;
6443                         case RTE_MAC_HASH_MATCH:
6444                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6445                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6446                                 break;
6447                         case RTE_MACVLAN_HASH_MATCH:
6448                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6449                                 break;
6450                         default:
6451                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6452                                 ret = I40E_ERR_PARAM;
6453                                 goto DONE;
6454                         }
6455
6456                         req_list[i].queue_number = 0;
6457
6458                         req_list[i].flags = rte_cpu_to_le_16(flags);
6459                 }
6460
6461                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6462                                                 actual_num, NULL);
6463                 if (ret != I40E_SUCCESS) {
6464                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6465                         goto DONE;
6466                 }
6467                 num += actual_num;
6468         } while (num < total);
6469
6470 DONE:
6471         rte_free(req_list);
6472         return ret;
6473 }
6474
6475 int
6476 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6477                             struct i40e_macvlan_filter *filter,
6478                             int total)
6479 {
6480         int ele_num, ele_buff_size;
6481         int num, actual_num, i;
6482         uint16_t flags;
6483         int ret = I40E_SUCCESS;
6484         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6485         struct i40e_aqc_remove_macvlan_element_data *req_list;
6486
6487         if (filter == NULL  || total == 0)
6488                 return I40E_ERR_PARAM;
6489
6490         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6491         ele_buff_size = hw->aq.asq_buf_size;
6492
6493         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6494         if (req_list == NULL) {
6495                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6496                 return I40E_ERR_NO_MEMORY;
6497         }
6498
6499         num = 0;
6500         do {
6501                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6502                 memset(req_list, 0, ele_buff_size);
6503
6504                 for (i = 0; i < actual_num; i++) {
6505                         rte_memcpy(req_list[i].mac_addr,
6506                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6507                         req_list[i].vlan_tag =
6508                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6509
6510                         switch (filter[num + i].filter_type) {
6511                         case RTE_MAC_PERFECT_MATCH:
6512                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6513                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6514                                 break;
6515                         case RTE_MACVLAN_PERFECT_MATCH:
6516                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6517                                 break;
6518                         case RTE_MAC_HASH_MATCH:
6519                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6520                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6521                                 break;
6522                         case RTE_MACVLAN_HASH_MATCH:
6523                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6524                                 break;
6525                         default:
6526                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6527                                 ret = I40E_ERR_PARAM;
6528                                 goto DONE;
6529                         }
6530                         req_list[i].flags = rte_cpu_to_le_16(flags);
6531                 }
6532
6533                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6534                                                 actual_num, NULL);
6535                 if (ret != I40E_SUCCESS) {
6536                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6537                         goto DONE;
6538                 }
6539                 num += actual_num;
6540         } while (num < total);
6541
6542 DONE:
6543         rte_free(req_list);
6544         return ret;
6545 }
6546
6547 /* Find out specific MAC filter */
6548 static struct i40e_mac_filter *
6549 i40e_find_mac_filter(struct i40e_vsi *vsi,
6550                          struct ether_addr *macaddr)
6551 {
6552         struct i40e_mac_filter *f;
6553
6554         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6555                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6556                         return f;
6557         }
6558
6559         return NULL;
6560 }
6561
6562 static bool
6563 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6564                          uint16_t vlan_id)
6565 {
6566         uint32_t vid_idx, vid_bit;
6567
6568         if (vlan_id > ETH_VLAN_ID_MAX)
6569                 return 0;
6570
6571         vid_idx = I40E_VFTA_IDX(vlan_id);
6572         vid_bit = I40E_VFTA_BIT(vlan_id);
6573
6574         if (vsi->vfta[vid_idx] & vid_bit)
6575                 return 1;
6576         else
6577                 return 0;
6578 }
6579
6580 static void
6581 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6582                        uint16_t vlan_id, bool on)
6583 {
6584         uint32_t vid_idx, vid_bit;
6585
6586         vid_idx = I40E_VFTA_IDX(vlan_id);
6587         vid_bit = I40E_VFTA_BIT(vlan_id);
6588
6589         if (on)
6590                 vsi->vfta[vid_idx] |= vid_bit;
6591         else
6592                 vsi->vfta[vid_idx] &= ~vid_bit;
6593 }
6594
6595 void
6596 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6597                      uint16_t vlan_id, bool on)
6598 {
6599         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6600         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6601         int ret;
6602
6603         if (vlan_id > ETH_VLAN_ID_MAX)
6604                 return;
6605
6606         i40e_store_vlan_filter(vsi, vlan_id, on);
6607
6608         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6609                 return;
6610
6611         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6612
6613         if (on) {
6614                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6615                                        &vlan_data, 1, NULL);
6616                 if (ret != I40E_SUCCESS)
6617                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6618         } else {
6619                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6620                                           &vlan_data, 1, NULL);
6621                 if (ret != I40E_SUCCESS)
6622                         PMD_DRV_LOG(ERR,
6623                                     "Failed to remove vlan filter");
6624         }
6625 }
6626
6627 /**
6628  * Find all vlan options for specific mac addr,
6629  * return with actual vlan found.
6630  */
6631 int
6632 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6633                            struct i40e_macvlan_filter *mv_f,
6634                            int num, struct ether_addr *addr)
6635 {
6636         int i;
6637         uint32_t j, k;
6638
6639         /**
6640          * Not to use i40e_find_vlan_filter to decrease the loop time,
6641          * although the code looks complex.
6642           */
6643         if (num < vsi->vlan_num)
6644                 return I40E_ERR_PARAM;
6645
6646         i = 0;
6647         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6648                 if (vsi->vfta[j]) {
6649                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6650                                 if (vsi->vfta[j] & (1 << k)) {
6651                                         if (i > num - 1) {
6652                                                 PMD_DRV_LOG(ERR,
6653                                                         "vlan number doesn't match");
6654                                                 return I40E_ERR_PARAM;
6655                                         }
6656                                         rte_memcpy(&mv_f[i].macaddr,
6657                                                         addr, ETH_ADDR_LEN);
6658                                         mv_f[i].vlan_id =
6659                                                 j * I40E_UINT32_BIT_SIZE + k;
6660                                         i++;
6661                                 }
6662                         }
6663                 }
6664         }
6665         return I40E_SUCCESS;
6666 }
6667
6668 static inline int
6669 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6670                            struct i40e_macvlan_filter *mv_f,
6671                            int num,
6672                            uint16_t vlan)
6673 {
6674         int i = 0;
6675         struct i40e_mac_filter *f;
6676
6677         if (num < vsi->mac_num)
6678                 return I40E_ERR_PARAM;
6679
6680         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6681                 if (i > num - 1) {
6682                         PMD_DRV_LOG(ERR, "buffer number not match");
6683                         return I40E_ERR_PARAM;
6684                 }
6685                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6686                                 ETH_ADDR_LEN);
6687                 mv_f[i].vlan_id = vlan;
6688                 mv_f[i].filter_type = f->mac_info.filter_type;
6689                 i++;
6690         }
6691
6692         return I40E_SUCCESS;
6693 }
6694
6695 static int
6696 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6697 {
6698         int i, j, num;
6699         struct i40e_mac_filter *f;
6700         struct i40e_macvlan_filter *mv_f;
6701         int ret = I40E_SUCCESS;
6702
6703         if (vsi == NULL || vsi->mac_num == 0)
6704                 return I40E_ERR_PARAM;
6705
6706         /* Case that no vlan is set */
6707         if (vsi->vlan_num == 0)
6708                 num = vsi->mac_num;
6709         else
6710                 num = vsi->mac_num * vsi->vlan_num;
6711
6712         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6713         if (mv_f == NULL) {
6714                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6715                 return I40E_ERR_NO_MEMORY;
6716         }
6717
6718         i = 0;
6719         if (vsi->vlan_num == 0) {
6720                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6721                         rte_memcpy(&mv_f[i].macaddr,
6722                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6723                         mv_f[i].filter_type = f->mac_info.filter_type;
6724                         mv_f[i].vlan_id = 0;
6725                         i++;
6726                 }
6727         } else {
6728                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6729                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6730                                         vsi->vlan_num, &f->mac_info.mac_addr);
6731                         if (ret != I40E_SUCCESS)
6732                                 goto DONE;
6733                         for (j = i; j < i + vsi->vlan_num; j++)
6734                                 mv_f[j].filter_type = f->mac_info.filter_type;
6735                         i += vsi->vlan_num;
6736                 }
6737         }
6738
6739         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6740 DONE:
6741         rte_free(mv_f);
6742
6743         return ret;
6744 }
6745
6746 int
6747 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6748 {
6749         struct i40e_macvlan_filter *mv_f;
6750         int mac_num;
6751         int ret = I40E_SUCCESS;
6752
6753         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6754                 return I40E_ERR_PARAM;
6755
6756         /* If it's already set, just return */
6757         if (i40e_find_vlan_filter(vsi,vlan))
6758                 return I40E_SUCCESS;
6759
6760         mac_num = vsi->mac_num;
6761
6762         if (mac_num == 0) {
6763                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6764                 return I40E_ERR_PARAM;
6765         }
6766
6767         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6768
6769         if (mv_f == NULL) {
6770                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6771                 return I40E_ERR_NO_MEMORY;
6772         }
6773
6774         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6775
6776         if (ret != I40E_SUCCESS)
6777                 goto DONE;
6778
6779         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6780
6781         if (ret != I40E_SUCCESS)
6782                 goto DONE;
6783
6784         i40e_set_vlan_filter(vsi, vlan, 1);
6785
6786         vsi->vlan_num++;
6787         ret = I40E_SUCCESS;
6788 DONE:
6789         rte_free(mv_f);
6790         return ret;
6791 }
6792
6793 int
6794 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6795 {
6796         struct i40e_macvlan_filter *mv_f;
6797         int mac_num;
6798         int ret = I40E_SUCCESS;
6799
6800         /**
6801          * Vlan 0 is the generic filter for untagged packets
6802          * and can't be removed.
6803          */
6804         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6805                 return I40E_ERR_PARAM;
6806
6807         /* If can't find it, just return */
6808         if (!i40e_find_vlan_filter(vsi, vlan))
6809                 return I40E_ERR_PARAM;
6810
6811         mac_num = vsi->mac_num;
6812
6813         if (mac_num == 0) {
6814                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6815                 return I40E_ERR_PARAM;
6816         }
6817
6818         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6819
6820         if (mv_f == NULL) {
6821                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6822                 return I40E_ERR_NO_MEMORY;
6823         }
6824
6825         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6826
6827         if (ret != I40E_SUCCESS)
6828                 goto DONE;
6829
6830         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6831
6832         if (ret != I40E_SUCCESS)
6833                 goto DONE;
6834
6835         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6836         if (vsi->vlan_num == 1) {
6837                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6838                 if (ret != I40E_SUCCESS)
6839                         goto DONE;
6840
6841                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6842                 if (ret != I40E_SUCCESS)
6843                         goto DONE;
6844         }
6845
6846         i40e_set_vlan_filter(vsi, vlan, 0);
6847
6848         vsi->vlan_num--;
6849         ret = I40E_SUCCESS;
6850 DONE:
6851         rte_free(mv_f);
6852         return ret;
6853 }
6854
6855 int
6856 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6857 {
6858         struct i40e_mac_filter *f;
6859         struct i40e_macvlan_filter *mv_f;
6860         int i, vlan_num = 0;
6861         int ret = I40E_SUCCESS;
6862
6863         /* If it's add and we've config it, return */
6864         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6865         if (f != NULL)
6866                 return I40E_SUCCESS;
6867         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6868                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6869
6870                 /**
6871                  * If vlan_num is 0, that's the first time to add mac,
6872                  * set mask for vlan_id 0.
6873                  */
6874                 if (vsi->vlan_num == 0) {
6875                         i40e_set_vlan_filter(vsi, 0, 1);
6876                         vsi->vlan_num = 1;
6877                 }
6878                 vlan_num = vsi->vlan_num;
6879         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6880                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6881                 vlan_num = 1;
6882
6883         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6884         if (mv_f == NULL) {
6885                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6886                 return I40E_ERR_NO_MEMORY;
6887         }
6888
6889         for (i = 0; i < vlan_num; i++) {
6890                 mv_f[i].filter_type = mac_filter->filter_type;
6891                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6892                                 ETH_ADDR_LEN);
6893         }
6894
6895         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6896                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6897                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6898                                         &mac_filter->mac_addr);
6899                 if (ret != I40E_SUCCESS)
6900                         goto DONE;
6901         }
6902
6903         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6904         if (ret != I40E_SUCCESS)
6905                 goto DONE;
6906
6907         /* Add the mac addr into mac list */
6908         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6909         if (f == NULL) {
6910                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6911                 ret = I40E_ERR_NO_MEMORY;
6912                 goto DONE;
6913         }
6914         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6915                         ETH_ADDR_LEN);
6916         f->mac_info.filter_type = mac_filter->filter_type;
6917         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6918         vsi->mac_num++;
6919
6920         ret = I40E_SUCCESS;
6921 DONE:
6922         rte_free(mv_f);
6923
6924         return ret;
6925 }
6926
6927 int
6928 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6929 {
6930         struct i40e_mac_filter *f;
6931         struct i40e_macvlan_filter *mv_f;
6932         int i, vlan_num;
6933         enum rte_mac_filter_type filter_type;
6934         int ret = I40E_SUCCESS;
6935
6936         /* Can't find it, return an error */
6937         f = i40e_find_mac_filter(vsi, addr);
6938         if (f == NULL)
6939                 return I40E_ERR_PARAM;
6940
6941         vlan_num = vsi->vlan_num;
6942         filter_type = f->mac_info.filter_type;
6943         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6944                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6945                 if (vlan_num == 0) {
6946                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6947                         return I40E_ERR_PARAM;
6948                 }
6949         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6950                         filter_type == RTE_MAC_HASH_MATCH)
6951                 vlan_num = 1;
6952
6953         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6954         if (mv_f == NULL) {
6955                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6956                 return I40E_ERR_NO_MEMORY;
6957         }
6958
6959         for (i = 0; i < vlan_num; i++) {
6960                 mv_f[i].filter_type = filter_type;
6961                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6962                                 ETH_ADDR_LEN);
6963         }
6964         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6965                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6966                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6967                 if (ret != I40E_SUCCESS)
6968                         goto DONE;
6969         }
6970
6971         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6972         if (ret != I40E_SUCCESS)
6973                 goto DONE;
6974
6975         /* Remove the mac addr into mac list */
6976         TAILQ_REMOVE(&vsi->mac_list, f, next);
6977         rte_free(f);
6978         vsi->mac_num--;
6979
6980         ret = I40E_SUCCESS;
6981 DONE:
6982         rte_free(mv_f);
6983         return ret;
6984 }
6985
6986 /* Configure hash enable flags for RSS */
6987 uint64_t
6988 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6989 {
6990         uint64_t hena = 0;
6991         int i;
6992
6993         if (!flags)
6994                 return hena;
6995
6996         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6997                 if (flags & (1ULL << i))
6998                         hena |= adapter->pctypes_tbl[i];
6999         }
7000
7001         return hena;
7002 }
7003
7004 /* Parse the hash enable flags */
7005 uint64_t
7006 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7007 {
7008         uint64_t rss_hf = 0;
7009
7010         if (!flags)
7011                 return rss_hf;
7012         int i;
7013
7014         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7015                 if (flags & adapter->pctypes_tbl[i])
7016                         rss_hf |= (1ULL << i);
7017         }
7018         return rss_hf;
7019 }
7020
7021 /* Disable RSS */
7022 static void
7023 i40e_pf_disable_rss(struct i40e_pf *pf)
7024 {
7025         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7026
7027         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7028         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7029         I40E_WRITE_FLUSH(hw);
7030 }
7031
7032 int
7033 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7034 {
7035         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7036         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7037         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7038                            I40E_VFQF_HKEY_MAX_INDEX :
7039                            I40E_PFQF_HKEY_MAX_INDEX;
7040         int ret = 0;
7041
7042         if (!key || key_len == 0) {
7043                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7044                 return 0;
7045         } else if (key_len != (key_idx + 1) *
7046                 sizeof(uint32_t)) {
7047                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7048                 return -EINVAL;
7049         }
7050
7051         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7052                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7053                         (struct i40e_aqc_get_set_rss_key_data *)key;
7054
7055                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7056                 if (ret)
7057                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7058         } else {
7059                 uint32_t *hash_key = (uint32_t *)key;
7060                 uint16_t i;
7061
7062                 if (vsi->type == I40E_VSI_SRIOV) {
7063                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7064                                 I40E_WRITE_REG(
7065                                         hw,
7066                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7067                                         hash_key[i]);
7068
7069                 } else {
7070                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7071                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7072                                                hash_key[i]);
7073                 }
7074                 I40E_WRITE_FLUSH(hw);
7075         }
7076
7077         return ret;
7078 }
7079
7080 static int
7081 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7082 {
7083         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7084         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7085         uint32_t reg;
7086         int ret;
7087
7088         if (!key || !key_len)
7089                 return -EINVAL;
7090
7091         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7092                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7093                         (struct i40e_aqc_get_set_rss_key_data *)key);
7094                 if (ret) {
7095                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7096                         return ret;
7097                 }
7098         } else {
7099                 uint32_t *key_dw = (uint32_t *)key;
7100                 uint16_t i;
7101
7102                 if (vsi->type == I40E_VSI_SRIOV) {
7103                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7104                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7105                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7106                         }
7107                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7108                                    sizeof(uint32_t);
7109                 } else {
7110                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7111                                 reg = I40E_PFQF_HKEY(i);
7112                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7113                         }
7114                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7115                                    sizeof(uint32_t);
7116                 }
7117         }
7118         return 0;
7119 }
7120
7121 static int
7122 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7123 {
7124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7125         uint64_t hena;
7126         int ret;
7127
7128         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7129                                rss_conf->rss_key_len);
7130         if (ret)
7131                 return ret;
7132
7133         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7134         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7135         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7136         I40E_WRITE_FLUSH(hw);
7137
7138         return 0;
7139 }
7140
7141 static int
7142 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7143                          struct rte_eth_rss_conf *rss_conf)
7144 {
7145         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7146         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7147         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7148         uint64_t hena;
7149
7150         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7151         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7152
7153         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7154                 if (rss_hf != 0) /* Enable RSS */
7155                         return -EINVAL;
7156                 return 0; /* Nothing to do */
7157         }
7158         /* RSS enabled */
7159         if (rss_hf == 0) /* Disable RSS */
7160                 return -EINVAL;
7161
7162         return i40e_hw_rss_hash_set(pf, rss_conf);
7163 }
7164
7165 static int
7166 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7167                            struct rte_eth_rss_conf *rss_conf)
7168 {
7169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7171         uint64_t hena;
7172
7173         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7174                          &rss_conf->rss_key_len);
7175
7176         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7177         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7178         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7179
7180         return 0;
7181 }
7182
7183 static int
7184 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7185 {
7186         switch (filter_type) {
7187         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7188                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7189                 break;
7190         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7191                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7192                 break;
7193         case RTE_TUNNEL_FILTER_IMAC_TENID:
7194                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7195                 break;
7196         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7197                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7198                 break;
7199         case ETH_TUNNEL_FILTER_IMAC:
7200                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7201                 break;
7202         case ETH_TUNNEL_FILTER_OIP:
7203                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7204                 break;
7205         case ETH_TUNNEL_FILTER_IIP:
7206                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7207                 break;
7208         default:
7209                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7210                 return -EINVAL;
7211         }
7212
7213         return 0;
7214 }
7215
7216 /* Convert tunnel filter structure */
7217 static int
7218 i40e_tunnel_filter_convert(
7219         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7220         struct i40e_tunnel_filter *tunnel_filter)
7221 {
7222         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7223                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7224         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7225                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7226         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7227         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7228              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7229             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7230                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7231         else
7232                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7233         tunnel_filter->input.flags = cld_filter->element.flags;
7234         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7235         tunnel_filter->queue = cld_filter->element.queue_number;
7236         rte_memcpy(tunnel_filter->input.general_fields,
7237                    cld_filter->general_fields,
7238                    sizeof(cld_filter->general_fields));
7239
7240         return 0;
7241 }
7242
7243 /* Check if there exists the tunnel filter */
7244 struct i40e_tunnel_filter *
7245 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7246                              const struct i40e_tunnel_filter_input *input)
7247 {
7248         int ret;
7249
7250         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7251         if (ret < 0)
7252                 return NULL;
7253
7254         return tunnel_rule->hash_map[ret];
7255 }
7256
7257 /* Add a tunnel filter into the SW list */
7258 static int
7259 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7260                              struct i40e_tunnel_filter *tunnel_filter)
7261 {
7262         struct i40e_tunnel_rule *rule = &pf->tunnel;
7263         int ret;
7264
7265         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7266         if (ret < 0) {
7267                 PMD_DRV_LOG(ERR,
7268                             "Failed to insert tunnel filter to hash table %d!",
7269                             ret);
7270                 return ret;
7271         }
7272         rule->hash_map[ret] = tunnel_filter;
7273
7274         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7275
7276         return 0;
7277 }
7278
7279 /* Delete a tunnel filter from the SW list */
7280 int
7281 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7282                           struct i40e_tunnel_filter_input *input)
7283 {
7284         struct i40e_tunnel_rule *rule = &pf->tunnel;
7285         struct i40e_tunnel_filter *tunnel_filter;
7286         int ret;
7287
7288         ret = rte_hash_del_key(rule->hash_table, input);
7289         if (ret < 0) {
7290                 PMD_DRV_LOG(ERR,
7291                             "Failed to delete tunnel filter to hash table %d!",
7292                             ret);
7293                 return ret;
7294         }
7295         tunnel_filter = rule->hash_map[ret];
7296         rule->hash_map[ret] = NULL;
7297
7298         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7299         rte_free(tunnel_filter);
7300
7301         return 0;
7302 }
7303
7304 int
7305 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7306                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7307                         uint8_t add)
7308 {
7309         uint16_t ip_type;
7310         uint32_t ipv4_addr, ipv4_addr_le;
7311         uint8_t i, tun_type = 0;
7312         /* internal varialbe to convert ipv6 byte order */
7313         uint32_t convert_ipv6[4];
7314         int val, ret = 0;
7315         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7316         struct i40e_vsi *vsi = pf->main_vsi;
7317         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7318         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7319         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7320         struct i40e_tunnel_filter *tunnel, *node;
7321         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7322
7323         cld_filter = rte_zmalloc("tunnel_filter",
7324                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7325         0);
7326
7327         if (NULL == cld_filter) {
7328                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7329                 return -ENOMEM;
7330         }
7331         pfilter = cld_filter;
7332
7333         ether_addr_copy(&tunnel_filter->outer_mac,
7334                         (struct ether_addr *)&pfilter->element.outer_mac);
7335         ether_addr_copy(&tunnel_filter->inner_mac,
7336                         (struct ether_addr *)&pfilter->element.inner_mac);
7337
7338         pfilter->element.inner_vlan =
7339                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7340         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7341                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7342                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7343                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7344                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7345                                 &ipv4_addr_le,
7346                                 sizeof(pfilter->element.ipaddr.v4.data));
7347         } else {
7348                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7349                 for (i = 0; i < 4; i++) {
7350                         convert_ipv6[i] =
7351                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7352                 }
7353                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7354                            &convert_ipv6,
7355                            sizeof(pfilter->element.ipaddr.v6.data));
7356         }
7357
7358         /* check tunneled type */
7359         switch (tunnel_filter->tunnel_type) {
7360         case RTE_TUNNEL_TYPE_VXLAN:
7361                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7362                 break;
7363         case RTE_TUNNEL_TYPE_NVGRE:
7364                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7365                 break;
7366         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7367                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7368                 break;
7369         default:
7370                 /* Other tunnel types is not supported. */
7371                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7372                 rte_free(cld_filter);
7373                 return -EINVAL;
7374         }
7375
7376         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7377                                        &pfilter->element.flags);
7378         if (val < 0) {
7379                 rte_free(cld_filter);
7380                 return -EINVAL;
7381         }
7382
7383         pfilter->element.flags |= rte_cpu_to_le_16(
7384                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7385                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7386         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7387         pfilter->element.queue_number =
7388                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7389
7390         /* Check if there is the filter in SW list */
7391         memset(&check_filter, 0, sizeof(check_filter));
7392         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7393         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7394         if (add && node) {
7395                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7396                 rte_free(cld_filter);
7397                 return -EINVAL;
7398         }
7399
7400         if (!add && !node) {
7401                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7402                 rte_free(cld_filter);
7403                 return -EINVAL;
7404         }
7405
7406         if (add) {
7407                 ret = i40e_aq_add_cloud_filters(hw,
7408                                         vsi->seid, &cld_filter->element, 1);
7409                 if (ret < 0) {
7410                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7411                         rte_free(cld_filter);
7412                         return -ENOTSUP;
7413                 }
7414                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7415                 if (tunnel == NULL) {
7416                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7417                         rte_free(cld_filter);
7418                         return -ENOMEM;
7419                 }
7420
7421                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7422                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7423                 if (ret < 0)
7424                         rte_free(tunnel);
7425         } else {
7426                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7427                                                    &cld_filter->element, 1);
7428                 if (ret < 0) {
7429                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7430                         rte_free(cld_filter);
7431                         return -ENOTSUP;
7432                 }
7433                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7434         }
7435
7436         rte_free(cld_filter);
7437         return ret;
7438 }
7439
7440 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7441 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7442 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7443 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7444 #define I40E_TR_GRE_KEY_MASK                    0x400
7445 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7446 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7447
7448 static enum
7449 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7450 {
7451         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7452         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7453         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7454         enum i40e_status_code status = I40E_SUCCESS;
7455
7456         if (pf->support_multi_driver) {
7457                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7458                 return I40E_NOT_SUPPORTED;
7459         }
7460
7461         memset(&filter_replace, 0,
7462                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7463         memset(&filter_replace_buf, 0,
7464                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7465
7466         /* create L1 filter */
7467         filter_replace.old_filter_type =
7468                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7469         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7470         filter_replace.tr_bit = 0;
7471
7472         /* Prepare the buffer, 3 entries */
7473         filter_replace_buf.data[0] =
7474                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7475         filter_replace_buf.data[0] |=
7476                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7477         filter_replace_buf.data[2] = 0xFF;
7478         filter_replace_buf.data[3] = 0xFF;
7479         filter_replace_buf.data[4] =
7480                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7481         filter_replace_buf.data[4] |=
7482                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7483         filter_replace_buf.data[7] = 0xF0;
7484         filter_replace_buf.data[8]
7485                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7486         filter_replace_buf.data[8] |=
7487                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7488         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7489                 I40E_TR_GENEVE_KEY_MASK |
7490                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7491         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7492                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7493                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7494
7495         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7496                                                &filter_replace_buf);
7497         if (!status) {
7498                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7499                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7500                             "cloud l1 type is changed from 0x%x to 0x%x",
7501                             filter_replace.old_filter_type,
7502                             filter_replace.new_filter_type);
7503         }
7504         return status;
7505 }
7506
7507 static enum
7508 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7509 {
7510         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7511         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7512         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7513         enum i40e_status_code status = I40E_SUCCESS;
7514
7515         if (pf->support_multi_driver) {
7516                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7517                 return I40E_NOT_SUPPORTED;
7518         }
7519
7520         /* For MPLSoUDP */
7521         memset(&filter_replace, 0,
7522                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7523         memset(&filter_replace_buf, 0,
7524                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7525         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7526                 I40E_AQC_MIRROR_CLOUD_FILTER;
7527         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7528         filter_replace.new_filter_type =
7529                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7530         /* Prepare the buffer, 2 entries */
7531         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7532         filter_replace_buf.data[0] |=
7533                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7534         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7535         filter_replace_buf.data[4] |=
7536                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7537         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7538                                                &filter_replace_buf);
7539         if (status < 0)
7540                 return status;
7541         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7542                     "cloud filter type is changed from 0x%x to 0x%x",
7543                     filter_replace.old_filter_type,
7544                     filter_replace.new_filter_type);
7545
7546         /* For MPLSoGRE */
7547         memset(&filter_replace, 0,
7548                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7549         memset(&filter_replace_buf, 0,
7550                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7551
7552         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7553                 I40E_AQC_MIRROR_CLOUD_FILTER;
7554         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7555         filter_replace.new_filter_type =
7556                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7557         /* Prepare the buffer, 2 entries */
7558         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7559         filter_replace_buf.data[0] |=
7560                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7561         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7562         filter_replace_buf.data[4] |=
7563                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7564
7565         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7566                                                &filter_replace_buf);
7567         if (!status) {
7568                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7569                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7570                             "cloud filter type is changed from 0x%x to 0x%x",
7571                             filter_replace.old_filter_type,
7572                             filter_replace.new_filter_type);
7573         }
7574         return status;
7575 }
7576
7577 static enum i40e_status_code
7578 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7579 {
7580         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7581         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7582         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7583         enum i40e_status_code status = I40E_SUCCESS;
7584
7585         if (pf->support_multi_driver) {
7586                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7587                 return I40E_NOT_SUPPORTED;
7588         }
7589
7590         /* For GTP-C */
7591         memset(&filter_replace, 0,
7592                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7593         memset(&filter_replace_buf, 0,
7594                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7595         /* create L1 filter */
7596         filter_replace.old_filter_type =
7597                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7598         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7599         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7600                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7601         /* Prepare the buffer, 2 entries */
7602         filter_replace_buf.data[0] =
7603                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7604         filter_replace_buf.data[0] |=
7605                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7606         filter_replace_buf.data[2] = 0xFF;
7607         filter_replace_buf.data[3] = 0xFF;
7608         filter_replace_buf.data[4] =
7609                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7610         filter_replace_buf.data[4] |=
7611                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7612         filter_replace_buf.data[6] = 0xFF;
7613         filter_replace_buf.data[7] = 0xFF;
7614         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7615                                                &filter_replace_buf);
7616         if (status < 0)
7617                 return status;
7618         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7619                     "cloud l1 type is changed from 0x%x to 0x%x",
7620                     filter_replace.old_filter_type,
7621                     filter_replace.new_filter_type);
7622
7623         /* for GTP-U */
7624         memset(&filter_replace, 0,
7625                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7626         memset(&filter_replace_buf, 0,
7627                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7628         /* create L1 filter */
7629         filter_replace.old_filter_type =
7630                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7631         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7632         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7633                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7634         /* Prepare the buffer, 2 entries */
7635         filter_replace_buf.data[0] =
7636                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7637         filter_replace_buf.data[0] |=
7638                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7639         filter_replace_buf.data[2] = 0xFF;
7640         filter_replace_buf.data[3] = 0xFF;
7641         filter_replace_buf.data[4] =
7642                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7643         filter_replace_buf.data[4] |=
7644                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7645         filter_replace_buf.data[6] = 0xFF;
7646         filter_replace_buf.data[7] = 0xFF;
7647
7648         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7649                                                &filter_replace_buf);
7650         if (!status) {
7651                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7652                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7653                             "cloud l1 type is changed from 0x%x to 0x%x",
7654                             filter_replace.old_filter_type,
7655                             filter_replace.new_filter_type);
7656         }
7657         return status;
7658 }
7659
7660 static enum
7661 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7662 {
7663         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7664         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7665         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7666         enum i40e_status_code status = I40E_SUCCESS;
7667
7668         if (pf->support_multi_driver) {
7669                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7670                 return I40E_NOT_SUPPORTED;
7671         }
7672
7673         /* for GTP-C */
7674         memset(&filter_replace, 0,
7675                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7676         memset(&filter_replace_buf, 0,
7677                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7678         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7679         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7680         filter_replace.new_filter_type =
7681                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7682         /* Prepare the buffer, 2 entries */
7683         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7684         filter_replace_buf.data[0] |=
7685                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7686         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7687         filter_replace_buf.data[4] |=
7688                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7689         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7690                                                &filter_replace_buf);
7691         if (status < 0)
7692                 return status;
7693         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7694                     "cloud filter type is changed from 0x%x to 0x%x",
7695                     filter_replace.old_filter_type,
7696                     filter_replace.new_filter_type);
7697
7698         /* for GTP-U */
7699         memset(&filter_replace, 0,
7700                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7701         memset(&filter_replace_buf, 0,
7702                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7703         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7704         filter_replace.old_filter_type =
7705                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7706         filter_replace.new_filter_type =
7707                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7708         /* Prepare the buffer, 2 entries */
7709         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7710         filter_replace_buf.data[0] |=
7711                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7712         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7713         filter_replace_buf.data[4] |=
7714                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7715
7716         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7717                                                &filter_replace_buf);
7718         if (!status) {
7719                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7720                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7721                             "cloud filter type is changed from 0x%x to 0x%x",
7722                             filter_replace.old_filter_type,
7723                             filter_replace.new_filter_type);
7724         }
7725         return status;
7726 }
7727
7728 int
7729 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7730                       struct i40e_tunnel_filter_conf *tunnel_filter,
7731                       uint8_t add)
7732 {
7733         uint16_t ip_type;
7734         uint32_t ipv4_addr, ipv4_addr_le;
7735         uint8_t i, tun_type = 0;
7736         /* internal variable to convert ipv6 byte order */
7737         uint32_t convert_ipv6[4];
7738         int val, ret = 0;
7739         struct i40e_pf_vf *vf = NULL;
7740         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7741         struct i40e_vsi *vsi;
7742         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7743         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7744         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7745         struct i40e_tunnel_filter *tunnel, *node;
7746         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7747         uint32_t teid_le;
7748         bool big_buffer = 0;
7749
7750         cld_filter = rte_zmalloc("tunnel_filter",
7751                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7752                          0);
7753
7754         if (cld_filter == NULL) {
7755                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7756                 return -ENOMEM;
7757         }
7758         pfilter = cld_filter;
7759
7760         ether_addr_copy(&tunnel_filter->outer_mac,
7761                         (struct ether_addr *)&pfilter->element.outer_mac);
7762         ether_addr_copy(&tunnel_filter->inner_mac,
7763                         (struct ether_addr *)&pfilter->element.inner_mac);
7764
7765         pfilter->element.inner_vlan =
7766                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7767         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7768                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7769                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7770                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7771                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7772                                 &ipv4_addr_le,
7773                                 sizeof(pfilter->element.ipaddr.v4.data));
7774         } else {
7775                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7776                 for (i = 0; i < 4; i++) {
7777                         convert_ipv6[i] =
7778                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7779                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7780                 }
7781                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7782                            &convert_ipv6,
7783                            sizeof(pfilter->element.ipaddr.v6.data));
7784         }
7785
7786         /* check tunneled type */
7787         switch (tunnel_filter->tunnel_type) {
7788         case I40E_TUNNEL_TYPE_VXLAN:
7789                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7790                 break;
7791         case I40E_TUNNEL_TYPE_NVGRE:
7792                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7793                 break;
7794         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7795                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7796                 break;
7797         case I40E_TUNNEL_TYPE_MPLSoUDP:
7798                 if (!pf->mpls_replace_flag) {
7799                         i40e_replace_mpls_l1_filter(pf);
7800                         i40e_replace_mpls_cloud_filter(pf);
7801                         pf->mpls_replace_flag = 1;
7802                 }
7803                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7804                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7805                         teid_le >> 4;
7806                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7807                         (teid_le & 0xF) << 12;
7808                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7809                         0x40;
7810                 big_buffer = 1;
7811                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7812                 break;
7813         case I40E_TUNNEL_TYPE_MPLSoGRE:
7814                 if (!pf->mpls_replace_flag) {
7815                         i40e_replace_mpls_l1_filter(pf);
7816                         i40e_replace_mpls_cloud_filter(pf);
7817                         pf->mpls_replace_flag = 1;
7818                 }
7819                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7820                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7821                         teid_le >> 4;
7822                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7823                         (teid_le & 0xF) << 12;
7824                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7825                         0x0;
7826                 big_buffer = 1;
7827                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7828                 break;
7829         case I40E_TUNNEL_TYPE_GTPC:
7830                 if (!pf->gtp_replace_flag) {
7831                         i40e_replace_gtp_l1_filter(pf);
7832                         i40e_replace_gtp_cloud_filter(pf);
7833                         pf->gtp_replace_flag = 1;
7834                 }
7835                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7836                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7837                         (teid_le >> 16) & 0xFFFF;
7838                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7839                         teid_le & 0xFFFF;
7840                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7841                         0x0;
7842                 big_buffer = 1;
7843                 break;
7844         case I40E_TUNNEL_TYPE_GTPU:
7845                 if (!pf->gtp_replace_flag) {
7846                         i40e_replace_gtp_l1_filter(pf);
7847                         i40e_replace_gtp_cloud_filter(pf);
7848                         pf->gtp_replace_flag = 1;
7849                 }
7850                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7851                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7852                         (teid_le >> 16) & 0xFFFF;
7853                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7854                         teid_le & 0xFFFF;
7855                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7856                         0x0;
7857                 big_buffer = 1;
7858                 break;
7859         case I40E_TUNNEL_TYPE_QINQ:
7860                 if (!pf->qinq_replace_flag) {
7861                         ret = i40e_cloud_filter_qinq_create(pf);
7862                         if (ret < 0)
7863                                 PMD_DRV_LOG(DEBUG,
7864                                             "QinQ tunnel filter already created.");
7865                         pf->qinq_replace_flag = 1;
7866                 }
7867                 /*      Add in the General fields the values of
7868                  *      the Outer and Inner VLAN
7869                  *      Big Buffer should be set, see changes in
7870                  *      i40e_aq_add_cloud_filters
7871                  */
7872                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7873                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7874                 big_buffer = 1;
7875                 break;
7876         default:
7877                 /* Other tunnel types is not supported. */
7878                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7879                 rte_free(cld_filter);
7880                 return -EINVAL;
7881         }
7882
7883         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7884                 pfilter->element.flags =
7885                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7886         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7887                 pfilter->element.flags =
7888                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7889         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7890                 pfilter->element.flags =
7891                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7892         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7893                 pfilter->element.flags =
7894                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7895         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7896                 pfilter->element.flags |=
7897                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7898         else {
7899                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7900                                                 &pfilter->element.flags);
7901                 if (val < 0) {
7902                         rte_free(cld_filter);
7903                         return -EINVAL;
7904                 }
7905         }
7906
7907         pfilter->element.flags |= rte_cpu_to_le_16(
7908                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7909                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7910         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7911         pfilter->element.queue_number =
7912                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7913
7914         if (!tunnel_filter->is_to_vf)
7915                 vsi = pf->main_vsi;
7916         else {
7917                 if (tunnel_filter->vf_id >= pf->vf_num) {
7918                         PMD_DRV_LOG(ERR, "Invalid argument.");
7919                         rte_free(cld_filter);
7920                         return -EINVAL;
7921                 }
7922                 vf = &pf->vfs[tunnel_filter->vf_id];
7923                 vsi = vf->vsi;
7924         }
7925
7926         /* Check if there is the filter in SW list */
7927         memset(&check_filter, 0, sizeof(check_filter));
7928         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7929         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7930         check_filter.vf_id = tunnel_filter->vf_id;
7931         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7932         if (add && node) {
7933                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7934                 rte_free(cld_filter);
7935                 return -EINVAL;
7936         }
7937
7938         if (!add && !node) {
7939                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7940                 rte_free(cld_filter);
7941                 return -EINVAL;
7942         }
7943
7944         if (add) {
7945                 if (big_buffer)
7946                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7947                                                    vsi->seid, cld_filter, 1);
7948                 else
7949                         ret = i40e_aq_add_cloud_filters(hw,
7950                                         vsi->seid, &cld_filter->element, 1);
7951                 if (ret < 0) {
7952                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7953                         rte_free(cld_filter);
7954                         return -ENOTSUP;
7955                 }
7956                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7957                 if (tunnel == NULL) {
7958                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7959                         rte_free(cld_filter);
7960                         return -ENOMEM;
7961                 }
7962
7963                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7964                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7965                 if (ret < 0)
7966                         rte_free(tunnel);
7967         } else {
7968                 if (big_buffer)
7969                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7970                                 hw, vsi->seid, cld_filter, 1);
7971                 else
7972                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7973                                                    &cld_filter->element, 1);
7974                 if (ret < 0) {
7975                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7976                         rte_free(cld_filter);
7977                         return -ENOTSUP;
7978                 }
7979                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7980         }
7981
7982         rte_free(cld_filter);
7983         return ret;
7984 }
7985
7986 static int
7987 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7988 {
7989         uint8_t i;
7990
7991         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7992                 if (pf->vxlan_ports[i] == port)
7993                         return i;
7994         }
7995
7996         return -1;
7997 }
7998
7999 static int
8000 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8001 {
8002         int  idx, ret;
8003         uint8_t filter_idx;
8004         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8005
8006         idx = i40e_get_vxlan_port_idx(pf, port);
8007
8008         /* Check if port already exists */
8009         if (idx >= 0) {
8010                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8011                 return -EINVAL;
8012         }
8013
8014         /* Now check if there is space to add the new port */
8015         idx = i40e_get_vxlan_port_idx(pf, 0);
8016         if (idx < 0) {
8017                 PMD_DRV_LOG(ERR,
8018                         "Maximum number of UDP ports reached, not adding port %d",
8019                         port);
8020                 return -ENOSPC;
8021         }
8022
8023         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8024                                         &filter_idx, NULL);
8025         if (ret < 0) {
8026                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8027                 return -1;
8028         }
8029
8030         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8031                          port,  filter_idx);
8032
8033         /* New port: add it and mark its index in the bitmap */
8034         pf->vxlan_ports[idx] = port;
8035         pf->vxlan_bitmap |= (1 << idx);
8036
8037         if (!(pf->flags & I40E_FLAG_VXLAN))
8038                 pf->flags |= I40E_FLAG_VXLAN;
8039
8040         return 0;
8041 }
8042
8043 static int
8044 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8045 {
8046         int idx;
8047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8048
8049         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8050                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8051                 return -EINVAL;
8052         }
8053
8054         idx = i40e_get_vxlan_port_idx(pf, port);
8055
8056         if (idx < 0) {
8057                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8058                 return -EINVAL;
8059         }
8060
8061         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8062                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8063                 return -1;
8064         }
8065
8066         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8067                         port, idx);
8068
8069         pf->vxlan_ports[idx] = 0;
8070         pf->vxlan_bitmap &= ~(1 << idx);
8071
8072         if (!pf->vxlan_bitmap)
8073                 pf->flags &= ~I40E_FLAG_VXLAN;
8074
8075         return 0;
8076 }
8077
8078 /* Add UDP tunneling port */
8079 static int
8080 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8081                              struct rte_eth_udp_tunnel *udp_tunnel)
8082 {
8083         int ret = 0;
8084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8085
8086         if (udp_tunnel == NULL)
8087                 return -EINVAL;
8088
8089         switch (udp_tunnel->prot_type) {
8090         case RTE_TUNNEL_TYPE_VXLAN:
8091                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8092                 break;
8093
8094         case RTE_TUNNEL_TYPE_GENEVE:
8095         case RTE_TUNNEL_TYPE_TEREDO:
8096                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8097                 ret = -1;
8098                 break;
8099
8100         default:
8101                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8102                 ret = -1;
8103                 break;
8104         }
8105
8106         return ret;
8107 }
8108
8109 /* Remove UDP tunneling port */
8110 static int
8111 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8112                              struct rte_eth_udp_tunnel *udp_tunnel)
8113 {
8114         int ret = 0;
8115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8116
8117         if (udp_tunnel == NULL)
8118                 return -EINVAL;
8119
8120         switch (udp_tunnel->prot_type) {
8121         case RTE_TUNNEL_TYPE_VXLAN:
8122                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8123                 break;
8124         case RTE_TUNNEL_TYPE_GENEVE:
8125         case RTE_TUNNEL_TYPE_TEREDO:
8126                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8127                 ret = -1;
8128                 break;
8129         default:
8130                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8131                 ret = -1;
8132                 break;
8133         }
8134
8135         return ret;
8136 }
8137
8138 /* Calculate the maximum number of contiguous PF queues that are configured */
8139 static int
8140 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8141 {
8142         struct rte_eth_dev_data *data = pf->dev_data;
8143         int i, num;
8144         struct i40e_rx_queue *rxq;
8145
8146         num = 0;
8147         for (i = 0; i < pf->lan_nb_qps; i++) {
8148                 rxq = data->rx_queues[i];
8149                 if (rxq && rxq->q_set)
8150                         num++;
8151                 else
8152                         break;
8153         }
8154
8155         return num;
8156 }
8157
8158 /* Configure RSS */
8159 static int
8160 i40e_pf_config_rss(struct i40e_pf *pf)
8161 {
8162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8163         struct rte_eth_rss_conf rss_conf;
8164         uint32_t i, lut = 0;
8165         uint16_t j, num;
8166
8167         /*
8168          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8169          * It's necessary to calculate the actual PF queues that are configured.
8170          */
8171         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8172                 num = i40e_pf_calc_configured_queues_num(pf);
8173         else
8174                 num = pf->dev_data->nb_rx_queues;
8175
8176         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8177         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8178                         num);
8179
8180         if (num == 0) {
8181                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8182                 return -ENOTSUP;
8183         }
8184
8185         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8186                 if (j == num)
8187                         j = 0;
8188                 lut = (lut << 8) | (j & ((0x1 <<
8189                         hw->func_caps.rss_table_entry_width) - 1));
8190                 if ((i & 3) == 3)
8191                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8192         }
8193
8194         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8195         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8196                 i40e_pf_disable_rss(pf);
8197                 return 0;
8198         }
8199         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8200                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8201                 /* Random default keys */
8202                 static uint32_t rss_key_default[] = {0x6b793944,
8203                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8204                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8205                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8206
8207                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8208                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8209                                                         sizeof(uint32_t);
8210         }
8211
8212         return i40e_hw_rss_hash_set(pf, &rss_conf);
8213 }
8214
8215 static int
8216 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8217                                struct rte_eth_tunnel_filter_conf *filter)
8218 {
8219         if (pf == NULL || filter == NULL) {
8220                 PMD_DRV_LOG(ERR, "Invalid parameter");
8221                 return -EINVAL;
8222         }
8223
8224         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8225                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8226                 return -EINVAL;
8227         }
8228
8229         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8230                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8231                 return -EINVAL;
8232         }
8233
8234         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8235                 (is_zero_ether_addr(&filter->outer_mac))) {
8236                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8237                 return -EINVAL;
8238         }
8239
8240         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8241                 (is_zero_ether_addr(&filter->inner_mac))) {
8242                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8243                 return -EINVAL;
8244         }
8245
8246         return 0;
8247 }
8248
8249 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8250 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8251 static int
8252 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8253 {
8254         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8255         uint32_t val, reg;
8256         int ret = -EINVAL;
8257
8258         if (pf->support_multi_driver) {
8259                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8260                 return -ENOTSUP;
8261         }
8262
8263         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8264         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8265
8266         if (len == 3) {
8267                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8268         } else if (len == 4) {
8269                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8270         } else {
8271                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8272                 return ret;
8273         }
8274
8275         if (reg != val) {
8276                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8277                                                    reg, NULL);
8278                 if (ret != 0)
8279                         return ret;
8280                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8281                             "with value 0x%08x",
8282                             I40E_GL_PRS_FVBM(2), reg);
8283                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8284         } else {
8285                 ret = 0;
8286         }
8287         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8288                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8289
8290         return ret;
8291 }
8292
8293 static int
8294 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8295 {
8296         int ret = -EINVAL;
8297
8298         if (!hw || !cfg)
8299                 return -EINVAL;
8300
8301         switch (cfg->cfg_type) {
8302         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8303                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8304                 break;
8305         default:
8306                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8307                 break;
8308         }
8309
8310         return ret;
8311 }
8312
8313 static int
8314 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8315                                enum rte_filter_op filter_op,
8316                                void *arg)
8317 {
8318         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8319         int ret = I40E_ERR_PARAM;
8320
8321         switch (filter_op) {
8322         case RTE_ETH_FILTER_SET:
8323                 ret = i40e_dev_global_config_set(hw,
8324                         (struct rte_eth_global_cfg *)arg);
8325                 break;
8326         default:
8327                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8328                 break;
8329         }
8330
8331         return ret;
8332 }
8333
8334 static int
8335 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8336                           enum rte_filter_op filter_op,
8337                           void *arg)
8338 {
8339         struct rte_eth_tunnel_filter_conf *filter;
8340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8341         int ret = I40E_SUCCESS;
8342
8343         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8344
8345         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8346                 return I40E_ERR_PARAM;
8347
8348         switch (filter_op) {
8349         case RTE_ETH_FILTER_NOP:
8350                 if (!(pf->flags & I40E_FLAG_VXLAN))
8351                         ret = I40E_NOT_SUPPORTED;
8352                 break;
8353         case RTE_ETH_FILTER_ADD:
8354                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8355                 break;
8356         case RTE_ETH_FILTER_DELETE:
8357                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8358                 break;
8359         default:
8360                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8361                 ret = I40E_ERR_PARAM;
8362                 break;
8363         }
8364
8365         return ret;
8366 }
8367
8368 static int
8369 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8370 {
8371         int ret = 0;
8372         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8373
8374         /* RSS setup */
8375         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8376                 ret = i40e_pf_config_rss(pf);
8377         else
8378                 i40e_pf_disable_rss(pf);
8379
8380         return ret;
8381 }
8382
8383 /* Get the symmetric hash enable configurations per port */
8384 static void
8385 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8386 {
8387         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8388
8389         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8390 }
8391
8392 /* Set the symmetric hash enable configurations per port */
8393 static void
8394 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8395 {
8396         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8397
8398         if (enable > 0) {
8399                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8400                         PMD_DRV_LOG(INFO,
8401                                 "Symmetric hash has already been enabled");
8402                         return;
8403                 }
8404                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8405         } else {
8406                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8407                         PMD_DRV_LOG(INFO,
8408                                 "Symmetric hash has already been disabled");
8409                         return;
8410                 }
8411                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8412         }
8413         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8414         I40E_WRITE_FLUSH(hw);
8415 }
8416
8417 /*
8418  * Get global configurations of hash function type and symmetric hash enable
8419  * per flow type (pctype). Note that global configuration means it affects all
8420  * the ports on the same NIC.
8421  */
8422 static int
8423 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8424                                    struct rte_eth_hash_global_conf *g_cfg)
8425 {
8426         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8427         uint32_t reg;
8428         uint16_t i, j;
8429
8430         memset(g_cfg, 0, sizeof(*g_cfg));
8431         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8432         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8433                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8434         else
8435                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8436         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8437                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8438
8439         /*
8440          * As i40e supports less than 64 flow types, only first 64 bits need to
8441          * be checked.
8442          */
8443         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8444                 g_cfg->valid_bit_mask[i] = 0ULL;
8445                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8446         }
8447
8448         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8449
8450         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8451                 if (!adapter->pctypes_tbl[i])
8452                         continue;
8453                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8454                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8455                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8456                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8457                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8458                                         g_cfg->sym_hash_enable_mask[0] |=
8459                                                                 (1ULL << i);
8460                                 }
8461                         }
8462                 }
8463         }
8464
8465         return 0;
8466 }
8467
8468 static int
8469 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8470                               const struct rte_eth_hash_global_conf *g_cfg)
8471 {
8472         uint32_t i;
8473         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8474
8475         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8476                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8477                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8478                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8479                                                 g_cfg->hash_func);
8480                 return -EINVAL;
8481         }
8482
8483         /*
8484          * As i40e supports less than 64 flow types, only first 64 bits need to
8485          * be checked.
8486          */
8487         mask0 = g_cfg->valid_bit_mask[0];
8488         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8489                 if (i == 0) {
8490                         /* Check if any unsupported flow type configured */
8491                         if ((mask0 | i40e_mask) ^ i40e_mask)
8492                                 goto mask_err;
8493                 } else {
8494                         if (g_cfg->valid_bit_mask[i])
8495                                 goto mask_err;
8496                 }
8497         }
8498
8499         return 0;
8500
8501 mask_err:
8502         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8503
8504         return -EINVAL;
8505 }
8506
8507 /*
8508  * Set global configurations of hash function type and symmetric hash enable
8509  * per flow type (pctype). Note any modifying global configuration will affect
8510  * all the ports on the same NIC.
8511  */
8512 static int
8513 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8514                                    struct rte_eth_hash_global_conf *g_cfg)
8515 {
8516         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8517         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8518         int ret;
8519         uint16_t i, j;
8520         uint32_t reg;
8521         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8522
8523         if (pf->support_multi_driver) {
8524                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8525                 return -ENOTSUP;
8526         }
8527
8528         /* Check the input parameters */
8529         ret = i40e_hash_global_config_check(adapter, g_cfg);
8530         if (ret < 0)
8531                 return ret;
8532
8533         /*
8534          * As i40e supports less than 64 flow types, only first 64 bits need to
8535          * be configured.
8536          */
8537         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8538                 if (mask0 & (1UL << i)) {
8539                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8540                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8541
8542                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8543                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8544                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8545                                         i40e_write_global_rx_ctl(hw,
8546                                                           I40E_GLQF_HSYM(j),
8547                                                           reg);
8548                         }
8549                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8550                 }
8551         }
8552
8553         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8554         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8555                 /* Toeplitz */
8556                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8557                         PMD_DRV_LOG(DEBUG,
8558                                 "Hash function already set to Toeplitz");
8559                         goto out;
8560                 }
8561                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8562         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8563                 /* Simple XOR */
8564                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8565                         PMD_DRV_LOG(DEBUG,
8566                                 "Hash function already set to Simple XOR");
8567                         goto out;
8568                 }
8569                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8570         } else
8571                 /* Use the default, and keep it as it is */
8572                 goto out;
8573
8574         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8575         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8576
8577 out:
8578         I40E_WRITE_FLUSH(hw);
8579
8580         return 0;
8581 }
8582
8583 /**
8584  * Valid input sets for hash and flow director filters per PCTYPE
8585  */
8586 static uint64_t
8587 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8588                 enum rte_filter_type filter)
8589 {
8590         uint64_t valid;
8591
8592         static const uint64_t valid_hash_inset_table[] = {
8593                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8594                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8595                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8596                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8597                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8598                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8599                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8600                         I40E_INSET_FLEX_PAYLOAD,
8601                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8602                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8603                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8604                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8605                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8606                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8607                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8608                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8609                         I40E_INSET_FLEX_PAYLOAD,
8610                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8611                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8612                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8613                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8614                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8615                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8616                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8617                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8618                         I40E_INSET_FLEX_PAYLOAD,
8619                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8620                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8621                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8622                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8623                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8624                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8625                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8626                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8627                         I40E_INSET_FLEX_PAYLOAD,
8628                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8629                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8630                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8631                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8632                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8633                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8634                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8635                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8636                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8637                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8638                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8639                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8640                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8641                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8642                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8643                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8644                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8645                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8646                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8647                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8648                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8649                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8650                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8651                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8652                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8653                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8654                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8655                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8656                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8657                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8658                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8659                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8660                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8661                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8662                         I40E_INSET_FLEX_PAYLOAD,
8663                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8664                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8665                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8666                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8667                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8668                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8669                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8670                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8671                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8672                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8673                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8674                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8675                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8676                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8677                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8678                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8679                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8680                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8681                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8682                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8683                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8684                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8685                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8686                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8687                         I40E_INSET_FLEX_PAYLOAD,
8688                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8689                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8690                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8691                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8692                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8693                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8694                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8695                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8696                         I40E_INSET_FLEX_PAYLOAD,
8697                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8698                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8699                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8700                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8701                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8702                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8703                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8704                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8705                         I40E_INSET_FLEX_PAYLOAD,
8706                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8707                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8708                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8709                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8710                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8711                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8712                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8713                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8714                         I40E_INSET_FLEX_PAYLOAD,
8715                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8716                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8717                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8718                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8719                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8720                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8721                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8722                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8723                         I40E_INSET_FLEX_PAYLOAD,
8724                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8725                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8726                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8727                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8728                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8729                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8730                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8731                         I40E_INSET_FLEX_PAYLOAD,
8732                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8733                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8734                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8735                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8736                         I40E_INSET_FLEX_PAYLOAD,
8737         };
8738
8739         /**
8740          * Flow director supports only fields defined in
8741          * union rte_eth_fdir_flow.
8742          */
8743         static const uint64_t valid_fdir_inset_table[] = {
8744                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8745                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8746                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8747                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8748                 I40E_INSET_IPV4_TTL,
8749                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8750                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8751                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8752                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8753                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8754                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8755                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8756                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8757                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8758                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8759                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8760                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8761                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8762                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8763                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8764                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8765                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8766                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8767                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8768                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8769                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8770                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8771                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8772                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8773                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8774                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8775                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8776                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8777                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8778                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8779                 I40E_INSET_SCTP_VT,
8780                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8781                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8782                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8783                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8784                 I40E_INSET_IPV4_TTL,
8785                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8786                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8787                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8788                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8789                 I40E_INSET_IPV6_HOP_LIMIT,
8790                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8791                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8792                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8793                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8794                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8795                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8796                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8797                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8798                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8799                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8800                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8801                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8802                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8803                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8804                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8805                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8806                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8807                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8808                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8809                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8810                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8811                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8812                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8813                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8814                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8815                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8816                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8817                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8818                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8819                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8820                 I40E_INSET_SCTP_VT,
8821                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8822                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8823                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8824                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8825                 I40E_INSET_IPV6_HOP_LIMIT,
8826                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8827                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8828                 I40E_INSET_LAST_ETHER_TYPE,
8829         };
8830
8831         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8832                 return 0;
8833         if (filter == RTE_ETH_FILTER_HASH)
8834                 valid = valid_hash_inset_table[pctype];
8835         else
8836                 valid = valid_fdir_inset_table[pctype];
8837
8838         return valid;
8839 }
8840
8841 /**
8842  * Validate if the input set is allowed for a specific PCTYPE
8843  */
8844 int
8845 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8846                 enum rte_filter_type filter, uint64_t inset)
8847 {
8848         uint64_t valid;
8849
8850         valid = i40e_get_valid_input_set(pctype, filter);
8851         if (inset & (~valid))
8852                 return -EINVAL;
8853
8854         return 0;
8855 }
8856
8857 /* default input set fields combination per pctype */
8858 uint64_t
8859 i40e_get_default_input_set(uint16_t pctype)
8860 {
8861         static const uint64_t default_inset_table[] = {
8862                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8863                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8864                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8865                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8866                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8867                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8868                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8869                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8870                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8871                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8872                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8873                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8874                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8875                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8876                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8877                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8878                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8879                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8880                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8881                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8882                         I40E_INSET_SCTP_VT,
8883                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8884                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8885                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8886                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8887                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8888                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8889                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8890                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8891                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8892                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8893                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8894                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8895                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8896                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8897                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8898                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8899                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8900                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8901                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8902                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8903                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8904                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8905                         I40E_INSET_SCTP_VT,
8906                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8907                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8908                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8909                         I40E_INSET_LAST_ETHER_TYPE,
8910         };
8911
8912         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8913                 return 0;
8914
8915         return default_inset_table[pctype];
8916 }
8917
8918 /**
8919  * Parse the input set from index to logical bit masks
8920  */
8921 static int
8922 i40e_parse_input_set(uint64_t *inset,
8923                      enum i40e_filter_pctype pctype,
8924                      enum rte_eth_input_set_field *field,
8925                      uint16_t size)
8926 {
8927         uint16_t i, j;
8928         int ret = -EINVAL;
8929
8930         static const struct {
8931                 enum rte_eth_input_set_field field;
8932                 uint64_t inset;
8933         } inset_convert_table[] = {
8934                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8935                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8936                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8937                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8938                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8939                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8940                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8941                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8942                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8943                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8944                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8945                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8946                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8947                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8948                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8949                         I40E_INSET_IPV6_NEXT_HDR},
8950                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8951                         I40E_INSET_IPV6_HOP_LIMIT},
8952                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8953                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8954                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8955                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8956                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8957                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8958                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8959                         I40E_INSET_SCTP_VT},
8960                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8961                         I40E_INSET_TUNNEL_DMAC},
8962                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8963                         I40E_INSET_VLAN_TUNNEL},
8964                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8965                         I40E_INSET_TUNNEL_ID},
8966                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8967                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8968                         I40E_INSET_FLEX_PAYLOAD_W1},
8969                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8970                         I40E_INSET_FLEX_PAYLOAD_W2},
8971                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8972                         I40E_INSET_FLEX_PAYLOAD_W3},
8973                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8974                         I40E_INSET_FLEX_PAYLOAD_W4},
8975                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8976                         I40E_INSET_FLEX_PAYLOAD_W5},
8977                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8978                         I40E_INSET_FLEX_PAYLOAD_W6},
8979                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8980                         I40E_INSET_FLEX_PAYLOAD_W7},
8981                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8982                         I40E_INSET_FLEX_PAYLOAD_W8},
8983         };
8984
8985         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8986                 return ret;
8987
8988         /* Only one item allowed for default or all */
8989         if (size == 1) {
8990                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8991                         *inset = i40e_get_default_input_set(pctype);
8992                         return 0;
8993                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8994                         *inset = I40E_INSET_NONE;
8995                         return 0;
8996                 }
8997         }
8998
8999         for (i = 0, *inset = 0; i < size; i++) {
9000                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9001                         if (field[i] == inset_convert_table[j].field) {
9002                                 *inset |= inset_convert_table[j].inset;
9003                                 break;
9004                         }
9005                 }
9006
9007                 /* It contains unsupported input set, return immediately */
9008                 if (j == RTE_DIM(inset_convert_table))
9009                         return ret;
9010         }
9011
9012         return 0;
9013 }
9014
9015 /**
9016  * Translate the input set from bit masks to register aware bit masks
9017  * and vice versa
9018  */
9019 uint64_t
9020 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9021 {
9022         uint64_t val = 0;
9023         uint16_t i;
9024
9025         struct inset_map {
9026                 uint64_t inset;
9027                 uint64_t inset_reg;
9028         };
9029
9030         static const struct inset_map inset_map_common[] = {
9031                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9032                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9033                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9034                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9035                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9036                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9037                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9038                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9039                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9040                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9041                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9042                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9043                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9044                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9045                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9046                 {I40E_INSET_TUNNEL_DMAC,
9047                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9048                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9049                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9050                 {I40E_INSET_TUNNEL_SRC_PORT,
9051                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9052                 {I40E_INSET_TUNNEL_DST_PORT,
9053                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9054                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9055                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9056                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9057                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9058                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9059                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9060                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9061                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9062                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9063         };
9064
9065     /* some different registers map in x722*/
9066         static const struct inset_map inset_map_diff_x722[] = {
9067                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9068                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9069                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9070                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9071         };
9072
9073         static const struct inset_map inset_map_diff_not_x722[] = {
9074                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9075                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9076                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9077                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9078         };
9079
9080         if (input == 0)
9081                 return val;
9082
9083         /* Translate input set to register aware inset */
9084         if (type == I40E_MAC_X722) {
9085                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9086                         if (input & inset_map_diff_x722[i].inset)
9087                                 val |= inset_map_diff_x722[i].inset_reg;
9088                 }
9089         } else {
9090                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9091                         if (input & inset_map_diff_not_x722[i].inset)
9092                                 val |= inset_map_diff_not_x722[i].inset_reg;
9093                 }
9094         }
9095
9096         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9097                 if (input & inset_map_common[i].inset)
9098                         val |= inset_map_common[i].inset_reg;
9099         }
9100
9101         return val;
9102 }
9103
9104 int
9105 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9106 {
9107         uint8_t i, idx = 0;
9108         uint64_t inset_need_mask = inset;
9109
9110         static const struct {
9111                 uint64_t inset;
9112                 uint32_t mask;
9113         } inset_mask_map[] = {
9114                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9115                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9116                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9117                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9118                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9119                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9120                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9121                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9122         };
9123
9124         if (!inset || !mask || !nb_elem)
9125                 return 0;
9126
9127         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9128                 /* Clear the inset bit, if no MASK is required,
9129                  * for example proto + ttl
9130                  */
9131                 if ((inset & inset_mask_map[i].inset) ==
9132                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9133                         inset_need_mask &= ~inset_mask_map[i].inset;
9134                 if (!inset_need_mask)
9135                         return 0;
9136         }
9137         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9138                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9139                     inset_mask_map[i].inset) {
9140                         if (idx >= nb_elem) {
9141                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9142                                 return -EINVAL;
9143                         }
9144                         mask[idx] = inset_mask_map[i].mask;
9145                         idx++;
9146                 }
9147         }
9148
9149         return idx;
9150 }
9151
9152 void
9153 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9154 {
9155         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9156
9157         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9158         if (reg != val)
9159                 i40e_write_rx_ctl(hw, addr, val);
9160         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9161                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9162 }
9163
9164 void
9165 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9166 {
9167         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9168
9169         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9170         if (reg != val)
9171                 i40e_write_global_rx_ctl(hw, addr, val);
9172         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9173                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9174 }
9175
9176 static void
9177 i40e_filter_input_set_init(struct i40e_pf *pf)
9178 {
9179         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9180         enum i40e_filter_pctype pctype;
9181         uint64_t input_set, inset_reg;
9182         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9183         int num, i;
9184         uint16_t flow_type;
9185
9186         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9187              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9188                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9189
9190                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9191                         continue;
9192
9193                 input_set = i40e_get_default_input_set(pctype);
9194
9195                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9196                                                    I40E_INSET_MASK_NUM_REG);
9197                 if (num < 0)
9198                         return;
9199                 if (pf->support_multi_driver && num > 0) {
9200                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9201                         return;
9202                 }
9203                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9204                                         input_set);
9205
9206                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9207                                       (uint32_t)(inset_reg & UINT32_MAX));
9208                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9209                                      (uint32_t)((inset_reg >>
9210                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9211                 if (!pf->support_multi_driver) {
9212                         i40e_check_write_global_reg(hw,
9213                                             I40E_GLQF_HASH_INSET(0, pctype),
9214                                             (uint32_t)(inset_reg & UINT32_MAX));
9215                         i40e_check_write_global_reg(hw,
9216                                              I40E_GLQF_HASH_INSET(1, pctype),
9217                                              (uint32_t)((inset_reg >>
9218                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9219
9220                         for (i = 0; i < num; i++) {
9221                                 i40e_check_write_global_reg(hw,
9222                                                     I40E_GLQF_FD_MSK(i, pctype),
9223                                                     mask_reg[i]);
9224                                 i40e_check_write_global_reg(hw,
9225                                                   I40E_GLQF_HASH_MSK(i, pctype),
9226                                                   mask_reg[i]);
9227                         }
9228                         /*clear unused mask registers of the pctype */
9229                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9230                                 i40e_check_write_global_reg(hw,
9231                                                     I40E_GLQF_FD_MSK(i, pctype),
9232                                                     0);
9233                                 i40e_check_write_global_reg(hw,
9234                                                   I40E_GLQF_HASH_MSK(i, pctype),
9235                                                   0);
9236                         }
9237                 } else {
9238                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9239                 }
9240                 I40E_WRITE_FLUSH(hw);
9241
9242                 /* store the default input set */
9243                 if (!pf->support_multi_driver)
9244                         pf->hash_input_set[pctype] = input_set;
9245                 pf->fdir.input_set[pctype] = input_set;
9246         }
9247
9248         if (!pf->support_multi_driver) {
9249                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9250                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9251                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9252         }
9253 }
9254
9255 int
9256 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9257                          struct rte_eth_input_set_conf *conf)
9258 {
9259         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9260         enum i40e_filter_pctype pctype;
9261         uint64_t input_set, inset_reg = 0;
9262         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9263         int ret, i, num;
9264
9265         if (!conf) {
9266                 PMD_DRV_LOG(ERR, "Invalid pointer");
9267                 return -EFAULT;
9268         }
9269         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9270             conf->op != RTE_ETH_INPUT_SET_ADD) {
9271                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9272                 return -EINVAL;
9273         }
9274
9275         if (pf->support_multi_driver) {
9276                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9277                 return -ENOTSUP;
9278         }
9279
9280         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9281         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9282                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9283                 return -EINVAL;
9284         }
9285
9286         if (hw->mac.type == I40E_MAC_X722) {
9287                 /* get translated pctype value in fd pctype register */
9288                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9289                         I40E_GLQF_FD_PCTYPES((int)pctype));
9290         }
9291
9292         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9293                                    conf->inset_size);
9294         if (ret) {
9295                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9296                 return -EINVAL;
9297         }
9298
9299         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9300                 /* get inset value in register */
9301                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9302                 inset_reg <<= I40E_32_BIT_WIDTH;
9303                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9304                 input_set |= pf->hash_input_set[pctype];
9305         }
9306         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9307                                            I40E_INSET_MASK_NUM_REG);
9308         if (num < 0)
9309                 return -EINVAL;
9310
9311         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9312
9313         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9314                                     (uint32_t)(inset_reg & UINT32_MAX));
9315         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9316                                     (uint32_t)((inset_reg >>
9317                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9318         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9319
9320         for (i = 0; i < num; i++)
9321                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9322                                             mask_reg[i]);
9323         /*clear unused mask registers of the pctype */
9324         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9325                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9326                                             0);
9327         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9328         I40E_WRITE_FLUSH(hw);
9329
9330         pf->hash_input_set[pctype] = input_set;
9331         return 0;
9332 }
9333
9334 int
9335 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9336                          struct rte_eth_input_set_conf *conf)
9337 {
9338         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9339         enum i40e_filter_pctype pctype;
9340         uint64_t input_set, inset_reg = 0;
9341         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9342         int ret, i, num;
9343
9344         if (!hw || !conf) {
9345                 PMD_DRV_LOG(ERR, "Invalid pointer");
9346                 return -EFAULT;
9347         }
9348         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9349             conf->op != RTE_ETH_INPUT_SET_ADD) {
9350                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9351                 return -EINVAL;
9352         }
9353
9354         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9355
9356         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9357                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9358                 return -EINVAL;
9359         }
9360
9361         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9362                                    conf->inset_size);
9363         if (ret) {
9364                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9365                 return -EINVAL;
9366         }
9367
9368         /* get inset value in register */
9369         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9370         inset_reg <<= I40E_32_BIT_WIDTH;
9371         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9372
9373         /* Can not change the inset reg for flex payload for fdir,
9374          * it is done by writing I40E_PRTQF_FD_FLXINSET
9375          * in i40e_set_flex_mask_on_pctype.
9376          */
9377         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9378                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9379         else
9380                 input_set |= pf->fdir.input_set[pctype];
9381         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9382                                            I40E_INSET_MASK_NUM_REG);
9383         if (num < 0)
9384                 return -EINVAL;
9385         if (pf->support_multi_driver && num > 0) {
9386                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9387                 return -ENOTSUP;
9388         }
9389
9390         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9391
9392         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9393                               (uint32_t)(inset_reg & UINT32_MAX));
9394         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9395                              (uint32_t)((inset_reg >>
9396                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9397
9398         if (!pf->support_multi_driver) {
9399                 for (i = 0; i < num; i++)
9400                         i40e_check_write_global_reg(hw,
9401                                                     I40E_GLQF_FD_MSK(i, pctype),
9402                                                     mask_reg[i]);
9403                 /*clear unused mask registers of the pctype */
9404                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9405                         i40e_check_write_global_reg(hw,
9406                                                     I40E_GLQF_FD_MSK(i, pctype),
9407                                                     0);
9408                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9409         } else {
9410                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9411         }
9412         I40E_WRITE_FLUSH(hw);
9413
9414         pf->fdir.input_set[pctype] = input_set;
9415         return 0;
9416 }
9417
9418 static int
9419 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9420 {
9421         int ret = 0;
9422
9423         if (!hw || !info) {
9424                 PMD_DRV_LOG(ERR, "Invalid pointer");
9425                 return -EFAULT;
9426         }
9427
9428         switch (info->info_type) {
9429         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9430                 i40e_get_symmetric_hash_enable_per_port(hw,
9431                                         &(info->info.enable));
9432                 break;
9433         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9434                 ret = i40e_get_hash_filter_global_config(hw,
9435                                 &(info->info.global_conf));
9436                 break;
9437         default:
9438                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9439                                                         info->info_type);
9440                 ret = -EINVAL;
9441                 break;
9442         }
9443
9444         return ret;
9445 }
9446
9447 static int
9448 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9449 {
9450         int ret = 0;
9451
9452         if (!hw || !info) {
9453                 PMD_DRV_LOG(ERR, "Invalid pointer");
9454                 return -EFAULT;
9455         }
9456
9457         switch (info->info_type) {
9458         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9459                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9460                 break;
9461         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9462                 ret = i40e_set_hash_filter_global_config(hw,
9463                                 &(info->info.global_conf));
9464                 break;
9465         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9466                 ret = i40e_hash_filter_inset_select(hw,
9467                                                &(info->info.input_set_conf));
9468                 break;
9469
9470         default:
9471                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9472                                                         info->info_type);
9473                 ret = -EINVAL;
9474                 break;
9475         }
9476
9477         return ret;
9478 }
9479
9480 /* Operations for hash function */
9481 static int
9482 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9483                       enum rte_filter_op filter_op,
9484                       void *arg)
9485 {
9486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9487         int ret = 0;
9488
9489         switch (filter_op) {
9490         case RTE_ETH_FILTER_NOP:
9491                 break;
9492         case RTE_ETH_FILTER_GET:
9493                 ret = i40e_hash_filter_get(hw,
9494                         (struct rte_eth_hash_filter_info *)arg);
9495                 break;
9496         case RTE_ETH_FILTER_SET:
9497                 ret = i40e_hash_filter_set(hw,
9498                         (struct rte_eth_hash_filter_info *)arg);
9499                 break;
9500         default:
9501                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9502                                                                 filter_op);
9503                 ret = -ENOTSUP;
9504                 break;
9505         }
9506
9507         return ret;
9508 }
9509
9510 /* Convert ethertype filter structure */
9511 static int
9512 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9513                               struct i40e_ethertype_filter *filter)
9514 {
9515         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9516         filter->input.ether_type = input->ether_type;
9517         filter->flags = input->flags;
9518         filter->queue = input->queue;
9519
9520         return 0;
9521 }
9522
9523 /* Check if there exists the ehtertype filter */
9524 struct i40e_ethertype_filter *
9525 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9526                                 const struct i40e_ethertype_filter_input *input)
9527 {
9528         int ret;
9529
9530         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9531         if (ret < 0)
9532                 return NULL;
9533
9534         return ethertype_rule->hash_map[ret];
9535 }
9536
9537 /* Add ethertype filter in SW list */
9538 static int
9539 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9540                                 struct i40e_ethertype_filter *filter)
9541 {
9542         struct i40e_ethertype_rule *rule = &pf->ethertype;
9543         int ret;
9544
9545         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9546         if (ret < 0) {
9547                 PMD_DRV_LOG(ERR,
9548                             "Failed to insert ethertype filter"
9549                             " to hash table %d!",
9550                             ret);
9551                 return ret;
9552         }
9553         rule->hash_map[ret] = filter;
9554
9555         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9556
9557         return 0;
9558 }
9559
9560 /* Delete ethertype filter in SW list */
9561 int
9562 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9563                              struct i40e_ethertype_filter_input *input)
9564 {
9565         struct i40e_ethertype_rule *rule = &pf->ethertype;
9566         struct i40e_ethertype_filter *filter;
9567         int ret;
9568
9569         ret = rte_hash_del_key(rule->hash_table, input);
9570         if (ret < 0) {
9571                 PMD_DRV_LOG(ERR,
9572                             "Failed to delete ethertype filter"
9573                             " to hash table %d!",
9574                             ret);
9575                 return ret;
9576         }
9577         filter = rule->hash_map[ret];
9578         rule->hash_map[ret] = NULL;
9579
9580         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9581         rte_free(filter);
9582
9583         return 0;
9584 }
9585
9586 /*
9587  * Configure ethertype filter, which can director packet by filtering
9588  * with mac address and ether_type or only ether_type
9589  */
9590 int
9591 i40e_ethertype_filter_set(struct i40e_pf *pf,
9592                         struct rte_eth_ethertype_filter *filter,
9593                         bool add)
9594 {
9595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9596         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9597         struct i40e_ethertype_filter *ethertype_filter, *node;
9598         struct i40e_ethertype_filter check_filter;
9599         struct i40e_control_filter_stats stats;
9600         uint16_t flags = 0;
9601         int ret;
9602
9603         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9604                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9605                 return -EINVAL;
9606         }
9607         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9608                 filter->ether_type == ETHER_TYPE_IPv6) {
9609                 PMD_DRV_LOG(ERR,
9610                         "unsupported ether_type(0x%04x) in control packet filter.",
9611                         filter->ether_type);
9612                 return -EINVAL;
9613         }
9614         if (filter->ether_type == ETHER_TYPE_VLAN)
9615                 PMD_DRV_LOG(WARNING,
9616                         "filter vlan ether_type in first tag is not supported.");
9617
9618         /* Check if there is the filter in SW list */
9619         memset(&check_filter, 0, sizeof(check_filter));
9620         i40e_ethertype_filter_convert(filter, &check_filter);
9621         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9622                                                &check_filter.input);
9623         if (add && node) {
9624                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9625                 return -EINVAL;
9626         }
9627
9628         if (!add && !node) {
9629                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9630                 return -EINVAL;
9631         }
9632
9633         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9634                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9635         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9636                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9637         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9638
9639         memset(&stats, 0, sizeof(stats));
9640         ret = i40e_aq_add_rem_control_packet_filter(hw,
9641                         filter->mac_addr.addr_bytes,
9642                         filter->ether_type, flags,
9643                         pf->main_vsi->seid,
9644                         filter->queue, add, &stats, NULL);
9645
9646         PMD_DRV_LOG(INFO,
9647                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9648                 ret, stats.mac_etype_used, stats.etype_used,
9649                 stats.mac_etype_free, stats.etype_free);
9650         if (ret < 0)
9651                 return -ENOSYS;
9652
9653         /* Add or delete a filter in SW list */
9654         if (add) {
9655                 ethertype_filter = rte_zmalloc("ethertype_filter",
9656                                        sizeof(*ethertype_filter), 0);
9657                 if (ethertype_filter == NULL) {
9658                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9659                         return -ENOMEM;
9660                 }
9661
9662                 rte_memcpy(ethertype_filter, &check_filter,
9663                            sizeof(check_filter));
9664                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9665                 if (ret < 0)
9666                         rte_free(ethertype_filter);
9667         } else {
9668                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9669         }
9670
9671         return ret;
9672 }
9673
9674 /*
9675  * Handle operations for ethertype filter.
9676  */
9677 static int
9678 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9679                                 enum rte_filter_op filter_op,
9680                                 void *arg)
9681 {
9682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9683         int ret = 0;
9684
9685         if (filter_op == RTE_ETH_FILTER_NOP)
9686                 return ret;
9687
9688         if (arg == NULL) {
9689                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9690                             filter_op);
9691                 return -EINVAL;
9692         }
9693
9694         switch (filter_op) {
9695         case RTE_ETH_FILTER_ADD:
9696                 ret = i40e_ethertype_filter_set(pf,
9697                         (struct rte_eth_ethertype_filter *)arg,
9698                         TRUE);
9699                 break;
9700         case RTE_ETH_FILTER_DELETE:
9701                 ret = i40e_ethertype_filter_set(pf,
9702                         (struct rte_eth_ethertype_filter *)arg,
9703                         FALSE);
9704                 break;
9705         default:
9706                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9707                 ret = -ENOSYS;
9708                 break;
9709         }
9710         return ret;
9711 }
9712
9713 static int
9714 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9715                      enum rte_filter_type filter_type,
9716                      enum rte_filter_op filter_op,
9717                      void *arg)
9718 {
9719         int ret = 0;
9720
9721         if (dev == NULL)
9722                 return -EINVAL;
9723
9724         switch (filter_type) {
9725         case RTE_ETH_FILTER_NONE:
9726                 /* For global configuration */
9727                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9728                 break;
9729         case RTE_ETH_FILTER_HASH:
9730                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9731                 break;
9732         case RTE_ETH_FILTER_MACVLAN:
9733                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9734                 break;
9735         case RTE_ETH_FILTER_ETHERTYPE:
9736                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9737                 break;
9738         case RTE_ETH_FILTER_TUNNEL:
9739                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9740                 break;
9741         case RTE_ETH_FILTER_FDIR:
9742                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9743                 break;
9744         case RTE_ETH_FILTER_GENERIC:
9745                 if (filter_op != RTE_ETH_FILTER_GET)
9746                         return -EINVAL;
9747                 *(const void **)arg = &i40e_flow_ops;
9748                 break;
9749         default:
9750                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9751                                                         filter_type);
9752                 ret = -EINVAL;
9753                 break;
9754         }
9755
9756         return ret;
9757 }
9758
9759 /*
9760  * Check and enable Extended Tag.
9761  * Enabling Extended Tag is important for 40G performance.
9762  */
9763 static void
9764 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9765 {
9766         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9767         uint32_t buf = 0;
9768         int ret;
9769
9770         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9771                                       PCI_DEV_CAP_REG);
9772         if (ret < 0) {
9773                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9774                             PCI_DEV_CAP_REG);
9775                 return;
9776         }
9777         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9778                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9779                 return;
9780         }
9781
9782         buf = 0;
9783         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9784                                       PCI_DEV_CTRL_REG);
9785         if (ret < 0) {
9786                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9787                             PCI_DEV_CTRL_REG);
9788                 return;
9789         }
9790         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9791                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9792                 return;
9793         }
9794         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9795         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9796                                        PCI_DEV_CTRL_REG);
9797         if (ret < 0) {
9798                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9799                             PCI_DEV_CTRL_REG);
9800                 return;
9801         }
9802 }
9803
9804 /*
9805  * As some registers wouldn't be reset unless a global hardware reset,
9806  * hardware initialization is needed to put those registers into an
9807  * expected initial state.
9808  */
9809 static void
9810 i40e_hw_init(struct rte_eth_dev *dev)
9811 {
9812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9813
9814         i40e_enable_extended_tag(dev);
9815
9816         /* clear the PF Queue Filter control register */
9817         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9818
9819         /* Disable symmetric hash per port */
9820         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9821 }
9822
9823 /*
9824  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9825  * however this function will return only one highest pctype index,
9826  * which is not quite correct. This is known problem of i40e driver
9827  * and needs to be fixed later.
9828  */
9829 enum i40e_filter_pctype
9830 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9831 {
9832         int i;
9833         uint64_t pctype_mask;
9834
9835         if (flow_type < I40E_FLOW_TYPE_MAX) {
9836                 pctype_mask = adapter->pctypes_tbl[flow_type];
9837                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9838                         if (pctype_mask & (1ULL << i))
9839                                 return (enum i40e_filter_pctype)i;
9840                 }
9841         }
9842         return I40E_FILTER_PCTYPE_INVALID;
9843 }
9844
9845 uint16_t
9846 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9847                         enum i40e_filter_pctype pctype)
9848 {
9849         uint16_t flowtype;
9850         uint64_t pctype_mask = 1ULL << pctype;
9851
9852         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9853              flowtype++) {
9854                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9855                         return flowtype;
9856         }
9857
9858         return RTE_ETH_FLOW_UNKNOWN;
9859 }
9860
9861 /*
9862  * On X710, performance number is far from the expectation on recent firmware
9863  * versions; on XL710, performance number is also far from the expectation on
9864  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9865  * mode is enabled and port MAC address is equal to the packet destination MAC
9866  * address. The fix for this issue may not be integrated in the following
9867  * firmware version. So the workaround in software driver is needed. It needs
9868  * to modify the initial values of 3 internal only registers for both X710 and
9869  * XL710. Note that the values for X710 or XL710 could be different, and the
9870  * workaround can be removed when it is fixed in firmware in the future.
9871  */
9872
9873 /* For both X710 and XL710 */
9874 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9875 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9876 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9877
9878 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9879 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9880
9881 /* For X722 */
9882 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9883 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9884
9885 /* For X710 */
9886 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9887 /* For XL710 */
9888 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9889 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9890
9891 static int
9892 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9893 {
9894         enum i40e_status_code status;
9895         struct i40e_aq_get_phy_abilities_resp phy_ab;
9896         int ret = -ENOTSUP;
9897         int retries = 0;
9898
9899         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9900                                               NULL);
9901
9902         while (status) {
9903                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9904                         status);
9905                 retries++;
9906                 rte_delay_us(100000);
9907                 if  (retries < 5)
9908                         status = i40e_aq_get_phy_capabilities(hw, false,
9909                                         true, &phy_ab, NULL);
9910                 else
9911                         return ret;
9912         }
9913         return 0;
9914 }
9915
9916 static void
9917 i40e_configure_registers(struct i40e_hw *hw)
9918 {
9919         static struct {
9920                 uint32_t addr;
9921                 uint64_t val;
9922         } reg_table[] = {
9923                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9924                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9925                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9926         };
9927         uint64_t reg;
9928         uint32_t i;
9929         int ret;
9930
9931         for (i = 0; i < RTE_DIM(reg_table); i++) {
9932                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9933                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9934                                 reg_table[i].val =
9935                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9936                         else /* For X710/XL710/XXV710 */
9937                                 if (hw->aq.fw_maj_ver < 6)
9938                                         reg_table[i].val =
9939                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9940                                 else
9941                                         reg_table[i].val =
9942                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9943                 }
9944
9945                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9946                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9947                                 reg_table[i].val =
9948                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9949                         else /* For X710/XL710/XXV710 */
9950                                 reg_table[i].val =
9951                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9952                 }
9953
9954                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9955                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9956                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9957                                 reg_table[i].val =
9958                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9959                         else /* For X710 */
9960                                 reg_table[i].val =
9961                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9962                 }
9963
9964                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9965                                                         &reg, NULL);
9966                 if (ret < 0) {
9967                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9968                                                         reg_table[i].addr);
9969                         break;
9970                 }
9971                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9972                                                 reg_table[i].addr, reg);
9973                 if (reg == reg_table[i].val)
9974                         continue;
9975
9976                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9977                                                 reg_table[i].val, NULL);
9978                 if (ret < 0) {
9979                         PMD_DRV_LOG(ERR,
9980                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9981                                 reg_table[i].val, reg_table[i].addr);
9982                         break;
9983                 }
9984                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9985                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9986         }
9987 }
9988
9989 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9990 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9991 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9992 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9993 static int
9994 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9995 {
9996         uint32_t reg;
9997         int ret;
9998
9999         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10000                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10001                 return -EINVAL;
10002         }
10003
10004         /* Configure for double VLAN RX stripping */
10005         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10006         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10007                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10008                 ret = i40e_aq_debug_write_register(hw,
10009                                                    I40E_VSI_TSR(vsi->vsi_id),
10010                                                    reg, NULL);
10011                 if (ret < 0) {
10012                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10013                                     vsi->vsi_id);
10014                         return I40E_ERR_CONFIG;
10015                 }
10016         }
10017
10018         /* Configure for double VLAN TX insertion */
10019         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10020         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10021                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10022                 ret = i40e_aq_debug_write_register(hw,
10023                                                    I40E_VSI_L2TAGSTXVALID(
10024                                                    vsi->vsi_id), reg, NULL);
10025                 if (ret < 0) {
10026                         PMD_DRV_LOG(ERR,
10027                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10028                                 vsi->vsi_id);
10029                         return I40E_ERR_CONFIG;
10030                 }
10031         }
10032
10033         return 0;
10034 }
10035
10036 /**
10037  * i40e_aq_add_mirror_rule
10038  * @hw: pointer to the hardware structure
10039  * @seid: VEB seid to add mirror rule to
10040  * @dst_id: destination vsi seid
10041  * @entries: Buffer which contains the entities to be mirrored
10042  * @count: number of entities contained in the buffer
10043  * @rule_id:the rule_id of the rule to be added
10044  *
10045  * Add a mirror rule for a given veb.
10046  *
10047  **/
10048 static enum i40e_status_code
10049 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10050                         uint16_t seid, uint16_t dst_id,
10051                         uint16_t rule_type, uint16_t *entries,
10052                         uint16_t count, uint16_t *rule_id)
10053 {
10054         struct i40e_aq_desc desc;
10055         struct i40e_aqc_add_delete_mirror_rule cmd;
10056         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10057                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10058                 &desc.params.raw;
10059         uint16_t buff_len;
10060         enum i40e_status_code status;
10061
10062         i40e_fill_default_direct_cmd_desc(&desc,
10063                                           i40e_aqc_opc_add_mirror_rule);
10064         memset(&cmd, 0, sizeof(cmd));
10065
10066         buff_len = sizeof(uint16_t) * count;
10067         desc.datalen = rte_cpu_to_le_16(buff_len);
10068         if (buff_len > 0)
10069                 desc.flags |= rte_cpu_to_le_16(
10070                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10071         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10072                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10073         cmd.num_entries = rte_cpu_to_le_16(count);
10074         cmd.seid = rte_cpu_to_le_16(seid);
10075         cmd.destination = rte_cpu_to_le_16(dst_id);
10076
10077         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10078         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10079         PMD_DRV_LOG(INFO,
10080                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10081                 hw->aq.asq_last_status, resp->rule_id,
10082                 resp->mirror_rules_used, resp->mirror_rules_free);
10083         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10084
10085         return status;
10086 }
10087
10088 /**
10089  * i40e_aq_del_mirror_rule
10090  * @hw: pointer to the hardware structure
10091  * @seid: VEB seid to add mirror rule to
10092  * @entries: Buffer which contains the entities to be mirrored
10093  * @count: number of entities contained in the buffer
10094  * @rule_id:the rule_id of the rule to be delete
10095  *
10096  * Delete a mirror rule for a given veb.
10097  *
10098  **/
10099 static enum i40e_status_code
10100 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10101                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10102                 uint16_t count, uint16_t rule_id)
10103 {
10104         struct i40e_aq_desc desc;
10105         struct i40e_aqc_add_delete_mirror_rule cmd;
10106         uint16_t buff_len = 0;
10107         enum i40e_status_code status;
10108         void *buff = NULL;
10109
10110         i40e_fill_default_direct_cmd_desc(&desc,
10111                                           i40e_aqc_opc_delete_mirror_rule);
10112         memset(&cmd, 0, sizeof(cmd));
10113         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10114                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10115                                                           I40E_AQ_FLAG_RD));
10116                 cmd.num_entries = count;
10117                 buff_len = sizeof(uint16_t) * count;
10118                 desc.datalen = rte_cpu_to_le_16(buff_len);
10119                 buff = (void *)entries;
10120         } else
10121                 /* rule id is filled in destination field for deleting mirror rule */
10122                 cmd.destination = rte_cpu_to_le_16(rule_id);
10123
10124         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10125                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10126         cmd.seid = rte_cpu_to_le_16(seid);
10127
10128         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10129         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10130
10131         return status;
10132 }
10133
10134 /**
10135  * i40e_mirror_rule_set
10136  * @dev: pointer to the hardware structure
10137  * @mirror_conf: mirror rule info
10138  * @sw_id: mirror rule's sw_id
10139  * @on: enable/disable
10140  *
10141  * set a mirror rule.
10142  *
10143  **/
10144 static int
10145 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10146                         struct rte_eth_mirror_conf *mirror_conf,
10147                         uint8_t sw_id, uint8_t on)
10148 {
10149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10151         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10152         struct i40e_mirror_rule *parent = NULL;
10153         uint16_t seid, dst_seid, rule_id;
10154         uint16_t i, j = 0;
10155         int ret;
10156
10157         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10158
10159         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10160                 PMD_DRV_LOG(ERR,
10161                         "mirror rule can not be configured without veb or vfs.");
10162                 return -ENOSYS;
10163         }
10164         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10165                 PMD_DRV_LOG(ERR, "mirror table is full.");
10166                 return -ENOSPC;
10167         }
10168         if (mirror_conf->dst_pool > pf->vf_num) {
10169                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10170                                  mirror_conf->dst_pool);
10171                 return -EINVAL;
10172         }
10173
10174         seid = pf->main_vsi->veb->seid;
10175
10176         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10177                 if (sw_id <= it->index) {
10178                         mirr_rule = it;
10179                         break;
10180                 }
10181                 parent = it;
10182         }
10183         if (mirr_rule && sw_id == mirr_rule->index) {
10184                 if (on) {
10185                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10186                         return -EEXIST;
10187                 } else {
10188                         ret = i40e_aq_del_mirror_rule(hw, seid,
10189                                         mirr_rule->rule_type,
10190                                         mirr_rule->entries,
10191                                         mirr_rule->num_entries, mirr_rule->id);
10192                         if (ret < 0) {
10193                                 PMD_DRV_LOG(ERR,
10194                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10195                                         ret, hw->aq.asq_last_status);
10196                                 return -ENOSYS;
10197                         }
10198                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10199                         rte_free(mirr_rule);
10200                         pf->nb_mirror_rule--;
10201                         return 0;
10202                 }
10203         } else if (!on) {
10204                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10205                 return -ENOENT;
10206         }
10207
10208         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10209                                 sizeof(struct i40e_mirror_rule) , 0);
10210         if (!mirr_rule) {
10211                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10212                 return I40E_ERR_NO_MEMORY;
10213         }
10214         switch (mirror_conf->rule_type) {
10215         case ETH_MIRROR_VLAN:
10216                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10217                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10218                                 mirr_rule->entries[j] =
10219                                         mirror_conf->vlan.vlan_id[i];
10220                                 j++;
10221                         }
10222                 }
10223                 if (j == 0) {
10224                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10225                         rte_free(mirr_rule);
10226                         return -EINVAL;
10227                 }
10228                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10229                 break;
10230         case ETH_MIRROR_VIRTUAL_POOL_UP:
10231         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10232                 /* check if the specified pool bit is out of range */
10233                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10234                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10235                         rte_free(mirr_rule);
10236                         return -EINVAL;
10237                 }
10238                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10239                         if (mirror_conf->pool_mask & (1ULL << i)) {
10240                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10241                                 j++;
10242                         }
10243                 }
10244                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10245                         /* add pf vsi to entries */
10246                         mirr_rule->entries[j] = pf->main_vsi_seid;
10247                         j++;
10248                 }
10249                 if (j == 0) {
10250                         PMD_DRV_LOG(ERR, "pool is not specified.");
10251                         rte_free(mirr_rule);
10252                         return -EINVAL;
10253                 }
10254                 /* egress and ingress in aq commands means from switch but not port */
10255                 mirr_rule->rule_type =
10256                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10257                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10258                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10259                 break;
10260         case ETH_MIRROR_UPLINK_PORT:
10261                 /* egress and ingress in aq commands means from switch but not port*/
10262                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10263                 break;
10264         case ETH_MIRROR_DOWNLINK_PORT:
10265                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10266                 break;
10267         default:
10268                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10269                         mirror_conf->rule_type);
10270                 rte_free(mirr_rule);
10271                 return -EINVAL;
10272         }
10273
10274         /* If the dst_pool is equal to vf_num, consider it as PF */
10275         if (mirror_conf->dst_pool == pf->vf_num)
10276                 dst_seid = pf->main_vsi_seid;
10277         else
10278                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10279
10280         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10281                                       mirr_rule->rule_type, mirr_rule->entries,
10282                                       j, &rule_id);
10283         if (ret < 0) {
10284                 PMD_DRV_LOG(ERR,
10285                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10286                         ret, hw->aq.asq_last_status);
10287                 rte_free(mirr_rule);
10288                 return -ENOSYS;
10289         }
10290
10291         mirr_rule->index = sw_id;
10292         mirr_rule->num_entries = j;
10293         mirr_rule->id = rule_id;
10294         mirr_rule->dst_vsi_seid = dst_seid;
10295
10296         if (parent)
10297                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10298         else
10299                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10300
10301         pf->nb_mirror_rule++;
10302         return 0;
10303 }
10304
10305 /**
10306  * i40e_mirror_rule_reset
10307  * @dev: pointer to the device
10308  * @sw_id: mirror rule's sw_id
10309  *
10310  * reset a mirror rule.
10311  *
10312  **/
10313 static int
10314 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10315 {
10316         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10317         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10318         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10319         uint16_t seid;
10320         int ret;
10321
10322         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10323
10324         seid = pf->main_vsi->veb->seid;
10325
10326         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10327                 if (sw_id == it->index) {
10328                         mirr_rule = it;
10329                         break;
10330                 }
10331         }
10332         if (mirr_rule) {
10333                 ret = i40e_aq_del_mirror_rule(hw, seid,
10334                                 mirr_rule->rule_type,
10335                                 mirr_rule->entries,
10336                                 mirr_rule->num_entries, mirr_rule->id);
10337                 if (ret < 0) {
10338                         PMD_DRV_LOG(ERR,
10339                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10340                                 ret, hw->aq.asq_last_status);
10341                         return -ENOSYS;
10342                 }
10343                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10344                 rte_free(mirr_rule);
10345                 pf->nb_mirror_rule--;
10346         } else {
10347                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10348                 return -ENOENT;
10349         }
10350         return 0;
10351 }
10352
10353 static uint64_t
10354 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10355 {
10356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10357         uint64_t systim_cycles;
10358
10359         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10360         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10361                         << 32;
10362
10363         return systim_cycles;
10364 }
10365
10366 static uint64_t
10367 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10368 {
10369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10370         uint64_t rx_tstamp;
10371
10372         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10373         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10374                         << 32;
10375
10376         return rx_tstamp;
10377 }
10378
10379 static uint64_t
10380 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10381 {
10382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10383         uint64_t tx_tstamp;
10384
10385         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10386         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10387                         << 32;
10388
10389         return tx_tstamp;
10390 }
10391
10392 static void
10393 i40e_start_timecounters(struct rte_eth_dev *dev)
10394 {
10395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10396         struct i40e_adapter *adapter =
10397                         (struct i40e_adapter *)dev->data->dev_private;
10398         struct rte_eth_link link;
10399         uint32_t tsync_inc_l;
10400         uint32_t tsync_inc_h;
10401
10402         /* Get current link speed. */
10403         i40e_dev_link_update(dev, 1);
10404         rte_eth_linkstatus_get(dev, &link);
10405
10406         switch (link.link_speed) {
10407         case ETH_SPEED_NUM_40G:
10408                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10409                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10410                 break;
10411         case ETH_SPEED_NUM_10G:
10412                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10413                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10414                 break;
10415         case ETH_SPEED_NUM_1G:
10416                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10417                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10418                 break;
10419         default:
10420                 tsync_inc_l = 0x0;
10421                 tsync_inc_h = 0x0;
10422         }
10423
10424         /* Set the timesync increment value. */
10425         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10426         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10427
10428         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10429         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10430         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10431
10432         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10433         adapter->systime_tc.cc_shift = 0;
10434         adapter->systime_tc.nsec_mask = 0;
10435
10436         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10437         adapter->rx_tstamp_tc.cc_shift = 0;
10438         adapter->rx_tstamp_tc.nsec_mask = 0;
10439
10440         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10441         adapter->tx_tstamp_tc.cc_shift = 0;
10442         adapter->tx_tstamp_tc.nsec_mask = 0;
10443 }
10444
10445 static int
10446 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10447 {
10448         struct i40e_adapter *adapter =
10449                         (struct i40e_adapter *)dev->data->dev_private;
10450
10451         adapter->systime_tc.nsec += delta;
10452         adapter->rx_tstamp_tc.nsec += delta;
10453         adapter->tx_tstamp_tc.nsec += delta;
10454
10455         return 0;
10456 }
10457
10458 static int
10459 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10460 {
10461         uint64_t ns;
10462         struct i40e_adapter *adapter =
10463                         (struct i40e_adapter *)dev->data->dev_private;
10464
10465         ns = rte_timespec_to_ns(ts);
10466
10467         /* Set the timecounters to a new value. */
10468         adapter->systime_tc.nsec = ns;
10469         adapter->rx_tstamp_tc.nsec = ns;
10470         adapter->tx_tstamp_tc.nsec = ns;
10471
10472         return 0;
10473 }
10474
10475 static int
10476 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10477 {
10478         uint64_t ns, systime_cycles;
10479         struct i40e_adapter *adapter =
10480                         (struct i40e_adapter *)dev->data->dev_private;
10481
10482         systime_cycles = i40e_read_systime_cyclecounter(dev);
10483         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10484         *ts = rte_ns_to_timespec(ns);
10485
10486         return 0;
10487 }
10488
10489 static int
10490 i40e_timesync_enable(struct rte_eth_dev *dev)
10491 {
10492         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10493         uint32_t tsync_ctl_l;
10494         uint32_t tsync_ctl_h;
10495
10496         /* Stop the timesync system time. */
10497         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10498         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10499         /* Reset the timesync system time value. */
10500         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10501         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10502
10503         i40e_start_timecounters(dev);
10504
10505         /* Clear timesync registers. */
10506         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10507         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10508         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10509         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10510         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10511         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10512
10513         /* Enable timestamping of PTP packets. */
10514         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10515         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10516
10517         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10518         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10519         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10520
10521         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10522         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10523
10524         return 0;
10525 }
10526
10527 static int
10528 i40e_timesync_disable(struct rte_eth_dev *dev)
10529 {
10530         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10531         uint32_t tsync_ctl_l;
10532         uint32_t tsync_ctl_h;
10533
10534         /* Disable timestamping of transmitted PTP packets. */
10535         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10536         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10537
10538         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10539         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10540
10541         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10542         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10543
10544         /* Reset the timesync increment value. */
10545         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10546         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10547
10548         return 0;
10549 }
10550
10551 static int
10552 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10553                                 struct timespec *timestamp, uint32_t flags)
10554 {
10555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10556         struct i40e_adapter *adapter =
10557                 (struct i40e_adapter *)dev->data->dev_private;
10558
10559         uint32_t sync_status;
10560         uint32_t index = flags & 0x03;
10561         uint64_t rx_tstamp_cycles;
10562         uint64_t ns;
10563
10564         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10565         if ((sync_status & (1 << index)) == 0)
10566                 return -EINVAL;
10567
10568         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10569         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10570         *timestamp = rte_ns_to_timespec(ns);
10571
10572         return 0;
10573 }
10574
10575 static int
10576 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10577                                 struct timespec *timestamp)
10578 {
10579         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10580         struct i40e_adapter *adapter =
10581                 (struct i40e_adapter *)dev->data->dev_private;
10582
10583         uint32_t sync_status;
10584         uint64_t tx_tstamp_cycles;
10585         uint64_t ns;
10586
10587         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10588         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10589                 return -EINVAL;
10590
10591         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10592         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10593         *timestamp = rte_ns_to_timespec(ns);
10594
10595         return 0;
10596 }
10597
10598 /*
10599  * i40e_parse_dcb_configure - parse dcb configure from user
10600  * @dev: the device being configured
10601  * @dcb_cfg: pointer of the result of parse
10602  * @*tc_map: bit map of enabled traffic classes
10603  *
10604  * Returns 0 on success, negative value on failure
10605  */
10606 static int
10607 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10608                          struct i40e_dcbx_config *dcb_cfg,
10609                          uint8_t *tc_map)
10610 {
10611         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10612         uint8_t i, tc_bw, bw_lf;
10613
10614         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10615
10616         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10617         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10618                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10619                 return -EINVAL;
10620         }
10621
10622         /* assume each tc has the same bw */
10623         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10624         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10625                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10626         /* to ensure the sum of tcbw is equal to 100 */
10627         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10628         for (i = 0; i < bw_lf; i++)
10629                 dcb_cfg->etscfg.tcbwtable[i]++;
10630
10631         /* assume each tc has the same Transmission Selection Algorithm */
10632         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10633                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10634
10635         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10636                 dcb_cfg->etscfg.prioritytable[i] =
10637                                 dcb_rx_conf->dcb_tc[i];
10638
10639         /* FW needs one App to configure HW */
10640         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10641         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10642         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10643         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10644
10645         if (dcb_rx_conf->nb_tcs == 0)
10646                 *tc_map = 1; /* tc0 only */
10647         else
10648                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10649
10650         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10651                 dcb_cfg->pfc.willing = 0;
10652                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10653                 dcb_cfg->pfc.pfcenable = *tc_map;
10654         }
10655         return 0;
10656 }
10657
10658
10659 static enum i40e_status_code
10660 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10661                               struct i40e_aqc_vsi_properties_data *info,
10662                               uint8_t enabled_tcmap)
10663 {
10664         enum i40e_status_code ret;
10665         int i, total_tc = 0;
10666         uint16_t qpnum_per_tc, bsf, qp_idx;
10667         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10668         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10669         uint16_t used_queues;
10670
10671         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10672         if (ret != I40E_SUCCESS)
10673                 return ret;
10674
10675         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10676                 if (enabled_tcmap & (1 << i))
10677                         total_tc++;
10678         }
10679         if (total_tc == 0)
10680                 total_tc = 1;
10681         vsi->enabled_tc = enabled_tcmap;
10682
10683         /* different VSI has different queues assigned */
10684         if (vsi->type == I40E_VSI_MAIN)
10685                 used_queues = dev_data->nb_rx_queues -
10686                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10687         else if (vsi->type == I40E_VSI_VMDQ2)
10688                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10689         else {
10690                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10691                 return I40E_ERR_NO_AVAILABLE_VSI;
10692         }
10693
10694         qpnum_per_tc = used_queues / total_tc;
10695         /* Number of queues per enabled TC */
10696         if (qpnum_per_tc == 0) {
10697                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10698                 return I40E_ERR_INVALID_QP_ID;
10699         }
10700         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10701                                 I40E_MAX_Q_PER_TC);
10702         bsf = rte_bsf32(qpnum_per_tc);
10703
10704         /**
10705          * Configure TC and queue mapping parameters, for enabled TC,
10706          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10707          * default queue will serve it.
10708          */
10709         qp_idx = 0;
10710         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10711                 if (vsi->enabled_tc & (1 << i)) {
10712                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10713                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10714                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10715                         qp_idx += qpnum_per_tc;
10716                 } else
10717                         info->tc_mapping[i] = 0;
10718         }
10719
10720         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10721         if (vsi->type == I40E_VSI_SRIOV) {
10722                 info->mapping_flags |=
10723                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10724                 for (i = 0; i < vsi->nb_qps; i++)
10725                         info->queue_mapping[i] =
10726                                 rte_cpu_to_le_16(vsi->base_queue + i);
10727         } else {
10728                 info->mapping_flags |=
10729                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10730                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10731         }
10732         info->valid_sections |=
10733                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10734
10735         return I40E_SUCCESS;
10736 }
10737
10738 /*
10739  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10740  * @veb: VEB to be configured
10741  * @tc_map: enabled TC bitmap
10742  *
10743  * Returns 0 on success, negative value on failure
10744  */
10745 static enum i40e_status_code
10746 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10747 {
10748         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10749         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10750         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10751         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10752         enum i40e_status_code ret = I40E_SUCCESS;
10753         int i;
10754         uint32_t bw_max;
10755
10756         /* Check if enabled_tc is same as existing or new TCs */
10757         if (veb->enabled_tc == tc_map)
10758                 return ret;
10759
10760         /* configure tc bandwidth */
10761         memset(&veb_bw, 0, sizeof(veb_bw));
10762         veb_bw.tc_valid_bits = tc_map;
10763         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10764         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10765                 if (tc_map & BIT_ULL(i))
10766                         veb_bw.tc_bw_share_credits[i] = 1;
10767         }
10768         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10769                                                    &veb_bw, NULL);
10770         if (ret) {
10771                 PMD_INIT_LOG(ERR,
10772                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10773                         hw->aq.asq_last_status);
10774                 return ret;
10775         }
10776
10777         memset(&ets_query, 0, sizeof(ets_query));
10778         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10779                                                    &ets_query, NULL);
10780         if (ret != I40E_SUCCESS) {
10781                 PMD_DRV_LOG(ERR,
10782                         "Failed to get switch_comp ETS configuration %u",
10783                         hw->aq.asq_last_status);
10784                 return ret;
10785         }
10786         memset(&bw_query, 0, sizeof(bw_query));
10787         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10788                                                   &bw_query, NULL);
10789         if (ret != I40E_SUCCESS) {
10790                 PMD_DRV_LOG(ERR,
10791                         "Failed to get switch_comp bandwidth configuration %u",
10792                         hw->aq.asq_last_status);
10793                 return ret;
10794         }
10795
10796         /* store and print out BW info */
10797         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10798         veb->bw_info.bw_max = ets_query.tc_bw_max;
10799         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10800         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10801         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10802                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10803                      I40E_16_BIT_WIDTH);
10804         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10805                 veb->bw_info.bw_ets_share_credits[i] =
10806                                 bw_query.tc_bw_share_credits[i];
10807                 veb->bw_info.bw_ets_credits[i] =
10808                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10809                 /* 4 bits per TC, 4th bit is reserved */
10810                 veb->bw_info.bw_ets_max[i] =
10811                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10812                                   RTE_LEN2MASK(3, uint8_t));
10813                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10814                             veb->bw_info.bw_ets_share_credits[i]);
10815                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10816                             veb->bw_info.bw_ets_credits[i]);
10817                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10818                             veb->bw_info.bw_ets_max[i]);
10819         }
10820
10821         veb->enabled_tc = tc_map;
10822
10823         return ret;
10824 }
10825
10826
10827 /*
10828  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10829  * @vsi: VSI to be configured
10830  * @tc_map: enabled TC bitmap
10831  *
10832  * Returns 0 on success, negative value on failure
10833  */
10834 static enum i40e_status_code
10835 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10836 {
10837         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10838         struct i40e_vsi_context ctxt;
10839         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10840         enum i40e_status_code ret = I40E_SUCCESS;
10841         int i;
10842
10843         /* Check if enabled_tc is same as existing or new TCs */
10844         if (vsi->enabled_tc == tc_map)
10845                 return ret;
10846
10847         /* configure tc bandwidth */
10848         memset(&bw_data, 0, sizeof(bw_data));
10849         bw_data.tc_valid_bits = tc_map;
10850         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10851         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10852                 if (tc_map & BIT_ULL(i))
10853                         bw_data.tc_bw_credits[i] = 1;
10854         }
10855         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10856         if (ret) {
10857                 PMD_INIT_LOG(ERR,
10858                         "AQ command Config VSI BW allocation per TC failed = %d",
10859                         hw->aq.asq_last_status);
10860                 goto out;
10861         }
10862         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10863                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10864
10865         /* Update Queue Pairs Mapping for currently enabled UPs */
10866         ctxt.seid = vsi->seid;
10867         ctxt.pf_num = hw->pf_id;
10868         ctxt.vf_num = 0;
10869         ctxt.uplink_seid = vsi->uplink_seid;
10870         ctxt.info = vsi->info;
10871         i40e_get_cap(hw);
10872         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10873         if (ret)
10874                 goto out;
10875
10876         /* Update the VSI after updating the VSI queue-mapping information */
10877         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10878         if (ret) {
10879                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10880                         hw->aq.asq_last_status);
10881                 goto out;
10882         }
10883         /* update the local VSI info with updated queue map */
10884         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10885                                         sizeof(vsi->info.tc_mapping));
10886         rte_memcpy(&vsi->info.queue_mapping,
10887                         &ctxt.info.queue_mapping,
10888                 sizeof(vsi->info.queue_mapping));
10889         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10890         vsi->info.valid_sections = 0;
10891
10892         /* query and update current VSI BW information */
10893         ret = i40e_vsi_get_bw_config(vsi);
10894         if (ret) {
10895                 PMD_INIT_LOG(ERR,
10896                          "Failed updating vsi bw info, err %s aq_err %s",
10897                          i40e_stat_str(hw, ret),
10898                          i40e_aq_str(hw, hw->aq.asq_last_status));
10899                 goto out;
10900         }
10901
10902         vsi->enabled_tc = tc_map;
10903
10904 out:
10905         return ret;
10906 }
10907
10908 /*
10909  * i40e_dcb_hw_configure - program the dcb setting to hw
10910  * @pf: pf the configuration is taken on
10911  * @new_cfg: new configuration
10912  * @tc_map: enabled TC bitmap
10913  *
10914  * Returns 0 on success, negative value on failure
10915  */
10916 static enum i40e_status_code
10917 i40e_dcb_hw_configure(struct i40e_pf *pf,
10918                       struct i40e_dcbx_config *new_cfg,
10919                       uint8_t tc_map)
10920 {
10921         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10922         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10923         struct i40e_vsi *main_vsi = pf->main_vsi;
10924         struct i40e_vsi_list *vsi_list;
10925         enum i40e_status_code ret;
10926         int i;
10927         uint32_t val;
10928
10929         /* Use the FW API if FW > v4.4*/
10930         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10931               (hw->aq.fw_maj_ver >= 5))) {
10932                 PMD_INIT_LOG(ERR,
10933                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10934                 return I40E_ERR_FIRMWARE_API_VERSION;
10935         }
10936
10937         /* Check if need reconfiguration */
10938         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10939                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10940                 return I40E_SUCCESS;
10941         }
10942
10943         /* Copy the new config to the current config */
10944         *old_cfg = *new_cfg;
10945         old_cfg->etsrec = old_cfg->etscfg;
10946         ret = i40e_set_dcb_config(hw);
10947         if (ret) {
10948                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10949                          i40e_stat_str(hw, ret),
10950                          i40e_aq_str(hw, hw->aq.asq_last_status));
10951                 return ret;
10952         }
10953         /* set receive Arbiter to RR mode and ETS scheme by default */
10954         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10955                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10956                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10957                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10958                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10959                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10960                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10961                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10962                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10963                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10964                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10965                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10966                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10967         }
10968         /* get local mib to check whether it is configured correctly */
10969         /* IEEE mode */
10970         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10971         /* Get Local DCB Config */
10972         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10973                                      &hw->local_dcbx_config);
10974
10975         /* if Veb is created, need to update TC of it at first */
10976         if (main_vsi->veb) {
10977                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10978                 if (ret)
10979                         PMD_INIT_LOG(WARNING,
10980                                  "Failed configuring TC for VEB seid=%d",
10981                                  main_vsi->veb->seid);
10982         }
10983         /* Update each VSI */
10984         i40e_vsi_config_tc(main_vsi, tc_map);
10985         if (main_vsi->veb) {
10986                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10987                         /* Beside main VSI and VMDQ VSIs, only enable default
10988                          * TC for other VSIs
10989                          */
10990                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10991                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10992                                                          tc_map);
10993                         else
10994                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10995                                                          I40E_DEFAULT_TCMAP);
10996                         if (ret)
10997                                 PMD_INIT_LOG(WARNING,
10998                                         "Failed configuring TC for VSI seid=%d",
10999                                         vsi_list->vsi->seid);
11000                         /* continue */
11001                 }
11002         }
11003         return I40E_SUCCESS;
11004 }
11005
11006 /*
11007  * i40e_dcb_init_configure - initial dcb config
11008  * @dev: device being configured
11009  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11010  *
11011  * Returns 0 on success, negative value on failure
11012  */
11013 int
11014 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11015 {
11016         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11018         int i, ret = 0;
11019
11020         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11021                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11022                 return -ENOTSUP;
11023         }
11024
11025         /* DCB initialization:
11026          * Update DCB configuration from the Firmware and configure
11027          * LLDP MIB change event.
11028          */
11029         if (sw_dcb == TRUE) {
11030                 ret = i40e_init_dcb(hw);
11031                 /* If lldp agent is stopped, the return value from
11032                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11033                  * adminq status. Otherwise, it should return success.
11034                  */
11035                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11036                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11037                         memset(&hw->local_dcbx_config, 0,
11038                                 sizeof(struct i40e_dcbx_config));
11039                         /* set dcb default configuration */
11040                         hw->local_dcbx_config.etscfg.willing = 0;
11041                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11042                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11043                         hw->local_dcbx_config.etscfg.tsatable[0] =
11044                                                 I40E_IEEE_TSA_ETS;
11045                         /* all UPs mapping to TC0 */
11046                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11047                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11048                         hw->local_dcbx_config.etsrec =
11049                                 hw->local_dcbx_config.etscfg;
11050                         hw->local_dcbx_config.pfc.willing = 0;
11051                         hw->local_dcbx_config.pfc.pfccap =
11052                                                 I40E_MAX_TRAFFIC_CLASS;
11053                         /* FW needs one App to configure HW */
11054                         hw->local_dcbx_config.numapps = 1;
11055                         hw->local_dcbx_config.app[0].selector =
11056                                                 I40E_APP_SEL_ETHTYPE;
11057                         hw->local_dcbx_config.app[0].priority = 3;
11058                         hw->local_dcbx_config.app[0].protocolid =
11059                                                 I40E_APP_PROTOID_FCOE;
11060                         ret = i40e_set_dcb_config(hw);
11061                         if (ret) {
11062                                 PMD_INIT_LOG(ERR,
11063                                         "default dcb config fails. err = %d, aq_err = %d.",
11064                                         ret, hw->aq.asq_last_status);
11065                                 return -ENOSYS;
11066                         }
11067                 } else {
11068                         PMD_INIT_LOG(ERR,
11069                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11070                                 ret, hw->aq.asq_last_status);
11071                         return -ENOTSUP;
11072                 }
11073         } else {
11074                 ret = i40e_aq_start_lldp(hw, NULL);
11075                 if (ret != I40E_SUCCESS)
11076                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11077
11078                 ret = i40e_init_dcb(hw);
11079                 if (!ret) {
11080                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11081                                 PMD_INIT_LOG(ERR,
11082                                         "HW doesn't support DCBX offload.");
11083                                 return -ENOTSUP;
11084                         }
11085                 } else {
11086                         PMD_INIT_LOG(ERR,
11087                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11088                                 ret, hw->aq.asq_last_status);
11089                         return -ENOTSUP;
11090                 }
11091         }
11092         return 0;
11093 }
11094
11095 /*
11096  * i40e_dcb_setup - setup dcb related config
11097  * @dev: device being configured
11098  *
11099  * Returns 0 on success, negative value on failure
11100  */
11101 static int
11102 i40e_dcb_setup(struct rte_eth_dev *dev)
11103 {
11104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11105         struct i40e_dcbx_config dcb_cfg;
11106         uint8_t tc_map = 0;
11107         int ret = 0;
11108
11109         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11110                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11111                 return -ENOTSUP;
11112         }
11113
11114         if (pf->vf_num != 0)
11115                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11116
11117         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11118         if (ret) {
11119                 PMD_INIT_LOG(ERR, "invalid dcb config");
11120                 return -EINVAL;
11121         }
11122         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11123         if (ret) {
11124                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11125                 return -ENOSYS;
11126         }
11127
11128         return 0;
11129 }
11130
11131 static int
11132 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11133                       struct rte_eth_dcb_info *dcb_info)
11134 {
11135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11136         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11137         struct i40e_vsi *vsi = pf->main_vsi;
11138         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11139         uint16_t bsf, tc_mapping;
11140         int i, j = 0;
11141
11142         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11143                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11144         else
11145                 dcb_info->nb_tcs = 1;
11146         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11147                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11148         for (i = 0; i < dcb_info->nb_tcs; i++)
11149                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11150
11151         /* get queue mapping if vmdq is disabled */
11152         if (!pf->nb_cfg_vmdq_vsi) {
11153                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11154                         if (!(vsi->enabled_tc & (1 << i)))
11155                                 continue;
11156                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11157                         dcb_info->tc_queue.tc_rxq[j][i].base =
11158                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11159                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11160                         dcb_info->tc_queue.tc_txq[j][i].base =
11161                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11162                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11163                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11164                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11165                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11166                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11167                 }
11168                 return 0;
11169         }
11170
11171         /* get queue mapping if vmdq is enabled */
11172         do {
11173                 vsi = pf->vmdq[j].vsi;
11174                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11175                         if (!(vsi->enabled_tc & (1 << i)))
11176                                 continue;
11177                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11178                         dcb_info->tc_queue.tc_rxq[j][i].base =
11179                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11180                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11181                         dcb_info->tc_queue.tc_txq[j][i].base =
11182                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11183                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11184                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11185                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11186                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11187                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11188                 }
11189                 j++;
11190         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11191         return 0;
11192 }
11193
11194 static int
11195 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11196 {
11197         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11198         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11200         uint16_t msix_intr;
11201
11202         msix_intr = intr_handle->intr_vec[queue_id];
11203         if (msix_intr == I40E_MISC_VEC_ID)
11204                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11205                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11206                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11207                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11208         else
11209                 I40E_WRITE_REG(hw,
11210                                I40E_PFINT_DYN_CTLN(msix_intr -
11211                                                    I40E_RX_VEC_START),
11212                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11213                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11214                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11215
11216         I40E_WRITE_FLUSH(hw);
11217         rte_intr_enable(&pci_dev->intr_handle);
11218
11219         return 0;
11220 }
11221
11222 static int
11223 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11224 {
11225         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11226         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11227         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11228         uint16_t msix_intr;
11229
11230         msix_intr = intr_handle->intr_vec[queue_id];
11231         if (msix_intr == I40E_MISC_VEC_ID)
11232                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11233                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11234         else
11235                 I40E_WRITE_REG(hw,
11236                                I40E_PFINT_DYN_CTLN(msix_intr -
11237                                                    I40E_RX_VEC_START),
11238                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11239         I40E_WRITE_FLUSH(hw);
11240
11241         return 0;
11242 }
11243
11244 static int i40e_get_regs(struct rte_eth_dev *dev,
11245                          struct rte_dev_reg_info *regs)
11246 {
11247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11248         uint32_t *ptr_data = regs->data;
11249         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11250         const struct i40e_reg_info *reg_info;
11251
11252         if (ptr_data == NULL) {
11253                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11254                 regs->width = sizeof(uint32_t);
11255                 return 0;
11256         }
11257
11258         /* The first few registers have to be read using AQ operations */
11259         reg_idx = 0;
11260         while (i40e_regs_adminq[reg_idx].name) {
11261                 reg_info = &i40e_regs_adminq[reg_idx++];
11262                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11263                         for (arr_idx2 = 0;
11264                                         arr_idx2 <= reg_info->count2;
11265                                         arr_idx2++) {
11266                                 reg_offset = arr_idx * reg_info->stride1 +
11267                                         arr_idx2 * reg_info->stride2;
11268                                 reg_offset += reg_info->base_addr;
11269                                 ptr_data[reg_offset >> 2] =
11270                                         i40e_read_rx_ctl(hw, reg_offset);
11271                         }
11272         }
11273
11274         /* The remaining registers can be read using primitives */
11275         reg_idx = 0;
11276         while (i40e_regs_others[reg_idx].name) {
11277                 reg_info = &i40e_regs_others[reg_idx++];
11278                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11279                         for (arr_idx2 = 0;
11280                                         arr_idx2 <= reg_info->count2;
11281                                         arr_idx2++) {
11282                                 reg_offset = arr_idx * reg_info->stride1 +
11283                                         arr_idx2 * reg_info->stride2;
11284                                 reg_offset += reg_info->base_addr;
11285                                 ptr_data[reg_offset >> 2] =
11286                                         I40E_READ_REG(hw, reg_offset);
11287                         }
11288         }
11289
11290         return 0;
11291 }
11292
11293 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11294 {
11295         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11296
11297         /* Convert word count to byte count */
11298         return hw->nvm.sr_size << 1;
11299 }
11300
11301 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11302                            struct rte_dev_eeprom_info *eeprom)
11303 {
11304         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11305         uint16_t *data = eeprom->data;
11306         uint16_t offset, length, cnt_words;
11307         int ret_code;
11308
11309         offset = eeprom->offset >> 1;
11310         length = eeprom->length >> 1;
11311         cnt_words = length;
11312
11313         if (offset > hw->nvm.sr_size ||
11314                 offset + length > hw->nvm.sr_size) {
11315                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11316                 return -EINVAL;
11317         }
11318
11319         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11320
11321         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11322         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11323                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11324                 return -EIO;
11325         }
11326
11327         return 0;
11328 }
11329
11330 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11331                                      struct ether_addr *mac_addr)
11332 {
11333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11335         struct i40e_vsi *vsi = pf->main_vsi;
11336         struct i40e_mac_filter_info mac_filter;
11337         struct i40e_mac_filter *f;
11338         int ret;
11339
11340         if (!is_valid_assigned_ether_addr(mac_addr)) {
11341                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11342                 return -EINVAL;
11343         }
11344
11345         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11346                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11347                         break;
11348         }
11349
11350         if (f == NULL) {
11351                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11352                 return -EIO;
11353         }
11354
11355         mac_filter = f->mac_info;
11356         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11357         if (ret != I40E_SUCCESS) {
11358                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11359                 return -EIO;
11360         }
11361         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11362         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11363         if (ret != I40E_SUCCESS) {
11364                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11365                 return -EIO;
11366         }
11367         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11368
11369         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11370                                         mac_addr->addr_bytes, NULL);
11371         if (ret != I40E_SUCCESS) {
11372                 PMD_DRV_LOG(ERR, "Failed to change mac");
11373                 return -EIO;
11374         }
11375
11376         return 0;
11377 }
11378
11379 static int
11380 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11381 {
11382         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11383         struct rte_eth_dev_data *dev_data = pf->dev_data;
11384         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11385         int ret = 0;
11386
11387         /* check if mtu is within the allowed range */
11388         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11389                 return -EINVAL;
11390
11391         /* mtu setting is forbidden if port is start */
11392         if (dev_data->dev_started) {
11393                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11394                             dev_data->port_id);
11395                 return -EBUSY;
11396         }
11397
11398         if (frame_size > ETHER_MAX_LEN)
11399                 dev_data->dev_conf.rxmode.offloads |=
11400                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11401         else
11402                 dev_data->dev_conf.rxmode.offloads &=
11403                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11404
11405         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11406
11407         return ret;
11408 }
11409
11410 /* Restore ethertype filter */
11411 static void
11412 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11413 {
11414         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11415         struct i40e_ethertype_filter_list
11416                 *ethertype_list = &pf->ethertype.ethertype_list;
11417         struct i40e_ethertype_filter *f;
11418         struct i40e_control_filter_stats stats;
11419         uint16_t flags;
11420
11421         TAILQ_FOREACH(f, ethertype_list, rules) {
11422                 flags = 0;
11423                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11424                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11425                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11426                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11427                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11428
11429                 memset(&stats, 0, sizeof(stats));
11430                 i40e_aq_add_rem_control_packet_filter(hw,
11431                                             f->input.mac_addr.addr_bytes,
11432                                             f->input.ether_type,
11433                                             flags, pf->main_vsi->seid,
11434                                             f->queue, 1, &stats, NULL);
11435         }
11436         PMD_DRV_LOG(INFO, "Ethertype filter:"
11437                     " mac_etype_used = %u, etype_used = %u,"
11438                     " mac_etype_free = %u, etype_free = %u",
11439                     stats.mac_etype_used, stats.etype_used,
11440                     stats.mac_etype_free, stats.etype_free);
11441 }
11442
11443 /* Restore tunnel filter */
11444 static void
11445 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11446 {
11447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11448         struct i40e_vsi *vsi;
11449         struct i40e_pf_vf *vf;
11450         struct i40e_tunnel_filter_list
11451                 *tunnel_list = &pf->tunnel.tunnel_list;
11452         struct i40e_tunnel_filter *f;
11453         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11454         bool big_buffer = 0;
11455
11456         TAILQ_FOREACH(f, tunnel_list, rules) {
11457                 if (!f->is_to_vf)
11458                         vsi = pf->main_vsi;
11459                 else {
11460                         vf = &pf->vfs[f->vf_id];
11461                         vsi = vf->vsi;
11462                 }
11463                 memset(&cld_filter, 0, sizeof(cld_filter));
11464                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11465                         (struct ether_addr *)&cld_filter.element.outer_mac);
11466                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11467                         (struct ether_addr *)&cld_filter.element.inner_mac);
11468                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11469                 cld_filter.element.flags = f->input.flags;
11470                 cld_filter.element.tenant_id = f->input.tenant_id;
11471                 cld_filter.element.queue_number = f->queue;
11472                 rte_memcpy(cld_filter.general_fields,
11473                            f->input.general_fields,
11474                            sizeof(f->input.general_fields));
11475
11476                 if (((f->input.flags &
11477                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11478                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11479                     ((f->input.flags &
11480                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11481                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11482                     ((f->input.flags &
11483                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11484                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11485                         big_buffer = 1;
11486
11487                 if (big_buffer)
11488                         i40e_aq_add_cloud_filters_big_buffer(hw,
11489                                              vsi->seid, &cld_filter, 1);
11490                 else
11491                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11492                                                   &cld_filter.element, 1);
11493         }
11494 }
11495
11496 /* Restore rss filter */
11497 static inline void
11498 i40e_rss_filter_restore(struct i40e_pf *pf)
11499 {
11500         struct i40e_rte_flow_rss_conf *conf =
11501                                         &pf->rss_info;
11502         if (conf->num)
11503                 i40e_config_rss_filter(pf, conf, TRUE);
11504 }
11505
11506 static void
11507 i40e_filter_restore(struct i40e_pf *pf)
11508 {
11509         i40e_ethertype_filter_restore(pf);
11510         i40e_tunnel_filter_restore(pf);
11511         i40e_fdir_filter_restore(pf);
11512         i40e_rss_filter_restore(pf);
11513 }
11514
11515 static bool
11516 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11517 {
11518         if (strcmp(dev->device->driver->name, drv->driver.name))
11519                 return false;
11520
11521         return true;
11522 }
11523
11524 bool
11525 is_i40e_supported(struct rte_eth_dev *dev)
11526 {
11527         return is_device_supported(dev, &rte_i40e_pmd);
11528 }
11529
11530 struct i40e_customized_pctype*
11531 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11532 {
11533         int i;
11534
11535         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11536                 if (pf->customized_pctype[i].index == index)
11537                         return &pf->customized_pctype[i];
11538         }
11539         return NULL;
11540 }
11541
11542 static int
11543 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11544                               uint32_t pkg_size, uint32_t proto_num,
11545                               struct rte_pmd_i40e_proto_info *proto,
11546                               enum rte_pmd_i40e_package_op op)
11547 {
11548         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11549         uint32_t pctype_num;
11550         struct rte_pmd_i40e_ptype_info *pctype;
11551         uint32_t buff_size;
11552         struct i40e_customized_pctype *new_pctype = NULL;
11553         uint8_t proto_id;
11554         uint8_t pctype_value;
11555         char name[64];
11556         uint32_t i, j, n;
11557         int ret;
11558
11559         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11560             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11561                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11562                 return -1;
11563         }
11564
11565         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11566                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11567                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11568         if (ret) {
11569                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11570                 return -1;
11571         }
11572         if (!pctype_num) {
11573                 PMD_DRV_LOG(INFO, "No new pctype added");
11574                 return -1;
11575         }
11576
11577         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11578         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11579         if (!pctype) {
11580                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11581                 return -1;
11582         }
11583         /* get information about new pctype list */
11584         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11585                                         (uint8_t *)pctype, buff_size,
11586                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11587         if (ret) {
11588                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11589                 rte_free(pctype);
11590                 return -1;
11591         }
11592
11593         /* Update customized pctype. */
11594         for (i = 0; i < pctype_num; i++) {
11595                 pctype_value = pctype[i].ptype_id;
11596                 memset(name, 0, sizeof(name));
11597                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11598                         proto_id = pctype[i].protocols[j];
11599                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11600                                 continue;
11601                         for (n = 0; n < proto_num; n++) {
11602                                 if (proto[n].proto_id != proto_id)
11603                                         continue;
11604                                 strcat(name, proto[n].name);
11605                                 strcat(name, "_");
11606                                 break;
11607                         }
11608                 }
11609                 name[strlen(name) - 1] = '\0';
11610                 if (!strcmp(name, "GTPC"))
11611                         new_pctype =
11612                                 i40e_find_customized_pctype(pf,
11613                                                       I40E_CUSTOMIZED_GTPC);
11614                 else if (!strcmp(name, "GTPU_IPV4"))
11615                         new_pctype =
11616                                 i40e_find_customized_pctype(pf,
11617                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11618                 else if (!strcmp(name, "GTPU_IPV6"))
11619                         new_pctype =
11620                                 i40e_find_customized_pctype(pf,
11621                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11622                 else if (!strcmp(name, "GTPU"))
11623                         new_pctype =
11624                                 i40e_find_customized_pctype(pf,
11625                                                       I40E_CUSTOMIZED_GTPU);
11626                 if (new_pctype) {
11627                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11628                                 new_pctype->pctype = pctype_value;
11629                                 new_pctype->valid = true;
11630                         } else {
11631                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11632                                 new_pctype->valid = false;
11633                         }
11634                 }
11635         }
11636
11637         rte_free(pctype);
11638         return 0;
11639 }
11640
11641 static int
11642 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11643                              uint32_t pkg_size, uint32_t proto_num,
11644                              struct rte_pmd_i40e_proto_info *proto,
11645                              enum rte_pmd_i40e_package_op op)
11646 {
11647         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11648         uint16_t port_id = dev->data->port_id;
11649         uint32_t ptype_num;
11650         struct rte_pmd_i40e_ptype_info *ptype;
11651         uint32_t buff_size;
11652         uint8_t proto_id;
11653         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11654         uint32_t i, j, n;
11655         bool in_tunnel;
11656         int ret;
11657
11658         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11659             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11660                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11661                 return -1;
11662         }
11663
11664         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11665                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11666                 return 0;
11667         }
11668
11669         /* get information about new ptype num */
11670         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11671                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11672                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11673         if (ret) {
11674                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11675                 return ret;
11676         }
11677         if (!ptype_num) {
11678                 PMD_DRV_LOG(INFO, "No new ptype added");
11679                 return -1;
11680         }
11681
11682         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11683         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11684         if (!ptype) {
11685                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11686                 return -1;
11687         }
11688
11689         /* get information about new ptype list */
11690         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11691                                         (uint8_t *)ptype, buff_size,
11692                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11693         if (ret) {
11694                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11695                 rte_free(ptype);
11696                 return ret;
11697         }
11698
11699         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11700         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11701         if (!ptype_mapping) {
11702                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11703                 rte_free(ptype);
11704                 return -1;
11705         }
11706
11707         /* Update ptype mapping table. */
11708         for (i = 0; i < ptype_num; i++) {
11709                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11710                 ptype_mapping[i].sw_ptype = 0;
11711                 in_tunnel = false;
11712                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11713                         proto_id = ptype[i].protocols[j];
11714                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11715                                 continue;
11716                         for (n = 0; n < proto_num; n++) {
11717                                 if (proto[n].proto_id != proto_id)
11718                                         continue;
11719                                 memset(name, 0, sizeof(name));
11720                                 strcpy(name, proto[n].name);
11721                                 if (!strncasecmp(name, "PPPOE", 5))
11722                                         ptype_mapping[i].sw_ptype |=
11723                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11724                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11725                                          !in_tunnel) {
11726                                         ptype_mapping[i].sw_ptype |=
11727                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11728                                         ptype_mapping[i].sw_ptype |=
11729                                                 RTE_PTYPE_L4_FRAG;
11730                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11731                                            in_tunnel) {
11732                                         ptype_mapping[i].sw_ptype |=
11733                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11734                                         ptype_mapping[i].sw_ptype |=
11735                                                 RTE_PTYPE_INNER_L4_FRAG;
11736                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11737                                         ptype_mapping[i].sw_ptype |=
11738                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11739                                         in_tunnel = true;
11740                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11741                                            !in_tunnel)
11742                                         ptype_mapping[i].sw_ptype |=
11743                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11744                                 else if (!strncasecmp(name, "IPV4", 4) &&
11745                                          in_tunnel)
11746                                         ptype_mapping[i].sw_ptype |=
11747                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11748                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11749                                          !in_tunnel) {
11750                                         ptype_mapping[i].sw_ptype |=
11751                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11752                                         ptype_mapping[i].sw_ptype |=
11753                                                 RTE_PTYPE_L4_FRAG;
11754                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11755                                            in_tunnel) {
11756                                         ptype_mapping[i].sw_ptype |=
11757                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11758                                         ptype_mapping[i].sw_ptype |=
11759                                                 RTE_PTYPE_INNER_L4_FRAG;
11760                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11761                                         ptype_mapping[i].sw_ptype |=
11762                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11763                                         in_tunnel = true;
11764                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11765                                            !in_tunnel)
11766                                         ptype_mapping[i].sw_ptype |=
11767                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11768                                 else if (!strncasecmp(name, "IPV6", 4) &&
11769                                          in_tunnel)
11770                                         ptype_mapping[i].sw_ptype |=
11771                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11772                                 else if (!strncasecmp(name, "UDP", 3) &&
11773                                          !in_tunnel)
11774                                         ptype_mapping[i].sw_ptype |=
11775                                                 RTE_PTYPE_L4_UDP;
11776                                 else if (!strncasecmp(name, "UDP", 3) &&
11777                                          in_tunnel)
11778                                         ptype_mapping[i].sw_ptype |=
11779                                                 RTE_PTYPE_INNER_L4_UDP;
11780                                 else if (!strncasecmp(name, "TCP", 3) &&
11781                                          !in_tunnel)
11782                                         ptype_mapping[i].sw_ptype |=
11783                                                 RTE_PTYPE_L4_TCP;
11784                                 else if (!strncasecmp(name, "TCP", 3) &&
11785                                          in_tunnel)
11786                                         ptype_mapping[i].sw_ptype |=
11787                                                 RTE_PTYPE_INNER_L4_TCP;
11788                                 else if (!strncasecmp(name, "SCTP", 4) &&
11789                                          !in_tunnel)
11790                                         ptype_mapping[i].sw_ptype |=
11791                                                 RTE_PTYPE_L4_SCTP;
11792                                 else if (!strncasecmp(name, "SCTP", 4) &&
11793                                          in_tunnel)
11794                                         ptype_mapping[i].sw_ptype |=
11795                                                 RTE_PTYPE_INNER_L4_SCTP;
11796                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11797                                           !strncasecmp(name, "ICMPV6", 6)) &&
11798                                          !in_tunnel)
11799                                         ptype_mapping[i].sw_ptype |=
11800                                                 RTE_PTYPE_L4_ICMP;
11801                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11802                                           !strncasecmp(name, "ICMPV6", 6)) &&
11803                                          in_tunnel)
11804                                         ptype_mapping[i].sw_ptype |=
11805                                                 RTE_PTYPE_INNER_L4_ICMP;
11806                                 else if (!strncasecmp(name, "GTPC", 4)) {
11807                                         ptype_mapping[i].sw_ptype |=
11808                                                 RTE_PTYPE_TUNNEL_GTPC;
11809                                         in_tunnel = true;
11810                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11811                                         ptype_mapping[i].sw_ptype |=
11812                                                 RTE_PTYPE_TUNNEL_GTPU;
11813                                         in_tunnel = true;
11814                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11815                                         ptype_mapping[i].sw_ptype |=
11816                                                 RTE_PTYPE_TUNNEL_GRENAT;
11817                                         in_tunnel = true;
11818                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11819                                         ptype_mapping[i].sw_ptype |=
11820                                                 RTE_PTYPE_TUNNEL_L2TP;
11821                                         in_tunnel = true;
11822                                 }
11823
11824                                 break;
11825                         }
11826                 }
11827         }
11828
11829         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11830                                                 ptype_num, 0);
11831         if (ret)
11832                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11833
11834         rte_free(ptype_mapping);
11835         rte_free(ptype);
11836         return ret;
11837 }
11838
11839 void
11840 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11841                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11842 {
11843         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11844         uint32_t proto_num;
11845         struct rte_pmd_i40e_proto_info *proto;
11846         uint32_t buff_size;
11847         uint32_t i;
11848         int ret;
11849
11850         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11851             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11852                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11853                 return;
11854         }
11855
11856         /* get information about protocol number */
11857         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11858                                        (uint8_t *)&proto_num, sizeof(proto_num),
11859                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11860         if (ret) {
11861                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11862                 return;
11863         }
11864         if (!proto_num) {
11865                 PMD_DRV_LOG(INFO, "No new protocol added");
11866                 return;
11867         }
11868
11869         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11870         proto = rte_zmalloc("new_proto", buff_size, 0);
11871         if (!proto) {
11872                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11873                 return;
11874         }
11875
11876         /* get information about protocol list */
11877         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11878                                         (uint8_t *)proto, buff_size,
11879                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11880         if (ret) {
11881                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11882                 rte_free(proto);
11883                 return;
11884         }
11885
11886         /* Check if GTP is supported. */
11887         for (i = 0; i < proto_num; i++) {
11888                 if (!strncmp(proto[i].name, "GTP", 3)) {
11889                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11890                                 pf->gtp_support = true;
11891                         else
11892                                 pf->gtp_support = false;
11893                         break;
11894                 }
11895         }
11896
11897         /* Update customized pctype info */
11898         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11899                                             proto_num, proto, op);
11900         if (ret)
11901                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11902
11903         /* Update customized ptype info */
11904         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11905                                            proto_num, proto, op);
11906         if (ret)
11907                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11908
11909         rte_free(proto);
11910 }
11911
11912 /* Create a QinQ cloud filter
11913  *
11914  * The Fortville NIC has limited resources for tunnel filters,
11915  * so we can only reuse existing filters.
11916  *
11917  * In step 1 we define which Field Vector fields can be used for
11918  * filter types.
11919  * As we do not have the inner tag defined as a field,
11920  * we have to define it first, by reusing one of L1 entries.
11921  *
11922  * In step 2 we are replacing one of existing filter types with
11923  * a new one for QinQ.
11924  * As we reusing L1 and replacing L2, some of the default filter
11925  * types will disappear,which depends on L1 and L2 entries we reuse.
11926  *
11927  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11928  *
11929  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11930  *              later when we define the cloud filter.
11931  *      a.      Valid_flags.replace_cloud = 0
11932  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11933  *      c.      New_filter = 0x10
11934  *      d.      TR bit = 0xff (optional, not used here)
11935  *      e.      Buffer – 2 entries:
11936  *              i.      Byte 0 = 8 (outer vlan FV index).
11937  *                      Byte 1 = 0 (rsv)
11938  *                      Byte 2-3 = 0x0fff
11939  *              ii.     Byte 0 = 37 (inner vlan FV index).
11940  *                      Byte 1 =0 (rsv)
11941  *                      Byte 2-3 = 0x0fff
11942  *
11943  * Step 2:
11944  * 2.   Create cloud filter using two L1 filters entries: stag and
11945  *              new filter(outer vlan+ inner vlan)
11946  *      a.      Valid_flags.replace_cloud = 1
11947  *      b.      Old_filter = 1 (instead of outer IP)
11948  *      c.      New_filter = 0x10
11949  *      d.      Buffer – 2 entries:
11950  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11951  *                      Byte 1-3 = 0 (rsv)
11952  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11953  *                      Byte 9-11 = 0 (rsv)
11954  */
11955 static int
11956 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11957 {
11958         int ret = -ENOTSUP;
11959         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11960         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11961         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11962
11963         if (pf->support_multi_driver) {
11964                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11965                 return ret;
11966         }
11967
11968         /* Init */
11969         memset(&filter_replace, 0,
11970                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11971         memset(&filter_replace_buf, 0,
11972                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11973
11974         /* create L1 filter */
11975         filter_replace.old_filter_type =
11976                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11977         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11978         filter_replace.tr_bit = 0;
11979
11980         /* Prepare the buffer, 2 entries */
11981         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11982         filter_replace_buf.data[0] |=
11983                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11984         /* Field Vector 12b mask */
11985         filter_replace_buf.data[2] = 0xff;
11986         filter_replace_buf.data[3] = 0x0f;
11987         filter_replace_buf.data[4] =
11988                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11989         filter_replace_buf.data[4] |=
11990                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11991         /* Field Vector 12b mask */
11992         filter_replace_buf.data[6] = 0xff;
11993         filter_replace_buf.data[7] = 0x0f;
11994         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11995                         &filter_replace_buf);
11996         if (ret != I40E_SUCCESS)
11997                 return ret;
11998         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11999                     "cloud l1 type is changed from 0x%x to 0x%x",
12000                     filter_replace.old_filter_type,
12001                     filter_replace.new_filter_type);
12002
12003         /* Apply the second L2 cloud filter */
12004         memset(&filter_replace, 0,
12005                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12006         memset(&filter_replace_buf, 0,
12007                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12008
12009         /* create L2 filter, input for L2 filter will be L1 filter  */
12010         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12011         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12012         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12013
12014         /* Prepare the buffer, 2 entries */
12015         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12016         filter_replace_buf.data[0] |=
12017                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12018         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12019         filter_replace_buf.data[4] |=
12020                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12021         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12022                         &filter_replace_buf);
12023         if (!ret) {
12024                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12025                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12026                             "cloud filter type is changed from 0x%x to 0x%x",
12027                             filter_replace.old_filter_type,
12028                             filter_replace.new_filter_type);
12029         }
12030         return ret;
12031 }
12032
12033 int
12034 i40e_config_rss_filter(struct i40e_pf *pf,
12035                 struct i40e_rte_flow_rss_conf *conf, bool add)
12036 {
12037         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12038         uint32_t i, lut = 0;
12039         uint16_t j, num;
12040         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
12041         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12042
12043         if (!add) {
12044                 if (memcmp(conf, rss_info,
12045                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
12046                         i40e_pf_disable_rss(pf);
12047                         memset(rss_info, 0,
12048                                 sizeof(struct i40e_rte_flow_rss_conf));
12049                         return 0;
12050                 }
12051                 return -EINVAL;
12052         }
12053
12054         if (rss_info->num)
12055                 return -EINVAL;
12056
12057         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12058          * It's necessary to calculate the actual PF queues that are configured.
12059          */
12060         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12061                 num = i40e_pf_calc_configured_queues_num(pf);
12062         else
12063                 num = pf->dev_data->nb_rx_queues;
12064
12065         num = RTE_MIN(num, conf->num);
12066         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12067                         num);
12068
12069         if (num == 0) {
12070                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12071                 return -ENOTSUP;
12072         }
12073
12074         /* Fill in redirection table */
12075         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12076                 if (j == num)
12077                         j = 0;
12078                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
12079                         hw->func_caps.rss_table_entry_width) - 1));
12080                 if ((i & 3) == 3)
12081                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12082         }
12083
12084         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12085                 i40e_pf_disable_rss(pf);
12086                 return 0;
12087         }
12088         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12089                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12090                 /* Random default keys */
12091                 static uint32_t rss_key_default[] = {0x6b793944,
12092                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12093                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12094                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12095
12096                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12097                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12098                                                         sizeof(uint32_t);
12099         }
12100
12101         i40e_hw_rss_hash_set(pf, &rss_conf);
12102
12103         rte_memcpy(rss_info,
12104                 conf, sizeof(struct i40e_rte_flow_rss_conf));
12105
12106         return 0;
12107 }
12108
12109 RTE_INIT(i40e_init_log);
12110 static void
12111 i40e_init_log(void)
12112 {
12113         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12114         if (i40e_logtype_init >= 0)
12115                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12116         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12117         if (i40e_logtype_driver >= 0)
12118                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12119 }
12120
12121 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12122                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12123                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");