drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 458 #include "rte_pci_dev_ids.h"
 459 { .vendor_id = 0, /* sentinel */ },
 460 };
 461
 462 static const struct eth_dev_ops i40e_eth_dev_ops = {
 463         .dev_configure                = i40e_dev_configure,
 464         .dev_start                    = i40e_dev_start,
 465         .dev_stop                     = i40e_dev_stop,
 466         .dev_close                    = i40e_dev_close,
 467         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 468         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 469         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 470         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 471         .dev_set_link_up              = i40e_dev_set_link_up,
 472         .dev_set_link_down            = i40e_dev_set_link_down,
 473         .link_update                  = i40e_dev_link_update,
 474         .stats_get                    = i40e_dev_stats_get,
 475         .xstats_get                   = i40e_dev_xstats_get,
 476         .xstats_get_names             = i40e_dev_xstats_get_names,
 477         .stats_reset                  = i40e_dev_stats_reset,
 478         .xstats_reset                 = i40e_dev_stats_reset,
 479         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 480         .dev_infos_get                = i40e_dev_info_get,
 481         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 482         .vlan_filter_set              = i40e_vlan_filter_set,
 483         .vlan_tpid_set                = i40e_vlan_tpid_set,
 484         .vlan_offload_set             = i40e_vlan_offload_set,
 485         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 486         .vlan_pvid_set                = i40e_vlan_pvid_set,
 487         .rx_queue_start               = i40e_dev_rx_queue_start,
 488         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 489         .tx_queue_start               = i40e_dev_tx_queue_start,
 490         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 491         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 492         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 493         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 494         .rx_queue_release             = i40e_dev_rx_queue_release,
 495         .rx_queue_count               = i40e_dev_rx_queue_count,
 496         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 497         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 498         .tx_queue_release             = i40e_dev_tx_queue_release,
 499         .dev_led_on                   = i40e_dev_led_on,
 500         .dev_led_off                  = i40e_dev_led_off,
 501         .flow_ctrl_get                = i40e_flow_ctrl_get,
 502         .flow_ctrl_set                = i40e_flow_ctrl_set,
 503         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 504         .mac_addr_add                 = i40e_macaddr_add,
 505         .mac_addr_remove              = i40e_macaddr_remove,
 506         .reta_update                  = i40e_dev_rss_reta_update,
 507         .reta_query                   = i40e_dev_rss_reta_query,
 508         .rss_hash_update              = i40e_dev_rss_hash_update,
 509         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 510         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 511         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 512         .filter_ctrl                  = i40e_dev_filter_ctrl,
 513         .rxq_info_get                 = i40e_rxq_info_get,
 514         .txq_info_get                 = i40e_txq_info_get,
 515         .mirror_rule_set              = i40e_mirror_rule_set,
 516         .mirror_rule_reset            = i40e_mirror_rule_reset,
 517         .timesync_enable              = i40e_timesync_enable,
 518         .timesync_disable             = i40e_timesync_disable,
 519         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 520         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 521         .get_dcb_info                 = i40e_dev_get_dcb_info,
 522         .timesync_adjust_time         = i40e_timesync_adjust_time,
 523         .timesync_read_time           = i40e_timesync_read_time,
 524         .timesync_write_time          = i40e_timesync_write_time,
 525         .get_reg                      = i40e_get_regs,
 526         .get_eeprom_length            = i40e_get_eeprom_length,
 527         .get_eeprom                   = i40e_get_eeprom,
 528         .mac_addr_set                 = i40e_set_default_mac_addr,
 529         .mtu_set                      = i40e_dev_mtu_set,
 530 };
 531
 532 /* store statistics names and its offset in stats structure */
 533 struct rte_i40e_xstats_name_off {
 534         char name[RTE_ETH_XSTATS_NAME_SIZE];
 535         unsigned offset;
 536 };
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 539         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 540         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 541         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 542         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 543         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 544                 rx_unknown_protocol)},
 545         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 546         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 547         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 548         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 549 };
 550
 551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 552                 sizeof(rte_i40e_stats_strings[0]))
 553
 554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 555         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 556                 tx_dropped_link_down)},
 557         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 558         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 559                 illegal_bytes)},
 560         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 561         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_local_faults)},
 563         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 564                 mac_remote_faults)},
 565         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 566                 rx_length_errors)},
 567         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 568         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 569         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 570         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 571         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 572         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_127)},
 574         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_255)},
 576         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_511)},
 578         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1023)},
 580         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_1522)},
 582         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 583                 rx_size_big)},
 584         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_undersize)},
 586         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 587                 rx_oversize)},
 588         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 589                 mac_short_packet_dropped)},
 590         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 591                 rx_fragments)},
 592         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 593         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 594         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_127)},
 596         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_255)},
 598         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_511)},
 600         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1023)},
 602         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_1522)},
 604         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 605                 tx_size_big)},
 606         {"rx_flow_director_atr_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 608         {"rx_flow_director_sb_match_packets",
 609                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 610         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 tx_lpi_status)},
 612         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 613                 rx_lpi_status)},
 614         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 tx_lpi_count)},
 616         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 617                 rx_lpi_count)},
 618 };
 619
 620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 621                 sizeof(rte_i40e_hw_port_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_rx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_rx)},
 628 };
 629
 630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 631                 sizeof(rte_i40e_rxq_prio_strings[0]))
 632
 633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 634         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xon_tx)},
 636         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xoff_tx)},
 638         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 639                 priority_xon_2_xoff)},
 640 };
 641
 642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 643                 sizeof(rte_i40e_txq_prio_strings[0]))
 644
 645 static struct eth_driver rte_i40e_pmd = {
 646         .pci_drv = {
 647                 .name = "rte_i40e_pmd",
 648                 .id_table = pci_id_i40e_map,
 649                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 650                         RTE_PCI_DRV_DETACHABLE,
 651         },
 652         .eth_dev_init = eth_i40e_dev_init,
 653         .eth_dev_uninit = eth_i40e_dev_uninit,
 654         .dev_private_size = sizeof(struct i40e_adapter),
 655 };
 656
 657 static inline int
 658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 659                                      struct rte_eth_link *link)
 660 {
 661         struct rte_eth_link *dst = link;
 662         struct rte_eth_link *src = &(dev->data->dev_link);
 663
 664         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 665                                         *(uint64_t *)src) == 0)
 666                 return -1;
 667
 668         return 0;
 669 }
 670
 671 static inline int
 672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                       struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * Driver initialization routine.
 687  * Invoked once at EAL init time.
 688  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 689  */
 690 static int
 691 rte_i40e_pmd_init(const char *name __rte_unused,
 692                   const char *params __rte_unused)
 693 {
 694         PMD_INIT_FUNC_TRACE();
 695         rte_eth_driver_register(&rte_i40e_pmd);
 696
 697         return 0;
 698 }
 699
 700 static struct rte_driver rte_i40e_driver = {
 701         .type = PMD_PDEV,
 702         .init = rte_i40e_pmd_init,
 703 };
 704
 705 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
 706 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
 707
 708 /*
 709  * Initialize registers for flexible payload, which should be set by NVM.
 710  * This should be removed from code once it is fixed in NVM.
 711  */
 712 #ifndef I40E_GLQF_ORT
 713 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 714 #endif
 715 #ifndef I40E_GLQF_PIT
 716 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 717 #endif
 718
 719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 720 {
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731
 732         /* GLQF_PIT Registers */
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 734         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 735 }
 736
 737 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 738
 739 /*
 740  * Add a ethertype filter to drop all flow control frames transmitted
 741  * from VSIs.
 742 */
 743 static void
 744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 745 {
 746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 747         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 749                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 750         int ret;
 751
 752         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 753                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 754                                 pf->main_vsi_seid, 0,
 755                                 TRUE, NULL, NULL);
 756         if (ret)
 757                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 758                                   " frames from VSIs.");
 759 }
 760
 761 static int
 762 floating_veb_list_handler(__rte_unused const char *key,
 763                           const char *floating_veb_value,
 764                           void *opaque)
 765 {
 766         int idx = 0;
 767         unsigned int count = 0;
 768         char *end = NULL;
 769         int min, max;
 770         bool *vf_floating_veb = opaque;
 771
 772         while (isblank(*floating_veb_value))
 773                 floating_veb_value++;
 774
 775         /* Reset floating VEB configuration for VFs */
 776         for (idx = 0; idx < I40E_MAX_VF; idx++)
 777                 vf_floating_veb[idx] = false;
 778
 779         min = I40E_MAX_VF;
 780         do {
 781                 while (isblank(*floating_veb_value))
 782                         floating_veb_value++;
 783                 if (*floating_veb_value == '\0')
 784                         return -1;
 785                 errno = 0;
 786                 idx = strtoul(floating_veb_value, &end, 10);
 787                 if (errno || end == NULL)
 788                         return -1;
 789                 while (isblank(*end))
 790                         end++;
 791                 if (*end == '-') {
 792                         min = idx;
 793                 } else if ((*end == ';') || (*end == '\0')) {
 794                         max = idx;
 795                         if (min == I40E_MAX_VF)
 796                                 min = idx;
 797                         if (max >= I40E_MAX_VF)
 798                                 max = I40E_MAX_VF - 1;
 799                         for (idx = min; idx <= max; idx++) {
 800                                 vf_floating_veb[idx] = true;
 801                                 count++;
 802                         }
 803                         min = I40E_MAX_VF;
 804                 } else {
 805                         return -1;
 806                 }
 807                 floating_veb_value = end + 1;
 808         } while (*end != '\0');
 809
 810         if (count == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static void
 817 config_vf_floating_veb(struct rte_devargs *devargs,
 818                        uint16_t floating_veb,
 819                        bool *vf_floating_veb)
 820 {
 821         struct rte_kvargs *kvlist;
 822         int i;
 823         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 824
 825         if (!floating_veb)
 826                 return;
 827         /* All the VFs attach to the floating VEB by default
 828          * when the floating VEB is enabled.
 829          */
 830         for (i = 0; i < I40E_MAX_VF; i++)
 831                 vf_floating_veb[i] = true;
 832
 833         if (devargs == NULL)
 834                 return;
 835
 836         kvlist = rte_kvargs_parse(devargs->args, NULL);
 837         if (kvlist == NULL)
 838                 return;
 839
 840         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         /* When the floating_veb_list parameter exists, all the VFs
 845          * will attach to the legacy VEB firstly, then configure VFs
 846          * to the floating VEB according to the floating_veb_list.
 847          */
 848         if (rte_kvargs_process(kvlist, floating_veb_list,
 849                                floating_veb_list_handler,
 850                                vf_floating_veb) < 0) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         rte_kvargs_free(kvlist);
 855 }
 856
 857 static int
 858 i40e_check_floating_handler(__rte_unused const char *key,
 859                             const char *value,
 860                             __rte_unused void *opaque)
 861 {
 862         if (strcmp(value, "1"))
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 static int
 869 is_floating_veb_supported(struct rte_devargs *devargs)
 870 {
 871         struct rte_kvargs *kvlist;
 872         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 873
 874         if (devargs == NULL)
 875                 return 0;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, NULL);
 878         if (kvlist == NULL)
 879                 return 0;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 882                 rte_kvargs_free(kvlist);
 883                 return 0;
 884         }
 885         /* Floating VEB is enabled when there's key-value:
 886          * enable_floating_veb=1
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_key,
 889                                i40e_check_floating_handler, NULL) < 0) {
 890                 rte_kvargs_free(kvlist);
 891                 return 0;
 892         }
 893         rte_kvargs_free(kvlist);
 894
 895         return 1;
 896 }
 897
 898 static void
 899 config_floating_veb(struct rte_eth_dev *dev)
 900 {
 901         struct rte_pci_device *pci_dev = dev->pci_dev;
 902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 904
 905         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 906
 907         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 908                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 909                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 910                                        pf->floating_veb_list);
 911         } else {
 912                 pf->floating_veb = false;
 913         }
 914 }
 915
 916 static int
 917 eth_i40e_dev_init(struct rte_eth_dev *dev)
 918 {
 919         struct rte_pci_device *pci_dev;
 920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 922         struct i40e_vsi *vsi;
 923         int ret;
 924         uint32_t len;
 925         uint8_t aq_fail = 0;
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         dev->dev_ops = &i40e_eth_dev_ops;
 930         dev->rx_pkt_burst = i40e_recv_pkts;
 931         dev->tx_pkt_burst = i40e_xmit_pkts;
 932
 933         /* for secondary processes, we don't initialise any further as primary
 934          * has already done this work. Only check we don't need a different
 935          * RX function */
 936         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 937                 i40e_set_rx_function(dev);
 938                 i40e_set_tx_function(dev);
 939                 return 0;
 940         }
 941         pci_dev = dev->pci_dev;
 942
 943         rte_eth_copy_pci_info(dev, pci_dev);
 944
 945         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 946         pf->adapter->eth_dev = dev;
 947         pf->dev_data = dev->data;
 948
 949         hw->back = I40E_PF_TO_ADAPTER(pf);
 950         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 951         if (!hw->hw_addr) {
 952                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 953                              "as address is NULL");
 954                 return -ENODEV;
 955         }
 956
 957         hw->vendor_id = pci_dev->id.vendor_id;
 958         hw->device_id = pci_dev->id.device_id;
 959         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 960         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 961         hw->bus.device = pci_dev->addr.devid;
 962         hw->bus.func = pci_dev->addr.function;
 963         hw->adapter_stopped = 0;
 964
 965         /* Make sure all is clean before doing PF reset */
 966         i40e_clear_hw(hw);
 967
 968         /* Initialize the hardware */
 969         i40e_hw_init(dev);
 970
 971         /* Reset here to make sure all is clean for each PF */
 972         ret = i40e_pf_reset(hw);
 973         if (ret) {
 974                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 975                 return ret;
 976         }
 977
 978         /* Initialize the shared code (base driver) */
 979         ret = i40e_init_shared_code(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 982                 return ret;
 983         }
 984
 985         /*
 986          * To work around the NVM issue,initialize registers
 987          * for flexible payload by software.
 988          * It should be removed once issues are fixed in NVM.
 989          */
 990         i40e_flex_payload_reg_init(hw);
 991
 992         /* Initialize the input set for filters (hash and fd) to default value */
 993         i40e_filter_input_set_init(pf);
 994
 995         /* Initialize the parameters for adminq */
 996         i40e_init_adminq_parameter(hw);
 997         ret = i40e_init_adminq(hw);
 998         if (ret != I40E_SUCCESS) {
 999                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1000                 return -EIO;
1001         }
1002         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1003                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1004                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1005                      ((hw->nvm.version >> 12) & 0xf),
1006                      ((hw->nvm.version >> 4) & 0xff),
1007                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1008
1009         /* Need the special FW version to support floating VEB */
1010         config_floating_veb(dev);
1011         /* Clear PXE mode */
1012         i40e_clear_pxe_mode(hw);
1013
1014         /*
1015          * On X710, performance number is far from the expectation on recent
1016          * firmware versions. The fix for this issue may not be integrated in
1017          * the following firmware version. So the workaround in software driver
1018          * is needed. It needs to modify the initial values of 3 internal only
1019          * registers. Note that the workaround can be removed when it is fixed
1020          * in firmware in the future.
1021          */
1022         i40e_configure_registers(hw);
1023
1024         /* Get hw capabilities */
1025         ret = i40e_get_cap(hw);
1026         if (ret != I40E_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1028                 goto err_get_capabilities;
1029         }
1030
1031         /* Initialize parameters for PF */
1032         ret = i40e_pf_parameter_init(dev);
1033         if (ret != 0) {
1034                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1035                 goto err_parameter_init;
1036         }
1037
1038         /* Initialize the queue management */
1039         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1040         if (ret < 0) {
1041                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1042                 goto err_qp_pool_init;
1043         }
1044         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1045                                 hw->func_caps.num_msix_vectors - 1);
1046         if (ret < 0) {
1047                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1048                 goto err_msix_pool_init;
1049         }
1050
1051         /* Initialize lan hmc */
1052         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1053                                 hw->func_caps.num_rx_qp, 0, 0);
1054         if (ret != I40E_SUCCESS) {
1055                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1056                 goto err_init_lan_hmc;
1057         }
1058
1059         /* Configure lan hmc */
1060         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1061         if (ret != I40E_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1063                 goto err_configure_lan_hmc;
1064         }
1065
1066         /* Get and check the mac address */
1067         i40e_get_mac_addr(hw, hw->mac.addr);
1068         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1069                 PMD_INIT_LOG(ERR, "mac address is not valid");
1070                 ret = -EIO;
1071                 goto err_get_mac_addr;
1072         }
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1075                         (struct ether_addr *) hw->mac.perm_addr);
1076
1077         /* Disable flow control */
1078         hw->fc.requested_mode = I40E_FC_NONE;
1079         i40e_set_fc(hw, &aq_fail, TRUE);
1080
1081         /* Set the global registers with default ether type value */
1082         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1085                              "VLAN ether type");
1086                 goto err_setup_pf_switch;
1087         }
1088
1089         /* PF setup, which includes VSI setup */
1090         ret = i40e_pf_setup(pf);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1093                 goto err_setup_pf_switch;
1094         }
1095
1096         /* reset all stats of the device, including pf and main vsi */
1097         i40e_dev_stats_reset(dev);
1098
1099         vsi = pf->main_vsi;
1100
1101         /* Disable double vlan by default */
1102         i40e_vsi_config_double_vlan(vsi, FALSE);
1103
1104         if (!vsi->max_macaddrs)
1105                 len = ETHER_ADDR_LEN;
1106         else
1107                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1108
1109         /* Should be after VSI initialized */
1110         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1111         if (!dev->data->mac_addrs) {
1112                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1113                                         "for storing mac address");
1114                 goto err_mac_alloc;
1115         }
1116         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1117                                         &dev->data->mac_addrs[0]);
1118
1119         /* initialize pf host driver to setup SRIOV resource if applicable */
1120         i40e_pf_host_init(dev);
1121
1122         /* register callback func to eal lib */
1123         rte_intr_callback_register(&(pci_dev->intr_handle),
1124                 i40e_dev_interrupt_handler, (void *)dev);
1125
1126         /* configure and enable device interrupt */
1127         i40e_pf_config_irq0(hw, TRUE);
1128         i40e_pf_enable_irq0(hw);
1129
1130         /* enable uio intr after callback register */
1131         rte_intr_enable(&(pci_dev->intr_handle));
1132         /*
1133          * Add an ethertype filter to drop all flow control frames transmitted
1134          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1135          * frames to wire.
1136          */
1137         i40e_add_tx_flow_control_drop_filter(pf);
1138
1139         /* Set the max frame size to 0x2600 by default,
1140          * in case other drivers changed the default value.
1141          */
1142         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1143
1144         /* initialize mirror rule list */
1145         TAILQ_INIT(&pf->mirror_list);
1146
1147         /* Init dcb to sw mode by default */
1148         ret = i40e_dcb_init_configure(dev, TRUE);
1149         if (ret != I40E_SUCCESS) {
1150                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1151                 pf->flags &= ~I40E_FLAG_DCB;
1152         }
1153
1154         return 0;
1155
1156 err_mac_alloc:
1157         i40e_vsi_release(pf->main_vsi);
1158 err_setup_pf_switch:
1159 err_get_mac_addr:
1160 err_configure_lan_hmc:
1161         (void)i40e_shutdown_lan_hmc(hw);
1162 err_init_lan_hmc:
1163         i40e_res_pool_destroy(&pf->msix_pool);
1164 err_msix_pool_init:
1165         i40e_res_pool_destroy(&pf->qp_pool);
1166 err_qp_pool_init:
1167 err_parameter_init:
1168 err_get_capabilities:
1169         (void)i40e_shutdown_adminq(hw);
1170
1171         return ret;
1172 }
1173
1174 static int
1175 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1176 {
1177         struct rte_pci_device *pci_dev;
1178         struct i40e_hw *hw;
1179         struct i40e_filter_control_settings settings;
1180         int ret;
1181         uint8_t aq_fail = 0;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1186                 return 0;
1187
1188         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189         pci_dev = dev->pci_dev;
1190
1191         if (hw->adapter_stopped == 0)
1192                 i40e_dev_close(dev);
1193
1194         dev->dev_ops = NULL;
1195         dev->rx_pkt_burst = NULL;
1196         dev->tx_pkt_burst = NULL;
1197
1198         /* Disable LLDP */
1199         ret = i40e_aq_stop_lldp(hw, true, NULL);
1200         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1201                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1202
1203         /* Clear PXE mode */
1204         i40e_clear_pxe_mode(hw);
1205
1206         /* Unconfigure filter control */
1207         memset(&settings, 0, sizeof(settings));
1208         ret = i40e_set_filter_control(hw, &settings);
1209         if (ret)
1210                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1211                                         ret);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* uninitialize pf host driver */
1218         i40e_pf_host_uninit(dev);
1219
1220         rte_free(dev->data->mac_addrs);
1221         dev->data->mac_addrs = NULL;
1222
1223         /* disable uio intr before callback unregister */
1224         rte_intr_disable(&(pci_dev->intr_handle));
1225
1226         /* register callback func to eal lib */
1227         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1228                 i40e_dev_interrupt_handler, (void *)dev);
1229
1230         return 0;
1231 }
1232
1233 static int
1234 i40e_dev_configure(struct rte_eth_dev *dev)
1235 {
1236         struct i40e_adapter *ad =
1237                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1239         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1240         int i, ret;
1241
1242         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1243          * bulk allocation or vector Rx preconditions we will reset it.
1244          */
1245         ad->rx_bulk_alloc_allowed = true;
1246         ad->rx_vec_allowed = true;
1247         ad->tx_simple_allowed = true;
1248         ad->tx_vec_allowed = true;
1249
1250         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1251                 ret = i40e_fdir_setup(pf);
1252                 if (ret != I40E_SUCCESS) {
1253                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1254                         return -ENOTSUP;
1255                 }
1256                 ret = i40e_fdir_configure(dev);
1257                 if (ret < 0) {
1258                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1259                         goto err;
1260                 }
1261         } else
1262                 i40e_fdir_teardown(pf);
1263
1264         ret = i40e_dev_init_vlan(dev);
1265         if (ret < 0)
1266                 goto err;
1267
1268         /* VMDQ setup.
1269          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1270          *  RSS setting have different requirements.
1271          *  General PMD driver call sequence are NIC init, configure,
1272          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1273          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1274          *  applicable. So, VMDQ setting has to be done before
1275          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1276          *  For RSS setting, it will try to calculate actual configured RX queue
1277          *  number, which will be available after rx_queue_setup(). dev_start()
1278          *  function is good to place RSS setup.
1279          */
1280         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1281                 ret = i40e_vmdq_setup(dev);
1282                 if (ret)
1283                         goto err;
1284         }
1285
1286         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1287                 ret = i40e_dcb_setup(dev);
1288                 if (ret) {
1289                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1290                         goto err_dcb;
1291                 }
1292         }
1293
1294         return 0;
1295
1296 err_dcb:
1297         /* need to release vmdq resource if exists */
1298         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1299                 i40e_vsi_release(pf->vmdq[i].vsi);
1300                 pf->vmdq[i].vsi = NULL;
1301         }
1302         rte_free(pf->vmdq);
1303         pf->vmdq = NULL;
1304 err:
1305         /* need to release fdir resource if exists */
1306         i40e_fdir_teardown(pf);
1307         return ret;
1308 }
1309
1310 void
1311 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1312 {
1313         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1314         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1315         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1316         uint16_t msix_vect = vsi->msix_intr;
1317         uint16_t i;
1318
1319         for (i = 0; i < vsi->nb_qps; i++) {
1320                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1321                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1322                 rte_wmb();
1323         }
1324
1325         if (vsi->type != I40E_VSI_SRIOV) {
1326                 if (!rte_intr_allow_others(intr_handle)) {
1327                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1328                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1329                         I40E_WRITE_REG(hw,
1330                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1331                                        0);
1332                 } else {
1333                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1334                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1335                         I40E_WRITE_REG(hw,
1336                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1337                                                        msix_vect - 1), 0);
1338                 }
1339         } else {
1340                 uint32_t reg;
1341                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1342                         vsi->user_param + (msix_vect - 1);
1343
1344                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1345                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1346         }
1347         I40E_WRITE_FLUSH(hw);
1348 }
1349
1350 static void
1351 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1352                        int base_queue, int nb_queue)
1353 {
1354         int i;
1355         uint32_t val;
1356         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1357
1358         /* Bind all RX queues to allocated MSIX interrupt */
1359         for (i = 0; i < nb_queue; i++) {
1360                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1361                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1362                         ((base_queue + i + 1) <<
1363                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1364                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1365                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1366
1367                 if (i == nb_queue - 1)
1368                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1369                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1370         }
1371
1372         /* Write first RX queue to Link list register as the head element */
1373         if (vsi->type != I40E_VSI_SRIOV) {
1374                 uint16_t interval =
1375                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1376
1377                 if (msix_vect == I40E_MISC_VEC_ID) {
1378                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1379                                        (base_queue <<
1380                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1381                                        (0x0 <<
1382                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1383                         I40E_WRITE_REG(hw,
1384                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1385                                        interval);
1386                 } else {
1387                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1388                                        (base_queue <<
1389                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1390                                        (0x0 <<
1391                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1392                         I40E_WRITE_REG(hw,
1393                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1394                                                        msix_vect - 1),
1395                                        interval);
1396                 }
1397         } else {
1398                 uint32_t reg;
1399
1400                 if (msix_vect == I40E_MISC_VEC_ID) {
1401                         I40E_WRITE_REG(hw,
1402                                        I40E_VPINT_LNKLST0(vsi->user_param),
1403                                        (base_queue <<
1404                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1407                 } else {
1408                         /* num_msix_vectors_vf needs to minus irq0 */
1409                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1410                                 vsi->user_param + (msix_vect - 1);
1411
1412                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1413                                        (base_queue <<
1414                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417                 }
1418         }
1419
1420         I40E_WRITE_FLUSH(hw);
1421 }
1422
1423 void
1424 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1425 {
1426         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1427         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1429         uint16_t msix_vect = vsi->msix_intr;
1430         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1431         uint16_t queue_idx = 0;
1432         int record = 0;
1433         uint32_t val;
1434         int i;
1435
1436         for (i = 0; i < vsi->nb_qps; i++) {
1437                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1438                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1439         }
1440
1441         /* INTENA flag is not auto-cleared for interrupt */
1442         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1443         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1444                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1445                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1446         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1447
1448         /* VF bind interrupt */
1449         if (vsi->type == I40E_VSI_SRIOV) {
1450                 __vsi_queues_bind_intr(vsi, msix_vect,
1451                                        vsi->base_queue, vsi->nb_qps);
1452                 return;
1453         }
1454
1455         /* PF & VMDq bind interrupt */
1456         if (rte_intr_dp_is_en(intr_handle)) {
1457                 if (vsi->type == I40E_VSI_MAIN) {
1458                         queue_idx = 0;
1459                         record = 1;
1460                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1461                         struct i40e_vsi *main_vsi =
1462                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1463                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1464                         record = 1;
1465                 }
1466         }
1467
1468         for (i = 0; i < vsi->nb_used_qps; i++) {
1469                 if (nb_msix <= 1) {
1470                         if (!rte_intr_allow_others(intr_handle))
1471                                 /* allow to share MISC_VEC_ID */
1472                                 msix_vect = I40E_MISC_VEC_ID;
1473
1474                         /* no enough msix_vect, map all to one */
1475                         __vsi_queues_bind_intr(vsi, msix_vect,
1476                                                vsi->base_queue + i,
1477                                                vsi->nb_used_qps - i);
1478                         for (; !!record && i < vsi->nb_used_qps; i++)
1479                                 intr_handle->intr_vec[queue_idx + i] =
1480                                         msix_vect;
1481                         break;
1482                 }
1483                 /* 1:1 queue/msix_vect mapping */
1484                 __vsi_queues_bind_intr(vsi, msix_vect,
1485                                        vsi->base_queue + i, 1);
1486                 if (!!record)
1487                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1488
1489                 msix_vect++;
1490                 nb_msix--;
1491         }
1492 }
1493
1494 static void
1495 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1496 {
1497         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1498         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1500         uint16_t interval = i40e_calc_itr_interval(\
1501                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1502         uint16_t msix_intr, i;
1503
1504         if (rte_intr_allow_others(intr_handle))
1505                 for (i = 0; i < vsi->nb_msix; i++) {
1506                         msix_intr = vsi->msix_intr + i;
1507                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1508                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1509                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1510                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1511                                 (interval <<
1512                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1513                 }
1514         else
1515                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1516                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1517                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1518                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1519                                (interval <<
1520                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1521
1522         I40E_WRITE_FLUSH(hw);
1523 }
1524
1525 static void
1526 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1530         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1531         uint16_t msix_intr, i;
1532
1533         if (rte_intr_allow_others(intr_handle))
1534                 for (i = 0; i < vsi->nb_msix; i++) {
1535                         msix_intr = vsi->msix_intr + i;
1536                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1537                                        0);
1538                 }
1539         else
1540                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1541
1542         I40E_WRITE_FLUSH(hw);
1543 }
1544
1545 static inline uint8_t
1546 i40e_parse_link_speeds(uint16_t link_speeds)
1547 {
1548         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1549
1550         if (link_speeds & ETH_LINK_SPEED_40G)
1551                 link_speed |= I40E_LINK_SPEED_40GB;
1552         if (link_speeds & ETH_LINK_SPEED_20G)
1553                 link_speed |= I40E_LINK_SPEED_20GB;
1554         if (link_speeds & ETH_LINK_SPEED_10G)
1555                 link_speed |= I40E_LINK_SPEED_10GB;
1556         if (link_speeds & ETH_LINK_SPEED_1G)
1557                 link_speed |= I40E_LINK_SPEED_1GB;
1558         if (link_speeds & ETH_LINK_SPEED_100M)
1559                 link_speed |= I40E_LINK_SPEED_100MB;
1560
1561         return link_speed;
1562 }
1563
1564 static int
1565 i40e_phy_conf_link(struct i40e_hw *hw,
1566                    uint8_t abilities,
1567                    uint8_t force_speed)
1568 {
1569         enum i40e_status_code status;
1570         struct i40e_aq_get_phy_abilities_resp phy_ab;
1571         struct i40e_aq_set_phy_config phy_conf;
1572         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1573                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1574                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1575                         I40E_AQ_PHY_FLAG_LOW_POWER;
1576         const uint8_t advt = I40E_LINK_SPEED_40GB |
1577                         I40E_LINK_SPEED_10GB |
1578                         I40E_LINK_SPEED_1GB |
1579                         I40E_LINK_SPEED_100MB;
1580         int ret = -ENOTSUP;
1581
1582
1583         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1584                                               NULL);
1585         if (status)
1586                 return ret;
1587
1588         memset(&phy_conf, 0, sizeof(phy_conf));
1589
1590         /* bits 0-2 use the values from get_phy_abilities_resp */
1591         abilities &= ~mask;
1592         abilities |= phy_ab.abilities & mask;
1593
1594         /* update ablities and speed */
1595         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1596                 phy_conf.link_speed = advt;
1597         else
1598                 phy_conf.link_speed = force_speed;
1599
1600         phy_conf.abilities = abilities;
1601
1602         /* use get_phy_abilities_resp value for the rest */
1603         phy_conf.phy_type = phy_ab.phy_type;
1604         phy_conf.eee_capability = phy_ab.eee_capability;
1605         phy_conf.eeer = phy_ab.eeer_val;
1606         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1607
1608         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1609                     phy_ab.abilities, phy_ab.link_speed);
1610         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1611                     phy_conf.abilities, phy_conf.link_speed);
1612
1613         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1614         if (status)
1615                 return ret;
1616
1617         return I40E_SUCCESS;
1618 }
1619
1620 static int
1621 i40e_apply_link_speed(struct rte_eth_dev *dev)
1622 {
1623         uint8_t speed;
1624         uint8_t abilities = 0;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         struct rte_eth_conf *conf = &dev->data->dev_conf;
1627
1628         speed = i40e_parse_link_speeds(conf->link_speeds);
1629         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1630         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1631                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1632         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1633
1634         /* Skip changing speed on 40G interfaces, FW does not support */
1635         if (i40e_is_40G_device(hw->device_id)) {
1636                 speed =  I40E_LINK_SPEED_UNKNOWN;
1637                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1638         }
1639
1640         return i40e_phy_conf_link(hw, abilities, speed);
1641 }
1642
1643 static int
1644 i40e_dev_start(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct i40e_vsi *main_vsi = pf->main_vsi;
1649         int ret, i;
1650         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1651         uint32_t intr_vector = 0;
1652
1653         hw->adapter_stopped = 0;
1654
1655         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1656                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1657                              dev->data->port_id);
1658                 return -EINVAL;
1659         }
1660
1661         rte_intr_disable(intr_handle);
1662
1663         if ((rte_intr_cap_multiple(intr_handle) ||
1664              !RTE_ETH_DEV_SRIOV(dev).active) &&
1665             dev->data->dev_conf.intr_conf.rxq != 0) {
1666                 intr_vector = dev->data->nb_rx_queues;
1667                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1668                         return -1;
1669         }
1670
1671         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1672                 intr_handle->intr_vec =
1673                         rte_zmalloc("intr_vec",
1674                                     dev->data->nb_rx_queues * sizeof(int),
1675                                     0);
1676                 if (!intr_handle->intr_vec) {
1677                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1678                                      " intr_vec\n", dev->data->nb_rx_queues);
1679                         return -ENOMEM;
1680                 }
1681         }
1682
1683         /* Initialize VSI */
1684         ret = i40e_dev_rxtx_init(pf);
1685         if (ret != I40E_SUCCESS) {
1686                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1687                 goto err_up;
1688         }
1689
1690         /* Map queues with MSIX interrupt */
1691         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1692                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1693         i40e_vsi_queues_bind_intr(main_vsi);
1694         i40e_vsi_enable_queues_intr(main_vsi);
1695
1696         /* Map VMDQ VSI queues with MSIX interrupt */
1697         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1698                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1699                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1700                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1701         }
1702
1703         /* enable FDIR MSIX interrupt */
1704         if (pf->fdir.fdir_vsi) {
1705                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1706                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1707         }
1708
1709         /* Enable all queues which have been configured */
1710         ret = i40e_dev_switch_queues(pf, TRUE);
1711         if (ret != I40E_SUCCESS) {
1712                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1713                 goto err_up;
1714         }
1715
1716         /* Enable receiving broadcast packets */
1717         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1718         if (ret != I40E_SUCCESS)
1719                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1720
1721         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1722                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1723                                                 true, NULL);
1724                 if (ret != I40E_SUCCESS)
1725                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1726         }
1727
1728         /* Apply link configure */
1729         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1730                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1731                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1732                 PMD_DRV_LOG(ERR, "Invalid link setting");
1733                 goto err_up;
1734         }
1735         ret = i40e_apply_link_speed(dev);
1736         if (I40E_SUCCESS != ret) {
1737                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1738                 goto err_up;
1739         }
1740
1741         if (!rte_intr_allow_others(intr_handle)) {
1742                 rte_intr_callback_unregister(intr_handle,
1743                                              i40e_dev_interrupt_handler,
1744                                              (void *)dev);
1745                 /* configure and enable device interrupt */
1746                 i40e_pf_config_irq0(hw, FALSE);
1747                 i40e_pf_enable_irq0(hw);
1748
1749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1751                                      " no intr multiplex\n");
1752         }
1753
1754         /* enable uio intr after callback register */
1755         rte_intr_enable(intr_handle);
1756
1757         return I40E_SUCCESS;
1758
1759 err_up:
1760         i40e_dev_switch_queues(pf, FALSE);
1761         i40e_dev_clear_queues(dev);
1762
1763         return ret;
1764 }
1765
1766 static void
1767 i40e_dev_stop(struct rte_eth_dev *dev)
1768 {
1769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1770         struct i40e_vsi *main_vsi = pf->main_vsi;
1771         struct i40e_mirror_rule *p_mirror;
1772         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1773         int i;
1774
1775         /* Disable all queues */
1776         i40e_dev_switch_queues(pf, FALSE);
1777
1778         /* un-map queues with interrupt registers */
1779         i40e_vsi_disable_queues_intr(main_vsi);
1780         i40e_vsi_queues_unbind_intr(main_vsi);
1781
1782         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1783                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1784                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1785         }
1786
1787         if (pf->fdir.fdir_vsi) {
1788                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1789                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1790         }
1791         /* Clear all queues and release memory */
1792         i40e_dev_clear_queues(dev);
1793
1794         /* Set link down */
1795         i40e_dev_set_link_down(dev);
1796
1797         /* Remove all mirror rules */
1798         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1799                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1800                 rte_free(p_mirror);
1801         }
1802         pf->nb_mirror_rule = 0;
1803
1804         if (!rte_intr_allow_others(intr_handle))
1805                 /* resume to the default handler */
1806                 rte_intr_callback_register(intr_handle,
1807                                            i40e_dev_interrupt_handler,
1808                                            (void *)dev);
1809
1810         /* Clean datapath event and queue/vec mapping */
1811         rte_intr_efd_disable(intr_handle);
1812         if (intr_handle->intr_vec) {
1813                 rte_free(intr_handle->intr_vec);
1814                 intr_handle->intr_vec = NULL;
1815         }
1816 }
1817
1818 static void
1819 i40e_dev_close(struct rte_eth_dev *dev)
1820 {
1821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         uint32_t reg;
1824         int i;
1825
1826         PMD_INIT_FUNC_TRACE();
1827
1828         i40e_dev_stop(dev);
1829         hw->adapter_stopped = 1;
1830         i40e_dev_free_queues(dev);
1831
1832         /* Disable interrupt */
1833         i40e_pf_disable_irq0(hw);
1834         rte_intr_disable(&(dev->pci_dev->intr_handle));
1835
1836         /* shutdown and destroy the HMC */
1837         i40e_shutdown_lan_hmc(hw);
1838
1839         /* release all the existing VSIs and VEBs */
1840         i40e_fdir_teardown(pf);
1841         i40e_vsi_release(pf->main_vsi);
1842
1843         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1844                 i40e_vsi_release(pf->vmdq[i].vsi);
1845                 pf->vmdq[i].vsi = NULL;
1846         }
1847
1848         rte_free(pf->vmdq);
1849         pf->vmdq = NULL;
1850
1851         /* shutdown the adminq */
1852         i40e_aq_queue_shutdown(hw, true);
1853         i40e_shutdown_adminq(hw);
1854
1855         i40e_res_pool_destroy(&pf->qp_pool);
1856         i40e_res_pool_destroy(&pf->msix_pool);
1857
1858         /* force a PF reset to clean anything leftover */
1859         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1860         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1861                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1862         I40E_WRITE_FLUSH(hw);
1863 }
1864
1865 static void
1866 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1867 {
1868         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         struct i40e_vsi *vsi = pf->main_vsi;
1871         int status;
1872
1873         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1874                                                      true, NULL, true);
1875         if (status != I40E_SUCCESS)
1876                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1877
1878         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1879                                                         TRUE, NULL);
1880         if (status != I40E_SUCCESS)
1881                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1882
1883 }
1884
1885 static void
1886 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1887 {
1888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         struct i40e_vsi *vsi = pf->main_vsi;
1891         int status;
1892
1893         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1894                                                      false, NULL, true);
1895         if (status != I40E_SUCCESS)
1896                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1897
1898         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1899                                                         false, NULL);
1900         if (status != I40E_SUCCESS)
1901                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1902 }
1903
1904 static void
1905 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int ret;
1911
1912         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1913         if (ret != I40E_SUCCESS)
1914                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1915 }
1916
1917 static void
1918 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int ret;
1924
1925         if (dev->data->promiscuous == 1)
1926                 return; /* must remain in all_multicast mode */
1927
1928         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1929                                 vsi->seid, FALSE, NULL);
1930         if (ret != I40E_SUCCESS)
1931                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1932 }
1933
1934 /*
1935  * Set device link up.
1936  */
1937 static int
1938 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1939 {
1940         /* re-apply link speed setting */
1941         return i40e_apply_link_speed(dev);
1942 }
1943
1944 /*
1945  * Set device link down.
1946  */
1947 static int
1948 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1949 {
1950         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1951         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953
1954         return i40e_phy_conf_link(hw, abilities, speed);
1955 }
1956
1957 int
1958 i40e_dev_link_update(struct rte_eth_dev *dev,
1959                      int wait_to_complete)
1960 {
1961 #define CHECK_INTERVAL 100  /* 100ms */
1962 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct i40e_link_status link_status;
1965         struct rte_eth_link link, old;
1966         int status;
1967         unsigned rep_cnt = MAX_REPEAT_TIME;
1968
1969         memset(&link, 0, sizeof(link));
1970         memset(&old, 0, sizeof(old));
1971         memset(&link_status, 0, sizeof(link_status));
1972         rte_i40e_dev_atomic_read_link_status(dev, &old);
1973
1974         do {
1975                 /* Get link status information from hardware */
1976                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1977                 if (status != I40E_SUCCESS) {
1978                         link.link_speed = ETH_SPEED_NUM_100M;
1979                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1980                         PMD_DRV_LOG(ERR, "Failed to get link info");
1981                         goto out;
1982                 }
1983
1984                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1985                 if (!wait_to_complete)
1986                         break;
1987
1988                 rte_delay_ms(CHECK_INTERVAL);
1989         } while (!link.link_status && rep_cnt--);
1990
1991         if (!link.link_status)
1992                 goto out;
1993
1994         /* i40e uses full duplex only */
1995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1996
1997         /* Parse the link status */
1998         switch (link_status.link_speed) {
1999         case I40E_LINK_SPEED_100MB:
2000                 link.link_speed = ETH_SPEED_NUM_100M;
2001                 break;
2002         case I40E_LINK_SPEED_1GB:
2003                 link.link_speed = ETH_SPEED_NUM_1G;
2004                 break;
2005         case I40E_LINK_SPEED_10GB:
2006                 link.link_speed = ETH_SPEED_NUM_10G;
2007                 break;
2008         case I40E_LINK_SPEED_20GB:
2009                 link.link_speed = ETH_SPEED_NUM_20G;
2010                 break;
2011         case I40E_LINK_SPEED_40GB:
2012                 link.link_speed = ETH_SPEED_NUM_40G;
2013                 break;
2014         default:
2015                 link.link_speed = ETH_SPEED_NUM_100M;
2016                 break;
2017         }
2018
2019         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2020                         ETH_LINK_SPEED_FIXED);
2021
2022 out:
2023         rte_i40e_dev_atomic_write_link_status(dev, &link);
2024         if (link.link_status == old.link_status)
2025                 return -1;
2026
2027         return 0;
2028 }
2029
2030 /* Get all the statistics of a VSI */
2031 void
2032 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2033 {
2034         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2035         struct i40e_eth_stats *nes = &vsi->eth_stats;
2036         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2037         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2038
2039         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2040                             vsi->offset_loaded, &oes->rx_bytes,
2041                             &nes->rx_bytes);
2042         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2043                             vsi->offset_loaded, &oes->rx_unicast,
2044                             &nes->rx_unicast);
2045         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2046                             vsi->offset_loaded, &oes->rx_multicast,
2047                             &nes->rx_multicast);
2048         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2049                             vsi->offset_loaded, &oes->rx_broadcast,
2050                             &nes->rx_broadcast);
2051         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2052                             &oes->rx_discards, &nes->rx_discards);
2053         /* GLV_REPC not supported */
2054         /* GLV_RMPC not supported */
2055         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2056                             &oes->rx_unknown_protocol,
2057                             &nes->rx_unknown_protocol);
2058         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2059                             vsi->offset_loaded, &oes->tx_bytes,
2060                             &nes->tx_bytes);
2061         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2062                             vsi->offset_loaded, &oes->tx_unicast,
2063                             &nes->tx_unicast);
2064         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2065                             vsi->offset_loaded, &oes->tx_multicast,
2066                             &nes->tx_multicast);
2067         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2068                             vsi->offset_loaded,  &oes->tx_broadcast,
2069                             &nes->tx_broadcast);
2070         /* GLV_TDPC not supported */
2071         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2072                             &oes->tx_errors, &nes->tx_errors);
2073         vsi->offset_loaded = true;
2074
2075         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2076                     vsi->vsi_id);
2077         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2078         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2079         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2080         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2081         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2082         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2083                     nes->rx_unknown_protocol);
2084         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2085         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2086         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2087         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2088         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2089         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2090         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2091                     vsi->vsi_id);
2092 }
2093
2094 static void
2095 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2096 {
2097         unsigned int i;
2098         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2099         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2100
2101         /* Get statistics of struct i40e_eth_stats */
2102         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2103                             I40E_GLPRT_GORCL(hw->port),
2104                             pf->offset_loaded, &os->eth.rx_bytes,
2105                             &ns->eth.rx_bytes);
2106         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2107                             I40E_GLPRT_UPRCL(hw->port),
2108                             pf->offset_loaded, &os->eth.rx_unicast,
2109                             &ns->eth.rx_unicast);
2110         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2111                             I40E_GLPRT_MPRCL(hw->port),
2112                             pf->offset_loaded, &os->eth.rx_multicast,
2113                             &ns->eth.rx_multicast);
2114         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2115                             I40E_GLPRT_BPRCL(hw->port),
2116                             pf->offset_loaded, &os->eth.rx_broadcast,
2117                             &ns->eth.rx_broadcast);
2118         /* Workaround: CRC size should not be included in byte statistics,
2119          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2120          */
2121         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2122                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2123
2124         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2125                             pf->offset_loaded, &os->eth.rx_discards,
2126                             &ns->eth.rx_discards);
2127         /* GLPRT_REPC not supported */
2128         /* GLPRT_RMPC not supported */
2129         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2130                             pf->offset_loaded,
2131                             &os->eth.rx_unknown_protocol,
2132                             &ns->eth.rx_unknown_protocol);
2133         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2134                             I40E_GLPRT_GOTCL(hw->port),
2135                             pf->offset_loaded, &os->eth.tx_bytes,
2136                             &ns->eth.tx_bytes);
2137         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2138                             I40E_GLPRT_UPTCL(hw->port),
2139                             pf->offset_loaded, &os->eth.tx_unicast,
2140                             &ns->eth.tx_unicast);
2141         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2142                             I40E_GLPRT_MPTCL(hw->port),
2143                             pf->offset_loaded, &os->eth.tx_multicast,
2144                             &ns->eth.tx_multicast);
2145         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2146                             I40E_GLPRT_BPTCL(hw->port),
2147                             pf->offset_loaded, &os->eth.tx_broadcast,
2148                             &ns->eth.tx_broadcast);
2149         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2150                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2151         /* GLPRT_TEPC not supported */
2152
2153         /* additional port specific stats */
2154         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2155                             pf->offset_loaded, &os->tx_dropped_link_down,
2156                             &ns->tx_dropped_link_down);
2157         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2158                             pf->offset_loaded, &os->crc_errors,
2159                             &ns->crc_errors);
2160         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2161                             pf->offset_loaded, &os->illegal_bytes,
2162                             &ns->illegal_bytes);
2163         /* GLPRT_ERRBC not supported */
2164         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2165                             pf->offset_loaded, &os->mac_local_faults,
2166                             &ns->mac_local_faults);
2167         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2168                             pf->offset_loaded, &os->mac_remote_faults,
2169                             &ns->mac_remote_faults);
2170         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2171                             pf->offset_loaded, &os->rx_length_errors,
2172                             &ns->rx_length_errors);
2173         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2174                             pf->offset_loaded, &os->link_xon_rx,
2175                             &ns->link_xon_rx);
2176         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2177                             pf->offset_loaded, &os->link_xoff_rx,
2178                             &ns->link_xoff_rx);
2179         for (i = 0; i < 8; i++) {
2180                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2181                                     pf->offset_loaded,
2182                                     &os->priority_xon_rx[i],
2183                                     &ns->priority_xon_rx[i]);
2184                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2185                                     pf->offset_loaded,
2186                                     &os->priority_xoff_rx[i],
2187                                     &ns->priority_xoff_rx[i]);
2188         }
2189         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2190                             pf->offset_loaded, &os->link_xon_tx,
2191                             &ns->link_xon_tx);
2192         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2193                             pf->offset_loaded, &os->link_xoff_tx,
2194                             &ns->link_xoff_tx);
2195         for (i = 0; i < 8; i++) {
2196                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2197                                     pf->offset_loaded,
2198                                     &os->priority_xon_tx[i],
2199                                     &ns->priority_xon_tx[i]);
2200                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2201                                     pf->offset_loaded,
2202                                     &os->priority_xoff_tx[i],
2203                                     &ns->priority_xoff_tx[i]);
2204                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2205                                     pf->offset_loaded,
2206                                     &os->priority_xon_2_xoff[i],
2207                                     &ns->priority_xon_2_xoff[i]);
2208         }
2209         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2210                             I40E_GLPRT_PRC64L(hw->port),
2211                             pf->offset_loaded, &os->rx_size_64,
2212                             &ns->rx_size_64);
2213         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2214                             I40E_GLPRT_PRC127L(hw->port),
2215                             pf->offset_loaded, &os->rx_size_127,
2216                             &ns->rx_size_127);
2217         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2218                             I40E_GLPRT_PRC255L(hw->port),
2219                             pf->offset_loaded, &os->rx_size_255,
2220                             &ns->rx_size_255);
2221         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2222                             I40E_GLPRT_PRC511L(hw->port),
2223                             pf->offset_loaded, &os->rx_size_511,
2224                             &ns->rx_size_511);
2225         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2226                             I40E_GLPRT_PRC1023L(hw->port),
2227                             pf->offset_loaded, &os->rx_size_1023,
2228                             &ns->rx_size_1023);
2229         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2230                             I40E_GLPRT_PRC1522L(hw->port),
2231                             pf->offset_loaded, &os->rx_size_1522,
2232                             &ns->rx_size_1522);
2233         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2234                             I40E_GLPRT_PRC9522L(hw->port),
2235                             pf->offset_loaded, &os->rx_size_big,
2236                             &ns->rx_size_big);
2237         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2238                             pf->offset_loaded, &os->rx_undersize,
2239                             &ns->rx_undersize);
2240         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2241                             pf->offset_loaded, &os->rx_fragments,
2242                             &ns->rx_fragments);
2243         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2244                             pf->offset_loaded, &os->rx_oversize,
2245                             &ns->rx_oversize);
2246         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2247                             pf->offset_loaded, &os->rx_jabber,
2248                             &ns->rx_jabber);
2249         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2250                             I40E_GLPRT_PTC64L(hw->port),
2251                             pf->offset_loaded, &os->tx_size_64,
2252                             &ns->tx_size_64);
2253         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2254                             I40E_GLPRT_PTC127L(hw->port),
2255                             pf->offset_loaded, &os->tx_size_127,
2256                             &ns->tx_size_127);
2257         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2258                             I40E_GLPRT_PTC255L(hw->port),
2259                             pf->offset_loaded, &os->tx_size_255,
2260                             &ns->tx_size_255);
2261         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2262                             I40E_GLPRT_PTC511L(hw->port),
2263                             pf->offset_loaded, &os->tx_size_511,
2264                             &ns->tx_size_511);
2265         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2266                             I40E_GLPRT_PTC1023L(hw->port),
2267                             pf->offset_loaded, &os->tx_size_1023,
2268                             &ns->tx_size_1023);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2270                             I40E_GLPRT_PTC1522L(hw->port),
2271                             pf->offset_loaded, &os->tx_size_1522,
2272                             &ns->tx_size_1522);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2274                             I40E_GLPRT_PTC9522L(hw->port),
2275                             pf->offset_loaded, &os->tx_size_big,
2276                             &ns->tx_size_big);
2277         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2278                            pf->offset_loaded,
2279                            &os->fd_sb_match, &ns->fd_sb_match);
2280         /* GLPRT_MSPDC not supported */
2281         /* GLPRT_XEC not supported */
2282
2283         pf->offset_loaded = true;
2284
2285         if (pf->main_vsi)
2286                 i40e_update_vsi_stats(pf->main_vsi);
2287 }
2288
2289 /* Get all statistics of a port */
2290 static void
2291 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2292 {
2293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2296         unsigned i;
2297
2298         /* call read registers - updates values, now write them to struct */
2299         i40e_read_stats_registers(pf, hw);
2300
2301         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2302                         pf->main_vsi->eth_stats.rx_multicast +
2303                         pf->main_vsi->eth_stats.rx_broadcast -
2304                         pf->main_vsi->eth_stats.rx_discards;
2305         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2306                         pf->main_vsi->eth_stats.tx_multicast +
2307                         pf->main_vsi->eth_stats.tx_broadcast;
2308         stats->ibytes   = ns->eth.rx_bytes;
2309         stats->obytes   = ns->eth.tx_bytes;
2310         stats->oerrors  = ns->eth.tx_errors +
2311                         pf->main_vsi->eth_stats.tx_errors;
2312
2313         /* Rx Errors */
2314         stats->imissed  = ns->eth.rx_discards +
2315                         pf->main_vsi->eth_stats.rx_discards;
2316         stats->ierrors  = ns->crc_errors +
2317                         ns->rx_length_errors + ns->rx_undersize +
2318                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2319
2320         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2321         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2322         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2323         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2324         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2325         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2326         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2327                     ns->eth.rx_unknown_protocol);
2328         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2329         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2330         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2331         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2332         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2333         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2334
2335         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2336                     ns->tx_dropped_link_down);
2337         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2338         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2339                     ns->illegal_bytes);
2340         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2341         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2342                     ns->mac_local_faults);
2343         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2344                     ns->mac_remote_faults);
2345         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2346                     ns->rx_length_errors);
2347         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2348         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2349         for (i = 0; i < 8; i++) {
2350                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2351                                 i, ns->priority_xon_rx[i]);
2352                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2353                                 i, ns->priority_xoff_rx[i]);
2354         }
2355         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2356         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2357         for (i = 0; i < 8; i++) {
2358                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2359                                 i, ns->priority_xon_tx[i]);
2360                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2361                                 i, ns->priority_xoff_tx[i]);
2362                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2363                                 i, ns->priority_xon_2_xoff[i]);
2364         }
2365         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2366         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2367         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2368         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2369         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2370         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2371         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2372         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2373         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2374         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2375         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2376         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2377         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2378         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2379         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2380         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2381         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2382         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2383         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2384                         ns->mac_short_packet_dropped);
2385         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2386                     ns->checksum_error);
2387         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2388         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2389 }
2390
2391 /* Reset the statistics */
2392 static void
2393 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2394 {
2395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397
2398         /* Mark PF and VSI stats to update the offset, aka "reset" */
2399         pf->offset_loaded = false;
2400         if (pf->main_vsi)
2401                 pf->main_vsi->offset_loaded = false;
2402
2403         /* read the stats, reading current register values into offset */
2404         i40e_read_stats_registers(pf, hw);
2405 }
2406
2407 static uint32_t
2408 i40e_xstats_calc_num(void)
2409 {
2410         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2411                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2412                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2413 }
2414
2415 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2416                                      struct rte_eth_xstat_name *xstats_names,
2417                                      __rte_unused unsigned limit)
2418 {
2419         unsigned count = 0;
2420         unsigned i, prio;
2421
2422         if (xstats_names == NULL)
2423                 return i40e_xstats_calc_num();
2424
2425         /* Note: limit checked in rte_eth_xstats_names() */
2426
2427         /* Get stats from i40e_eth_stats struct */
2428         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2429                 snprintf(xstats_names[count].name,
2430                          sizeof(xstats_names[count].name),
2431                          "%s", rte_i40e_stats_strings[i].name);
2432                 count++;
2433         }
2434
2435         /* Get individiual stats from i40e_hw_port struct */
2436         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2437                 snprintf(xstats_names[count].name,
2438                         sizeof(xstats_names[count].name),
2439                          "%s", rte_i40e_hw_port_strings[i].name);
2440                 count++;
2441         }
2442
2443         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2444                 for (prio = 0; prio < 8; prio++) {
2445                         snprintf(xstats_names[count].name,
2446                                  sizeof(xstats_names[count].name),
2447                                  "rx_priority%u_%s", prio,
2448                                  rte_i40e_rxq_prio_strings[i].name);
2449                         count++;
2450                 }
2451         }
2452
2453         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2454                 for (prio = 0; prio < 8; prio++) {
2455                         snprintf(xstats_names[count].name,
2456                                  sizeof(xstats_names[count].name),
2457                                  "tx_priority%u_%s", prio,
2458                                  rte_i40e_txq_prio_strings[i].name);
2459                         count++;
2460                 }
2461         }
2462         return count;
2463 }
2464
2465 static int
2466 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2467                     unsigned n)
2468 {
2469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         unsigned i, count, prio;
2472         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2473
2474         count = i40e_xstats_calc_num();
2475         if (n < count)
2476                 return count;
2477
2478         i40e_read_stats_registers(pf, hw);
2479
2480         if (xstats == NULL)
2481                 return 0;
2482
2483         count = 0;
2484
2485         /* Get stats from i40e_eth_stats struct */
2486         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2487                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2488                         rte_i40e_stats_strings[i].offset);
2489                 count++;
2490         }
2491
2492         /* Get individiual stats from i40e_hw_port struct */
2493         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2494                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2495                         rte_i40e_hw_port_strings[i].offset);
2496                 count++;
2497         }
2498
2499         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2500                 for (prio = 0; prio < 8; prio++) {
2501                         xstats[count].value =
2502                                 *(uint64_t *)(((char *)hw_stats) +
2503                                 rte_i40e_rxq_prio_strings[i].offset +
2504                                 (sizeof(uint64_t) * prio));
2505                         count++;
2506                 }
2507         }
2508
2509         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2510                 for (prio = 0; prio < 8; prio++) {
2511                         xstats[count].value =
2512                                 *(uint64_t *)(((char *)hw_stats) +
2513                                 rte_i40e_txq_prio_strings[i].offset +
2514                                 (sizeof(uint64_t) * prio));
2515                         count++;
2516                 }
2517         }
2518
2519         return count;
2520 }
2521
2522 static int
2523 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2524                                  __rte_unused uint16_t queue_id,
2525                                  __rte_unused uint8_t stat_idx,
2526                                  __rte_unused uint8_t is_rx)
2527 {
2528         PMD_INIT_FUNC_TRACE();
2529
2530         return -ENOSYS;
2531 }
2532
2533 static void
2534 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2535 {
2536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct i40e_vsi *vsi = pf->main_vsi;
2539
2540         dev_info->max_rx_queues = vsi->nb_qps;
2541         dev_info->max_tx_queues = vsi->nb_qps;
2542         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2543         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2544         dev_info->max_mac_addrs = vsi->max_macaddrs;
2545         dev_info->max_vfs = dev->pci_dev->max_vfs;
2546         dev_info->rx_offload_capa =
2547                 DEV_RX_OFFLOAD_VLAN_STRIP |
2548                 DEV_RX_OFFLOAD_QINQ_STRIP |
2549                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2550                 DEV_RX_OFFLOAD_UDP_CKSUM |
2551                 DEV_RX_OFFLOAD_TCP_CKSUM;
2552         dev_info->tx_offload_capa =
2553                 DEV_TX_OFFLOAD_VLAN_INSERT |
2554                 DEV_TX_OFFLOAD_QINQ_INSERT |
2555                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2556                 DEV_TX_OFFLOAD_UDP_CKSUM |
2557                 DEV_TX_OFFLOAD_TCP_CKSUM |
2558                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2559                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2560                 DEV_TX_OFFLOAD_TCP_TSO;
2561         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2562                                                 sizeof(uint32_t);
2563         dev_info->reta_size = pf->hash_lut_size;
2564         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2565
2566         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2567                 .rx_thresh = {
2568                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2569                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2570                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2571                 },
2572                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2573                 .rx_drop_en = 0,
2574         };
2575
2576         dev_info->default_txconf = (struct rte_eth_txconf) {
2577                 .tx_thresh = {
2578                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2579                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2580                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2581                 },
2582                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2583                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2584                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2585                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2586         };
2587
2588         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2589                 .nb_max = I40E_MAX_RING_DESC,
2590                 .nb_min = I40E_MIN_RING_DESC,
2591                 .nb_align = I40E_ALIGN_RING_DESC,
2592         };
2593
2594         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2595                 .nb_max = I40E_MAX_RING_DESC,
2596                 .nb_min = I40E_MIN_RING_DESC,
2597                 .nb_align = I40E_ALIGN_RING_DESC,
2598         };
2599
2600         if (pf->flags & I40E_FLAG_VMDQ) {
2601                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2602                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2603                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2604                                                 pf->max_nb_vmdq_vsi;
2605                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2606                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2607                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2608         }
2609
2610         if (i40e_is_40G_device(hw->device_id))
2611                 /* For XL710 */
2612                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2613         else
2614                 /* For X710 */
2615                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2616 }
2617
2618 static int
2619 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2620 {
2621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2622         struct i40e_vsi *vsi = pf->main_vsi;
2623         PMD_INIT_FUNC_TRACE();
2624
2625         if (on)
2626                 return i40e_vsi_add_vlan(vsi, vlan_id);
2627         else
2628                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2629 }
2630
2631 static int
2632 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2633                    enum rte_vlan_type vlan_type,
2634                    uint16_t tpid)
2635 {
2636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637         uint64_t reg_r = 0, reg_w = 0;
2638         uint16_t reg_id = 0;
2639         int ret = 0;
2640         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2641
2642         switch (vlan_type) {
2643         case ETH_VLAN_TYPE_OUTER:
2644                 if (qinq)
2645                         reg_id = 2;
2646                 else
2647                         reg_id = 3;
2648                 break;
2649         case ETH_VLAN_TYPE_INNER:
2650                 if (qinq)
2651                         reg_id = 3;
2652                 else {
2653                         ret = -EINVAL;
2654                         PMD_DRV_LOG(ERR,
2655                                 "Unsupported vlan type in single vlan.\n");
2656                         return ret;
2657                 }
2658                 break;
2659         default:
2660                 ret = -EINVAL;
2661                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2662                 return ret;
2663         }
2664         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2665                                           &reg_r, NULL);
2666         if (ret != I40E_SUCCESS) {
2667                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2668                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2669                 ret = -EIO;
2670                 return ret;
2671         }
2672         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2673                     "0x%08"PRIx64"", reg_id, reg_r);
2674
2675         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2676         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2677         if (reg_r == reg_w) {
2678                 ret = 0;
2679                 PMD_DRV_LOG(DEBUG, "No need to write");
2680                 return ret;
2681         }
2682
2683         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2684                                            reg_w, NULL);
2685         if (ret != I40E_SUCCESS) {
2686                 ret = -EIO;
2687                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2688                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2689                 return ret;
2690         }
2691         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2692                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2693
2694         return ret;
2695 }
2696
2697 static void
2698 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2699 {
2700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         struct i40e_vsi *vsi = pf->main_vsi;
2702         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2703
2704         if (mask & ETH_VLAN_FILTER_MASK) {
2705                 if (dev->data->dev_conf.rxmode.hw_vlan_filter) {
2706                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, false, NULL);
2707                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2708                 } else {
2709                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid, true, NULL);
2710                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2711                 }
2712         }
2713
2714         if (mask & ETH_VLAN_STRIP_MASK) {
2715                 /* Enable or disable VLAN stripping */
2716                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2717                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2718                 else
2719                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2720         }
2721
2722         if (mask & ETH_VLAN_EXTEND_MASK) {
2723                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2724                         i40e_vsi_config_double_vlan(vsi, TRUE);
2725                         /* Set global registers with default ether type value */
2726                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2727                                            ETHER_TYPE_VLAN);
2728                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2729                                            ETHER_TYPE_VLAN);
2730                 }
2731                 else
2732                         i40e_vsi_config_double_vlan(vsi, FALSE);
2733         }
2734 }
2735
2736 static void
2737 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2738                           __rte_unused uint16_t queue,
2739                           __rte_unused int on)
2740 {
2741         PMD_INIT_FUNC_TRACE();
2742 }
2743
2744 static int
2745 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2746 {
2747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2748         struct i40e_vsi *vsi = pf->main_vsi;
2749         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2750         struct i40e_vsi_vlan_pvid_info info;
2751
2752         memset(&info, 0, sizeof(info));
2753         info.on = on;
2754         if (info.on)
2755                 info.config.pvid = pvid;
2756         else {
2757                 info.config.reject.tagged =
2758                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2759                 info.config.reject.untagged =
2760                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2761         }
2762
2763         return i40e_vsi_vlan_pvid_set(vsi, &info);
2764 }
2765
2766 static int
2767 i40e_dev_led_on(struct rte_eth_dev *dev)
2768 {
2769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         uint32_t mode = i40e_led_get(hw);
2771
2772         if (mode == 0)
2773                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2774
2775         return 0;
2776 }
2777
2778 static int
2779 i40e_dev_led_off(struct rte_eth_dev *dev)
2780 {
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         uint32_t mode = i40e_led_get(hw);
2783
2784         if (mode != 0)
2785                 i40e_led_set(hw, 0, false);
2786
2787         return 0;
2788 }
2789
2790 static int
2791 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2792 {
2793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795
2796         fc_conf->pause_time = pf->fc_conf.pause_time;
2797         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2798         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2799
2800          /* Return current mode according to actual setting*/
2801         switch (hw->fc.current_mode) {
2802         case I40E_FC_FULL:
2803                 fc_conf->mode = RTE_FC_FULL;
2804                 break;
2805         case I40E_FC_TX_PAUSE:
2806                 fc_conf->mode = RTE_FC_TX_PAUSE;
2807                 break;
2808         case I40E_FC_RX_PAUSE:
2809                 fc_conf->mode = RTE_FC_RX_PAUSE;
2810                 break;
2811         case I40E_FC_NONE:
2812         default:
2813                 fc_conf->mode = RTE_FC_NONE;
2814         };
2815
2816         return 0;
2817 }
2818
2819 static int
2820 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2821 {
2822         uint32_t mflcn_reg, fctrl_reg, reg;
2823         uint32_t max_high_water;
2824         uint8_t i, aq_failure;
2825         int err;
2826         struct i40e_hw *hw;
2827         struct i40e_pf *pf;
2828         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2829                 [RTE_FC_NONE] = I40E_FC_NONE,
2830                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2831                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2832                 [RTE_FC_FULL] = I40E_FC_FULL
2833         };
2834
2835         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2836
2837         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2838         if ((fc_conf->high_water > max_high_water) ||
2839                         (fc_conf->high_water < fc_conf->low_water)) {
2840                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2841                         "High_water must <= %d.", max_high_water);
2842                 return -EINVAL;
2843         }
2844
2845         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2846         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2847         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2848
2849         pf->fc_conf.pause_time = fc_conf->pause_time;
2850         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2851         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2852
2853         PMD_INIT_FUNC_TRACE();
2854
2855         /* All the link flow control related enable/disable register
2856          * configuration is handle by the F/W
2857          */
2858         err = i40e_set_fc(hw, &aq_failure, true);
2859         if (err < 0)
2860                 return -ENOSYS;
2861
2862         if (i40e_is_40G_device(hw->device_id)) {
2863                 /* Configure flow control refresh threshold,
2864                  * the value for stat_tx_pause_refresh_timer[8]
2865                  * is used for global pause operation.
2866                  */
2867
2868                 I40E_WRITE_REG(hw,
2869                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2870                                pf->fc_conf.pause_time);
2871
2872                 /* configure the timer value included in transmitted pause
2873                  * frame,
2874                  * the value for stat_tx_pause_quanta[8] is used for global
2875                  * pause operation
2876                  */
2877                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2878                                pf->fc_conf.pause_time);
2879
2880                 fctrl_reg = I40E_READ_REG(hw,
2881                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2882
2883                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2884                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2885                 else
2886                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2887
2888                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2889                                fctrl_reg);
2890         } else {
2891                 /* Configure pause time (2 TCs per register) */
2892                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2893                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2894                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2895
2896                 /* Configure flow control refresh threshold value */
2897                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2898                                pf->fc_conf.pause_time / 2);
2899
2900                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2901
2902                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2903                  *depending on configuration
2904                  */
2905                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2906                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2907                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2908                 } else {
2909                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2910                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2911                 }
2912
2913                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2914         }
2915
2916         /* config the water marker both based on the packets and bytes */
2917         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2918                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2919                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2920         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2921                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2922                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2923         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2924                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2925                        << I40E_KILOSHIFT);
2926         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2927                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2928                        << I40E_KILOSHIFT);
2929
2930         I40E_WRITE_FLUSH(hw);
2931
2932         return 0;
2933 }
2934
2935 static int
2936 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2937                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2938 {
2939         PMD_INIT_FUNC_TRACE();
2940
2941         return -ENOSYS;
2942 }
2943
2944 /* Add a MAC address, and update filters */
2945 static void
2946 i40e_macaddr_add(struct rte_eth_dev *dev,
2947                  struct ether_addr *mac_addr,
2948                  __rte_unused uint32_t index,
2949                  uint32_t pool)
2950 {
2951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2952         struct i40e_mac_filter_info mac_filter;
2953         struct i40e_vsi *vsi;
2954         int ret;
2955
2956         /* If VMDQ not enabled or configured, return */
2957         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2958                           !pf->nb_cfg_vmdq_vsi)) {
2959                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2960                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2961                         pool);
2962                 return;
2963         }
2964
2965         if (pool > pf->nb_cfg_vmdq_vsi) {
2966                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2967                                 pool, pf->nb_cfg_vmdq_vsi);
2968                 return;
2969         }
2970
2971         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2972         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2973                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2974         else
2975                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2976
2977         if (pool == 0)
2978                 vsi = pf->main_vsi;
2979         else
2980                 vsi = pf->vmdq[pool - 1].vsi;
2981
2982         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2983         if (ret != I40E_SUCCESS) {
2984                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2985                 return;
2986         }
2987 }
2988
2989 /* Remove a MAC address, and update filters */
2990 static void
2991 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2992 {
2993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2994         struct i40e_vsi *vsi;
2995         struct rte_eth_dev_data *data = dev->data;
2996         struct ether_addr *macaddr;
2997         int ret;
2998         uint32_t i;
2999         uint64_t pool_sel;
3000
3001         macaddr = &(data->mac_addrs[index]);
3002
3003         pool_sel = dev->data->mac_pool_sel[index];
3004
3005         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3006                 if (pool_sel & (1ULL << i)) {
3007                         if (i == 0)
3008                                 vsi = pf->main_vsi;
3009                         else {
3010                                 /* No VMDQ pool enabled or configured */
3011                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3012                                         (i > pf->nb_cfg_vmdq_vsi)) {
3013                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3014                                                         "/configured");
3015                                         return;
3016                                 }
3017                                 vsi = pf->vmdq[i - 1].vsi;
3018                         }
3019                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3020
3021                         if (ret) {
3022                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3023                                 return;
3024                         }
3025                 }
3026         }
3027 }
3028
3029 /* Set perfect match or hash match of MAC and VLAN for a VF */
3030 static int
3031 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3032                  struct rte_eth_mac_filter *filter,
3033                  bool add)
3034 {
3035         struct i40e_hw *hw;
3036         struct i40e_mac_filter_info mac_filter;
3037         struct ether_addr old_mac;
3038         struct ether_addr *new_mac;
3039         struct i40e_pf_vf *vf = NULL;
3040         uint16_t vf_id;
3041         int ret;
3042
3043         if (pf == NULL) {
3044                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3045                 return -EINVAL;
3046         }
3047         hw = I40E_PF_TO_HW(pf);
3048
3049         if (filter == NULL) {
3050                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3051                 return -EINVAL;
3052         }
3053
3054         new_mac = &filter->mac_addr;
3055
3056         if (is_zero_ether_addr(new_mac)) {
3057                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3058                 return -EINVAL;
3059         }
3060
3061         vf_id = filter->dst_id;
3062
3063         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3064                 PMD_DRV_LOG(ERR, "Invalid argument.");
3065                 return -EINVAL;
3066         }
3067         vf = &pf->vfs[vf_id];
3068
3069         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3070                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3071                 return -EINVAL;
3072         }
3073
3074         if (add) {
3075                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3076                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3077                                 ETHER_ADDR_LEN);
3078                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3079                                  ETHER_ADDR_LEN);
3080
3081                 mac_filter.filter_type = filter->filter_type;
3082                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3083                 if (ret != I40E_SUCCESS) {
3084                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3085                         return -1;
3086                 }
3087                 ether_addr_copy(new_mac, &pf->dev_addr);
3088         } else {
3089                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3090                                 ETHER_ADDR_LEN);
3091                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3092                 if (ret != I40E_SUCCESS) {
3093                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3094                         return -1;
3095                 }
3096
3097                 /* Clear device address as it has been removed */
3098                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3099                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3100         }
3101
3102         return 0;
3103 }
3104
3105 /* MAC filter handle */
3106 static int
3107 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3108                 void *arg)
3109 {
3110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3111         struct rte_eth_mac_filter *filter;
3112         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3113         int ret = I40E_NOT_SUPPORTED;
3114
3115         filter = (struct rte_eth_mac_filter *)(arg);
3116
3117         switch (filter_op) {
3118         case RTE_ETH_FILTER_NOP:
3119                 ret = I40E_SUCCESS;
3120                 break;
3121         case RTE_ETH_FILTER_ADD:
3122                 i40e_pf_disable_irq0(hw);
3123                 if (filter->is_vf)
3124                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3125                 i40e_pf_enable_irq0(hw);
3126                 break;
3127         case RTE_ETH_FILTER_DELETE:
3128                 i40e_pf_disable_irq0(hw);
3129                 if (filter->is_vf)
3130                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3131                 i40e_pf_enable_irq0(hw);
3132                 break;
3133         default:
3134                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3135                 ret = I40E_ERR_PARAM;
3136                 break;
3137         }
3138
3139         return ret;
3140 }
3141
3142 static int
3143 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3144 {
3145         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3146         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3147         int ret;
3148
3149         if (!lut)
3150                 return -EINVAL;
3151
3152         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3153                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3154                                           lut, lut_size);
3155                 if (ret) {
3156                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3157                         return ret;
3158                 }
3159         } else {
3160                 uint32_t *lut_dw = (uint32_t *)lut;
3161                 uint16_t i, lut_size_dw = lut_size / 4;
3162
3163                 for (i = 0; i < lut_size_dw; i++)
3164                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3165         }
3166
3167         return 0;
3168 }
3169
3170 static int
3171 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3172 {
3173         struct i40e_pf *pf;
3174         struct i40e_hw *hw;
3175         int ret;
3176
3177         if (!vsi || !lut)
3178                 return -EINVAL;
3179
3180         pf = I40E_VSI_TO_PF(vsi);
3181         hw = I40E_VSI_TO_HW(vsi);
3182
3183         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3184                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3185                                           lut, lut_size);
3186                 if (ret) {
3187                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3188                         return ret;
3189                 }
3190         } else {
3191                 uint32_t *lut_dw = (uint32_t *)lut;
3192                 uint16_t i, lut_size_dw = lut_size / 4;
3193
3194                 for (i = 0; i < lut_size_dw; i++)
3195                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3196                 I40E_WRITE_FLUSH(hw);
3197         }
3198
3199         return 0;
3200 }
3201
3202 static int
3203 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3204                          struct rte_eth_rss_reta_entry64 *reta_conf,
3205                          uint16_t reta_size)
3206 {
3207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3208         uint16_t i, lut_size = pf->hash_lut_size;
3209         uint16_t idx, shift;
3210         uint8_t *lut;
3211         int ret;
3212
3213         if (reta_size != lut_size ||
3214                 reta_size > ETH_RSS_RETA_SIZE_512) {
3215                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3216                         "(%d) doesn't match the number hardware can supported "
3217                                         "(%d)\n", reta_size, lut_size);
3218                 return -EINVAL;
3219         }
3220
3221         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3222         if (!lut) {
3223                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3224                 return -ENOMEM;
3225         }
3226         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3227         if (ret)
3228                 goto out;
3229         for (i = 0; i < reta_size; i++) {
3230                 idx = i / RTE_RETA_GROUP_SIZE;
3231                 shift = i % RTE_RETA_GROUP_SIZE;
3232                 if (reta_conf[idx].mask & (1ULL << shift))
3233                         lut[i] = reta_conf[idx].reta[shift];
3234         }
3235         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3236
3237 out:
3238         rte_free(lut);
3239
3240         return ret;
3241 }
3242
3243 static int
3244 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3245                         struct rte_eth_rss_reta_entry64 *reta_conf,
3246                         uint16_t reta_size)
3247 {
3248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3249         uint16_t i, lut_size = pf->hash_lut_size;
3250         uint16_t idx, shift;
3251         uint8_t *lut;
3252         int ret;
3253
3254         if (reta_size != lut_size ||
3255                 reta_size > ETH_RSS_RETA_SIZE_512) {
3256                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3257                         "(%d) doesn't match the number hardware can supported "
3258                                         "(%d)\n", reta_size, lut_size);
3259                 return -EINVAL;
3260         }
3261
3262         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3263         if (!lut) {
3264                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3265                 return -ENOMEM;
3266         }
3267
3268         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3269         if (ret)
3270                 goto out;
3271         for (i = 0; i < reta_size; i++) {
3272                 idx = i / RTE_RETA_GROUP_SIZE;
3273                 shift = i % RTE_RETA_GROUP_SIZE;
3274                 if (reta_conf[idx].mask & (1ULL << shift))
3275                         reta_conf[idx].reta[shift] = lut[i];
3276         }
3277
3278 out:
3279         rte_free(lut);
3280
3281         return ret;
3282 }
3283
3284 /**
3285  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3286  * @hw:   pointer to the HW structure
3287  * @mem:  pointer to mem struct to fill out
3288  * @size: size of memory requested
3289  * @alignment: what to align the allocation to
3290  **/
3291 enum i40e_status_code
3292 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3293                         struct i40e_dma_mem *mem,
3294                         u64 size,
3295                         u32 alignment)
3296 {
3297         const struct rte_memzone *mz = NULL;
3298         char z_name[RTE_MEMZONE_NAMESIZE];
3299
3300         if (!mem)
3301                 return I40E_ERR_PARAM;
3302
3303         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3304         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3305                                          alignment, RTE_PGSIZE_2M);
3306         if (!mz)
3307                 return I40E_ERR_NO_MEMORY;
3308
3309         mem->size = size;
3310         mem->va = mz->addr;
3311         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3312         mem->zone = (const void *)mz;
3313         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3314                     "%"PRIu64, mz->name, mem->pa);
3315
3316         return I40E_SUCCESS;
3317 }
3318
3319 /**
3320  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3321  * @hw:   pointer to the HW structure
3322  * @mem:  ptr to mem struct to free
3323  **/
3324 enum i40e_status_code
3325 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3326                     struct i40e_dma_mem *mem)
3327 {
3328         if (!mem)
3329                 return I40E_ERR_PARAM;
3330
3331         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3332                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3333                     mem->pa);
3334         rte_memzone_free((const struct rte_memzone *)mem->zone);
3335         mem->zone = NULL;
3336         mem->va = NULL;
3337         mem->pa = (u64)0;
3338
3339         return I40E_SUCCESS;
3340 }
3341
3342 /**
3343  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3344  * @hw:   pointer to the HW structure
3345  * @mem:  pointer to mem struct to fill out
3346  * @size: size of memory requested
3347  **/
3348 enum i40e_status_code
3349 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3350                          struct i40e_virt_mem *mem,
3351                          u32 size)
3352 {
3353         if (!mem)
3354                 return I40E_ERR_PARAM;
3355
3356         mem->size = size;
3357         mem->va = rte_zmalloc("i40e", size, 0);
3358
3359         if (mem->va)
3360                 return I40E_SUCCESS;
3361         else
3362                 return I40E_ERR_NO_MEMORY;
3363 }
3364
3365 /**
3366  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3367  * @hw:   pointer to the HW structure
3368  * @mem:  pointer to mem struct to free
3369  **/
3370 enum i40e_status_code
3371 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3372                      struct i40e_virt_mem *mem)
3373 {
3374         if (!mem)
3375                 return I40E_ERR_PARAM;
3376
3377         rte_free(mem->va);
3378         mem->va = NULL;
3379
3380         return I40E_SUCCESS;
3381 }
3382
3383 void
3384 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3385 {
3386         rte_spinlock_init(&sp->spinlock);
3387 }
3388
3389 void
3390 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3391 {
3392         rte_spinlock_lock(&sp->spinlock);
3393 }
3394
3395 void
3396 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3397 {
3398         rte_spinlock_unlock(&sp->spinlock);
3399 }
3400
3401 void
3402 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3403 {
3404         return;
3405 }
3406
3407 /**
3408  * Get the hardware capabilities, which will be parsed
3409  * and saved into struct i40e_hw.
3410  */
3411 static int
3412 i40e_get_cap(struct i40e_hw *hw)
3413 {
3414         struct i40e_aqc_list_capabilities_element_resp *buf;
3415         uint16_t len, size = 0;
3416         int ret;
3417
3418         /* Calculate a huge enough buff for saving response data temporarily */
3419         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3420                                                 I40E_MAX_CAP_ELE_NUM;
3421         buf = rte_zmalloc("i40e", len, 0);
3422         if (!buf) {
3423                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3424                 return I40E_ERR_NO_MEMORY;
3425         }
3426
3427         /* Get, parse the capabilities and save it to hw */
3428         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3429                         i40e_aqc_opc_list_func_capabilities, NULL);
3430         if (ret != I40E_SUCCESS)
3431                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3432
3433         /* Free the temporary buffer after being used */
3434         rte_free(buf);
3435
3436         return ret;
3437 }
3438
3439 static int
3440 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3441 {
3442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3444         uint16_t qp_count = 0, vsi_count = 0;
3445
3446         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3447                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3448                 return -EINVAL;
3449         }
3450         /* Add the parameter init for LFC */
3451         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3452         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3453         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3454
3455         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3456         pf->max_num_vsi = hw->func_caps.num_vsis;
3457         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3458         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3459         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3460
3461         /* FDir queue/VSI allocation */
3462         pf->fdir_qp_offset = 0;
3463         if (hw->func_caps.fd) {
3464                 pf->flags |= I40E_FLAG_FDIR;
3465                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3466         } else {
3467                 pf->fdir_nb_qps = 0;
3468         }
3469         qp_count += pf->fdir_nb_qps;
3470         vsi_count += 1;
3471
3472         /* LAN queue/VSI allocation */
3473         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3474         if (!hw->func_caps.rss) {
3475                 pf->lan_nb_qps = 1;
3476         } else {
3477                 pf->flags |= I40E_FLAG_RSS;
3478                 if (hw->mac.type == I40E_MAC_X722)
3479                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3480                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3481         }
3482         qp_count += pf->lan_nb_qps;
3483         vsi_count += 1;
3484
3485         /* VF queue/VSI allocation */
3486         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3487         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3488                 pf->flags |= I40E_FLAG_SRIOV;
3489                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3490                 pf->vf_num = dev->pci_dev->max_vfs;
3491                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3492                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3493                             pf->vf_nb_qps * pf->vf_num);
3494         } else {
3495                 pf->vf_nb_qps = 0;
3496                 pf->vf_num = 0;
3497         }
3498         qp_count += pf->vf_nb_qps * pf->vf_num;
3499         vsi_count += pf->vf_num;
3500
3501         /* VMDq queue/VSI allocation */
3502         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3503         pf->vmdq_nb_qps = 0;
3504         pf->max_nb_vmdq_vsi = 0;
3505         if (hw->func_caps.vmdq) {
3506                 if (qp_count < hw->func_caps.num_tx_qp &&
3507                         vsi_count < hw->func_caps.num_vsis) {
3508                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3509                                 qp_count) / pf->vmdq_nb_qp_max;
3510
3511                         /* Limit the maximum number of VMDq vsi to the maximum
3512                          * ethdev can support
3513                          */
3514                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3515                                 hw->func_caps.num_vsis - vsi_count);
3516                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3517                                 ETH_64_POOLS);
3518                         if (pf->max_nb_vmdq_vsi) {
3519                                 pf->flags |= I40E_FLAG_VMDQ;
3520                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3521                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3522                                             "per VMDQ VSI, in total %u queues",
3523                                             pf->max_nb_vmdq_vsi,
3524                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3525                                             pf->max_nb_vmdq_vsi);
3526                         } else {
3527                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3528                                             "VMDq");
3529                         }
3530                 } else {
3531                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3532                 }
3533         }
3534         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3535         vsi_count += pf->max_nb_vmdq_vsi;
3536
3537         if (hw->func_caps.dcb)
3538                 pf->flags |= I40E_FLAG_DCB;
3539
3540         if (qp_count > hw->func_caps.num_tx_qp) {
3541                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3542                             "the hardware maximum %u", qp_count,
3543                             hw->func_caps.num_tx_qp);
3544                 return -EINVAL;
3545         }
3546         if (vsi_count > hw->func_caps.num_vsis) {
3547                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3548                             "the hardware maximum %u", vsi_count,
3549                             hw->func_caps.num_vsis);
3550                 return -EINVAL;
3551         }
3552
3553         return 0;
3554 }
3555
3556 static int
3557 i40e_pf_get_switch_config(struct i40e_pf *pf)
3558 {
3559         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3560         struct i40e_aqc_get_switch_config_resp *switch_config;
3561         struct i40e_aqc_switch_config_element_resp *element;
3562         uint16_t start_seid = 0, num_reported;
3563         int ret;
3564
3565         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3566                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3567         if (!switch_config) {
3568                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3569                 return -ENOMEM;
3570         }
3571
3572         /* Get the switch configurations */
3573         ret = i40e_aq_get_switch_config(hw, switch_config,
3574                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3575         if (ret != I40E_SUCCESS) {
3576                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3577                 goto fail;
3578         }
3579         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3580         if (num_reported != 1) { /* The number should be 1 */
3581                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3582                 goto fail;
3583         }
3584
3585         /* Parse the switch configuration elements */
3586         element = &(switch_config->element[0]);
3587         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3588                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3589                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3590         } else
3591                 PMD_DRV_LOG(INFO, "Unknown element type");
3592
3593 fail:
3594         rte_free(switch_config);
3595
3596         return ret;
3597 }
3598
3599 static int
3600 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3601                         uint32_t num)
3602 {
3603         struct pool_entry *entry;
3604
3605         if (pool == NULL || num == 0)
3606                 return -EINVAL;
3607
3608         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3609         if (entry == NULL) {
3610                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3611                 return -ENOMEM;
3612         }
3613
3614         /* queue heap initialize */
3615         pool->num_free = num;
3616         pool->num_alloc = 0;
3617         pool->base = base;
3618         LIST_INIT(&pool->alloc_list);
3619         LIST_INIT(&pool->free_list);
3620
3621         /* Initialize element  */
3622         entry->base = 0;
3623         entry->len = num;
3624
3625         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3626         return 0;
3627 }
3628
3629 static void
3630 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3631 {
3632         struct pool_entry *entry, *next_entry;
3633
3634         if (pool == NULL)
3635                 return;
3636
3637         for (entry = LIST_FIRST(&pool->alloc_list);
3638                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3639                         entry = next_entry) {
3640                 LIST_REMOVE(entry, next);
3641                 rte_free(entry);
3642         }
3643
3644         for (entry = LIST_FIRST(&pool->free_list);
3645                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3646                         entry = next_entry) {
3647                 LIST_REMOVE(entry, next);
3648                 rte_free(entry);
3649         }
3650
3651         pool->num_free = 0;
3652         pool->num_alloc = 0;
3653         pool->base = 0;
3654         LIST_INIT(&pool->alloc_list);
3655         LIST_INIT(&pool->free_list);
3656 }
3657
3658 static int
3659 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3660                        uint32_t base)
3661 {
3662         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3663         uint32_t pool_offset;
3664         int insert;
3665
3666         if (pool == NULL) {
3667                 PMD_DRV_LOG(ERR, "Invalid parameter");
3668                 return -EINVAL;
3669         }
3670
3671         pool_offset = base - pool->base;
3672         /* Lookup in alloc list */
3673         LIST_FOREACH(entry, &pool->alloc_list, next) {
3674                 if (entry->base == pool_offset) {
3675                         valid_entry = entry;
3676                         LIST_REMOVE(entry, next);
3677                         break;
3678                 }
3679         }
3680
3681         /* Not find, return */
3682         if (valid_entry == NULL) {
3683                 PMD_DRV_LOG(ERR, "Failed to find entry");
3684                 return -EINVAL;
3685         }
3686
3687         /**
3688          * Found it, move it to free list  and try to merge.
3689          * In order to make merge easier, always sort it by qbase.
3690          * Find adjacent prev and last entries.
3691          */
3692         prev = next = NULL;
3693         LIST_FOREACH(entry, &pool->free_list, next) {
3694                 if (entry->base > valid_entry->base) {
3695                         next = entry;
3696                         break;
3697                 }
3698                 prev = entry;
3699         }
3700
3701         insert = 0;
3702         /* Try to merge with next one*/
3703         if (next != NULL) {
3704                 /* Merge with next one */
3705                 if (valid_entry->base + valid_entry->len == next->base) {
3706                         next->base = valid_entry->base;
3707                         next->len += valid_entry->len;
3708                         rte_free(valid_entry);
3709                         valid_entry = next;
3710                         insert = 1;
3711                 }
3712         }
3713
3714         if (prev != NULL) {
3715                 /* Merge with previous one */
3716                 if (prev->base + prev->len == valid_entry->base) {
3717                         prev->len += valid_entry->len;
3718                         /* If it merge with next one, remove next node */
3719                         if (insert == 1) {
3720                                 LIST_REMOVE(valid_entry, next);
3721                                 rte_free(valid_entry);
3722                         } else {
3723                                 rte_free(valid_entry);
3724                                 insert = 1;
3725                         }
3726                 }
3727         }
3728
3729         /* Not find any entry to merge, insert */
3730         if (insert == 0) {
3731                 if (prev != NULL)
3732                         LIST_INSERT_AFTER(prev, valid_entry, next);
3733                 else if (next != NULL)
3734                         LIST_INSERT_BEFORE(next, valid_entry, next);
3735                 else /* It's empty list, insert to head */
3736                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3737         }
3738
3739         pool->num_free += valid_entry->len;
3740         pool->num_alloc -= valid_entry->len;
3741
3742         return 0;
3743 }
3744
3745 static int
3746 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3747                        uint16_t num)
3748 {
3749         struct pool_entry *entry, *valid_entry;
3750
3751         if (pool == NULL || num == 0) {
3752                 PMD_DRV_LOG(ERR, "Invalid parameter");
3753                 return -EINVAL;
3754         }
3755
3756         if (pool->num_free < num) {
3757                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3758                             num, pool->num_free);
3759                 return -ENOMEM;
3760         }
3761
3762         valid_entry = NULL;
3763         /* Lookup  in free list and find most fit one */
3764         LIST_FOREACH(entry, &pool->free_list, next) {
3765                 if (entry->len >= num) {
3766                         /* Find best one */
3767                         if (entry->len == num) {
3768                                 valid_entry = entry;
3769                                 break;
3770                         }
3771                         if (valid_entry == NULL || valid_entry->len > entry->len)
3772                                 valid_entry = entry;
3773                 }
3774         }
3775
3776         /* Not find one to satisfy the request, return */
3777         if (valid_entry == NULL) {
3778                 PMD_DRV_LOG(ERR, "No valid entry found");
3779                 return -ENOMEM;
3780         }
3781         /**
3782          * The entry have equal queue number as requested,
3783          * remove it from alloc_list.
3784          */
3785         if (valid_entry->len == num) {
3786                 LIST_REMOVE(valid_entry, next);
3787         } else {
3788                 /**
3789                  * The entry have more numbers than requested,
3790                  * create a new entry for alloc_list and minus its
3791                  * queue base and number in free_list.
3792                  */
3793                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3794                 if (entry == NULL) {
3795                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3796                                     "resource pool");
3797                         return -ENOMEM;
3798                 }
3799                 entry->base = valid_entry->base;
3800                 entry->len = num;
3801                 valid_entry->base += num;
3802                 valid_entry->len -= num;
3803                 valid_entry = entry;
3804         }
3805
3806         /* Insert it into alloc list, not sorted */
3807         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3808
3809         pool->num_free -= valid_entry->len;
3810         pool->num_alloc += valid_entry->len;
3811
3812         return valid_entry->base + pool->base;
3813 }
3814
3815 /**
3816  * bitmap_is_subset - Check whether src2 is subset of src1
3817  **/
3818 static inline int
3819 bitmap_is_subset(uint8_t src1, uint8_t src2)
3820 {
3821         return !((src1 ^ src2) & src2);
3822 }
3823
3824 static enum i40e_status_code
3825 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3826 {
3827         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3828
3829         /* If DCB is not supported, only default TC is supported */
3830         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3831                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3832                 return I40E_NOT_SUPPORTED;
3833         }
3834
3835         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3836                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3837                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3838                             enabled_tcmap);
3839                 return I40E_NOT_SUPPORTED;
3840         }
3841         return I40E_SUCCESS;
3842 }
3843
3844 int
3845 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3846                                 struct i40e_vsi_vlan_pvid_info *info)
3847 {
3848         struct i40e_hw *hw;
3849         struct i40e_vsi_context ctxt;
3850         uint8_t vlan_flags = 0;
3851         int ret;
3852
3853         if (vsi == NULL || info == NULL) {
3854                 PMD_DRV_LOG(ERR, "invalid parameters");
3855                 return I40E_ERR_PARAM;
3856         }
3857
3858         if (info->on) {
3859                 vsi->info.pvid = info->config.pvid;
3860                 /**
3861                  * If insert pvid is enabled, only tagged pkts are
3862                  * allowed to be sent out.
3863                  */
3864                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3865                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3866         } else {
3867                 vsi->info.pvid = 0;
3868                 if (info->config.reject.tagged == 0)
3869                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3870
3871                 if (info->config.reject.untagged == 0)
3872                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3873         }
3874         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3875                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3876         vsi->info.port_vlan_flags |= vlan_flags;
3877         vsi->info.valid_sections =
3878                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3879         memset(&ctxt, 0, sizeof(ctxt));
3880         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3881         ctxt.seid = vsi->seid;
3882
3883         hw = I40E_VSI_TO_HW(vsi);
3884         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3885         if (ret != I40E_SUCCESS)
3886                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3887
3888         return ret;
3889 }
3890
3891 static int
3892 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3893 {
3894         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3895         int i, ret;
3896         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3897
3898         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3899         if (ret != I40E_SUCCESS)
3900                 return ret;
3901
3902         if (!vsi->seid) {
3903                 PMD_DRV_LOG(ERR, "seid not valid");
3904                 return -EINVAL;
3905         }
3906
3907         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3908         tc_bw_data.tc_valid_bits = enabled_tcmap;
3909         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3910                 tc_bw_data.tc_bw_credits[i] =
3911                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3912
3913         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3914         if (ret != I40E_SUCCESS) {
3915                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3916                 return ret;
3917         }
3918
3919         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3920                                         sizeof(vsi->info.qs_handle));
3921         return I40E_SUCCESS;
3922 }
3923
3924 static enum i40e_status_code
3925 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3926                                  struct i40e_aqc_vsi_properties_data *info,
3927                                  uint8_t enabled_tcmap)
3928 {
3929         enum i40e_status_code ret;
3930         int i, total_tc = 0;
3931         uint16_t qpnum_per_tc, bsf, qp_idx;
3932
3933         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3934         if (ret != I40E_SUCCESS)
3935                 return ret;
3936
3937         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3938                 if (enabled_tcmap & (1 << i))
3939                         total_tc++;
3940         vsi->enabled_tc = enabled_tcmap;
3941
3942         /* Number of queues per enabled TC */
3943         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3944         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3945         bsf = rte_bsf32(qpnum_per_tc);
3946
3947         /* Adjust the queue number to actual queues that can be applied */
3948         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3949                 vsi->nb_qps = qpnum_per_tc * total_tc;
3950
3951         /**
3952          * Configure TC and queue mapping parameters, for enabled TC,
3953          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3954          * default queue will serve it.
3955          */
3956         qp_idx = 0;
3957         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3958                 if (vsi->enabled_tc & (1 << i)) {
3959                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3960                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3961                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3962                         qp_idx += qpnum_per_tc;
3963                 } else
3964                         info->tc_mapping[i] = 0;
3965         }
3966
3967         /* Associate queue number with VSI */
3968         if (vsi->type == I40E_VSI_SRIOV) {
3969                 info->mapping_flags |=
3970                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3971                 for (i = 0; i < vsi->nb_qps; i++)
3972                         info->queue_mapping[i] =
3973                                 rte_cpu_to_le_16(vsi->base_queue + i);
3974         } else {
3975                 info->mapping_flags |=
3976                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3977                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3978         }
3979         info->valid_sections |=
3980                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3981
3982         return I40E_SUCCESS;
3983 }
3984
3985 static int
3986 i40e_veb_release(struct i40e_veb *veb)
3987 {
3988         struct i40e_vsi *vsi;
3989         struct i40e_hw *hw;
3990
3991         if (veb == NULL)
3992                 return -EINVAL;
3993
3994         if (!TAILQ_EMPTY(&veb->head)) {
3995                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3996                 return -EACCES;
3997         }
3998         /* associate_vsi field is NULL for floating VEB */
3999         if (veb->associate_vsi != NULL) {
4000                 vsi = veb->associate_vsi;
4001                 hw = I40E_VSI_TO_HW(vsi);
4002
4003                 vsi->uplink_seid = veb->uplink_seid;
4004                 vsi->veb = NULL;
4005         } else {
4006                 veb->associate_pf->main_vsi->floating_veb = NULL;
4007                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4008         }
4009
4010         i40e_aq_delete_element(hw, veb->seid, NULL);
4011         rte_free(veb);
4012         return I40E_SUCCESS;
4013 }
4014
4015 /* Setup a veb */
4016 static struct i40e_veb *
4017 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4018 {
4019         struct i40e_veb *veb;
4020         int ret;
4021         struct i40e_hw *hw;
4022
4023         if (pf == NULL) {
4024                 PMD_DRV_LOG(ERR,
4025                             "veb setup failed, associated PF shouldn't null");
4026                 return NULL;
4027         }
4028         hw = I40E_PF_TO_HW(pf);
4029
4030         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4031         if (!veb) {
4032                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4033                 goto fail;
4034         }
4035
4036         veb->associate_vsi = vsi;
4037         veb->associate_pf = pf;
4038         TAILQ_INIT(&veb->head);
4039         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4040
4041         /* create floating veb if vsi is NULL */
4042         if (vsi != NULL) {
4043                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4044                                       I40E_DEFAULT_TCMAP, false,
4045                                       &veb->seid, false, NULL);
4046         } else {
4047                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4048                                       true, &veb->seid, false, NULL);
4049         }
4050
4051         if (ret != I40E_SUCCESS) {
4052                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4053                             hw->aq.asq_last_status);
4054                 goto fail;
4055         }
4056
4057         /* get statistics index */
4058         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4059                                 &veb->stats_idx, NULL, NULL, NULL);
4060         if (ret != I40E_SUCCESS) {
4061                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4062                             hw->aq.asq_last_status);
4063                 goto fail;
4064         }
4065         /* Get VEB bandwidth, to be implemented */
4066         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4067         if (vsi)
4068                 vsi->uplink_seid = veb->seid;
4069
4070         return veb;
4071 fail:
4072         rte_free(veb);
4073         return NULL;
4074 }
4075
4076 int
4077 i40e_vsi_release(struct i40e_vsi *vsi)
4078 {
4079         struct i40e_pf *pf;
4080         struct i40e_hw *hw;
4081         struct i40e_vsi_list *vsi_list;
4082         int ret;
4083         struct i40e_mac_filter *f;
4084         uint16_t user_param = vsi->user_param;
4085
4086         if (!vsi)
4087                 return I40E_SUCCESS;
4088
4089         pf = I40E_VSI_TO_PF(vsi);
4090         hw = I40E_VSI_TO_HW(vsi);
4091
4092         /* VSI has child to attach, release child first */
4093         if (vsi->veb) {
4094                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4095                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4096                                 return -1;
4097                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4098                 }
4099                 i40e_veb_release(vsi->veb);
4100         }
4101
4102         if (vsi->floating_veb) {
4103                 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4104                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4105                                 return -1;
4106                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4107                 }
4108         }
4109
4110         /* Remove all macvlan filters of the VSI */
4111         i40e_vsi_remove_all_macvlan_filter(vsi);
4112         TAILQ_FOREACH(f, &vsi->mac_list, next)
4113                 rte_free(f);
4114
4115         if (vsi->type != I40E_VSI_MAIN &&
4116             ((vsi->type != I40E_VSI_SRIOV) ||
4117             !pf->floating_veb_list[user_param])) {
4118                 /* Remove vsi from parent's sibling list */
4119                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4120                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4121                         return I40E_ERR_PARAM;
4122                 }
4123                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4124                                 &vsi->sib_vsi_list, list);
4125
4126                 /* Remove all switch element of the VSI */
4127                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4128                 if (ret != I40E_SUCCESS)
4129                         PMD_DRV_LOG(ERR, "Failed to delete element");
4130         }
4131
4132         if ((vsi->type == I40E_VSI_SRIOV) &&
4133             pf->floating_veb_list[user_param]) {
4134                 /* Remove vsi from parent's sibling list */
4135                 if (vsi->parent_vsi == NULL ||
4136                     vsi->parent_vsi->floating_veb == NULL) {
4137                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4138                         return I40E_ERR_PARAM;
4139                 }
4140                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4141                              &vsi->sib_vsi_list, list);
4142
4143                 /* Remove all switch element of the VSI */
4144                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4145                 if (ret != I40E_SUCCESS)
4146                         PMD_DRV_LOG(ERR, "Failed to delete element");
4147         }
4148
4149         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4150
4151         if (vsi->type != I40E_VSI_SRIOV)
4152                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4153         rte_free(vsi);
4154
4155         return I40E_SUCCESS;
4156 }
4157
4158 static int
4159 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4160 {
4161         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4162         struct i40e_aqc_remove_macvlan_element_data def_filter;
4163         struct i40e_mac_filter_info filter;
4164         int ret;
4165
4166         if (vsi->type != I40E_VSI_MAIN)
4167                 return I40E_ERR_CONFIG;
4168         memset(&def_filter, 0, sizeof(def_filter));
4169         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4170                                         ETH_ADDR_LEN);
4171         def_filter.vlan_tag = 0;
4172         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4173                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4174         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4175         if (ret != I40E_SUCCESS) {
4176                 struct i40e_mac_filter *f;
4177                 struct ether_addr *mac;
4178
4179                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4180                             "macvlan filter");
4181                 /* It needs to add the permanent mac into mac list */
4182                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4183                 if (f == NULL) {
4184                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4185                         return I40E_ERR_NO_MEMORY;
4186                 }
4187                 mac = &f->mac_info.mac_addr;
4188                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4189                                 ETH_ADDR_LEN);
4190                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4191                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4192                 vsi->mac_num++;
4193
4194                 return ret;
4195         }
4196         (void)rte_memcpy(&filter.mac_addr,
4197                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4198         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4199         return i40e_vsi_add_mac(vsi, &filter);
4200 }
4201
4202 /*
4203  * i40e_vsi_get_bw_config - Query VSI BW Information
4204  * @vsi: the VSI to be queried
4205  *
4206  * Returns 0 on success, negative value on failure
4207  */
4208 static enum i40e_status_code
4209 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4210 {
4211         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4212         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4213         struct i40e_hw *hw = &vsi->adapter->hw;
4214         i40e_status ret;
4215         int i;
4216         uint32_t bw_max;
4217
4218         memset(&bw_config, 0, sizeof(bw_config));
4219         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4220         if (ret != I40E_SUCCESS) {
4221                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4222                             hw->aq.asq_last_status);
4223                 return ret;
4224         }
4225
4226         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4227         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4228                                         &ets_sla_config, NULL);
4229         if (ret != I40E_SUCCESS) {
4230                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4231                             "configuration %u", hw->aq.asq_last_status);
4232                 return ret;
4233         }
4234
4235         /* store and print out BW info */
4236         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4237         vsi->bw_info.bw_max = bw_config.max_bw;
4238         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4239         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4240         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4241                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4242                      I40E_16_BIT_WIDTH);
4243         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4244                 vsi->bw_info.bw_ets_share_credits[i] =
4245                                 ets_sla_config.share_credits[i];
4246                 vsi->bw_info.bw_ets_credits[i] =
4247                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4248                 /* 4 bits per TC, 4th bit is reserved */
4249                 vsi->bw_info.bw_ets_max[i] =
4250                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4251                                   RTE_LEN2MASK(3, uint8_t));
4252                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4253                             vsi->bw_info.bw_ets_share_credits[i]);
4254                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4255                             vsi->bw_info.bw_ets_credits[i]);
4256                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4257                             vsi->bw_info.bw_ets_max[i]);
4258         }
4259
4260         return I40E_SUCCESS;
4261 }
4262
4263 /* i40e_enable_pf_lb
4264  * @pf: pointer to the pf structure
4265  *
4266  * allow loopback on pf
4267  */
4268 static inline void
4269 i40e_enable_pf_lb(struct i40e_pf *pf)
4270 {
4271         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4272         struct i40e_vsi_context ctxt;
4273         int ret;
4274
4275         /* Use the FW API if FW >= v5.0 */
4276         if (hw->aq.fw_maj_ver < 5) {
4277                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4278                 return;
4279         }
4280
4281         memset(&ctxt, 0, sizeof(ctxt));
4282         ctxt.seid = pf->main_vsi_seid;
4283         ctxt.pf_num = hw->pf_id;
4284         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4285         if (ret) {
4286                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4287                             ret, hw->aq.asq_last_status);
4288                 return;
4289         }
4290         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4291         ctxt.info.valid_sections =
4292                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4293         ctxt.info.switch_id |=
4294                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4295
4296         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4297         if (ret)
4298                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4299                             hw->aq.asq_last_status);
4300 }
4301
4302 /* Setup a VSI */
4303 struct i40e_vsi *
4304 i40e_vsi_setup(struct i40e_pf *pf,
4305                enum i40e_vsi_type type,
4306                struct i40e_vsi *uplink_vsi,
4307                uint16_t user_param)
4308 {
4309         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4310         struct i40e_vsi *vsi;
4311         struct i40e_mac_filter_info filter;
4312         int ret;
4313         struct i40e_vsi_context ctxt;
4314         struct ether_addr broadcast =
4315                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4316
4317         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4318             uplink_vsi == NULL) {
4319                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4320                             "VSI link shouldn't be NULL");
4321                 return NULL;
4322         }
4323
4324         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4325                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4326                             "uplink VSI should be NULL");
4327                 return NULL;
4328         }
4329
4330         /* two situations
4331          * 1.type is not MAIN and uplink vsi is not NULL
4332          * If uplink vsi didn't setup VEB, create one first under veb field
4333          * 2.type is SRIOV and the uplink is NULL
4334          * If floating VEB is NULL, create one veb under floating veb field
4335          */
4336
4337         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4338             uplink_vsi->veb == NULL) {
4339                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4340
4341                 if (uplink_vsi->veb == NULL) {
4342                         PMD_DRV_LOG(ERR, "VEB setup failed");
4343                         return NULL;
4344                 }
4345                 /* set ALLOWLOOPBACk on pf, when veb is created */
4346                 i40e_enable_pf_lb(pf);
4347         }
4348
4349         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4350             pf->main_vsi->floating_veb == NULL) {
4351                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4352
4353                 if (pf->main_vsi->floating_veb == NULL) {
4354                         PMD_DRV_LOG(ERR, "VEB setup failed");
4355                         return NULL;
4356                 }
4357         }
4358
4359         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4360         if (!vsi) {
4361                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4362                 return NULL;
4363         }
4364         TAILQ_INIT(&vsi->mac_list);
4365         vsi->type = type;
4366         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4367         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4368         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4369         vsi->user_param = user_param;
4370         /* Allocate queues */
4371         switch (vsi->type) {
4372         case I40E_VSI_MAIN  :
4373                 vsi->nb_qps = pf->lan_nb_qps;
4374                 break;
4375         case I40E_VSI_SRIOV :
4376                 vsi->nb_qps = pf->vf_nb_qps;
4377                 break;
4378         case I40E_VSI_VMDQ2:
4379                 vsi->nb_qps = pf->vmdq_nb_qps;
4380                 break;
4381         case I40E_VSI_FDIR:
4382                 vsi->nb_qps = pf->fdir_nb_qps;
4383                 break;
4384         default:
4385                 goto fail_mem;
4386         }
4387         /*
4388          * The filter status descriptor is reported in rx queue 0,
4389          * while the tx queue for fdir filter programming has no
4390          * such constraints, can be non-zero queues.
4391          * To simplify it, choose FDIR vsi use queue 0 pair.
4392          * To make sure it will use queue 0 pair, queue allocation
4393          * need be done before this function is called
4394          */
4395         if (type != I40E_VSI_FDIR) {
4396                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4397                         if (ret < 0) {
4398                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4399                                                 vsi->seid, ret);
4400                                 goto fail_mem;
4401                         }
4402                         vsi->base_queue = ret;
4403         } else
4404                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4405
4406         /* VF has MSIX interrupt in VF range, don't allocate here */
4407         if (type == I40E_VSI_MAIN) {
4408                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4409                                           RTE_MIN(vsi->nb_qps,
4410                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4411                 if (ret < 0) {
4412                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4413                                     vsi->seid, ret);
4414                         goto fail_queue_alloc;
4415                 }
4416                 vsi->msix_intr = ret;
4417                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4418         } else if (type != I40E_VSI_SRIOV) {
4419                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4420                 if (ret < 0) {
4421                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4422                         goto fail_queue_alloc;
4423                 }
4424                 vsi->msix_intr = ret;
4425                 vsi->nb_msix = 1;
4426         } else {
4427                 vsi->msix_intr = 0;
4428                 vsi->nb_msix = 0;
4429         }
4430
4431         /* Add VSI */
4432         if (type == I40E_VSI_MAIN) {
4433                 /* For main VSI, no need to add since it's default one */
4434                 vsi->uplink_seid = pf->mac_seid;
4435                 vsi->seid = pf->main_vsi_seid;
4436                 /* Bind queues with specific MSIX interrupt */
4437                 /**
4438                  * Needs 2 interrupt at least, one for misc cause which will
4439                  * enabled from OS side, Another for queues binding the
4440                  * interrupt from device side only.
4441                  */
4442
4443                 /* Get default VSI parameters from hardware */
4444                 memset(&ctxt, 0, sizeof(ctxt));
4445                 ctxt.seid = vsi->seid;
4446                 ctxt.pf_num = hw->pf_id;
4447                 ctxt.uplink_seid = vsi->uplink_seid;
4448                 ctxt.vf_num = 0;
4449                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4450                 if (ret != I40E_SUCCESS) {
4451                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4452                         goto fail_msix_alloc;
4453                 }
4454                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4455                         sizeof(struct i40e_aqc_vsi_properties_data));
4456                 vsi->vsi_id = ctxt.vsi_number;
4457                 vsi->info.valid_sections = 0;
4458
4459                 /* Configure tc, enabled TC0 only */
4460                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4461                         I40E_SUCCESS) {
4462                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4463                         goto fail_msix_alloc;
4464                 }
4465
4466                 /* TC, queue mapping */
4467                 memset(&ctxt, 0, sizeof(ctxt));
4468                 vsi->info.valid_sections |=
4469                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4470                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4471                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4472                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4473                         sizeof(struct i40e_aqc_vsi_properties_data));
4474                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4475                                                 I40E_DEFAULT_TCMAP);
4476                 if (ret != I40E_SUCCESS) {
4477                         PMD_DRV_LOG(ERR, "Failed to configure "
4478                                     "TC queue mapping");
4479                         goto fail_msix_alloc;
4480                 }
4481                 ctxt.seid = vsi->seid;
4482                 ctxt.pf_num = hw->pf_id;
4483                 ctxt.uplink_seid = vsi->uplink_seid;
4484                 ctxt.vf_num = 0;
4485
4486                 /* Update VSI parameters */
4487                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4488                 if (ret != I40E_SUCCESS) {
4489                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4490                         goto fail_msix_alloc;
4491                 }
4492
4493                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4494                                                 sizeof(vsi->info.tc_mapping));
4495                 (void)rte_memcpy(&vsi->info.queue_mapping,
4496                                 &ctxt.info.queue_mapping,
4497                         sizeof(vsi->info.queue_mapping));
4498                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4499                 vsi->info.valid_sections = 0;
4500
4501                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4502                                 ETH_ADDR_LEN);
4503
4504                 /**
4505                  * Updating default filter settings are necessary to prevent
4506                  * reception of tagged packets.
4507                  * Some old firmware configurations load a default macvlan
4508                  * filter which accepts both tagged and untagged packets.
4509                  * The updating is to use a normal filter instead if needed.
4510                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4511                  * The firmware with correct configurations load the default
4512                  * macvlan filter which is expected and cannot be removed.
4513                  */
4514                 i40e_update_default_filter_setting(vsi);
4515                 i40e_config_qinq(hw, vsi);
4516         } else if (type == I40E_VSI_SRIOV) {
4517                 memset(&ctxt, 0, sizeof(ctxt));
4518                 /**
4519                  * For other VSI, the uplink_seid equals to uplink VSI's
4520                  * uplink_seid since they share same VEB
4521                  */
4522                 if (uplink_vsi == NULL)
4523                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4524                 else
4525                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4526                 ctxt.pf_num = hw->pf_id;
4527                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4528                 ctxt.uplink_seid = vsi->uplink_seid;
4529                 ctxt.connection_type = 0x1;
4530                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4531
4532                 /* Use the VEB configuration if FW >= v5.0 */
4533                 if (hw->aq.fw_maj_ver >= 5) {
4534                         /* Configure switch ID */
4535                         ctxt.info.valid_sections |=
4536                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4537                         ctxt.info.switch_id =
4538                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4539                 }
4540
4541                 /* Configure port/vlan */
4542                 ctxt.info.valid_sections |=
4543                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4544                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4545                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4546                                                 I40E_DEFAULT_TCMAP);
4547                 if (ret != I40E_SUCCESS) {
4548                         PMD_DRV_LOG(ERR, "Failed to configure "
4549                                     "TC queue mapping");
4550                         goto fail_msix_alloc;
4551                 }
4552                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4553                 ctxt.info.valid_sections |=
4554                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4555                 /**
4556                  * Since VSI is not created yet, only configure parameter,
4557                  * will add vsi below.
4558                  */
4559
4560                 i40e_config_qinq(hw, vsi);
4561         } else if (type == I40E_VSI_VMDQ2) {
4562                 memset(&ctxt, 0, sizeof(ctxt));
4563                 /*
4564                  * For other VSI, the uplink_seid equals to uplink VSI's
4565                  * uplink_seid since they share same VEB
4566                  */
4567                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4568                 ctxt.pf_num = hw->pf_id;
4569                 ctxt.vf_num = 0;
4570                 ctxt.uplink_seid = vsi->uplink_seid;
4571                 ctxt.connection_type = 0x1;
4572                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4573
4574                 ctxt.info.valid_sections |=
4575                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4576                 /* user_param carries flag to enable loop back */
4577                 if (user_param) {
4578                         ctxt.info.switch_id =
4579                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4580                         ctxt.info.switch_id |=
4581                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4582                 }
4583
4584                 /* Configure port/vlan */
4585                 ctxt.info.valid_sections |=
4586                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4587                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4588                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4589                                                 I40E_DEFAULT_TCMAP);
4590                 if (ret != I40E_SUCCESS) {
4591                         PMD_DRV_LOG(ERR, "Failed to configure "
4592                                         "TC queue mapping");
4593                         goto fail_msix_alloc;
4594                 }
4595                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4596                 ctxt.info.valid_sections |=
4597                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4598         } else if (type == I40E_VSI_FDIR) {
4599                 memset(&ctxt, 0, sizeof(ctxt));
4600                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4601                 ctxt.pf_num = hw->pf_id;
4602                 ctxt.vf_num = 0;
4603                 ctxt.uplink_seid = vsi->uplink_seid;
4604                 ctxt.connection_type = 0x1;     /* regular data port */
4605                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4606                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4607                                                 I40E_DEFAULT_TCMAP);
4608                 if (ret != I40E_SUCCESS) {
4609                         PMD_DRV_LOG(ERR, "Failed to configure "
4610                                         "TC queue mapping.");
4611                         goto fail_msix_alloc;
4612                 }
4613                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4614                 ctxt.info.valid_sections |=
4615                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4616         } else {
4617                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4618                 goto fail_msix_alloc;
4619         }
4620
4621         if (vsi->type != I40E_VSI_MAIN) {
4622                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4623                 if (ret != I40E_SUCCESS) {
4624                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4625                                     hw->aq.asq_last_status);
4626                         goto fail_msix_alloc;
4627                 }
4628                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4629                 vsi->info.valid_sections = 0;
4630                 vsi->seid = ctxt.seid;
4631                 vsi->vsi_id = ctxt.vsi_number;
4632                 vsi->sib_vsi_list.vsi = vsi;
4633                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4634                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4635                                           &vsi->sib_vsi_list, list);
4636                 } else {
4637                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4638                                           &vsi->sib_vsi_list, list);
4639                 }
4640         }
4641
4642         /* MAC/VLAN configuration */
4643         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4644         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4645
4646         ret = i40e_vsi_add_mac(vsi, &filter);
4647         if (ret != I40E_SUCCESS) {
4648                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4649                 goto fail_msix_alloc;
4650         }
4651
4652         /* Get VSI BW information */
4653         i40e_vsi_get_bw_config(vsi);
4654         return vsi;
4655 fail_msix_alloc:
4656         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4657 fail_queue_alloc:
4658         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4659 fail_mem:
4660         rte_free(vsi);
4661         return NULL;
4662 }
4663
4664 /* Configure vlan filter on or off */
4665 int
4666 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4667 {
4668         int i, num;
4669         struct i40e_mac_filter *f;
4670         struct i40e_mac_filter_info *mac_filter;
4671         enum rte_mac_filter_type desired_filter;
4672         int ret = I40E_SUCCESS;
4673
4674         if (on) {
4675                 /* Filter to match MAC and VLAN */
4676                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4677         } else {
4678                 /* Filter to match only MAC */
4679                 desired_filter = RTE_MAC_PERFECT_MATCH;
4680         }
4681
4682         num = vsi->mac_num;
4683
4684         mac_filter = rte_zmalloc("mac_filter_info_data",
4685                                  num * sizeof(*mac_filter), 0);
4686         if (mac_filter == NULL) {
4687                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4688                 return I40E_ERR_NO_MEMORY;
4689         }
4690
4691         i = 0;
4692
4693         /* Remove all existing mac */
4694         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4695                 mac_filter[i] = f->mac_info;
4696                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4697                 if (ret) {
4698                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4699                                     on ? "enable" : "disable");
4700                         goto DONE;
4701                 }
4702                 i++;
4703         }
4704
4705         /* Override with new filter */
4706         for (i = 0; i < num; i++) {
4707                 mac_filter[i].filter_type = desired_filter;
4708                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4709                 if (ret) {
4710                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4711                                     on ? "enable" : "disable");
4712                         goto DONE;
4713                 }
4714         }
4715
4716 DONE:
4717         rte_free(mac_filter);
4718         return ret;
4719 }
4720
4721 /* Configure vlan stripping on or off */
4722 int
4723 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4724 {
4725         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4726         struct i40e_vsi_context ctxt;
4727         uint8_t vlan_flags;
4728         int ret = I40E_SUCCESS;
4729
4730         /* Check if it has been already on or off */
4731         if (vsi->info.valid_sections &
4732                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4733                 if (on) {
4734                         if ((vsi->info.port_vlan_flags &
4735                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4736                                 return 0; /* already on */
4737                 } else {
4738                         if ((vsi->info.port_vlan_flags &
4739                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4740                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4741                                 return 0; /* already off */
4742                 }
4743         }
4744
4745         if (on)
4746                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4747         else
4748                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4749         vsi->info.valid_sections =
4750                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4751         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4752         vsi->info.port_vlan_flags |= vlan_flags;
4753         ctxt.seid = vsi->seid;
4754         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4755         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4756         if (ret)
4757                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4758                             on ? "enable" : "disable");
4759
4760         return ret;
4761 }
4762
4763 static int
4764 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4765 {
4766         struct rte_eth_dev_data *data = dev->data;
4767         int ret;
4768         int mask = 0;
4769
4770         /* Apply vlan offload setting */
4771         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4772         i40e_vlan_offload_set(dev, mask);
4773
4774         /* Apply double-vlan setting, not implemented yet */
4775
4776         /* Apply pvid setting */
4777         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4778                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4779         if (ret)
4780                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4781
4782         return ret;
4783 }
4784
4785 static int
4786 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4787 {
4788         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4789
4790         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4791 }
4792
4793 static int
4794 i40e_update_flow_control(struct i40e_hw *hw)
4795 {
4796 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4797         struct i40e_link_status link_status;
4798         uint32_t rxfc = 0, txfc = 0, reg;
4799         uint8_t an_info;
4800         int ret;
4801
4802         memset(&link_status, 0, sizeof(link_status));
4803         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4804         if (ret != I40E_SUCCESS) {
4805                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4806                 goto write_reg; /* Disable flow control */
4807         }
4808
4809         an_info = hw->phy.link_info.an_info;
4810         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4811                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4812                 ret = I40E_ERR_NOT_READY;
4813                 goto write_reg; /* Disable flow control */
4814         }
4815         /**
4816          * If link auto negotiation is enabled, flow control needs to
4817          * be configured according to it
4818          */
4819         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4820         case I40E_LINK_PAUSE_RXTX:
4821                 rxfc = 1;
4822                 txfc = 1;
4823                 hw->fc.current_mode = I40E_FC_FULL;
4824                 break;
4825         case I40E_AQ_LINK_PAUSE_RX:
4826                 rxfc = 1;
4827                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4828                 break;
4829         case I40E_AQ_LINK_PAUSE_TX:
4830                 txfc = 1;
4831                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4832                 break;
4833         default:
4834                 hw->fc.current_mode = I40E_FC_NONE;
4835                 break;
4836         }
4837
4838 write_reg:
4839         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4840                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4841         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4842         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4843         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4844         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4845
4846         return ret;
4847 }
4848
4849 /* PF setup */
4850 static int
4851 i40e_pf_setup(struct i40e_pf *pf)
4852 {
4853         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4854         struct i40e_filter_control_settings settings;
4855         struct i40e_vsi *vsi;
4856         int ret;
4857
4858         /* Clear all stats counters */
4859         pf->offset_loaded = FALSE;
4860         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4861         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4862
4863         ret = i40e_pf_get_switch_config(pf);
4864         if (ret != I40E_SUCCESS) {
4865                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4866                 return ret;
4867         }
4868         if (pf->flags & I40E_FLAG_FDIR) {
4869                 /* make queue allocated first, let FDIR use queue pair 0*/
4870                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4871                 if (ret != I40E_FDIR_QUEUE_ID) {
4872                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4873                                     " ret =%d", ret);
4874                         pf->flags &= ~I40E_FLAG_FDIR;
4875                 }
4876         }
4877         /*  main VSI setup */
4878         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4879         if (!vsi) {
4880                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4881                 return I40E_ERR_NOT_READY;
4882         }
4883         pf->main_vsi = vsi;
4884
4885         /* Configure filter control */
4886         memset(&settings, 0, sizeof(settings));
4887         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4888                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4889         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4890                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4891         else {
4892                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4893                                                 hw->func_caps.rss_table_size);
4894                 return I40E_ERR_PARAM;
4895         }
4896         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4897                         "size: %u\n", hw->func_caps.rss_table_size);
4898         pf->hash_lut_size = hw->func_caps.rss_table_size;
4899
4900         /* Enable ethtype and macvlan filters */
4901         settings.enable_ethtype = TRUE;
4902         settings.enable_macvlan = TRUE;
4903         ret = i40e_set_filter_control(hw, &settings);
4904         if (ret)
4905                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4906                                                                 ret);
4907
4908         /* Update flow control according to the auto negotiation */
4909         i40e_update_flow_control(hw);
4910
4911         return I40E_SUCCESS;
4912 }
4913
4914 int
4915 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4916 {
4917         uint32_t reg;
4918         uint16_t j;
4919
4920         /**
4921          * Set or clear TX Queue Disable flags,
4922          * which is required by hardware.
4923          */
4924         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4925         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4926
4927         /* Wait until the request is finished */
4928         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4929                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4930                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4931                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4932                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4933                                                         & 0x1))) {
4934                         break;
4935                 }
4936         }
4937         if (on) {
4938                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4939                         return I40E_SUCCESS; /* already on, skip next steps */
4940
4941                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4942                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4943         } else {
4944                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4945                         return I40E_SUCCESS; /* already off, skip next steps */
4946                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4947         }
4948         /* Write the register */
4949         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4950         /* Check the result */
4951         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4952                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4953                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4954                 if (on) {
4955                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4956                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4957                                 break;
4958                 } else {
4959                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4960                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4961                                 break;
4962                 }
4963         }
4964         /* Check if it is timeout */
4965         if (j >= I40E_CHK_Q_ENA_COUNT) {
4966                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4967                             (on ? "enable" : "disable"), q_idx);
4968                 return I40E_ERR_TIMEOUT;
4969         }
4970
4971         return I40E_SUCCESS;
4972 }
4973
4974 /* Swith on or off the tx queues */
4975 static int
4976 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4977 {
4978         struct rte_eth_dev_data *dev_data = pf->dev_data;
4979         struct i40e_tx_queue *txq;
4980         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4981         uint16_t i;
4982         int ret;
4983
4984         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4985                 txq = dev_data->tx_queues[i];
4986                 /* Don't operate the queue if not configured or
4987                  * if starting only per queue */
4988                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4989                         continue;
4990                 if (on)
4991                         ret = i40e_dev_tx_queue_start(dev, i);
4992                 else
4993                         ret = i40e_dev_tx_queue_stop(dev, i);
4994                 if ( ret != I40E_SUCCESS)
4995                         return ret;
4996         }
4997
4998         return I40E_SUCCESS;
4999 }
5000
5001 int
5002 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5003 {
5004         uint32_t reg;
5005         uint16_t j;
5006
5007         /* Wait until the request is finished */
5008         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5009                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5010                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5011                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5012                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5013                         break;
5014         }
5015
5016         if (on) {
5017                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5018                         return I40E_SUCCESS; /* Already on, skip next steps */
5019                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5020         } else {
5021                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5022                         return I40E_SUCCESS; /* Already off, skip next steps */
5023                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5024         }
5025
5026         /* Write the register */
5027         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5028         /* Check the result */
5029         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5030                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5031                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5032                 if (on) {
5033                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5034                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5035                                 break;
5036                 } else {
5037                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5038                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5039                                 break;
5040                 }
5041         }
5042
5043         /* Check if it is timeout */
5044         if (j >= I40E_CHK_Q_ENA_COUNT) {
5045                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5046                             (on ? "enable" : "disable"), q_idx);
5047                 return I40E_ERR_TIMEOUT;
5048         }
5049
5050         return I40E_SUCCESS;
5051 }
5052 /* Switch on or off the rx queues */
5053 static int
5054 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5055 {
5056         struct rte_eth_dev_data *dev_data = pf->dev_data;
5057         struct i40e_rx_queue *rxq;
5058         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5059         uint16_t i;
5060         int ret;
5061
5062         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5063                 rxq = dev_data->rx_queues[i];
5064                 /* Don't operate the queue if not configured or
5065                  * if starting only per queue */
5066                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5067                         continue;
5068                 if (on)
5069                         ret = i40e_dev_rx_queue_start(dev, i);
5070                 else
5071                         ret = i40e_dev_rx_queue_stop(dev, i);
5072                 if (ret != I40E_SUCCESS)
5073                         return ret;
5074         }
5075
5076         return I40E_SUCCESS;
5077 }
5078
5079 /* Switch on or off all the rx/tx queues */
5080 int
5081 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5082 {
5083         int ret;
5084
5085         if (on) {
5086                 /* enable rx queues before enabling tx queues */
5087                 ret = i40e_dev_switch_rx_queues(pf, on);
5088                 if (ret) {
5089                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5090                         return ret;
5091                 }
5092                 ret = i40e_dev_switch_tx_queues(pf, on);
5093         } else {
5094                 /* Stop tx queues before stopping rx queues */
5095                 ret = i40e_dev_switch_tx_queues(pf, on);
5096                 if (ret) {
5097                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5098                         return ret;
5099                 }
5100                 ret = i40e_dev_switch_rx_queues(pf, on);
5101         }
5102
5103         return ret;
5104 }
5105
5106 /* Initialize VSI for TX */
5107 static int
5108 i40e_dev_tx_init(struct i40e_pf *pf)
5109 {
5110         struct rte_eth_dev_data *data = pf->dev_data;
5111         uint16_t i;
5112         uint32_t ret = I40E_SUCCESS;
5113         struct i40e_tx_queue *txq;
5114
5115         for (i = 0; i < data->nb_tx_queues; i++) {
5116                 txq = data->tx_queues[i];
5117                 if (!txq || !txq->q_set)
5118                         continue;
5119                 ret = i40e_tx_queue_init(txq);
5120                 if (ret != I40E_SUCCESS)
5121                         break;
5122         }
5123         if (ret == I40E_SUCCESS)
5124                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5125                                      ->eth_dev);
5126
5127         return ret;
5128 }
5129
5130 /* Initialize VSI for RX */
5131 static int
5132 i40e_dev_rx_init(struct i40e_pf *pf)
5133 {
5134         struct rte_eth_dev_data *data = pf->dev_data;
5135         int ret = I40E_SUCCESS;
5136         uint16_t i;
5137         struct i40e_rx_queue *rxq;
5138
5139         i40e_pf_config_mq_rx(pf);
5140         for (i = 0; i < data->nb_rx_queues; i++) {
5141                 rxq = data->rx_queues[i];
5142                 if (!rxq || !rxq->q_set)
5143                         continue;
5144
5145                 ret = i40e_rx_queue_init(rxq);
5146                 if (ret != I40E_SUCCESS) {
5147                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5148                                     "initialization");
5149                         break;
5150                 }
5151         }
5152         if (ret == I40E_SUCCESS)
5153                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5154                                      ->eth_dev);
5155
5156         return ret;
5157 }
5158
5159 static int
5160 i40e_dev_rxtx_init(struct i40e_pf *pf)
5161 {
5162         int err;
5163
5164         err = i40e_dev_tx_init(pf);
5165         if (err) {
5166                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5167                 return err;
5168         }
5169         err = i40e_dev_rx_init(pf);
5170         if (err) {
5171                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5172                 return err;
5173         }
5174
5175         return err;
5176 }
5177
5178 static int
5179 i40e_vmdq_setup(struct rte_eth_dev *dev)
5180 {
5181         struct rte_eth_conf *conf = &dev->data->dev_conf;
5182         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5183         int i, err, conf_vsis, j, loop;
5184         struct i40e_vsi *vsi;
5185         struct i40e_vmdq_info *vmdq_info;
5186         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5187         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5188
5189         /*
5190          * Disable interrupt to avoid message from VF. Furthermore, it will
5191          * avoid race condition in VSI creation/destroy.
5192          */
5193         i40e_pf_disable_irq0(hw);
5194
5195         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5196                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5197                 return -ENOTSUP;
5198         }
5199
5200         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5201         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5202                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5203                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5204                         pf->max_nb_vmdq_vsi);
5205                 return -ENOTSUP;
5206         }
5207
5208         if (pf->vmdq != NULL) {
5209                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5210                 return 0;
5211         }
5212
5213         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5214                                 sizeof(*vmdq_info) * conf_vsis, 0);
5215
5216         if (pf->vmdq == NULL) {
5217                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5218                 return -ENOMEM;
5219         }
5220
5221         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5222
5223         /* Create VMDQ VSI */
5224         for (i = 0; i < conf_vsis; i++) {
5225                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5226                                 vmdq_conf->enable_loop_back);
5227                 if (vsi == NULL) {
5228                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5229                         err = -1;
5230                         goto err_vsi_setup;
5231                 }
5232                 vmdq_info = &pf->vmdq[i];
5233                 vmdq_info->pf = pf;
5234                 vmdq_info->vsi = vsi;
5235         }
5236         pf->nb_cfg_vmdq_vsi = conf_vsis;
5237
5238         /* Configure Vlan */
5239         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5240         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5241                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5242                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5243                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5244                                         vmdq_conf->pool_map[i].vlan_id, j);
5245
5246                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5247                                                 vmdq_conf->pool_map[i].vlan_id);
5248                                 if (err) {
5249                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5250                                         err = -1;
5251                                         goto err_vsi_setup;
5252                                 }
5253                         }
5254                 }
5255         }
5256
5257         i40e_pf_enable_irq0(hw);
5258
5259         return 0;
5260
5261 err_vsi_setup:
5262         for (i = 0; i < conf_vsis; i++)
5263                 if (pf->vmdq[i].vsi == NULL)
5264                         break;
5265                 else
5266                         i40e_vsi_release(pf->vmdq[i].vsi);
5267
5268         rte_free(pf->vmdq);
5269         pf->vmdq = NULL;
5270         i40e_pf_enable_irq0(hw);
5271         return err;
5272 }
5273
5274 static void
5275 i40e_stat_update_32(struct i40e_hw *hw,
5276                    uint32_t reg,
5277                    bool offset_loaded,
5278                    uint64_t *offset,
5279                    uint64_t *stat)
5280 {
5281         uint64_t new_data;
5282
5283         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5284         if (!offset_loaded)
5285                 *offset = new_data;
5286
5287         if (new_data >= *offset)
5288                 *stat = (uint64_t)(new_data - *offset);
5289         else
5290                 *stat = (uint64_t)((new_data +
5291                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5292 }
5293
5294 static void
5295 i40e_stat_update_48(struct i40e_hw *hw,
5296                    uint32_t hireg,
5297                    uint32_t loreg,
5298                    bool offset_loaded,
5299                    uint64_t *offset,
5300                    uint64_t *stat)
5301 {
5302         uint64_t new_data;
5303
5304         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5305         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5306                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5307
5308         if (!offset_loaded)
5309                 *offset = new_data;
5310
5311         if (new_data >= *offset)
5312                 *stat = new_data - *offset;
5313         else
5314                 *stat = (uint64_t)((new_data +
5315                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5316
5317         *stat &= I40E_48_BIT_MASK;
5318 }
5319
5320 /* Disable IRQ0 */
5321 void
5322 i40e_pf_disable_irq0(struct i40e_hw *hw)
5323 {
5324         /* Disable all interrupt types */
5325         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5326         I40E_WRITE_FLUSH(hw);
5327 }
5328
5329 /* Enable IRQ0 */
5330 void
5331 i40e_pf_enable_irq0(struct i40e_hw *hw)
5332 {
5333         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5334                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5335                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5336                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5337         I40E_WRITE_FLUSH(hw);
5338 }
5339
5340 static void
5341 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5342 {
5343         /* read pending request and disable first */
5344         i40e_pf_disable_irq0(hw);
5345         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5346         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5347                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5348
5349         if (no_queue)
5350                 /* Link no queues with irq0 */
5351                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5352                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5353 }
5354
5355 static void
5356 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5357 {
5358         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5359         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5360         int i;
5361         uint16_t abs_vf_id;
5362         uint32_t index, offset, val;
5363
5364         if (!pf->vfs)
5365                 return;
5366         /**
5367          * Try to find which VF trigger a reset, use absolute VF id to access
5368          * since the reg is global register.
5369          */
5370         for (i = 0; i < pf->vf_num; i++) {
5371                 abs_vf_id = hw->func_caps.vf_base_id + i;
5372                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5373                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5374                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5375                 /* VFR event occured */
5376                 if (val & (0x1 << offset)) {
5377                         int ret;
5378
5379                         /* Clear the event first */
5380                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5381                                                         (0x1 << offset));
5382                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5383                         /**
5384                          * Only notify a VF reset event occured,
5385                          * don't trigger another SW reset
5386                          */
5387                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5388                         if (ret != I40E_SUCCESS)
5389                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5390                 }
5391         }
5392 }
5393
5394 static void
5395 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5396 {
5397         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5398         struct i40e_arq_event_info info;
5399         uint16_t pending, opcode;
5400         int ret;
5401
5402         info.buf_len = I40E_AQ_BUF_SZ;
5403         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5404         if (!info.msg_buf) {
5405                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5406                 return;
5407         }
5408
5409         pending = 1;
5410         while (pending) {
5411                 ret = i40e_clean_arq_element(hw, &info, &pending);
5412
5413                 if (ret != I40E_SUCCESS) {
5414                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5415                                     "aq_err: %u", hw->aq.asq_last_status);
5416                         break;
5417                 }
5418                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5419
5420                 switch (opcode) {
5421                 case i40e_aqc_opc_send_msg_to_pf:
5422                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5423                         i40e_pf_host_handle_vf_msg(dev,
5424                                         rte_le_to_cpu_16(info.desc.retval),
5425                                         rte_le_to_cpu_32(info.desc.cookie_high),
5426                                         rte_le_to_cpu_32(info.desc.cookie_low),
5427                                         info.msg_buf,
5428                                         info.msg_len);
5429                         break;
5430                 default:
5431                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5432                                     opcode);
5433                         break;
5434                 }
5435         }
5436         rte_free(info.msg_buf);
5437 }
5438
5439 /*
5440  * Interrupt handler is registered as the alarm callback for handling LSC
5441  * interrupt in a definite of time, in order to wait the NIC into a stable
5442  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5443  * no need for link down interrupt.
5444  */
5445 static void
5446 i40e_dev_interrupt_delayed_handler(void *param)
5447 {
5448         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5449         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5450         uint32_t icr0;
5451
5452         /* read interrupt causes again */
5453         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5454
5455 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5456         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5457                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5458         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5459                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5460         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5461                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5462         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5463                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5464         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5465                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5466                                                                 "state\n");
5467         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5468                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5469         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5470                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5471 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5472
5473         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5474                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5475                 i40e_dev_handle_vfr_event(dev);
5476         }
5477         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5478                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5479                 i40e_dev_handle_aq_msg(dev);
5480         }
5481
5482         /* handle the link up interrupt in an alarm callback */
5483         i40e_dev_link_update(dev, 0);
5484         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5485
5486         i40e_pf_enable_irq0(hw);
5487         rte_intr_enable(&(dev->pci_dev->intr_handle));
5488 }
5489
5490 /**
5491  * Interrupt handler triggered by NIC  for handling
5492  * specific interrupt.
5493  *
5494  * @param handle
5495  *  Pointer to interrupt handle.
5496  * @param param
5497  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5498  *
5499  * @return
5500  *  void
5501  */
5502 static void
5503 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5504                            void *param)
5505 {
5506         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5507         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5508         uint32_t icr0;
5509
5510         /* Disable interrupt */
5511         i40e_pf_disable_irq0(hw);
5512
5513         /* read out interrupt causes */
5514         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5515
5516         /* No interrupt event indicated */
5517         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5518                 PMD_DRV_LOG(INFO, "No interrupt event");
5519                 goto done;
5520         }
5521 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5522         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5523                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5524         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5525                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5526         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5527                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5528         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5529                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5530         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5531                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5532         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5533                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5534         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5535                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5536 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5537
5538         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5539                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5540                 i40e_dev_handle_vfr_event(dev);
5541         }
5542         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5543                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5544                 i40e_dev_handle_aq_msg(dev);
5545         }
5546
5547         /* Link Status Change interrupt */
5548         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5549 #define I40E_US_PER_SECOND 1000000
5550                 struct rte_eth_link link;
5551
5552                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5553                 memset(&link, 0, sizeof(link));
5554                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5555                 i40e_dev_link_update(dev, 0);
5556
5557                 /*
5558                  * For link up interrupt, it needs to wait 1 second to let the
5559                  * hardware be a stable state. Otherwise several consecutive
5560                  * interrupts can be observed.
5561                  * For link down interrupt, no need to wait.
5562                  */
5563                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5564                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5565                         return;
5566                 else
5567                         _rte_eth_dev_callback_process(dev,
5568                                 RTE_ETH_EVENT_INTR_LSC);
5569         }
5570
5571 done:
5572         /* Enable interrupt */
5573         i40e_pf_enable_irq0(hw);
5574         rte_intr_enable(&(dev->pci_dev->intr_handle));
5575 }
5576
5577 static int
5578 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5579                          struct i40e_macvlan_filter *filter,
5580                          int total)
5581 {
5582         int ele_num, ele_buff_size;
5583         int num, actual_num, i;
5584         uint16_t flags;
5585         int ret = I40E_SUCCESS;
5586         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5587         struct i40e_aqc_add_macvlan_element_data *req_list;
5588
5589         if (filter == NULL  || total == 0)
5590                 return I40E_ERR_PARAM;
5591         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5592         ele_buff_size = hw->aq.asq_buf_size;
5593
5594         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5595         if (req_list == NULL) {
5596                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5597                 return I40E_ERR_NO_MEMORY;
5598         }
5599
5600         num = 0;
5601         do {
5602                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5603                 memset(req_list, 0, ele_buff_size);
5604
5605                 for (i = 0; i < actual_num; i++) {
5606                         (void)rte_memcpy(req_list[i].mac_addr,
5607                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5608                         req_list[i].vlan_tag =
5609                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5610
5611                         switch (filter[num + i].filter_type) {
5612                         case RTE_MAC_PERFECT_MATCH:
5613                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5614                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5615                                 break;
5616                         case RTE_MACVLAN_PERFECT_MATCH:
5617                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5618                                 break;
5619                         case RTE_MAC_HASH_MATCH:
5620                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5621                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5622                                 break;
5623                         case RTE_MACVLAN_HASH_MATCH:
5624                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5625                                 break;
5626                         default:
5627                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5628                                 ret = I40E_ERR_PARAM;
5629                                 goto DONE;
5630                         }
5631
5632                         req_list[i].queue_number = 0;
5633
5634                         req_list[i].flags = rte_cpu_to_le_16(flags);
5635                 }
5636
5637                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5638                                                 actual_num, NULL);
5639                 if (ret != I40E_SUCCESS) {
5640                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5641                         goto DONE;
5642                 }
5643                 num += actual_num;
5644         } while (num < total);
5645
5646 DONE:
5647         rte_free(req_list);
5648         return ret;
5649 }
5650
5651 static int
5652 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5653                             struct i40e_macvlan_filter *filter,
5654                             int total)
5655 {
5656         int ele_num, ele_buff_size;
5657         int num, actual_num, i;
5658         uint16_t flags;
5659         int ret = I40E_SUCCESS;
5660         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5661         struct i40e_aqc_remove_macvlan_element_data *req_list;
5662
5663         if (filter == NULL  || total == 0)
5664                 return I40E_ERR_PARAM;
5665
5666         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5667         ele_buff_size = hw->aq.asq_buf_size;
5668
5669         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5670         if (req_list == NULL) {
5671                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5672                 return I40E_ERR_NO_MEMORY;
5673         }
5674
5675         num = 0;
5676         do {
5677                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5678                 memset(req_list, 0, ele_buff_size);
5679
5680                 for (i = 0; i < actual_num; i++) {
5681                         (void)rte_memcpy(req_list[i].mac_addr,
5682                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5683                         req_list[i].vlan_tag =
5684                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5685
5686                         switch (filter[num + i].filter_type) {
5687                         case RTE_MAC_PERFECT_MATCH:
5688                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5689                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5690                                 break;
5691                         case RTE_MACVLAN_PERFECT_MATCH:
5692                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5693                                 break;
5694                         case RTE_MAC_HASH_MATCH:
5695                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5696                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5697                                 break;
5698                         case RTE_MACVLAN_HASH_MATCH:
5699                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5700                                 break;
5701                         default:
5702                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5703                                 ret = I40E_ERR_PARAM;
5704                                 goto DONE;
5705                         }
5706                         req_list[i].flags = rte_cpu_to_le_16(flags);
5707                 }
5708
5709                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5710                                                 actual_num, NULL);
5711                 if (ret != I40E_SUCCESS) {
5712                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5713                         goto DONE;
5714                 }
5715                 num += actual_num;
5716         } while (num < total);
5717
5718 DONE:
5719         rte_free(req_list);
5720         return ret;
5721 }
5722
5723 /* Find out specific MAC filter */
5724 static struct i40e_mac_filter *
5725 i40e_find_mac_filter(struct i40e_vsi *vsi,
5726                          struct ether_addr *macaddr)
5727 {
5728         struct i40e_mac_filter *f;
5729
5730         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5731                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5732                         return f;
5733         }
5734
5735         return NULL;
5736 }
5737
5738 static bool
5739 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5740                          uint16_t vlan_id)
5741 {
5742         uint32_t vid_idx, vid_bit;
5743
5744         if (vlan_id > ETH_VLAN_ID_MAX)
5745                 return 0;
5746
5747         vid_idx = I40E_VFTA_IDX(vlan_id);
5748         vid_bit = I40E_VFTA_BIT(vlan_id);
5749
5750         if (vsi->vfta[vid_idx] & vid_bit)
5751                 return 1;
5752         else
5753                 return 0;
5754 }
5755
5756 static void
5757 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5758                          uint16_t vlan_id, bool on)
5759 {
5760         uint32_t vid_idx, vid_bit;
5761         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5762         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
5763         int ret;
5764
5765         if (vlan_id > ETH_VLAN_ID_MAX)
5766                 return;
5767
5768         vid_idx = I40E_VFTA_IDX(vlan_id);
5769         vid_bit = I40E_VFTA_BIT(vlan_id);
5770         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
5771
5772         if (on) {
5773                 ret = i40e_aq_add_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
5774                 if (ret != I40E_SUCCESS)
5775                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
5776                 vsi->vfta[vid_idx] |= vid_bit;
5777         } else {
5778                 ret = i40e_aq_remove_vlan(hw, vsi->seid, &vlan_data, 1, NULL);
5779                 if (ret != I40E_SUCCESS)
5780                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
5781                 vsi->vfta[vid_idx] &= ~vid_bit;
5782         }
5783 }
5784
5785 /**
5786  * Find all vlan options for specific mac addr,
5787  * return with actual vlan found.
5788  */
5789 static inline int
5790 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5791                            struct i40e_macvlan_filter *mv_f,
5792                            int num, struct ether_addr *addr)
5793 {
5794         int i;
5795         uint32_t j, k;
5796
5797         /**
5798          * Not to use i40e_find_vlan_filter to decrease the loop time,
5799          * although the code looks complex.
5800           */
5801         if (num < vsi->vlan_num)
5802                 return I40E_ERR_PARAM;
5803
5804         i = 0;
5805         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5806                 if (vsi->vfta[j]) {
5807                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5808                                 if (vsi->vfta[j] & (1 << k)) {
5809                                         if (i > num - 1) {
5810                                                 PMD_DRV_LOG(ERR, "vlan number "
5811                                                             "not match");
5812                                                 return I40E_ERR_PARAM;
5813                                         }
5814                                         (void)rte_memcpy(&mv_f[i].macaddr,
5815                                                         addr, ETH_ADDR_LEN);
5816                                         mv_f[i].vlan_id =
5817                                                 j * I40E_UINT32_BIT_SIZE + k;
5818                                         i++;
5819                                 }
5820                         }
5821                 }
5822         }
5823         return I40E_SUCCESS;
5824 }
5825
5826 static inline int
5827 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5828                            struct i40e_macvlan_filter *mv_f,
5829                            int num,
5830                            uint16_t vlan)
5831 {
5832         int i = 0;
5833         struct i40e_mac_filter *f;
5834
5835         if (num < vsi->mac_num)
5836                 return I40E_ERR_PARAM;
5837
5838         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5839                 if (i > num - 1) {
5840                         PMD_DRV_LOG(ERR, "buffer number not match");
5841                         return I40E_ERR_PARAM;
5842                 }
5843                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5844                                 ETH_ADDR_LEN);
5845                 mv_f[i].vlan_id = vlan;
5846                 mv_f[i].filter_type = f->mac_info.filter_type;
5847                 i++;
5848         }
5849
5850         return I40E_SUCCESS;
5851 }
5852
5853 static int
5854 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5855 {
5856         int i, num;
5857         struct i40e_mac_filter *f;
5858         struct i40e_macvlan_filter *mv_f;
5859         int ret = I40E_SUCCESS;
5860
5861         if (vsi == NULL || vsi->mac_num == 0)
5862                 return I40E_ERR_PARAM;
5863
5864         /* Case that no vlan is set */
5865         if (vsi->vlan_num == 0)
5866                 num = vsi->mac_num;
5867         else
5868                 num = vsi->mac_num * vsi->vlan_num;
5869
5870         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5871         if (mv_f == NULL) {
5872                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5873                 return I40E_ERR_NO_MEMORY;
5874         }
5875
5876         i = 0;
5877         if (vsi->vlan_num == 0) {
5878                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5879                         (void)rte_memcpy(&mv_f[i].macaddr,
5880                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5881                         mv_f[i].vlan_id = 0;
5882                         i++;
5883                 }
5884         } else {
5885                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5886                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5887                                         vsi->vlan_num, &f->mac_info.mac_addr);
5888                         if (ret != I40E_SUCCESS)
5889                                 goto DONE;
5890                         i += vsi->vlan_num;
5891                 }
5892         }
5893
5894         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5895 DONE:
5896         rte_free(mv_f);
5897
5898         return ret;
5899 }
5900
5901 int
5902 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5903 {
5904         struct i40e_macvlan_filter *mv_f;
5905         int mac_num;
5906         int ret = I40E_SUCCESS;
5907
5908         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5909                 return I40E_ERR_PARAM;
5910
5911         /* If it's already set, just return */
5912         if (i40e_find_vlan_filter(vsi,vlan))
5913                 return I40E_SUCCESS;
5914
5915         mac_num = vsi->mac_num;
5916
5917         if (mac_num == 0) {
5918                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5919                 return I40E_ERR_PARAM;
5920         }
5921
5922         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5923
5924         if (mv_f == NULL) {
5925                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5926                 return I40E_ERR_NO_MEMORY;
5927         }
5928
5929         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5930
5931         if (ret != I40E_SUCCESS)
5932                 goto DONE;
5933
5934         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5935
5936         if (ret != I40E_SUCCESS)
5937                 goto DONE;
5938
5939         i40e_set_vlan_filter(vsi, vlan, 1);
5940
5941         vsi->vlan_num++;
5942         ret = I40E_SUCCESS;
5943 DONE:
5944         rte_free(mv_f);
5945         return ret;
5946 }
5947
5948 int
5949 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5950 {
5951         struct i40e_macvlan_filter *mv_f;
5952         int mac_num;
5953         int ret = I40E_SUCCESS;
5954
5955         /**
5956          * Vlan 0 is the generic filter for untagged packets
5957          * and can't be removed.
5958          */
5959         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5960                 return I40E_ERR_PARAM;
5961
5962         /* If can't find it, just return */
5963         if (!i40e_find_vlan_filter(vsi, vlan))
5964                 return I40E_ERR_PARAM;
5965
5966         mac_num = vsi->mac_num;
5967
5968         if (mac_num == 0) {
5969                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5970                 return I40E_ERR_PARAM;
5971         }
5972
5973         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5974
5975         if (mv_f == NULL) {
5976                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5977                 return I40E_ERR_NO_MEMORY;
5978         }
5979
5980         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5981
5982         if (ret != I40E_SUCCESS)
5983                 goto DONE;
5984
5985         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5986
5987         if (ret != I40E_SUCCESS)
5988                 goto DONE;
5989
5990         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5991         if (vsi->vlan_num == 1) {
5992                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5993                 if (ret != I40E_SUCCESS)
5994                         goto DONE;
5995
5996                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5997                 if (ret != I40E_SUCCESS)
5998                         goto DONE;
5999         }
6000
6001         i40e_set_vlan_filter(vsi, vlan, 0);
6002
6003         vsi->vlan_num--;
6004         ret = I40E_SUCCESS;
6005 DONE:
6006         rte_free(mv_f);
6007         return ret;
6008 }
6009
6010 int
6011 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6012 {
6013         struct i40e_mac_filter *f;
6014         struct i40e_macvlan_filter *mv_f;
6015         int i, vlan_num = 0;
6016         int ret = I40E_SUCCESS;
6017
6018         /* If it's add and we've config it, return */
6019         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6020         if (f != NULL)
6021                 return I40E_SUCCESS;
6022         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6023                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6024
6025                 /**
6026                  * If vlan_num is 0, that's the first time to add mac,
6027                  * set mask for vlan_id 0.
6028                  */
6029                 if (vsi->vlan_num == 0) {
6030                         i40e_set_vlan_filter(vsi, 0, 1);
6031                         vsi->vlan_num = 1;
6032                 }
6033                 vlan_num = vsi->vlan_num;
6034         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6035                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6036                 vlan_num = 1;
6037
6038         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6039         if (mv_f == NULL) {
6040                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6041                 return I40E_ERR_NO_MEMORY;
6042         }
6043
6044         for (i = 0; i < vlan_num; i++) {
6045                 mv_f[i].filter_type = mac_filter->filter_type;
6046                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6047                                 ETH_ADDR_LEN);
6048         }
6049
6050         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6051                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6052                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6053                                         &mac_filter->mac_addr);
6054                 if (ret != I40E_SUCCESS)
6055                         goto DONE;
6056         }
6057
6058         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6059         if (ret != I40E_SUCCESS)
6060                 goto DONE;
6061
6062         /* Add the mac addr into mac list */
6063         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6064         if (f == NULL) {
6065                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6066                 ret = I40E_ERR_NO_MEMORY;
6067                 goto DONE;
6068         }
6069         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6070                         ETH_ADDR_LEN);
6071         f->mac_info.filter_type = mac_filter->filter_type;
6072         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6073         vsi->mac_num++;
6074
6075         ret = I40E_SUCCESS;
6076 DONE:
6077         rte_free(mv_f);
6078
6079         return ret;
6080 }
6081
6082 int
6083 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6084 {
6085         struct i40e_mac_filter *f;
6086         struct i40e_macvlan_filter *mv_f;
6087         int i, vlan_num;
6088         enum rte_mac_filter_type filter_type;
6089         int ret = I40E_SUCCESS;
6090
6091         /* Can't find it, return an error */
6092         f = i40e_find_mac_filter(vsi, addr);
6093         if (f == NULL)
6094                 return I40E_ERR_PARAM;
6095
6096         vlan_num = vsi->vlan_num;
6097         filter_type = f->mac_info.filter_type;
6098         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6099                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6100                 if (vlan_num == 0) {
6101                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6102                         return I40E_ERR_PARAM;
6103                 }
6104         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6105                         filter_type == RTE_MAC_HASH_MATCH)
6106                 vlan_num = 1;
6107
6108         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6109         if (mv_f == NULL) {
6110                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6111                 return I40E_ERR_NO_MEMORY;
6112         }
6113
6114         for (i = 0; i < vlan_num; i++) {
6115                 mv_f[i].filter_type = filter_type;
6116                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6117                                 ETH_ADDR_LEN);
6118         }
6119         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6120                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6121                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6122                 if (ret != I40E_SUCCESS)
6123                         goto DONE;
6124         }
6125
6126         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6127         if (ret != I40E_SUCCESS)
6128                 goto DONE;
6129
6130         /* Remove the mac addr into mac list */
6131         TAILQ_REMOVE(&vsi->mac_list, f, next);
6132         rte_free(f);
6133         vsi->mac_num--;
6134
6135         ret = I40E_SUCCESS;
6136 DONE:
6137         rte_free(mv_f);
6138         return ret;
6139 }
6140
6141 /* Configure hash enable flags for RSS */
6142 uint64_t
6143 i40e_config_hena(uint64_t flags)
6144 {
6145         uint64_t hena = 0;
6146
6147         if (!flags)
6148                 return hena;
6149
6150         if (flags & ETH_RSS_FRAG_IPV4)
6151                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6152         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6153                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6154         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6155                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6156         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6157                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6158         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6159                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6160         if (flags & ETH_RSS_FRAG_IPV6)
6161                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6162         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6163                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6164         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6165                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6166         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6167                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6168         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6169                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6170         if (flags & ETH_RSS_L2_PAYLOAD)
6171                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6172
6173         return hena;
6174 }
6175
6176 /* Parse the hash enable flags */
6177 uint64_t
6178 i40e_parse_hena(uint64_t flags)
6179 {
6180         uint64_t rss_hf = 0;
6181
6182         if (!flags)
6183                 return rss_hf;
6184         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6185                 rss_hf |= ETH_RSS_FRAG_IPV4;
6186         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6187                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6188         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6189                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6190         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6191                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6192         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6193                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6194         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6195                 rss_hf |= ETH_RSS_FRAG_IPV6;
6196         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6197                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6198         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6199                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6200         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6201                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6202         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6203                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6204         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6205                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6206
6207         return rss_hf;
6208 }
6209
6210 /* Disable RSS */
6211 static void
6212 i40e_pf_disable_rss(struct i40e_pf *pf)
6213 {
6214         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6215         uint64_t hena;
6216
6217         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6218         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6219         hena &= ~I40E_RSS_HENA_ALL;
6220         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6221         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6222         I40E_WRITE_FLUSH(hw);
6223 }
6224
6225 static int
6226 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6227 {
6228         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6229         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6230         int ret = 0;
6231
6232         if (!key || key_len == 0) {
6233                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6234                 return 0;
6235         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6236                 sizeof(uint32_t)) {
6237                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6238                 return -EINVAL;
6239         }
6240
6241         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6242                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6243                         (struct i40e_aqc_get_set_rss_key_data *)key;
6244
6245                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6246                 if (ret)
6247                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6248                                      "via AQ");
6249         } else {
6250                 uint32_t *hash_key = (uint32_t *)key;
6251                 uint16_t i;
6252
6253                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6254                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6255                 I40E_WRITE_FLUSH(hw);
6256         }
6257
6258         return ret;
6259 }
6260
6261 static int
6262 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6263 {
6264         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6265         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6266         int ret;
6267
6268         if (!key || !key_len)
6269                 return -EINVAL;
6270
6271         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6272                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6273                         (struct i40e_aqc_get_set_rss_key_data *)key);
6274                 if (ret) {
6275                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6276                         return ret;
6277                 }
6278         } else {
6279                 uint32_t *key_dw = (uint32_t *)key;
6280                 uint16_t i;
6281
6282                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6283                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6284         }
6285         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6286
6287         return 0;
6288 }
6289
6290 static int
6291 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6292 {
6293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6294         uint64_t rss_hf;
6295         uint64_t hena;
6296         int ret;
6297
6298         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6299                                rss_conf->rss_key_len);
6300         if (ret)
6301                 return ret;
6302
6303         rss_hf = rss_conf->rss_hf;
6304         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6305         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6306         hena &= ~I40E_RSS_HENA_ALL;
6307         hena |= i40e_config_hena(rss_hf);
6308         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6309         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6310         I40E_WRITE_FLUSH(hw);
6311
6312         return 0;
6313 }
6314
6315 static int
6316 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6317                          struct rte_eth_rss_conf *rss_conf)
6318 {
6319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6320         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6321         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6322         uint64_t hena;
6323
6324         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6325         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6326         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6327                 if (rss_hf != 0) /* Enable RSS */
6328                         return -EINVAL;
6329                 return 0; /* Nothing to do */
6330         }
6331         /* RSS enabled */
6332         if (rss_hf == 0) /* Disable RSS */
6333                 return -EINVAL;
6334
6335         return i40e_hw_rss_hash_set(pf, rss_conf);
6336 }
6337
6338 static int
6339 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6340                            struct rte_eth_rss_conf *rss_conf)
6341 {
6342         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6343         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6344         uint64_t hena;
6345
6346         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6347                          &rss_conf->rss_key_len);
6348
6349         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6350         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6351         rss_conf->rss_hf = i40e_parse_hena(hena);
6352
6353         return 0;
6354 }
6355
6356 static int
6357 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6358 {
6359         switch (filter_type) {
6360         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6361                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6362                 break;
6363         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6364                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6365                 break;
6366         case RTE_TUNNEL_FILTER_IMAC_TENID:
6367                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6368                 break;
6369         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6370                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6371                 break;
6372         case ETH_TUNNEL_FILTER_IMAC:
6373                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6374                 break;
6375         case ETH_TUNNEL_FILTER_OIP:
6376                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6377                 break;
6378         case ETH_TUNNEL_FILTER_IIP:
6379                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6380                 break;
6381         default:
6382                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6383                 return -EINVAL;
6384         }
6385
6386         return 0;
6387 }
6388
6389 static int
6390 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6391                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6392                         uint8_t add)
6393 {
6394         uint16_t ip_type;
6395         uint32_t ipv4_addr;
6396         uint8_t i, tun_type = 0;
6397         /* internal varialbe to convert ipv6 byte order */
6398         uint32_t convert_ipv6[4];
6399         int val, ret = 0;
6400         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6401         struct i40e_vsi *vsi = pf->main_vsi;
6402         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6403         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6404
6405         cld_filter = rte_zmalloc("tunnel_filter",
6406                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6407                 0);
6408
6409         if (NULL == cld_filter) {
6410                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6411                 return -EINVAL;
6412         }
6413         pfilter = cld_filter;
6414
6415         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6416         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6417
6418         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6419         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6420                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6421                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6422                 rte_memcpy(&pfilter->ipaddr.v4.data,
6423                                 &rte_cpu_to_le_32(ipv4_addr),
6424                                 sizeof(pfilter->ipaddr.v4.data));
6425         } else {
6426                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6427                 for (i = 0; i < 4; i++) {
6428                         convert_ipv6[i] =
6429                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6430                 }
6431                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6432                                 sizeof(pfilter->ipaddr.v6.data));
6433         }
6434
6435         /* check tunneled type */
6436         switch (tunnel_filter->tunnel_type) {
6437         case RTE_TUNNEL_TYPE_VXLAN:
6438                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6439                 break;
6440         case RTE_TUNNEL_TYPE_NVGRE:
6441                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6442                 break;
6443         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6444                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6445                 break;
6446         default:
6447                 /* Other tunnel types is not supported. */
6448                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6449                 rte_free(cld_filter);
6450                 return -EINVAL;
6451         }
6452
6453         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6454                                                 &pfilter->flags);
6455         if (val < 0) {
6456                 rte_free(cld_filter);
6457                 return -EINVAL;
6458         }
6459
6460         pfilter->flags |= rte_cpu_to_le_16(
6461                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6462                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6463         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6464         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6465
6466         if (add)
6467                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6468         else
6469                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6470                                                 cld_filter, 1);
6471
6472         rte_free(cld_filter);
6473         return ret;
6474 }
6475
6476 static int
6477 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6478 {
6479         uint8_t i;
6480
6481         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6482                 if (pf->vxlan_ports[i] == port)
6483                         return i;
6484         }
6485
6486         return -1;
6487 }
6488
6489 static int
6490 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6491 {
6492         int  idx, ret;
6493         uint8_t filter_idx;
6494         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6495
6496         idx = i40e_get_vxlan_port_idx(pf, port);
6497
6498         /* Check if port already exists */
6499         if (idx >= 0) {
6500                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6501                 return -EINVAL;
6502         }
6503
6504         /* Now check if there is space to add the new port */
6505         idx = i40e_get_vxlan_port_idx(pf, 0);
6506         if (idx < 0) {
6507                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6508                         "not adding port %d", port);
6509                 return -ENOSPC;
6510         }
6511
6512         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6513                                         &filter_idx, NULL);
6514         if (ret < 0) {
6515                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6516                 return -1;
6517         }
6518
6519         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6520                          port,  filter_idx);
6521
6522         /* New port: add it and mark its index in the bitmap */
6523         pf->vxlan_ports[idx] = port;
6524         pf->vxlan_bitmap |= (1 << idx);
6525
6526         if (!(pf->flags & I40E_FLAG_VXLAN))
6527                 pf->flags |= I40E_FLAG_VXLAN;
6528
6529         return 0;
6530 }
6531
6532 static int
6533 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6534 {
6535         int idx;
6536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6537
6538         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6539                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6540                 return -EINVAL;
6541         }
6542
6543         idx = i40e_get_vxlan_port_idx(pf, port);
6544
6545         if (idx < 0) {
6546                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6547                 return -EINVAL;
6548         }
6549
6550         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6551                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6552                 return -1;
6553         }
6554
6555         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6556                         port, idx);
6557
6558         pf->vxlan_ports[idx] = 0;
6559         pf->vxlan_bitmap &= ~(1 << idx);
6560
6561         if (!pf->vxlan_bitmap)
6562                 pf->flags &= ~I40E_FLAG_VXLAN;
6563
6564         return 0;
6565 }
6566
6567 /* Add UDP tunneling port */
6568 static int
6569 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6570                              struct rte_eth_udp_tunnel *udp_tunnel)
6571 {
6572         int ret = 0;
6573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6574
6575         if (udp_tunnel == NULL)
6576                 return -EINVAL;
6577
6578         switch (udp_tunnel->prot_type) {
6579         case RTE_TUNNEL_TYPE_VXLAN:
6580                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6581                 break;
6582
6583         case RTE_TUNNEL_TYPE_GENEVE:
6584         case RTE_TUNNEL_TYPE_TEREDO:
6585                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6586                 ret = -1;
6587                 break;
6588
6589         default:
6590                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6591                 ret = -1;
6592                 break;
6593         }
6594
6595         return ret;
6596 }
6597
6598 /* Remove UDP tunneling port */
6599 static int
6600 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6601                              struct rte_eth_udp_tunnel *udp_tunnel)
6602 {
6603         int ret = 0;
6604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6605
6606         if (udp_tunnel == NULL)
6607                 return -EINVAL;
6608
6609         switch (udp_tunnel->prot_type) {
6610         case RTE_TUNNEL_TYPE_VXLAN:
6611                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6612                 break;
6613         case RTE_TUNNEL_TYPE_GENEVE:
6614         case RTE_TUNNEL_TYPE_TEREDO:
6615                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6616                 ret = -1;
6617                 break;
6618         default:
6619                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6620                 ret = -1;
6621                 break;
6622         }
6623
6624         return ret;
6625 }
6626
6627 /* Calculate the maximum number of contiguous PF queues that are configured */
6628 static int
6629 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6630 {
6631         struct rte_eth_dev_data *data = pf->dev_data;
6632         int i, num;
6633         struct i40e_rx_queue *rxq;
6634
6635         num = 0;
6636         for (i = 0; i < pf->lan_nb_qps; i++) {
6637                 rxq = data->rx_queues[i];
6638                 if (rxq && rxq->q_set)
6639                         num++;
6640                 else
6641                         break;
6642         }
6643
6644         return num;
6645 }
6646
6647 /* Configure RSS */
6648 static int
6649 i40e_pf_config_rss(struct i40e_pf *pf)
6650 {
6651         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6652         struct rte_eth_rss_conf rss_conf;
6653         uint32_t i, lut = 0;
6654         uint16_t j, num;
6655
6656         /*
6657          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6658          * It's necessary to calulate the actual PF queues that are configured.
6659          */
6660         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6661                 num = i40e_pf_calc_configured_queues_num(pf);
6662         else
6663                 num = pf->dev_data->nb_rx_queues;
6664
6665         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6666         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6667                         num);
6668
6669         if (num == 0) {
6670                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6671                 return -ENOTSUP;
6672         }
6673
6674         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6675                 if (j == num)
6676                         j = 0;
6677                 lut = (lut << 8) | (j & ((0x1 <<
6678                         hw->func_caps.rss_table_entry_width) - 1));
6679                 if ((i & 3) == 3)
6680                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6681         }
6682
6683         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6684         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6685                 i40e_pf_disable_rss(pf);
6686                 return 0;
6687         }
6688         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6689                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6690                 /* Random default keys */
6691                 static uint32_t rss_key_default[] = {0x6b793944,
6692                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6693                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6694                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6695
6696                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6697                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6698                                                         sizeof(uint32_t);
6699         }
6700
6701         return i40e_hw_rss_hash_set(pf, &rss_conf);
6702 }
6703
6704 static int
6705 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6706                                struct rte_eth_tunnel_filter_conf *filter)
6707 {
6708         if (pf == NULL || filter == NULL) {
6709                 PMD_DRV_LOG(ERR, "Invalid parameter");
6710                 return -EINVAL;
6711         }
6712
6713         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6714                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6715                 return -EINVAL;
6716         }
6717
6718         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6719                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6720                 return -EINVAL;
6721         }
6722
6723         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6724                 (is_zero_ether_addr(&filter->outer_mac))) {
6725                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6726                 return -EINVAL;
6727         }
6728
6729         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6730                 (is_zero_ether_addr(&filter->inner_mac))) {
6731                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6732                 return -EINVAL;
6733         }
6734
6735         return 0;
6736 }
6737
6738 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6739 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6740 static int
6741 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6742 {
6743         uint32_t val, reg;
6744         int ret = -EINVAL;
6745
6746         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6747         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6748
6749         if (len == 3) {
6750                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6751         } else if (len == 4) {
6752                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6753         } else {
6754                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6755                 return ret;
6756         }
6757
6758         if (reg != val) {
6759                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6760                                                    reg, NULL);
6761                 if (ret != 0)
6762                         return ret;
6763         } else {
6764                 ret = 0;
6765         }
6766         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6767                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6768
6769         return ret;
6770 }
6771
6772 static int
6773 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6774 {
6775         int ret = -EINVAL;
6776
6777         if (!hw || !cfg)
6778                 return -EINVAL;
6779
6780         switch (cfg->cfg_type) {
6781         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6782                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6783                 break;
6784         default:
6785                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6786                 break;
6787         }
6788
6789         return ret;
6790 }
6791
6792 static int
6793 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6794                                enum rte_filter_op filter_op,
6795                                void *arg)
6796 {
6797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6798         int ret = I40E_ERR_PARAM;
6799
6800         switch (filter_op) {
6801         case RTE_ETH_FILTER_SET:
6802                 ret = i40e_dev_global_config_set(hw,
6803                         (struct rte_eth_global_cfg *)arg);
6804                 break;
6805         default:
6806                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6807                 break;
6808         }
6809
6810         return ret;
6811 }
6812
6813 static int
6814 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6815                           enum rte_filter_op filter_op,
6816                           void *arg)
6817 {
6818         struct rte_eth_tunnel_filter_conf *filter;
6819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6820         int ret = I40E_SUCCESS;
6821
6822         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6823
6824         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6825                 return I40E_ERR_PARAM;
6826
6827         switch (filter_op) {
6828         case RTE_ETH_FILTER_NOP:
6829                 if (!(pf->flags & I40E_FLAG_VXLAN))
6830                         ret = I40E_NOT_SUPPORTED;
6831                 break;
6832         case RTE_ETH_FILTER_ADD:
6833                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6834                 break;
6835         case RTE_ETH_FILTER_DELETE:
6836                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6837                 break;
6838         default:
6839                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6840                 ret = I40E_ERR_PARAM;
6841                 break;
6842         }
6843
6844         return ret;
6845 }
6846
6847 static int
6848 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6849 {
6850         int ret = 0;
6851         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6852
6853         /* RSS setup */
6854         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6855                 ret = i40e_pf_config_rss(pf);
6856         else
6857                 i40e_pf_disable_rss(pf);
6858
6859         return ret;
6860 }
6861
6862 /* Get the symmetric hash enable configurations per port */
6863 static void
6864 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6865 {
6866         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6867
6868         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6869 }
6870
6871 /* Set the symmetric hash enable configurations per port */
6872 static void
6873 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6874 {
6875         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6876
6877         if (enable > 0) {
6878                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6879                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6880                                                         "been enabled");
6881                         return;
6882                 }
6883                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6884         } else {
6885                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6886                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6887                                                         "been disabled");
6888                         return;
6889                 }
6890                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6891         }
6892         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6893         I40E_WRITE_FLUSH(hw);
6894 }
6895
6896 /*
6897  * Get global configurations of hash function type and symmetric hash enable
6898  * per flow type (pctype). Note that global configuration means it affects all
6899  * the ports on the same NIC.
6900  */
6901 static int
6902 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6903                                    struct rte_eth_hash_global_conf *g_cfg)
6904 {
6905         uint32_t reg, mask = I40E_FLOW_TYPES;
6906         uint16_t i;
6907         enum i40e_filter_pctype pctype;
6908
6909         memset(g_cfg, 0, sizeof(*g_cfg));
6910         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6911         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6912                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6913         else
6914                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6915         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6916                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6917
6918         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6919                 if (!(mask & (1UL << i)))
6920                         continue;
6921                 mask &= ~(1UL << i);
6922                 /* Bit set indicats the coresponding flow type is supported */
6923                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6924                 /* if flowtype is invalid, continue */
6925                 if (!I40E_VALID_FLOW(i))
6926                         continue;
6927                 pctype = i40e_flowtype_to_pctype(i);
6928                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6929                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6930                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6931         }
6932
6933         return 0;
6934 }
6935
6936 static int
6937 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6938 {
6939         uint32_t i;
6940         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6941
6942         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6943                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6944                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6945                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6946                                                 g_cfg->hash_func);
6947                 return -EINVAL;
6948         }
6949
6950         /*
6951          * As i40e supports less than 32 flow types, only first 32 bits need to
6952          * be checked.
6953          */
6954         mask0 = g_cfg->valid_bit_mask[0];
6955         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6956                 if (i == 0) {
6957                         /* Check if any unsupported flow type configured */
6958                         if ((mask0 | i40e_mask) ^ i40e_mask)
6959                                 goto mask_err;
6960                 } else {
6961                         if (g_cfg->valid_bit_mask[i])
6962                                 goto mask_err;
6963                 }
6964         }
6965
6966         return 0;
6967
6968 mask_err:
6969         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6970
6971         return -EINVAL;
6972 }
6973
6974 /*
6975  * Set global configurations of hash function type and symmetric hash enable
6976  * per flow type (pctype). Note any modifying global configuration will affect
6977  * all the ports on the same NIC.
6978  */
6979 static int
6980 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6981                                    struct rte_eth_hash_global_conf *g_cfg)
6982 {
6983         int ret;
6984         uint16_t i;
6985         uint32_t reg;
6986         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6987         enum i40e_filter_pctype pctype;
6988
6989         /* Check the input parameters */
6990         ret = i40e_hash_global_config_check(g_cfg);
6991         if (ret < 0)
6992                 return ret;
6993
6994         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6995                 if (!(mask0 & (1UL << i)))
6996                         continue;
6997                 mask0 &= ~(1UL << i);
6998                 /* if flowtype is invalid, continue */
6999                 if (!I40E_VALID_FLOW(i))
7000                         continue;
7001                 pctype = i40e_flowtype_to_pctype(i);
7002                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7003                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7004                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7005         }
7006
7007         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7008         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7009                 /* Toeplitz */
7010                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7011                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7012                                                                 "Toeplitz");
7013                         goto out;
7014                 }
7015                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7016         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7017                 /* Simple XOR */
7018                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7019                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7020                                                         "Simple XOR");
7021                         goto out;
7022                 }
7023                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7024         } else
7025                 /* Use the default, and keep it as it is */
7026                 goto out;
7027
7028         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7029
7030 out:
7031         I40E_WRITE_FLUSH(hw);
7032
7033         return 0;
7034 }
7035
7036 /**
7037  * Valid input sets for hash and flow director filters per PCTYPE
7038  */
7039 static uint64_t
7040 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7041                 enum rte_filter_type filter)
7042 {
7043         uint64_t valid;
7044
7045         static const uint64_t valid_hash_inset_table[] = {
7046                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7047                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7048                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7049                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7050                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7051                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7052                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7053                         I40E_INSET_FLEX_PAYLOAD,
7054                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7055                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7056                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7057                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7058                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7059                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7060                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7061                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7062                         I40E_INSET_FLEX_PAYLOAD,
7063                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7064                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7065                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7066                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7067                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7068                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7069                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7070                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7071                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7072                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7076                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7077                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7078                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7079                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7080                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7081                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7082                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7083                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7084                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7085                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7086                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7087                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7088                         I40E_INSET_FLEX_PAYLOAD,
7089                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7090                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7091                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7092                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7093                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7094                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7095                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7096                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7097                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7098                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7099                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7100                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7101                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7102                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7103                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7104                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7105                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7109                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7110                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7111                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7112                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7113                         I40E_INSET_FLEX_PAYLOAD,
7114                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7118                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7119                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7120                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7121                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7122                         I40E_INSET_FLEX_PAYLOAD,
7123                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7127                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7128                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7129                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7130                         I40E_INSET_FLEX_PAYLOAD,
7131                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7132                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7133                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7134                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7135                         I40E_INSET_FLEX_PAYLOAD,
7136         };
7137
7138         /**
7139          * Flow director supports only fields defined in
7140          * union rte_eth_fdir_flow.
7141          */
7142         static const uint64_t valid_fdir_inset_table[] = {
7143                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7145                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7146                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7147                 I40E_INSET_IPV4_TTL,
7148                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7149                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7150                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7151                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7152                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7153                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7154                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7155                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7156                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7157                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7158                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7159                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7160                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7161                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7162                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7163                 I40E_INSET_SCTP_VT,
7164                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7165                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7166                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7167                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7168                 I40E_INSET_IPV4_TTL,
7169                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7170                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7171                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7172                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7173                 I40E_INSET_IPV6_HOP_LIMIT,
7174                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7175                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7176                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7177                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7178                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7179                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7180                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7181                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7182                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7183                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7184                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7185                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7186                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7187                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7188                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7189                 I40E_INSET_SCTP_VT,
7190                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7191                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7192                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7193                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7194                 I40E_INSET_IPV6_HOP_LIMIT,
7195                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7196                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7197                 I40E_INSET_LAST_ETHER_TYPE,
7198         };
7199
7200         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7201                 return 0;
7202         if (filter == RTE_ETH_FILTER_HASH)
7203                 valid = valid_hash_inset_table[pctype];
7204         else
7205                 valid = valid_fdir_inset_table[pctype];
7206
7207         return valid;
7208 }
7209
7210 /**
7211  * Validate if the input set is allowed for a specific PCTYPE
7212  */
7213 static int
7214 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7215                 enum rte_filter_type filter, uint64_t inset)
7216 {
7217         uint64_t valid;
7218
7219         valid = i40e_get_valid_input_set(pctype, filter);
7220         if (inset & (~valid))
7221                 return -EINVAL;
7222
7223         return 0;
7224 }
7225
7226 /* default input set fields combination per pctype */
7227 static uint64_t
7228 i40e_get_default_input_set(uint16_t pctype)
7229 {
7230         static const uint64_t default_inset_table[] = {
7231                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7232                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7233                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7234                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7235                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7236                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7237                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7238                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7239                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7240                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7241                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7242                         I40E_INSET_SCTP_VT,
7243                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7244                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7245                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7246                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7247                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7248                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7249                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7250                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7251                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7252                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7253                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7254                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7255                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7256                         I40E_INSET_SCTP_VT,
7257                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7258                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7259                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7260                         I40E_INSET_LAST_ETHER_TYPE,
7261         };
7262
7263         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7264                 return 0;
7265
7266         return default_inset_table[pctype];
7267 }
7268
7269 /**
7270  * Parse the input set from index to logical bit masks
7271  */
7272 static int
7273 i40e_parse_input_set(uint64_t *inset,
7274                      enum i40e_filter_pctype pctype,
7275                      enum rte_eth_input_set_field *field,
7276                      uint16_t size)
7277 {
7278         uint16_t i, j;
7279         int ret = -EINVAL;
7280
7281         static const struct {
7282                 enum rte_eth_input_set_field field;
7283                 uint64_t inset;
7284         } inset_convert_table[] = {
7285                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7286                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7287                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7288                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7289                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7290                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7291                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7292                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7293                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7294                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7295                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7296                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7297                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7298                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7299                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7300                         I40E_INSET_IPV6_NEXT_HDR},
7301                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7302                         I40E_INSET_IPV6_HOP_LIMIT},
7303                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7304                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7305                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7306                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7307                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7308                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7309                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7310                         I40E_INSET_SCTP_VT},
7311                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7312                         I40E_INSET_TUNNEL_DMAC},
7313                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7314                         I40E_INSET_VLAN_TUNNEL},
7315                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7316                         I40E_INSET_TUNNEL_ID},
7317                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7318                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7319                         I40E_INSET_FLEX_PAYLOAD_W1},
7320                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7321                         I40E_INSET_FLEX_PAYLOAD_W2},
7322                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7323                         I40E_INSET_FLEX_PAYLOAD_W3},
7324                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7325                         I40E_INSET_FLEX_PAYLOAD_W4},
7326                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7327                         I40E_INSET_FLEX_PAYLOAD_W5},
7328                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7329                         I40E_INSET_FLEX_PAYLOAD_W6},
7330                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7331                         I40E_INSET_FLEX_PAYLOAD_W7},
7332                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7333                         I40E_INSET_FLEX_PAYLOAD_W8},
7334         };
7335
7336         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7337                 return ret;
7338
7339         /* Only one item allowed for default or all */
7340         if (size == 1) {
7341                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7342                         *inset = i40e_get_default_input_set(pctype);
7343                         return 0;
7344                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7345                         *inset = I40E_INSET_NONE;
7346                         return 0;
7347                 }
7348         }
7349
7350         for (i = 0, *inset = 0; i < size; i++) {
7351                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7352                         if (field[i] == inset_convert_table[j].field) {
7353                                 *inset |= inset_convert_table[j].inset;
7354                                 break;
7355                         }
7356                 }
7357
7358                 /* It contains unsupported input set, return immediately */
7359                 if (j == RTE_DIM(inset_convert_table))
7360                         return ret;
7361         }
7362
7363         return 0;
7364 }
7365
7366 /**
7367  * Translate the input set from bit masks to register aware bit masks
7368  * and vice versa
7369  */
7370 static uint64_t
7371 i40e_translate_input_set_reg(uint64_t input)
7372 {
7373         uint64_t val = 0;
7374         uint16_t i;
7375
7376         static const struct {
7377                 uint64_t inset;
7378                 uint64_t inset_reg;
7379         } inset_map[] = {
7380                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7381                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7382                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7383                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7384                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7385                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7386                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7387                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7388                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7389                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7390                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7391                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7392                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7393                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7394                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7395                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7396                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7397                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7398                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7399                 {I40E_INSET_TUNNEL_DMAC,
7400                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7401                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7402                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7403                 {I40E_INSET_TUNNEL_SRC_PORT,
7404                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7405                 {I40E_INSET_TUNNEL_DST_PORT,
7406                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7407                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7408                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7409                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7410                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7411                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7412                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7413                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7414                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7415                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7416         };
7417
7418         if (input == 0)
7419                 return val;
7420
7421         /* Translate input set to register aware inset */
7422         for (i = 0; i < RTE_DIM(inset_map); i++) {
7423                 if (input & inset_map[i].inset)
7424                         val |= inset_map[i].inset_reg;
7425         }
7426
7427         return val;
7428 }
7429
7430 static int
7431 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7432 {
7433         uint8_t i, idx = 0;
7434         uint64_t inset_need_mask = inset;
7435
7436         static const struct {
7437                 uint64_t inset;
7438                 uint32_t mask;
7439         } inset_mask_map[] = {
7440                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7441                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7442                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7443                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7444                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7445                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7446                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7447                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7448         };
7449
7450         if (!inset || !mask || !nb_elem)
7451                 return 0;
7452
7453         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7454                 /* Clear the inset bit, if no MASK is required,
7455                  * for example proto + ttl
7456                  */
7457                 if ((inset & inset_mask_map[i].inset) ==
7458                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7459                         inset_need_mask &= ~inset_mask_map[i].inset;
7460                 if (!inset_need_mask)
7461                         return 0;
7462         }
7463         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7464                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7465                     inset_mask_map[i].inset) {
7466                         if (idx >= nb_elem) {
7467                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7468                                 return -EINVAL;
7469                         }
7470                         mask[idx] = inset_mask_map[i].mask;
7471                         idx++;
7472                 }
7473         }
7474
7475         return idx;
7476 }
7477
7478 static void
7479 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7480 {
7481         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7482
7483         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7484         if (reg != val)
7485                 i40e_write_rx_ctl(hw, addr, val);
7486         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7487                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7488 }
7489
7490 static void
7491 i40e_filter_input_set_init(struct i40e_pf *pf)
7492 {
7493         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7494         enum i40e_filter_pctype pctype;
7495         uint64_t input_set, inset_reg;
7496         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7497         int num, i;
7498
7499         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7500              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7501                 if (!I40E_VALID_PCTYPE(pctype))
7502                         continue;
7503                 input_set = i40e_get_default_input_set(pctype);
7504
7505                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7506                                                    I40E_INSET_MASK_NUM_REG);
7507                 if (num < 0)
7508                         return;
7509                 inset_reg = i40e_translate_input_set_reg(input_set);
7510
7511                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7512                                       (uint32_t)(inset_reg & UINT32_MAX));
7513                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7514                                      (uint32_t)((inset_reg >>
7515                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7516                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7517                                       (uint32_t)(inset_reg & UINT32_MAX));
7518                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7519                                      (uint32_t)((inset_reg >>
7520                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7521
7522                 for (i = 0; i < num; i++) {
7523                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7524                                              mask_reg[i]);
7525                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7526                                              mask_reg[i]);
7527                 }
7528                 /*clear unused mask registers of the pctype */
7529                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7530                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7531                                              0);
7532                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7533                                              0);
7534                 }
7535                 I40E_WRITE_FLUSH(hw);
7536
7537                 /* store the default input set */
7538                 pf->hash_input_set[pctype] = input_set;
7539                 pf->fdir.input_set[pctype] = input_set;
7540         }
7541 }
7542
7543 int
7544 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7545                          struct rte_eth_input_set_conf *conf)
7546 {
7547         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7548         enum i40e_filter_pctype pctype;
7549         uint64_t input_set, inset_reg = 0;
7550         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7551         int ret, i, num;
7552
7553         if (!conf) {
7554                 PMD_DRV_LOG(ERR, "Invalid pointer");
7555                 return -EFAULT;
7556         }
7557         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7558             conf->op != RTE_ETH_INPUT_SET_ADD) {
7559                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7560                 return -EINVAL;
7561         }
7562
7563         if (!I40E_VALID_FLOW(conf->flow_type)) {
7564                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7565                 return -EINVAL;
7566         }
7567         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7568         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7569                                    conf->inset_size);
7570         if (ret) {
7571                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7572                 return -EINVAL;
7573         }
7574         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7575                                     input_set) != 0) {
7576                 PMD_DRV_LOG(ERR, "Invalid input set");
7577                 return -EINVAL;
7578         }
7579         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7580                 /* get inset value in register */
7581                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7582                 inset_reg <<= I40E_32_BIT_WIDTH;
7583                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7584                 input_set |= pf->hash_input_set[pctype];
7585         }
7586         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7587                                            I40E_INSET_MASK_NUM_REG);
7588         if (num < 0)
7589                 return -EINVAL;
7590
7591         inset_reg |= i40e_translate_input_set_reg(input_set);
7592
7593         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7594                               (uint32_t)(inset_reg & UINT32_MAX));
7595         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7596                              (uint32_t)((inset_reg >>
7597                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7598
7599         for (i = 0; i < num; i++)
7600                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7601                                      mask_reg[i]);
7602         /*clear unused mask registers of the pctype */
7603         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7604                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7605                                      0);
7606         I40E_WRITE_FLUSH(hw);
7607
7608         pf->hash_input_set[pctype] = input_set;
7609         return 0;
7610 }
7611
7612 int
7613 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7614                          struct rte_eth_input_set_conf *conf)
7615 {
7616         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7617         enum i40e_filter_pctype pctype;
7618         uint64_t input_set, inset_reg = 0;
7619         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7620         int ret, i, num;
7621
7622         if (!hw || !conf) {
7623                 PMD_DRV_LOG(ERR, "Invalid pointer");
7624                 return -EFAULT;
7625         }
7626         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7627             conf->op != RTE_ETH_INPUT_SET_ADD) {
7628                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7629                 return -EINVAL;
7630         }
7631
7632         if (!I40E_VALID_FLOW(conf->flow_type)) {
7633                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7634                 return -EINVAL;
7635         }
7636         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7637         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7638                                    conf->inset_size);
7639         if (ret) {
7640                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7641                 return -EINVAL;
7642         }
7643         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7644                                     input_set) != 0) {
7645                 PMD_DRV_LOG(ERR, "Invalid input set");
7646                 return -EINVAL;
7647         }
7648
7649         /* get inset value in register */
7650         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7651         inset_reg <<= I40E_32_BIT_WIDTH;
7652         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7653
7654         /* Can not change the inset reg for flex payload for fdir,
7655          * it is done by writing I40E_PRTQF_FD_FLXINSET
7656          * in i40e_set_flex_mask_on_pctype.
7657          */
7658         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7659                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7660         else
7661                 input_set |= pf->fdir.input_set[pctype];
7662         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7663                                            I40E_INSET_MASK_NUM_REG);
7664         if (num < 0)
7665                 return -EINVAL;
7666
7667         inset_reg |= i40e_translate_input_set_reg(input_set);
7668
7669         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7670                               (uint32_t)(inset_reg & UINT32_MAX));
7671         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7672                              (uint32_t)((inset_reg >>
7673                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7674
7675         for (i = 0; i < num; i++)
7676                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7677                                      mask_reg[i]);
7678         /*clear unused mask registers of the pctype */
7679         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7680                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7681                                      0);
7682         I40E_WRITE_FLUSH(hw);
7683
7684         pf->fdir.input_set[pctype] = input_set;
7685         return 0;
7686 }
7687
7688 static int
7689 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7690 {
7691         int ret = 0;
7692
7693         if (!hw || !info) {
7694                 PMD_DRV_LOG(ERR, "Invalid pointer");
7695                 return -EFAULT;
7696         }
7697
7698         switch (info->info_type) {
7699         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7700                 i40e_get_symmetric_hash_enable_per_port(hw,
7701                                         &(info->info.enable));
7702                 break;
7703         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7704                 ret = i40e_get_hash_filter_global_config(hw,
7705                                 &(info->info.global_conf));
7706                 break;
7707         default:
7708                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7709                                                         info->info_type);
7710                 ret = -EINVAL;
7711                 break;
7712         }
7713
7714         return ret;
7715 }
7716
7717 static int
7718 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7719 {
7720         int ret = 0;
7721
7722         if (!hw || !info) {
7723                 PMD_DRV_LOG(ERR, "Invalid pointer");
7724                 return -EFAULT;
7725         }
7726
7727         switch (info->info_type) {
7728         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7729                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7730                 break;
7731         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7732                 ret = i40e_set_hash_filter_global_config(hw,
7733                                 &(info->info.global_conf));
7734                 break;
7735         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7736                 ret = i40e_hash_filter_inset_select(hw,
7737                                                &(info->info.input_set_conf));
7738                 break;
7739
7740         default:
7741                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7742                                                         info->info_type);
7743                 ret = -EINVAL;
7744                 break;
7745         }
7746
7747         return ret;
7748 }
7749
7750 /* Operations for hash function */
7751 static int
7752 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7753                       enum rte_filter_op filter_op,
7754                       void *arg)
7755 {
7756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7757         int ret = 0;
7758
7759         switch (filter_op) {
7760         case RTE_ETH_FILTER_NOP:
7761                 break;
7762         case RTE_ETH_FILTER_GET:
7763                 ret = i40e_hash_filter_get(hw,
7764                         (struct rte_eth_hash_filter_info *)arg);
7765                 break;
7766         case RTE_ETH_FILTER_SET:
7767                 ret = i40e_hash_filter_set(hw,
7768                         (struct rte_eth_hash_filter_info *)arg);
7769                 break;
7770         default:
7771                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7772                                                                 filter_op);
7773                 ret = -ENOTSUP;
7774                 break;
7775         }
7776
7777         return ret;
7778 }
7779
7780 /*
7781  * Configure ethertype filter, which can director packet by filtering
7782  * with mac address and ether_type or only ether_type
7783  */
7784 static int
7785 i40e_ethertype_filter_set(struct i40e_pf *pf,
7786                         struct rte_eth_ethertype_filter *filter,
7787                         bool add)
7788 {
7789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7790         struct i40e_control_filter_stats stats;
7791         uint16_t flags = 0;
7792         int ret;
7793
7794         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7795                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7796                 return -EINVAL;
7797         }
7798         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7799                 filter->ether_type == ETHER_TYPE_IPv6) {
7800                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7801                         " control packet filter.", filter->ether_type);
7802                 return -EINVAL;
7803         }
7804         if (filter->ether_type == ETHER_TYPE_VLAN)
7805                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7806                         " not supported.");
7807
7808         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7809                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7810         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7811                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7812         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7813
7814         memset(&stats, 0, sizeof(stats));
7815         ret = i40e_aq_add_rem_control_packet_filter(hw,
7816                         filter->mac_addr.addr_bytes,
7817                         filter->ether_type, flags,
7818                         pf->main_vsi->seid,
7819                         filter->queue, add, &stats, NULL);
7820
7821         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7822                          " mac_etype_used = %u, etype_used = %u,"
7823                          " mac_etype_free = %u, etype_free = %u\n",
7824                          ret, stats.mac_etype_used, stats.etype_used,
7825                          stats.mac_etype_free, stats.etype_free);
7826         if (ret < 0)
7827                 return -ENOSYS;
7828         return 0;
7829 }
7830
7831 /*
7832  * Handle operations for ethertype filter.
7833  */
7834 static int
7835 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7836                                 enum rte_filter_op filter_op,
7837                                 void *arg)
7838 {
7839         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7840         int ret = 0;
7841
7842         if (filter_op == RTE_ETH_FILTER_NOP)
7843                 return ret;
7844
7845         if (arg == NULL) {
7846                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7847                             filter_op);
7848                 return -EINVAL;
7849         }
7850
7851         switch (filter_op) {
7852         case RTE_ETH_FILTER_ADD:
7853                 ret = i40e_ethertype_filter_set(pf,
7854                         (struct rte_eth_ethertype_filter *)arg,
7855                         TRUE);
7856                 break;
7857         case RTE_ETH_FILTER_DELETE:
7858                 ret = i40e_ethertype_filter_set(pf,
7859                         (struct rte_eth_ethertype_filter *)arg,
7860                         FALSE);
7861                 break;
7862         default:
7863                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7864                 ret = -ENOSYS;
7865                 break;
7866         }
7867         return ret;
7868 }
7869
7870 static int
7871 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7872                      enum rte_filter_type filter_type,
7873                      enum rte_filter_op filter_op,
7874                      void *arg)
7875 {
7876         int ret = 0;
7877
7878         if (dev == NULL)
7879                 return -EINVAL;
7880
7881         switch (filter_type) {
7882         case RTE_ETH_FILTER_NONE:
7883                 /* For global configuration */
7884                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7885                 break;
7886         case RTE_ETH_FILTER_HASH:
7887                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7888                 break;
7889         case RTE_ETH_FILTER_MACVLAN:
7890                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7891                 break;
7892         case RTE_ETH_FILTER_ETHERTYPE:
7893                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7894                 break;
7895         case RTE_ETH_FILTER_TUNNEL:
7896                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7897                 break;
7898         case RTE_ETH_FILTER_FDIR:
7899                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7900                 break;
7901         default:
7902                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7903                                                         filter_type);
7904                 ret = -EINVAL;
7905                 break;
7906         }
7907
7908         return ret;
7909 }
7910
7911 /*
7912  * Check and enable Extended Tag.
7913  * Enabling Extended Tag is important for 40G performance.
7914  */
7915 static void
7916 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7917 {
7918         uint32_t buf = 0;
7919         int ret;
7920
7921         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7922                                       PCI_DEV_CAP_REG);
7923         if (ret < 0) {
7924                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7925                             PCI_DEV_CAP_REG);
7926                 return;
7927         }
7928         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7929                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7930                 return;
7931         }
7932
7933         buf = 0;
7934         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7935                                       PCI_DEV_CTRL_REG);
7936         if (ret < 0) {
7937                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7938                             PCI_DEV_CTRL_REG);
7939                 return;
7940         }
7941         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7942                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7943                 return;
7944         }
7945         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7946         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7947                                        PCI_DEV_CTRL_REG);
7948         if (ret < 0) {
7949                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7950                             PCI_DEV_CTRL_REG);
7951                 return;
7952         }
7953 }
7954
7955 /*
7956  * As some registers wouldn't be reset unless a global hardware reset,
7957  * hardware initialization is needed to put those registers into an
7958  * expected initial state.
7959  */
7960 static void
7961 i40e_hw_init(struct rte_eth_dev *dev)
7962 {
7963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7964
7965         i40e_enable_extended_tag(dev);
7966
7967         /* clear the PF Queue Filter control register */
7968         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7969
7970         /* Disable symmetric hash per port */
7971         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7972 }
7973
7974 enum i40e_filter_pctype
7975 i40e_flowtype_to_pctype(uint16_t flow_type)
7976 {
7977         static const enum i40e_filter_pctype pctype_table[] = {
7978                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7979                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7980                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7981                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7982                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7983                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7984                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7985                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7986                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7987                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7988                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7989                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7990                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7991                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7992                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7993                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7994                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7995                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7996                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7997         };
7998
7999         return pctype_table[flow_type];
8000 }
8001
8002 uint16_t
8003 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8004 {
8005         static const uint16_t flowtype_table[] = {
8006                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8007                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8008                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8009                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8010                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8011                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8012                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8013                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8014                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8015                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8016                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8017                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8018                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8019                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8020                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8021                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8022                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8023                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8024                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8025         };
8026
8027         return flowtype_table[pctype];
8028 }
8029
8030 /*
8031  * On X710, performance number is far from the expectation on recent firmware
8032  * versions; on XL710, performance number is also far from the expectation on
8033  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8034  * mode is enabled and port MAC address is equal to the packet destination MAC
8035  * address. The fix for this issue may not be integrated in the following
8036  * firmware version. So the workaround in software driver is needed. It needs
8037  * to modify the initial values of 3 internal only registers for both X710 and
8038  * XL710. Note that the values for X710 or XL710 could be different, and the
8039  * workaround can be removed when it is fixed in firmware in the future.
8040  */
8041
8042 /* For both X710 and XL710 */
8043 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8044 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8045
8046 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8047 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8048
8049 /* For X710 */
8050 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8051 /* For XL710 */
8052 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8053 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8054
8055 static void
8056 i40e_configure_registers(struct i40e_hw *hw)
8057 {
8058         static struct {
8059                 uint32_t addr;
8060                 uint64_t val;
8061         } reg_table[] = {
8062                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8063                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8064                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8065         };
8066         uint64_t reg;
8067         uint32_t i;
8068         int ret;
8069
8070         for (i = 0; i < RTE_DIM(reg_table); i++) {
8071                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8072                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8073                                 reg_table[i].val =
8074                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8075                         else /* For X710 */
8076                                 reg_table[i].val =
8077                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8078                 }
8079
8080                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8081                                                         &reg, NULL);
8082                 if (ret < 0) {
8083                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8084                                                         reg_table[i].addr);
8085                         break;
8086                 }
8087                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8088                                                 reg_table[i].addr, reg);
8089                 if (reg == reg_table[i].val)
8090                         continue;
8091
8092                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8093                                                 reg_table[i].val, NULL);
8094                 if (ret < 0) {
8095                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8096                                 "address of 0x%"PRIx32, reg_table[i].val,
8097                                                         reg_table[i].addr);
8098                         break;
8099                 }
8100                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8101                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8102         }
8103 }
8104
8105 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8106 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8107 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8108 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8109 static int
8110 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8111 {
8112         uint32_t reg;
8113         int ret;
8114
8115         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8116                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8117                 return -EINVAL;
8118         }
8119
8120         /* Configure for double VLAN RX stripping */
8121         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8122         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8123                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8124                 ret = i40e_aq_debug_write_register(hw,
8125                                                    I40E_VSI_TSR(vsi->vsi_id),
8126                                                    reg, NULL);
8127                 if (ret < 0) {
8128                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8129                                     vsi->vsi_id);
8130                         return I40E_ERR_CONFIG;
8131                 }
8132         }
8133
8134         /* Configure for double VLAN TX insertion */
8135         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8136         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8137                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8138                 ret = i40e_aq_debug_write_register(hw,
8139                                                    I40E_VSI_L2TAGSTXVALID(
8140                                                    vsi->vsi_id), reg, NULL);
8141                 if (ret < 0) {
8142                         PMD_DRV_LOG(ERR, "Failed to update "
8143                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8144                         return I40E_ERR_CONFIG;
8145                 }
8146         }
8147
8148         return 0;
8149 }
8150
8151 /**
8152  * i40e_aq_add_mirror_rule
8153  * @hw: pointer to the hardware structure
8154  * @seid: VEB seid to add mirror rule to
8155  * @dst_id: destination vsi seid
8156  * @entries: Buffer which contains the entities to be mirrored
8157  * @count: number of entities contained in the buffer
8158  * @rule_id:the rule_id of the rule to be added
8159  *
8160  * Add a mirror rule for a given veb.
8161  *
8162  **/
8163 static enum i40e_status_code
8164 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8165                         uint16_t seid, uint16_t dst_id,
8166                         uint16_t rule_type, uint16_t *entries,
8167                         uint16_t count, uint16_t *rule_id)
8168 {
8169         struct i40e_aq_desc desc;
8170         struct i40e_aqc_add_delete_mirror_rule cmd;
8171         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8172                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8173                 &desc.params.raw;
8174         uint16_t buff_len;
8175         enum i40e_status_code status;
8176
8177         i40e_fill_default_direct_cmd_desc(&desc,
8178                                           i40e_aqc_opc_add_mirror_rule);
8179         memset(&cmd, 0, sizeof(cmd));
8180
8181         buff_len = sizeof(uint16_t) * count;
8182         desc.datalen = rte_cpu_to_le_16(buff_len);
8183         if (buff_len > 0)
8184                 desc.flags |= rte_cpu_to_le_16(
8185                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8186         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8187                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8188         cmd.num_entries = rte_cpu_to_le_16(count);
8189         cmd.seid = rte_cpu_to_le_16(seid);
8190         cmd.destination = rte_cpu_to_le_16(dst_id);
8191
8192         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8193         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8194         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8195                          "rule_id = %u"
8196                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8197                          hw->aq.asq_last_status, resp->rule_id,
8198                          resp->mirror_rules_used, resp->mirror_rules_free);
8199         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8200
8201         return status;
8202 }
8203
8204 /**
8205  * i40e_aq_del_mirror_rule
8206  * @hw: pointer to the hardware structure
8207  * @seid: VEB seid to add mirror rule to
8208  * @entries: Buffer which contains the entities to be mirrored
8209  * @count: number of entities contained in the buffer
8210  * @rule_id:the rule_id of the rule to be delete
8211  *
8212  * Delete a mirror rule for a given veb.
8213  *
8214  **/
8215 static enum i40e_status_code
8216 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8217                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8218                 uint16_t count, uint16_t rule_id)
8219 {
8220         struct i40e_aq_desc desc;
8221         struct i40e_aqc_add_delete_mirror_rule cmd;
8222         uint16_t buff_len = 0;
8223         enum i40e_status_code status;
8224         void *buff = NULL;
8225
8226         i40e_fill_default_direct_cmd_desc(&desc,
8227                                           i40e_aqc_opc_delete_mirror_rule);
8228         memset(&cmd, 0, sizeof(cmd));
8229         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8230                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8231                                                           I40E_AQ_FLAG_RD));
8232                 cmd.num_entries = count;
8233                 buff_len = sizeof(uint16_t) * count;
8234                 desc.datalen = rte_cpu_to_le_16(buff_len);
8235                 buff = (void *)entries;
8236         } else
8237                 /* rule id is filled in destination field for deleting mirror rule */
8238                 cmd.destination = rte_cpu_to_le_16(rule_id);
8239
8240         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8241                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8242         cmd.seid = rte_cpu_to_le_16(seid);
8243
8244         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8245         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8246
8247         return status;
8248 }
8249
8250 /**
8251  * i40e_mirror_rule_set
8252  * @dev: pointer to the hardware structure
8253  * @mirror_conf: mirror rule info
8254  * @sw_id: mirror rule's sw_id
8255  * @on: enable/disable
8256  *
8257  * set a mirror rule.
8258  *
8259  **/
8260 static int
8261 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8262                         struct rte_eth_mirror_conf *mirror_conf,
8263                         uint8_t sw_id, uint8_t on)
8264 {
8265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8266         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8267         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8268         struct i40e_mirror_rule *parent = NULL;
8269         uint16_t seid, dst_seid, rule_id;
8270         uint16_t i, j = 0;
8271         int ret;
8272
8273         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8274
8275         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8276                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8277                         " without veb or vfs.");
8278                 return -ENOSYS;
8279         }
8280         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8281                 PMD_DRV_LOG(ERR, "mirror table is full.");
8282                 return -ENOSPC;
8283         }
8284         if (mirror_conf->dst_pool > pf->vf_num) {
8285                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8286                                  mirror_conf->dst_pool);
8287                 return -EINVAL;
8288         }
8289
8290         seid = pf->main_vsi->veb->seid;
8291
8292         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8293                 if (sw_id <= it->index) {
8294                         mirr_rule = it;
8295                         break;
8296                 }
8297                 parent = it;
8298         }
8299         if (mirr_rule && sw_id == mirr_rule->index) {
8300                 if (on) {
8301                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8302                         return -EEXIST;
8303                 } else {
8304                         ret = i40e_aq_del_mirror_rule(hw, seid,
8305                                         mirr_rule->rule_type,
8306                                         mirr_rule->entries,
8307                                         mirr_rule->num_entries, mirr_rule->id);
8308                         if (ret < 0) {
8309                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8310                                                    " ret = %d, aq_err = %d.",
8311                                                    ret, hw->aq.asq_last_status);
8312                                 return -ENOSYS;
8313                         }
8314                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8315                         rte_free(mirr_rule);
8316                         pf->nb_mirror_rule--;
8317                         return 0;
8318                 }
8319         } else if (!on) {
8320                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8321                 return -ENOENT;
8322         }
8323
8324         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8325                                 sizeof(struct i40e_mirror_rule) , 0);
8326         if (!mirr_rule) {
8327                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8328                 return I40E_ERR_NO_MEMORY;
8329         }
8330         switch (mirror_conf->rule_type) {
8331         case ETH_MIRROR_VLAN:
8332                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8333                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8334                                 mirr_rule->entries[j] =
8335                                         mirror_conf->vlan.vlan_id[i];
8336                                 j++;
8337                         }
8338                 }
8339                 if (j == 0) {
8340                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8341                         rte_free(mirr_rule);
8342                         return -EINVAL;
8343                 }
8344                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8345                 break;
8346         case ETH_MIRROR_VIRTUAL_POOL_UP:
8347         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8348                 /* check if the specified pool bit is out of range */
8349                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8350                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8351                         rte_free(mirr_rule);
8352                         return -EINVAL;
8353                 }
8354                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8355                         if (mirror_conf->pool_mask & (1ULL << i)) {
8356                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8357                                 j++;
8358                         }
8359                 }
8360                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8361                         /* add pf vsi to entries */
8362                         mirr_rule->entries[j] = pf->main_vsi_seid;
8363                         j++;
8364                 }
8365                 if (j == 0) {
8366                         PMD_DRV_LOG(ERR, "pool is not specified.");
8367                         rte_free(mirr_rule);
8368                         return -EINVAL;
8369                 }
8370                 /* egress and ingress in aq commands means from switch but not port */
8371                 mirr_rule->rule_type =
8372                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8373                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8374                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8375                 break;
8376         case ETH_MIRROR_UPLINK_PORT:
8377                 /* egress and ingress in aq commands means from switch but not port*/
8378                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8379                 break;
8380         case ETH_MIRROR_DOWNLINK_PORT:
8381                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8382                 break;
8383         default:
8384                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8385                         mirror_conf->rule_type);
8386                 rte_free(mirr_rule);
8387                 return -EINVAL;
8388         }
8389
8390         /* If the dst_pool is equal to vf_num, consider it as PF */
8391         if (mirror_conf->dst_pool == pf->vf_num)
8392                 dst_seid = pf->main_vsi_seid;
8393         else
8394                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8395
8396         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8397                                       mirr_rule->rule_type, mirr_rule->entries,
8398                                       j, &rule_id);
8399         if (ret < 0) {
8400                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8401                                    " ret = %d, aq_err = %d.",
8402                                    ret, hw->aq.asq_last_status);
8403                 rte_free(mirr_rule);
8404                 return -ENOSYS;
8405         }
8406
8407         mirr_rule->index = sw_id;
8408         mirr_rule->num_entries = j;
8409         mirr_rule->id = rule_id;
8410         mirr_rule->dst_vsi_seid = dst_seid;
8411
8412         if (parent)
8413                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8414         else
8415                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8416
8417         pf->nb_mirror_rule++;
8418         return 0;
8419 }
8420
8421 /**
8422  * i40e_mirror_rule_reset
8423  * @dev: pointer to the device
8424  * @sw_id: mirror rule's sw_id
8425  *
8426  * reset a mirror rule.
8427  *
8428  **/
8429 static int
8430 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8431 {
8432         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8433         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8434         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8435         uint16_t seid;
8436         int ret;
8437
8438         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8439
8440         seid = pf->main_vsi->veb->seid;
8441
8442         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8443                 if (sw_id == it->index) {
8444                         mirr_rule = it;
8445                         break;
8446                 }
8447         }
8448         if (mirr_rule) {
8449                 ret = i40e_aq_del_mirror_rule(hw, seid,
8450                                 mirr_rule->rule_type,
8451                                 mirr_rule->entries,
8452                                 mirr_rule->num_entries, mirr_rule->id);
8453                 if (ret < 0) {
8454                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8455                                            " status = %d, aq_err = %d.",
8456                                            ret, hw->aq.asq_last_status);
8457                         return -ENOSYS;
8458                 }
8459                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8460                 rte_free(mirr_rule);
8461                 pf->nb_mirror_rule--;
8462         } else {
8463                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8464                 return -ENOENT;
8465         }
8466         return 0;
8467 }
8468
8469 static uint64_t
8470 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8471 {
8472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8473         uint64_t systim_cycles;
8474
8475         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8476         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8477                         << 32;
8478
8479         return systim_cycles;
8480 }
8481
8482 static uint64_t
8483 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8484 {
8485         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8486         uint64_t rx_tstamp;
8487
8488         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8489         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8490                         << 32;
8491
8492         return rx_tstamp;
8493 }
8494
8495 static uint64_t
8496 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8497 {
8498         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8499         uint64_t tx_tstamp;
8500
8501         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8502         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8503                         << 32;
8504
8505         return tx_tstamp;
8506 }
8507
8508 static void
8509 i40e_start_timecounters(struct rte_eth_dev *dev)
8510 {
8511         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8512         struct i40e_adapter *adapter =
8513                         (struct i40e_adapter *)dev->data->dev_private;
8514         struct rte_eth_link link;
8515         uint32_t tsync_inc_l;
8516         uint32_t tsync_inc_h;
8517
8518         /* Get current link speed. */
8519         memset(&link, 0, sizeof(link));
8520         i40e_dev_link_update(dev, 1);
8521         rte_i40e_dev_atomic_read_link_status(dev, &link);
8522
8523         switch (link.link_speed) {
8524         case ETH_SPEED_NUM_40G:
8525                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8526                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8527                 break;
8528         case ETH_SPEED_NUM_10G:
8529                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8530                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8531                 break;
8532         case ETH_SPEED_NUM_1G:
8533                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8534                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8535                 break;
8536         default:
8537                 tsync_inc_l = 0x0;
8538                 tsync_inc_h = 0x0;
8539         }
8540
8541         /* Set the timesync increment value. */
8542         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8543         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8544
8545         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8546         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8547         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8548
8549         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8550         adapter->systime_tc.cc_shift = 0;
8551         adapter->systime_tc.nsec_mask = 0;
8552
8553         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8554         adapter->rx_tstamp_tc.cc_shift = 0;
8555         adapter->rx_tstamp_tc.nsec_mask = 0;
8556
8557         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8558         adapter->tx_tstamp_tc.cc_shift = 0;
8559         adapter->tx_tstamp_tc.nsec_mask = 0;
8560 }
8561
8562 static int
8563 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8564 {
8565         struct i40e_adapter *adapter =
8566                         (struct i40e_adapter *)dev->data->dev_private;
8567
8568         adapter->systime_tc.nsec += delta;
8569         adapter->rx_tstamp_tc.nsec += delta;
8570         adapter->tx_tstamp_tc.nsec += delta;
8571
8572         return 0;
8573 }
8574
8575 static int
8576 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8577 {
8578         uint64_t ns;
8579         struct i40e_adapter *adapter =
8580                         (struct i40e_adapter *)dev->data->dev_private;
8581
8582         ns = rte_timespec_to_ns(ts);
8583
8584         /* Set the timecounters to a new value. */
8585         adapter->systime_tc.nsec = ns;
8586         adapter->rx_tstamp_tc.nsec = ns;
8587         adapter->tx_tstamp_tc.nsec = ns;
8588
8589         return 0;
8590 }
8591
8592 static int
8593 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8594 {
8595         uint64_t ns, systime_cycles;
8596         struct i40e_adapter *adapter =
8597                         (struct i40e_adapter *)dev->data->dev_private;
8598
8599         systime_cycles = i40e_read_systime_cyclecounter(dev);
8600         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8601         *ts = rte_ns_to_timespec(ns);
8602
8603         return 0;
8604 }
8605
8606 static int
8607 i40e_timesync_enable(struct rte_eth_dev *dev)
8608 {
8609         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8610         uint32_t tsync_ctl_l;
8611         uint32_t tsync_ctl_h;
8612
8613         /* Stop the timesync system time. */
8614         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8615         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8616         /* Reset the timesync system time value. */
8617         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8618         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8619
8620         i40e_start_timecounters(dev);
8621
8622         /* Clear timesync registers. */
8623         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8624         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8625         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8626         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8627         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8628         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8629
8630         /* Enable timestamping of PTP packets. */
8631         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8632         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8633
8634         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8635         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8636         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8637
8638         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8639         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8640
8641         return 0;
8642 }
8643
8644 static int
8645 i40e_timesync_disable(struct rte_eth_dev *dev)
8646 {
8647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8648         uint32_t tsync_ctl_l;
8649         uint32_t tsync_ctl_h;
8650
8651         /* Disable timestamping of transmitted PTP packets. */
8652         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8653         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8654
8655         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8656         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8657
8658         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8659         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8660
8661         /* Reset the timesync increment value. */
8662         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8663         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8664
8665         return 0;
8666 }
8667
8668 static int
8669 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8670                                 struct timespec *timestamp, uint32_t flags)
8671 {
8672         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8673         struct i40e_adapter *adapter =
8674                 (struct i40e_adapter *)dev->data->dev_private;
8675
8676         uint32_t sync_status;
8677         uint32_t index = flags & 0x03;
8678         uint64_t rx_tstamp_cycles;
8679         uint64_t ns;
8680
8681         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8682         if ((sync_status & (1 << index)) == 0)
8683                 return -EINVAL;
8684
8685         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8686         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8687         *timestamp = rte_ns_to_timespec(ns);
8688
8689         return 0;
8690 }
8691
8692 static int
8693 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8694                                 struct timespec *timestamp)
8695 {
8696         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8697         struct i40e_adapter *adapter =
8698                 (struct i40e_adapter *)dev->data->dev_private;
8699
8700         uint32_t sync_status;
8701         uint64_t tx_tstamp_cycles;
8702         uint64_t ns;
8703
8704         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8705         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8706                 return -EINVAL;
8707
8708         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8709         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8710         *timestamp = rte_ns_to_timespec(ns);
8711
8712         return 0;
8713 }
8714
8715 /*
8716  * i40e_parse_dcb_configure - parse dcb configure from user
8717  * @dev: the device being configured
8718  * @dcb_cfg: pointer of the result of parse
8719  * @*tc_map: bit map of enabled traffic classes
8720  *
8721  * Returns 0 on success, negative value on failure
8722  */
8723 static int
8724 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8725                          struct i40e_dcbx_config *dcb_cfg,
8726                          uint8_t *tc_map)
8727 {
8728         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8729         uint8_t i, tc_bw, bw_lf;
8730
8731         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8732
8733         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8734         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8735                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8736                 return -EINVAL;
8737         }
8738
8739         /* assume each tc has the same bw */
8740         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8741         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8742                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8743         /* to ensure the sum of tcbw is equal to 100 */
8744         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8745         for (i = 0; i < bw_lf; i++)
8746                 dcb_cfg->etscfg.tcbwtable[i]++;
8747
8748         /* assume each tc has the same Transmission Selection Algorithm */
8749         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8750                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8751
8752         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8753                 dcb_cfg->etscfg.prioritytable[i] =
8754                                 dcb_rx_conf->dcb_tc[i];
8755
8756         /* FW needs one App to configure HW */
8757         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8758         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8759         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8760         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8761
8762         if (dcb_rx_conf->nb_tcs == 0)
8763                 *tc_map = 1; /* tc0 only */
8764         else
8765                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8766
8767         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8768                 dcb_cfg->pfc.willing = 0;
8769                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8770                 dcb_cfg->pfc.pfcenable = *tc_map;
8771         }
8772         return 0;
8773 }
8774
8775
8776 static enum i40e_status_code
8777 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8778                               struct i40e_aqc_vsi_properties_data *info,
8779                               uint8_t enabled_tcmap)
8780 {
8781         enum i40e_status_code ret;
8782         int i, total_tc = 0;
8783         uint16_t qpnum_per_tc, bsf, qp_idx;
8784         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8785         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8786         uint16_t used_queues;
8787
8788         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8789         if (ret != I40E_SUCCESS)
8790                 return ret;
8791
8792         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8793                 if (enabled_tcmap & (1 << i))
8794                         total_tc++;
8795         }
8796         if (total_tc == 0)
8797                 total_tc = 1;
8798         vsi->enabled_tc = enabled_tcmap;
8799
8800         /* different VSI has different queues assigned */
8801         if (vsi->type == I40E_VSI_MAIN)
8802                 used_queues = dev_data->nb_rx_queues -
8803                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8804         else if (vsi->type == I40E_VSI_VMDQ2)
8805                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8806         else {
8807                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8808                 return I40E_ERR_NO_AVAILABLE_VSI;
8809         }
8810
8811         qpnum_per_tc = used_queues / total_tc;
8812         /* Number of queues per enabled TC */
8813         if (qpnum_per_tc == 0) {
8814                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8815                 return I40E_ERR_INVALID_QP_ID;
8816         }
8817         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8818                                 I40E_MAX_Q_PER_TC);
8819         bsf = rte_bsf32(qpnum_per_tc);
8820
8821         /**
8822          * Configure TC and queue mapping parameters, for enabled TC,
8823          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8824          * default queue will serve it.
8825          */
8826         qp_idx = 0;
8827         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8828                 if (vsi->enabled_tc & (1 << i)) {
8829                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8830                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8831                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8832                         qp_idx += qpnum_per_tc;
8833                 } else
8834                         info->tc_mapping[i] = 0;
8835         }
8836
8837         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8838         if (vsi->type == I40E_VSI_SRIOV) {
8839                 info->mapping_flags |=
8840                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8841                 for (i = 0; i < vsi->nb_qps; i++)
8842                         info->queue_mapping[i] =
8843                                 rte_cpu_to_le_16(vsi->base_queue + i);
8844         } else {
8845                 info->mapping_flags |=
8846                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8847                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8848         }
8849         info->valid_sections |=
8850                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8851
8852         return I40E_SUCCESS;
8853 }
8854
8855 /*
8856  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8857  * @veb: VEB to be configured
8858  * @tc_map: enabled TC bitmap
8859  *
8860  * Returns 0 on success, negative value on failure
8861  */
8862 static enum i40e_status_code
8863 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8864 {
8865         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8866         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8867         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8868         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8869         enum i40e_status_code ret = I40E_SUCCESS;
8870         int i;
8871         uint32_t bw_max;
8872
8873         /* Check if enabled_tc is same as existing or new TCs */
8874         if (veb->enabled_tc == tc_map)
8875                 return ret;
8876
8877         /* configure tc bandwidth */
8878         memset(&veb_bw, 0, sizeof(veb_bw));
8879         veb_bw.tc_valid_bits = tc_map;
8880         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8881         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8882                 if (tc_map & BIT_ULL(i))
8883                         veb_bw.tc_bw_share_credits[i] = 1;
8884         }
8885         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8886                                                    &veb_bw, NULL);
8887         if (ret) {
8888                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8889                                   " per TC failed = %d",
8890                                   hw->aq.asq_last_status);
8891                 return ret;
8892         }
8893
8894         memset(&ets_query, 0, sizeof(ets_query));
8895         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8896                                                    &ets_query, NULL);
8897         if (ret != I40E_SUCCESS) {
8898                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8899                                  " configuration %u", hw->aq.asq_last_status);
8900                 return ret;
8901         }
8902         memset(&bw_query, 0, sizeof(bw_query));
8903         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8904                                                   &bw_query, NULL);
8905         if (ret != I40E_SUCCESS) {
8906                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8907                                  " configuration %u", hw->aq.asq_last_status);
8908                 return ret;
8909         }
8910
8911         /* store and print out BW info */
8912         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8913         veb->bw_info.bw_max = ets_query.tc_bw_max;
8914         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8915         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8916         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8917                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8918                      I40E_16_BIT_WIDTH);
8919         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8920                 veb->bw_info.bw_ets_share_credits[i] =
8921                                 bw_query.tc_bw_share_credits[i];
8922                 veb->bw_info.bw_ets_credits[i] =
8923                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8924                 /* 4 bits per TC, 4th bit is reserved */
8925                 veb->bw_info.bw_ets_max[i] =
8926                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8927                                   RTE_LEN2MASK(3, uint8_t));
8928                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8929                             veb->bw_info.bw_ets_share_credits[i]);
8930                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8931                             veb->bw_info.bw_ets_credits[i]);
8932                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8933                             veb->bw_info.bw_ets_max[i]);
8934         }
8935
8936         veb->enabled_tc = tc_map;
8937
8938         return ret;
8939 }
8940
8941
8942 /*
8943  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8944  * @vsi: VSI to be configured
8945  * @tc_map: enabled TC bitmap
8946  *
8947  * Returns 0 on success, negative value on failure
8948  */
8949 static enum i40e_status_code
8950 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8951 {
8952         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8953         struct i40e_vsi_context ctxt;
8954         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8955         enum i40e_status_code ret = I40E_SUCCESS;
8956         int i;
8957
8958         /* Check if enabled_tc is same as existing or new TCs */
8959         if (vsi->enabled_tc == tc_map)
8960                 return ret;
8961
8962         /* configure tc bandwidth */
8963         memset(&bw_data, 0, sizeof(bw_data));
8964         bw_data.tc_valid_bits = tc_map;
8965         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8966         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8967                 if (tc_map & BIT_ULL(i))
8968                         bw_data.tc_bw_credits[i] = 1;
8969         }
8970         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8971         if (ret) {
8972                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8973                         " per TC failed = %d",
8974                         hw->aq.asq_last_status);
8975                 goto out;
8976         }
8977         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8978                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8979
8980         /* Update Queue Pairs Mapping for currently enabled UPs */
8981         ctxt.seid = vsi->seid;
8982         ctxt.pf_num = hw->pf_id;
8983         ctxt.vf_num = 0;
8984         ctxt.uplink_seid = vsi->uplink_seid;
8985         ctxt.info = vsi->info;
8986         i40e_get_cap(hw);
8987         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8988         if (ret)
8989                 goto out;
8990
8991         /* Update the VSI after updating the VSI queue-mapping information */
8992         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8993         if (ret) {
8994                 PMD_INIT_LOG(ERR, "Failed to configure "
8995                             "TC queue mapping = %d",
8996                             hw->aq.asq_last_status);
8997                 goto out;
8998         }
8999         /* update the local VSI info with updated queue map */
9000         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9001                                         sizeof(vsi->info.tc_mapping));
9002         (void)rte_memcpy(&vsi->info.queue_mapping,
9003                         &ctxt.info.queue_mapping,
9004                 sizeof(vsi->info.queue_mapping));
9005         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9006         vsi->info.valid_sections = 0;
9007
9008         /* query and update current VSI BW information */
9009         ret = i40e_vsi_get_bw_config(vsi);
9010         if (ret) {
9011                 PMD_INIT_LOG(ERR,
9012                          "Failed updating vsi bw info, err %s aq_err %s",
9013                          i40e_stat_str(hw, ret),
9014                          i40e_aq_str(hw, hw->aq.asq_last_status));
9015                 goto out;
9016         }
9017
9018         vsi->enabled_tc = tc_map;
9019
9020 out:
9021         return ret;
9022 }
9023
9024 /*
9025  * i40e_dcb_hw_configure - program the dcb setting to hw
9026  * @pf: pf the configuration is taken on
9027  * @new_cfg: new configuration
9028  * @tc_map: enabled TC bitmap
9029  *
9030  * Returns 0 on success, negative value on failure
9031  */
9032 static enum i40e_status_code
9033 i40e_dcb_hw_configure(struct i40e_pf *pf,
9034                       struct i40e_dcbx_config *new_cfg,
9035                       uint8_t tc_map)
9036 {
9037         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9038         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9039         struct i40e_vsi *main_vsi = pf->main_vsi;
9040         struct i40e_vsi_list *vsi_list;
9041         enum i40e_status_code ret;
9042         int i;
9043         uint32_t val;
9044
9045         /* Use the FW API if FW > v4.4*/
9046         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9047               (hw->aq.fw_maj_ver >= 5))) {
9048                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9049                                   " to configure DCB");
9050                 return I40E_ERR_FIRMWARE_API_VERSION;
9051         }
9052
9053         /* Check if need reconfiguration */
9054         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9055                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9056                 return I40E_SUCCESS;
9057         }
9058
9059         /* Copy the new config to the current config */
9060         *old_cfg = *new_cfg;
9061         old_cfg->etsrec = old_cfg->etscfg;
9062         ret = i40e_set_dcb_config(hw);
9063         if (ret) {
9064                 PMD_INIT_LOG(ERR,
9065                          "Set DCB Config failed, err %s aq_err %s\n",
9066                          i40e_stat_str(hw, ret),
9067                          i40e_aq_str(hw, hw->aq.asq_last_status));
9068                 return ret;
9069         }
9070         /* set receive Arbiter to RR mode and ETS scheme by default */
9071         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9072                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9073                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9074                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9075                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9076                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9077                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9078                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9079                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9080                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9081                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9082                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9083                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9084         }
9085         /* get local mib to check whether it is configured correctly */
9086         /* IEEE mode */
9087         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9088         /* Get Local DCB Config */
9089         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9090                                      &hw->local_dcbx_config);
9091
9092         /* if Veb is created, need to update TC of it at first */
9093         if (main_vsi->veb) {
9094                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9095                 if (ret)
9096                         PMD_INIT_LOG(WARNING,
9097                                  "Failed configuring TC for VEB seid=%d\n",
9098                                  main_vsi->veb->seid);
9099         }
9100         /* Update each VSI */
9101         i40e_vsi_config_tc(main_vsi, tc_map);
9102         if (main_vsi->veb) {
9103                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9104                         /* Beside main VSI and VMDQ VSIs, only enable default
9105                          * TC for other VSIs
9106                          */
9107                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9108                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9109                                                          tc_map);
9110                         else
9111                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9112                                                          I40E_DEFAULT_TCMAP);
9113                         if (ret)
9114                                 PMD_INIT_LOG(WARNING,
9115                                          "Failed configuring TC for VSI seid=%d\n",
9116                                          vsi_list->vsi->seid);
9117                         /* continue */
9118                 }
9119         }
9120         return I40E_SUCCESS;
9121 }
9122
9123 /*
9124  * i40e_dcb_init_configure - initial dcb config
9125  * @dev: device being configured
9126  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9127  *
9128  * Returns 0 on success, negative value on failure
9129  */
9130 static int
9131 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9132 {
9133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9135         int ret = 0;
9136
9137         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9138                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9139                 return -ENOTSUP;
9140         }
9141
9142         /* DCB initialization:
9143          * Update DCB configuration from the Firmware and configure
9144          * LLDP MIB change event.
9145          */
9146         if (sw_dcb == TRUE) {
9147                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9148                 if (ret != I40E_SUCCESS)
9149                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9150
9151                 ret = i40e_init_dcb(hw);
9152                 /* if sw_dcb, lldp agent is stopped, the return from
9153                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9154                  * adminq status.
9155                  */
9156                 if (ret != I40E_SUCCESS &&
9157                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9158                         memset(&hw->local_dcbx_config, 0,
9159                                 sizeof(struct i40e_dcbx_config));
9160                         /* set dcb default configuration */
9161                         hw->local_dcbx_config.etscfg.willing = 0;
9162                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9163                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9164                         hw->local_dcbx_config.etscfg.tsatable[0] =
9165                                                 I40E_IEEE_TSA_ETS;
9166                         hw->local_dcbx_config.etsrec =
9167                                 hw->local_dcbx_config.etscfg;
9168                         hw->local_dcbx_config.pfc.willing = 0;
9169                         hw->local_dcbx_config.pfc.pfccap =
9170                                                 I40E_MAX_TRAFFIC_CLASS;
9171                         /* FW needs one App to configure HW */
9172                         hw->local_dcbx_config.numapps = 1;
9173                         hw->local_dcbx_config.app[0].selector =
9174                                                 I40E_APP_SEL_ETHTYPE;
9175                         hw->local_dcbx_config.app[0].priority = 3;
9176                         hw->local_dcbx_config.app[0].protocolid =
9177                                                 I40E_APP_PROTOID_FCOE;
9178                         ret = i40e_set_dcb_config(hw);
9179                         if (ret) {
9180                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9181                                         " err = %d, aq_err = %d.", ret,
9182                                           hw->aq.asq_last_status);
9183                                 return -ENOSYS;
9184                         }
9185                 } else {
9186                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9187                                           " aq_err = %d.", ret,
9188                                           hw->aq.asq_last_status);
9189                         return -ENOTSUP;
9190                 }
9191         } else {
9192                 ret = i40e_aq_start_lldp(hw, NULL);
9193                 if (ret != I40E_SUCCESS)
9194                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9195
9196                 ret = i40e_init_dcb(hw);
9197                 if (!ret) {
9198                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9199                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9200                                                   " DCBX offload.");
9201                                 return -ENOTSUP;
9202                         }
9203                 } else {
9204                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9205                                           " aq_err = %d.", ret,
9206                                           hw->aq.asq_last_status);
9207                         return -ENOTSUP;
9208                 }
9209         }
9210         return 0;
9211 }
9212
9213 /*
9214  * i40e_dcb_setup - setup dcb related config
9215  * @dev: device being configured
9216  *
9217  * Returns 0 on success, negative value on failure
9218  */
9219 static int
9220 i40e_dcb_setup(struct rte_eth_dev *dev)
9221 {
9222         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9223         struct i40e_dcbx_config dcb_cfg;
9224         uint8_t tc_map = 0;
9225         int ret = 0;
9226
9227         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9228                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9229                 return -ENOTSUP;
9230         }
9231
9232         if (pf->vf_num != 0)
9233                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9234
9235         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9236         if (ret) {
9237                 PMD_INIT_LOG(ERR, "invalid dcb config");
9238                 return -EINVAL;
9239         }
9240         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9241         if (ret) {
9242                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9243                 return -ENOSYS;
9244         }
9245
9246         return 0;
9247 }
9248
9249 static int
9250 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9251                       struct rte_eth_dcb_info *dcb_info)
9252 {
9253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9254         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9255         struct i40e_vsi *vsi = pf->main_vsi;
9256         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9257         uint16_t bsf, tc_mapping;
9258         int i, j = 0;
9259
9260         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9261                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9262         else
9263                 dcb_info->nb_tcs = 1;
9264         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9265                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9266         for (i = 0; i < dcb_info->nb_tcs; i++)
9267                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9268
9269         /* get queue mapping if vmdq is disabled */
9270         if (!pf->nb_cfg_vmdq_vsi) {
9271                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9272                         if (!(vsi->enabled_tc & (1 << i)))
9273                                 continue;
9274                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9275                         dcb_info->tc_queue.tc_rxq[j][i].base =
9276                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9277                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9278                         dcb_info->tc_queue.tc_txq[j][i].base =
9279                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9280                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9281                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9282                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9283                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9284                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9285                 }
9286                 return 0;
9287         }
9288
9289         /* get queue mapping if vmdq is enabled */
9290         do {
9291                 vsi = pf->vmdq[j].vsi;
9292                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9293                         if (!(vsi->enabled_tc & (1 << i)))
9294                                 continue;
9295                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9296                         dcb_info->tc_queue.tc_rxq[j][i].base =
9297                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9298                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9299                         dcb_info->tc_queue.tc_txq[j][i].base =
9300                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9301                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9302                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9303                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9304                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9305                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9306                 }
9307                 j++;
9308         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9309         return 0;
9310 }
9311
9312 static int
9313 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9314 {
9315         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9317         uint16_t interval =
9318                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9319         uint16_t msix_intr;
9320
9321         msix_intr = intr_handle->intr_vec[queue_id];
9322         if (msix_intr == I40E_MISC_VEC_ID)
9323                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9324                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9325                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9326                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9327                                (interval <<
9328                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9329         else
9330                 I40E_WRITE_REG(hw,
9331                                I40E_PFINT_DYN_CTLN(msix_intr -
9332                                                    I40E_RX_VEC_START),
9333                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9334                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9335                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9336                                (interval <<
9337                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9338
9339         I40E_WRITE_FLUSH(hw);
9340         rte_intr_enable(&dev->pci_dev->intr_handle);
9341
9342         return 0;
9343 }
9344
9345 static int
9346 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9347 {
9348         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9350         uint16_t msix_intr;
9351
9352         msix_intr = intr_handle->intr_vec[queue_id];
9353         if (msix_intr == I40E_MISC_VEC_ID)
9354                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9355         else
9356                 I40E_WRITE_REG(hw,
9357                                I40E_PFINT_DYN_CTLN(msix_intr -
9358                                                    I40E_RX_VEC_START),
9359                                0);
9360         I40E_WRITE_FLUSH(hw);
9361
9362         return 0;
9363 }
9364
9365 static int i40e_get_regs(struct rte_eth_dev *dev,
9366                          struct rte_dev_reg_info *regs)
9367 {
9368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9369         uint32_t *ptr_data = regs->data;
9370         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9371         const struct i40e_reg_info *reg_info;
9372
9373         if (ptr_data == NULL) {
9374                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9375                 regs->width = sizeof(uint32_t);
9376                 return 0;
9377         }
9378
9379         /* The first few registers have to be read using AQ operations */
9380         reg_idx = 0;
9381         while (i40e_regs_adminq[reg_idx].name) {
9382                 reg_info = &i40e_regs_adminq[reg_idx++];
9383                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9384                         for (arr_idx2 = 0;
9385                                         arr_idx2 <= reg_info->count2;
9386                                         arr_idx2++) {
9387                                 reg_offset = arr_idx * reg_info->stride1 +
9388                                         arr_idx2 * reg_info->stride2;
9389                                 reg_offset += reg_info->base_addr;
9390                                 ptr_data[reg_offset >> 2] =
9391                                         i40e_read_rx_ctl(hw, reg_offset);
9392                         }
9393         }
9394
9395         /* The remaining registers can be read using primitives */
9396         reg_idx = 0;
9397         while (i40e_regs_others[reg_idx].name) {
9398                 reg_info = &i40e_regs_others[reg_idx++];
9399                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9400                         for (arr_idx2 = 0;
9401                                         arr_idx2 <= reg_info->count2;
9402                                         arr_idx2++) {
9403                                 reg_offset = arr_idx * reg_info->stride1 +
9404                                         arr_idx2 * reg_info->stride2;
9405                                 reg_offset += reg_info->base_addr;
9406                                 ptr_data[reg_offset >> 2] =
9407                                         I40E_READ_REG(hw, reg_offset);
9408                         }
9409         }
9410
9411         return 0;
9412 }
9413
9414 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9415 {
9416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9417
9418         /* Convert word count to byte count */
9419         return hw->nvm.sr_size << 1;
9420 }
9421
9422 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9423                            struct rte_dev_eeprom_info *eeprom)
9424 {
9425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9426         uint16_t *data = eeprom->data;
9427         uint16_t offset, length, cnt_words;
9428         int ret_code;
9429
9430         offset = eeprom->offset >> 1;
9431         length = eeprom->length >> 1;
9432         cnt_words = length;
9433
9434         if (offset > hw->nvm.sr_size ||
9435                 offset + length > hw->nvm.sr_size) {
9436                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9437                 return -EINVAL;
9438         }
9439
9440         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9441
9442         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9443         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9444                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9445                 return -EIO;
9446         }
9447
9448         return 0;
9449 }
9450
9451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9452                                       struct ether_addr *mac_addr)
9453 {
9454         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9455
9456         if (!is_valid_assigned_ether_addr(mac_addr)) {
9457                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9458                 return;
9459         }
9460
9461         /* Flags: 0x3 updates port address */
9462         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9463 }
9464
9465 static int
9466 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9467 {
9468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9469         struct rte_eth_dev_data *dev_data = pf->dev_data;
9470         uint32_t frame_size = mtu + ETHER_HDR_LEN
9471                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9472         int ret = 0;
9473
9474         /* check if mtu is within the allowed range */
9475         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9476                 return -EINVAL;
9477
9478         /* mtu setting is forbidden if port is start */
9479         if (dev_data->dev_started) {
9480                 PMD_DRV_LOG(ERR,
9481                             "port %d must be stopped before configuration\n",
9482                             dev_data->port_id);
9483                 return -EBUSY;
9484         }
9485
9486         if (frame_size > ETHER_MAX_LEN)
9487                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9488         else
9489                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9490
9491         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9492
9493         return ret;
9494 }