drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  79
  80 /* Flow control default timer */
  81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  82
  83 /* Flow control default high water */
  84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  85
  86 /* Flow control default low water */
  87 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Receive Average Packet Size in Byte*/
  99 #define I40E_PACKET_AVERAGE_SIZE 128
 100
 101 /* Mask of PF interrupt causes */
 102 #define I40E_PFINT_ICR0_ENA_MASK ( \
 103                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 104                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 105                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 106                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 107                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 109                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 113
 114 #define I40E_FLOW_TYPES ( \
 115         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 126
 127 /* Additional timesync values. */
 128 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA     0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 133 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 134
 135 #define I40E_MAX_PERCENT            100
 136 #define I40E_DEFAULT_DCB_APP_NUM    1
 137 #define I40E_DEFAULT_DCB_APP_PRIO   3
 138
 139 #define I40E_INSET_NONE            0x00000000000000000ULL
 140
 141 /* bit0 ~ bit 7 */
 142 #define I40E_INSET_DMAC            0x0000000000000001ULL
 143 #define I40E_INSET_SMAC            0x0000000000000002ULL
 144 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 145 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 146 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 147
 148 /* bit 8 ~ bit 15 */
 149 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 150 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 151 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 152 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 153 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 154 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 155 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 156
 157 /* bit 16 ~ bit 31 */
 158 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 159 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 160 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 161 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 162 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 163 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 164 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 165 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 166
 167 /* bit 32 ~ bit 47, tunnel fields */
 168 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 169 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 170 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 171 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 172 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 173 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 174
 175 /* bit 48 ~ bit 55 */
 176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 177
 178 /* bit 56 ~ bit 63, Flex Payload */
 179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD \
 188         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 189         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 190         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 191         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 192
 193 /**
 194  * Below are values for writing un-exposed registers suggested
 195  * by silicon experts
 196  */
 197 /* Destination MAC address */
 198 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 199 /* Source MAC address */
 200 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 202 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 205 /* Single VLAN tag in the inner L2 header */
 206 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 207 /* Source IPv4 address */
 208 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 209 /* Destination IPv4 address */
 210 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 211 /* IPv4 Type of Service (TOS) */
 212 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 213 /* IPv4 Protocol */
 214 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 215 /* IPv4 Time to Live */
 216 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 217 /* Source IPv6 address */
 218 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 219 /* Destination IPv6 address */
 220 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 221 /* IPv6 Traffic Class (TC) */
 222 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 223 /* IPv6 Next Header */
 224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 225 /* IPv6 Hop Limit */
 226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263 /* all 8 words flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 265 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 266
 267 #define I40E_TRANSLATE_INSET 0
 268 #define I40E_TRANSLATE_REG   1
 269
 270 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 271 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 272 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 273 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 275 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 276
 277 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 280         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 281
 282 /* PCI offset for querying capability */
 283 #define PCI_DEV_CAP_REG            0xA4
 284 /* PCI offset for enabling/disabling Extended Tag */
 285 #define PCI_DEV_CTRL_REG           0xA8
 286 /* Bit mask of Extended Tag capability */
 287 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 288 /* Bit shift of Extended Tag enable/disable */
 289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 290 /* Bit mask of Extended Tag enable/disable */
 291 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 292
 293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 295 static int i40e_dev_configure(struct rte_eth_dev *dev);
 296 static int i40e_dev_start(struct rte_eth_dev *dev);
 297 static void i40e_dev_stop(struct rte_eth_dev *dev);
 298 static void i40e_dev_close(struct rte_eth_dev *dev);
 299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 306                                struct rte_eth_stats *stats);
 307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 308                                struct rte_eth_xstat *xstats, unsigned n);
 309 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 310                                      struct rte_eth_xstat_name *xstats_names,
 311                                      unsigned limit);
 312 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 313 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 314                                             uint16_t queue_id,
 315                                             uint8_t stat_idx,
 316                                             uint8_t is_rx);
 317 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 318                               struct rte_eth_dev_info *dev_info);
 319 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 320                                 uint16_t vlan_id,
 321                                 int on);
 322 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 323                               enum rte_vlan_type vlan_type,
 324                               uint16_t tpid);
 325 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 326 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 327                                       uint16_t queue,
 328                                       int on);
 329 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 330 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 331 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 332 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 333                               struct rte_eth_fc_conf *fc_conf);
 334 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 335                               struct rte_eth_fc_conf *fc_conf);
 336 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 337                                        struct rte_eth_pfc_conf *pfc_conf);
 338 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 339                           struct ether_addr *mac_addr,
 340                           uint32_t index,
 341                           uint32_t pool);
 342 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 343 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 344                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 345                                     uint16_t reta_size);
 346 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 347                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                    uint16_t reta_size);
 349
 350 static int i40e_get_cap(struct i40e_hw *hw);
 351 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 352 static int i40e_pf_setup(struct i40e_pf *pf);
 353 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 354 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 355 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 356 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 357 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 358                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 359 static void i40e_stat_update_48(struct i40e_hw *hw,
 360                                uint32_t hireg,
 361                                uint32_t loreg,
 362                                bool offset_loaded,
 363                                uint64_t *offset,
 364                                uint64_t *stat);
 365 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 366 static void i40e_dev_interrupt_handler(
 367                 __rte_unused struct rte_intr_handle *handle, void *param);
 368 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 369                                 uint32_t base, uint32_t num);
 370 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 371 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 372                         uint32_t base);
 373 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 374                         uint16_t num);
 375 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 376 static int i40e_veb_release(struct i40e_veb *veb);
 377 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 378                                                 struct i40e_vsi *vsi);
 379 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 380 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 381 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 382                                              struct i40e_macvlan_filter *mv_f,
 383                                              int num,
 384                                              struct ether_addr *addr);
 385 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 386                                              struct i40e_macvlan_filter *mv_f,
 387                                              int num,
 388                                              uint16_t vlan);
 389 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 390 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 391                                     struct rte_eth_rss_conf *rss_conf);
 392 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 393                                       struct rte_eth_rss_conf *rss_conf);
 394 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 395                                         struct rte_eth_udp_tunnel *udp_tunnel);
 396 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 397                                         struct rte_eth_udp_tunnel *udp_tunnel);
 398 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 399 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 400                         struct rte_eth_ethertype_filter *filter,
 401                         bool add);
 402 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 403                                 enum rte_filter_op filter_op,
 404                                 void *arg);
 405 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 406                                 enum rte_filter_type filter_type,
 407                                 enum rte_filter_op filter_op,
 408                                 void *arg);
 409 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 410                                   struct rte_eth_dcb_info *dcb_info);
 411 static void i40e_configure_registers(struct i40e_hw *hw);
 412 static void i40e_hw_init(struct rte_eth_dev *dev);
 413 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 414 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 415                         struct rte_eth_mirror_conf *mirror_conf,
 416                         uint8_t sw_id, uint8_t on);
 417 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 418
 419 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 420 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 421 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 422                                            struct timespec *timestamp,
 423                                            uint32_t flags);
 424 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp);
 426 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 427
 428 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 429
 430 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 431                                    struct timespec *timestamp);
 432 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 433                                     const struct timespec *timestamp);
 434
 435 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 436                                          uint16_t queue_id);
 437 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 438                                           uint16_t queue_id);
 439
 440 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 441
 442 static int i40e_get_regs(struct rte_eth_dev *dev,
 443                          struct rte_dev_reg_info *regs);
 444
 445 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 446
 447 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 448                            struct rte_dev_eeprom_info *eeprom);
 449
 450 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 451                                       struct ether_addr *mac_addr);
 452
 453 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 454
 455 static const struct rte_pci_id pci_id_i40e_map[] = {
 456 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 457 #include "rte_pci_dev_ids.h"
 458 { .vendor_id = 0, /* sentinel */ },
 459 };
 460
 461 static const struct eth_dev_ops i40e_eth_dev_ops = {
 462         .dev_configure                = i40e_dev_configure,
 463         .dev_start                    = i40e_dev_start,
 464         .dev_stop                     = i40e_dev_stop,
 465         .dev_close                    = i40e_dev_close,
 466         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 467         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 468         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 469         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 470         .dev_set_link_up              = i40e_dev_set_link_up,
 471         .dev_set_link_down            = i40e_dev_set_link_down,
 472         .link_update                  = i40e_dev_link_update,
 473         .stats_get                    = i40e_dev_stats_get,
 474         .xstats_get                   = i40e_dev_xstats_get,
 475         .xstats_get_names             = i40e_dev_xstats_get_names,
 476         .stats_reset                  = i40e_dev_stats_reset,
 477         .xstats_reset                 = i40e_dev_stats_reset,
 478         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 479         .dev_infos_get                = i40e_dev_info_get,
 480         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 481         .vlan_filter_set              = i40e_vlan_filter_set,
 482         .vlan_tpid_set                = i40e_vlan_tpid_set,
 483         .vlan_offload_set             = i40e_vlan_offload_set,
 484         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 485         .vlan_pvid_set                = i40e_vlan_pvid_set,
 486         .rx_queue_start               = i40e_dev_rx_queue_start,
 487         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 488         .tx_queue_start               = i40e_dev_tx_queue_start,
 489         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 490         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 491         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 492         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 493         .rx_queue_release             = i40e_dev_rx_queue_release,
 494         .rx_queue_count               = i40e_dev_rx_queue_count,
 495         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 496         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 497         .tx_queue_release             = i40e_dev_tx_queue_release,
 498         .dev_led_on                   = i40e_dev_led_on,
 499         .dev_led_off                  = i40e_dev_led_off,
 500         .flow_ctrl_get                = i40e_flow_ctrl_get,
 501         .flow_ctrl_set                = i40e_flow_ctrl_set,
 502         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 503         .mac_addr_add                 = i40e_macaddr_add,
 504         .mac_addr_remove              = i40e_macaddr_remove,
 505         .reta_update                  = i40e_dev_rss_reta_update,
 506         .reta_query                   = i40e_dev_rss_reta_query,
 507         .rss_hash_update              = i40e_dev_rss_hash_update,
 508         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 509         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 510         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 511         .filter_ctrl                  = i40e_dev_filter_ctrl,
 512         .rxq_info_get                 = i40e_rxq_info_get,
 513         .txq_info_get                 = i40e_txq_info_get,
 514         .mirror_rule_set              = i40e_mirror_rule_set,
 515         .mirror_rule_reset            = i40e_mirror_rule_reset,
 516         .timesync_enable              = i40e_timesync_enable,
 517         .timesync_disable             = i40e_timesync_disable,
 518         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 519         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 520         .get_dcb_info                 = i40e_dev_get_dcb_info,
 521         .timesync_adjust_time         = i40e_timesync_adjust_time,
 522         .timesync_read_time           = i40e_timesync_read_time,
 523         .timesync_write_time          = i40e_timesync_write_time,
 524         .get_reg_length               = i40e_get_reg_length,
 525         .get_reg                      = i40e_get_regs,
 526         .get_eeprom_length            = i40e_get_eeprom_length,
 527         .get_eeprom                   = i40e_get_eeprom,
 528         .mac_addr_set                 = i40e_set_default_mac_addr,
 529         .mtu_set                      = i40e_dev_mtu_set,
 530 };
 531
 532 /* store statistics names and its offset in stats structure */
 533 struct rte_i40e_xstats_name_off {
 534         char name[RTE_ETH_XSTATS_NAME_SIZE];
 535         unsigned offset;
 536 };
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 539         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 540         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 541         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 542         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 543         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 544                 rx_unknown_protocol)},
 545         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 546         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 547         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 548         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 549 };
 550
 551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 552                 sizeof(rte_i40e_stats_strings[0]))
 553
 554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 555         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 556                 tx_dropped_link_down)},
 557         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 558         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 559                 illegal_bytes)},
 560         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 561         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_local_faults)},
 563         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 564                 mac_remote_faults)},
 565         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 566                 rx_length_errors)},
 567         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 568         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 569         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 570         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 571         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 572         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_127)},
 574         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_255)},
 576         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_511)},
 578         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1023)},
 580         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_1522)},
 582         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 583                 rx_size_big)},
 584         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_undersize)},
 586         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 587                 rx_oversize)},
 588         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 589                 mac_short_packet_dropped)},
 590         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 591                 rx_fragments)},
 592         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 593         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 594         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_127)},
 596         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_255)},
 598         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_511)},
 600         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1023)},
 602         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_1522)},
 604         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 605                 tx_size_big)},
 606         {"rx_flow_director_atr_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 608         {"rx_flow_director_sb_match_packets",
 609                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 610         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 tx_lpi_status)},
 612         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 613                 rx_lpi_status)},
 614         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 tx_lpi_count)},
 616         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 617                 rx_lpi_count)},
 618 };
 619
 620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 621                 sizeof(rte_i40e_hw_port_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_rx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_rx)},
 628 };
 629
 630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 631                 sizeof(rte_i40e_rxq_prio_strings[0]))
 632
 633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 634         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xon_tx)},
 636         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xoff_tx)},
 638         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 639                 priority_xon_2_xoff)},
 640 };
 641
 642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 643                 sizeof(rte_i40e_txq_prio_strings[0]))
 644
 645 static struct eth_driver rte_i40e_pmd = {
 646         .pci_drv = {
 647                 .name = "rte_i40e_pmd",
 648                 .id_table = pci_id_i40e_map,
 649                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 650                         RTE_PCI_DRV_DETACHABLE,
 651         },
 652         .eth_dev_init = eth_i40e_dev_init,
 653         .eth_dev_uninit = eth_i40e_dev_uninit,
 654         .dev_private_size = sizeof(struct i40e_adapter),
 655 };
 656
 657 static inline int
 658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 659                                      struct rte_eth_link *link)
 660 {
 661         struct rte_eth_link *dst = link;
 662         struct rte_eth_link *src = &(dev->data->dev_link);
 663
 664         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 665                                         *(uint64_t *)src) == 0)
 666                 return -1;
 667
 668         return 0;
 669 }
 670
 671 static inline int
 672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                       struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * Driver initialization routine.
 687  * Invoked once at EAL init time.
 688  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 689  */
 690 static int
 691 rte_i40e_pmd_init(const char *name __rte_unused,
 692                   const char *params __rte_unused)
 693 {
 694         PMD_INIT_FUNC_TRACE();
 695         rte_eth_driver_register(&rte_i40e_pmd);
 696
 697         return 0;
 698 }
 699
 700 static struct rte_driver rte_i40e_driver = {
 701         .type = PMD_PDEV,
 702         .init = rte_i40e_pmd_init,
 703 };
 704
 705 PMD_REGISTER_DRIVER(rte_i40e_driver);
 706
 707 /*
 708  * Initialize registers for flexible payload, which should be set by NVM.
 709  * This should be removed from code once it is fixed in NVM.
 710  */
 711 #ifndef I40E_GLQF_ORT
 712 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 713 #endif
 714 #ifndef I40E_GLQF_PIT
 715 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 716 #endif
 717
 718 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 719 {
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 730
 731         /* GLQF_PIT Registers */
 732         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 734 }
 735
 736 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 737
 738 /*
 739  * Add a ethertype filter to drop all flow control frames transmitted
 740  * from VSIs.
 741 */
 742 static void
 743 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 744 {
 745         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 746         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 747                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 749         int ret;
 750
 751         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 752                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 753                                 pf->main_vsi_seid, 0,
 754                                 TRUE, NULL, NULL);
 755         if (ret)
 756                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 757                                   " frames from VSIs.");
 758 }
 759
 760 static int
 761 eth_i40e_dev_init(struct rte_eth_dev *dev)
 762 {
 763         struct rte_pci_device *pci_dev;
 764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 766         struct i40e_vsi *vsi;
 767         int ret;
 768         uint32_t len;
 769         uint8_t aq_fail = 0;
 770
 771         PMD_INIT_FUNC_TRACE();
 772
 773         dev->dev_ops = &i40e_eth_dev_ops;
 774         dev->rx_pkt_burst = i40e_recv_pkts;
 775         dev->tx_pkt_burst = i40e_xmit_pkts;
 776
 777         /* for secondary processes, we don't initialise any further as primary
 778          * has already done this work. Only check we don't need a different
 779          * RX function */
 780         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 781                 i40e_set_rx_function(dev);
 782                 i40e_set_tx_function(dev);
 783                 return 0;
 784         }
 785         pci_dev = dev->pci_dev;
 786
 787         rte_eth_copy_pci_info(dev, pci_dev);
 788
 789         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 790         pf->adapter->eth_dev = dev;
 791         pf->dev_data = dev->data;
 792
 793         hw->back = I40E_PF_TO_ADAPTER(pf);
 794         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 795         if (!hw->hw_addr) {
 796                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 797                              "as address is NULL");
 798                 return -ENODEV;
 799         }
 800
 801         hw->vendor_id = pci_dev->id.vendor_id;
 802         hw->device_id = pci_dev->id.device_id;
 803         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 804         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 805         hw->bus.device = pci_dev->addr.devid;
 806         hw->bus.func = pci_dev->addr.function;
 807         hw->adapter_stopped = 0;
 808
 809         /* Make sure all is clean before doing PF reset */
 810         i40e_clear_hw(hw);
 811
 812         /* Initialize the hardware */
 813         i40e_hw_init(dev);
 814
 815         /* Reset here to make sure all is clean for each PF */
 816         ret = i40e_pf_reset(hw);
 817         if (ret) {
 818                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 819                 return ret;
 820         }
 821
 822         /* Initialize the shared code (base driver) */
 823         ret = i40e_init_shared_code(hw);
 824         if (ret) {
 825                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 826                 return ret;
 827         }
 828
 829         /*
 830          * To work around the NVM issue,initialize registers
 831          * for flexible payload by software.
 832          * It should be removed once issues are fixed in NVM.
 833          */
 834         i40e_flex_payload_reg_init(hw);
 835
 836         /* Initialize the input set for filters (hash and fd) to default value */
 837         i40e_filter_input_set_init(pf);
 838
 839         /* Initialize the parameters for adminq */
 840         i40e_init_adminq_parameter(hw);
 841         ret = i40e_init_adminq(hw);
 842         if (ret != I40E_SUCCESS) {
 843                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 844                 return -EIO;
 845         }
 846         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 847                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 848                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 849                      ((hw->nvm.version >> 12) & 0xf),
 850                      ((hw->nvm.version >> 4) & 0xff),
 851                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 852
 853         /* Clear PXE mode */
 854         i40e_clear_pxe_mode(hw);
 855
 856         /*
 857          * On X710, performance number is far from the expectation on recent
 858          * firmware versions. The fix for this issue may not be integrated in
 859          * the following firmware version. So the workaround in software driver
 860          * is needed. It needs to modify the initial values of 3 internal only
 861          * registers. Note that the workaround can be removed when it is fixed
 862          * in firmware in the future.
 863          */
 864         i40e_configure_registers(hw);
 865
 866         /* Get hw capabilities */
 867         ret = i40e_get_cap(hw);
 868         if (ret != I40E_SUCCESS) {
 869                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 870                 goto err_get_capabilities;
 871         }
 872
 873         /* Initialize parameters for PF */
 874         ret = i40e_pf_parameter_init(dev);
 875         if (ret != 0) {
 876                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 877                 goto err_parameter_init;
 878         }
 879
 880         /* Initialize the queue management */
 881         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 882         if (ret < 0) {
 883                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 884                 goto err_qp_pool_init;
 885         }
 886         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 887                                 hw->func_caps.num_msix_vectors - 1);
 888         if (ret < 0) {
 889                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 890                 goto err_msix_pool_init;
 891         }
 892
 893         /* Initialize lan hmc */
 894         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 895                                 hw->func_caps.num_rx_qp, 0, 0);
 896         if (ret != I40E_SUCCESS) {
 897                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 898                 goto err_init_lan_hmc;
 899         }
 900
 901         /* Configure lan hmc */
 902         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 903         if (ret != I40E_SUCCESS) {
 904                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 905                 goto err_configure_lan_hmc;
 906         }
 907
 908         /* Get and check the mac address */
 909         i40e_get_mac_addr(hw, hw->mac.addr);
 910         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 911                 PMD_INIT_LOG(ERR, "mac address is not valid");
 912                 ret = -EIO;
 913                 goto err_get_mac_addr;
 914         }
 915         /* Copy the permanent MAC address */
 916         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 917                         (struct ether_addr *) hw->mac.perm_addr);
 918
 919         /* Disable flow control */
 920         hw->fc.requested_mode = I40E_FC_NONE;
 921         i40e_set_fc(hw, &aq_fail, TRUE);
 922
 923         /* Set the global registers with default ether type value */
 924         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 925         if (ret != I40E_SUCCESS) {
 926                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 927                              "VLAN ether type");
 928                 goto err_setup_pf_switch;
 929         }
 930
 931         /* PF setup, which includes VSI setup */
 932         ret = i40e_pf_setup(pf);
 933         if (ret) {
 934                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 935                 goto err_setup_pf_switch;
 936         }
 937
 938         /* reset all stats of the device, including pf and main vsi */
 939         i40e_dev_stats_reset(dev);
 940
 941         vsi = pf->main_vsi;
 942
 943         /* Disable double vlan by default */
 944         i40e_vsi_config_double_vlan(vsi, FALSE);
 945
 946         if (!vsi->max_macaddrs)
 947                 len = ETHER_ADDR_LEN;
 948         else
 949                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 950
 951         /* Should be after VSI initialized */
 952         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 953         if (!dev->data->mac_addrs) {
 954                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 955                                         "for storing mac address");
 956                 goto err_mac_alloc;
 957         }
 958         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 959                                         &dev->data->mac_addrs[0]);
 960
 961         /* initialize pf host driver to setup SRIOV resource if applicable */
 962         i40e_pf_host_init(dev);
 963
 964         /* register callback func to eal lib */
 965         rte_intr_callback_register(&(pci_dev->intr_handle),
 966                 i40e_dev_interrupt_handler, (void *)dev);
 967
 968         /* configure and enable device interrupt */
 969         i40e_pf_config_irq0(hw, TRUE);
 970         i40e_pf_enable_irq0(hw);
 971
 972         /* enable uio intr after callback register */
 973         rte_intr_enable(&(pci_dev->intr_handle));
 974         /*
 975          * Add an ethertype filter to drop all flow control frames transmitted
 976          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 977          * frames to wire.
 978          */
 979         i40e_add_tx_flow_control_drop_filter(pf);
 980
 981         /* Set the max frame size to 0x2600 by default,
 982          * in case other drivers changed the default value.
 983          */
 984         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 985
 986         /* initialize mirror rule list */
 987         TAILQ_INIT(&pf->mirror_list);
 988
 989         /* Init dcb to sw mode by default */
 990         ret = i40e_dcb_init_configure(dev, TRUE);
 991         if (ret != I40E_SUCCESS) {
 992                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 993                 pf->flags &= ~I40E_FLAG_DCB;
 994         }
 995
 996         return 0;
 997
 998 err_mac_alloc:
 999         i40e_vsi_release(pf->main_vsi);
1000 err_setup_pf_switch:
1001 err_get_mac_addr:
1002 err_configure_lan_hmc:
1003         (void)i40e_shutdown_lan_hmc(hw);
1004 err_init_lan_hmc:
1005         i40e_res_pool_destroy(&pf->msix_pool);
1006 err_msix_pool_init:
1007         i40e_res_pool_destroy(&pf->qp_pool);
1008 err_qp_pool_init:
1009 err_parameter_init:
1010 err_get_capabilities:
1011         (void)i40e_shutdown_adminq(hw);
1012
1013         return ret;
1014 }
1015
1016 static int
1017 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1018 {
1019         struct rte_pci_device *pci_dev;
1020         struct i40e_hw *hw;
1021         struct i40e_filter_control_settings settings;
1022         int ret;
1023         uint8_t aq_fail = 0;
1024
1025         PMD_INIT_FUNC_TRACE();
1026
1027         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1028                 return 0;
1029
1030         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1031         pci_dev = dev->pci_dev;
1032
1033         if (hw->adapter_stopped == 0)
1034                 i40e_dev_close(dev);
1035
1036         dev->dev_ops = NULL;
1037         dev->rx_pkt_burst = NULL;
1038         dev->tx_pkt_burst = NULL;
1039
1040         /* Disable LLDP */
1041         ret = i40e_aq_stop_lldp(hw, true, NULL);
1042         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1043                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1044
1045         /* Clear PXE mode */
1046         i40e_clear_pxe_mode(hw);
1047
1048         /* Unconfigure filter control */
1049         memset(&settings, 0, sizeof(settings));
1050         ret = i40e_set_filter_control(hw, &settings);
1051         if (ret)
1052                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1053                                         ret);
1054
1055         /* Disable flow control */
1056         hw->fc.requested_mode = I40E_FC_NONE;
1057         i40e_set_fc(hw, &aq_fail, TRUE);
1058
1059         /* uninitialize pf host driver */
1060         i40e_pf_host_uninit(dev);
1061
1062         rte_free(dev->data->mac_addrs);
1063         dev->data->mac_addrs = NULL;
1064
1065         /* disable uio intr before callback unregister */
1066         rte_intr_disable(&(pci_dev->intr_handle));
1067
1068         /* register callback func to eal lib */
1069         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1070                 i40e_dev_interrupt_handler, (void *)dev);
1071
1072         return 0;
1073 }
1074
1075 static int
1076 i40e_dev_configure(struct rte_eth_dev *dev)
1077 {
1078         struct i40e_adapter *ad =
1079                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1081         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1082         int i, ret;
1083
1084         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1085          * bulk allocation or vector Rx preconditions we will reset it.
1086          */
1087         ad->rx_bulk_alloc_allowed = true;
1088         ad->rx_vec_allowed = true;
1089         ad->tx_simple_allowed = true;
1090         ad->tx_vec_allowed = true;
1091
1092         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1093                 ret = i40e_fdir_setup(pf);
1094                 if (ret != I40E_SUCCESS) {
1095                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1096                         return -ENOTSUP;
1097                 }
1098                 ret = i40e_fdir_configure(dev);
1099                 if (ret < 0) {
1100                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1101                         goto err;
1102                 }
1103         } else
1104                 i40e_fdir_teardown(pf);
1105
1106         ret = i40e_dev_init_vlan(dev);
1107         if (ret < 0)
1108                 goto err;
1109
1110         /* VMDQ setup.
1111          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1112          *  RSS setting have different requirements.
1113          *  General PMD driver call sequence are NIC init, configure,
1114          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1115          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1116          *  applicable. So, VMDQ setting has to be done before
1117          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1118          *  For RSS setting, it will try to calculate actual configured RX queue
1119          *  number, which will be available after rx_queue_setup(). dev_start()
1120          *  function is good to place RSS setup.
1121          */
1122         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1123                 ret = i40e_vmdq_setup(dev);
1124                 if (ret)
1125                         goto err;
1126         }
1127
1128         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1129                 ret = i40e_dcb_setup(dev);
1130                 if (ret) {
1131                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1132                         goto err_dcb;
1133                 }
1134         }
1135
1136         return 0;
1137
1138 err_dcb:
1139         /* need to release vmdq resource if exists */
1140         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1141                 i40e_vsi_release(pf->vmdq[i].vsi);
1142                 pf->vmdq[i].vsi = NULL;
1143         }
1144         rte_free(pf->vmdq);
1145         pf->vmdq = NULL;
1146 err:
1147         /* need to release fdir resource if exists */
1148         i40e_fdir_teardown(pf);
1149         return ret;
1150 }
1151
1152 void
1153 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1154 {
1155         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1156         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1157         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1158         uint16_t msix_vect = vsi->msix_intr;
1159         uint16_t i;
1160
1161         for (i = 0; i < vsi->nb_qps; i++) {
1162                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1163                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1164                 rte_wmb();
1165         }
1166
1167         if (vsi->type != I40E_VSI_SRIOV) {
1168                 if (!rte_intr_allow_others(intr_handle)) {
1169                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1170                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1171                         I40E_WRITE_REG(hw,
1172                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1173                                        0);
1174                 } else {
1175                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1176                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1177                         I40E_WRITE_REG(hw,
1178                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1179                                                        msix_vect - 1), 0);
1180                 }
1181         } else {
1182                 uint32_t reg;
1183                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1184                         vsi->user_param + (msix_vect - 1);
1185
1186                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1187                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1188         }
1189         I40E_WRITE_FLUSH(hw);
1190 }
1191
1192 static void
1193 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1194                        int base_queue, int nb_queue)
1195 {
1196         int i;
1197         uint32_t val;
1198         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1199
1200         /* Bind all RX queues to allocated MSIX interrupt */
1201         for (i = 0; i < nb_queue; i++) {
1202                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1203                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1204                         ((base_queue + i + 1) <<
1205                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1206                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1207                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1208
1209                 if (i == nb_queue - 1)
1210                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1211                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1212         }
1213
1214         /* Write first RX queue to Link list register as the head element */
1215         if (vsi->type != I40E_VSI_SRIOV) {
1216                 uint16_t interval =
1217                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1218
1219                 if (msix_vect == I40E_MISC_VEC_ID) {
1220                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1221                                        (base_queue <<
1222                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1223                                        (0x0 <<
1224                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1225                         I40E_WRITE_REG(hw,
1226                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1227                                        interval);
1228                 } else {
1229                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1230                                        (base_queue <<
1231                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1232                                        (0x0 <<
1233                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1234                         I40E_WRITE_REG(hw,
1235                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1236                                                        msix_vect - 1),
1237                                        interval);
1238                 }
1239         } else {
1240                 uint32_t reg;
1241
1242                 if (msix_vect == I40E_MISC_VEC_ID) {
1243                         I40E_WRITE_REG(hw,
1244                                        I40E_VPINT_LNKLST0(vsi->user_param),
1245                                        (base_queue <<
1246                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1247                                        (0x0 <<
1248                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1249                 } else {
1250                         /* num_msix_vectors_vf needs to minus irq0 */
1251                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1252                                 vsi->user_param + (msix_vect - 1);
1253
1254                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1255                                        (base_queue <<
1256                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1257                                        (0x0 <<
1258                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1259                 }
1260         }
1261
1262         I40E_WRITE_FLUSH(hw);
1263 }
1264
1265 void
1266 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1267 {
1268         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1269         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1270         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1271         uint16_t msix_vect = vsi->msix_intr;
1272         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1273         uint16_t queue_idx = 0;
1274         int record = 0;
1275         uint32_t val;
1276         int i;
1277
1278         for (i = 0; i < vsi->nb_qps; i++) {
1279                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1280                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1281         }
1282
1283         /* INTENA flag is not auto-cleared for interrupt */
1284         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1285         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1286                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1287                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1288         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1289
1290         /* VF bind interrupt */
1291         if (vsi->type == I40E_VSI_SRIOV) {
1292                 __vsi_queues_bind_intr(vsi, msix_vect,
1293                                        vsi->base_queue, vsi->nb_qps);
1294                 return;
1295         }
1296
1297         /* PF & VMDq bind interrupt */
1298         if (rte_intr_dp_is_en(intr_handle)) {
1299                 if (vsi->type == I40E_VSI_MAIN) {
1300                         queue_idx = 0;
1301                         record = 1;
1302                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1303                         struct i40e_vsi *main_vsi =
1304                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1305                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1306                         record = 1;
1307                 }
1308         }
1309
1310         for (i = 0; i < vsi->nb_used_qps; i++) {
1311                 if (nb_msix <= 1) {
1312                         if (!rte_intr_allow_others(intr_handle))
1313                                 /* allow to share MISC_VEC_ID */
1314                                 msix_vect = I40E_MISC_VEC_ID;
1315
1316                         /* no enough msix_vect, map all to one */
1317                         __vsi_queues_bind_intr(vsi, msix_vect,
1318                                                vsi->base_queue + i,
1319                                                vsi->nb_used_qps - i);
1320                         for (; !!record && i < vsi->nb_used_qps; i++)
1321                                 intr_handle->intr_vec[queue_idx + i] =
1322                                         msix_vect;
1323                         break;
1324                 }
1325                 /* 1:1 queue/msix_vect mapping */
1326                 __vsi_queues_bind_intr(vsi, msix_vect,
1327                                        vsi->base_queue + i, 1);
1328                 if (!!record)
1329                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1330
1331                 msix_vect++;
1332                 nb_msix--;
1333         }
1334 }
1335
1336 static void
1337 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1338 {
1339         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1340         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1341         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1342         uint16_t interval = i40e_calc_itr_interval(\
1343                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1344         uint16_t msix_intr, i;
1345
1346         if (rte_intr_allow_others(intr_handle))
1347                 for (i = 0; i < vsi->nb_msix; i++) {
1348                         msix_intr = vsi->msix_intr + i;
1349                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1350                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1351                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1352                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1353                                 (interval <<
1354                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1355                 }
1356         else
1357                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1358                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1359                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1360                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1361                                (interval <<
1362                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1363
1364         I40E_WRITE_FLUSH(hw);
1365 }
1366
1367 static void
1368 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1369 {
1370         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1371         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1372         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1373         uint16_t msix_intr, i;
1374
1375         if (rte_intr_allow_others(intr_handle))
1376                 for (i = 0; i < vsi->nb_msix; i++) {
1377                         msix_intr = vsi->msix_intr + i;
1378                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1379                                        0);
1380                 }
1381         else
1382                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1383
1384         I40E_WRITE_FLUSH(hw);
1385 }
1386
1387 static inline uint8_t
1388 i40e_parse_link_speeds(uint16_t link_speeds)
1389 {
1390         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1391
1392         if (link_speeds & ETH_LINK_SPEED_40G)
1393                 link_speed |= I40E_LINK_SPEED_40GB;
1394         if (link_speeds & ETH_LINK_SPEED_20G)
1395                 link_speed |= I40E_LINK_SPEED_20GB;
1396         if (link_speeds & ETH_LINK_SPEED_10G)
1397                 link_speed |= I40E_LINK_SPEED_10GB;
1398         if (link_speeds & ETH_LINK_SPEED_1G)
1399                 link_speed |= I40E_LINK_SPEED_1GB;
1400         if (link_speeds & ETH_LINK_SPEED_100M)
1401                 link_speed |= I40E_LINK_SPEED_100MB;
1402
1403         return link_speed;
1404 }
1405
1406 static int
1407 i40e_phy_conf_link(struct i40e_hw *hw,
1408                    uint8_t abilities,
1409                    uint8_t force_speed)
1410 {
1411         enum i40e_status_code status;
1412         struct i40e_aq_get_phy_abilities_resp phy_ab;
1413         struct i40e_aq_set_phy_config phy_conf;
1414         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1415                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1416                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1417                         I40E_AQ_PHY_FLAG_LOW_POWER;
1418         const uint8_t advt = I40E_LINK_SPEED_40GB |
1419                         I40E_LINK_SPEED_10GB |
1420                         I40E_LINK_SPEED_1GB |
1421                         I40E_LINK_SPEED_100MB;
1422         int ret = -ENOTSUP;
1423
1424
1425         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1426                                               NULL);
1427         if (status)
1428                 return ret;
1429
1430         memset(&phy_conf, 0, sizeof(phy_conf));
1431
1432         /* bits 0-2 use the values from get_phy_abilities_resp */
1433         abilities &= ~mask;
1434         abilities |= phy_ab.abilities & mask;
1435
1436         /* update ablities and speed */
1437         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1438                 phy_conf.link_speed = advt;
1439         else
1440                 phy_conf.link_speed = force_speed;
1441
1442         phy_conf.abilities = abilities;
1443
1444         /* use get_phy_abilities_resp value for the rest */
1445         phy_conf.phy_type = phy_ab.phy_type;
1446         phy_conf.eee_capability = phy_ab.eee_capability;
1447         phy_conf.eeer = phy_ab.eeer_val;
1448         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1449
1450         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1451                     phy_ab.abilities, phy_ab.link_speed);
1452         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1453                     phy_conf.abilities, phy_conf.link_speed);
1454
1455         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1456         if (status)
1457                 return ret;
1458
1459         return I40E_SUCCESS;
1460 }
1461
1462 static int
1463 i40e_apply_link_speed(struct rte_eth_dev *dev)
1464 {
1465         uint8_t speed;
1466         uint8_t abilities = 0;
1467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468         struct rte_eth_conf *conf = &dev->data->dev_conf;
1469
1470         speed = i40e_parse_link_speeds(conf->link_speeds);
1471         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1472         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1473                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1474         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1475
1476         /* Skip changing speed on 40G interfaces, FW does not support */
1477         if (i40e_is_40G_device(hw->device_id)) {
1478                 speed =  I40E_LINK_SPEED_UNKNOWN;
1479                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1480         }
1481
1482         return i40e_phy_conf_link(hw, abilities, speed);
1483 }
1484
1485 static int
1486 i40e_dev_start(struct rte_eth_dev *dev)
1487 {
1488         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490         struct i40e_vsi *main_vsi = pf->main_vsi;
1491         int ret, i;
1492         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1493         uint32_t intr_vector = 0;
1494
1495         hw->adapter_stopped = 0;
1496
1497         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1498                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1499                              dev->data->port_id);
1500                 return -EINVAL;
1501         }
1502
1503         rte_intr_disable(intr_handle);
1504
1505         if ((rte_intr_cap_multiple(intr_handle) ||
1506              !RTE_ETH_DEV_SRIOV(dev).active) &&
1507             dev->data->dev_conf.intr_conf.rxq != 0) {
1508                 intr_vector = dev->data->nb_rx_queues;
1509                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1510                         return -1;
1511         }
1512
1513         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1514                 intr_handle->intr_vec =
1515                         rte_zmalloc("intr_vec",
1516                                     dev->data->nb_rx_queues * sizeof(int),
1517                                     0);
1518                 if (!intr_handle->intr_vec) {
1519                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1520                                      " intr_vec\n", dev->data->nb_rx_queues);
1521                         return -ENOMEM;
1522                 }
1523         }
1524
1525         /* Initialize VSI */
1526         ret = i40e_dev_rxtx_init(pf);
1527         if (ret != I40E_SUCCESS) {
1528                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1529                 goto err_up;
1530         }
1531
1532         /* Map queues with MSIX interrupt */
1533         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1534                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1535         i40e_vsi_queues_bind_intr(main_vsi);
1536         i40e_vsi_enable_queues_intr(main_vsi);
1537
1538         /* Map VMDQ VSI queues with MSIX interrupt */
1539         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1540                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1541                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1542                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1543         }
1544
1545         /* enable FDIR MSIX interrupt */
1546         if (pf->fdir.fdir_vsi) {
1547                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1548                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1549         }
1550
1551         /* Enable all queues which have been configured */
1552         ret = i40e_dev_switch_queues(pf, TRUE);
1553         if (ret != I40E_SUCCESS) {
1554                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1555                 goto err_up;
1556         }
1557
1558         /* Enable receiving broadcast packets */
1559         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1560         if (ret != I40E_SUCCESS)
1561                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1562
1563         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1564                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1565                                                 true, NULL);
1566                 if (ret != I40E_SUCCESS)
1567                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1568         }
1569
1570         /* Apply link configure */
1571         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1572                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1573                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1574                 PMD_DRV_LOG(ERR, "Invalid link setting");
1575                 goto err_up;
1576         }
1577         ret = i40e_apply_link_speed(dev);
1578         if (I40E_SUCCESS != ret) {
1579                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1580                 goto err_up;
1581         }
1582
1583         if (!rte_intr_allow_others(intr_handle)) {
1584                 rte_intr_callback_unregister(intr_handle,
1585                                              i40e_dev_interrupt_handler,
1586                                              (void *)dev);
1587                 /* configure and enable device interrupt */
1588                 i40e_pf_config_irq0(hw, FALSE);
1589                 i40e_pf_enable_irq0(hw);
1590
1591                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1592                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1593                                      " no intr multiplex\n");
1594         }
1595
1596         /* enable uio intr after callback register */
1597         rte_intr_enable(intr_handle);
1598
1599         return I40E_SUCCESS;
1600
1601 err_up:
1602         i40e_dev_switch_queues(pf, FALSE);
1603         i40e_dev_clear_queues(dev);
1604
1605         return ret;
1606 }
1607
1608 static void
1609 i40e_dev_stop(struct rte_eth_dev *dev)
1610 {
1611         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1612         struct i40e_vsi *main_vsi = pf->main_vsi;
1613         struct i40e_mirror_rule *p_mirror;
1614         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1615         int i;
1616
1617         /* Disable all queues */
1618         i40e_dev_switch_queues(pf, FALSE);
1619
1620         /* un-map queues with interrupt registers */
1621         i40e_vsi_disable_queues_intr(main_vsi);
1622         i40e_vsi_queues_unbind_intr(main_vsi);
1623
1624         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1625                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1626                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1627         }
1628
1629         if (pf->fdir.fdir_vsi) {
1630                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1631                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1632         }
1633         /* Clear all queues and release memory */
1634         i40e_dev_clear_queues(dev);
1635
1636         /* Set link down */
1637         i40e_dev_set_link_down(dev);
1638
1639         /* Remove all mirror rules */
1640         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1641                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1642                 rte_free(p_mirror);
1643         }
1644         pf->nb_mirror_rule = 0;
1645
1646         if (!rte_intr_allow_others(intr_handle))
1647                 /* resume to the default handler */
1648                 rte_intr_callback_register(intr_handle,
1649                                            i40e_dev_interrupt_handler,
1650                                            (void *)dev);
1651
1652         /* Clean datapath event and queue/vec mapping */
1653         rte_intr_efd_disable(intr_handle);
1654         if (intr_handle->intr_vec) {
1655                 rte_free(intr_handle->intr_vec);
1656                 intr_handle->intr_vec = NULL;
1657         }
1658 }
1659
1660 static void
1661 i40e_dev_close(struct rte_eth_dev *dev)
1662 {
1663         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1664         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         uint32_t reg;
1666         int i;
1667
1668         PMD_INIT_FUNC_TRACE();
1669
1670         i40e_dev_stop(dev);
1671         hw->adapter_stopped = 1;
1672         i40e_dev_free_queues(dev);
1673
1674         /* Disable interrupt */
1675         i40e_pf_disable_irq0(hw);
1676         rte_intr_disable(&(dev->pci_dev->intr_handle));
1677
1678         /* shutdown and destroy the HMC */
1679         i40e_shutdown_lan_hmc(hw);
1680
1681         /* release all the existing VSIs and VEBs */
1682         i40e_fdir_teardown(pf);
1683         i40e_vsi_release(pf->main_vsi);
1684
1685         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1686                 i40e_vsi_release(pf->vmdq[i].vsi);
1687                 pf->vmdq[i].vsi = NULL;
1688         }
1689
1690         rte_free(pf->vmdq);
1691         pf->vmdq = NULL;
1692
1693         /* shutdown the adminq */
1694         i40e_aq_queue_shutdown(hw, true);
1695         i40e_shutdown_adminq(hw);
1696
1697         i40e_res_pool_destroy(&pf->qp_pool);
1698         i40e_res_pool_destroy(&pf->msix_pool);
1699
1700         /* force a PF reset to clean anything leftover */
1701         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1702         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1703                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1704         I40E_WRITE_FLUSH(hw);
1705 }
1706
1707 static void
1708 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1709 {
1710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         struct i40e_vsi *vsi = pf->main_vsi;
1713         int status;
1714
1715         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1716                                                      true, NULL, true);
1717         if (status != I40E_SUCCESS)
1718                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1719
1720         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1721                                                         TRUE, NULL);
1722         if (status != I40E_SUCCESS)
1723                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1724
1725 }
1726
1727 static void
1728 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1729 {
1730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732         struct i40e_vsi *vsi = pf->main_vsi;
1733         int status;
1734
1735         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1736                                                      false, NULL, true);
1737         if (status != I40E_SUCCESS)
1738                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1739
1740         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1741                                                         false, NULL);
1742         if (status != I40E_SUCCESS)
1743                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1744 }
1745
1746 static void
1747 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1748 {
1749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751         struct i40e_vsi *vsi = pf->main_vsi;
1752         int ret;
1753
1754         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1755         if (ret != I40E_SUCCESS)
1756                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1757 }
1758
1759 static void
1760 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1761 {
1762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764         struct i40e_vsi *vsi = pf->main_vsi;
1765         int ret;
1766
1767         if (dev->data->promiscuous == 1)
1768                 return; /* must remain in all_multicast mode */
1769
1770         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1771                                 vsi->seid, FALSE, NULL);
1772         if (ret != I40E_SUCCESS)
1773                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1774 }
1775
1776 /*
1777  * Set device link up.
1778  */
1779 static int
1780 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1781 {
1782         /* re-apply link speed setting */
1783         return i40e_apply_link_speed(dev);
1784 }
1785
1786 /*
1787  * Set device link down.
1788  */
1789 static int
1790 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1791 {
1792         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1793         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1795
1796         return i40e_phy_conf_link(hw, abilities, speed);
1797 }
1798
1799 int
1800 i40e_dev_link_update(struct rte_eth_dev *dev,
1801                      int wait_to_complete)
1802 {
1803 #define CHECK_INTERVAL 100  /* 100ms */
1804 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806         struct i40e_link_status link_status;
1807         struct rte_eth_link link, old;
1808         int status;
1809         unsigned rep_cnt = MAX_REPEAT_TIME;
1810
1811         memset(&link, 0, sizeof(link));
1812         memset(&old, 0, sizeof(old));
1813         memset(&link_status, 0, sizeof(link_status));
1814         rte_i40e_dev_atomic_read_link_status(dev, &old);
1815
1816         do {
1817                 /* Get link status information from hardware */
1818                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1819                 if (status != I40E_SUCCESS) {
1820                         link.link_speed = ETH_SPEED_NUM_100M;
1821                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1822                         PMD_DRV_LOG(ERR, "Failed to get link info");
1823                         goto out;
1824                 }
1825
1826                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1827                 if (!wait_to_complete)
1828                         break;
1829
1830                 rte_delay_ms(CHECK_INTERVAL);
1831         } while (!link.link_status && rep_cnt--);
1832
1833         if (!link.link_status)
1834                 goto out;
1835
1836         /* i40e uses full duplex only */
1837         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1838
1839         /* Parse the link status */
1840         switch (link_status.link_speed) {
1841         case I40E_LINK_SPEED_100MB:
1842                 link.link_speed = ETH_SPEED_NUM_100M;
1843                 break;
1844         case I40E_LINK_SPEED_1GB:
1845                 link.link_speed = ETH_SPEED_NUM_1G;
1846                 break;
1847         case I40E_LINK_SPEED_10GB:
1848                 link.link_speed = ETH_SPEED_NUM_10G;
1849                 break;
1850         case I40E_LINK_SPEED_20GB:
1851                 link.link_speed = ETH_SPEED_NUM_20G;
1852                 break;
1853         case I40E_LINK_SPEED_40GB:
1854                 link.link_speed = ETH_SPEED_NUM_40G;
1855                 break;
1856         default:
1857                 link.link_speed = ETH_SPEED_NUM_100M;
1858                 break;
1859         }
1860
1861         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1862                         ETH_LINK_SPEED_FIXED);
1863
1864 out:
1865         rte_i40e_dev_atomic_write_link_status(dev, &link);
1866         if (link.link_status == old.link_status)
1867                 return -1;
1868
1869         return 0;
1870 }
1871
1872 /* Get all the statistics of a VSI */
1873 void
1874 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1875 {
1876         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1877         struct i40e_eth_stats *nes = &vsi->eth_stats;
1878         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1879         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1880
1881         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1882                             vsi->offset_loaded, &oes->rx_bytes,
1883                             &nes->rx_bytes);
1884         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1885                             vsi->offset_loaded, &oes->rx_unicast,
1886                             &nes->rx_unicast);
1887         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1888                             vsi->offset_loaded, &oes->rx_multicast,
1889                             &nes->rx_multicast);
1890         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1891                             vsi->offset_loaded, &oes->rx_broadcast,
1892                             &nes->rx_broadcast);
1893         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1894                             &oes->rx_discards, &nes->rx_discards);
1895         /* GLV_REPC not supported */
1896         /* GLV_RMPC not supported */
1897         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1898                             &oes->rx_unknown_protocol,
1899                             &nes->rx_unknown_protocol);
1900         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1901                             vsi->offset_loaded, &oes->tx_bytes,
1902                             &nes->tx_bytes);
1903         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1904                             vsi->offset_loaded, &oes->tx_unicast,
1905                             &nes->tx_unicast);
1906         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1907                             vsi->offset_loaded, &oes->tx_multicast,
1908                             &nes->tx_multicast);
1909         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1910                             vsi->offset_loaded,  &oes->tx_broadcast,
1911                             &nes->tx_broadcast);
1912         /* GLV_TDPC not supported */
1913         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1914                             &oes->tx_errors, &nes->tx_errors);
1915         vsi->offset_loaded = true;
1916
1917         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1918                     vsi->vsi_id);
1919         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1920         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1921         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1922         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1923         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1924         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1925                     nes->rx_unknown_protocol);
1926         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1927         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1928         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1929         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1930         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1931         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1932         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1933                     vsi->vsi_id);
1934 }
1935
1936 static void
1937 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1938 {
1939         unsigned int i;
1940         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1941         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1942
1943         /* Get statistics of struct i40e_eth_stats */
1944         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1945                             I40E_GLPRT_GORCL(hw->port),
1946                             pf->offset_loaded, &os->eth.rx_bytes,
1947                             &ns->eth.rx_bytes);
1948         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1949                             I40E_GLPRT_UPRCL(hw->port),
1950                             pf->offset_loaded, &os->eth.rx_unicast,
1951                             &ns->eth.rx_unicast);
1952         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1953                             I40E_GLPRT_MPRCL(hw->port),
1954                             pf->offset_loaded, &os->eth.rx_multicast,
1955                             &ns->eth.rx_multicast);
1956         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1957                             I40E_GLPRT_BPRCL(hw->port),
1958                             pf->offset_loaded, &os->eth.rx_broadcast,
1959                             &ns->eth.rx_broadcast);
1960         /* Workaround: CRC size should not be included in byte statistics,
1961          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1962          */
1963         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1964                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1965
1966         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1967                             pf->offset_loaded, &os->eth.rx_discards,
1968                             &ns->eth.rx_discards);
1969         /* GLPRT_REPC not supported */
1970         /* GLPRT_RMPC not supported */
1971         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1972                             pf->offset_loaded,
1973                             &os->eth.rx_unknown_protocol,
1974                             &ns->eth.rx_unknown_protocol);
1975         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1976                             I40E_GLPRT_GOTCL(hw->port),
1977                             pf->offset_loaded, &os->eth.tx_bytes,
1978                             &ns->eth.tx_bytes);
1979         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1980                             I40E_GLPRT_UPTCL(hw->port),
1981                             pf->offset_loaded, &os->eth.tx_unicast,
1982                             &ns->eth.tx_unicast);
1983         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1984                             I40E_GLPRT_MPTCL(hw->port),
1985                             pf->offset_loaded, &os->eth.tx_multicast,
1986                             &ns->eth.tx_multicast);
1987         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1988                             I40E_GLPRT_BPTCL(hw->port),
1989                             pf->offset_loaded, &os->eth.tx_broadcast,
1990                             &ns->eth.tx_broadcast);
1991         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1992                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1993         /* GLPRT_TEPC not supported */
1994
1995         /* additional port specific stats */
1996         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1997                             pf->offset_loaded, &os->tx_dropped_link_down,
1998                             &ns->tx_dropped_link_down);
1999         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2000                             pf->offset_loaded, &os->crc_errors,
2001                             &ns->crc_errors);
2002         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2003                             pf->offset_loaded, &os->illegal_bytes,
2004                             &ns->illegal_bytes);
2005         /* GLPRT_ERRBC not supported */
2006         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2007                             pf->offset_loaded, &os->mac_local_faults,
2008                             &ns->mac_local_faults);
2009         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2010                             pf->offset_loaded, &os->mac_remote_faults,
2011                             &ns->mac_remote_faults);
2012         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2013                             pf->offset_loaded, &os->rx_length_errors,
2014                             &ns->rx_length_errors);
2015         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2016                             pf->offset_loaded, &os->link_xon_rx,
2017                             &ns->link_xon_rx);
2018         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2019                             pf->offset_loaded, &os->link_xoff_rx,
2020                             &ns->link_xoff_rx);
2021         for (i = 0; i < 8; i++) {
2022                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2023                                     pf->offset_loaded,
2024                                     &os->priority_xon_rx[i],
2025                                     &ns->priority_xon_rx[i]);
2026                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2027                                     pf->offset_loaded,
2028                                     &os->priority_xoff_rx[i],
2029                                     &ns->priority_xoff_rx[i]);
2030         }
2031         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2032                             pf->offset_loaded, &os->link_xon_tx,
2033                             &ns->link_xon_tx);
2034         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2035                             pf->offset_loaded, &os->link_xoff_tx,
2036                             &ns->link_xoff_tx);
2037         for (i = 0; i < 8; i++) {
2038                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2039                                     pf->offset_loaded,
2040                                     &os->priority_xon_tx[i],
2041                                     &ns->priority_xon_tx[i]);
2042                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2043                                     pf->offset_loaded,
2044                                     &os->priority_xoff_tx[i],
2045                                     &ns->priority_xoff_tx[i]);
2046                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2047                                     pf->offset_loaded,
2048                                     &os->priority_xon_2_xoff[i],
2049                                     &ns->priority_xon_2_xoff[i]);
2050         }
2051         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2052                             I40E_GLPRT_PRC64L(hw->port),
2053                             pf->offset_loaded, &os->rx_size_64,
2054                             &ns->rx_size_64);
2055         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2056                             I40E_GLPRT_PRC127L(hw->port),
2057                             pf->offset_loaded, &os->rx_size_127,
2058                             &ns->rx_size_127);
2059         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2060                             I40E_GLPRT_PRC255L(hw->port),
2061                             pf->offset_loaded, &os->rx_size_255,
2062                             &ns->rx_size_255);
2063         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2064                             I40E_GLPRT_PRC511L(hw->port),
2065                             pf->offset_loaded, &os->rx_size_511,
2066                             &ns->rx_size_511);
2067         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2068                             I40E_GLPRT_PRC1023L(hw->port),
2069                             pf->offset_loaded, &os->rx_size_1023,
2070                             &ns->rx_size_1023);
2071         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2072                             I40E_GLPRT_PRC1522L(hw->port),
2073                             pf->offset_loaded, &os->rx_size_1522,
2074                             &ns->rx_size_1522);
2075         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2076                             I40E_GLPRT_PRC9522L(hw->port),
2077                             pf->offset_loaded, &os->rx_size_big,
2078                             &ns->rx_size_big);
2079         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2080                             pf->offset_loaded, &os->rx_undersize,
2081                             &ns->rx_undersize);
2082         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2083                             pf->offset_loaded, &os->rx_fragments,
2084                             &ns->rx_fragments);
2085         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2086                             pf->offset_loaded, &os->rx_oversize,
2087                             &ns->rx_oversize);
2088         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2089                             pf->offset_loaded, &os->rx_jabber,
2090                             &ns->rx_jabber);
2091         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2092                             I40E_GLPRT_PTC64L(hw->port),
2093                             pf->offset_loaded, &os->tx_size_64,
2094                             &ns->tx_size_64);
2095         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2096                             I40E_GLPRT_PTC127L(hw->port),
2097                             pf->offset_loaded, &os->tx_size_127,
2098                             &ns->tx_size_127);
2099         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2100                             I40E_GLPRT_PTC255L(hw->port),
2101                             pf->offset_loaded, &os->tx_size_255,
2102                             &ns->tx_size_255);
2103         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2104                             I40E_GLPRT_PTC511L(hw->port),
2105                             pf->offset_loaded, &os->tx_size_511,
2106                             &ns->tx_size_511);
2107         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2108                             I40E_GLPRT_PTC1023L(hw->port),
2109                             pf->offset_loaded, &os->tx_size_1023,
2110                             &ns->tx_size_1023);
2111         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2112                             I40E_GLPRT_PTC1522L(hw->port),
2113                             pf->offset_loaded, &os->tx_size_1522,
2114                             &ns->tx_size_1522);
2115         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2116                             I40E_GLPRT_PTC9522L(hw->port),
2117                             pf->offset_loaded, &os->tx_size_big,
2118                             &ns->tx_size_big);
2119         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2120                            pf->offset_loaded,
2121                            &os->fd_sb_match, &ns->fd_sb_match);
2122         /* GLPRT_MSPDC not supported */
2123         /* GLPRT_XEC not supported */
2124
2125         pf->offset_loaded = true;
2126
2127         if (pf->main_vsi)
2128                 i40e_update_vsi_stats(pf->main_vsi);
2129 }
2130
2131 /* Get all statistics of a port */
2132 static void
2133 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2134 {
2135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2136         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2137         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2138         unsigned i;
2139
2140         /* call read registers - updates values, now write them to struct */
2141         i40e_read_stats_registers(pf, hw);
2142
2143         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2144                         pf->main_vsi->eth_stats.rx_multicast +
2145                         pf->main_vsi->eth_stats.rx_broadcast -
2146                         pf->main_vsi->eth_stats.rx_discards;
2147         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2148                         pf->main_vsi->eth_stats.tx_multicast +
2149                         pf->main_vsi->eth_stats.tx_broadcast;
2150         stats->ibytes   = ns->eth.rx_bytes;
2151         stats->obytes   = ns->eth.tx_bytes;
2152         stats->oerrors  = ns->eth.tx_errors +
2153                         pf->main_vsi->eth_stats.tx_errors;
2154
2155         /* Rx Errors */
2156         stats->imissed  = ns->eth.rx_discards +
2157                         pf->main_vsi->eth_stats.rx_discards;
2158         stats->ierrors  = ns->crc_errors +
2159                         ns->rx_length_errors + ns->rx_undersize +
2160                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2161
2162         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2163         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2164         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2165         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2166         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2167         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2168         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2169                     ns->eth.rx_unknown_protocol);
2170         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2171         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2172         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2173         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2174         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2175         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2176
2177         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2178                     ns->tx_dropped_link_down);
2179         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2180         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2181                     ns->illegal_bytes);
2182         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2183         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2184                     ns->mac_local_faults);
2185         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2186                     ns->mac_remote_faults);
2187         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2188                     ns->rx_length_errors);
2189         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2190         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2191         for (i = 0; i < 8; i++) {
2192                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2193                                 i, ns->priority_xon_rx[i]);
2194                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2195                                 i, ns->priority_xoff_rx[i]);
2196         }
2197         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2198         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2199         for (i = 0; i < 8; i++) {
2200                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2201                                 i, ns->priority_xon_tx[i]);
2202                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2203                                 i, ns->priority_xoff_tx[i]);
2204                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2205                                 i, ns->priority_xon_2_xoff[i]);
2206         }
2207         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2208         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2209         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2210         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2211         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2212         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2213         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2214         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2215         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2216         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2217         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2218         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2219         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2220         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2221         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2222         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2223         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2224         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2225         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2226                         ns->mac_short_packet_dropped);
2227         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2228                     ns->checksum_error);
2229         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2230         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2231 }
2232
2233 /* Reset the statistics */
2234 static void
2235 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2236 {
2237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239
2240         /* Mark PF and VSI stats to update the offset, aka "reset" */
2241         pf->offset_loaded = false;
2242         if (pf->main_vsi)
2243                 pf->main_vsi->offset_loaded = false;
2244
2245         /* read the stats, reading current register values into offset */
2246         i40e_read_stats_registers(pf, hw);
2247 }
2248
2249 static uint32_t
2250 i40e_xstats_calc_num(void)
2251 {
2252         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2253                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2254                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2255 }
2256
2257 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2258                                      struct rte_eth_xstat_name *xstats_names,
2259                                      __rte_unused unsigned limit)
2260 {
2261         unsigned count = 0;
2262         unsigned i, prio;
2263
2264         if (xstats_names == NULL)
2265                 return i40e_xstats_calc_num();
2266
2267         /* Note: limit checked in rte_eth_xstats_names() */
2268
2269         /* Get stats from i40e_eth_stats struct */
2270         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2271                 snprintf(xstats_names[count].name,
2272                          sizeof(xstats_names[count].name),
2273                          "%s", rte_i40e_stats_strings[i].name);
2274                 xstats_names[count].id = count;
2275                 count++;
2276         }
2277
2278         /* Get individiual stats from i40e_hw_port struct */
2279         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2280                 snprintf(xstats_names[count].name,
2281                         sizeof(xstats_names[count].name),
2282                          "%s", rte_i40e_hw_port_strings[i].name);
2283                 xstats_names[count].id = count;
2284                 count++;
2285         }
2286
2287         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2288                 for (prio = 0; prio < 8; prio++) {
2289                         snprintf(xstats_names[count].name,
2290                                  sizeof(xstats_names[count].name),
2291                                  "rx_priority%u_%s", prio,
2292                                  rte_i40e_rxq_prio_strings[i].name);
2293                         xstats_names[count].id = count;
2294                         count++;
2295                 }
2296         }
2297
2298         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2299                 for (prio = 0; prio < 8; prio++) {
2300                         snprintf(xstats_names[count].name,
2301                                  sizeof(xstats_names[count].name),
2302                                  "tx_priority%u_%s", prio,
2303                                  rte_i40e_txq_prio_strings[i].name);
2304                         xstats_names[count].id = count;
2305                         count++;
2306                 }
2307         }
2308         return count;
2309 }
2310
2311 static int
2312 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2313                     unsigned n)
2314 {
2315         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317         unsigned i, count, prio;
2318         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2319
2320         count = i40e_xstats_calc_num();
2321         if (n < count)
2322                 return count;
2323
2324         i40e_read_stats_registers(pf, hw);
2325
2326         if (xstats == NULL)
2327                 return 0;
2328
2329         count = 0;
2330
2331         /* Get stats from i40e_eth_stats struct */
2332         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2333                 xstats[count].id = count;
2334                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2335                         rte_i40e_stats_strings[i].offset);
2336                 count++;
2337         }
2338
2339         /* Get individiual stats from i40e_hw_port struct */
2340         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2341                 xstats[count].id = count;
2342                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2343                         rte_i40e_hw_port_strings[i].offset);
2344                 count++;
2345         }
2346
2347         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2348                 for (prio = 0; prio < 8; prio++) {
2349                         xstats[count].id = count;
2350                         xstats[count].value =
2351                                 *(uint64_t *)(((char *)hw_stats) +
2352                                 rte_i40e_rxq_prio_strings[i].offset +
2353                                 (sizeof(uint64_t) * prio));
2354                         count++;
2355                 }
2356         }
2357
2358         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2359                 for (prio = 0; prio < 8; prio++) {
2360                         xstats[count].id = count;
2361                         xstats[count].value =
2362                                 *(uint64_t *)(((char *)hw_stats) +
2363                                 rte_i40e_txq_prio_strings[i].offset +
2364                                 (sizeof(uint64_t) * prio));
2365                         count++;
2366                 }
2367         }
2368
2369         return count;
2370 }
2371
2372 static int
2373 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2374                                  __rte_unused uint16_t queue_id,
2375                                  __rte_unused uint8_t stat_idx,
2376                                  __rte_unused uint8_t is_rx)
2377 {
2378         PMD_INIT_FUNC_TRACE();
2379
2380         return -ENOSYS;
2381 }
2382
2383 static void
2384 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2385 {
2386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct i40e_vsi *vsi = pf->main_vsi;
2389
2390         dev_info->max_rx_queues = vsi->nb_qps;
2391         dev_info->max_tx_queues = vsi->nb_qps;
2392         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2393         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2394         dev_info->max_mac_addrs = vsi->max_macaddrs;
2395         dev_info->max_vfs = dev->pci_dev->max_vfs;
2396         dev_info->rx_offload_capa =
2397                 DEV_RX_OFFLOAD_VLAN_STRIP |
2398                 DEV_RX_OFFLOAD_QINQ_STRIP |
2399                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2400                 DEV_RX_OFFLOAD_UDP_CKSUM |
2401                 DEV_RX_OFFLOAD_TCP_CKSUM;
2402         dev_info->tx_offload_capa =
2403                 DEV_TX_OFFLOAD_VLAN_INSERT |
2404                 DEV_TX_OFFLOAD_QINQ_INSERT |
2405                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2406                 DEV_TX_OFFLOAD_UDP_CKSUM |
2407                 DEV_TX_OFFLOAD_TCP_CKSUM |
2408                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2409                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2410                 DEV_TX_OFFLOAD_TCP_TSO;
2411         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2412                                                 sizeof(uint32_t);
2413         dev_info->reta_size = pf->hash_lut_size;
2414         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2415
2416         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2417                 .rx_thresh = {
2418                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2419                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2420                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2421                 },
2422                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2423                 .rx_drop_en = 0,
2424         };
2425
2426         dev_info->default_txconf = (struct rte_eth_txconf) {
2427                 .tx_thresh = {
2428                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2429                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2430                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2431                 },
2432                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2433                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2434                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2435                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2436         };
2437
2438         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2439                 .nb_max = I40E_MAX_RING_DESC,
2440                 .nb_min = I40E_MIN_RING_DESC,
2441                 .nb_align = I40E_ALIGN_RING_DESC,
2442         };
2443
2444         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2445                 .nb_max = I40E_MAX_RING_DESC,
2446                 .nb_min = I40E_MIN_RING_DESC,
2447                 .nb_align = I40E_ALIGN_RING_DESC,
2448         };
2449
2450         if (pf->flags & I40E_FLAG_VMDQ) {
2451                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2452                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2453                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2454                                                 pf->max_nb_vmdq_vsi;
2455                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2456                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2457                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2458         }
2459
2460         if (i40e_is_40G_device(hw->device_id))
2461                 /* For XL710 */
2462                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2463         else
2464                 /* For X710 */
2465                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2466 }
2467
2468 static int
2469 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2470 {
2471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2472         struct i40e_vsi *vsi = pf->main_vsi;
2473         PMD_INIT_FUNC_TRACE();
2474
2475         if (on)
2476                 return i40e_vsi_add_vlan(vsi, vlan_id);
2477         else
2478                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2479 }
2480
2481 static int
2482 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2483                    enum rte_vlan_type vlan_type,
2484                    uint16_t tpid)
2485 {
2486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         uint64_t reg_r = 0, reg_w = 0;
2488         uint16_t reg_id = 0;
2489         int ret = 0;
2490         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2491
2492         switch (vlan_type) {
2493         case ETH_VLAN_TYPE_OUTER:
2494                 if (qinq)
2495                         reg_id = 2;
2496                 else
2497                         reg_id = 3;
2498                 break;
2499         case ETH_VLAN_TYPE_INNER:
2500                 if (qinq)
2501                         reg_id = 3;
2502                 else {
2503                         ret = -EINVAL;
2504                         PMD_DRV_LOG(ERR,
2505                                 "Unsupported vlan type in single vlan.\n");
2506                         return ret;
2507                 }
2508                 break;
2509         default:
2510                 ret = -EINVAL;
2511                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2512                 return ret;
2513         }
2514         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2515                                           &reg_r, NULL);
2516         if (ret != I40E_SUCCESS) {
2517                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2518                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2519                 ret = -EIO;
2520                 return ret;
2521         }
2522         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2523                     "0x%08"PRIx64"", reg_id, reg_r);
2524
2525         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2526         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2527         if (reg_r == reg_w) {
2528                 ret = 0;
2529                 PMD_DRV_LOG(DEBUG, "No need to write");
2530                 return ret;
2531         }
2532
2533         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2534                                            reg_w, NULL);
2535         if (ret != I40E_SUCCESS) {
2536                 ret = -EIO;
2537                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2538                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2539                 return ret;
2540         }
2541         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2542                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2543
2544         return ret;
2545 }
2546
2547 static void
2548 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2549 {
2550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2551         struct i40e_vsi *vsi = pf->main_vsi;
2552
2553         if (mask & ETH_VLAN_FILTER_MASK) {
2554                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2555                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2556                 else
2557                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2558         }
2559
2560         if (mask & ETH_VLAN_STRIP_MASK) {
2561                 /* Enable or disable VLAN stripping */
2562                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2563                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2564                 else
2565                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2566         }
2567
2568         if (mask & ETH_VLAN_EXTEND_MASK) {
2569                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2570                         i40e_vsi_config_double_vlan(vsi, TRUE);
2571                         /* Set global registers with default ether type value */
2572                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2573                                            ETHER_TYPE_VLAN);
2574                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2575                                            ETHER_TYPE_VLAN);
2576                 }
2577                 else
2578                         i40e_vsi_config_double_vlan(vsi, FALSE);
2579         }
2580 }
2581
2582 static void
2583 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2584                           __rte_unused uint16_t queue,
2585                           __rte_unused int on)
2586 {
2587         PMD_INIT_FUNC_TRACE();
2588 }
2589
2590 static int
2591 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2592 {
2593         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2594         struct i40e_vsi *vsi = pf->main_vsi;
2595         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2596         struct i40e_vsi_vlan_pvid_info info;
2597
2598         memset(&info, 0, sizeof(info));
2599         info.on = on;
2600         if (info.on)
2601                 info.config.pvid = pvid;
2602         else {
2603                 info.config.reject.tagged =
2604                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2605                 info.config.reject.untagged =
2606                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2607         }
2608
2609         return i40e_vsi_vlan_pvid_set(vsi, &info);
2610 }
2611
2612 static int
2613 i40e_dev_led_on(struct rte_eth_dev *dev)
2614 {
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         uint32_t mode = i40e_led_get(hw);
2617
2618         if (mode == 0)
2619                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2620
2621         return 0;
2622 }
2623
2624 static int
2625 i40e_dev_led_off(struct rte_eth_dev *dev)
2626 {
2627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628         uint32_t mode = i40e_led_get(hw);
2629
2630         if (mode != 0)
2631                 i40e_led_set(hw, 0, false);
2632
2633         return 0;
2634 }
2635
2636 static int
2637 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2638 {
2639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641
2642         fc_conf->pause_time = pf->fc_conf.pause_time;
2643         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2644         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2645
2646          /* Return current mode according to actual setting*/
2647         switch (hw->fc.current_mode) {
2648         case I40E_FC_FULL:
2649                 fc_conf->mode = RTE_FC_FULL;
2650                 break;
2651         case I40E_FC_TX_PAUSE:
2652                 fc_conf->mode = RTE_FC_TX_PAUSE;
2653                 break;
2654         case I40E_FC_RX_PAUSE:
2655                 fc_conf->mode = RTE_FC_RX_PAUSE;
2656                 break;
2657         case I40E_FC_NONE:
2658         default:
2659                 fc_conf->mode = RTE_FC_NONE;
2660         };
2661
2662         return 0;
2663 }
2664
2665 static int
2666 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2667 {
2668         uint32_t mflcn_reg, fctrl_reg, reg;
2669         uint32_t max_high_water;
2670         uint8_t i, aq_failure;
2671         int err;
2672         struct i40e_hw *hw;
2673         struct i40e_pf *pf;
2674         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2675                 [RTE_FC_NONE] = I40E_FC_NONE,
2676                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2677                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2678                 [RTE_FC_FULL] = I40E_FC_FULL
2679         };
2680
2681         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2682
2683         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2684         if ((fc_conf->high_water > max_high_water) ||
2685                         (fc_conf->high_water < fc_conf->low_water)) {
2686                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2687                         "High_water must <= %d.", max_high_water);
2688                 return -EINVAL;
2689         }
2690
2691         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2693         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2694
2695         pf->fc_conf.pause_time = fc_conf->pause_time;
2696         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2697         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2698
2699         PMD_INIT_FUNC_TRACE();
2700
2701         /* All the link flow control related enable/disable register
2702          * configuration is handle by the F/W
2703          */
2704         err = i40e_set_fc(hw, &aq_failure, true);
2705         if (err < 0)
2706                 return -ENOSYS;
2707
2708         if (i40e_is_40G_device(hw->device_id)) {
2709                 /* Configure flow control refresh threshold,
2710                  * the value for stat_tx_pause_refresh_timer[8]
2711                  * is used for global pause operation.
2712                  */
2713
2714                 I40E_WRITE_REG(hw,
2715                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2716                                pf->fc_conf.pause_time);
2717
2718                 /* configure the timer value included in transmitted pause
2719                  * frame,
2720                  * the value for stat_tx_pause_quanta[8] is used for global
2721                  * pause operation
2722                  */
2723                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2724                                pf->fc_conf.pause_time);
2725
2726                 fctrl_reg = I40E_READ_REG(hw,
2727                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2728
2729                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2730                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2731                 else
2732                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2733
2734                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2735                                fctrl_reg);
2736         } else {
2737                 /* Configure pause time (2 TCs per register) */
2738                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2739                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2740                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2741
2742                 /* Configure flow control refresh threshold value */
2743                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2744                                pf->fc_conf.pause_time / 2);
2745
2746                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2747
2748                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2749                  *depending on configuration
2750                  */
2751                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2752                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2753                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2754                 } else {
2755                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2756                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2757                 }
2758
2759                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2760         }
2761
2762         /* config the water marker both based on the packets and bytes */
2763         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2764                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2765                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2766         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2767                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2768                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2769         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2770                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2771                        << I40E_KILOSHIFT);
2772         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2773                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2774                        << I40E_KILOSHIFT);
2775
2776         I40E_WRITE_FLUSH(hw);
2777
2778         return 0;
2779 }
2780
2781 static int
2782 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2783                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2784 {
2785         PMD_INIT_FUNC_TRACE();
2786
2787         return -ENOSYS;
2788 }
2789
2790 /* Add a MAC address, and update filters */
2791 static void
2792 i40e_macaddr_add(struct rte_eth_dev *dev,
2793                  struct ether_addr *mac_addr,
2794                  __rte_unused uint32_t index,
2795                  uint32_t pool)
2796 {
2797         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2798         struct i40e_mac_filter_info mac_filter;
2799         struct i40e_vsi *vsi;
2800         int ret;
2801
2802         /* If VMDQ not enabled or configured, return */
2803         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2804                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2805                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2806                         pool);
2807                 return;
2808         }
2809
2810         if (pool > pf->nb_cfg_vmdq_vsi) {
2811                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2812                                 pool, pf->nb_cfg_vmdq_vsi);
2813                 return;
2814         }
2815
2816         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2817         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2818                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2819         else
2820                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2821
2822         if (pool == 0)
2823                 vsi = pf->main_vsi;
2824         else
2825                 vsi = pf->vmdq[pool - 1].vsi;
2826
2827         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2828         if (ret != I40E_SUCCESS) {
2829                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2830                 return;
2831         }
2832 }
2833
2834 /* Remove a MAC address, and update filters */
2835 static void
2836 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2837 {
2838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2839         struct i40e_vsi *vsi;
2840         struct rte_eth_dev_data *data = dev->data;
2841         struct ether_addr *macaddr;
2842         int ret;
2843         uint32_t i;
2844         uint64_t pool_sel;
2845
2846         macaddr = &(data->mac_addrs[index]);
2847
2848         pool_sel = dev->data->mac_pool_sel[index];
2849
2850         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2851                 if (pool_sel & (1ULL << i)) {
2852                         if (i == 0)
2853                                 vsi = pf->main_vsi;
2854                         else {
2855                                 /* No VMDQ pool enabled or configured */
2856                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2857                                         (i > pf->nb_cfg_vmdq_vsi)) {
2858                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2859                                                         "/configured");
2860                                         return;
2861                                 }
2862                                 vsi = pf->vmdq[i - 1].vsi;
2863                         }
2864                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2865
2866                         if (ret) {
2867                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2868                                 return;
2869                         }
2870                 }
2871         }
2872 }
2873
2874 /* Set perfect match or hash match of MAC and VLAN for a VF */
2875 static int
2876 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2877                  struct rte_eth_mac_filter *filter,
2878                  bool add)
2879 {
2880         struct i40e_hw *hw;
2881         struct i40e_mac_filter_info mac_filter;
2882         struct ether_addr old_mac;
2883         struct ether_addr *new_mac;
2884         struct i40e_pf_vf *vf = NULL;
2885         uint16_t vf_id;
2886         int ret;
2887
2888         if (pf == NULL) {
2889                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2890                 return -EINVAL;
2891         }
2892         hw = I40E_PF_TO_HW(pf);
2893
2894         if (filter == NULL) {
2895                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2896                 return -EINVAL;
2897         }
2898
2899         new_mac = &filter->mac_addr;
2900
2901         if (is_zero_ether_addr(new_mac)) {
2902                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2903                 return -EINVAL;
2904         }
2905
2906         vf_id = filter->dst_id;
2907
2908         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2909                 PMD_DRV_LOG(ERR, "Invalid argument.");
2910                 return -EINVAL;
2911         }
2912         vf = &pf->vfs[vf_id];
2913
2914         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2915                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2916                 return -EINVAL;
2917         }
2918
2919         if (add) {
2920                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2921                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2922                                 ETHER_ADDR_LEN);
2923                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2924                                  ETHER_ADDR_LEN);
2925
2926                 mac_filter.filter_type = filter->filter_type;
2927                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2928                 if (ret != I40E_SUCCESS) {
2929                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2930                         return -1;
2931                 }
2932                 ether_addr_copy(new_mac, &pf->dev_addr);
2933         } else {
2934                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2935                                 ETHER_ADDR_LEN);
2936                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2937                 if (ret != I40E_SUCCESS) {
2938                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2939                         return -1;
2940                 }
2941
2942                 /* Clear device address as it has been removed */
2943                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2944                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2945         }
2946
2947         return 0;
2948 }
2949
2950 /* MAC filter handle */
2951 static int
2952 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2953                 void *arg)
2954 {
2955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2956         struct rte_eth_mac_filter *filter;
2957         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2958         int ret = I40E_NOT_SUPPORTED;
2959
2960         filter = (struct rte_eth_mac_filter *)(arg);
2961
2962         switch (filter_op) {
2963         case RTE_ETH_FILTER_NOP:
2964                 ret = I40E_SUCCESS;
2965                 break;
2966         case RTE_ETH_FILTER_ADD:
2967                 i40e_pf_disable_irq0(hw);
2968                 if (filter->is_vf)
2969                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2970                 i40e_pf_enable_irq0(hw);
2971                 break;
2972         case RTE_ETH_FILTER_DELETE:
2973                 i40e_pf_disable_irq0(hw);
2974                 if (filter->is_vf)
2975                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2976                 i40e_pf_enable_irq0(hw);
2977                 break;
2978         default:
2979                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2980                 ret = I40E_ERR_PARAM;
2981                 break;
2982         }
2983
2984         return ret;
2985 }
2986
2987 static int
2988 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2989 {
2990         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2992         int ret;
2993
2994         if (!lut)
2995                 return -EINVAL;
2996
2997         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2998                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2999                                           lut, lut_size);
3000                 if (ret) {
3001                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3002                         return ret;
3003                 }
3004         } else {
3005                 uint32_t *lut_dw = (uint32_t *)lut;
3006                 uint16_t i, lut_size_dw = lut_size / 4;
3007
3008                 for (i = 0; i < lut_size_dw; i++)
3009                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3010         }
3011
3012         return 0;
3013 }
3014
3015 static int
3016 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3017 {
3018         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3019         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3020         int ret;
3021
3022         if (!vsi || !lut)
3023                 return -EINVAL;
3024
3025         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3026                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3027                                           lut, lut_size);
3028                 if (ret) {
3029                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3030                         return ret;
3031                 }
3032         } else {
3033                 uint32_t *lut_dw = (uint32_t *)lut;
3034                 uint16_t i, lut_size_dw = lut_size / 4;
3035
3036                 for (i = 0; i < lut_size_dw; i++)
3037                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3038                 I40E_WRITE_FLUSH(hw);
3039         }
3040
3041         return 0;
3042 }
3043
3044 static int
3045 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3046                          struct rte_eth_rss_reta_entry64 *reta_conf,
3047                          uint16_t reta_size)
3048 {
3049         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3050         uint16_t i, lut_size = pf->hash_lut_size;
3051         uint16_t idx, shift;
3052         uint8_t *lut;
3053         int ret;
3054
3055         if (reta_size != lut_size ||
3056                 reta_size > ETH_RSS_RETA_SIZE_512) {
3057                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3058                         "(%d) doesn't match the number hardware can supported "
3059                                         "(%d)\n", reta_size, lut_size);
3060                 return -EINVAL;
3061         }
3062
3063         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3064         if (!lut) {
3065                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3066                 return -ENOMEM;
3067         }
3068         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3069         if (ret)
3070                 goto out;
3071         for (i = 0; i < reta_size; i++) {
3072                 idx = i / RTE_RETA_GROUP_SIZE;
3073                 shift = i % RTE_RETA_GROUP_SIZE;
3074                 if (reta_conf[idx].mask & (1ULL << shift))
3075                         lut[i] = reta_conf[idx].reta[shift];
3076         }
3077         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3078
3079 out:
3080         rte_free(lut);
3081
3082         return ret;
3083 }
3084
3085 static int
3086 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3087                         struct rte_eth_rss_reta_entry64 *reta_conf,
3088                         uint16_t reta_size)
3089 {
3090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3091         uint16_t i, lut_size = pf->hash_lut_size;
3092         uint16_t idx, shift;
3093         uint8_t *lut;
3094         int ret;
3095
3096         if (reta_size != lut_size ||
3097                 reta_size > ETH_RSS_RETA_SIZE_512) {
3098                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3099                         "(%d) doesn't match the number hardware can supported "
3100                                         "(%d)\n", reta_size, lut_size);
3101                 return -EINVAL;
3102         }
3103
3104         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3105         if (!lut) {
3106                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3107                 return -ENOMEM;
3108         }
3109
3110         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3111         if (ret)
3112                 goto out;
3113         for (i = 0; i < reta_size; i++) {
3114                 idx = i / RTE_RETA_GROUP_SIZE;
3115                 shift = i % RTE_RETA_GROUP_SIZE;
3116                 if (reta_conf[idx].mask & (1ULL << shift))
3117                         reta_conf[idx].reta[shift] = lut[i];
3118         }
3119
3120 out:
3121         rte_free(lut);
3122
3123         return ret;
3124 }
3125
3126 /**
3127  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3128  * @hw:   pointer to the HW structure
3129  * @mem:  pointer to mem struct to fill out
3130  * @size: size of memory requested
3131  * @alignment: what to align the allocation to
3132  **/
3133 enum i40e_status_code
3134 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3135                         struct i40e_dma_mem *mem,
3136                         u64 size,
3137                         u32 alignment)
3138 {
3139         const struct rte_memzone *mz = NULL;
3140         char z_name[RTE_MEMZONE_NAMESIZE];
3141
3142         if (!mem)
3143                 return I40E_ERR_PARAM;
3144
3145         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3146         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3147                                          alignment, RTE_PGSIZE_2M);
3148         if (!mz)
3149                 return I40E_ERR_NO_MEMORY;
3150
3151         mem->size = size;
3152         mem->va = mz->addr;
3153         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3154         mem->zone = (const void *)mz;
3155         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3156                     "%"PRIu64, mz->name, mem->pa);
3157
3158         return I40E_SUCCESS;
3159 }
3160
3161 /**
3162  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3163  * @hw:   pointer to the HW structure
3164  * @mem:  ptr to mem struct to free
3165  **/
3166 enum i40e_status_code
3167 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3168                     struct i40e_dma_mem *mem)
3169 {
3170         if (!mem)
3171                 return I40E_ERR_PARAM;
3172
3173         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3174                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3175                     mem->pa);
3176         rte_memzone_free((const struct rte_memzone *)mem->zone);
3177         mem->zone = NULL;
3178         mem->va = NULL;
3179         mem->pa = (u64)0;
3180
3181         return I40E_SUCCESS;
3182 }
3183
3184 /**
3185  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3186  * @hw:   pointer to the HW structure
3187  * @mem:  pointer to mem struct to fill out
3188  * @size: size of memory requested
3189  **/
3190 enum i40e_status_code
3191 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3192                          struct i40e_virt_mem *mem,
3193                          u32 size)
3194 {
3195         if (!mem)
3196                 return I40E_ERR_PARAM;
3197
3198         mem->size = size;
3199         mem->va = rte_zmalloc("i40e", size, 0);
3200
3201         if (mem->va)
3202                 return I40E_SUCCESS;
3203         else
3204                 return I40E_ERR_NO_MEMORY;
3205 }
3206
3207 /**
3208  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3209  * @hw:   pointer to the HW structure
3210  * @mem:  pointer to mem struct to free
3211  **/
3212 enum i40e_status_code
3213 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3214                      struct i40e_virt_mem *mem)
3215 {
3216         if (!mem)
3217                 return I40E_ERR_PARAM;
3218
3219         rte_free(mem->va);
3220         mem->va = NULL;
3221
3222         return I40E_SUCCESS;
3223 }
3224
3225 void
3226 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3227 {
3228         rte_spinlock_init(&sp->spinlock);
3229 }
3230
3231 void
3232 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3233 {
3234         rte_spinlock_lock(&sp->spinlock);
3235 }
3236
3237 void
3238 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3239 {
3240         rte_spinlock_unlock(&sp->spinlock);
3241 }
3242
3243 void
3244 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3245 {
3246         return;
3247 }
3248
3249 /**
3250  * Get the hardware capabilities, which will be parsed
3251  * and saved into struct i40e_hw.
3252  */
3253 static int
3254 i40e_get_cap(struct i40e_hw *hw)
3255 {
3256         struct i40e_aqc_list_capabilities_element_resp *buf;
3257         uint16_t len, size = 0;
3258         int ret;
3259
3260         /* Calculate a huge enough buff for saving response data temporarily */
3261         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3262                                                 I40E_MAX_CAP_ELE_NUM;
3263         buf = rte_zmalloc("i40e", len, 0);
3264         if (!buf) {
3265                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3266                 return I40E_ERR_NO_MEMORY;
3267         }
3268
3269         /* Get, parse the capabilities and save it to hw */
3270         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3271                         i40e_aqc_opc_list_func_capabilities, NULL);
3272         if (ret != I40E_SUCCESS)
3273                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3274
3275         /* Free the temporary buffer after being used */
3276         rte_free(buf);
3277
3278         return ret;
3279 }
3280
3281 static int
3282 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3283 {
3284         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3286         uint16_t qp_count = 0, vsi_count = 0;
3287
3288         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3289                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3290                 return -EINVAL;
3291         }
3292         /* Add the parameter init for LFC */
3293         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3294         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3295         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3296
3297         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3298         pf->max_num_vsi = hw->func_caps.num_vsis;
3299         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3300         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3301         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3302
3303         /* FDir queue/VSI allocation */
3304         pf->fdir_qp_offset = 0;
3305         if (hw->func_caps.fd) {
3306                 pf->flags |= I40E_FLAG_FDIR;
3307                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3308         } else {
3309                 pf->fdir_nb_qps = 0;
3310         }
3311         qp_count += pf->fdir_nb_qps;
3312         vsi_count += 1;
3313
3314         /* LAN queue/VSI allocation */
3315         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3316         if (!hw->func_caps.rss) {
3317                 pf->lan_nb_qps = 1;
3318         } else {
3319                 pf->flags |= I40E_FLAG_RSS;
3320                 if (hw->mac.type == I40E_MAC_X722)
3321                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3322                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3323         }
3324         qp_count += pf->lan_nb_qps;
3325         vsi_count += 1;
3326
3327         /* VF queue/VSI allocation */
3328         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3329         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3330                 pf->flags |= I40E_FLAG_SRIOV;
3331                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3332                 pf->vf_num = dev->pci_dev->max_vfs;
3333                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3334                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3335                             pf->vf_nb_qps * pf->vf_num);
3336         } else {
3337                 pf->vf_nb_qps = 0;
3338                 pf->vf_num = 0;
3339         }
3340         qp_count += pf->vf_nb_qps * pf->vf_num;
3341         vsi_count += pf->vf_num;
3342
3343         /* VMDq queue/VSI allocation */
3344         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3345         pf->vmdq_nb_qps = 0;
3346         pf->max_nb_vmdq_vsi = 0;
3347         if (hw->func_caps.vmdq) {
3348                 if (qp_count < hw->func_caps.num_tx_qp &&
3349                         vsi_count < hw->func_caps.num_vsis) {
3350                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3351                                 qp_count) / pf->vmdq_nb_qp_max;
3352
3353                         /* Limit the maximum number of VMDq vsi to the maximum
3354                          * ethdev can support
3355                          */
3356                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3357                                 hw->func_caps.num_vsis - vsi_count);
3358                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3359                                 ETH_64_POOLS);
3360                         if (pf->max_nb_vmdq_vsi) {
3361                                 pf->flags |= I40E_FLAG_VMDQ;
3362                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3363                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3364                                             "per VMDQ VSI, in total %u queues",
3365                                             pf->max_nb_vmdq_vsi,
3366                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3367                                             pf->max_nb_vmdq_vsi);
3368                         } else {
3369                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3370                                             "VMDq");
3371                         }
3372                 } else {
3373                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3374                 }
3375         }
3376         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3377         vsi_count += pf->max_nb_vmdq_vsi;
3378
3379         if (hw->func_caps.dcb)
3380                 pf->flags |= I40E_FLAG_DCB;
3381
3382         if (qp_count > hw->func_caps.num_tx_qp) {
3383                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3384                             "the hardware maximum %u", qp_count,
3385                             hw->func_caps.num_tx_qp);
3386                 return -EINVAL;
3387         }
3388         if (vsi_count > hw->func_caps.num_vsis) {
3389                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3390                             "the hardware maximum %u", vsi_count,
3391                             hw->func_caps.num_vsis);
3392                 return -EINVAL;
3393         }
3394
3395         return 0;
3396 }
3397
3398 static int
3399 i40e_pf_get_switch_config(struct i40e_pf *pf)
3400 {
3401         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3402         struct i40e_aqc_get_switch_config_resp *switch_config;
3403         struct i40e_aqc_switch_config_element_resp *element;
3404         uint16_t start_seid = 0, num_reported;
3405         int ret;
3406
3407         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3408                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3409         if (!switch_config) {
3410                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3411                 return -ENOMEM;
3412         }
3413
3414         /* Get the switch configurations */
3415         ret = i40e_aq_get_switch_config(hw, switch_config,
3416                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3417         if (ret != I40E_SUCCESS) {
3418                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3419                 goto fail;
3420         }
3421         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3422         if (num_reported != 1) { /* The number should be 1 */
3423                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3424                 goto fail;
3425         }
3426
3427         /* Parse the switch configuration elements */
3428         element = &(switch_config->element[0]);
3429         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3430                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3431                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3432         } else
3433                 PMD_DRV_LOG(INFO, "Unknown element type");
3434
3435 fail:
3436         rte_free(switch_config);
3437
3438         return ret;
3439 }
3440
3441 static int
3442 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3443                         uint32_t num)
3444 {
3445         struct pool_entry *entry;
3446
3447         if (pool == NULL || num == 0)
3448                 return -EINVAL;
3449
3450         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3451         if (entry == NULL) {
3452                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3453                 return -ENOMEM;
3454         }
3455
3456         /* queue heap initialize */
3457         pool->num_free = num;
3458         pool->num_alloc = 0;
3459         pool->base = base;
3460         LIST_INIT(&pool->alloc_list);
3461         LIST_INIT(&pool->free_list);
3462
3463         /* Initialize element  */
3464         entry->base = 0;
3465         entry->len = num;
3466
3467         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3468         return 0;
3469 }
3470
3471 static void
3472 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3473 {
3474         struct pool_entry *entry, *next_entry;
3475
3476         if (pool == NULL)
3477                 return;
3478
3479         for (entry = LIST_FIRST(&pool->alloc_list);
3480                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3481                         entry = next_entry) {
3482                 LIST_REMOVE(entry, next);
3483                 rte_free(entry);
3484         }
3485
3486         for (entry = LIST_FIRST(&pool->free_list);
3487                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3488                         entry = next_entry) {
3489                 LIST_REMOVE(entry, next);
3490                 rte_free(entry);
3491         }
3492
3493         pool->num_free = 0;
3494         pool->num_alloc = 0;
3495         pool->base = 0;
3496         LIST_INIT(&pool->alloc_list);
3497         LIST_INIT(&pool->free_list);
3498 }
3499
3500 static int
3501 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3502                        uint32_t base)
3503 {
3504         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3505         uint32_t pool_offset;
3506         int insert;
3507
3508         if (pool == NULL) {
3509                 PMD_DRV_LOG(ERR, "Invalid parameter");
3510                 return -EINVAL;
3511         }
3512
3513         pool_offset = base - pool->base;
3514         /* Lookup in alloc list */
3515         LIST_FOREACH(entry, &pool->alloc_list, next) {
3516                 if (entry->base == pool_offset) {
3517                         valid_entry = entry;
3518                         LIST_REMOVE(entry, next);
3519                         break;
3520                 }
3521         }
3522
3523         /* Not find, return */
3524         if (valid_entry == NULL) {
3525                 PMD_DRV_LOG(ERR, "Failed to find entry");
3526                 return -EINVAL;
3527         }
3528
3529         /**
3530          * Found it, move it to free list  and try to merge.
3531          * In order to make merge easier, always sort it by qbase.
3532          * Find adjacent prev and last entries.
3533          */
3534         prev = next = NULL;
3535         LIST_FOREACH(entry, &pool->free_list, next) {
3536                 if (entry->base > valid_entry->base) {
3537                         next = entry;
3538                         break;
3539                 }
3540                 prev = entry;
3541         }
3542
3543         insert = 0;
3544         /* Try to merge with next one*/
3545         if (next != NULL) {
3546                 /* Merge with next one */
3547                 if (valid_entry->base + valid_entry->len == next->base) {
3548                         next->base = valid_entry->base;
3549                         next->len += valid_entry->len;
3550                         rte_free(valid_entry);
3551                         valid_entry = next;
3552                         insert = 1;
3553                 }
3554         }
3555
3556         if (prev != NULL) {
3557                 /* Merge with previous one */
3558                 if (prev->base + prev->len == valid_entry->base) {
3559                         prev->len += valid_entry->len;
3560                         /* If it merge with next one, remove next node */
3561                         if (insert == 1) {
3562                                 LIST_REMOVE(valid_entry, next);
3563                                 rte_free(valid_entry);
3564                         } else {
3565                                 rte_free(valid_entry);
3566                                 insert = 1;
3567                         }
3568                 }
3569         }
3570
3571         /* Not find any entry to merge, insert */
3572         if (insert == 0) {
3573                 if (prev != NULL)
3574                         LIST_INSERT_AFTER(prev, valid_entry, next);
3575                 else if (next != NULL)
3576                         LIST_INSERT_BEFORE(next, valid_entry, next);
3577                 else /* It's empty list, insert to head */
3578                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3579         }
3580
3581         pool->num_free += valid_entry->len;
3582         pool->num_alloc -= valid_entry->len;
3583
3584         return 0;
3585 }
3586
3587 static int
3588 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3589                        uint16_t num)
3590 {
3591         struct pool_entry *entry, *valid_entry;
3592
3593         if (pool == NULL || num == 0) {
3594                 PMD_DRV_LOG(ERR, "Invalid parameter");
3595                 return -EINVAL;
3596         }
3597
3598         if (pool->num_free < num) {
3599                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3600                             num, pool->num_free);
3601                 return -ENOMEM;
3602         }
3603
3604         valid_entry = NULL;
3605         /* Lookup  in free list and find most fit one */
3606         LIST_FOREACH(entry, &pool->free_list, next) {
3607                 if (entry->len >= num) {
3608                         /* Find best one */
3609                         if (entry->len == num) {
3610                                 valid_entry = entry;
3611                                 break;
3612                         }
3613                         if (valid_entry == NULL || valid_entry->len > entry->len)
3614                                 valid_entry = entry;
3615                 }
3616         }
3617
3618         /* Not find one to satisfy the request, return */
3619         if (valid_entry == NULL) {
3620                 PMD_DRV_LOG(ERR, "No valid entry found");
3621                 return -ENOMEM;
3622         }
3623         /**
3624          * The entry have equal queue number as requested,
3625          * remove it from alloc_list.
3626          */
3627         if (valid_entry->len == num) {
3628                 LIST_REMOVE(valid_entry, next);
3629         } else {
3630                 /**
3631                  * The entry have more numbers than requested,
3632                  * create a new entry for alloc_list and minus its
3633                  * queue base and number in free_list.
3634                  */
3635                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3636                 if (entry == NULL) {
3637                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3638                                     "resource pool");
3639                         return -ENOMEM;
3640                 }
3641                 entry->base = valid_entry->base;
3642                 entry->len = num;
3643                 valid_entry->base += num;
3644                 valid_entry->len -= num;
3645                 valid_entry = entry;
3646         }
3647
3648         /* Insert it into alloc list, not sorted */
3649         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3650
3651         pool->num_free -= valid_entry->len;
3652         pool->num_alloc += valid_entry->len;
3653
3654         return valid_entry->base + pool->base;
3655 }
3656
3657 /**
3658  * bitmap_is_subset - Check whether src2 is subset of src1
3659  **/
3660 static inline int
3661 bitmap_is_subset(uint8_t src1, uint8_t src2)
3662 {
3663         return !((src1 ^ src2) & src2);
3664 }
3665
3666 static enum i40e_status_code
3667 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3668 {
3669         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3670
3671         /* If DCB is not supported, only default TC is supported */
3672         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3673                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3674                 return I40E_NOT_SUPPORTED;
3675         }
3676
3677         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3678                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3679                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3680                             enabled_tcmap);
3681                 return I40E_NOT_SUPPORTED;
3682         }
3683         return I40E_SUCCESS;
3684 }
3685
3686 int
3687 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3688                                 struct i40e_vsi_vlan_pvid_info *info)
3689 {
3690         struct i40e_hw *hw;
3691         struct i40e_vsi_context ctxt;
3692         uint8_t vlan_flags = 0;
3693         int ret;
3694
3695         if (vsi == NULL || info == NULL) {
3696                 PMD_DRV_LOG(ERR, "invalid parameters");
3697                 return I40E_ERR_PARAM;
3698         }
3699
3700         if (info->on) {
3701                 vsi->info.pvid = info->config.pvid;
3702                 /**
3703                  * If insert pvid is enabled, only tagged pkts are
3704                  * allowed to be sent out.
3705                  */
3706                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3707                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3708         } else {
3709                 vsi->info.pvid = 0;
3710                 if (info->config.reject.tagged == 0)
3711                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3712
3713                 if (info->config.reject.untagged == 0)
3714                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3715         }
3716         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3717                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3718         vsi->info.port_vlan_flags |= vlan_flags;
3719         vsi->info.valid_sections =
3720                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3721         memset(&ctxt, 0, sizeof(ctxt));
3722         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3723         ctxt.seid = vsi->seid;
3724
3725         hw = I40E_VSI_TO_HW(vsi);
3726         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3727         if (ret != I40E_SUCCESS)
3728                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3729
3730         return ret;
3731 }
3732
3733 static int
3734 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3735 {
3736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3737         int i, ret;
3738         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3739
3740         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3741         if (ret != I40E_SUCCESS)
3742                 return ret;
3743
3744         if (!vsi->seid) {
3745                 PMD_DRV_LOG(ERR, "seid not valid");
3746                 return -EINVAL;
3747         }
3748
3749         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3750         tc_bw_data.tc_valid_bits = enabled_tcmap;
3751         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3752                 tc_bw_data.tc_bw_credits[i] =
3753                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3754
3755         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3756         if (ret != I40E_SUCCESS) {
3757                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3758                 return ret;
3759         }
3760
3761         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3762                                         sizeof(vsi->info.qs_handle));
3763         return I40E_SUCCESS;
3764 }
3765
3766 static enum i40e_status_code
3767 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3768                                  struct i40e_aqc_vsi_properties_data *info,
3769                                  uint8_t enabled_tcmap)
3770 {
3771         enum i40e_status_code ret;
3772         int i, total_tc = 0;
3773         uint16_t qpnum_per_tc, bsf, qp_idx;
3774
3775         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3776         if (ret != I40E_SUCCESS)
3777                 return ret;
3778
3779         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3780                 if (enabled_tcmap & (1 << i))
3781                         total_tc++;
3782         vsi->enabled_tc = enabled_tcmap;
3783
3784         /* Number of queues per enabled TC */
3785         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3786         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3787         bsf = rte_bsf32(qpnum_per_tc);
3788
3789         /* Adjust the queue number to actual queues that can be applied */
3790         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3791                 vsi->nb_qps = qpnum_per_tc * total_tc;
3792
3793         /**
3794          * Configure TC and queue mapping parameters, for enabled TC,
3795          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3796          * default queue will serve it.
3797          */
3798         qp_idx = 0;
3799         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3800                 if (vsi->enabled_tc & (1 << i)) {
3801                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3802                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3803                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3804                         qp_idx += qpnum_per_tc;
3805                 } else
3806                         info->tc_mapping[i] = 0;
3807         }
3808
3809         /* Associate queue number with VSI */
3810         if (vsi->type == I40E_VSI_SRIOV) {
3811                 info->mapping_flags |=
3812                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3813                 for (i = 0; i < vsi->nb_qps; i++)
3814                         info->queue_mapping[i] =
3815                                 rte_cpu_to_le_16(vsi->base_queue + i);
3816         } else {
3817                 info->mapping_flags |=
3818                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3819                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3820         }
3821         info->valid_sections |=
3822                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3823
3824         return I40E_SUCCESS;
3825 }
3826
3827 static int
3828 i40e_veb_release(struct i40e_veb *veb)
3829 {
3830         struct i40e_vsi *vsi;
3831         struct i40e_hw *hw;
3832
3833         if (veb == NULL)
3834                 return -EINVAL;
3835
3836         if (!TAILQ_EMPTY(&veb->head)) {
3837                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3838                 return -EACCES;
3839         }
3840         /* associate_vsi field is NULL for floating VEB */
3841         if (veb->associate_vsi != NULL) {
3842                 vsi = veb->associate_vsi;
3843                 hw = I40E_VSI_TO_HW(vsi);
3844
3845                 vsi->uplink_seid = veb->uplink_seid;
3846                 vsi->veb = NULL;
3847         } else {
3848                 veb->associate_pf->main_vsi->floating_veb = NULL;
3849                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
3850         }
3851
3852         i40e_aq_delete_element(hw, veb->seid, NULL);
3853         rte_free(veb);
3854         return I40E_SUCCESS;
3855 }
3856
3857 /* Setup a veb */
3858 static struct i40e_veb *
3859 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3860 {
3861         struct i40e_veb *veb;
3862         int ret;
3863         struct i40e_hw *hw;
3864
3865         if (pf == NULL) {
3866                 PMD_DRV_LOG(ERR,
3867                             "veb setup failed, associated PF shouldn't null");
3868                 return NULL;
3869         }
3870         hw = I40E_PF_TO_HW(pf);
3871
3872         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3873         if (!veb) {
3874                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3875                 goto fail;
3876         }
3877
3878         veb->associate_vsi = vsi;
3879         veb->associate_pf = pf;
3880         TAILQ_INIT(&veb->head);
3881         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
3882
3883         /* create floating veb if vsi is NULL */
3884         if (vsi != NULL) {
3885                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3886                                       I40E_DEFAULT_TCMAP, false,
3887                                       &veb->seid, false, NULL);
3888         } else {
3889                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
3890                                       true, &veb->seid, false, NULL);
3891         }
3892
3893         if (ret != I40E_SUCCESS) {
3894                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3895                             hw->aq.asq_last_status);
3896                 goto fail;
3897         }
3898
3899         /* get statistics index */
3900         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3901                                 &veb->stats_idx, NULL, NULL, NULL);
3902         if (ret != I40E_SUCCESS) {
3903                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3904                             hw->aq.asq_last_status);
3905                 goto fail;
3906         }
3907         /* Get VEB bandwidth, to be implemented */
3908         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3909         if (vsi)
3910                 vsi->uplink_seid = veb->seid;
3911
3912         return veb;
3913 fail:
3914         rte_free(veb);
3915         return NULL;
3916 }
3917
3918 int
3919 i40e_vsi_release(struct i40e_vsi *vsi)
3920 {
3921         struct i40e_pf *pf;
3922         struct i40e_hw *hw;
3923         struct i40e_vsi_list *vsi_list;
3924         int ret;
3925         struct i40e_mac_filter *f;
3926         uint16_t user_param = vsi->user_param;
3927
3928         if (!vsi)
3929                 return I40E_SUCCESS;
3930
3931         pf = I40E_VSI_TO_PF(vsi);
3932         hw = I40E_VSI_TO_HW(vsi);
3933
3934         /* VSI has child to attach, release child first */
3935         if (vsi->veb) {
3936                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3937                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3938                                 return -1;
3939                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3940                 }
3941                 i40e_veb_release(vsi->veb);
3942         }
3943
3944         if (vsi->floating_veb) {
3945                 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
3946                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3947                                 return -1;
3948                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
3949                 }
3950         }
3951
3952         /* Remove all macvlan filters of the VSI */
3953         i40e_vsi_remove_all_macvlan_filter(vsi);
3954         TAILQ_FOREACH(f, &vsi->mac_list, next)
3955                 rte_free(f);
3956
3957         if (vsi->type != I40E_VSI_MAIN &&
3958             ((vsi->type != I40E_VSI_SRIOV) ||
3959             !pf->floating_veb_list[user_param])) {
3960                 /* Remove vsi from parent's sibling list */
3961                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3962                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3963                         return I40E_ERR_PARAM;
3964                 }
3965                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3966                                 &vsi->sib_vsi_list, list);
3967
3968                 /* Remove all switch element of the VSI */
3969                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3970                 if (ret != I40E_SUCCESS)
3971                         PMD_DRV_LOG(ERR, "Failed to delete element");
3972         }
3973
3974         if ((vsi->type == I40E_VSI_SRIOV) &&
3975             pf->floating_veb_list[user_param]) {
3976                 /* Remove vsi from parent's sibling list */
3977                 if (vsi->parent_vsi == NULL ||
3978                     vsi->parent_vsi->floating_veb == NULL) {
3979                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3980                         return I40E_ERR_PARAM;
3981                 }
3982                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
3983                              &vsi->sib_vsi_list, list);
3984
3985                 /* Remove all switch element of the VSI */
3986                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3987                 if (ret != I40E_SUCCESS)
3988                         PMD_DRV_LOG(ERR, "Failed to delete element");
3989         }
3990
3991         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3992
3993         if (vsi->type != I40E_VSI_SRIOV)
3994                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3995         rte_free(vsi);
3996
3997         return I40E_SUCCESS;
3998 }
3999
4000 static int
4001 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4002 {
4003         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4004         struct i40e_aqc_remove_macvlan_element_data def_filter;
4005         struct i40e_mac_filter_info filter;
4006         int ret;
4007
4008         if (vsi->type != I40E_VSI_MAIN)
4009                 return I40E_ERR_CONFIG;
4010         memset(&def_filter, 0, sizeof(def_filter));
4011         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4012                                         ETH_ADDR_LEN);
4013         def_filter.vlan_tag = 0;
4014         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4015                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4016         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4017         if (ret != I40E_SUCCESS) {
4018                 struct i40e_mac_filter *f;
4019                 struct ether_addr *mac;
4020
4021                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4022                             "macvlan filter");
4023                 /* It needs to add the permanent mac into mac list */
4024                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4025                 if (f == NULL) {
4026                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4027                         return I40E_ERR_NO_MEMORY;
4028                 }
4029                 mac = &f->mac_info.mac_addr;
4030                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4031                                 ETH_ADDR_LEN);
4032                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4033                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4034                 vsi->mac_num++;
4035
4036                 return ret;
4037         }
4038         (void)rte_memcpy(&filter.mac_addr,
4039                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4040         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4041         return i40e_vsi_add_mac(vsi, &filter);
4042 }
4043
4044 /*
4045  * i40e_vsi_get_bw_config - Query VSI BW Information
4046  * @vsi: the VSI to be queried
4047  *
4048  * Returns 0 on success, negative value on failure
4049  */
4050 static enum i40e_status_code
4051 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4052 {
4053         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4054         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4055         struct i40e_hw *hw = &vsi->adapter->hw;
4056         i40e_status ret;
4057         int i;
4058         uint32_t bw_max;
4059
4060         memset(&bw_config, 0, sizeof(bw_config));
4061         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4062         if (ret != I40E_SUCCESS) {
4063                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4064                             hw->aq.asq_last_status);
4065                 return ret;
4066         }
4067
4068         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4069         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4070                                         &ets_sla_config, NULL);
4071         if (ret != I40E_SUCCESS) {
4072                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4073                             "configuration %u", hw->aq.asq_last_status);
4074                 return ret;
4075         }
4076
4077         /* store and print out BW info */
4078         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4079         vsi->bw_info.bw_max = bw_config.max_bw;
4080         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4081         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4082         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4083                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4084                      I40E_16_BIT_WIDTH);
4085         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4086                 vsi->bw_info.bw_ets_share_credits[i] =
4087                                 ets_sla_config.share_credits[i];
4088                 vsi->bw_info.bw_ets_credits[i] =
4089                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4090                 /* 4 bits per TC, 4th bit is reserved */
4091                 vsi->bw_info.bw_ets_max[i] =
4092                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4093                                   RTE_LEN2MASK(3, uint8_t));
4094                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4095                             vsi->bw_info.bw_ets_share_credits[i]);
4096                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4097                             vsi->bw_info.bw_ets_credits[i]);
4098                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4099                             vsi->bw_info.bw_ets_max[i]);
4100         }
4101
4102         return I40E_SUCCESS;
4103 }
4104
4105 /* i40e_enable_pf_lb
4106  * @pf: pointer to the pf structure
4107  *
4108  * allow loopback on pf
4109  */
4110 static inline void
4111 i40e_enable_pf_lb(struct i40e_pf *pf)
4112 {
4113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4114         struct i40e_vsi_context ctxt;
4115         int ret;
4116
4117         /* Use the FW API if FW >= v5.0 */
4118         if (hw->aq.fw_maj_ver < 5) {
4119                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4120                 return;
4121         }
4122
4123         memset(&ctxt, 0, sizeof(ctxt));
4124         ctxt.seid = pf->main_vsi_seid;
4125         ctxt.pf_num = hw->pf_id;
4126         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4127         if (ret) {
4128                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4129                             ret, hw->aq.asq_last_status);
4130                 return;
4131         }
4132         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4133         ctxt.info.valid_sections =
4134                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4135         ctxt.info.switch_id |=
4136                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4137
4138         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4139         if (ret)
4140                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4141                             hw->aq.asq_last_status);
4142 }
4143
4144 /* Setup a VSI */
4145 struct i40e_vsi *
4146 i40e_vsi_setup(struct i40e_pf *pf,
4147                enum i40e_vsi_type type,
4148                struct i40e_vsi *uplink_vsi,
4149                uint16_t user_param)
4150 {
4151         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4152         struct i40e_vsi *vsi;
4153         struct i40e_mac_filter_info filter;
4154         int ret;
4155         struct i40e_vsi_context ctxt;
4156         struct ether_addr broadcast =
4157                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4158
4159         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4160             uplink_vsi == NULL) {
4161                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4162                             "VSI link shouldn't be NULL");
4163                 return NULL;
4164         }
4165
4166         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4167                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4168                             "uplink VSI should be NULL");
4169                 return NULL;
4170         }
4171
4172         /* two situations
4173          * 1.type is not MAIN and uplink vsi is not NULL
4174          * If uplink vsi didn't setup VEB, create one first under veb field
4175          * 2.type is SRIOV and the uplink is NULL
4176          * If floating VEB is NULL, create one veb under floating veb field
4177          */
4178
4179         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4180             uplink_vsi->veb == NULL) {
4181                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4182
4183                 if (uplink_vsi->veb == NULL) {
4184                         PMD_DRV_LOG(ERR, "VEB setup failed");
4185                         return NULL;
4186                 }
4187                 /* set ALLOWLOOPBACk on pf, when veb is created */
4188                 i40e_enable_pf_lb(pf);
4189         }
4190
4191         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4192             pf->main_vsi->floating_veb == NULL) {
4193                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4194
4195                 if (pf->main_vsi->floating_veb == NULL) {
4196                         PMD_DRV_LOG(ERR, "VEB setup failed");
4197                         return NULL;
4198                 }
4199         }
4200
4201         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4202         if (!vsi) {
4203                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4204                 return NULL;
4205         }
4206         TAILQ_INIT(&vsi->mac_list);
4207         vsi->type = type;
4208         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4209         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4210         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4211         vsi->user_param = user_param;
4212         /* Allocate queues */
4213         switch (vsi->type) {
4214         case I40E_VSI_MAIN  :
4215                 vsi->nb_qps = pf->lan_nb_qps;
4216                 break;
4217         case I40E_VSI_SRIOV :
4218                 vsi->nb_qps = pf->vf_nb_qps;
4219                 break;
4220         case I40E_VSI_VMDQ2:
4221                 vsi->nb_qps = pf->vmdq_nb_qps;
4222                 break;
4223         case I40E_VSI_FDIR:
4224                 vsi->nb_qps = pf->fdir_nb_qps;
4225                 break;
4226         default:
4227                 goto fail_mem;
4228         }
4229         /*
4230          * The filter status descriptor is reported in rx queue 0,
4231          * while the tx queue for fdir filter programming has no
4232          * such constraints, can be non-zero queues.
4233          * To simplify it, choose FDIR vsi use queue 0 pair.
4234          * To make sure it will use queue 0 pair, queue allocation
4235          * need be done before this function is called
4236          */
4237         if (type != I40E_VSI_FDIR) {
4238                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4239                         if (ret < 0) {
4240                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4241                                                 vsi->seid, ret);
4242                                 goto fail_mem;
4243                         }
4244                         vsi->base_queue = ret;
4245         } else
4246                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4247
4248         /* VF has MSIX interrupt in VF range, don't allocate here */
4249         if (type == I40E_VSI_MAIN) {
4250                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4251                                           RTE_MIN(vsi->nb_qps,
4252                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4253                 if (ret < 0) {
4254                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4255                                     vsi->seid, ret);
4256                         goto fail_queue_alloc;
4257                 }
4258                 vsi->msix_intr = ret;
4259                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4260         } else if (type != I40E_VSI_SRIOV) {
4261                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4262                 if (ret < 0) {
4263                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4264                         goto fail_queue_alloc;
4265                 }
4266                 vsi->msix_intr = ret;
4267                 vsi->nb_msix = 1;
4268         } else {
4269                 vsi->msix_intr = 0;
4270                 vsi->nb_msix = 0;
4271         }
4272
4273         /* Add VSI */
4274         if (type == I40E_VSI_MAIN) {
4275                 /* For main VSI, no need to add since it's default one */
4276                 vsi->uplink_seid = pf->mac_seid;
4277                 vsi->seid = pf->main_vsi_seid;
4278                 /* Bind queues with specific MSIX interrupt */
4279                 /**
4280                  * Needs 2 interrupt at least, one for misc cause which will
4281                  * enabled from OS side, Another for queues binding the
4282                  * interrupt from device side only.
4283                  */
4284
4285                 /* Get default VSI parameters from hardware */
4286                 memset(&ctxt, 0, sizeof(ctxt));
4287                 ctxt.seid = vsi->seid;
4288                 ctxt.pf_num = hw->pf_id;
4289                 ctxt.uplink_seid = vsi->uplink_seid;
4290                 ctxt.vf_num = 0;
4291                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4292                 if (ret != I40E_SUCCESS) {
4293                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4294                         goto fail_msix_alloc;
4295                 }
4296                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4297                         sizeof(struct i40e_aqc_vsi_properties_data));
4298                 vsi->vsi_id = ctxt.vsi_number;
4299                 vsi->info.valid_sections = 0;
4300
4301                 /* Configure tc, enabled TC0 only */
4302                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4303                         I40E_SUCCESS) {
4304                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4305                         goto fail_msix_alloc;
4306                 }
4307
4308                 /* TC, queue mapping */
4309                 memset(&ctxt, 0, sizeof(ctxt));
4310                 vsi->info.valid_sections |=
4311                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4312                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4313                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4314                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4315                         sizeof(struct i40e_aqc_vsi_properties_data));
4316                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4317                                                 I40E_DEFAULT_TCMAP);
4318                 if (ret != I40E_SUCCESS) {
4319                         PMD_DRV_LOG(ERR, "Failed to configure "
4320                                     "TC queue mapping");
4321                         goto fail_msix_alloc;
4322                 }
4323                 ctxt.seid = vsi->seid;
4324                 ctxt.pf_num = hw->pf_id;
4325                 ctxt.uplink_seid = vsi->uplink_seid;
4326                 ctxt.vf_num = 0;
4327
4328                 /* Update VSI parameters */
4329                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4330                 if (ret != I40E_SUCCESS) {
4331                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4332                         goto fail_msix_alloc;
4333                 }
4334
4335                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4336                                                 sizeof(vsi->info.tc_mapping));
4337                 (void)rte_memcpy(&vsi->info.queue_mapping,
4338                                 &ctxt.info.queue_mapping,
4339                         sizeof(vsi->info.queue_mapping));
4340                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4341                 vsi->info.valid_sections = 0;
4342
4343                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4344                                 ETH_ADDR_LEN);
4345
4346                 /**
4347                  * Updating default filter settings are necessary to prevent
4348                  * reception of tagged packets.
4349                  * Some old firmware configurations load a default macvlan
4350                  * filter which accepts both tagged and untagged packets.
4351                  * The updating is to use a normal filter instead if needed.
4352                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4353                  * The firmware with correct configurations load the default
4354                  * macvlan filter which is expected and cannot be removed.
4355                  */
4356                 i40e_update_default_filter_setting(vsi);
4357                 i40e_config_qinq(hw, vsi);
4358         } else if (type == I40E_VSI_SRIOV) {
4359                 memset(&ctxt, 0, sizeof(ctxt));
4360                 /**
4361                  * For other VSI, the uplink_seid equals to uplink VSI's
4362                  * uplink_seid since they share same VEB
4363                  */
4364                 if (uplink_vsi == NULL)
4365                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4366                 else
4367                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4368                 ctxt.pf_num = hw->pf_id;
4369                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4370                 ctxt.uplink_seid = vsi->uplink_seid;
4371                 ctxt.connection_type = 0x1;
4372                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4373
4374                 /* Use the VEB configuration if FW >= v5.0 */
4375                 if (hw->aq.fw_maj_ver >= 5) {
4376                         /* Configure switch ID */
4377                         ctxt.info.valid_sections |=
4378                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4379                         ctxt.info.switch_id =
4380                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4381                 }
4382
4383                 /* Configure port/vlan */
4384                 ctxt.info.valid_sections |=
4385                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4386                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4387                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4388                                                 I40E_DEFAULT_TCMAP);
4389                 if (ret != I40E_SUCCESS) {
4390                         PMD_DRV_LOG(ERR, "Failed to configure "
4391                                     "TC queue mapping");
4392                         goto fail_msix_alloc;
4393                 }
4394                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4395                 ctxt.info.valid_sections |=
4396                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4397                 /**
4398                  * Since VSI is not created yet, only configure parameter,
4399                  * will add vsi below.
4400                  */
4401
4402                 i40e_config_qinq(hw, vsi);
4403         } else if (type == I40E_VSI_VMDQ2) {
4404                 memset(&ctxt, 0, sizeof(ctxt));
4405                 /*
4406                  * For other VSI, the uplink_seid equals to uplink VSI's
4407                  * uplink_seid since they share same VEB
4408                  */
4409                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4410                 ctxt.pf_num = hw->pf_id;
4411                 ctxt.vf_num = 0;
4412                 ctxt.uplink_seid = vsi->uplink_seid;
4413                 ctxt.connection_type = 0x1;
4414                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4415
4416                 ctxt.info.valid_sections |=
4417                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4418                 /* user_param carries flag to enable loop back */
4419                 if (user_param) {
4420                         ctxt.info.switch_id =
4421                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4422                         ctxt.info.switch_id |=
4423                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4424                 }
4425
4426                 /* Configure port/vlan */
4427                 ctxt.info.valid_sections |=
4428                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4429                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4430                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4431                                                 I40E_DEFAULT_TCMAP);
4432                 if (ret != I40E_SUCCESS) {
4433                         PMD_DRV_LOG(ERR, "Failed to configure "
4434                                         "TC queue mapping");
4435                         goto fail_msix_alloc;
4436                 }
4437                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4438                 ctxt.info.valid_sections |=
4439                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4440         } else if (type == I40E_VSI_FDIR) {
4441                 memset(&ctxt, 0, sizeof(ctxt));
4442                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4443                 ctxt.pf_num = hw->pf_id;
4444                 ctxt.vf_num = 0;
4445                 ctxt.uplink_seid = vsi->uplink_seid;
4446                 ctxt.connection_type = 0x1;     /* regular data port */
4447                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4448                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4449                                                 I40E_DEFAULT_TCMAP);
4450                 if (ret != I40E_SUCCESS) {
4451                         PMD_DRV_LOG(ERR, "Failed to configure "
4452                                         "TC queue mapping.");
4453                         goto fail_msix_alloc;
4454                 }
4455                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4456                 ctxt.info.valid_sections |=
4457                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4458         } else {
4459                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4460                 goto fail_msix_alloc;
4461         }
4462
4463         if (vsi->type != I40E_VSI_MAIN) {
4464                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4465                 if (ret != I40E_SUCCESS) {
4466                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4467                                     hw->aq.asq_last_status);
4468                         goto fail_msix_alloc;
4469                 }
4470                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4471                 vsi->info.valid_sections = 0;
4472                 vsi->seid = ctxt.seid;
4473                 vsi->vsi_id = ctxt.vsi_number;
4474                 vsi->sib_vsi_list.vsi = vsi;
4475                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4476                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4477                                           &vsi->sib_vsi_list, list);
4478                 } else {
4479                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4480                                           &vsi->sib_vsi_list, list);
4481                 }
4482         }
4483
4484         /* MAC/VLAN configuration */
4485         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4486         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4487
4488         ret = i40e_vsi_add_mac(vsi, &filter);
4489         if (ret != I40E_SUCCESS) {
4490                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4491                 goto fail_msix_alloc;
4492         }
4493
4494         /* Get VSI BW information */
4495         i40e_vsi_get_bw_config(vsi);
4496         return vsi;
4497 fail_msix_alloc:
4498         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4499 fail_queue_alloc:
4500         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4501 fail_mem:
4502         rte_free(vsi);
4503         return NULL;
4504 }
4505
4506 /* Configure vlan filter on or off */
4507 int
4508 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4509 {
4510         int i, num;
4511         struct i40e_mac_filter *f;
4512         struct i40e_mac_filter_info *mac_filter;
4513         enum rte_mac_filter_type desired_filter;
4514         int ret = I40E_SUCCESS;
4515
4516         if (on) {
4517                 /* Filter to match MAC and VLAN */
4518                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4519         } else {
4520                 /* Filter to match only MAC */
4521                 desired_filter = RTE_MAC_PERFECT_MATCH;
4522         }
4523
4524         num = vsi->mac_num;
4525
4526         mac_filter = rte_zmalloc("mac_filter_info_data",
4527                                  num * sizeof(*mac_filter), 0);
4528         if (mac_filter == NULL) {
4529                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4530                 return I40E_ERR_NO_MEMORY;
4531         }
4532
4533         i = 0;
4534
4535         /* Remove all existing mac */
4536         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4537                 mac_filter[i] = f->mac_info;
4538                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4539                 if (ret) {
4540                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4541                                     on ? "enable" : "disable");
4542                         goto DONE;
4543                 }
4544                 i++;
4545         }
4546
4547         /* Override with new filter */
4548         for (i = 0; i < num; i++) {
4549                 mac_filter[i].filter_type = desired_filter;
4550                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4551                 if (ret) {
4552                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4553                                     on ? "enable" : "disable");
4554                         goto DONE;
4555                 }
4556         }
4557
4558 DONE:
4559         rte_free(mac_filter);
4560         return ret;
4561 }
4562
4563 /* Configure vlan stripping on or off */
4564 int
4565 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4566 {
4567         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4568         struct i40e_vsi_context ctxt;
4569         uint8_t vlan_flags;
4570         int ret = I40E_SUCCESS;
4571
4572         /* Check if it has been already on or off */
4573         if (vsi->info.valid_sections &
4574                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4575                 if (on) {
4576                         if ((vsi->info.port_vlan_flags &
4577                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4578                                 return 0; /* already on */
4579                 } else {
4580                         if ((vsi->info.port_vlan_flags &
4581                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4582                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4583                                 return 0; /* already off */
4584                 }
4585         }
4586
4587         if (on)
4588                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4589         else
4590                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4591         vsi->info.valid_sections =
4592                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4593         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4594         vsi->info.port_vlan_flags |= vlan_flags;
4595         ctxt.seid = vsi->seid;
4596         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4597         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4598         if (ret)
4599                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4600                             on ? "enable" : "disable");
4601
4602         return ret;
4603 }
4604
4605 static int
4606 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4607 {
4608         struct rte_eth_dev_data *data = dev->data;
4609         int ret;
4610         int mask = 0;
4611
4612         /* Apply vlan offload setting */
4613         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4614         i40e_vlan_offload_set(dev, mask);
4615
4616         /* Apply double-vlan setting, not implemented yet */
4617
4618         /* Apply pvid setting */
4619         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4620                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4621         if (ret)
4622                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4623
4624         return ret;
4625 }
4626
4627 static int
4628 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4629 {
4630         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4631
4632         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4633 }
4634
4635 static int
4636 i40e_update_flow_control(struct i40e_hw *hw)
4637 {
4638 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4639         struct i40e_link_status link_status;
4640         uint32_t rxfc = 0, txfc = 0, reg;
4641         uint8_t an_info;
4642         int ret;
4643
4644         memset(&link_status, 0, sizeof(link_status));
4645         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4646         if (ret != I40E_SUCCESS) {
4647                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4648                 goto write_reg; /* Disable flow control */
4649         }
4650
4651         an_info = hw->phy.link_info.an_info;
4652         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4653                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4654                 ret = I40E_ERR_NOT_READY;
4655                 goto write_reg; /* Disable flow control */
4656         }
4657         /**
4658          * If link auto negotiation is enabled, flow control needs to
4659          * be configured according to it
4660          */
4661         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4662         case I40E_LINK_PAUSE_RXTX:
4663                 rxfc = 1;
4664                 txfc = 1;
4665                 hw->fc.current_mode = I40E_FC_FULL;
4666                 break;
4667         case I40E_AQ_LINK_PAUSE_RX:
4668                 rxfc = 1;
4669                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4670                 break;
4671         case I40E_AQ_LINK_PAUSE_TX:
4672                 txfc = 1;
4673                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4674                 break;
4675         default:
4676                 hw->fc.current_mode = I40E_FC_NONE;
4677                 break;
4678         }
4679
4680 write_reg:
4681         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4682                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4683         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4684         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4685         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4686         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4687
4688         return ret;
4689 }
4690
4691 /* PF setup */
4692 static int
4693 i40e_pf_setup(struct i40e_pf *pf)
4694 {
4695         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4696         struct i40e_filter_control_settings settings;
4697         struct i40e_vsi *vsi;
4698         int ret;
4699
4700         /* Clear all stats counters */
4701         pf->offset_loaded = FALSE;
4702         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4703         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4704
4705         ret = i40e_pf_get_switch_config(pf);
4706         if (ret != I40E_SUCCESS) {
4707                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4708                 return ret;
4709         }
4710         if (pf->flags & I40E_FLAG_FDIR) {
4711                 /* make queue allocated first, let FDIR use queue pair 0*/
4712                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4713                 if (ret != I40E_FDIR_QUEUE_ID) {
4714                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4715                                     " ret =%d", ret);
4716                         pf->flags &= ~I40E_FLAG_FDIR;
4717                 }
4718         }
4719         /*  main VSI setup */
4720         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4721         if (!vsi) {
4722                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4723                 return I40E_ERR_NOT_READY;
4724         }
4725         pf->main_vsi = vsi;
4726
4727         /* Configure filter control */
4728         memset(&settings, 0, sizeof(settings));
4729         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4730                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4731         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4732                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4733         else {
4734                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4735                                                 hw->func_caps.rss_table_size);
4736                 return I40E_ERR_PARAM;
4737         }
4738         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4739                         "size: %u\n", hw->func_caps.rss_table_size);
4740         pf->hash_lut_size = hw->func_caps.rss_table_size;
4741
4742         /* Enable ethtype and macvlan filters */
4743         settings.enable_ethtype = TRUE;
4744         settings.enable_macvlan = TRUE;
4745         ret = i40e_set_filter_control(hw, &settings);
4746         if (ret)
4747                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4748                                                                 ret);
4749
4750         /* Update flow control according to the auto negotiation */
4751         i40e_update_flow_control(hw);
4752
4753         return I40E_SUCCESS;
4754 }
4755
4756 int
4757 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4758 {
4759         uint32_t reg;
4760         uint16_t j;
4761
4762         /**
4763          * Set or clear TX Queue Disable flags,
4764          * which is required by hardware.
4765          */
4766         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4767         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4768
4769         /* Wait until the request is finished */
4770         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4771                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4772                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4773                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4774                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4775                                                         & 0x1))) {
4776                         break;
4777                 }
4778         }
4779         if (on) {
4780                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4781                         return I40E_SUCCESS; /* already on, skip next steps */
4782
4783                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4784                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4785         } else {
4786                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4787                         return I40E_SUCCESS; /* already off, skip next steps */
4788                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4789         }
4790         /* Write the register */
4791         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4792         /* Check the result */
4793         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4794                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4795                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4796                 if (on) {
4797                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4798                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4799                                 break;
4800                 } else {
4801                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4802                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4803                                 break;
4804                 }
4805         }
4806         /* Check if it is timeout */
4807         if (j >= I40E_CHK_Q_ENA_COUNT) {
4808                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4809                             (on ? "enable" : "disable"), q_idx);
4810                 return I40E_ERR_TIMEOUT;
4811         }
4812
4813         return I40E_SUCCESS;
4814 }
4815
4816 /* Swith on or off the tx queues */
4817 static int
4818 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4819 {
4820         struct rte_eth_dev_data *dev_data = pf->dev_data;
4821         struct i40e_tx_queue *txq;
4822         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4823         uint16_t i;
4824         int ret;
4825
4826         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4827                 txq = dev_data->tx_queues[i];
4828                 /* Don't operate the queue if not configured or
4829                  * if starting only per queue */
4830                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4831                         continue;
4832                 if (on)
4833                         ret = i40e_dev_tx_queue_start(dev, i);
4834                 else
4835                         ret = i40e_dev_tx_queue_stop(dev, i);
4836                 if ( ret != I40E_SUCCESS)
4837                         return ret;
4838         }
4839
4840         return I40E_SUCCESS;
4841 }
4842
4843 int
4844 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4845 {
4846         uint32_t reg;
4847         uint16_t j;
4848
4849         /* Wait until the request is finished */
4850         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4851                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4852                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4853                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4854                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4855                         break;
4856         }
4857
4858         if (on) {
4859                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4860                         return I40E_SUCCESS; /* Already on, skip next steps */
4861                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4862         } else {
4863                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4864                         return I40E_SUCCESS; /* Already off, skip next steps */
4865                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4866         }
4867
4868         /* Write the register */
4869         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4870         /* Check the result */
4871         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4872                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4873                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4874                 if (on) {
4875                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4876                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4877                                 break;
4878                 } else {
4879                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4880                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4881                                 break;
4882                 }
4883         }
4884
4885         /* Check if it is timeout */
4886         if (j >= I40E_CHK_Q_ENA_COUNT) {
4887                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4888                             (on ? "enable" : "disable"), q_idx);
4889                 return I40E_ERR_TIMEOUT;
4890         }
4891
4892         return I40E_SUCCESS;
4893 }
4894 /* Switch on or off the rx queues */
4895 static int
4896 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4897 {
4898         struct rte_eth_dev_data *dev_data = pf->dev_data;
4899         struct i40e_rx_queue *rxq;
4900         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4901         uint16_t i;
4902         int ret;
4903
4904         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4905                 rxq = dev_data->rx_queues[i];
4906                 /* Don't operate the queue if not configured or
4907                  * if starting only per queue */
4908                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4909                         continue;
4910                 if (on)
4911                         ret = i40e_dev_rx_queue_start(dev, i);
4912                 else
4913                         ret = i40e_dev_rx_queue_stop(dev, i);
4914                 if (ret != I40E_SUCCESS)
4915                         return ret;
4916         }
4917
4918         return I40E_SUCCESS;
4919 }
4920
4921 /* Switch on or off all the rx/tx queues */
4922 int
4923 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4924 {
4925         int ret;
4926
4927         if (on) {
4928                 /* enable rx queues before enabling tx queues */
4929                 ret = i40e_dev_switch_rx_queues(pf, on);
4930                 if (ret) {
4931                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4932                         return ret;
4933                 }
4934                 ret = i40e_dev_switch_tx_queues(pf, on);
4935         } else {
4936                 /* Stop tx queues before stopping rx queues */
4937                 ret = i40e_dev_switch_tx_queues(pf, on);
4938                 if (ret) {
4939                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4940                         return ret;
4941                 }
4942                 ret = i40e_dev_switch_rx_queues(pf, on);
4943         }
4944
4945         return ret;
4946 }
4947
4948 /* Initialize VSI for TX */
4949 static int
4950 i40e_dev_tx_init(struct i40e_pf *pf)
4951 {
4952         struct rte_eth_dev_data *data = pf->dev_data;
4953         uint16_t i;
4954         uint32_t ret = I40E_SUCCESS;
4955         struct i40e_tx_queue *txq;
4956
4957         for (i = 0; i < data->nb_tx_queues; i++) {
4958                 txq = data->tx_queues[i];
4959                 if (!txq || !txq->q_set)
4960                         continue;
4961                 ret = i40e_tx_queue_init(txq);
4962                 if (ret != I40E_SUCCESS)
4963                         break;
4964         }
4965         if (ret == I40E_SUCCESS)
4966                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4967                                      ->eth_dev);
4968
4969         return ret;
4970 }
4971
4972 /* Initialize VSI for RX */
4973 static int
4974 i40e_dev_rx_init(struct i40e_pf *pf)
4975 {
4976         struct rte_eth_dev_data *data = pf->dev_data;
4977         int ret = I40E_SUCCESS;
4978         uint16_t i;
4979         struct i40e_rx_queue *rxq;
4980
4981         i40e_pf_config_mq_rx(pf);
4982         for (i = 0; i < data->nb_rx_queues; i++) {
4983                 rxq = data->rx_queues[i];
4984                 if (!rxq || !rxq->q_set)
4985                         continue;
4986
4987                 ret = i40e_rx_queue_init(rxq);
4988                 if (ret != I40E_SUCCESS) {
4989                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4990                                     "initialization");
4991                         break;
4992                 }
4993         }
4994         if (ret == I40E_SUCCESS)
4995                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4996                                      ->eth_dev);
4997
4998         return ret;
4999 }
5000
5001 static int
5002 i40e_dev_rxtx_init(struct i40e_pf *pf)
5003 {
5004         int err;
5005
5006         err = i40e_dev_tx_init(pf);
5007         if (err) {
5008                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5009                 return err;
5010         }
5011         err = i40e_dev_rx_init(pf);
5012         if (err) {
5013                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5014                 return err;
5015         }
5016
5017         return err;
5018 }
5019
5020 static int
5021 i40e_vmdq_setup(struct rte_eth_dev *dev)
5022 {
5023         struct rte_eth_conf *conf = &dev->data->dev_conf;
5024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5025         int i, err, conf_vsis, j, loop;
5026         struct i40e_vsi *vsi;
5027         struct i40e_vmdq_info *vmdq_info;
5028         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5029         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5030
5031         /*
5032          * Disable interrupt to avoid message from VF. Furthermore, it will
5033          * avoid race condition in VSI creation/destroy.
5034          */
5035         i40e_pf_disable_irq0(hw);
5036
5037         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5038                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5039                 return -ENOTSUP;
5040         }
5041
5042         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5043         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5044                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5045                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5046                         pf->max_nb_vmdq_vsi);
5047                 return -ENOTSUP;
5048         }
5049
5050         if (pf->vmdq != NULL) {
5051                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5052                 return 0;
5053         }
5054
5055         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5056                                 sizeof(*vmdq_info) * conf_vsis, 0);
5057
5058         if (pf->vmdq == NULL) {
5059                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5060                 return -ENOMEM;
5061         }
5062
5063         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5064
5065         /* Create VMDQ VSI */
5066         for (i = 0; i < conf_vsis; i++) {
5067                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5068                                 vmdq_conf->enable_loop_back);
5069                 if (vsi == NULL) {
5070                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5071                         err = -1;
5072                         goto err_vsi_setup;
5073                 }
5074                 vmdq_info = &pf->vmdq[i];
5075                 vmdq_info->pf = pf;
5076                 vmdq_info->vsi = vsi;
5077         }
5078         pf->nb_cfg_vmdq_vsi = conf_vsis;
5079
5080         /* Configure Vlan */
5081         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5082         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5083                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5084                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5085                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5086                                         vmdq_conf->pool_map[i].vlan_id, j);
5087
5088                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5089                                                 vmdq_conf->pool_map[i].vlan_id);
5090                                 if (err) {
5091                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5092                                         err = -1;
5093                                         goto err_vsi_setup;
5094                                 }
5095                         }
5096                 }
5097         }
5098
5099         i40e_pf_enable_irq0(hw);
5100
5101         return 0;
5102
5103 err_vsi_setup:
5104         for (i = 0; i < conf_vsis; i++)
5105                 if (pf->vmdq[i].vsi == NULL)
5106                         break;
5107                 else
5108                         i40e_vsi_release(pf->vmdq[i].vsi);
5109
5110         rte_free(pf->vmdq);
5111         pf->vmdq = NULL;
5112         i40e_pf_enable_irq0(hw);
5113         return err;
5114 }
5115
5116 static void
5117 i40e_stat_update_32(struct i40e_hw *hw,
5118                    uint32_t reg,
5119                    bool offset_loaded,
5120                    uint64_t *offset,
5121                    uint64_t *stat)
5122 {
5123         uint64_t new_data;
5124
5125         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5126         if (!offset_loaded)
5127                 *offset = new_data;
5128
5129         if (new_data >= *offset)
5130                 *stat = (uint64_t)(new_data - *offset);
5131         else
5132                 *stat = (uint64_t)((new_data +
5133                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5134 }
5135
5136 static void
5137 i40e_stat_update_48(struct i40e_hw *hw,
5138                    uint32_t hireg,
5139                    uint32_t loreg,
5140                    bool offset_loaded,
5141                    uint64_t *offset,
5142                    uint64_t *stat)
5143 {
5144         uint64_t new_data;
5145
5146         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5147         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5148                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5149
5150         if (!offset_loaded)
5151                 *offset = new_data;
5152
5153         if (new_data >= *offset)
5154                 *stat = new_data - *offset;
5155         else
5156                 *stat = (uint64_t)((new_data +
5157                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5158
5159         *stat &= I40E_48_BIT_MASK;
5160 }
5161
5162 /* Disable IRQ0 */
5163 void
5164 i40e_pf_disable_irq0(struct i40e_hw *hw)
5165 {
5166         /* Disable all interrupt types */
5167         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5168         I40E_WRITE_FLUSH(hw);
5169 }
5170
5171 /* Enable IRQ0 */
5172 void
5173 i40e_pf_enable_irq0(struct i40e_hw *hw)
5174 {
5175         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5176                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5177                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5178                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5179         I40E_WRITE_FLUSH(hw);
5180 }
5181
5182 static void
5183 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5184 {
5185         /* read pending request and disable first */
5186         i40e_pf_disable_irq0(hw);
5187         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5188         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5189                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5190
5191         if (no_queue)
5192                 /* Link no queues with irq0 */
5193                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5194                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5195 }
5196
5197 static void
5198 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5199 {
5200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5202         int i;
5203         uint16_t abs_vf_id;
5204         uint32_t index, offset, val;
5205
5206         if (!pf->vfs)
5207                 return;
5208         /**
5209          * Try to find which VF trigger a reset, use absolute VF id to access
5210          * since the reg is global register.
5211          */
5212         for (i = 0; i < pf->vf_num; i++) {
5213                 abs_vf_id = hw->func_caps.vf_base_id + i;
5214                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5215                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5216                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5217                 /* VFR event occured */
5218                 if (val & (0x1 << offset)) {
5219                         int ret;
5220
5221                         /* Clear the event first */
5222                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5223                                                         (0x1 << offset));
5224                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5225                         /**
5226                          * Only notify a VF reset event occured,
5227                          * don't trigger another SW reset
5228                          */
5229                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5230                         if (ret != I40E_SUCCESS)
5231                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5232                 }
5233         }
5234 }
5235
5236 static void
5237 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5238 {
5239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5240         struct i40e_arq_event_info info;
5241         uint16_t pending, opcode;
5242         int ret;
5243
5244         info.buf_len = I40E_AQ_BUF_SZ;
5245         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5246         if (!info.msg_buf) {
5247                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5248                 return;
5249         }
5250
5251         pending = 1;
5252         while (pending) {
5253                 ret = i40e_clean_arq_element(hw, &info, &pending);
5254
5255                 if (ret != I40E_SUCCESS) {
5256                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5257                                     "aq_err: %u", hw->aq.asq_last_status);
5258                         break;
5259                 }
5260                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5261
5262                 switch (opcode) {
5263                 case i40e_aqc_opc_send_msg_to_pf:
5264                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5265                         i40e_pf_host_handle_vf_msg(dev,
5266                                         rte_le_to_cpu_16(info.desc.retval),
5267                                         rte_le_to_cpu_32(info.desc.cookie_high),
5268                                         rte_le_to_cpu_32(info.desc.cookie_low),
5269                                         info.msg_buf,
5270                                         info.msg_len);
5271                         break;
5272                 default:
5273                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5274                                     opcode);
5275                         break;
5276                 }
5277         }
5278         rte_free(info.msg_buf);
5279 }
5280
5281 /*
5282  * Interrupt handler is registered as the alarm callback for handling LSC
5283  * interrupt in a definite of time, in order to wait the NIC into a stable
5284  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5285  * no need for link down interrupt.
5286  */
5287 static void
5288 i40e_dev_interrupt_delayed_handler(void *param)
5289 {
5290         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5291         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5292         uint32_t icr0;
5293
5294         /* read interrupt causes again */
5295         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5296
5297 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5298         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5299                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5300         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5301                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5302         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5303                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5304         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5305                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5306         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5307                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5308                                                                 "state\n");
5309         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5310                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5311         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5312                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5313 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5314
5315         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5316                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5317                 i40e_dev_handle_vfr_event(dev);
5318         }
5319         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5320                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5321                 i40e_dev_handle_aq_msg(dev);
5322         }
5323
5324         /* handle the link up interrupt in an alarm callback */
5325         i40e_dev_link_update(dev, 0);
5326         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5327
5328         i40e_pf_enable_irq0(hw);
5329         rte_intr_enable(&(dev->pci_dev->intr_handle));
5330 }
5331
5332 /**
5333  * Interrupt handler triggered by NIC  for handling
5334  * specific interrupt.
5335  *
5336  * @param handle
5337  *  Pointer to interrupt handle.
5338  * @param param
5339  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5340  *
5341  * @return
5342  *  void
5343  */
5344 static void
5345 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5346                            void *param)
5347 {
5348         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5350         uint32_t icr0;
5351
5352         /* Disable interrupt */
5353         i40e_pf_disable_irq0(hw);
5354
5355         /* read out interrupt causes */
5356         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5357
5358         /* No interrupt event indicated */
5359         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5360                 PMD_DRV_LOG(INFO, "No interrupt event");
5361                 goto done;
5362         }
5363 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5364         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5365                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5366         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5367                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5368         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5369                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5370         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5371                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5372         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5373                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5374         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5375                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5376         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5377                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5378 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5379
5380         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5381                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5382                 i40e_dev_handle_vfr_event(dev);
5383         }
5384         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5385                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5386                 i40e_dev_handle_aq_msg(dev);
5387         }
5388
5389         /* Link Status Change interrupt */
5390         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5391 #define I40E_US_PER_SECOND 1000000
5392                 struct rte_eth_link link;
5393
5394                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5395                 memset(&link, 0, sizeof(link));
5396                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5397                 i40e_dev_link_update(dev, 0);
5398
5399                 /*
5400                  * For link up interrupt, it needs to wait 1 second to let the
5401                  * hardware be a stable state. Otherwise several consecutive
5402                  * interrupts can be observed.
5403                  * For link down interrupt, no need to wait.
5404                  */
5405                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5406                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5407                         return;
5408                 else
5409                         _rte_eth_dev_callback_process(dev,
5410                                 RTE_ETH_EVENT_INTR_LSC);
5411         }
5412
5413 done:
5414         /* Enable interrupt */
5415         i40e_pf_enable_irq0(hw);
5416         rte_intr_enable(&(dev->pci_dev->intr_handle));
5417 }
5418
5419 static int
5420 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5421                          struct i40e_macvlan_filter *filter,
5422                          int total)
5423 {
5424         int ele_num, ele_buff_size;
5425         int num, actual_num, i;
5426         uint16_t flags;
5427         int ret = I40E_SUCCESS;
5428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5429         struct i40e_aqc_add_macvlan_element_data *req_list;
5430
5431         if (filter == NULL  || total == 0)
5432                 return I40E_ERR_PARAM;
5433         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5434         ele_buff_size = hw->aq.asq_buf_size;
5435
5436         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5437         if (req_list == NULL) {
5438                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5439                 return I40E_ERR_NO_MEMORY;
5440         }
5441
5442         num = 0;
5443         do {
5444                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5445                 memset(req_list, 0, ele_buff_size);
5446
5447                 for (i = 0; i < actual_num; i++) {
5448                         (void)rte_memcpy(req_list[i].mac_addr,
5449                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5450                         req_list[i].vlan_tag =
5451                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5452
5453                         switch (filter[num + i].filter_type) {
5454                         case RTE_MAC_PERFECT_MATCH:
5455                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5456                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5457                                 break;
5458                         case RTE_MACVLAN_PERFECT_MATCH:
5459                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5460                                 break;
5461                         case RTE_MAC_HASH_MATCH:
5462                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5463                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5464                                 break;
5465                         case RTE_MACVLAN_HASH_MATCH:
5466                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5467                                 break;
5468                         default:
5469                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5470                                 ret = I40E_ERR_PARAM;
5471                                 goto DONE;
5472                         }
5473
5474                         req_list[i].queue_number = 0;
5475
5476                         req_list[i].flags = rte_cpu_to_le_16(flags);
5477                 }
5478
5479                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5480                                                 actual_num, NULL);
5481                 if (ret != I40E_SUCCESS) {
5482                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5483                         goto DONE;
5484                 }
5485                 num += actual_num;
5486         } while (num < total);
5487
5488 DONE:
5489         rte_free(req_list);
5490         return ret;
5491 }
5492
5493 static int
5494 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5495                             struct i40e_macvlan_filter *filter,
5496                             int total)
5497 {
5498         int ele_num, ele_buff_size;
5499         int num, actual_num, i;
5500         uint16_t flags;
5501         int ret = I40E_SUCCESS;
5502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5503         struct i40e_aqc_remove_macvlan_element_data *req_list;
5504
5505         if (filter == NULL  || total == 0)
5506                 return I40E_ERR_PARAM;
5507
5508         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5509         ele_buff_size = hw->aq.asq_buf_size;
5510
5511         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5512         if (req_list == NULL) {
5513                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5514                 return I40E_ERR_NO_MEMORY;
5515         }
5516
5517         num = 0;
5518         do {
5519                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5520                 memset(req_list, 0, ele_buff_size);
5521
5522                 for (i = 0; i < actual_num; i++) {
5523                         (void)rte_memcpy(req_list[i].mac_addr,
5524                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5525                         req_list[i].vlan_tag =
5526                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5527
5528                         switch (filter[num + i].filter_type) {
5529                         case RTE_MAC_PERFECT_MATCH:
5530                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5531                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5532                                 break;
5533                         case RTE_MACVLAN_PERFECT_MATCH:
5534                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5535                                 break;
5536                         case RTE_MAC_HASH_MATCH:
5537                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5538                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5539                                 break;
5540                         case RTE_MACVLAN_HASH_MATCH:
5541                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5542                                 break;
5543                         default:
5544                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5545                                 ret = I40E_ERR_PARAM;
5546                                 goto DONE;
5547                         }
5548                         req_list[i].flags = rte_cpu_to_le_16(flags);
5549                 }
5550
5551                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5552                                                 actual_num, NULL);
5553                 if (ret != I40E_SUCCESS) {
5554                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5555                         goto DONE;
5556                 }
5557                 num += actual_num;
5558         } while (num < total);
5559
5560 DONE:
5561         rte_free(req_list);
5562         return ret;
5563 }
5564
5565 /* Find out specific MAC filter */
5566 static struct i40e_mac_filter *
5567 i40e_find_mac_filter(struct i40e_vsi *vsi,
5568                          struct ether_addr *macaddr)
5569 {
5570         struct i40e_mac_filter *f;
5571
5572         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5573                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5574                         return f;
5575         }
5576
5577         return NULL;
5578 }
5579
5580 static bool
5581 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5582                          uint16_t vlan_id)
5583 {
5584         uint32_t vid_idx, vid_bit;
5585
5586         if (vlan_id > ETH_VLAN_ID_MAX)
5587                 return 0;
5588
5589         vid_idx = I40E_VFTA_IDX(vlan_id);
5590         vid_bit = I40E_VFTA_BIT(vlan_id);
5591
5592         if (vsi->vfta[vid_idx] & vid_bit)
5593                 return 1;
5594         else
5595                 return 0;
5596 }
5597
5598 static void
5599 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5600                          uint16_t vlan_id, bool on)
5601 {
5602         uint32_t vid_idx, vid_bit;
5603
5604         if (vlan_id > ETH_VLAN_ID_MAX)
5605                 return;
5606
5607         vid_idx = I40E_VFTA_IDX(vlan_id);
5608         vid_bit = I40E_VFTA_BIT(vlan_id);
5609
5610         if (on)
5611                 vsi->vfta[vid_idx] |= vid_bit;
5612         else
5613                 vsi->vfta[vid_idx] &= ~vid_bit;
5614 }
5615
5616 /**
5617  * Find all vlan options for specific mac addr,
5618  * return with actual vlan found.
5619  */
5620 static inline int
5621 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5622                            struct i40e_macvlan_filter *mv_f,
5623                            int num, struct ether_addr *addr)
5624 {
5625         int i;
5626         uint32_t j, k;
5627
5628         /**
5629          * Not to use i40e_find_vlan_filter to decrease the loop time,
5630          * although the code looks complex.
5631           */
5632         if (num < vsi->vlan_num)
5633                 return I40E_ERR_PARAM;
5634
5635         i = 0;
5636         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5637                 if (vsi->vfta[j]) {
5638                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5639                                 if (vsi->vfta[j] & (1 << k)) {
5640                                         if (i > num - 1) {
5641                                                 PMD_DRV_LOG(ERR, "vlan number "
5642                                                             "not match");
5643                                                 return I40E_ERR_PARAM;
5644                                         }
5645                                         (void)rte_memcpy(&mv_f[i].macaddr,
5646                                                         addr, ETH_ADDR_LEN);
5647                                         mv_f[i].vlan_id =
5648                                                 j * I40E_UINT32_BIT_SIZE + k;
5649                                         i++;
5650                                 }
5651                         }
5652                 }
5653         }
5654         return I40E_SUCCESS;
5655 }
5656
5657 static inline int
5658 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5659                            struct i40e_macvlan_filter *mv_f,
5660                            int num,
5661                            uint16_t vlan)
5662 {
5663         int i = 0;
5664         struct i40e_mac_filter *f;
5665
5666         if (num < vsi->mac_num)
5667                 return I40E_ERR_PARAM;
5668
5669         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5670                 if (i > num - 1) {
5671                         PMD_DRV_LOG(ERR, "buffer number not match");
5672                         return I40E_ERR_PARAM;
5673                 }
5674                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5675                                 ETH_ADDR_LEN);
5676                 mv_f[i].vlan_id = vlan;
5677                 mv_f[i].filter_type = f->mac_info.filter_type;
5678                 i++;
5679         }
5680
5681         return I40E_SUCCESS;
5682 }
5683
5684 static int
5685 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5686 {
5687         int i, num;
5688         struct i40e_mac_filter *f;
5689         struct i40e_macvlan_filter *mv_f;
5690         int ret = I40E_SUCCESS;
5691
5692         if (vsi == NULL || vsi->mac_num == 0)
5693                 return I40E_ERR_PARAM;
5694
5695         /* Case that no vlan is set */
5696         if (vsi->vlan_num == 0)
5697                 num = vsi->mac_num;
5698         else
5699                 num = vsi->mac_num * vsi->vlan_num;
5700
5701         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5702         if (mv_f == NULL) {
5703                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5704                 return I40E_ERR_NO_MEMORY;
5705         }
5706
5707         i = 0;
5708         if (vsi->vlan_num == 0) {
5709                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5710                         (void)rte_memcpy(&mv_f[i].macaddr,
5711                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5712                         mv_f[i].vlan_id = 0;
5713                         i++;
5714                 }
5715         } else {
5716                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5717                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5718                                         vsi->vlan_num, &f->mac_info.mac_addr);
5719                         if (ret != I40E_SUCCESS)
5720                                 goto DONE;
5721                         i += vsi->vlan_num;
5722                 }
5723         }
5724
5725         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5726 DONE:
5727         rte_free(mv_f);
5728
5729         return ret;
5730 }
5731
5732 int
5733 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5734 {
5735         struct i40e_macvlan_filter *mv_f;
5736         int mac_num;
5737         int ret = I40E_SUCCESS;
5738
5739         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5740                 return I40E_ERR_PARAM;
5741
5742         /* If it's already set, just return */
5743         if (i40e_find_vlan_filter(vsi,vlan))
5744                 return I40E_SUCCESS;
5745
5746         mac_num = vsi->mac_num;
5747
5748         if (mac_num == 0) {
5749                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5750                 return I40E_ERR_PARAM;
5751         }
5752
5753         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5754
5755         if (mv_f == NULL) {
5756                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5757                 return I40E_ERR_NO_MEMORY;
5758         }
5759
5760         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5761
5762         if (ret != I40E_SUCCESS)
5763                 goto DONE;
5764
5765         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5766
5767         if (ret != I40E_SUCCESS)
5768                 goto DONE;
5769
5770         i40e_set_vlan_filter(vsi, vlan, 1);
5771
5772         vsi->vlan_num++;
5773         ret = I40E_SUCCESS;
5774 DONE:
5775         rte_free(mv_f);
5776         return ret;
5777 }
5778
5779 int
5780 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5781 {
5782         struct i40e_macvlan_filter *mv_f;
5783         int mac_num;
5784         int ret = I40E_SUCCESS;
5785
5786         /**
5787          * Vlan 0 is the generic filter for untagged packets
5788          * and can't be removed.
5789          */
5790         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5791                 return I40E_ERR_PARAM;
5792
5793         /* If can't find it, just return */
5794         if (!i40e_find_vlan_filter(vsi, vlan))
5795                 return I40E_ERR_PARAM;
5796
5797         mac_num = vsi->mac_num;
5798
5799         if (mac_num == 0) {
5800                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5801                 return I40E_ERR_PARAM;
5802         }
5803
5804         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5805
5806         if (mv_f == NULL) {
5807                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5808                 return I40E_ERR_NO_MEMORY;
5809         }
5810
5811         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5812
5813         if (ret != I40E_SUCCESS)
5814                 goto DONE;
5815
5816         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5817
5818         if (ret != I40E_SUCCESS)
5819                 goto DONE;
5820
5821         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5822         if (vsi->vlan_num == 1) {
5823                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5824                 if (ret != I40E_SUCCESS)
5825                         goto DONE;
5826
5827                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5828                 if (ret != I40E_SUCCESS)
5829                         goto DONE;
5830         }
5831
5832         i40e_set_vlan_filter(vsi, vlan, 0);
5833
5834         vsi->vlan_num--;
5835         ret = I40E_SUCCESS;
5836 DONE:
5837         rte_free(mv_f);
5838         return ret;
5839 }
5840
5841 int
5842 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5843 {
5844         struct i40e_mac_filter *f;
5845         struct i40e_macvlan_filter *mv_f;
5846         int i, vlan_num = 0;
5847         int ret = I40E_SUCCESS;
5848
5849         /* If it's add and we've config it, return */
5850         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5851         if (f != NULL)
5852                 return I40E_SUCCESS;
5853         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5854                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5855
5856                 /**
5857                  * If vlan_num is 0, that's the first time to add mac,
5858                  * set mask for vlan_id 0.
5859                  */
5860                 if (vsi->vlan_num == 0) {
5861                         i40e_set_vlan_filter(vsi, 0, 1);
5862                         vsi->vlan_num = 1;
5863                 }
5864                 vlan_num = vsi->vlan_num;
5865         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5866                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5867                 vlan_num = 1;
5868
5869         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5870         if (mv_f == NULL) {
5871                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5872                 return I40E_ERR_NO_MEMORY;
5873         }
5874
5875         for (i = 0; i < vlan_num; i++) {
5876                 mv_f[i].filter_type = mac_filter->filter_type;
5877                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5878                                 ETH_ADDR_LEN);
5879         }
5880
5881         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5882                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5883                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5884                                         &mac_filter->mac_addr);
5885                 if (ret != I40E_SUCCESS)
5886                         goto DONE;
5887         }
5888
5889         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5890         if (ret != I40E_SUCCESS)
5891                 goto DONE;
5892
5893         /* Add the mac addr into mac list */
5894         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5895         if (f == NULL) {
5896                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5897                 ret = I40E_ERR_NO_MEMORY;
5898                 goto DONE;
5899         }
5900         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5901                         ETH_ADDR_LEN);
5902         f->mac_info.filter_type = mac_filter->filter_type;
5903         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5904         vsi->mac_num++;
5905
5906         ret = I40E_SUCCESS;
5907 DONE:
5908         rte_free(mv_f);
5909
5910         return ret;
5911 }
5912
5913 int
5914 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5915 {
5916         struct i40e_mac_filter *f;
5917         struct i40e_macvlan_filter *mv_f;
5918         int i, vlan_num;
5919         enum rte_mac_filter_type filter_type;
5920         int ret = I40E_SUCCESS;
5921
5922         /* Can't find it, return an error */
5923         f = i40e_find_mac_filter(vsi, addr);
5924         if (f == NULL)
5925                 return I40E_ERR_PARAM;
5926
5927         vlan_num = vsi->vlan_num;
5928         filter_type = f->mac_info.filter_type;
5929         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5930                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5931                 if (vlan_num == 0) {
5932                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5933                         return I40E_ERR_PARAM;
5934                 }
5935         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5936                         filter_type == RTE_MAC_HASH_MATCH)
5937                 vlan_num = 1;
5938
5939         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5940         if (mv_f == NULL) {
5941                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5942                 return I40E_ERR_NO_MEMORY;
5943         }
5944
5945         for (i = 0; i < vlan_num; i++) {
5946                 mv_f[i].filter_type = filter_type;
5947                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5948                                 ETH_ADDR_LEN);
5949         }
5950         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5951                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5952                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5953                 if (ret != I40E_SUCCESS)
5954                         goto DONE;
5955         }
5956
5957         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5958         if (ret != I40E_SUCCESS)
5959                 goto DONE;
5960
5961         /* Remove the mac addr into mac list */
5962         TAILQ_REMOVE(&vsi->mac_list, f, next);
5963         rte_free(f);
5964         vsi->mac_num--;
5965
5966         ret = I40E_SUCCESS;
5967 DONE:
5968         rte_free(mv_f);
5969         return ret;
5970 }
5971
5972 /* Configure hash enable flags for RSS */
5973 uint64_t
5974 i40e_config_hena(uint64_t flags)
5975 {
5976         uint64_t hena = 0;
5977
5978         if (!flags)
5979                 return hena;
5980
5981         if (flags & ETH_RSS_FRAG_IPV4)
5982                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5983         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5984                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5985         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5986                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5987         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5988                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5989         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5990                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5991         if (flags & ETH_RSS_FRAG_IPV6)
5992                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5993         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5994                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5995         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5996                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5997         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5998                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5999         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6000                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6001         if (flags & ETH_RSS_L2_PAYLOAD)
6002                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6003
6004         return hena;
6005 }
6006
6007 /* Parse the hash enable flags */
6008 uint64_t
6009 i40e_parse_hena(uint64_t flags)
6010 {
6011         uint64_t rss_hf = 0;
6012
6013         if (!flags)
6014                 return rss_hf;
6015         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6016                 rss_hf |= ETH_RSS_FRAG_IPV4;
6017         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6018                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6019         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6020                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6021         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6022                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6023         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6024                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6025         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6026                 rss_hf |= ETH_RSS_FRAG_IPV6;
6027         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6028                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6029         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6030                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6031         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6032                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6033         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6034                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6035         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6036                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6037
6038         return rss_hf;
6039 }
6040
6041 /* Disable RSS */
6042 static void
6043 i40e_pf_disable_rss(struct i40e_pf *pf)
6044 {
6045         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6046         uint64_t hena;
6047
6048         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6049         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6050         hena &= ~I40E_RSS_HENA_ALL;
6051         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6052         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6053         I40E_WRITE_FLUSH(hw);
6054 }
6055
6056 static int
6057 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6058 {
6059         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6060         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6061         int ret = 0;
6062
6063         if (!key || key_len == 0) {
6064                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6065                 return 0;
6066         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6067                 sizeof(uint32_t)) {
6068                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6069                 return -EINVAL;
6070         }
6071
6072         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6073                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6074                         (struct i40e_aqc_get_set_rss_key_data *)key;
6075
6076                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6077                 if (ret)
6078                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6079                                      "via AQ");
6080         } else {
6081                 uint32_t *hash_key = (uint32_t *)key;
6082                 uint16_t i;
6083
6084                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6085                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6086                 I40E_WRITE_FLUSH(hw);
6087         }
6088
6089         return ret;
6090 }
6091
6092 static int
6093 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6094 {
6095         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6096         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6097         int ret;
6098
6099         if (!key || !key_len)
6100                 return -EINVAL;
6101
6102         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6103                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6104                         (struct i40e_aqc_get_set_rss_key_data *)key);
6105                 if (ret) {
6106                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6107                         return ret;
6108                 }
6109         } else {
6110                 uint32_t *key_dw = (uint32_t *)key;
6111                 uint16_t i;
6112
6113                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6114                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6115         }
6116         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6117
6118         return 0;
6119 }
6120
6121 static int
6122 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6123 {
6124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6125         uint64_t rss_hf;
6126         uint64_t hena;
6127         int ret;
6128
6129         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6130                                rss_conf->rss_key_len);
6131         if (ret)
6132                 return ret;
6133
6134         rss_hf = rss_conf->rss_hf;
6135         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6136         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6137         hena &= ~I40E_RSS_HENA_ALL;
6138         hena |= i40e_config_hena(rss_hf);
6139         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6140         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6141         I40E_WRITE_FLUSH(hw);
6142
6143         return 0;
6144 }
6145
6146 static int
6147 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6148                          struct rte_eth_rss_conf *rss_conf)
6149 {
6150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6152         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6153         uint64_t hena;
6154
6155         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6156         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6157         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6158                 if (rss_hf != 0) /* Enable RSS */
6159                         return -EINVAL;
6160                 return 0; /* Nothing to do */
6161         }
6162         /* RSS enabled */
6163         if (rss_hf == 0) /* Disable RSS */
6164                 return -EINVAL;
6165
6166         return i40e_hw_rss_hash_set(pf, rss_conf);
6167 }
6168
6169 static int
6170 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6171                            struct rte_eth_rss_conf *rss_conf)
6172 {
6173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6175         uint64_t hena;
6176
6177         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6178                          &rss_conf->rss_key_len);
6179
6180         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6181         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6182         rss_conf->rss_hf = i40e_parse_hena(hena);
6183
6184         return 0;
6185 }
6186
6187 static int
6188 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6189 {
6190         switch (filter_type) {
6191         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6192                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6193                 break;
6194         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6195                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6196                 break;
6197         case RTE_TUNNEL_FILTER_IMAC_TENID:
6198                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6199                 break;
6200         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6201                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6202                 break;
6203         case ETH_TUNNEL_FILTER_IMAC:
6204                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6205                 break;
6206         case ETH_TUNNEL_FILTER_OIP:
6207                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6208                 break;
6209         case ETH_TUNNEL_FILTER_IIP:
6210                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6211                 break;
6212         default:
6213                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6214                 return -EINVAL;
6215         }
6216
6217         return 0;
6218 }
6219
6220 static int
6221 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6222                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6223                         uint8_t add)
6224 {
6225         uint16_t ip_type;
6226         uint32_t ipv4_addr;
6227         uint8_t i, tun_type = 0;
6228         /* internal varialbe to convert ipv6 byte order */
6229         uint32_t convert_ipv6[4];
6230         int val, ret = 0;
6231         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6232         struct i40e_vsi *vsi = pf->main_vsi;
6233         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6234         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6235
6236         cld_filter = rte_zmalloc("tunnel_filter",
6237                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6238                 0);
6239
6240         if (NULL == cld_filter) {
6241                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6242                 return -EINVAL;
6243         }
6244         pfilter = cld_filter;
6245
6246         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6247         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6248
6249         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6250         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6251                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6252                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6253                 rte_memcpy(&pfilter->ipaddr.v4.data,
6254                                 &rte_cpu_to_le_32(ipv4_addr),
6255                                 sizeof(pfilter->ipaddr.v4.data));
6256         } else {
6257                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6258                 for (i = 0; i < 4; i++) {
6259                         convert_ipv6[i] =
6260                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6261                 }
6262                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6263                                 sizeof(pfilter->ipaddr.v6.data));
6264         }
6265
6266         /* check tunneled type */
6267         switch (tunnel_filter->tunnel_type) {
6268         case RTE_TUNNEL_TYPE_VXLAN:
6269                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6270                 break;
6271         case RTE_TUNNEL_TYPE_NVGRE:
6272                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6273                 break;
6274         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6275                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6276                 break;
6277         default:
6278                 /* Other tunnel types is not supported. */
6279                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6280                 rte_free(cld_filter);
6281                 return -EINVAL;
6282         }
6283
6284         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6285                                                 &pfilter->flags);
6286         if (val < 0) {
6287                 rte_free(cld_filter);
6288                 return -EINVAL;
6289         }
6290
6291         pfilter->flags |= rte_cpu_to_le_16(
6292                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6293                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6294         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6295         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6296
6297         if (add)
6298                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6299         else
6300                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6301                                                 cld_filter, 1);
6302
6303         rte_free(cld_filter);
6304         return ret;
6305 }
6306
6307 static int
6308 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6309 {
6310         uint8_t i;
6311
6312         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6313                 if (pf->vxlan_ports[i] == port)
6314                         return i;
6315         }
6316
6317         return -1;
6318 }
6319
6320 static int
6321 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6322 {
6323         int  idx, ret;
6324         uint8_t filter_idx;
6325         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6326
6327         idx = i40e_get_vxlan_port_idx(pf, port);
6328
6329         /* Check if port already exists */
6330         if (idx >= 0) {
6331                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6332                 return -EINVAL;
6333         }
6334
6335         /* Now check if there is space to add the new port */
6336         idx = i40e_get_vxlan_port_idx(pf, 0);
6337         if (idx < 0) {
6338                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6339                         "not adding port %d", port);
6340                 return -ENOSPC;
6341         }
6342
6343         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6344                                         &filter_idx, NULL);
6345         if (ret < 0) {
6346                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6347                 return -1;
6348         }
6349
6350         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6351                          port,  filter_idx);
6352
6353         /* New port: add it and mark its index in the bitmap */
6354         pf->vxlan_ports[idx] = port;
6355         pf->vxlan_bitmap |= (1 << idx);
6356
6357         if (!(pf->flags & I40E_FLAG_VXLAN))
6358                 pf->flags |= I40E_FLAG_VXLAN;
6359
6360         return 0;
6361 }
6362
6363 static int
6364 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6365 {
6366         int idx;
6367         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6368
6369         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6370                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6371                 return -EINVAL;
6372         }
6373
6374         idx = i40e_get_vxlan_port_idx(pf, port);
6375
6376         if (idx < 0) {
6377                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6378                 return -EINVAL;
6379         }
6380
6381         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6382                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6383                 return -1;
6384         }
6385
6386         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6387                         port, idx);
6388
6389         pf->vxlan_ports[idx] = 0;
6390         pf->vxlan_bitmap &= ~(1 << idx);
6391
6392         if (!pf->vxlan_bitmap)
6393                 pf->flags &= ~I40E_FLAG_VXLAN;
6394
6395         return 0;
6396 }
6397
6398 /* Add UDP tunneling port */
6399 static int
6400 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6401                              struct rte_eth_udp_tunnel *udp_tunnel)
6402 {
6403         int ret = 0;
6404         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6405
6406         if (udp_tunnel == NULL)
6407                 return -EINVAL;
6408
6409         switch (udp_tunnel->prot_type) {
6410         case RTE_TUNNEL_TYPE_VXLAN:
6411                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6412                 break;
6413
6414         case RTE_TUNNEL_TYPE_GENEVE:
6415         case RTE_TUNNEL_TYPE_TEREDO:
6416                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6417                 ret = -1;
6418                 break;
6419
6420         default:
6421                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6422                 ret = -1;
6423                 break;
6424         }
6425
6426         return ret;
6427 }
6428
6429 /* Remove UDP tunneling port */
6430 static int
6431 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6432                              struct rte_eth_udp_tunnel *udp_tunnel)
6433 {
6434         int ret = 0;
6435         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6436
6437         if (udp_tunnel == NULL)
6438                 return -EINVAL;
6439
6440         switch (udp_tunnel->prot_type) {
6441         case RTE_TUNNEL_TYPE_VXLAN:
6442                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6443                 break;
6444         case RTE_TUNNEL_TYPE_GENEVE:
6445         case RTE_TUNNEL_TYPE_TEREDO:
6446                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6447                 ret = -1;
6448                 break;
6449         default:
6450                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6451                 ret = -1;
6452                 break;
6453         }
6454
6455         return ret;
6456 }
6457
6458 /* Calculate the maximum number of contiguous PF queues that are configured */
6459 static int
6460 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6461 {
6462         struct rte_eth_dev_data *data = pf->dev_data;
6463         int i, num;
6464         struct i40e_rx_queue *rxq;
6465
6466         num = 0;
6467         for (i = 0; i < pf->lan_nb_qps; i++) {
6468                 rxq = data->rx_queues[i];
6469                 if (rxq && rxq->q_set)
6470                         num++;
6471                 else
6472                         break;
6473         }
6474
6475         return num;
6476 }
6477
6478 /* Configure RSS */
6479 static int
6480 i40e_pf_config_rss(struct i40e_pf *pf)
6481 {
6482         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6483         struct rte_eth_rss_conf rss_conf;
6484         uint32_t i, lut = 0;
6485         uint16_t j, num;
6486
6487         /*
6488          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6489          * It's necessary to calulate the actual PF queues that are configured.
6490          */
6491         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6492                 num = i40e_pf_calc_configured_queues_num(pf);
6493         else
6494                 num = pf->dev_data->nb_rx_queues;
6495
6496         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6497         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6498                         num);
6499
6500         if (num == 0) {
6501                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6502                 return -ENOTSUP;
6503         }
6504
6505         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6506                 if (j == num)
6507                         j = 0;
6508                 lut = (lut << 8) | (j & ((0x1 <<
6509                         hw->func_caps.rss_table_entry_width) - 1));
6510                 if ((i & 3) == 3)
6511                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6512         }
6513
6514         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6515         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6516                 i40e_pf_disable_rss(pf);
6517                 return 0;
6518         }
6519         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6520                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6521                 /* Random default keys */
6522                 static uint32_t rss_key_default[] = {0x6b793944,
6523                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6524                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6525                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6526
6527                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6528                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6529                                                         sizeof(uint32_t);
6530         }
6531
6532         return i40e_hw_rss_hash_set(pf, &rss_conf);
6533 }
6534
6535 static int
6536 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6537                                struct rte_eth_tunnel_filter_conf *filter)
6538 {
6539         if (pf == NULL || filter == NULL) {
6540                 PMD_DRV_LOG(ERR, "Invalid parameter");
6541                 return -EINVAL;
6542         }
6543
6544         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6545                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6546                 return -EINVAL;
6547         }
6548
6549         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6550                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6551                 return -EINVAL;
6552         }
6553
6554         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6555                 (is_zero_ether_addr(&filter->outer_mac))) {
6556                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6557                 return -EINVAL;
6558         }
6559
6560         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6561                 (is_zero_ether_addr(&filter->inner_mac))) {
6562                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6563                 return -EINVAL;
6564         }
6565
6566         return 0;
6567 }
6568
6569 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6570 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6571 static int
6572 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6573 {
6574         uint32_t val, reg;
6575         int ret = -EINVAL;
6576
6577         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6578         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6579
6580         if (len == 3) {
6581                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6582         } else if (len == 4) {
6583                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6584         } else {
6585                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6586                 return ret;
6587         }
6588
6589         if (reg != val) {
6590                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6591                                                    reg, NULL);
6592                 if (ret != 0)
6593                         return ret;
6594         } else {
6595                 ret = 0;
6596         }
6597         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6598                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6599
6600         return ret;
6601 }
6602
6603 static int
6604 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6605 {
6606         int ret = -EINVAL;
6607
6608         if (!hw || !cfg)
6609                 return -EINVAL;
6610
6611         switch (cfg->cfg_type) {
6612         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6613                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6614                 break;
6615         default:
6616                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6617                 break;
6618         }
6619
6620         return ret;
6621 }
6622
6623 static int
6624 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6625                                enum rte_filter_op filter_op,
6626                                void *arg)
6627 {
6628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6629         int ret = I40E_ERR_PARAM;
6630
6631         switch (filter_op) {
6632         case RTE_ETH_FILTER_SET:
6633                 ret = i40e_dev_global_config_set(hw,
6634                         (struct rte_eth_global_cfg *)arg);
6635                 break;
6636         default:
6637                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6638                 break;
6639         }
6640
6641         return ret;
6642 }
6643
6644 static int
6645 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6646                           enum rte_filter_op filter_op,
6647                           void *arg)
6648 {
6649         struct rte_eth_tunnel_filter_conf *filter;
6650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6651         int ret = I40E_SUCCESS;
6652
6653         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6654
6655         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6656                 return I40E_ERR_PARAM;
6657
6658         switch (filter_op) {
6659         case RTE_ETH_FILTER_NOP:
6660                 if (!(pf->flags & I40E_FLAG_VXLAN))
6661                         ret = I40E_NOT_SUPPORTED;
6662                 break;
6663         case RTE_ETH_FILTER_ADD:
6664                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6665                 break;
6666         case RTE_ETH_FILTER_DELETE:
6667                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6668                 break;
6669         default:
6670                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6671                 ret = I40E_ERR_PARAM;
6672                 break;
6673         }
6674
6675         return ret;
6676 }
6677
6678 static int
6679 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6680 {
6681         int ret = 0;
6682         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6683
6684         /* RSS setup */
6685         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6686                 ret = i40e_pf_config_rss(pf);
6687         else
6688                 i40e_pf_disable_rss(pf);
6689
6690         return ret;
6691 }
6692
6693 /* Get the symmetric hash enable configurations per port */
6694 static void
6695 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6696 {
6697         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6698
6699         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6700 }
6701
6702 /* Set the symmetric hash enable configurations per port */
6703 static void
6704 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6705 {
6706         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6707
6708         if (enable > 0) {
6709                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6710                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6711                                                         "been enabled");
6712                         return;
6713                 }
6714                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6715         } else {
6716                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6717                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6718                                                         "been disabled");
6719                         return;
6720                 }
6721                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6722         }
6723         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6724         I40E_WRITE_FLUSH(hw);
6725 }
6726
6727 /*
6728  * Get global configurations of hash function type and symmetric hash enable
6729  * per flow type (pctype). Note that global configuration means it affects all
6730  * the ports on the same NIC.
6731  */
6732 static int
6733 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6734                                    struct rte_eth_hash_global_conf *g_cfg)
6735 {
6736         uint32_t reg, mask = I40E_FLOW_TYPES;
6737         uint16_t i;
6738         enum i40e_filter_pctype pctype;
6739
6740         memset(g_cfg, 0, sizeof(*g_cfg));
6741         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6742         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6743                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6744         else
6745                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6746         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6747                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6748
6749         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6750                 if (!(mask & (1UL << i)))
6751                         continue;
6752                 mask &= ~(1UL << i);
6753                 /* Bit set indicats the coresponding flow type is supported */
6754                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6755                 pctype = i40e_flowtype_to_pctype(i);
6756                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6757                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6758                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6759         }
6760
6761         return 0;
6762 }
6763
6764 static int
6765 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6766 {
6767         uint32_t i;
6768         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6769
6770         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6771                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6772                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6773                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6774                                                 g_cfg->hash_func);
6775                 return -EINVAL;
6776         }
6777
6778         /*
6779          * As i40e supports less than 32 flow types, only first 32 bits need to
6780          * be checked.
6781          */
6782         mask0 = g_cfg->valid_bit_mask[0];
6783         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6784                 if (i == 0) {
6785                         /* Check if any unsupported flow type configured */
6786                         if ((mask0 | i40e_mask) ^ i40e_mask)
6787                                 goto mask_err;
6788                 } else {
6789                         if (g_cfg->valid_bit_mask[i])
6790                                 goto mask_err;
6791                 }
6792         }
6793
6794         return 0;
6795
6796 mask_err:
6797         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6798
6799         return -EINVAL;
6800 }
6801
6802 /*
6803  * Set global configurations of hash function type and symmetric hash enable
6804  * per flow type (pctype). Note any modifying global configuration will affect
6805  * all the ports on the same NIC.
6806  */
6807 static int
6808 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6809                                    struct rte_eth_hash_global_conf *g_cfg)
6810 {
6811         int ret;
6812         uint16_t i;
6813         uint32_t reg;
6814         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6815         enum i40e_filter_pctype pctype;
6816
6817         /* Check the input parameters */
6818         ret = i40e_hash_global_config_check(g_cfg);
6819         if (ret < 0)
6820                 return ret;
6821
6822         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6823                 if (!(mask0 & (1UL << i)))
6824                         continue;
6825                 mask0 &= ~(1UL << i);
6826                 pctype = i40e_flowtype_to_pctype(i);
6827                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6828                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6829                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6830         }
6831
6832         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6833         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6834                 /* Toeplitz */
6835                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6836                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6837                                                                 "Toeplitz");
6838                         goto out;
6839                 }
6840                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6841         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6842                 /* Simple XOR */
6843                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6844                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6845                                                         "Simple XOR");
6846                         goto out;
6847                 }
6848                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6849         } else
6850                 /* Use the default, and keep it as it is */
6851                 goto out;
6852
6853         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6854
6855 out:
6856         I40E_WRITE_FLUSH(hw);
6857
6858         return 0;
6859 }
6860
6861 /**
6862  * Valid input sets for hash and flow director filters per PCTYPE
6863  */
6864 static uint64_t
6865 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6866                 enum rte_filter_type filter)
6867 {
6868         uint64_t valid;
6869
6870         static const uint64_t valid_hash_inset_table[] = {
6871                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6872                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6873                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6874                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6875                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6876                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6877                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6878                         I40E_INSET_FLEX_PAYLOAD,
6879                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6880                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6881                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6882                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6883                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6884                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6885                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6886                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6887                         I40E_INSET_FLEX_PAYLOAD,
6888                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6889                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6890                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6891                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6892                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6893                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6894                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6895                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6896                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6897                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6898                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6899                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6900                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6901                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6902                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6903                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6904                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6905                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6906                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6907                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6908                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6909                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6910                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6911                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6912                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6913                         I40E_INSET_FLEX_PAYLOAD,
6914                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6915                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6916                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6917                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6918                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6919                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6920                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6921                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6922                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6923                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6924                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6925                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6926                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6927                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6928                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6929                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6930                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6931                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6932                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6933                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6934                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6935                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6936                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6937                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6938                         I40E_INSET_FLEX_PAYLOAD,
6939                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6940                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6941                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6942                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6943                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6944                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6945                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6946                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6947                         I40E_INSET_FLEX_PAYLOAD,
6948                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6949                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6950                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6951                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6952                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6953                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6954                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6955                         I40E_INSET_FLEX_PAYLOAD,
6956                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6957                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6958                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6959                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6960                         I40E_INSET_FLEX_PAYLOAD,
6961         };
6962
6963         /**
6964          * Flow director supports only fields defined in
6965          * union rte_eth_fdir_flow.
6966          */
6967         static const uint64_t valid_fdir_inset_table[] = {
6968                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6969                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6970                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6971                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6972                 I40E_INSET_IPV4_TTL,
6973                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6974                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6975                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6976                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6977                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6978                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6979                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6980                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6981                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6982                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6983                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6984                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6985                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6986                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6987                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6988                 I40E_INSET_SCTP_VT,
6989                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6990                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6991                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6992                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6993                 I40E_INSET_IPV4_TTL,
6994                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6995                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6996                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6997                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6998                 I40E_INSET_IPV6_HOP_LIMIT,
6999                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7000                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7001                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7002                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7003                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7004                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7005                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7006                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7007                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7008                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7009                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7010                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7011                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7012                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7013                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7014                 I40E_INSET_SCTP_VT,
7015                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7016                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7017                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7018                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7019                 I40E_INSET_IPV6_HOP_LIMIT,
7020                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7021                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7022                 I40E_INSET_LAST_ETHER_TYPE,
7023         };
7024
7025         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7026                 return 0;
7027         if (filter == RTE_ETH_FILTER_HASH)
7028                 valid = valid_hash_inset_table[pctype];
7029         else
7030                 valid = valid_fdir_inset_table[pctype];
7031
7032         return valid;
7033 }
7034
7035 /**
7036  * Validate if the input set is allowed for a specific PCTYPE
7037  */
7038 static int
7039 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7040                 enum rte_filter_type filter, uint64_t inset)
7041 {
7042         uint64_t valid;
7043
7044         valid = i40e_get_valid_input_set(pctype, filter);
7045         if (inset & (~valid))
7046                 return -EINVAL;
7047
7048         return 0;
7049 }
7050
7051 /* default input set fields combination per pctype */
7052 static uint64_t
7053 i40e_get_default_input_set(uint16_t pctype)
7054 {
7055         static const uint64_t default_inset_table[] = {
7056                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7057                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7058                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7059                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7060                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7061                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7062                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7063                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7064                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7065                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7066                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7067                         I40E_INSET_SCTP_VT,
7068                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7069                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7070                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7071                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7072                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7073                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7074                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7075                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7076                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7077                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7078                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7079                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7080                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7081                         I40E_INSET_SCTP_VT,
7082                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7083                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7084                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7085                         I40E_INSET_LAST_ETHER_TYPE,
7086         };
7087
7088         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7089                 return 0;
7090
7091         return default_inset_table[pctype];
7092 }
7093
7094 /**
7095  * Parse the input set from index to logical bit masks
7096  */
7097 static int
7098 i40e_parse_input_set(uint64_t *inset,
7099                      enum i40e_filter_pctype pctype,
7100                      enum rte_eth_input_set_field *field,
7101                      uint16_t size)
7102 {
7103         uint16_t i, j;
7104         int ret = -EINVAL;
7105
7106         static const struct {
7107                 enum rte_eth_input_set_field field;
7108                 uint64_t inset;
7109         } inset_convert_table[] = {
7110                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7111                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7112                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7113                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7114                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7115                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7116                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7117                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7118                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7119                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7120                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7121                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7122                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7123                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7124                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7125                         I40E_INSET_IPV6_NEXT_HDR},
7126                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7127                         I40E_INSET_IPV6_HOP_LIMIT},
7128                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7129                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7130                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7131                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7132                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7133                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7134                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7135                         I40E_INSET_SCTP_VT},
7136                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7137                         I40E_INSET_TUNNEL_DMAC},
7138                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7139                         I40E_INSET_VLAN_TUNNEL},
7140                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7141                         I40E_INSET_TUNNEL_ID},
7142                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7143                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7144                         I40E_INSET_FLEX_PAYLOAD_W1},
7145                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7146                         I40E_INSET_FLEX_PAYLOAD_W2},
7147                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7148                         I40E_INSET_FLEX_PAYLOAD_W3},
7149                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7150                         I40E_INSET_FLEX_PAYLOAD_W4},
7151                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7152                         I40E_INSET_FLEX_PAYLOAD_W5},
7153                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7154                         I40E_INSET_FLEX_PAYLOAD_W6},
7155                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7156                         I40E_INSET_FLEX_PAYLOAD_W7},
7157                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7158                         I40E_INSET_FLEX_PAYLOAD_W8},
7159         };
7160
7161         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7162                 return ret;
7163
7164         /* Only one item allowed for default or all */
7165         if (size == 1) {
7166                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7167                         *inset = i40e_get_default_input_set(pctype);
7168                         return 0;
7169                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7170                         *inset = I40E_INSET_NONE;
7171                         return 0;
7172                 }
7173         }
7174
7175         for (i = 0, *inset = 0; i < size; i++) {
7176                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7177                         if (field[i] == inset_convert_table[j].field) {
7178                                 *inset |= inset_convert_table[j].inset;
7179                                 break;
7180                         }
7181                 }
7182
7183                 /* It contains unsupported input set, return immediately */
7184                 if (j == RTE_DIM(inset_convert_table))
7185                         return ret;
7186         }
7187
7188         return 0;
7189 }
7190
7191 /**
7192  * Translate the input set from bit masks to register aware bit masks
7193  * and vice versa
7194  */
7195 static uint64_t
7196 i40e_translate_input_set_reg(uint64_t input)
7197 {
7198         uint64_t val = 0;
7199         uint16_t i;
7200
7201         static const struct {
7202                 uint64_t inset;
7203                 uint64_t inset_reg;
7204         } inset_map[] = {
7205                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7206                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7207                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7208                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7209                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7210                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7211                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7212                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7213                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7214                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7215                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7216                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7217                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7218                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7219                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7220                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7221                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7222                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7223                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7224                 {I40E_INSET_TUNNEL_DMAC,
7225                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7226                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7227                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7228                 {I40E_INSET_TUNNEL_SRC_PORT,
7229                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7230                 {I40E_INSET_TUNNEL_DST_PORT,
7231                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7232                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7233                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7234                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7235                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7236                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7237                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7238                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7239                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7240                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7241         };
7242
7243         if (input == 0)
7244                 return val;
7245
7246         /* Translate input set to register aware inset */
7247         for (i = 0; i < RTE_DIM(inset_map); i++) {
7248                 if (input & inset_map[i].inset)
7249                         val |= inset_map[i].inset_reg;
7250         }
7251
7252         return val;
7253 }
7254
7255 static int
7256 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7257 {
7258         uint8_t i, idx = 0;
7259         uint64_t inset_need_mask = inset;
7260
7261         static const struct {
7262                 uint64_t inset;
7263                 uint32_t mask;
7264         } inset_mask_map[] = {
7265                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7266                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7267                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7268                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7269                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7270                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7271                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7272                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7273         };
7274
7275         if (!inset || !mask || !nb_elem)
7276                 return 0;
7277
7278         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7279                 /* Clear the inset bit, if no MASK is required,
7280                  * for example proto + ttl
7281                  */
7282                 if ((inset & inset_mask_map[i].inset) ==
7283                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7284                         inset_need_mask &= ~inset_mask_map[i].inset;
7285                 if (!inset_need_mask)
7286                         return 0;
7287         }
7288         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7289                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7290                     inset_mask_map[i].inset) {
7291                         if (idx >= nb_elem) {
7292                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7293                                 return -EINVAL;
7294                         }
7295                         mask[idx] = inset_mask_map[i].mask;
7296                         idx++;
7297                 }
7298         }
7299
7300         return idx;
7301 }
7302
7303 static void
7304 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7305 {
7306         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7307
7308         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7309         if (reg != val)
7310                 i40e_write_rx_ctl(hw, addr, val);
7311         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7312                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7313 }
7314
7315 static void
7316 i40e_filter_input_set_init(struct i40e_pf *pf)
7317 {
7318         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7319         enum i40e_filter_pctype pctype;
7320         uint64_t input_set, inset_reg;
7321         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7322         int num, i;
7323
7324         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7325              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7326                 if (!I40E_VALID_PCTYPE(pctype))
7327                         continue;
7328                 input_set = i40e_get_default_input_set(pctype);
7329
7330                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7331                                                    I40E_INSET_MASK_NUM_REG);
7332                 if (num < 0)
7333                         return;
7334                 inset_reg = i40e_translate_input_set_reg(input_set);
7335
7336                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7337                                       (uint32_t)(inset_reg & UINT32_MAX));
7338                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7339                                      (uint32_t)((inset_reg >>
7340                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7341                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7342                                       (uint32_t)(inset_reg & UINT32_MAX));
7343                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7344                                      (uint32_t)((inset_reg >>
7345                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7346
7347                 for (i = 0; i < num; i++) {
7348                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7349                                              mask_reg[i]);
7350                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7351                                              mask_reg[i]);
7352                 }
7353                 /*clear unused mask registers of the pctype */
7354                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7355                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7356                                              0);
7357                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7358                                              0);
7359                 }
7360                 I40E_WRITE_FLUSH(hw);
7361
7362                 /* store the default input set */
7363                 pf->hash_input_set[pctype] = input_set;
7364                 pf->fdir.input_set[pctype] = input_set;
7365         }
7366 }
7367
7368 int
7369 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7370                          struct rte_eth_input_set_conf *conf)
7371 {
7372         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7373         enum i40e_filter_pctype pctype;
7374         uint64_t input_set, inset_reg = 0;
7375         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7376         int ret, i, num;
7377
7378         if (!conf) {
7379                 PMD_DRV_LOG(ERR, "Invalid pointer");
7380                 return -EFAULT;
7381         }
7382         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7383             conf->op != RTE_ETH_INPUT_SET_ADD) {
7384                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7385                 return -EINVAL;
7386         }
7387
7388         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7389         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7390                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7391                             conf->flow_type);
7392                 return -EINVAL;
7393         }
7394
7395         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7396                                    conf->inset_size);
7397         if (ret) {
7398                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7399                 return -EINVAL;
7400         }
7401         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7402                                     input_set) != 0) {
7403                 PMD_DRV_LOG(ERR, "Invalid input set");
7404                 return -EINVAL;
7405         }
7406         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7407                 /* get inset value in register */
7408                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7409                 inset_reg <<= I40E_32_BIT_WIDTH;
7410                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7411                 input_set |= pf->hash_input_set[pctype];
7412         }
7413         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7414                                            I40E_INSET_MASK_NUM_REG);
7415         if (num < 0)
7416                 return -EINVAL;
7417
7418         inset_reg |= i40e_translate_input_set_reg(input_set);
7419
7420         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7421                               (uint32_t)(inset_reg & UINT32_MAX));
7422         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7423                              (uint32_t)((inset_reg >>
7424                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7425
7426         for (i = 0; i < num; i++)
7427                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7428                                      mask_reg[i]);
7429         /*clear unused mask registers of the pctype */
7430         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7431                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7432                                      0);
7433         I40E_WRITE_FLUSH(hw);
7434
7435         pf->hash_input_set[pctype] = input_set;
7436         return 0;
7437 }
7438
7439 int
7440 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7441                          struct rte_eth_input_set_conf *conf)
7442 {
7443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7444         enum i40e_filter_pctype pctype;
7445         uint64_t input_set, inset_reg = 0;
7446         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7447         int ret, i, num;
7448
7449         if (!hw || !conf) {
7450                 PMD_DRV_LOG(ERR, "Invalid pointer");
7451                 return -EFAULT;
7452         }
7453         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7454             conf->op != RTE_ETH_INPUT_SET_ADD) {
7455                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7456                 return -EINVAL;
7457         }
7458
7459         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7460         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7461                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7462                             conf->flow_type);
7463                 return -EINVAL;
7464         }
7465         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7466                                    conf->inset_size);
7467         if (ret) {
7468                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7469                 return -EINVAL;
7470         }
7471         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7472                                     input_set) != 0) {
7473                 PMD_DRV_LOG(ERR, "Invalid input set");
7474                 return -EINVAL;
7475         }
7476
7477         /* get inset value in register */
7478         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7479         inset_reg <<= I40E_32_BIT_WIDTH;
7480         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7481
7482         /* Can not change the inset reg for flex payload for fdir,
7483          * it is done by writing I40E_PRTQF_FD_FLXINSET
7484          * in i40e_set_flex_mask_on_pctype.
7485          */
7486         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7487                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7488         else
7489                 input_set |= pf->fdir.input_set[pctype];
7490         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7491                                            I40E_INSET_MASK_NUM_REG);
7492         if (num < 0)
7493                 return -EINVAL;
7494
7495         inset_reg |= i40e_translate_input_set_reg(input_set);
7496
7497         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7498                               (uint32_t)(inset_reg & UINT32_MAX));
7499         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7500                              (uint32_t)((inset_reg >>
7501                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7502
7503         for (i = 0; i < num; i++)
7504                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7505                                      mask_reg[i]);
7506         /*clear unused mask registers of the pctype */
7507         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7508                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7509                                      0);
7510         I40E_WRITE_FLUSH(hw);
7511
7512         pf->fdir.input_set[pctype] = input_set;
7513         return 0;
7514 }
7515
7516 static int
7517 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7518 {
7519         int ret = 0;
7520
7521         if (!hw || !info) {
7522                 PMD_DRV_LOG(ERR, "Invalid pointer");
7523                 return -EFAULT;
7524         }
7525
7526         switch (info->info_type) {
7527         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7528                 i40e_get_symmetric_hash_enable_per_port(hw,
7529                                         &(info->info.enable));
7530                 break;
7531         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7532                 ret = i40e_get_hash_filter_global_config(hw,
7533                                 &(info->info.global_conf));
7534                 break;
7535         default:
7536                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7537                                                         info->info_type);
7538                 ret = -EINVAL;
7539                 break;
7540         }
7541
7542         return ret;
7543 }
7544
7545 static int
7546 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7547 {
7548         int ret = 0;
7549
7550         if (!hw || !info) {
7551                 PMD_DRV_LOG(ERR, "Invalid pointer");
7552                 return -EFAULT;
7553         }
7554
7555         switch (info->info_type) {
7556         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7557                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7558                 break;
7559         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7560                 ret = i40e_set_hash_filter_global_config(hw,
7561                                 &(info->info.global_conf));
7562                 break;
7563         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7564                 ret = i40e_hash_filter_inset_select(hw,
7565                                                &(info->info.input_set_conf));
7566                 break;
7567
7568         default:
7569                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7570                                                         info->info_type);
7571                 ret = -EINVAL;
7572                 break;
7573         }
7574
7575         return ret;
7576 }
7577
7578 /* Operations for hash function */
7579 static int
7580 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7581                       enum rte_filter_op filter_op,
7582                       void *arg)
7583 {
7584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7585         int ret = 0;
7586
7587         switch (filter_op) {
7588         case RTE_ETH_FILTER_NOP:
7589                 break;
7590         case RTE_ETH_FILTER_GET:
7591                 ret = i40e_hash_filter_get(hw,
7592                         (struct rte_eth_hash_filter_info *)arg);
7593                 break;
7594         case RTE_ETH_FILTER_SET:
7595                 ret = i40e_hash_filter_set(hw,
7596                         (struct rte_eth_hash_filter_info *)arg);
7597                 break;
7598         default:
7599                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7600                                                                 filter_op);
7601                 ret = -ENOTSUP;
7602                 break;
7603         }
7604
7605         return ret;
7606 }
7607
7608 /*
7609  * Configure ethertype filter, which can director packet by filtering
7610  * with mac address and ether_type or only ether_type
7611  */
7612 static int
7613 i40e_ethertype_filter_set(struct i40e_pf *pf,
7614                         struct rte_eth_ethertype_filter *filter,
7615                         bool add)
7616 {
7617         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7618         struct i40e_control_filter_stats stats;
7619         uint16_t flags = 0;
7620         int ret;
7621
7622         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7623                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7624                 return -EINVAL;
7625         }
7626         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7627                 filter->ether_type == ETHER_TYPE_IPv6) {
7628                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7629                         " control packet filter.", filter->ether_type);
7630                 return -EINVAL;
7631         }
7632         if (filter->ether_type == ETHER_TYPE_VLAN)
7633                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7634                         " not supported.");
7635
7636         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7637                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7638         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7639                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7640         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7641
7642         memset(&stats, 0, sizeof(stats));
7643         ret = i40e_aq_add_rem_control_packet_filter(hw,
7644                         filter->mac_addr.addr_bytes,
7645                         filter->ether_type, flags,
7646                         pf->main_vsi->seid,
7647                         filter->queue, add, &stats, NULL);
7648
7649         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7650                          " mac_etype_used = %u, etype_used = %u,"
7651                          " mac_etype_free = %u, etype_free = %u\n",
7652                          ret, stats.mac_etype_used, stats.etype_used,
7653                          stats.mac_etype_free, stats.etype_free);
7654         if (ret < 0)
7655                 return -ENOSYS;
7656         return 0;
7657 }
7658
7659 /*
7660  * Handle operations for ethertype filter.
7661  */
7662 static int
7663 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7664                                 enum rte_filter_op filter_op,
7665                                 void *arg)
7666 {
7667         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7668         int ret = 0;
7669
7670         if (filter_op == RTE_ETH_FILTER_NOP)
7671                 return ret;
7672
7673         if (arg == NULL) {
7674                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7675                             filter_op);
7676                 return -EINVAL;
7677         }
7678
7679         switch (filter_op) {
7680         case RTE_ETH_FILTER_ADD:
7681                 ret = i40e_ethertype_filter_set(pf,
7682                         (struct rte_eth_ethertype_filter *)arg,
7683                         TRUE);
7684                 break;
7685         case RTE_ETH_FILTER_DELETE:
7686                 ret = i40e_ethertype_filter_set(pf,
7687                         (struct rte_eth_ethertype_filter *)arg,
7688                         FALSE);
7689                 break;
7690         default:
7691                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7692                 ret = -ENOSYS;
7693                 break;
7694         }
7695         return ret;
7696 }
7697
7698 static int
7699 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7700                      enum rte_filter_type filter_type,
7701                      enum rte_filter_op filter_op,
7702                      void *arg)
7703 {
7704         int ret = 0;
7705
7706         if (dev == NULL)
7707                 return -EINVAL;
7708
7709         switch (filter_type) {
7710         case RTE_ETH_FILTER_NONE:
7711                 /* For global configuration */
7712                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7713                 break;
7714         case RTE_ETH_FILTER_HASH:
7715                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7716                 break;
7717         case RTE_ETH_FILTER_MACVLAN:
7718                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7719                 break;
7720         case RTE_ETH_FILTER_ETHERTYPE:
7721                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7722                 break;
7723         case RTE_ETH_FILTER_TUNNEL:
7724                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7725                 break;
7726         case RTE_ETH_FILTER_FDIR:
7727                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7728                 break;
7729         default:
7730                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7731                                                         filter_type);
7732                 ret = -EINVAL;
7733                 break;
7734         }
7735
7736         return ret;
7737 }
7738
7739 /*
7740  * Check and enable Extended Tag.
7741  * Enabling Extended Tag is important for 40G performance.
7742  */
7743 static void
7744 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7745 {
7746         uint32_t buf = 0;
7747         int ret;
7748
7749         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7750                                       PCI_DEV_CAP_REG);
7751         if (ret < 0) {
7752                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7753                             PCI_DEV_CAP_REG);
7754                 return;
7755         }
7756         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7757                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7758                 return;
7759         }
7760
7761         buf = 0;
7762         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7763                                       PCI_DEV_CTRL_REG);
7764         if (ret < 0) {
7765                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7766                             PCI_DEV_CTRL_REG);
7767                 return;
7768         }
7769         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7770                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7771                 return;
7772         }
7773         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7774         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7775                                        PCI_DEV_CTRL_REG);
7776         if (ret < 0) {
7777                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7778                             PCI_DEV_CTRL_REG);
7779                 return;
7780         }
7781 }
7782
7783 /*
7784  * As some registers wouldn't be reset unless a global hardware reset,
7785  * hardware initialization is needed to put those registers into an
7786  * expected initial state.
7787  */
7788 static void
7789 i40e_hw_init(struct rte_eth_dev *dev)
7790 {
7791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7792
7793         i40e_enable_extended_tag(dev);
7794
7795         /* clear the PF Queue Filter control register */
7796         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7797
7798         /* Disable symmetric hash per port */
7799         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7800 }
7801
7802 enum i40e_filter_pctype
7803 i40e_flowtype_to_pctype(uint16_t flow_type)
7804 {
7805         static const enum i40e_filter_pctype pctype_table[] = {
7806                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7807                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7808                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7809                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7810                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7811                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7812                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7813                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7814                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7815                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7816                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7817                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7818                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7819                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7820                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7821                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7822                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7823                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7824                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7825         };
7826
7827         return pctype_table[flow_type];
7828 }
7829
7830 uint16_t
7831 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7832 {
7833         static const uint16_t flowtype_table[] = {
7834                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7835                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7836                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7837                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7838                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7839                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7840                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7841                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7842                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7843                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7844                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7845                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7846                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7847                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7848                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7849                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7850                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7851                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7852                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7853         };
7854
7855         return flowtype_table[pctype];
7856 }
7857
7858 /*
7859  * On X710, performance number is far from the expectation on recent firmware
7860  * versions; on XL710, performance number is also far from the expectation on
7861  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7862  * mode is enabled and port MAC address is equal to the packet destination MAC
7863  * address. The fix for this issue may not be integrated in the following
7864  * firmware version. So the workaround in software driver is needed. It needs
7865  * to modify the initial values of 3 internal only registers for both X710 and
7866  * XL710. Note that the values for X710 or XL710 could be different, and the
7867  * workaround can be removed when it is fixed in firmware in the future.
7868  */
7869
7870 /* For both X710 and XL710 */
7871 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7872 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7873
7874 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7875 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7876
7877 /* For X710 */
7878 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7879 /* For XL710 */
7880 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7881 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7882
7883 static void
7884 i40e_configure_registers(struct i40e_hw *hw)
7885 {
7886         static struct {
7887                 uint32_t addr;
7888                 uint64_t val;
7889         } reg_table[] = {
7890                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7891                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7892                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7893         };
7894         uint64_t reg;
7895         uint32_t i;
7896         int ret;
7897
7898         for (i = 0; i < RTE_DIM(reg_table); i++) {
7899                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7900                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7901                                 reg_table[i].val =
7902                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7903                         else /* For X710 */
7904                                 reg_table[i].val =
7905                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7906                 }
7907
7908                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7909                                                         &reg, NULL);
7910                 if (ret < 0) {
7911                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7912                                                         reg_table[i].addr);
7913                         break;
7914                 }
7915                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7916                                                 reg_table[i].addr, reg);
7917                 if (reg == reg_table[i].val)
7918                         continue;
7919
7920                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7921                                                 reg_table[i].val, NULL);
7922                 if (ret < 0) {
7923                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7924                                 "address of 0x%"PRIx32, reg_table[i].val,
7925                                                         reg_table[i].addr);
7926                         break;
7927                 }
7928                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7929                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7930         }
7931 }
7932
7933 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7934 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7935 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7936 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7937 static int
7938 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7939 {
7940         uint32_t reg;
7941         int ret;
7942
7943         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7944                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7945                 return -EINVAL;
7946         }
7947
7948         /* Configure for double VLAN RX stripping */
7949         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7950         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7951                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7952                 ret = i40e_aq_debug_write_register(hw,
7953                                                    I40E_VSI_TSR(vsi->vsi_id),
7954                                                    reg, NULL);
7955                 if (ret < 0) {
7956                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7957                                     vsi->vsi_id);
7958                         return I40E_ERR_CONFIG;
7959                 }
7960         }
7961
7962         /* Configure for double VLAN TX insertion */
7963         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7964         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7965                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7966                 ret = i40e_aq_debug_write_register(hw,
7967                                                    I40E_VSI_L2TAGSTXVALID(
7968                                                    vsi->vsi_id), reg, NULL);
7969                 if (ret < 0) {
7970                         PMD_DRV_LOG(ERR, "Failed to update "
7971                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7972                         return I40E_ERR_CONFIG;
7973                 }
7974         }
7975
7976         return 0;
7977 }
7978
7979 /**
7980  * i40e_aq_add_mirror_rule
7981  * @hw: pointer to the hardware structure
7982  * @seid: VEB seid to add mirror rule to
7983  * @dst_id: destination vsi seid
7984  * @entries: Buffer which contains the entities to be mirrored
7985  * @count: number of entities contained in the buffer
7986  * @rule_id:the rule_id of the rule to be added
7987  *
7988  * Add a mirror rule for a given veb.
7989  *
7990  **/
7991 static enum i40e_status_code
7992 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7993                         uint16_t seid, uint16_t dst_id,
7994                         uint16_t rule_type, uint16_t *entries,
7995                         uint16_t count, uint16_t *rule_id)
7996 {
7997         struct i40e_aq_desc desc;
7998         struct i40e_aqc_add_delete_mirror_rule cmd;
7999         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8000                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8001                 &desc.params.raw;
8002         uint16_t buff_len;
8003         enum i40e_status_code status;
8004
8005         i40e_fill_default_direct_cmd_desc(&desc,
8006                                           i40e_aqc_opc_add_mirror_rule);
8007         memset(&cmd, 0, sizeof(cmd));
8008
8009         buff_len = sizeof(uint16_t) * count;
8010         desc.datalen = rte_cpu_to_le_16(buff_len);
8011         if (buff_len > 0)
8012                 desc.flags |= rte_cpu_to_le_16(
8013                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8014         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8015                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8016         cmd.num_entries = rte_cpu_to_le_16(count);
8017         cmd.seid = rte_cpu_to_le_16(seid);
8018         cmd.destination = rte_cpu_to_le_16(dst_id);
8019
8020         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8021         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8022         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8023                          "rule_id = %u"
8024                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8025                          hw->aq.asq_last_status, resp->rule_id,
8026                          resp->mirror_rules_used, resp->mirror_rules_free);
8027         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8028
8029         return status;
8030 }
8031
8032 /**
8033  * i40e_aq_del_mirror_rule
8034  * @hw: pointer to the hardware structure
8035  * @seid: VEB seid to add mirror rule to
8036  * @entries: Buffer which contains the entities to be mirrored
8037  * @count: number of entities contained in the buffer
8038  * @rule_id:the rule_id of the rule to be delete
8039  *
8040  * Delete a mirror rule for a given veb.
8041  *
8042  **/
8043 static enum i40e_status_code
8044 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8045                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8046                 uint16_t count, uint16_t rule_id)
8047 {
8048         struct i40e_aq_desc desc;
8049         struct i40e_aqc_add_delete_mirror_rule cmd;
8050         uint16_t buff_len = 0;
8051         enum i40e_status_code status;
8052         void *buff = NULL;
8053
8054         i40e_fill_default_direct_cmd_desc(&desc,
8055                                           i40e_aqc_opc_delete_mirror_rule);
8056         memset(&cmd, 0, sizeof(cmd));
8057         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8058                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8059                                                           I40E_AQ_FLAG_RD));
8060                 cmd.num_entries = count;
8061                 buff_len = sizeof(uint16_t) * count;
8062                 desc.datalen = rte_cpu_to_le_16(buff_len);
8063                 buff = (void *)entries;
8064         } else
8065                 /* rule id is filled in destination field for deleting mirror rule */
8066                 cmd.destination = rte_cpu_to_le_16(rule_id);
8067
8068         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8069                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8070         cmd.seid = rte_cpu_to_le_16(seid);
8071
8072         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8073         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8074
8075         return status;
8076 }
8077
8078 /**
8079  * i40e_mirror_rule_set
8080  * @dev: pointer to the hardware structure
8081  * @mirror_conf: mirror rule info
8082  * @sw_id: mirror rule's sw_id
8083  * @on: enable/disable
8084  *
8085  * set a mirror rule.
8086  *
8087  **/
8088 static int
8089 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8090                         struct rte_eth_mirror_conf *mirror_conf,
8091                         uint8_t sw_id, uint8_t on)
8092 {
8093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8095         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8096         struct i40e_mirror_rule *parent = NULL;
8097         uint16_t seid, dst_seid, rule_id;
8098         uint16_t i, j = 0;
8099         int ret;
8100
8101         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8102
8103         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8104                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8105                         " without veb or vfs.");
8106                 return -ENOSYS;
8107         }
8108         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8109                 PMD_DRV_LOG(ERR, "mirror table is full.");
8110                 return -ENOSPC;
8111         }
8112         if (mirror_conf->dst_pool > pf->vf_num) {
8113                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8114                                  mirror_conf->dst_pool);
8115                 return -EINVAL;
8116         }
8117
8118         seid = pf->main_vsi->veb->seid;
8119
8120         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8121                 if (sw_id <= it->index) {
8122                         mirr_rule = it;
8123                         break;
8124                 }
8125                 parent = it;
8126         }
8127         if (mirr_rule && sw_id == mirr_rule->index) {
8128                 if (on) {
8129                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8130                         return -EEXIST;
8131                 } else {
8132                         ret = i40e_aq_del_mirror_rule(hw, seid,
8133                                         mirr_rule->rule_type,
8134                                         mirr_rule->entries,
8135                                         mirr_rule->num_entries, mirr_rule->id);
8136                         if (ret < 0) {
8137                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8138                                                    " ret = %d, aq_err = %d.",
8139                                                    ret, hw->aq.asq_last_status);
8140                                 return -ENOSYS;
8141                         }
8142                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8143                         rte_free(mirr_rule);
8144                         pf->nb_mirror_rule--;
8145                         return 0;
8146                 }
8147         } else if (!on) {
8148                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8149                 return -ENOENT;
8150         }
8151
8152         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8153                                 sizeof(struct i40e_mirror_rule) , 0);
8154         if (!mirr_rule) {
8155                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8156                 return I40E_ERR_NO_MEMORY;
8157         }
8158         switch (mirror_conf->rule_type) {
8159         case ETH_MIRROR_VLAN:
8160                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8161                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8162                                 mirr_rule->entries[j] =
8163                                         mirror_conf->vlan.vlan_id[i];
8164                                 j++;
8165                         }
8166                 }
8167                 if (j == 0) {
8168                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8169                         rte_free(mirr_rule);
8170                         return -EINVAL;
8171                 }
8172                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8173                 break;
8174         case ETH_MIRROR_VIRTUAL_POOL_UP:
8175         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8176                 /* check if the specified pool bit is out of range */
8177                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8178                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8179                         rte_free(mirr_rule);
8180                         return -EINVAL;
8181                 }
8182                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8183                         if (mirror_conf->pool_mask & (1ULL << i)) {
8184                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8185                                 j++;
8186                         }
8187                 }
8188                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8189                         /* add pf vsi to entries */
8190                         mirr_rule->entries[j] = pf->main_vsi_seid;
8191                         j++;
8192                 }
8193                 if (j == 0) {
8194                         PMD_DRV_LOG(ERR, "pool is not specified.");
8195                         rte_free(mirr_rule);
8196                         return -EINVAL;
8197                 }
8198                 /* egress and ingress in aq commands means from switch but not port */
8199                 mirr_rule->rule_type =
8200                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8201                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8202                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8203                 break;
8204         case ETH_MIRROR_UPLINK_PORT:
8205                 /* egress and ingress in aq commands means from switch but not port*/
8206                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8207                 break;
8208         case ETH_MIRROR_DOWNLINK_PORT:
8209                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8210                 break;
8211         default:
8212                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8213                         mirror_conf->rule_type);
8214                 rte_free(mirr_rule);
8215                 return -EINVAL;
8216         }
8217
8218         /* If the dst_pool is equal to vf_num, consider it as PF */
8219         if (mirror_conf->dst_pool == pf->vf_num)
8220                 dst_seid = pf->main_vsi_seid;
8221         else
8222                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8223
8224         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8225                                       mirr_rule->rule_type, mirr_rule->entries,
8226                                       j, &rule_id);
8227         if (ret < 0) {
8228                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8229                                    " ret = %d, aq_err = %d.",
8230                                    ret, hw->aq.asq_last_status);
8231                 rte_free(mirr_rule);
8232                 return -ENOSYS;
8233         }
8234
8235         mirr_rule->index = sw_id;
8236         mirr_rule->num_entries = j;
8237         mirr_rule->id = rule_id;
8238         mirr_rule->dst_vsi_seid = dst_seid;
8239
8240         if (parent)
8241                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8242         else
8243                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8244
8245         pf->nb_mirror_rule++;
8246         return 0;
8247 }
8248
8249 /**
8250  * i40e_mirror_rule_reset
8251  * @dev: pointer to the device
8252  * @sw_id: mirror rule's sw_id
8253  *
8254  * reset a mirror rule.
8255  *
8256  **/
8257 static int
8258 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8259 {
8260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8261         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8262         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8263         uint16_t seid;
8264         int ret;
8265
8266         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8267
8268         seid = pf->main_vsi->veb->seid;
8269
8270         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8271                 if (sw_id == it->index) {
8272                         mirr_rule = it;
8273                         break;
8274                 }
8275         }
8276         if (mirr_rule) {
8277                 ret = i40e_aq_del_mirror_rule(hw, seid,
8278                                 mirr_rule->rule_type,
8279                                 mirr_rule->entries,
8280                                 mirr_rule->num_entries, mirr_rule->id);
8281                 if (ret < 0) {
8282                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8283                                            " status = %d, aq_err = %d.",
8284                                            ret, hw->aq.asq_last_status);
8285                         return -ENOSYS;
8286                 }
8287                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8288                 rte_free(mirr_rule);
8289                 pf->nb_mirror_rule--;
8290         } else {
8291                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8292                 return -ENOENT;
8293         }
8294         return 0;
8295 }
8296
8297 static uint64_t
8298 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8299 {
8300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8301         uint64_t systim_cycles;
8302
8303         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8304         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8305                         << 32;
8306
8307         return systim_cycles;
8308 }
8309
8310 static uint64_t
8311 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8312 {
8313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8314         uint64_t rx_tstamp;
8315
8316         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8317         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8318                         << 32;
8319
8320         return rx_tstamp;
8321 }
8322
8323 static uint64_t
8324 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8325 {
8326         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8327         uint64_t tx_tstamp;
8328
8329         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8330         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8331                         << 32;
8332
8333         return tx_tstamp;
8334 }
8335
8336 static void
8337 i40e_start_timecounters(struct rte_eth_dev *dev)
8338 {
8339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8340         struct i40e_adapter *adapter =
8341                         (struct i40e_adapter *)dev->data->dev_private;
8342         struct rte_eth_link link;
8343         uint32_t tsync_inc_l;
8344         uint32_t tsync_inc_h;
8345
8346         /* Get current link speed. */
8347         memset(&link, 0, sizeof(link));
8348         i40e_dev_link_update(dev, 1);
8349         rte_i40e_dev_atomic_read_link_status(dev, &link);
8350
8351         switch (link.link_speed) {
8352         case ETH_SPEED_NUM_40G:
8353                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8354                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8355                 break;
8356         case ETH_SPEED_NUM_10G:
8357                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8358                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8359                 break;
8360         case ETH_SPEED_NUM_1G:
8361                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8362                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8363                 break;
8364         default:
8365                 tsync_inc_l = 0x0;
8366                 tsync_inc_h = 0x0;
8367         }
8368
8369         /* Set the timesync increment value. */
8370         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8371         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8372
8373         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8374         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8375         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8376
8377         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8378         adapter->systime_tc.cc_shift = 0;
8379         adapter->systime_tc.nsec_mask = 0;
8380
8381         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8382         adapter->rx_tstamp_tc.cc_shift = 0;
8383         adapter->rx_tstamp_tc.nsec_mask = 0;
8384
8385         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8386         adapter->tx_tstamp_tc.cc_shift = 0;
8387         adapter->tx_tstamp_tc.nsec_mask = 0;
8388 }
8389
8390 static int
8391 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8392 {
8393         struct i40e_adapter *adapter =
8394                         (struct i40e_adapter *)dev->data->dev_private;
8395
8396         adapter->systime_tc.nsec += delta;
8397         adapter->rx_tstamp_tc.nsec += delta;
8398         adapter->tx_tstamp_tc.nsec += delta;
8399
8400         return 0;
8401 }
8402
8403 static int
8404 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8405 {
8406         uint64_t ns;
8407         struct i40e_adapter *adapter =
8408                         (struct i40e_adapter *)dev->data->dev_private;
8409
8410         ns = rte_timespec_to_ns(ts);
8411
8412         /* Set the timecounters to a new value. */
8413         adapter->systime_tc.nsec = ns;
8414         adapter->rx_tstamp_tc.nsec = ns;
8415         adapter->tx_tstamp_tc.nsec = ns;
8416
8417         return 0;
8418 }
8419
8420 static int
8421 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8422 {
8423         uint64_t ns, systime_cycles;
8424         struct i40e_adapter *adapter =
8425                         (struct i40e_adapter *)dev->data->dev_private;
8426
8427         systime_cycles = i40e_read_systime_cyclecounter(dev);
8428         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8429         *ts = rte_ns_to_timespec(ns);
8430
8431         return 0;
8432 }
8433
8434 static int
8435 i40e_timesync_enable(struct rte_eth_dev *dev)
8436 {
8437         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8438         uint32_t tsync_ctl_l;
8439         uint32_t tsync_ctl_h;
8440
8441         /* Stop the timesync system time. */
8442         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8443         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8444         /* Reset the timesync system time value. */
8445         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8446         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8447
8448         i40e_start_timecounters(dev);
8449
8450         /* Clear timesync registers. */
8451         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8452         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8453         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8454         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8455         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8456         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8457
8458         /* Enable timestamping of PTP packets. */
8459         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8460         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8461
8462         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8463         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8464         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8465
8466         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8467         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8468
8469         return 0;
8470 }
8471
8472 static int
8473 i40e_timesync_disable(struct rte_eth_dev *dev)
8474 {
8475         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8476         uint32_t tsync_ctl_l;
8477         uint32_t tsync_ctl_h;
8478
8479         /* Disable timestamping of transmitted PTP packets. */
8480         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8481         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8482
8483         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8484         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8485
8486         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8487         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8488
8489         /* Reset the timesync increment value. */
8490         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8491         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8492
8493         return 0;
8494 }
8495
8496 static int
8497 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8498                                 struct timespec *timestamp, uint32_t flags)
8499 {
8500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8501         struct i40e_adapter *adapter =
8502                 (struct i40e_adapter *)dev->data->dev_private;
8503
8504         uint32_t sync_status;
8505         uint32_t index = flags & 0x03;
8506         uint64_t rx_tstamp_cycles;
8507         uint64_t ns;
8508
8509         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8510         if ((sync_status & (1 << index)) == 0)
8511                 return -EINVAL;
8512
8513         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8514         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8515         *timestamp = rte_ns_to_timespec(ns);
8516
8517         return 0;
8518 }
8519
8520 static int
8521 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8522                                 struct timespec *timestamp)
8523 {
8524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8525         struct i40e_adapter *adapter =
8526                 (struct i40e_adapter *)dev->data->dev_private;
8527
8528         uint32_t sync_status;
8529         uint64_t tx_tstamp_cycles;
8530         uint64_t ns;
8531
8532         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8533         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8534                 return -EINVAL;
8535
8536         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8537         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8538         *timestamp = rte_ns_to_timespec(ns);
8539
8540         return 0;
8541 }
8542
8543 /*
8544  * i40e_parse_dcb_configure - parse dcb configure from user
8545  * @dev: the device being configured
8546  * @dcb_cfg: pointer of the result of parse
8547  * @*tc_map: bit map of enabled traffic classes
8548  *
8549  * Returns 0 on success, negative value on failure
8550  */
8551 static int
8552 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8553                          struct i40e_dcbx_config *dcb_cfg,
8554                          uint8_t *tc_map)
8555 {
8556         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8557         uint8_t i, tc_bw, bw_lf;
8558
8559         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8560
8561         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8562         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8563                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8564                 return -EINVAL;
8565         }
8566
8567         /* assume each tc has the same bw */
8568         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8569         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8570                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8571         /* to ensure the sum of tcbw is equal to 100 */
8572         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8573         for (i = 0; i < bw_lf; i++)
8574                 dcb_cfg->etscfg.tcbwtable[i]++;
8575
8576         /* assume each tc has the same Transmission Selection Algorithm */
8577         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8578                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8579
8580         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8581                 dcb_cfg->etscfg.prioritytable[i] =
8582                                 dcb_rx_conf->dcb_tc[i];
8583
8584         /* FW needs one App to configure HW */
8585         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8586         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8587         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8588         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8589
8590         if (dcb_rx_conf->nb_tcs == 0)
8591                 *tc_map = 1; /* tc0 only */
8592         else
8593                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8594
8595         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8596                 dcb_cfg->pfc.willing = 0;
8597                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8598                 dcb_cfg->pfc.pfcenable = *tc_map;
8599         }
8600         return 0;
8601 }
8602
8603
8604 static enum i40e_status_code
8605 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8606                               struct i40e_aqc_vsi_properties_data *info,
8607                               uint8_t enabled_tcmap)
8608 {
8609         enum i40e_status_code ret;
8610         int i, total_tc = 0;
8611         uint16_t qpnum_per_tc, bsf, qp_idx;
8612         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8613         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8614         uint16_t used_queues;
8615
8616         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8617         if (ret != I40E_SUCCESS)
8618                 return ret;
8619
8620         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8621                 if (enabled_tcmap & (1 << i))
8622                         total_tc++;
8623         }
8624         if (total_tc == 0)
8625                 total_tc = 1;
8626         vsi->enabled_tc = enabled_tcmap;
8627
8628         /* different VSI has different queues assigned */
8629         if (vsi->type == I40E_VSI_MAIN)
8630                 used_queues = dev_data->nb_rx_queues -
8631                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8632         else if (vsi->type == I40E_VSI_VMDQ2)
8633                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8634         else {
8635                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8636                 return I40E_ERR_NO_AVAILABLE_VSI;
8637         }
8638
8639         qpnum_per_tc = used_queues / total_tc;
8640         /* Number of queues per enabled TC */
8641         if (qpnum_per_tc == 0) {
8642                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8643                 return I40E_ERR_INVALID_QP_ID;
8644         }
8645         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8646                                 I40E_MAX_Q_PER_TC);
8647         bsf = rte_bsf32(qpnum_per_tc);
8648
8649         /**
8650          * Configure TC and queue mapping parameters, for enabled TC,
8651          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8652          * default queue will serve it.
8653          */
8654         qp_idx = 0;
8655         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8656                 if (vsi->enabled_tc & (1 << i)) {
8657                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8658                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8659                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8660                         qp_idx += qpnum_per_tc;
8661                 } else
8662                         info->tc_mapping[i] = 0;
8663         }
8664
8665         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8666         if (vsi->type == I40E_VSI_SRIOV) {
8667                 info->mapping_flags |=
8668                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8669                 for (i = 0; i < vsi->nb_qps; i++)
8670                         info->queue_mapping[i] =
8671                                 rte_cpu_to_le_16(vsi->base_queue + i);
8672         } else {
8673                 info->mapping_flags |=
8674                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8675                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8676         }
8677         info->valid_sections |=
8678                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8679
8680         return I40E_SUCCESS;
8681 }
8682
8683 /*
8684  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8685  * @veb: VEB to be configured
8686  * @tc_map: enabled TC bitmap
8687  *
8688  * Returns 0 on success, negative value on failure
8689  */
8690 static enum i40e_status_code
8691 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8692 {
8693         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8694         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8695         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8696         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8697         enum i40e_status_code ret = I40E_SUCCESS;
8698         int i;
8699         uint32_t bw_max;
8700
8701         /* Check if enabled_tc is same as existing or new TCs */
8702         if (veb->enabled_tc == tc_map)
8703                 return ret;
8704
8705         /* configure tc bandwidth */
8706         memset(&veb_bw, 0, sizeof(veb_bw));
8707         veb_bw.tc_valid_bits = tc_map;
8708         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8709         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8710                 if (tc_map & BIT_ULL(i))
8711                         veb_bw.tc_bw_share_credits[i] = 1;
8712         }
8713         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8714                                                    &veb_bw, NULL);
8715         if (ret) {
8716                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8717                                   " per TC failed = %d",
8718                                   hw->aq.asq_last_status);
8719                 return ret;
8720         }
8721
8722         memset(&ets_query, 0, sizeof(ets_query));
8723         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8724                                                    &ets_query, NULL);
8725         if (ret != I40E_SUCCESS) {
8726                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8727                                  " configuration %u", hw->aq.asq_last_status);
8728                 return ret;
8729         }
8730         memset(&bw_query, 0, sizeof(bw_query));
8731         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8732                                                   &bw_query, NULL);
8733         if (ret != I40E_SUCCESS) {
8734                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8735                                  " configuration %u", hw->aq.asq_last_status);
8736                 return ret;
8737         }
8738
8739         /* store and print out BW info */
8740         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8741         veb->bw_info.bw_max = ets_query.tc_bw_max;
8742         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8743         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8744         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8745                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8746                      I40E_16_BIT_WIDTH);
8747         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8748                 veb->bw_info.bw_ets_share_credits[i] =
8749                                 bw_query.tc_bw_share_credits[i];
8750                 veb->bw_info.bw_ets_credits[i] =
8751                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8752                 /* 4 bits per TC, 4th bit is reserved */
8753                 veb->bw_info.bw_ets_max[i] =
8754                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8755                                   RTE_LEN2MASK(3, uint8_t));
8756                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8757                             veb->bw_info.bw_ets_share_credits[i]);
8758                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8759                             veb->bw_info.bw_ets_credits[i]);
8760                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8761                             veb->bw_info.bw_ets_max[i]);
8762         }
8763
8764         veb->enabled_tc = tc_map;
8765
8766         return ret;
8767 }
8768
8769
8770 /*
8771  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8772  * @vsi: VSI to be configured
8773  * @tc_map: enabled TC bitmap
8774  *
8775  * Returns 0 on success, negative value on failure
8776  */
8777 static enum i40e_status_code
8778 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8779 {
8780         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8781         struct i40e_vsi_context ctxt;
8782         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8783         enum i40e_status_code ret = I40E_SUCCESS;
8784         int i;
8785
8786         /* Check if enabled_tc is same as existing or new TCs */
8787         if (vsi->enabled_tc == tc_map)
8788                 return ret;
8789
8790         /* configure tc bandwidth */
8791         memset(&bw_data, 0, sizeof(bw_data));
8792         bw_data.tc_valid_bits = tc_map;
8793         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8794         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8795                 if (tc_map & BIT_ULL(i))
8796                         bw_data.tc_bw_credits[i] = 1;
8797         }
8798         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8799         if (ret) {
8800                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8801                         " per TC failed = %d",
8802                         hw->aq.asq_last_status);
8803                 goto out;
8804         }
8805         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8806                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8807
8808         /* Update Queue Pairs Mapping for currently enabled UPs */
8809         ctxt.seid = vsi->seid;
8810         ctxt.pf_num = hw->pf_id;
8811         ctxt.vf_num = 0;
8812         ctxt.uplink_seid = vsi->uplink_seid;
8813         ctxt.info = vsi->info;
8814         i40e_get_cap(hw);
8815         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8816         if (ret)
8817                 goto out;
8818
8819         /* Update the VSI after updating the VSI queue-mapping information */
8820         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8821         if (ret) {
8822                 PMD_INIT_LOG(ERR, "Failed to configure "
8823                             "TC queue mapping = %d",
8824                             hw->aq.asq_last_status);
8825                 goto out;
8826         }
8827         /* update the local VSI info with updated queue map */
8828         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8829                                         sizeof(vsi->info.tc_mapping));
8830         (void)rte_memcpy(&vsi->info.queue_mapping,
8831                         &ctxt.info.queue_mapping,
8832                 sizeof(vsi->info.queue_mapping));
8833         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8834         vsi->info.valid_sections = 0;
8835
8836         /* query and update current VSI BW information */
8837         ret = i40e_vsi_get_bw_config(vsi);
8838         if (ret) {
8839                 PMD_INIT_LOG(ERR,
8840                          "Failed updating vsi bw info, err %s aq_err %s",
8841                          i40e_stat_str(hw, ret),
8842                          i40e_aq_str(hw, hw->aq.asq_last_status));
8843                 goto out;
8844         }
8845
8846         vsi->enabled_tc = tc_map;
8847
8848 out:
8849         return ret;
8850 }
8851
8852 /*
8853  * i40e_dcb_hw_configure - program the dcb setting to hw
8854  * @pf: pf the configuration is taken on
8855  * @new_cfg: new configuration
8856  * @tc_map: enabled TC bitmap
8857  *
8858  * Returns 0 on success, negative value on failure
8859  */
8860 static enum i40e_status_code
8861 i40e_dcb_hw_configure(struct i40e_pf *pf,
8862                       struct i40e_dcbx_config *new_cfg,
8863                       uint8_t tc_map)
8864 {
8865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8866         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8867         struct i40e_vsi *main_vsi = pf->main_vsi;
8868         struct i40e_vsi_list *vsi_list;
8869         enum i40e_status_code ret;
8870         int i;
8871         uint32_t val;
8872
8873         /* Use the FW API if FW > v4.4*/
8874         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8875               (hw->aq.fw_maj_ver >= 5))) {
8876                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8877                                   " to configure DCB");
8878                 return I40E_ERR_FIRMWARE_API_VERSION;
8879         }
8880
8881         /* Check if need reconfiguration */
8882         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8883                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8884                 return I40E_SUCCESS;
8885         }
8886
8887         /* Copy the new config to the current config */
8888         *old_cfg = *new_cfg;
8889         old_cfg->etsrec = old_cfg->etscfg;
8890         ret = i40e_set_dcb_config(hw);
8891         if (ret) {
8892                 PMD_INIT_LOG(ERR,
8893                          "Set DCB Config failed, err %s aq_err %s\n",
8894                          i40e_stat_str(hw, ret),
8895                          i40e_aq_str(hw, hw->aq.asq_last_status));
8896                 return ret;
8897         }
8898         /* set receive Arbiter to RR mode and ETS scheme by default */
8899         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8900                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8901                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8902                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8903                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8904                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8905                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8906                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8907                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8908                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8909                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8910                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8911                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8912         }
8913         /* get local mib to check whether it is configured correctly */
8914         /* IEEE mode */
8915         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8916         /* Get Local DCB Config */
8917         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8918                                      &hw->local_dcbx_config);
8919
8920         /* if Veb is created, need to update TC of it at first */
8921         if (main_vsi->veb) {
8922                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8923                 if (ret)
8924                         PMD_INIT_LOG(WARNING,
8925                                  "Failed configuring TC for VEB seid=%d\n",
8926                                  main_vsi->veb->seid);
8927         }
8928         /* Update each VSI */
8929         i40e_vsi_config_tc(main_vsi, tc_map);
8930         if (main_vsi->veb) {
8931                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8932                         /* Beside main VSI and VMDQ VSIs, only enable default
8933                          * TC for other VSIs
8934                          */
8935                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8936                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8937                                                          tc_map);
8938                         else
8939                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8940                                                          I40E_DEFAULT_TCMAP);
8941                         if (ret)
8942                                 PMD_INIT_LOG(WARNING,
8943                                          "Failed configuring TC for VSI seid=%d\n",
8944                                          vsi_list->vsi->seid);
8945                         /* continue */
8946                 }
8947         }
8948         return I40E_SUCCESS;
8949 }
8950
8951 /*
8952  * i40e_dcb_init_configure - initial dcb config
8953  * @dev: device being configured
8954  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8955  *
8956  * Returns 0 on success, negative value on failure
8957  */
8958 static int
8959 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8960 {
8961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8962         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8963         int ret = 0;
8964
8965         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8966                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8967                 return -ENOTSUP;
8968         }
8969
8970         /* DCB initialization:
8971          * Update DCB configuration from the Firmware and configure
8972          * LLDP MIB change event.
8973          */
8974         if (sw_dcb == TRUE) {
8975                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8976                 if (ret != I40E_SUCCESS)
8977                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8978
8979                 ret = i40e_init_dcb(hw);
8980                 /* if sw_dcb, lldp agent is stopped, the return from
8981                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8982                  * adminq status.
8983                  */
8984                 if (ret != I40E_SUCCESS &&
8985                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8986                         memset(&hw->local_dcbx_config, 0,
8987                                 sizeof(struct i40e_dcbx_config));
8988                         /* set dcb default configuration */
8989                         hw->local_dcbx_config.etscfg.willing = 0;
8990                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8991                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8992                         hw->local_dcbx_config.etscfg.tsatable[0] =
8993                                                 I40E_IEEE_TSA_ETS;
8994                         hw->local_dcbx_config.etsrec =
8995                                 hw->local_dcbx_config.etscfg;
8996                         hw->local_dcbx_config.pfc.willing = 0;
8997                         hw->local_dcbx_config.pfc.pfccap =
8998                                                 I40E_MAX_TRAFFIC_CLASS;
8999                         /* FW needs one App to configure HW */
9000                         hw->local_dcbx_config.numapps = 1;
9001                         hw->local_dcbx_config.app[0].selector =
9002                                                 I40E_APP_SEL_ETHTYPE;
9003                         hw->local_dcbx_config.app[0].priority = 3;
9004                         hw->local_dcbx_config.app[0].protocolid =
9005                                                 I40E_APP_PROTOID_FCOE;
9006                         ret = i40e_set_dcb_config(hw);
9007                         if (ret) {
9008                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9009                                         " err = %d, aq_err = %d.", ret,
9010                                           hw->aq.asq_last_status);
9011                                 return -ENOSYS;
9012                         }
9013                 } else {
9014                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9015                                           " aq_err = %d.", ret,
9016                                           hw->aq.asq_last_status);
9017                         return -ENOTSUP;
9018                 }
9019         } else {
9020                 ret = i40e_aq_start_lldp(hw, NULL);
9021                 if (ret != I40E_SUCCESS)
9022                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9023
9024                 ret = i40e_init_dcb(hw);
9025                 if (!ret) {
9026                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9027                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9028                                                   " DCBX offload.");
9029                                 return -ENOTSUP;
9030                         }
9031                 } else {
9032                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9033                                           " aq_err = %d.", ret,
9034                                           hw->aq.asq_last_status);
9035                         return -ENOTSUP;
9036                 }
9037         }
9038         return 0;
9039 }
9040
9041 /*
9042  * i40e_dcb_setup - setup dcb related config
9043  * @dev: device being configured
9044  *
9045  * Returns 0 on success, negative value on failure
9046  */
9047 static int
9048 i40e_dcb_setup(struct rte_eth_dev *dev)
9049 {
9050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9051         struct i40e_dcbx_config dcb_cfg;
9052         uint8_t tc_map = 0;
9053         int ret = 0;
9054
9055         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9056                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9057                 return -ENOTSUP;
9058         }
9059
9060         if (pf->vf_num != 0)
9061                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9062
9063         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9064         if (ret) {
9065                 PMD_INIT_LOG(ERR, "invalid dcb config");
9066                 return -EINVAL;
9067         }
9068         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9069         if (ret) {
9070                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9071                 return -ENOSYS;
9072         }
9073
9074         return 0;
9075 }
9076
9077 static int
9078 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9079                       struct rte_eth_dcb_info *dcb_info)
9080 {
9081         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9082         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9083         struct i40e_vsi *vsi = pf->main_vsi;
9084         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9085         uint16_t bsf, tc_mapping;
9086         int i, j = 0;
9087
9088         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9089                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9090         else
9091                 dcb_info->nb_tcs = 1;
9092         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9093                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9094         for (i = 0; i < dcb_info->nb_tcs; i++)
9095                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9096
9097         /* get queue mapping if vmdq is disabled */
9098         if (!pf->nb_cfg_vmdq_vsi) {
9099                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9100                         if (!(vsi->enabled_tc & (1 << i)))
9101                                 continue;
9102                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9103                         dcb_info->tc_queue.tc_rxq[j][i].base =
9104                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9105                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9106                         dcb_info->tc_queue.tc_txq[j][i].base =
9107                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9108                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9109                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9110                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9111                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9112                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9113                 }
9114                 return 0;
9115         }
9116
9117         /* get queue mapping if vmdq is enabled */
9118         do {
9119                 vsi = pf->vmdq[j].vsi;
9120                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9121                         if (!(vsi->enabled_tc & (1 << i)))
9122                                 continue;
9123                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9124                         dcb_info->tc_queue.tc_rxq[j][i].base =
9125                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9126                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9127                         dcb_info->tc_queue.tc_txq[j][i].base =
9128                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9129                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9130                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9131                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9132                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9133                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9134                 }
9135                 j++;
9136         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9137         return 0;
9138 }
9139
9140 static int
9141 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9142 {
9143         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9144         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9145         uint16_t interval =
9146                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9147         uint16_t msix_intr;
9148
9149         msix_intr = intr_handle->intr_vec[queue_id];
9150         if (msix_intr == I40E_MISC_VEC_ID)
9151                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9152                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9153                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9154                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9155                                (interval <<
9156                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9157         else
9158                 I40E_WRITE_REG(hw,
9159                                I40E_PFINT_DYN_CTLN(msix_intr -
9160                                                    I40E_RX_VEC_START),
9161                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9162                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9163                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9164                                (interval <<
9165                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9166
9167         I40E_WRITE_FLUSH(hw);
9168         rte_intr_enable(&dev->pci_dev->intr_handle);
9169
9170         return 0;
9171 }
9172
9173 static int
9174 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9175 {
9176         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9177         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9178         uint16_t msix_intr;
9179
9180         msix_intr = intr_handle->intr_vec[queue_id];
9181         if (msix_intr == I40E_MISC_VEC_ID)
9182                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9183         else
9184                 I40E_WRITE_REG(hw,
9185                                I40E_PFINT_DYN_CTLN(msix_intr -
9186                                                    I40E_RX_VEC_START),
9187                                0);
9188         I40E_WRITE_FLUSH(hw);
9189
9190         return 0;
9191 }
9192
9193 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9194 {
9195         /* Highest base addr + 32-bit word */
9196         return I40E_GLGEN_STAT_CLEAR + 4;
9197 }
9198
9199 static int i40e_get_regs(struct rte_eth_dev *dev,
9200                          struct rte_dev_reg_info *regs)
9201 {
9202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9203         uint32_t *ptr_data = regs->data;
9204         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9205         const struct i40e_reg_info *reg_info;
9206
9207         /* The first few registers have to be read using AQ operations */
9208         reg_idx = 0;
9209         while (i40e_regs_adminq[reg_idx].name) {
9210                 reg_info = &i40e_regs_adminq[reg_idx++];
9211                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9212                         for (arr_idx2 = 0;
9213                                         arr_idx2 <= reg_info->count2;
9214                                         arr_idx2++) {
9215                                 reg_offset = arr_idx * reg_info->stride1 +
9216                                         arr_idx2 * reg_info->stride2;
9217                                 reg_offset += reg_info->base_addr;
9218                                 ptr_data[reg_offset >> 2] =
9219                                         i40e_read_rx_ctl(hw, reg_offset);
9220                         }
9221         }
9222
9223         /* The remaining registers can be read using primitives */
9224         reg_idx = 0;
9225         while (i40e_regs_others[reg_idx].name) {
9226                 reg_info = &i40e_regs_others[reg_idx++];
9227                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9228                         for (arr_idx2 = 0;
9229                                         arr_idx2 <= reg_info->count2;
9230                                         arr_idx2++) {
9231                                 reg_offset = arr_idx * reg_info->stride1 +
9232                                         arr_idx2 * reg_info->stride2;
9233                                 reg_offset += reg_info->base_addr;
9234                                 ptr_data[reg_offset >> 2] =
9235                                         I40E_READ_REG(hw, reg_offset);
9236                         }
9237         }
9238
9239         return 0;
9240 }
9241
9242 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9243 {
9244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9245
9246         /* Convert word count to byte count */
9247         return hw->nvm.sr_size << 1;
9248 }
9249
9250 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9251                            struct rte_dev_eeprom_info *eeprom)
9252 {
9253         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9254         uint16_t *data = eeprom->data;
9255         uint16_t offset, length, cnt_words;
9256         int ret_code;
9257
9258         offset = eeprom->offset >> 1;
9259         length = eeprom->length >> 1;
9260         cnt_words = length;
9261
9262         if (offset > hw->nvm.sr_size ||
9263                 offset + length > hw->nvm.sr_size) {
9264                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9265                 return -EINVAL;
9266         }
9267
9268         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9269
9270         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9271         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9272                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9273                 return -EIO;
9274         }
9275
9276         return 0;
9277 }
9278
9279 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9280                                       struct ether_addr *mac_addr)
9281 {
9282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9283
9284         if (!is_valid_assigned_ether_addr(mac_addr)) {
9285                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9286                 return;
9287         }
9288
9289         /* Flags: 0x3 updates port address */
9290         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9291 }
9292
9293 static int
9294 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9295 {
9296         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9297         struct rte_eth_dev_data *dev_data = pf->dev_data;
9298         uint32_t frame_size = mtu + ETHER_HDR_LEN
9299                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9300         int ret = 0;
9301
9302         /* check if mtu is within the allowed range */
9303         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9304                 return -EINVAL;
9305
9306         /* mtu setting is forbidden if port is start */
9307         if (dev_data->dev_started) {
9308                 PMD_DRV_LOG(ERR,
9309                             "port %d must be stopped before configuration\n",
9310                             dev_data->port_id);
9311                 return -EBUSY;
9312         }
9313
9314         if (frame_size > ETHER_MAX_LEN)
9315                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9316         else
9317                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9318
9319         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9320
9321         return ret;
9322 }