drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "base/i40e_dcb.h"
  60 #include "i40e_ethdev.h"
  61 #include "i40e_rxtx.h"
  62 #include "i40e_pf.h"
  63
  64 /* Maximun number of MAC addresses */
  65 #define I40E_NUM_MACADDR_MAX       64
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 /* Default queue interrupt throttling time in microseconds */
  79 #define I40E_ITR_INDEX_DEFAULT          0
  80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  81 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA  0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 144 static int i40e_dev_configure(struct rte_eth_dev *dev);
 145 static int i40e_dev_start(struct rte_eth_dev *dev);
 146 static void i40e_dev_stop(struct rte_eth_dev *dev);
 147 static void i40e_dev_close(struct rte_eth_dev *dev);
 148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 155                                struct rte_eth_stats *stats);
 156 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 157 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 158                                             uint16_t queue_id,
 159                                             uint8_t stat_idx,
 160                                             uint8_t is_rx);
 161 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 162                               struct rte_eth_dev_info *dev_info);
 163 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 164                                 uint16_t vlan_id,
 165                                 int on);
 166 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 167 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 168 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 169                                       uint16_t queue,
 170                                       int on);
 171 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 172 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 173 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 174 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 175                               struct rte_eth_fc_conf *fc_conf);
 176 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 177                               struct rte_eth_fc_conf *fc_conf);
 178 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 179                                        struct rte_eth_pfc_conf *pfc_conf);
 180 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 181                           struct ether_addr *mac_addr,
 182                           uint32_t index,
 183                           uint32_t pool);
 184 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 185 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                     uint16_t reta_size);
 188 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 190                                    uint16_t reta_size);
 191
 192 static int i40e_get_cap(struct i40e_hw *hw);
 193 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 194 static int i40e_pf_setup(struct i40e_pf *pf);
 195 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 196 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 197 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 198 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 199 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 200                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 201 static void i40e_stat_update_48(struct i40e_hw *hw,
 202                                uint32_t hireg,
 203                                uint32_t loreg,
 204                                bool offset_loaded,
 205                                uint64_t *offset,
 206                                uint64_t *stat);
 207 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 208 static void i40e_dev_interrupt_handler(
 209                 __rte_unused struct rte_intr_handle *handle, void *param);
 210 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 211                                 uint32_t base, uint32_t num);
 212 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 213 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 214                         uint32_t base);
 215 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 216                         uint16_t num);
 217 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 218 static int i40e_veb_release(struct i40e_veb *veb);
 219 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 220                                                 struct i40e_vsi *vsi);
 221 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 222 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 223 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 224                                              struct i40e_macvlan_filter *mv_f,
 225                                              int num,
 226                                              struct ether_addr *addr);
 227 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 228                                              struct i40e_macvlan_filter *mv_f,
 229                                              int num,
 230                                              uint16_t vlan);
 231 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 232 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 233                                     struct rte_eth_rss_conf *rss_conf);
 234 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 235                                       struct rte_eth_rss_conf *rss_conf);
 236 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 237                                 struct rte_eth_udp_tunnel *udp_tunnel);
 238 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 239                                 struct rte_eth_udp_tunnel *udp_tunnel);
 240 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 247                                 enum rte_filter_type filter_type,
 248                                 enum rte_filter_op filter_op,
 249                                 void *arg);
 250 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 251                                   struct rte_eth_dcb_info *dcb_info);
 252 static void i40e_configure_registers(struct i40e_hw *hw);
 253 static void i40e_hw_init(struct i40e_hw *hw);
 254 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 255 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 256                         struct rte_eth_mirror_conf *mirror_conf,
 257                         uint8_t sw_id, uint8_t on);
 258 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 259
 260 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 261 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 262 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 263                                            struct timespec *timestamp,
 264                                            uint32_t flags);
 265 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 266                                            struct timespec *timestamp);
 267
 268 static const struct rte_pci_id pci_id_i40e_map[] = {
 269 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 270 #include "rte_pci_dev_ids.h"
 271 { .vendor_id = 0, /* sentinel */ },
 272 };
 273
 274 static const struct eth_dev_ops i40e_eth_dev_ops = {
 275         .dev_configure                = i40e_dev_configure,
 276         .dev_start                    = i40e_dev_start,
 277         .dev_stop                     = i40e_dev_stop,
 278         .dev_close                    = i40e_dev_close,
 279         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 280         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 281         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 282         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 283         .dev_set_link_up              = i40e_dev_set_link_up,
 284         .dev_set_link_down            = i40e_dev_set_link_down,
 285         .link_update                  = i40e_dev_link_update,
 286         .stats_get                    = i40e_dev_stats_get,
 287         .stats_reset                  = i40e_dev_stats_reset,
 288         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 289         .dev_infos_get                = i40e_dev_info_get,
 290         .vlan_filter_set              = i40e_vlan_filter_set,
 291         .vlan_tpid_set                = i40e_vlan_tpid_set,
 292         .vlan_offload_set             = i40e_vlan_offload_set,
 293         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 294         .vlan_pvid_set                = i40e_vlan_pvid_set,
 295         .rx_queue_start               = i40e_dev_rx_queue_start,
 296         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 297         .tx_queue_start               = i40e_dev_tx_queue_start,
 298         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 299         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 300         .rx_queue_release             = i40e_dev_rx_queue_release,
 301         .rx_queue_count               = i40e_dev_rx_queue_count,
 302         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 303         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 304         .tx_queue_release             = i40e_dev_tx_queue_release,
 305         .dev_led_on                   = i40e_dev_led_on,
 306         .dev_led_off                  = i40e_dev_led_off,
 307         .flow_ctrl_get                = i40e_flow_ctrl_get,
 308         .flow_ctrl_set                = i40e_flow_ctrl_set,
 309         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 310         .mac_addr_add                 = i40e_macaddr_add,
 311         .mac_addr_remove              = i40e_macaddr_remove,
 312         .reta_update                  = i40e_dev_rss_reta_update,
 313         .reta_query                   = i40e_dev_rss_reta_query,
 314         .rss_hash_update              = i40e_dev_rss_hash_update,
 315         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 316         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 317         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 318         .filter_ctrl                  = i40e_dev_filter_ctrl,
 319         .mirror_rule_set              = i40e_mirror_rule_set,
 320         .mirror_rule_reset            = i40e_mirror_rule_reset,
 321         .timesync_enable              = i40e_timesync_enable,
 322         .timesync_disable             = i40e_timesync_disable,
 323         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 324         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 325         .get_dcb_info                 = i40e_dev_get_dcb_info,
 326 };
 327
 328 static struct eth_driver rte_i40e_pmd = {
 329         .pci_drv = {
 330                 .name = "rte_i40e_pmd",
 331                 .id_table = pci_id_i40e_map,
 332                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 333                         RTE_PCI_DRV_DETACHABLE,
 334         },
 335         .eth_dev_init = eth_i40e_dev_init,
 336         .eth_dev_uninit = eth_i40e_dev_uninit,
 337         .dev_private_size = sizeof(struct i40e_adapter),
 338 };
 339
 340 static inline int
 341 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 342                                      struct rte_eth_link *link)
 343 {
 344         struct rte_eth_link *dst = link;
 345         struct rte_eth_link *src = &(dev->data->dev_link);
 346
 347         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 348                                         *(uint64_t *)src) == 0)
 349                 return -1;
 350
 351         return 0;
 352 }
 353
 354 static inline int
 355 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 356                                       struct rte_eth_link *link)
 357 {
 358         struct rte_eth_link *dst = &(dev->data->dev_link);
 359         struct rte_eth_link *src = link;
 360
 361         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 362                                         *(uint64_t *)src) == 0)
 363                 return -1;
 364
 365         return 0;
 366 }
 367
 368 /*
 369  * Driver initialization routine.
 370  * Invoked once at EAL init time.
 371  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 372  */
 373 static int
 374 rte_i40e_pmd_init(const char *name __rte_unused,
 375                   const char *params __rte_unused)
 376 {
 377         PMD_INIT_FUNC_TRACE();
 378         rte_eth_driver_register(&rte_i40e_pmd);
 379
 380         return 0;
 381 }
 382
 383 static struct rte_driver rte_i40e_driver = {
 384         .type = PMD_PDEV,
 385         .init = rte_i40e_pmd_init,
 386 };
 387
 388 PMD_REGISTER_DRIVER(rte_i40e_driver);
 389
 390 /*
 391  * Initialize registers for flexible payload, which should be set by NVM.
 392  * This should be removed from code once it is fixed in NVM.
 393  */
 394 #ifndef I40E_GLQF_ORT
 395 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 396 #endif
 397 #ifndef I40E_GLQF_PIT
 398 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 399 #endif
 400
 401 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 402 {
 403         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 404         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 405         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 406         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 407         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 408         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 409         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 410         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 411         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 412         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 413
 414         /* GLQF_PIT Registers */
 415         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 416         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 417 }
 418
 419 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 420
 421 /*
 422  * Add a ethertype filter to drop all flow control frames transmitted
 423  * from VSIs.
 424 */
 425 static void
 426 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 427 {
 428         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 429         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 430                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 431                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 432         int ret;
 433
 434         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 435                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 436                                 pf->main_vsi_seid, 0,
 437                                 TRUE, NULL, NULL);
 438         if (ret)
 439                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 440                                   " frames from VSIs.");
 441 }
 442
 443 static int
 444 eth_i40e_dev_init(struct rte_eth_dev *dev)
 445 {
 446         struct rte_pci_device *pci_dev;
 447         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 448         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 449         struct i40e_vsi *vsi;
 450         int ret;
 451         uint32_t len;
 452         uint8_t aq_fail = 0;
 453
 454         PMD_INIT_FUNC_TRACE();
 455
 456         dev->dev_ops = &i40e_eth_dev_ops;
 457         dev->rx_pkt_burst = i40e_recv_pkts;
 458         dev->tx_pkt_burst = i40e_xmit_pkts;
 459
 460         /* for secondary processes, we don't initialise any further as primary
 461          * has already done this work. Only check we don't need a different
 462          * RX function */
 463         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 464                 i40e_set_rx_function(dev);
 465                 i40e_set_tx_function(dev);
 466                 return 0;
 467         }
 468         pci_dev = dev->pci_dev;
 469         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 470         pf->adapter->eth_dev = dev;
 471         pf->dev_data = dev->data;
 472
 473         hw->back = I40E_PF_TO_ADAPTER(pf);
 474         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 475         if (!hw->hw_addr) {
 476                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 477                              "as address is NULL");
 478                 return -ENODEV;
 479         }
 480
 481         hw->vendor_id = pci_dev->id.vendor_id;
 482         hw->device_id = pci_dev->id.device_id;
 483         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 484         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 485         hw->bus.device = pci_dev->addr.devid;
 486         hw->bus.func = pci_dev->addr.function;
 487         hw->adapter_stopped = 0;
 488
 489         /* Make sure all is clean before doing PF reset */
 490         i40e_clear_hw(hw);
 491
 492         /* Initialize the hardware */
 493         i40e_hw_init(hw);
 494
 495         /* Reset here to make sure all is clean for each PF */
 496         ret = i40e_pf_reset(hw);
 497         if (ret) {
 498                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 499                 return ret;
 500         }
 501
 502         /* Initialize the shared code (base driver) */
 503         ret = i40e_init_shared_code(hw);
 504         if (ret) {
 505                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 506                 return ret;
 507         }
 508
 509         /*
 510          * To work around the NVM issue,initialize registers
 511          * for flexible payload by software.
 512          * It should be removed once issues are fixed in NVM.
 513          */
 514         i40e_flex_payload_reg_init(hw);
 515
 516         /* Initialize the parameters for adminq */
 517         i40e_init_adminq_parameter(hw);
 518         ret = i40e_init_adminq(hw);
 519         if (ret != I40E_SUCCESS) {
 520                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 521                 return -EIO;
 522         }
 523         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 524                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 525                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 526                      ((hw->nvm.version >> 12) & 0xf),
 527                      ((hw->nvm.version >> 4) & 0xff),
 528                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 529
 530         /* Clear PXE mode */
 531         i40e_clear_pxe_mode(hw);
 532
 533         /*
 534          * On X710, performance number is far from the expectation on recent
 535          * firmware versions. The fix for this issue may not be integrated in
 536          * the following firmware version. So the workaround in software driver
 537          * is needed. It needs to modify the initial values of 3 internal only
 538          * registers. Note that the workaround can be removed when it is fixed
 539          * in firmware in the future.
 540          */
 541         i40e_configure_registers(hw);
 542
 543         /* Get hw capabilities */
 544         ret = i40e_get_cap(hw);
 545         if (ret != I40E_SUCCESS) {
 546                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 547                 goto err_get_capabilities;
 548         }
 549
 550         /* Initialize parameters for PF */
 551         ret = i40e_pf_parameter_init(dev);
 552         if (ret != 0) {
 553                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 554                 goto err_parameter_init;
 555         }
 556
 557         /* Initialize the queue management */
 558         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 559         if (ret < 0) {
 560                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 561                 goto err_qp_pool_init;
 562         }
 563         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 564                                 hw->func_caps.num_msix_vectors - 1);
 565         if (ret < 0) {
 566                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 567                 goto err_msix_pool_init;
 568         }
 569
 570         /* Initialize lan hmc */
 571         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 572                                 hw->func_caps.num_rx_qp, 0, 0);
 573         if (ret != I40E_SUCCESS) {
 574                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 575                 goto err_init_lan_hmc;
 576         }
 577
 578         /* Configure lan hmc */
 579         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 580         if (ret != I40E_SUCCESS) {
 581                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 582                 goto err_configure_lan_hmc;
 583         }
 584
 585         /* Get and check the mac address */
 586         i40e_get_mac_addr(hw, hw->mac.addr);
 587         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 588                 PMD_INIT_LOG(ERR, "mac address is not valid");
 589                 ret = -EIO;
 590                 goto err_get_mac_addr;
 591         }
 592         /* Copy the permanent MAC address */
 593         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 594                         (struct ether_addr *) hw->mac.perm_addr);
 595
 596         /* Disable flow control */
 597         hw->fc.requested_mode = I40E_FC_NONE;
 598         i40e_set_fc(hw, &aq_fail, TRUE);
 599
 600         /* PF setup, which includes VSI setup */
 601         ret = i40e_pf_setup(pf);
 602         if (ret) {
 603                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 604                 goto err_setup_pf_switch;
 605         }
 606
 607         vsi = pf->main_vsi;
 608
 609         /* Disable double vlan by default */
 610         i40e_vsi_config_double_vlan(vsi, FALSE);
 611
 612         if (!vsi->max_macaddrs)
 613                 len = ETHER_ADDR_LEN;
 614         else
 615                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 616
 617         /* Should be after VSI initialized */
 618         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 619         if (!dev->data->mac_addrs) {
 620                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 621                                         "for storing mac address");
 622                 goto err_mac_alloc;
 623         }
 624         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 625                                         &dev->data->mac_addrs[0]);
 626
 627         /* initialize pf host driver to setup SRIOV resource if applicable */
 628         i40e_pf_host_init(dev);
 629
 630         /* register callback func to eal lib */
 631         rte_intr_callback_register(&(pci_dev->intr_handle),
 632                 i40e_dev_interrupt_handler, (void *)dev);
 633
 634         /* configure and enable device interrupt */
 635         i40e_pf_config_irq0(hw);
 636         i40e_pf_enable_irq0(hw);
 637
 638         /* enable uio intr after callback register */
 639         rte_intr_enable(&(pci_dev->intr_handle));
 640         /*
 641          * Add an ethertype filter to drop all flow control frames transmitted
 642          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 643          * frames to wire.
 644          */
 645         i40e_add_tx_flow_control_drop_filter(pf);
 646
 647         /* initialize mirror rule list */
 648         TAILQ_INIT(&pf->mirror_list);
 649
 650         /* Init dcb to sw mode by default */
 651         ret = i40e_dcb_init_configure(dev, TRUE);
 652         if (ret != I40E_SUCCESS) {
 653                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 654                 pf->flags &= ~I40E_FLAG_DCB;
 655         }
 656
 657         return 0;
 658
 659 err_mac_alloc:
 660         i40e_vsi_release(pf->main_vsi);
 661 err_setup_pf_switch:
 662 err_get_mac_addr:
 663 err_configure_lan_hmc:
 664         (void)i40e_shutdown_lan_hmc(hw);
 665 err_init_lan_hmc:
 666         i40e_res_pool_destroy(&pf->msix_pool);
 667 err_msix_pool_init:
 668         i40e_res_pool_destroy(&pf->qp_pool);
 669 err_qp_pool_init:
 670 err_parameter_init:
 671 err_get_capabilities:
 672         (void)i40e_shutdown_adminq(hw);
 673
 674         return ret;
 675 }
 676
 677 static int
 678 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 679 {
 680         struct rte_pci_device *pci_dev;
 681         struct i40e_hw *hw;
 682         struct i40e_filter_control_settings settings;
 683         int ret;
 684         uint8_t aq_fail = 0;
 685
 686         PMD_INIT_FUNC_TRACE();
 687
 688         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 689                 return 0;
 690
 691         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 692         pci_dev = dev->pci_dev;
 693
 694         if (hw->adapter_stopped == 0)
 695                 i40e_dev_close(dev);
 696
 697         dev->dev_ops = NULL;
 698         dev->rx_pkt_burst = NULL;
 699         dev->tx_pkt_burst = NULL;
 700
 701         /* Disable LLDP */
 702         ret = i40e_aq_stop_lldp(hw, true, NULL);
 703         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 704                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 705
 706         /* Clear PXE mode */
 707         i40e_clear_pxe_mode(hw);
 708
 709         /* Unconfigure filter control */
 710         memset(&settings, 0, sizeof(settings));
 711         ret = i40e_set_filter_control(hw, &settings);
 712         if (ret)
 713                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 714                                         ret);
 715
 716         /* Disable flow control */
 717         hw->fc.requested_mode = I40E_FC_NONE;
 718         i40e_set_fc(hw, &aq_fail, TRUE);
 719
 720         /* uninitialize pf host driver */
 721         i40e_pf_host_uninit(dev);
 722
 723         rte_free(dev->data->mac_addrs);
 724         dev->data->mac_addrs = NULL;
 725
 726         /* disable uio intr before callback unregister */
 727         rte_intr_disable(&(pci_dev->intr_handle));
 728
 729         /* register callback func to eal lib */
 730         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 731                 i40e_dev_interrupt_handler, (void *)dev);
 732
 733         return 0;
 734 }
 735
 736 static int
 737 i40e_dev_configure(struct rte_eth_dev *dev)
 738 {
 739         struct i40e_adapter *ad =
 740                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 741         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 742         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 743         int i, ret;
 744
 745         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 746          * bulk allocation or vector Rx preconditions we will reset it.
 747          */
 748         ad->rx_bulk_alloc_allowed = true;
 749         ad->rx_vec_allowed = true;
 750         ad->tx_simple_allowed = true;
 751         ad->tx_vec_allowed = true;
 752
 753         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 754                 ret = i40e_fdir_setup(pf);
 755                 if (ret != I40E_SUCCESS) {
 756                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 757                         return -ENOTSUP;
 758                 }
 759                 ret = i40e_fdir_configure(dev);
 760                 if (ret < 0) {
 761                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 762                         goto err;
 763                 }
 764         } else
 765                 i40e_fdir_teardown(pf);
 766
 767         ret = i40e_dev_init_vlan(dev);
 768         if (ret < 0)
 769                 goto err;
 770
 771         /* VMDQ setup.
 772          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 773          *  RSS setting have different requirements.
 774          *  General PMD driver call sequence are NIC init, configure,
 775          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 776          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 777          *  applicable. So, VMDQ setting has to be done before
 778          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 779          *  For RSS setting, it will try to calculate actual configured RX queue
 780          *  number, which will be available after rx_queue_setup(). dev_start()
 781          *  function is good to place RSS setup.
 782          */
 783         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 784                 ret = i40e_vmdq_setup(dev);
 785                 if (ret)
 786                         goto err;
 787         }
 788
 789         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
 790                 ret = i40e_dcb_setup(dev);
 791                 if (ret) {
 792                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
 793                         goto err_dcb;
 794                 }
 795         }
 796
 797         return 0;
 798
 799 err_dcb:
 800         /* need to release vmdq resource if exists */
 801         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 802                 i40e_vsi_release(pf->vmdq[i].vsi);
 803                 pf->vmdq[i].vsi = NULL;
 804         }
 805         rte_free(pf->vmdq);
 806         pf->vmdq = NULL;
 807 err:
 808         /* need to release fdir resource if exists */
 809         i40e_fdir_teardown(pf);
 810         return ret;
 811 }
 812
 813 void
 814 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 815 {
 816         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 817         uint16_t msix_vect = vsi->msix_intr;
 818         uint16_t i;
 819
 820         for (i = 0; i < vsi->nb_qps; i++) {
 821                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 822                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 823                 rte_wmb();
 824         }
 825
 826         if (vsi->type != I40E_VSI_SRIOV) {
 827                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 828                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 829                                 msix_vect - 1), 0);
 830         } else {
 831                 uint32_t reg;
 832                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 833                         vsi->user_param + (msix_vect - 1);
 834
 835                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 836         }
 837         I40E_WRITE_FLUSH(hw);
 838 }
 839
 840 static inline uint16_t
 841 i40e_calc_itr_interval(int16_t interval)
 842 {
 843         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 844                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 845
 846         /* Convert to hardware count, as writing each 1 represents 2 us */
 847         return (interval/2);
 848 }
 849
 850 void
 851 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 852 {
 853         uint32_t val;
 854         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 855         uint16_t msix_vect = vsi->msix_intr;
 856         int i;
 857
 858         for (i = 0; i < vsi->nb_qps; i++)
 859                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 860
 861         /* Bind all RX queues to allocated MSIX interrupt */
 862         for (i = 0; i < vsi->nb_qps; i++) {
 863                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 864                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 865                         ((vsi->base_queue + i + 1) <<
 866                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 867                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 868                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 869
 870                 if (i == vsi->nb_qps - 1)
 871                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 872                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 873         }
 874
 875         /* Write first RX queue to Link list register as the head element */
 876         if (vsi->type != I40E_VSI_SRIOV) {
 877                 uint16_t interval =
 878                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 879
 880                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 881                                                 (vsi->base_queue <<
 882                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 883                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 884
 885                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 886                                                 msix_vect - 1), interval);
 887
 888 #ifndef I40E_GLINT_CTL
 889 #define I40E_GLINT_CTL                     0x0003F800
 890 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 891 #endif
 892                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 893                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 894                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 895         } else {
 896                 uint32_t reg;
 897
 898                 /* num_msix_vectors_vf needs to minus irq0 */
 899                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 900                         vsi->user_param + (msix_vect - 1);
 901
 902                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 903                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 904                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 905         }
 906
 907         I40E_WRITE_FLUSH(hw);
 908 }
 909
 910 static void
 911 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 912 {
 913         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 914         uint16_t interval = i40e_calc_itr_interval(\
 915                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 916
 917         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 918                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 919                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 920                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 921                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 922 }
 923
 924 static void
 925 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 926 {
 927         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 928
 929         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 930 }
 931
 932 static inline uint8_t
 933 i40e_parse_link_speed(uint16_t eth_link_speed)
 934 {
 935         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 936
 937         switch (eth_link_speed) {
 938         case ETH_LINK_SPEED_40G:
 939                 link_speed = I40E_LINK_SPEED_40GB;
 940                 break;
 941         case ETH_LINK_SPEED_20G:
 942                 link_speed = I40E_LINK_SPEED_20GB;
 943                 break;
 944         case ETH_LINK_SPEED_10G:
 945                 link_speed = I40E_LINK_SPEED_10GB;
 946                 break;
 947         case ETH_LINK_SPEED_1000:
 948                 link_speed = I40E_LINK_SPEED_1GB;
 949                 break;
 950         case ETH_LINK_SPEED_100:
 951                 link_speed = I40E_LINK_SPEED_100MB;
 952                 break;
 953         }
 954
 955         return link_speed;
 956 }
 957
 958 static int
 959 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 960 {
 961         enum i40e_status_code status;
 962         struct i40e_aq_get_phy_abilities_resp phy_ab;
 963         struct i40e_aq_set_phy_config phy_conf;
 964         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 965                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 966                         I40E_AQ_PHY_FLAG_LOW_POWER;
 967         const uint8_t advt = I40E_LINK_SPEED_40GB |
 968                         I40E_LINK_SPEED_10GB |
 969                         I40E_LINK_SPEED_1GB |
 970                         I40E_LINK_SPEED_100MB;
 971         int ret = -ENOTSUP;
 972
 973         /* Skip it on 40G interfaces, as a workaround for the link issue */
 974         if (i40e_is_40G_device(hw->device_id))
 975                 return I40E_SUCCESS;
 976
 977         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 978                                               NULL);
 979         if (status)
 980                 return ret;
 981
 982         memset(&phy_conf, 0, sizeof(phy_conf));
 983
 984         /* bits 0-2 use the values from get_phy_abilities_resp */
 985         abilities &= ~mask;
 986         abilities |= phy_ab.abilities & mask;
 987
 988         /* update ablities and speed */
 989         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 990                 phy_conf.link_speed = advt;
 991         else
 992                 phy_conf.link_speed = force_speed;
 993
 994         phy_conf.abilities = abilities;
 995
 996         /* use get_phy_abilities_resp value for the rest */
 997         phy_conf.phy_type = phy_ab.phy_type;
 998         phy_conf.eee_capability = phy_ab.eee_capability;
 999         phy_conf.eeer = phy_ab.eeer_val;
1000         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1001
1002         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1003                     phy_ab.abilities, phy_ab.link_speed);
1004         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1005                     phy_conf.abilities, phy_conf.link_speed);
1006
1007         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1008         if (status)
1009                 return ret;
1010
1011         return I40E_SUCCESS;
1012 }
1013
1014 static int
1015 i40e_apply_link_speed(struct rte_eth_dev *dev)
1016 {
1017         uint8_t speed;
1018         uint8_t abilities = 0;
1019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         struct rte_eth_conf *conf = &dev->data->dev_conf;
1021
1022         speed = i40e_parse_link_speed(conf->link_speed);
1023         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1024         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1025                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1026         else
1027                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1028
1029         return i40e_phy_conf_link(hw, abilities, speed);
1030 }
1031
1032 static int
1033 i40e_dev_start(struct rte_eth_dev *dev)
1034 {
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *main_vsi = pf->main_vsi;
1038         int ret, i;
1039
1040         hw->adapter_stopped = 0;
1041
1042         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1043                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1044                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1045                              dev->data->dev_conf.link_duplex,
1046                              dev->data->port_id);
1047                 return -EINVAL;
1048         }
1049
1050         /* Initialize VSI */
1051         ret = i40e_dev_rxtx_init(pf);
1052         if (ret != I40E_SUCCESS) {
1053                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1054                 goto err_up;
1055         }
1056
1057         /* Map queues with MSIX interrupt */
1058         i40e_vsi_queues_bind_intr(main_vsi);
1059         i40e_vsi_enable_queues_intr(main_vsi);
1060
1061         /* Map VMDQ VSI queues with MSIX interrupt */
1062         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1063                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1064                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1065         }
1066
1067         /* enable FDIR MSIX interrupt */
1068         if (pf->fdir.fdir_vsi) {
1069                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1070                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1071         }
1072
1073         /* Enable all queues which have been configured */
1074         ret = i40e_dev_switch_queues(pf, TRUE);
1075         if (ret != I40E_SUCCESS) {
1076                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1077                 goto err_up;
1078         }
1079
1080         /* Enable receiving broadcast packets */
1081         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1082         if (ret != I40E_SUCCESS)
1083                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1084
1085         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1086                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1087                                                 true, NULL);
1088                 if (ret != I40E_SUCCESS)
1089                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1090         }
1091
1092         /* Apply link configure */
1093         ret = i40e_apply_link_speed(dev);
1094         if (I40E_SUCCESS != ret) {
1095                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1096                 goto err_up;
1097         }
1098
1099         return I40E_SUCCESS;
1100
1101 err_up:
1102         i40e_dev_switch_queues(pf, FALSE);
1103         i40e_dev_clear_queues(dev);
1104
1105         return ret;
1106 }
1107
1108 static void
1109 i40e_dev_stop(struct rte_eth_dev *dev)
1110 {
1111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1112         struct i40e_vsi *main_vsi = pf->main_vsi;
1113         struct i40e_mirror_rule *p_mirror;
1114         int i;
1115
1116         /* Disable all queues */
1117         i40e_dev_switch_queues(pf, FALSE);
1118
1119         /* un-map queues with interrupt registers */
1120         i40e_vsi_disable_queues_intr(main_vsi);
1121         i40e_vsi_queues_unbind_intr(main_vsi);
1122
1123         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1124                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1125                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1126         }
1127
1128         if (pf->fdir.fdir_vsi) {
1129                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1130                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1131         }
1132         /* Clear all queues and release memory */
1133         i40e_dev_clear_queues(dev);
1134
1135         /* Set link down */
1136         i40e_dev_set_link_down(dev);
1137
1138         /* Remove all mirror rules */
1139         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1140                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1141                 rte_free(p_mirror);
1142         }
1143         pf->nb_mirror_rule = 0;
1144
1145 }
1146
1147 static void
1148 i40e_dev_close(struct rte_eth_dev *dev)
1149 {
1150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152         uint32_t reg;
1153         int i;
1154
1155         PMD_INIT_FUNC_TRACE();
1156
1157         i40e_dev_stop(dev);
1158         hw->adapter_stopped = 1;
1159         i40e_dev_free_queues(dev);
1160
1161         /* Disable interrupt */
1162         i40e_pf_disable_irq0(hw);
1163         rte_intr_disable(&(dev->pci_dev->intr_handle));
1164
1165         /* shutdown and destroy the HMC */
1166         i40e_shutdown_lan_hmc(hw);
1167
1168         /* release all the existing VSIs and VEBs */
1169         i40e_fdir_teardown(pf);
1170         i40e_vsi_release(pf->main_vsi);
1171
1172         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1173                 i40e_vsi_release(pf->vmdq[i].vsi);
1174                 pf->vmdq[i].vsi = NULL;
1175         }
1176
1177         rte_free(pf->vmdq);
1178         pf->vmdq = NULL;
1179
1180         /* shutdown the adminq */
1181         i40e_aq_queue_shutdown(hw, true);
1182         i40e_shutdown_adminq(hw);
1183
1184         i40e_res_pool_destroy(&pf->qp_pool);
1185         i40e_res_pool_destroy(&pf->msix_pool);
1186
1187         /* force a PF reset to clean anything leftover */
1188         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1189         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1190                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1191         I40E_WRITE_FLUSH(hw);
1192 }
1193
1194 static void
1195 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1196 {
1197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199         struct i40e_vsi *vsi = pf->main_vsi;
1200         int status;
1201
1202         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1203                                                         true, NULL);
1204         if (status != I40E_SUCCESS)
1205                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1206
1207         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1208                                                         TRUE, NULL);
1209         if (status != I40E_SUCCESS)
1210                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1211
1212 }
1213
1214 static void
1215 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1216 {
1217         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219         struct i40e_vsi *vsi = pf->main_vsi;
1220         int status;
1221
1222         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1223                                                         false, NULL);
1224         if (status != I40E_SUCCESS)
1225                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1226
1227         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1228                                                         false, NULL);
1229         if (status != I40E_SUCCESS)
1230                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1231 }
1232
1233 static void
1234 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1235 {
1236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238         struct i40e_vsi *vsi = pf->main_vsi;
1239         int ret;
1240
1241         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1242         if (ret != I40E_SUCCESS)
1243                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1244 }
1245
1246 static void
1247 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1248 {
1249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251         struct i40e_vsi *vsi = pf->main_vsi;
1252         int ret;
1253
1254         if (dev->data->promiscuous == 1)
1255                 return; /* must remain in all_multicast mode */
1256
1257         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1258                                 vsi->seid, FALSE, NULL);
1259         if (ret != I40E_SUCCESS)
1260                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1261 }
1262
1263 /*
1264  * Set device link up.
1265  */
1266 static int
1267 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1268 {
1269         /* re-apply link speed setting */
1270         return i40e_apply_link_speed(dev);
1271 }
1272
1273 /*
1274  * Set device link down.
1275  */
1276 static int
1277 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1278 {
1279         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1280         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1282
1283         return i40e_phy_conf_link(hw, abilities, speed);
1284 }
1285
1286 int
1287 i40e_dev_link_update(struct rte_eth_dev *dev,
1288                      int wait_to_complete)
1289 {
1290 #define CHECK_INTERVAL 100  /* 100ms */
1291 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293         struct i40e_link_status link_status;
1294         struct rte_eth_link link, old;
1295         int status;
1296         unsigned rep_cnt = MAX_REPEAT_TIME;
1297
1298         memset(&link, 0, sizeof(link));
1299         memset(&old, 0, sizeof(old));
1300         memset(&link_status, 0, sizeof(link_status));
1301         rte_i40e_dev_atomic_read_link_status(dev, &old);
1302
1303         do {
1304                 /* Get link status information from hardware */
1305                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1306                 if (status != I40E_SUCCESS) {
1307                         link.link_speed = ETH_LINK_SPEED_100;
1308                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1309                         PMD_DRV_LOG(ERR, "Failed to get link info");
1310                         goto out;
1311                 }
1312
1313                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1314                 if (!wait_to_complete)
1315                         break;
1316
1317                 rte_delay_ms(CHECK_INTERVAL);
1318         } while (!link.link_status && rep_cnt--);
1319
1320         if (!link.link_status)
1321                 goto out;
1322
1323         /* i40e uses full duplex only */
1324         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1325
1326         /* Parse the link status */
1327         switch (link_status.link_speed) {
1328         case I40E_LINK_SPEED_100MB:
1329                 link.link_speed = ETH_LINK_SPEED_100;
1330                 break;
1331         case I40E_LINK_SPEED_1GB:
1332                 link.link_speed = ETH_LINK_SPEED_1000;
1333                 break;
1334         case I40E_LINK_SPEED_10GB:
1335                 link.link_speed = ETH_LINK_SPEED_10G;
1336                 break;
1337         case I40E_LINK_SPEED_20GB:
1338                 link.link_speed = ETH_LINK_SPEED_20G;
1339                 break;
1340         case I40E_LINK_SPEED_40GB:
1341                 link.link_speed = ETH_LINK_SPEED_40G;
1342                 break;
1343         default:
1344                 link.link_speed = ETH_LINK_SPEED_100;
1345                 break;
1346         }
1347
1348 out:
1349         rte_i40e_dev_atomic_write_link_status(dev, &link);
1350         if (link.link_status == old.link_status)
1351                 return -1;
1352
1353         return 0;
1354 }
1355
1356 /* Get all the statistics of a VSI */
1357 void
1358 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1359 {
1360         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1361         struct i40e_eth_stats *nes = &vsi->eth_stats;
1362         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1363         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1364
1365         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1366                             vsi->offset_loaded, &oes->rx_bytes,
1367                             &nes->rx_bytes);
1368         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1369                             vsi->offset_loaded, &oes->rx_unicast,
1370                             &nes->rx_unicast);
1371         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1372                             vsi->offset_loaded, &oes->rx_multicast,
1373                             &nes->rx_multicast);
1374         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1375                             vsi->offset_loaded, &oes->rx_broadcast,
1376                             &nes->rx_broadcast);
1377         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1378                             &oes->rx_discards, &nes->rx_discards);
1379         /* GLV_REPC not supported */
1380         /* GLV_RMPC not supported */
1381         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1382                             &oes->rx_unknown_protocol,
1383                             &nes->rx_unknown_protocol);
1384         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1385                             vsi->offset_loaded, &oes->tx_bytes,
1386                             &nes->tx_bytes);
1387         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1388                             vsi->offset_loaded, &oes->tx_unicast,
1389                             &nes->tx_unicast);
1390         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1391                             vsi->offset_loaded, &oes->tx_multicast,
1392                             &nes->tx_multicast);
1393         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1394                             vsi->offset_loaded,  &oes->tx_broadcast,
1395                             &nes->tx_broadcast);
1396         /* GLV_TDPC not supported */
1397         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1398                             &oes->tx_errors, &nes->tx_errors);
1399         vsi->offset_loaded = true;
1400
1401         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1402                     vsi->vsi_id);
1403         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1404         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1405         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1406         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1407         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1408         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1409                     nes->rx_unknown_protocol);
1410         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1411         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1412         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1413         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1414         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1415         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1416         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1417                     vsi->vsi_id);
1418 }
1419
1420 /* Get all statistics of a port */
1421 static void
1422 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1423 {
1424         uint32_t i;
1425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1426         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1427         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1428         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1429
1430         /* Get statistics of struct i40e_eth_stats */
1431         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1432                             I40E_GLPRT_GORCL(hw->port),
1433                             pf->offset_loaded, &os->eth.rx_bytes,
1434                             &ns->eth.rx_bytes);
1435         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1436                             I40E_GLPRT_UPRCL(hw->port),
1437                             pf->offset_loaded, &os->eth.rx_unicast,
1438                             &ns->eth.rx_unicast);
1439         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1440                             I40E_GLPRT_MPRCL(hw->port),
1441                             pf->offset_loaded, &os->eth.rx_multicast,
1442                             &ns->eth.rx_multicast);
1443         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1444                             I40E_GLPRT_BPRCL(hw->port),
1445                             pf->offset_loaded, &os->eth.rx_broadcast,
1446                             &ns->eth.rx_broadcast);
1447         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1448                             pf->offset_loaded, &os->eth.rx_discards,
1449                             &ns->eth.rx_discards);
1450         /* GLPRT_REPC not supported */
1451         /* GLPRT_RMPC not supported */
1452         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1453                             pf->offset_loaded,
1454                             &os->eth.rx_unknown_protocol,
1455                             &ns->eth.rx_unknown_protocol);
1456         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1457                             I40E_GLPRT_GOTCL(hw->port),
1458                             pf->offset_loaded, &os->eth.tx_bytes,
1459                             &ns->eth.tx_bytes);
1460         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1461                             I40E_GLPRT_UPTCL(hw->port),
1462                             pf->offset_loaded, &os->eth.tx_unicast,
1463                             &ns->eth.tx_unicast);
1464         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1465                             I40E_GLPRT_MPTCL(hw->port),
1466                             pf->offset_loaded, &os->eth.tx_multicast,
1467                             &ns->eth.tx_multicast);
1468         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1469                             I40E_GLPRT_BPTCL(hw->port),
1470                             pf->offset_loaded, &os->eth.tx_broadcast,
1471                             &ns->eth.tx_broadcast);
1472         /* GLPRT_TEPC not supported */
1473
1474         /* additional port specific stats */
1475         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1476                             pf->offset_loaded, &os->tx_dropped_link_down,
1477                             &ns->tx_dropped_link_down);
1478         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1479                             pf->offset_loaded, &os->crc_errors,
1480                             &ns->crc_errors);
1481         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1482                             pf->offset_loaded, &os->illegal_bytes,
1483                             &ns->illegal_bytes);
1484         /* GLPRT_ERRBC not supported */
1485         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1486                             pf->offset_loaded, &os->mac_local_faults,
1487                             &ns->mac_local_faults);
1488         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1489                             pf->offset_loaded, &os->mac_remote_faults,
1490                             &ns->mac_remote_faults);
1491         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1492                             pf->offset_loaded, &os->rx_length_errors,
1493                             &ns->rx_length_errors);
1494         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1495                             pf->offset_loaded, &os->link_xon_rx,
1496                             &ns->link_xon_rx);
1497         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1498                             pf->offset_loaded, &os->link_xoff_rx,
1499                             &ns->link_xoff_rx);
1500         for (i = 0; i < 8; i++) {
1501                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1502                                     pf->offset_loaded,
1503                                     &os->priority_xon_rx[i],
1504                                     &ns->priority_xon_rx[i]);
1505                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1506                                     pf->offset_loaded,
1507                                     &os->priority_xoff_rx[i],
1508                                     &ns->priority_xoff_rx[i]);
1509         }
1510         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1511                             pf->offset_loaded, &os->link_xon_tx,
1512                             &ns->link_xon_tx);
1513         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1514                             pf->offset_loaded, &os->link_xoff_tx,
1515                             &ns->link_xoff_tx);
1516         for (i = 0; i < 8; i++) {
1517                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1518                                     pf->offset_loaded,
1519                                     &os->priority_xon_tx[i],
1520                                     &ns->priority_xon_tx[i]);
1521                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1522                                     pf->offset_loaded,
1523                                     &os->priority_xoff_tx[i],
1524                                     &ns->priority_xoff_tx[i]);
1525                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1526                                     pf->offset_loaded,
1527                                     &os->priority_xon_2_xoff[i],
1528                                     &ns->priority_xon_2_xoff[i]);
1529         }
1530         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1531                             I40E_GLPRT_PRC64L(hw->port),
1532                             pf->offset_loaded, &os->rx_size_64,
1533                             &ns->rx_size_64);
1534         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1535                             I40E_GLPRT_PRC127L(hw->port),
1536                             pf->offset_loaded, &os->rx_size_127,
1537                             &ns->rx_size_127);
1538         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1539                             I40E_GLPRT_PRC255L(hw->port),
1540                             pf->offset_loaded, &os->rx_size_255,
1541                             &ns->rx_size_255);
1542         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1543                             I40E_GLPRT_PRC511L(hw->port),
1544                             pf->offset_loaded, &os->rx_size_511,
1545                             &ns->rx_size_511);
1546         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1547                             I40E_GLPRT_PRC1023L(hw->port),
1548                             pf->offset_loaded, &os->rx_size_1023,
1549                             &ns->rx_size_1023);
1550         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1551                             I40E_GLPRT_PRC1522L(hw->port),
1552                             pf->offset_loaded, &os->rx_size_1522,
1553                             &ns->rx_size_1522);
1554         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1555                             I40E_GLPRT_PRC9522L(hw->port),
1556                             pf->offset_loaded, &os->rx_size_big,
1557                             &ns->rx_size_big);
1558         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1559                             pf->offset_loaded, &os->rx_undersize,
1560                             &ns->rx_undersize);
1561         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1562                             pf->offset_loaded, &os->rx_fragments,
1563                             &ns->rx_fragments);
1564         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1565                             pf->offset_loaded, &os->rx_oversize,
1566                             &ns->rx_oversize);
1567         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1568                             pf->offset_loaded, &os->rx_jabber,
1569                             &ns->rx_jabber);
1570         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1571                             I40E_GLPRT_PTC64L(hw->port),
1572                             pf->offset_loaded, &os->tx_size_64,
1573                             &ns->tx_size_64);
1574         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1575                             I40E_GLPRT_PTC127L(hw->port),
1576                             pf->offset_loaded, &os->tx_size_127,
1577                             &ns->tx_size_127);
1578         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1579                             I40E_GLPRT_PTC255L(hw->port),
1580                             pf->offset_loaded, &os->tx_size_255,
1581                             &ns->tx_size_255);
1582         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1583                             I40E_GLPRT_PTC511L(hw->port),
1584                             pf->offset_loaded, &os->tx_size_511,
1585                             &ns->tx_size_511);
1586         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1587                             I40E_GLPRT_PTC1023L(hw->port),
1588                             pf->offset_loaded, &os->tx_size_1023,
1589                             &ns->tx_size_1023);
1590         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1591                             I40E_GLPRT_PTC1522L(hw->port),
1592                             pf->offset_loaded, &os->tx_size_1522,
1593                             &ns->tx_size_1522);
1594         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1595                             I40E_GLPRT_PTC9522L(hw->port),
1596                             pf->offset_loaded, &os->tx_size_big,
1597                             &ns->tx_size_big);
1598         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1599                            pf->offset_loaded,
1600                            &os->fd_sb_match, &ns->fd_sb_match);
1601         /* GLPRT_MSPDC not supported */
1602         /* GLPRT_XEC not supported */
1603
1604         pf->offset_loaded = true;
1605
1606         if (pf->main_vsi)
1607                 i40e_update_vsi_stats(pf->main_vsi);
1608
1609         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1610                                                 ns->eth.rx_broadcast;
1611         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1612                                                 ns->eth.tx_broadcast;
1613         stats->ibytes   = ns->eth.rx_bytes;
1614         stats->obytes   = ns->eth.tx_bytes;
1615         stats->oerrors  = ns->eth.tx_errors;
1616         stats->imcasts  = ns->eth.rx_multicast;
1617         stats->fdirmatch = ns->fd_sb_match;
1618
1619         /* Rx Errors */
1620         stats->ibadcrc  = ns->crc_errors;
1621         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1622                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1623         stats->imissed  = ns->eth.rx_discards;
1624         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1625
1626         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1627         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1628         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1629         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1630         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1631         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1632         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1633                     ns->eth.rx_unknown_protocol);
1634         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1635         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1636         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1637         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1638         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1639         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1640
1641         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1642                     ns->tx_dropped_link_down);
1643         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1644         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1645                     ns->illegal_bytes);
1646         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1647         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1648                     ns->mac_local_faults);
1649         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1650                     ns->mac_remote_faults);
1651         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1652                     ns->rx_length_errors);
1653         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1654         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1655         for (i = 0; i < 8; i++) {
1656                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1657                                 i, ns->priority_xon_rx[i]);
1658                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1659                                 i, ns->priority_xoff_rx[i]);
1660         }
1661         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1662         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1663         for (i = 0; i < 8; i++) {
1664                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1665                                 i, ns->priority_xon_tx[i]);
1666                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1667                                 i, ns->priority_xoff_tx[i]);
1668                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1669                                 i, ns->priority_xon_2_xoff[i]);
1670         }
1671         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1672         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1673         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1674         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1675         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1676         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1677         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1678         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1679         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1680         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1681         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1682         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1683         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1684         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1685         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1686         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1687         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1688         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1689         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1690                         ns->mac_short_packet_dropped);
1691         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1692                     ns->checksum_error);
1693         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1694         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1695 }
1696
1697 /* Reset the statistics */
1698 static void
1699 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1700 {
1701         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1702
1703         /* It results in reloading the start point of each counter */
1704         pf->offset_loaded = false;
1705 }
1706
1707 static int
1708 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1709                                  __rte_unused uint16_t queue_id,
1710                                  __rte_unused uint8_t stat_idx,
1711                                  __rte_unused uint8_t is_rx)
1712 {
1713         PMD_INIT_FUNC_TRACE();
1714
1715         return -ENOSYS;
1716 }
1717
1718 static void
1719 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1720 {
1721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1722         struct i40e_vsi *vsi = pf->main_vsi;
1723
1724         dev_info->max_rx_queues = vsi->nb_qps;
1725         dev_info->max_tx_queues = vsi->nb_qps;
1726         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1727         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1728         dev_info->max_mac_addrs = vsi->max_macaddrs;
1729         dev_info->max_vfs = dev->pci_dev->max_vfs;
1730         dev_info->rx_offload_capa =
1731                 DEV_RX_OFFLOAD_VLAN_STRIP |
1732                 DEV_RX_OFFLOAD_QINQ_STRIP |
1733                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1734                 DEV_RX_OFFLOAD_UDP_CKSUM |
1735                 DEV_RX_OFFLOAD_TCP_CKSUM;
1736         dev_info->tx_offload_capa =
1737                 DEV_TX_OFFLOAD_VLAN_INSERT |
1738                 DEV_TX_OFFLOAD_QINQ_INSERT |
1739                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1740                 DEV_TX_OFFLOAD_UDP_CKSUM |
1741                 DEV_TX_OFFLOAD_TCP_CKSUM |
1742                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1743                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1744                 DEV_TX_OFFLOAD_TCP_TSO;
1745         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1746                                                 sizeof(uint32_t);
1747         dev_info->reta_size = pf->hash_lut_size;
1748         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1749
1750         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1751                 .rx_thresh = {
1752                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1753                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1754                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1755                 },
1756                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1757                 .rx_drop_en = 0,
1758         };
1759
1760         dev_info->default_txconf = (struct rte_eth_txconf) {
1761                 .tx_thresh = {
1762                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1763                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1764                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1765                 },
1766                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1767                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1768                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1769                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1770         };
1771
1772         if (pf->flags & I40E_FLAG_VMDQ) {
1773                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1774                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1775                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1776                                                 pf->max_nb_vmdq_vsi;
1777                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1778                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1779                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1780         }
1781 }
1782
1783 static int
1784 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1785 {
1786         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1787         struct i40e_vsi *vsi = pf->main_vsi;
1788         PMD_INIT_FUNC_TRACE();
1789
1790         if (on)
1791                 return i40e_vsi_add_vlan(vsi, vlan_id);
1792         else
1793                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1794 }
1795
1796 static void
1797 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1798                    __rte_unused uint16_t tpid)
1799 {
1800         PMD_INIT_FUNC_TRACE();
1801 }
1802
1803 static void
1804 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1805 {
1806         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1807         struct i40e_vsi *vsi = pf->main_vsi;
1808
1809         if (mask & ETH_VLAN_STRIP_MASK) {
1810                 /* Enable or disable VLAN stripping */
1811                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1812                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1813                 else
1814                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1815         }
1816
1817         if (mask & ETH_VLAN_EXTEND_MASK) {
1818                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1819                         i40e_vsi_config_double_vlan(vsi, TRUE);
1820                 else
1821                         i40e_vsi_config_double_vlan(vsi, FALSE);
1822         }
1823 }
1824
1825 static void
1826 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1827                           __rte_unused uint16_t queue,
1828                           __rte_unused int on)
1829 {
1830         PMD_INIT_FUNC_TRACE();
1831 }
1832
1833 static int
1834 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1835 {
1836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1837         struct i40e_vsi *vsi = pf->main_vsi;
1838         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1839         struct i40e_vsi_vlan_pvid_info info;
1840
1841         memset(&info, 0, sizeof(info));
1842         info.on = on;
1843         if (info.on)
1844                 info.config.pvid = pvid;
1845         else {
1846                 info.config.reject.tagged =
1847                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1848                 info.config.reject.untagged =
1849                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1850         }
1851
1852         return i40e_vsi_vlan_pvid_set(vsi, &info);
1853 }
1854
1855 static int
1856 i40e_dev_led_on(struct rte_eth_dev *dev)
1857 {
1858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         uint32_t mode = i40e_led_get(hw);
1860
1861         if (mode == 0)
1862                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1863
1864         return 0;
1865 }
1866
1867 static int
1868 i40e_dev_led_off(struct rte_eth_dev *dev)
1869 {
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         uint32_t mode = i40e_led_get(hw);
1872
1873         if (mode != 0)
1874                 i40e_led_set(hw, 0, false);
1875
1876         return 0;
1877 }
1878
1879 static int
1880 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1881 {
1882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1884
1885         fc_conf->pause_time = pf->fc_conf.pause_time;
1886         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
1887         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
1888
1889          /* Return current mode according to actual setting*/
1890         switch (hw->fc.current_mode) {
1891         case I40E_FC_FULL:
1892                 fc_conf->mode = RTE_FC_FULL;
1893                 break;
1894         case I40E_FC_TX_PAUSE:
1895                 fc_conf->mode = RTE_FC_TX_PAUSE;
1896                 break;
1897         case I40E_FC_RX_PAUSE:
1898                 fc_conf->mode = RTE_FC_RX_PAUSE;
1899                 break;
1900         case I40E_FC_NONE:
1901         default:
1902                 fc_conf->mode = RTE_FC_NONE;
1903         };
1904
1905         return 0;
1906 }
1907
1908 static int
1909 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1910 {
1911         uint32_t mflcn_reg, fctrl_reg, reg;
1912         uint32_t max_high_water;
1913         uint8_t i, aq_failure;
1914         int err;
1915         struct i40e_hw *hw;
1916         struct i40e_pf *pf;
1917         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
1918                 [RTE_FC_NONE] = I40E_FC_NONE,
1919                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
1920                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
1921                 [RTE_FC_FULL] = I40E_FC_FULL
1922         };
1923
1924         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
1925
1926         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
1927         if ((fc_conf->high_water > max_high_water) ||
1928                         (fc_conf->high_water < fc_conf->low_water)) {
1929                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
1930                         "High_water must <= %d.", max_high_water);
1931                 return -EINVAL;
1932         }
1933
1934         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1936         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
1937
1938         pf->fc_conf.pause_time = fc_conf->pause_time;
1939         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
1940         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
1941
1942         PMD_INIT_FUNC_TRACE();
1943
1944         /* All the link flow control related enable/disable register
1945          * configuration is handle by the F/W
1946          */
1947         err = i40e_set_fc(hw, &aq_failure, true);
1948         if (err < 0)
1949                 return -ENOSYS;
1950
1951         if (i40e_is_40G_device(hw->device_id)) {
1952                 /* Configure flow control refresh threshold,
1953                  * the value for stat_tx_pause_refresh_timer[8]
1954                  * is used for global pause operation.
1955                  */
1956
1957                 I40E_WRITE_REG(hw,
1958                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
1959                                pf->fc_conf.pause_time);
1960
1961                 /* configure the timer value included in transmitted pause
1962                  * frame,
1963                  * the value for stat_tx_pause_quanta[8] is used for global
1964                  * pause operation
1965                  */
1966                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
1967                                pf->fc_conf.pause_time);
1968
1969                 fctrl_reg = I40E_READ_REG(hw,
1970                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
1971
1972                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1973                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
1974                 else
1975                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
1976
1977                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
1978                                fctrl_reg);
1979         } else {
1980                 /* Configure pause time (2 TCs per register) */
1981                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
1982                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
1983                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
1984
1985                 /* Configure flow control refresh threshold value */
1986                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
1987                                pf->fc_conf.pause_time / 2);
1988
1989                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
1990
1991                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
1992                  *depending on configuration
1993                  */
1994                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
1995                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
1996                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
1997                 } else {
1998                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
1999                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2000                 }
2001
2002                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2003         }
2004
2005         /* config the water marker both based on the packets and bytes */
2006         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2007                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2008                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2009         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2010                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2011                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2012         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2013                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2014                        << I40E_KILOSHIFT);
2015         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2016                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2017                        << I40E_KILOSHIFT);
2018
2019         I40E_WRITE_FLUSH(hw);
2020
2021         return 0;
2022 }
2023
2024 static int
2025 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2026                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2027 {
2028         PMD_INIT_FUNC_TRACE();
2029
2030         return -ENOSYS;
2031 }
2032
2033 /* Add a MAC address, and update filters */
2034 static void
2035 i40e_macaddr_add(struct rte_eth_dev *dev,
2036                  struct ether_addr *mac_addr,
2037                  __rte_unused uint32_t index,
2038                  uint32_t pool)
2039 {
2040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041         struct i40e_mac_filter_info mac_filter;
2042         struct i40e_vsi *vsi;
2043         int ret;
2044
2045         /* If VMDQ not enabled or configured, return */
2046         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2047                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2048                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2049                         pool);
2050                 return;
2051         }
2052
2053         if (pool > pf->nb_cfg_vmdq_vsi) {
2054                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2055                                 pool, pf->nb_cfg_vmdq_vsi);
2056                 return;
2057         }
2058
2059         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2060         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2061
2062         if (pool == 0)
2063                 vsi = pf->main_vsi;
2064         else
2065                 vsi = pf->vmdq[pool - 1].vsi;
2066
2067         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2068         if (ret != I40E_SUCCESS) {
2069                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2070                 return;
2071         }
2072 }
2073
2074 /* Remove a MAC address, and update filters */
2075 static void
2076 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2077 {
2078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2079         struct i40e_vsi *vsi;
2080         struct rte_eth_dev_data *data = dev->data;
2081         struct ether_addr *macaddr;
2082         int ret;
2083         uint32_t i;
2084         uint64_t pool_sel;
2085
2086         macaddr = &(data->mac_addrs[index]);
2087
2088         pool_sel = dev->data->mac_pool_sel[index];
2089
2090         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2091                 if (pool_sel & (1ULL << i)) {
2092                         if (i == 0)
2093                                 vsi = pf->main_vsi;
2094                         else {
2095                                 /* No VMDQ pool enabled or configured */
2096                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2097                                         (i > pf->nb_cfg_vmdq_vsi)) {
2098                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2099                                                         "/configured");
2100                                         return;
2101                                 }
2102                                 vsi = pf->vmdq[i - 1].vsi;
2103                         }
2104                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2105
2106                         if (ret) {
2107                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2108                                 return;
2109                         }
2110                 }
2111         }
2112 }
2113
2114 /* Set perfect match or hash match of MAC and VLAN for a VF */
2115 static int
2116 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2117                  struct rte_eth_mac_filter *filter,
2118                  bool add)
2119 {
2120         struct i40e_hw *hw;
2121         struct i40e_mac_filter_info mac_filter;
2122         struct ether_addr old_mac;
2123         struct ether_addr *new_mac;
2124         struct i40e_pf_vf *vf = NULL;
2125         uint16_t vf_id;
2126         int ret;
2127
2128         if (pf == NULL) {
2129                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2130                 return -EINVAL;
2131         }
2132         hw = I40E_PF_TO_HW(pf);
2133
2134         if (filter == NULL) {
2135                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2136                 return -EINVAL;
2137         }
2138
2139         new_mac = &filter->mac_addr;
2140
2141         if (is_zero_ether_addr(new_mac)) {
2142                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2143                 return -EINVAL;
2144         }
2145
2146         vf_id = filter->dst_id;
2147
2148         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2149                 PMD_DRV_LOG(ERR, "Invalid argument.");
2150                 return -EINVAL;
2151         }
2152         vf = &pf->vfs[vf_id];
2153
2154         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2155                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2156                 return -EINVAL;
2157         }
2158
2159         if (add) {
2160                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2161                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2162                                 ETHER_ADDR_LEN);
2163                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2164                                  ETHER_ADDR_LEN);
2165
2166                 mac_filter.filter_type = filter->filter_type;
2167                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2168                 if (ret != I40E_SUCCESS) {
2169                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2170                         return -1;
2171                 }
2172                 ether_addr_copy(new_mac, &pf->dev_addr);
2173         } else {
2174                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2175                                 ETHER_ADDR_LEN);
2176                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2177                 if (ret != I40E_SUCCESS) {
2178                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2179                         return -1;
2180                 }
2181
2182                 /* Clear device address as it has been removed */
2183                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2184                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2185         }
2186
2187         return 0;
2188 }
2189
2190 /* MAC filter handle */
2191 static int
2192 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2193                 void *arg)
2194 {
2195         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2196         struct rte_eth_mac_filter *filter;
2197         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2198         int ret = I40E_NOT_SUPPORTED;
2199
2200         filter = (struct rte_eth_mac_filter *)(arg);
2201
2202         switch (filter_op) {
2203         case RTE_ETH_FILTER_NOP:
2204                 ret = I40E_SUCCESS;
2205                 break;
2206         case RTE_ETH_FILTER_ADD:
2207                 i40e_pf_disable_irq0(hw);
2208                 if (filter->is_vf)
2209                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2210                 i40e_pf_enable_irq0(hw);
2211                 break;
2212         case RTE_ETH_FILTER_DELETE:
2213                 i40e_pf_disable_irq0(hw);
2214                 if (filter->is_vf)
2215                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2216                 i40e_pf_enable_irq0(hw);
2217                 break;
2218         default:
2219                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2220                 ret = I40E_ERR_PARAM;
2221                 break;
2222         }
2223
2224         return ret;
2225 }
2226
2227 static int
2228 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2229                          struct rte_eth_rss_reta_entry64 *reta_conf,
2230                          uint16_t reta_size)
2231 {
2232         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234         uint32_t lut, l;
2235         uint16_t i, j, lut_size = pf->hash_lut_size;
2236         uint16_t idx, shift;
2237         uint8_t mask;
2238
2239         if (reta_size != lut_size ||
2240                 reta_size > ETH_RSS_RETA_SIZE_512) {
2241                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2242                         "(%d) doesn't match the number hardware can supported "
2243                                         "(%d)\n", reta_size, lut_size);
2244                 return -EINVAL;
2245         }
2246
2247         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2248                 idx = i / RTE_RETA_GROUP_SIZE;
2249                 shift = i % RTE_RETA_GROUP_SIZE;
2250                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2251                                                 I40E_4_BIT_MASK);
2252                 if (!mask)
2253                         continue;
2254                 if (mask == I40E_4_BIT_MASK)
2255                         l = 0;
2256                 else
2257                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2258                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2259                         if (mask & (0x1 << j))
2260                                 lut |= reta_conf[idx].reta[shift + j] <<
2261                                                         (CHAR_BIT * j);
2262                         else
2263                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2264                 }
2265                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2266         }
2267
2268         return 0;
2269 }
2270
2271 static int
2272 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2273                         struct rte_eth_rss_reta_entry64 *reta_conf,
2274                         uint16_t reta_size)
2275 {
2276         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2277         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2278         uint32_t lut;
2279         uint16_t i, j, lut_size = pf->hash_lut_size;
2280         uint16_t idx, shift;
2281         uint8_t mask;
2282
2283         if (reta_size != lut_size ||
2284                 reta_size > ETH_RSS_RETA_SIZE_512) {
2285                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2286                         "(%d) doesn't match the number hardware can supported "
2287                                         "(%d)\n", reta_size, lut_size);
2288                 return -EINVAL;
2289         }
2290
2291         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2292                 idx = i / RTE_RETA_GROUP_SIZE;
2293                 shift = i % RTE_RETA_GROUP_SIZE;
2294                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2295                                                 I40E_4_BIT_MASK);
2296                 if (!mask)
2297                         continue;
2298
2299                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2300                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2301                         if (mask & (0x1 << j))
2302                                 reta_conf[idx].reta[shift + j] = ((lut >>
2303                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2304                 }
2305         }
2306
2307         return 0;
2308 }
2309
2310 /**
2311  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2312  * @hw:   pointer to the HW structure
2313  * @mem:  pointer to mem struct to fill out
2314  * @size: size of memory requested
2315  * @alignment: what to align the allocation to
2316  **/
2317 enum i40e_status_code
2318 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2319                         struct i40e_dma_mem *mem,
2320                         u64 size,
2321                         u32 alignment)
2322 {
2323         static uint64_t id = 0;
2324         const struct rte_memzone *mz = NULL;
2325         char z_name[RTE_MEMZONE_NAMESIZE];
2326
2327         if (!mem)
2328                 return I40E_ERR_PARAM;
2329
2330         id++;
2331         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2332 #ifdef RTE_LIBRTE_XEN_DOM0
2333         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2334                                          alignment, RTE_PGSIZE_2M);
2335 #else
2336         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2337                                          alignment);
2338 #endif
2339         if (!mz)
2340                 return I40E_ERR_NO_MEMORY;
2341
2342         mem->id = id;
2343         mem->size = size;
2344         mem->va = mz->addr;
2345 #ifdef RTE_LIBRTE_XEN_DOM0
2346         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2347 #else
2348         mem->pa = mz->phys_addr;
2349 #endif
2350
2351         return I40E_SUCCESS;
2352 }
2353
2354 /**
2355  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2356  * @hw:   pointer to the HW structure
2357  * @mem:  ptr to mem struct to free
2358  **/
2359 enum i40e_status_code
2360 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2361                     struct i40e_dma_mem *mem)
2362 {
2363         if (!mem || !mem->va)
2364                 return I40E_ERR_PARAM;
2365
2366         mem->va = NULL;
2367         mem->pa = (u64)0;
2368
2369         return I40E_SUCCESS;
2370 }
2371
2372 /**
2373  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2374  * @hw:   pointer to the HW structure
2375  * @mem:  pointer to mem struct to fill out
2376  * @size: size of memory requested
2377  **/
2378 enum i40e_status_code
2379 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2380                          struct i40e_virt_mem *mem,
2381                          u32 size)
2382 {
2383         if (!mem)
2384                 return I40E_ERR_PARAM;
2385
2386         mem->size = size;
2387         mem->va = rte_zmalloc("i40e", size, 0);
2388
2389         if (mem->va)
2390                 return I40E_SUCCESS;
2391         else
2392                 return I40E_ERR_NO_MEMORY;
2393 }
2394
2395 /**
2396  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2397  * @hw:   pointer to the HW structure
2398  * @mem:  pointer to mem struct to free
2399  **/
2400 enum i40e_status_code
2401 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2402                      struct i40e_virt_mem *mem)
2403 {
2404         if (!mem)
2405                 return I40E_ERR_PARAM;
2406
2407         rte_free(mem->va);
2408         mem->va = NULL;
2409
2410         return I40E_SUCCESS;
2411 }
2412
2413 void
2414 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2415 {
2416         rte_spinlock_init(&sp->spinlock);
2417 }
2418
2419 void
2420 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2421 {
2422         rte_spinlock_lock(&sp->spinlock);
2423 }
2424
2425 void
2426 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2427 {
2428         rte_spinlock_unlock(&sp->spinlock);
2429 }
2430
2431 void
2432 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2433 {
2434         return;
2435 }
2436
2437 /**
2438  * Get the hardware capabilities, which will be parsed
2439  * and saved into struct i40e_hw.
2440  */
2441 static int
2442 i40e_get_cap(struct i40e_hw *hw)
2443 {
2444         struct i40e_aqc_list_capabilities_element_resp *buf;
2445         uint16_t len, size = 0;
2446         int ret;
2447
2448         /* Calculate a huge enough buff for saving response data temporarily */
2449         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2450                                                 I40E_MAX_CAP_ELE_NUM;
2451         buf = rte_zmalloc("i40e", len, 0);
2452         if (!buf) {
2453                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2454                 return I40E_ERR_NO_MEMORY;
2455         }
2456
2457         /* Get, parse the capabilities and save it to hw */
2458         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2459                         i40e_aqc_opc_list_func_capabilities, NULL);
2460         if (ret != I40E_SUCCESS)
2461                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2462
2463         /* Free the temporary buffer after being used */
2464         rte_free(buf);
2465
2466         return ret;
2467 }
2468
2469 static int
2470 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2471 {
2472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2473         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2474         uint16_t sum_queues = 0, sum_vsis, left_queues;
2475
2476         /* First check if FW support SRIOV */
2477         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2478                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2479                 return -EINVAL;
2480         }
2481         /* Add the parameter init for LFC */
2482         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2483         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2484         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2485
2486         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2487         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2488         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2489         /* Allocate queues for pf */
2490         if (hw->func_caps.rss) {
2491                 pf->flags |= I40E_FLAG_RSS;
2492                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2493                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2494                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2495         } else
2496                 pf->lan_nb_qps = 1;
2497         sum_queues = pf->lan_nb_qps;
2498         /* Default VSI is not counted in */
2499         sum_vsis = 0;
2500         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2501
2502         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2503                 pf->flags |= I40E_FLAG_SRIOV;
2504                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2505                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2506                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2507                                      "max supported %u.",
2508                                      dev->pci_dev->max_vfs,
2509                                      hw->func_caps.num_vfs);
2510                         return -EINVAL;
2511                 }
2512                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2513                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2514                                      "max support %u queues.",
2515                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2516                         return -EINVAL;
2517                 }
2518                 pf->vf_num = dev->pci_dev->max_vfs;
2519                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2520                 sum_vsis   += pf->vf_num;
2521                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2522                              pf->vf_num, pf->vf_nb_qps);
2523         } else
2524                 pf->vf_num = 0;
2525
2526         if (hw->func_caps.vmdq) {
2527                 pf->flags |= I40E_FLAG_VMDQ;
2528                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2529                 pf->max_nb_vmdq_vsi = 1;
2530                 /*
2531                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2532                  * later.
2533                  */
2534                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2535                 sum_vsis += pf->max_nb_vmdq_vsi;
2536         } else {
2537                 pf->vmdq_nb_qps = 0;
2538                 pf->max_nb_vmdq_vsi = 0;
2539         }
2540         pf->nb_cfg_vmdq_vsi = 0;
2541
2542         if (hw->func_caps.fd) {
2543                 pf->flags |= I40E_FLAG_FDIR;
2544                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2545                 /**
2546                  * Each flow director consumes one VSI and one queue,
2547                  * but can't calculate out predictably here.
2548                  */
2549         }
2550
2551         if (hw->func_caps.dcb)
2552                 pf->flags |= I40E_FLAG_DCB;
2553
2554         if (sum_vsis > pf->max_num_vsi ||
2555                 sum_queues > hw->func_caps.num_rx_qp) {
2556                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2557                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2558                              pf->max_num_vsi, sum_vsis);
2559                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2560                              hw->func_caps.num_rx_qp, sum_queues);
2561                 return -EINVAL;
2562         }
2563
2564         /* Adjust VMDQ setting to support as many VMs as possible */
2565         if (pf->flags & I40E_FLAG_VMDQ) {
2566                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2567
2568                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2569                                         pf->max_num_vsi - sum_vsis);
2570
2571                 /* Limit the max VMDQ number that rte_ether that can support  */
2572                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2573                                         ETH_64_POOLS - 1);
2574
2575                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2576                                 pf->max_nb_vmdq_vsi);
2577                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2578         }
2579
2580         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2581          * cause */
2582         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2583                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2584                              sum_vsis, hw->func_caps.num_msix_vectors);
2585                 return -EINVAL;
2586         }
2587         return I40E_SUCCESS;
2588 }
2589
2590 static int
2591 i40e_pf_get_switch_config(struct i40e_pf *pf)
2592 {
2593         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2594         struct i40e_aqc_get_switch_config_resp *switch_config;
2595         struct i40e_aqc_switch_config_element_resp *element;
2596         uint16_t start_seid = 0, num_reported;
2597         int ret;
2598
2599         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2600                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2601         if (!switch_config) {
2602                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2603                 return -ENOMEM;
2604         }
2605
2606         /* Get the switch configurations */
2607         ret = i40e_aq_get_switch_config(hw, switch_config,
2608                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2609         if (ret != I40E_SUCCESS) {
2610                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2611                 goto fail;
2612         }
2613         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2614         if (num_reported != 1) { /* The number should be 1 */
2615                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2616                 goto fail;
2617         }
2618
2619         /* Parse the switch configuration elements */
2620         element = &(switch_config->element[0]);
2621         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2622                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2623                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2624         } else
2625                 PMD_DRV_LOG(INFO, "Unknown element type");
2626
2627 fail:
2628         rte_free(switch_config);
2629
2630         return ret;
2631 }
2632
2633 static int
2634 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2635                         uint32_t num)
2636 {
2637         struct pool_entry *entry;
2638
2639         if (pool == NULL || num == 0)
2640                 return -EINVAL;
2641
2642         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2643         if (entry == NULL) {
2644                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2645                 return -ENOMEM;
2646         }
2647
2648         /* queue heap initialize */
2649         pool->num_free = num;
2650         pool->num_alloc = 0;
2651         pool->base = base;
2652         LIST_INIT(&pool->alloc_list);
2653         LIST_INIT(&pool->free_list);
2654
2655         /* Initialize element  */
2656         entry->base = 0;
2657         entry->len = num;
2658
2659         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2660         return 0;
2661 }
2662
2663 static void
2664 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2665 {
2666         struct pool_entry *entry;
2667
2668         if (pool == NULL)
2669                 return;
2670
2671         LIST_FOREACH(entry, &pool->alloc_list, next) {
2672                 LIST_REMOVE(entry, next);
2673                 rte_free(entry);
2674         }
2675
2676         LIST_FOREACH(entry, &pool->free_list, next) {
2677                 LIST_REMOVE(entry, next);
2678                 rte_free(entry);
2679         }
2680
2681         pool->num_free = 0;
2682         pool->num_alloc = 0;
2683         pool->base = 0;
2684         LIST_INIT(&pool->alloc_list);
2685         LIST_INIT(&pool->free_list);
2686 }
2687
2688 static int
2689 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2690                        uint32_t base)
2691 {
2692         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2693         uint32_t pool_offset;
2694         int insert;
2695
2696         if (pool == NULL) {
2697                 PMD_DRV_LOG(ERR, "Invalid parameter");
2698                 return -EINVAL;
2699         }
2700
2701         pool_offset = base - pool->base;
2702         /* Lookup in alloc list */
2703         LIST_FOREACH(entry, &pool->alloc_list, next) {
2704                 if (entry->base == pool_offset) {
2705                         valid_entry = entry;
2706                         LIST_REMOVE(entry, next);
2707                         break;
2708                 }
2709         }
2710
2711         /* Not find, return */
2712         if (valid_entry == NULL) {
2713                 PMD_DRV_LOG(ERR, "Failed to find entry");
2714                 return -EINVAL;
2715         }
2716
2717         /**
2718          * Found it, move it to free list  and try to merge.
2719          * In order to make merge easier, always sort it by qbase.
2720          * Find adjacent prev and last entries.
2721          */
2722         prev = next = NULL;
2723         LIST_FOREACH(entry, &pool->free_list, next) {
2724                 if (entry->base > valid_entry->base) {
2725                         next = entry;
2726                         break;
2727                 }
2728                 prev = entry;
2729         }
2730
2731         insert = 0;
2732         /* Try to merge with next one*/
2733         if (next != NULL) {
2734                 /* Merge with next one */
2735                 if (valid_entry->base + valid_entry->len == next->base) {
2736                         next->base = valid_entry->base;
2737                         next->len += valid_entry->len;
2738                         rte_free(valid_entry);
2739                         valid_entry = next;
2740                         insert = 1;
2741                 }
2742         }
2743
2744         if (prev != NULL) {
2745                 /* Merge with previous one */
2746                 if (prev->base + prev->len == valid_entry->base) {
2747                         prev->len += valid_entry->len;
2748                         /* If it merge with next one, remove next node */
2749                         if (insert == 1) {
2750                                 LIST_REMOVE(valid_entry, next);
2751                                 rte_free(valid_entry);
2752                         } else {
2753                                 rte_free(valid_entry);
2754                                 insert = 1;
2755                         }
2756                 }
2757         }
2758
2759         /* Not find any entry to merge, insert */
2760         if (insert == 0) {
2761                 if (prev != NULL)
2762                         LIST_INSERT_AFTER(prev, valid_entry, next);
2763                 else if (next != NULL)
2764                         LIST_INSERT_BEFORE(next, valid_entry, next);
2765                 else /* It's empty list, insert to head */
2766                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2767         }
2768
2769         pool->num_free += valid_entry->len;
2770         pool->num_alloc -= valid_entry->len;
2771
2772         return 0;
2773 }
2774
2775 static int
2776 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2777                        uint16_t num)
2778 {
2779         struct pool_entry *entry, *valid_entry;
2780
2781         if (pool == NULL || num == 0) {
2782                 PMD_DRV_LOG(ERR, "Invalid parameter");
2783                 return -EINVAL;
2784         }
2785
2786         if (pool->num_free < num) {
2787                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2788                             num, pool->num_free);
2789                 return -ENOMEM;
2790         }
2791
2792         valid_entry = NULL;
2793         /* Lookup  in free list and find most fit one */
2794         LIST_FOREACH(entry, &pool->free_list, next) {
2795                 if (entry->len >= num) {
2796                         /* Find best one */
2797                         if (entry->len == num) {
2798                                 valid_entry = entry;
2799                                 break;
2800                         }
2801                         if (valid_entry == NULL || valid_entry->len > entry->len)
2802                                 valid_entry = entry;
2803                 }
2804         }
2805
2806         /* Not find one to satisfy the request, return */
2807         if (valid_entry == NULL) {
2808                 PMD_DRV_LOG(ERR, "No valid entry found");
2809                 return -ENOMEM;
2810         }
2811         /**
2812          * The entry have equal queue number as requested,
2813          * remove it from alloc_list.
2814          */
2815         if (valid_entry->len == num) {
2816                 LIST_REMOVE(valid_entry, next);
2817         } else {
2818                 /**
2819                  * The entry have more numbers than requested,
2820                  * create a new entry for alloc_list and minus its
2821                  * queue base and number in free_list.
2822                  */
2823                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2824                 if (entry == NULL) {
2825                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2826                                     "resource pool");
2827                         return -ENOMEM;
2828                 }
2829                 entry->base = valid_entry->base;
2830                 entry->len = num;
2831                 valid_entry->base += num;
2832                 valid_entry->len -= num;
2833                 valid_entry = entry;
2834         }
2835
2836         /* Insert it into alloc list, not sorted */
2837         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2838
2839         pool->num_free -= valid_entry->len;
2840         pool->num_alloc += valid_entry->len;
2841
2842         return (valid_entry->base + pool->base);
2843 }
2844
2845 /**
2846  * bitmap_is_subset - Check whether src2 is subset of src1
2847  **/
2848 static inline int
2849 bitmap_is_subset(uint8_t src1, uint8_t src2)
2850 {
2851         return !((src1 ^ src2) & src2);
2852 }
2853
2854 static int
2855 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2856 {
2857         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2858
2859         /* If DCB is not supported, only default TC is supported */
2860         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2861                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2862                 return -EINVAL;
2863         }
2864
2865         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2866                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2867                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2868                             enabled_tcmap);
2869                 return -EINVAL;
2870         }
2871         return I40E_SUCCESS;
2872 }
2873
2874 int
2875 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2876                                 struct i40e_vsi_vlan_pvid_info *info)
2877 {
2878         struct i40e_hw *hw;
2879         struct i40e_vsi_context ctxt;
2880         uint8_t vlan_flags = 0;
2881         int ret;
2882
2883         if (vsi == NULL || info == NULL) {
2884                 PMD_DRV_LOG(ERR, "invalid parameters");
2885                 return I40E_ERR_PARAM;
2886         }
2887
2888         if (info->on) {
2889                 vsi->info.pvid = info->config.pvid;
2890                 /**
2891                  * If insert pvid is enabled, only tagged pkts are
2892                  * allowed to be sent out.
2893                  */
2894                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2895                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2896         } else {
2897                 vsi->info.pvid = 0;
2898                 if (info->config.reject.tagged == 0)
2899                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2900
2901                 if (info->config.reject.untagged == 0)
2902                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2903         }
2904         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2905                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2906         vsi->info.port_vlan_flags |= vlan_flags;
2907         vsi->info.valid_sections =
2908                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2909         memset(&ctxt, 0, sizeof(ctxt));
2910         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2911         ctxt.seid = vsi->seid;
2912
2913         hw = I40E_VSI_TO_HW(vsi);
2914         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2915         if (ret != I40E_SUCCESS)
2916                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2917
2918         return ret;
2919 }
2920
2921 static int
2922 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2923 {
2924         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2925         int i, ret;
2926         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2927
2928         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2929         if (ret != I40E_SUCCESS)
2930                 return ret;
2931
2932         if (!vsi->seid) {
2933                 PMD_DRV_LOG(ERR, "seid not valid");
2934                 return -EINVAL;
2935         }
2936
2937         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2938         tc_bw_data.tc_valid_bits = enabled_tcmap;
2939         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2940                 tc_bw_data.tc_bw_credits[i] =
2941                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2942
2943         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2944         if (ret != I40E_SUCCESS) {
2945                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2946                 return ret;
2947         }
2948
2949         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2950                                         sizeof(vsi->info.qs_handle));
2951         return I40E_SUCCESS;
2952 }
2953
2954 static int
2955 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2956                                  struct i40e_aqc_vsi_properties_data *info,
2957                                  uint8_t enabled_tcmap)
2958 {
2959         int ret, i, total_tc = 0;
2960         uint16_t qpnum_per_tc, bsf, qp_idx;
2961
2962         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2963         if (ret != I40E_SUCCESS)
2964                 return ret;
2965
2966         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2967                 if (enabled_tcmap & (1 << i))
2968                         total_tc++;
2969         vsi->enabled_tc = enabled_tcmap;
2970
2971         /* Number of queues per enabled TC */
2972         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2973         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2974         bsf = rte_bsf32(qpnum_per_tc);
2975
2976         /* Adjust the queue number to actual queues that can be applied */
2977         vsi->nb_qps = qpnum_per_tc * total_tc;
2978
2979         /**
2980          * Configure TC and queue mapping parameters, for enabled TC,
2981          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2982          * default queue will serve it.
2983          */
2984         qp_idx = 0;
2985         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2986                 if (vsi->enabled_tc & (1 << i)) {
2987                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2988                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2989                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2990                         qp_idx += qpnum_per_tc;
2991                 } else
2992                         info->tc_mapping[i] = 0;
2993         }
2994
2995         /* Associate queue number with VSI */
2996         if (vsi->type == I40E_VSI_SRIOV) {
2997                 info->mapping_flags |=
2998                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2999                 for (i = 0; i < vsi->nb_qps; i++)
3000                         info->queue_mapping[i] =
3001                                 rte_cpu_to_le_16(vsi->base_queue + i);
3002         } else {
3003                 info->mapping_flags |=
3004                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3005                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3006         }
3007         info->valid_sections |=
3008                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3009
3010         return I40E_SUCCESS;
3011 }
3012
3013 static int
3014 i40e_veb_release(struct i40e_veb *veb)
3015 {
3016         struct i40e_vsi *vsi;
3017         struct i40e_hw *hw;
3018
3019         if (veb == NULL || veb->associate_vsi == NULL)
3020                 return -EINVAL;
3021
3022         if (!TAILQ_EMPTY(&veb->head)) {
3023                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3024                 return -EACCES;
3025         }
3026
3027         vsi = veb->associate_vsi;
3028         hw = I40E_VSI_TO_HW(vsi);
3029
3030         vsi->uplink_seid = veb->uplink_seid;
3031         i40e_aq_delete_element(hw, veb->seid, NULL);
3032         rte_free(veb);
3033         vsi->veb = NULL;
3034         return I40E_SUCCESS;
3035 }
3036
3037 /* Setup a veb */
3038 static struct i40e_veb *
3039 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3040 {
3041         struct i40e_veb *veb;
3042         int ret;
3043         struct i40e_hw *hw;
3044
3045         if (NULL == pf || vsi == NULL) {
3046                 PMD_DRV_LOG(ERR, "veb setup failed, "
3047                             "associated VSI shouldn't null");
3048                 return NULL;
3049         }
3050         hw = I40E_PF_TO_HW(pf);
3051
3052         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3053         if (!veb) {
3054                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3055                 goto fail;
3056         }
3057
3058         veb->associate_vsi = vsi;
3059         TAILQ_INIT(&veb->head);
3060         veb->uplink_seid = vsi->uplink_seid;
3061
3062         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3063                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3064
3065         if (ret != I40E_SUCCESS) {
3066                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3067                             hw->aq.asq_last_status);
3068                 goto fail;
3069         }
3070
3071         /* get statistics index */
3072         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3073                                 &veb->stats_idx, NULL, NULL, NULL);
3074         if (ret != I40E_SUCCESS) {
3075                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3076                             hw->aq.asq_last_status);
3077                 goto fail;
3078         }
3079
3080         /* Get VEB bandwidth, to be implemented */
3081         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3082         vsi->uplink_seid = veb->seid;
3083
3084         return veb;
3085 fail:
3086         rte_free(veb);
3087         return NULL;
3088 }
3089
3090 int
3091 i40e_vsi_release(struct i40e_vsi *vsi)
3092 {
3093         struct i40e_pf *pf;
3094         struct i40e_hw *hw;
3095         struct i40e_vsi_list *vsi_list;
3096         int ret;
3097         struct i40e_mac_filter *f;
3098
3099         if (!vsi)
3100                 return I40E_SUCCESS;
3101
3102         pf = I40E_VSI_TO_PF(vsi);
3103         hw = I40E_VSI_TO_HW(vsi);
3104
3105         /* VSI has child to attach, release child first */
3106         if (vsi->veb) {
3107                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3108                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3109                                 return -1;
3110                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3111                 }
3112                 i40e_veb_release(vsi->veb);
3113         }
3114
3115         /* Remove all macvlan filters of the VSI */
3116         i40e_vsi_remove_all_macvlan_filter(vsi);
3117         TAILQ_FOREACH(f, &vsi->mac_list, next)
3118                 rte_free(f);
3119
3120         if (vsi->type != I40E_VSI_MAIN) {
3121                 /* Remove vsi from parent's sibling list */
3122                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3123                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3124                         return I40E_ERR_PARAM;
3125                 }
3126                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3127                                 &vsi->sib_vsi_list, list);
3128
3129                 /* Remove all switch element of the VSI */
3130                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3131                 if (ret != I40E_SUCCESS)
3132                         PMD_DRV_LOG(ERR, "Failed to delete element");
3133         }
3134         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3135
3136         if (vsi->type != I40E_VSI_SRIOV)
3137                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3138         rte_free(vsi);
3139
3140         return I40E_SUCCESS;
3141 }
3142
3143 static int
3144 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3145 {
3146         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3147         struct i40e_aqc_remove_macvlan_element_data def_filter;
3148         struct i40e_mac_filter_info filter;
3149         int ret;
3150
3151         if (vsi->type != I40E_VSI_MAIN)
3152                 return I40E_ERR_CONFIG;
3153         memset(&def_filter, 0, sizeof(def_filter));
3154         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3155                                         ETH_ADDR_LEN);
3156         def_filter.vlan_tag = 0;
3157         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3158                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3159         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3160         if (ret != I40E_SUCCESS) {
3161                 struct i40e_mac_filter *f;
3162                 struct ether_addr *mac;
3163
3164                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3165                             "macvlan filter");
3166                 /* It needs to add the permanent mac into mac list */
3167                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3168                 if (f == NULL) {
3169                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3170                         return I40E_ERR_NO_MEMORY;
3171                 }
3172                 mac = &f->mac_info.mac_addr;
3173                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3174                                 ETH_ADDR_LEN);
3175                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3176                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3177                 vsi->mac_num++;
3178
3179                 return ret;
3180         }
3181         (void)rte_memcpy(&filter.mac_addr,
3182                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3183         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3184         return i40e_vsi_add_mac(vsi, &filter);
3185 }
3186
3187 static int
3188 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3189 {
3190         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3191         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3192         struct i40e_hw *hw = &vsi->adapter->hw;
3193         i40e_status ret;
3194         int i;
3195
3196         memset(&bw_config, 0, sizeof(bw_config));
3197         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3198         if (ret != I40E_SUCCESS) {
3199                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3200                             hw->aq.asq_last_status);
3201                 return ret;
3202         }
3203
3204         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3205         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3206                                         &ets_sla_config, NULL);
3207         if (ret != I40E_SUCCESS) {
3208                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3209                             "configuration %u", hw->aq.asq_last_status);
3210                 return ret;
3211         }
3212
3213         /* Not store the info yet, just print out */
3214         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3215         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3216         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3217                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3218                             ets_sla_config.share_credits[i]);
3219                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3220                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3221                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3222                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3223                             (i * 4));
3224         }
3225
3226         return 0;
3227 }
3228
3229 /* Setup a VSI */
3230 struct i40e_vsi *
3231 i40e_vsi_setup(struct i40e_pf *pf,
3232                enum i40e_vsi_type type,
3233                struct i40e_vsi *uplink_vsi,
3234                uint16_t user_param)
3235 {
3236         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3237         struct i40e_vsi *vsi;
3238         struct i40e_mac_filter_info filter;
3239         int ret;
3240         struct i40e_vsi_context ctxt;
3241         struct ether_addr broadcast =
3242                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3243
3244         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3245                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3246                             "VSI link shouldn't be NULL");
3247                 return NULL;
3248         }
3249
3250         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3251                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3252                             "uplink VSI should be NULL");
3253                 return NULL;
3254         }
3255
3256         /* If uplink vsi didn't setup VEB, create one first */
3257         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3258                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3259
3260                 if (NULL == uplink_vsi->veb) {
3261                         PMD_DRV_LOG(ERR, "VEB setup failed");
3262                         return NULL;
3263                 }
3264         }
3265
3266         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3267         if (!vsi) {
3268                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3269                 return NULL;
3270         }
3271         TAILQ_INIT(&vsi->mac_list);
3272         vsi->type = type;
3273         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3274         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3275         vsi->parent_vsi = uplink_vsi;
3276         vsi->user_param = user_param;
3277         /* Allocate queues */
3278         switch (vsi->type) {
3279         case I40E_VSI_MAIN  :
3280                 vsi->nb_qps = pf->lan_nb_qps;
3281                 break;
3282         case I40E_VSI_SRIOV :
3283                 vsi->nb_qps = pf->vf_nb_qps;
3284                 break;
3285         case I40E_VSI_VMDQ2:
3286                 vsi->nb_qps = pf->vmdq_nb_qps;
3287                 break;
3288         case I40E_VSI_FDIR:
3289                 vsi->nb_qps = pf->fdir_nb_qps;
3290                 break;
3291         default:
3292                 goto fail_mem;
3293         }
3294         /*
3295          * The filter status descriptor is reported in rx queue 0,
3296          * while the tx queue for fdir filter programming has no
3297          * such constraints, can be non-zero queues.
3298          * To simplify it, choose FDIR vsi use queue 0 pair.
3299          * To make sure it will use queue 0 pair, queue allocation
3300          * need be done before this function is called
3301          */
3302         if (type != I40E_VSI_FDIR) {
3303                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3304                         if (ret < 0) {
3305                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3306                                                 vsi->seid, ret);
3307                                 goto fail_mem;
3308                         }
3309                         vsi->base_queue = ret;
3310         } else
3311                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3312
3313         /* VF has MSIX interrupt in VF range, don't allocate here */
3314         if (type != I40E_VSI_SRIOV) {
3315                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3316                 if (ret < 0) {
3317                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3318                         goto fail_queue_alloc;
3319                 }
3320                 vsi->msix_intr = ret;
3321         } else
3322                 vsi->msix_intr = 0;
3323         /* Add VSI */
3324         if (type == I40E_VSI_MAIN) {
3325                 /* For main VSI, no need to add since it's default one */
3326                 vsi->uplink_seid = pf->mac_seid;
3327                 vsi->seid = pf->main_vsi_seid;
3328                 /* Bind queues with specific MSIX interrupt */
3329                 /**
3330                  * Needs 2 interrupt at least, one for misc cause which will
3331                  * enabled from OS side, Another for queues binding the
3332                  * interrupt from device side only.
3333                  */
3334
3335                 /* Get default VSI parameters from hardware */
3336                 memset(&ctxt, 0, sizeof(ctxt));
3337                 ctxt.seid = vsi->seid;
3338                 ctxt.pf_num = hw->pf_id;
3339                 ctxt.uplink_seid = vsi->uplink_seid;
3340                 ctxt.vf_num = 0;
3341                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3342                 if (ret != I40E_SUCCESS) {
3343                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3344                         goto fail_msix_alloc;
3345                 }
3346                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3347                         sizeof(struct i40e_aqc_vsi_properties_data));
3348                 vsi->vsi_id = ctxt.vsi_number;
3349                 vsi->info.valid_sections = 0;
3350
3351                 /* Configure tc, enabled TC0 only */
3352                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3353                         I40E_SUCCESS) {
3354                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3355                         goto fail_msix_alloc;
3356                 }
3357
3358                 /* TC, queue mapping */
3359                 memset(&ctxt, 0, sizeof(ctxt));
3360                 vsi->info.valid_sections |=
3361                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3362                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3363                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3364                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3365                         sizeof(struct i40e_aqc_vsi_properties_data));
3366                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3367                                                 I40E_DEFAULT_TCMAP);
3368                 if (ret != I40E_SUCCESS) {
3369                         PMD_DRV_LOG(ERR, "Failed to configure "
3370                                     "TC queue mapping");
3371                         goto fail_msix_alloc;
3372                 }
3373                 ctxt.seid = vsi->seid;
3374                 ctxt.pf_num = hw->pf_id;
3375                 ctxt.uplink_seid = vsi->uplink_seid;
3376                 ctxt.vf_num = 0;
3377
3378                 /* Update VSI parameters */
3379                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3380                 if (ret != I40E_SUCCESS) {
3381                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3382                         goto fail_msix_alloc;
3383                 }
3384
3385                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3386                                                 sizeof(vsi->info.tc_mapping));
3387                 (void)rte_memcpy(&vsi->info.queue_mapping,
3388                                 &ctxt.info.queue_mapping,
3389                         sizeof(vsi->info.queue_mapping));
3390                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3391                 vsi->info.valid_sections = 0;
3392
3393                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3394                                 ETH_ADDR_LEN);
3395
3396                 /**
3397                  * Updating default filter settings are necessary to prevent
3398                  * reception of tagged packets.
3399                  * Some old firmware configurations load a default macvlan
3400                  * filter which accepts both tagged and untagged packets.
3401                  * The updating is to use a normal filter instead if needed.
3402                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3403                  * The firmware with correct configurations load the default
3404                  * macvlan filter which is expected and cannot be removed.
3405                  */
3406                 i40e_update_default_filter_setting(vsi);
3407                 i40e_config_qinq(hw, vsi);
3408         } else if (type == I40E_VSI_SRIOV) {
3409                 memset(&ctxt, 0, sizeof(ctxt));
3410                 /**
3411                  * For other VSI, the uplink_seid equals to uplink VSI's
3412                  * uplink_seid since they share same VEB
3413                  */
3414                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3415                 ctxt.pf_num = hw->pf_id;
3416                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3417                 ctxt.uplink_seid = vsi->uplink_seid;
3418                 ctxt.connection_type = 0x1;
3419                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3420
3421                 /**
3422                  * Do not configure switch ID to enable VEB switch by
3423                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3424                  * if the source mac address of packet sent from VF is not
3425                  * listed in the VEB's mac table, the VEB will switch the
3426                  * packet back to the VF. Need to enable it when HW issue
3427                  * is fixed.
3428                  */
3429
3430                 /* Configure port/vlan */
3431                 ctxt.info.valid_sections |=
3432                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3433                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3434                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3435                                                 I40E_DEFAULT_TCMAP);
3436                 if (ret != I40E_SUCCESS) {
3437                         PMD_DRV_LOG(ERR, "Failed to configure "
3438                                     "TC queue mapping");
3439                         goto fail_msix_alloc;
3440                 }
3441                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3442                 ctxt.info.valid_sections |=
3443                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3444                 /**
3445                  * Since VSI is not created yet, only configure parameter,
3446                  * will add vsi below.
3447                  */
3448
3449                 i40e_config_qinq(hw, vsi);
3450         } else if (type == I40E_VSI_VMDQ2) {
3451                 memset(&ctxt, 0, sizeof(ctxt));
3452                 /*
3453                  * For other VSI, the uplink_seid equals to uplink VSI's
3454                  * uplink_seid since they share same VEB
3455                  */
3456                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3457                 ctxt.pf_num = hw->pf_id;
3458                 ctxt.vf_num = 0;
3459                 ctxt.uplink_seid = vsi->uplink_seid;
3460                 ctxt.connection_type = 0x1;
3461                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3462
3463                 ctxt.info.valid_sections |=
3464                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3465                 /* user_param carries flag to enable loop back */
3466                 if (user_param) {
3467                         ctxt.info.switch_id =
3468                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3469                         ctxt.info.switch_id |=
3470                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3471                 }
3472
3473                 /* Configure port/vlan */
3474                 ctxt.info.valid_sections |=
3475                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3476                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3477                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3478                                                 I40E_DEFAULT_TCMAP);
3479                 if (ret != I40E_SUCCESS) {
3480                         PMD_DRV_LOG(ERR, "Failed to configure "
3481                                         "TC queue mapping");
3482                         goto fail_msix_alloc;
3483                 }
3484                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3485                 ctxt.info.valid_sections |=
3486                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3487         } else if (type == I40E_VSI_FDIR) {
3488                 memset(&ctxt, 0, sizeof(ctxt));
3489                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3490                 ctxt.pf_num = hw->pf_id;
3491                 ctxt.vf_num = 0;
3492                 ctxt.uplink_seid = vsi->uplink_seid;
3493                 ctxt.connection_type = 0x1;     /* regular data port */
3494                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3495                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3496                                                 I40E_DEFAULT_TCMAP);
3497                 if (ret != I40E_SUCCESS) {
3498                         PMD_DRV_LOG(ERR, "Failed to configure "
3499                                         "TC queue mapping.");
3500                         goto fail_msix_alloc;
3501                 }
3502                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3503                 ctxt.info.valid_sections |=
3504                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3505         } else {
3506                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3507                 goto fail_msix_alloc;
3508         }
3509
3510         if (vsi->type != I40E_VSI_MAIN) {
3511                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3512                 if (ret != I40E_SUCCESS) {
3513                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3514                                     hw->aq.asq_last_status);
3515                         goto fail_msix_alloc;
3516                 }
3517                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3518                 vsi->info.valid_sections = 0;
3519                 vsi->seid = ctxt.seid;
3520                 vsi->vsi_id = ctxt.vsi_number;
3521                 vsi->sib_vsi_list.vsi = vsi;
3522                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3523                                 &vsi->sib_vsi_list, list);
3524         }
3525
3526         /* MAC/VLAN configuration */
3527         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3528         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3529
3530         ret = i40e_vsi_add_mac(vsi, &filter);
3531         if (ret != I40E_SUCCESS) {
3532                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3533                 goto fail_msix_alloc;
3534         }
3535
3536         /* Get VSI BW information */
3537         i40e_vsi_dump_bw_config(vsi);
3538         return vsi;
3539 fail_msix_alloc:
3540         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3541 fail_queue_alloc:
3542         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3543 fail_mem:
3544         rte_free(vsi);
3545         return NULL;
3546 }
3547
3548 /* Configure vlan stripping on or off */
3549 int
3550 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3551 {
3552         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3553         struct i40e_vsi_context ctxt;
3554         uint8_t vlan_flags;
3555         int ret = I40E_SUCCESS;
3556
3557         /* Check if it has been already on or off */
3558         if (vsi->info.valid_sections &
3559                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3560                 if (on) {
3561                         if ((vsi->info.port_vlan_flags &
3562                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3563                                 return 0; /* already on */
3564                 } else {
3565                         if ((vsi->info.port_vlan_flags &
3566                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3567                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3568                                 return 0; /* already off */
3569                 }
3570         }
3571
3572         if (on)
3573                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3574         else
3575                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3576         vsi->info.valid_sections =
3577                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3578         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3579         vsi->info.port_vlan_flags |= vlan_flags;
3580         ctxt.seid = vsi->seid;
3581         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3582         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3583         if (ret)
3584                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3585                             on ? "enable" : "disable");
3586
3587         return ret;
3588 }
3589
3590 static int
3591 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3592 {
3593         struct rte_eth_dev_data *data = dev->data;
3594         int ret;
3595
3596         /* Apply vlan offload setting */
3597         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3598
3599         /* Apply double-vlan setting, not implemented yet */
3600
3601         /* Apply pvid setting */
3602         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3603                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3604         if (ret)
3605                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3606
3607         return ret;
3608 }
3609
3610 static int
3611 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3612 {
3613         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3614
3615         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3616 }
3617
3618 static int
3619 i40e_update_flow_control(struct i40e_hw *hw)
3620 {
3621 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3622         struct i40e_link_status link_status;
3623         uint32_t rxfc = 0, txfc = 0, reg;
3624         uint8_t an_info;
3625         int ret;
3626
3627         memset(&link_status, 0, sizeof(link_status));
3628         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3629         if (ret != I40E_SUCCESS) {
3630                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3631                 goto write_reg; /* Disable flow control */
3632         }
3633
3634         an_info = hw->phy.link_info.an_info;
3635         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3636                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3637                 ret = I40E_ERR_NOT_READY;
3638                 goto write_reg; /* Disable flow control */
3639         }
3640         /**
3641          * If link auto negotiation is enabled, flow control needs to
3642          * be configured according to it
3643          */
3644         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3645         case I40E_LINK_PAUSE_RXTX:
3646                 rxfc = 1;
3647                 txfc = 1;
3648                 hw->fc.current_mode = I40E_FC_FULL;
3649                 break;
3650         case I40E_AQ_LINK_PAUSE_RX:
3651                 rxfc = 1;
3652                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3653                 break;
3654         case I40E_AQ_LINK_PAUSE_TX:
3655                 txfc = 1;
3656                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3657                 break;
3658         default:
3659                 hw->fc.current_mode = I40E_FC_NONE;
3660                 break;
3661         }
3662
3663 write_reg:
3664         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3665                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3666         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3667         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3668         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3669         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3670
3671         return ret;
3672 }
3673
3674 /* PF setup */
3675 static int
3676 i40e_pf_setup(struct i40e_pf *pf)
3677 {
3678         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3679         struct i40e_filter_control_settings settings;
3680         struct i40e_vsi *vsi;
3681         int ret;
3682
3683         /* Clear all stats counters */
3684         pf->offset_loaded = FALSE;
3685         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3686         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3687
3688         ret = i40e_pf_get_switch_config(pf);
3689         if (ret != I40E_SUCCESS) {
3690                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3691                 return ret;
3692         }
3693         if (pf->flags & I40E_FLAG_FDIR) {
3694                 /* make queue allocated first, let FDIR use queue pair 0*/
3695                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3696                 if (ret != I40E_FDIR_QUEUE_ID) {
3697                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3698                                     " ret =%d", ret);
3699                         pf->flags &= ~I40E_FLAG_FDIR;
3700                 }
3701         }
3702         /*  main VSI setup */
3703         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3704         if (!vsi) {
3705                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3706                 return I40E_ERR_NOT_READY;
3707         }
3708         pf->main_vsi = vsi;
3709
3710         /* Configure filter control */
3711         memset(&settings, 0, sizeof(settings));
3712         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3713                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3714         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3715                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3716         else {
3717                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3718                                                 hw->func_caps.rss_table_size);
3719                 return I40E_ERR_PARAM;
3720         }
3721         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3722                         "size: %u\n", hw->func_caps.rss_table_size);
3723         pf->hash_lut_size = hw->func_caps.rss_table_size;
3724
3725         /* Enable ethtype and macvlan filters */
3726         settings.enable_ethtype = TRUE;
3727         settings.enable_macvlan = TRUE;
3728         ret = i40e_set_filter_control(hw, &settings);
3729         if (ret)
3730                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3731                                                                 ret);
3732
3733         /* Update flow control according to the auto negotiation */
3734         i40e_update_flow_control(hw);
3735
3736         return I40E_SUCCESS;
3737 }
3738
3739 int
3740 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3741 {
3742         uint32_t reg;
3743         uint16_t j;
3744
3745         /**
3746          * Set or clear TX Queue Disable flags,
3747          * which is required by hardware.
3748          */
3749         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3750         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3751
3752         /* Wait until the request is finished */
3753         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3754                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3755                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3756                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3757                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3758                                                         & 0x1))) {
3759                         break;
3760                 }
3761         }
3762         if (on) {
3763                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3764                         return I40E_SUCCESS; /* already on, skip next steps */
3765
3766                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3767                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3768         } else {
3769                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3770                         return I40E_SUCCESS; /* already off, skip next steps */
3771                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3772         }
3773         /* Write the register */
3774         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3775         /* Check the result */
3776         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3777                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3778                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3779                 if (on) {
3780                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3781                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3782                                 break;
3783                 } else {
3784                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3785                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3786                                 break;
3787                 }
3788         }
3789         /* Check if it is timeout */
3790         if (j >= I40E_CHK_Q_ENA_COUNT) {
3791                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3792                             (on ? "enable" : "disable"), q_idx);
3793                 return I40E_ERR_TIMEOUT;
3794         }
3795
3796         return I40E_SUCCESS;
3797 }
3798
3799 /* Swith on or off the tx queues */
3800 static int
3801 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3802 {
3803         struct rte_eth_dev_data *dev_data = pf->dev_data;
3804         struct i40e_tx_queue *txq;
3805         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3806         uint16_t i;
3807         int ret;
3808
3809         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3810                 txq = dev_data->tx_queues[i];
3811                 /* Don't operate the queue if not configured or
3812                  * if starting only per queue */
3813                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3814                         continue;
3815                 if (on)
3816                         ret = i40e_dev_tx_queue_start(dev, i);
3817                 else
3818                         ret = i40e_dev_tx_queue_stop(dev, i);
3819                 if ( ret != I40E_SUCCESS)
3820                         return ret;
3821         }
3822
3823         return I40E_SUCCESS;
3824 }
3825
3826 int
3827 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3828 {
3829         uint32_t reg;
3830         uint16_t j;
3831
3832         /* Wait until the request is finished */
3833         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3834                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3835                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3836                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3837                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3838                         break;
3839         }
3840
3841         if (on) {
3842                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3843                         return I40E_SUCCESS; /* Already on, skip next steps */
3844                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3845         } else {
3846                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3847                         return I40E_SUCCESS; /* Already off, skip next steps */
3848                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3849         }
3850
3851         /* Write the register */
3852         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3853         /* Check the result */
3854         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3855                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3856                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3857                 if (on) {
3858                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3859                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3860                                 break;
3861                 } else {
3862                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3863                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3864                                 break;
3865                 }
3866         }
3867
3868         /* Check if it is timeout */
3869         if (j >= I40E_CHK_Q_ENA_COUNT) {
3870                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3871                             (on ? "enable" : "disable"), q_idx);
3872                 return I40E_ERR_TIMEOUT;
3873         }
3874
3875         return I40E_SUCCESS;
3876 }
3877 /* Switch on or off the rx queues */
3878 static int
3879 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3880 {
3881         struct rte_eth_dev_data *dev_data = pf->dev_data;
3882         struct i40e_rx_queue *rxq;
3883         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3884         uint16_t i;
3885         int ret;
3886
3887         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3888                 rxq = dev_data->rx_queues[i];
3889                 /* Don't operate the queue if not configured or
3890                  * if starting only per queue */
3891                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3892                         continue;
3893                 if (on)
3894                         ret = i40e_dev_rx_queue_start(dev, i);
3895                 else
3896                         ret = i40e_dev_rx_queue_stop(dev, i);
3897                 if (ret != I40E_SUCCESS)
3898                         return ret;
3899         }
3900
3901         return I40E_SUCCESS;
3902 }
3903
3904 /* Switch on or off all the rx/tx queues */
3905 int
3906 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3907 {
3908         int ret;
3909
3910         if (on) {
3911                 /* enable rx queues before enabling tx queues */
3912                 ret = i40e_dev_switch_rx_queues(pf, on);
3913                 if (ret) {
3914                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3915                         return ret;
3916                 }
3917                 ret = i40e_dev_switch_tx_queues(pf, on);
3918         } else {
3919                 /* Stop tx queues before stopping rx queues */
3920                 ret = i40e_dev_switch_tx_queues(pf, on);
3921                 if (ret) {
3922                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3923                         return ret;
3924                 }
3925                 ret = i40e_dev_switch_rx_queues(pf, on);
3926         }
3927
3928         return ret;
3929 }
3930
3931 /* Initialize VSI for TX */
3932 static int
3933 i40e_dev_tx_init(struct i40e_pf *pf)
3934 {
3935         struct rte_eth_dev_data *data = pf->dev_data;
3936         uint16_t i;
3937         uint32_t ret = I40E_SUCCESS;
3938         struct i40e_tx_queue *txq;
3939
3940         for (i = 0; i < data->nb_tx_queues; i++) {
3941                 txq = data->tx_queues[i];
3942                 if (!txq || !txq->q_set)
3943                         continue;
3944                 ret = i40e_tx_queue_init(txq);
3945                 if (ret != I40E_SUCCESS)
3946                         break;
3947         }
3948         if (ret == I40E_SUCCESS)
3949                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
3950                                      ->eth_dev);
3951
3952         return ret;
3953 }
3954
3955 /* Initialize VSI for RX */
3956 static int
3957 i40e_dev_rx_init(struct i40e_pf *pf)
3958 {
3959         struct rte_eth_dev_data *data = pf->dev_data;
3960         int ret = I40E_SUCCESS;
3961         uint16_t i;
3962         struct i40e_rx_queue *rxq;
3963
3964         i40e_pf_config_mq_rx(pf);
3965         for (i = 0; i < data->nb_rx_queues; i++) {
3966                 rxq = data->rx_queues[i];
3967                 if (!rxq || !rxq->q_set)
3968                         continue;
3969
3970                 ret = i40e_rx_queue_init(rxq);
3971                 if (ret != I40E_SUCCESS) {
3972                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3973                                     "initialization");
3974                         break;
3975                 }
3976         }
3977         if (ret == I40E_SUCCESS)
3978                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
3979                                      ->eth_dev);
3980
3981         return ret;
3982 }
3983
3984 static int
3985 i40e_dev_rxtx_init(struct i40e_pf *pf)
3986 {
3987         int err;
3988
3989         err = i40e_dev_tx_init(pf);
3990         if (err) {
3991                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3992                 return err;
3993         }
3994         err = i40e_dev_rx_init(pf);
3995         if (err) {
3996                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3997                 return err;
3998         }
3999
4000         return err;
4001 }
4002
4003 static int
4004 i40e_vmdq_setup(struct rte_eth_dev *dev)
4005 {
4006         struct rte_eth_conf *conf = &dev->data->dev_conf;
4007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4008         int i, err, conf_vsis, j, loop;
4009         struct i40e_vsi *vsi;
4010         struct i40e_vmdq_info *vmdq_info;
4011         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4012         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4013
4014         /*
4015          * Disable interrupt to avoid message from VF. Furthermore, it will
4016          * avoid race condition in VSI creation/destroy.
4017          */
4018         i40e_pf_disable_irq0(hw);
4019
4020         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4021                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4022                 return -ENOTSUP;
4023         }
4024
4025         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4026         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4027                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4028                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4029                         pf->max_nb_vmdq_vsi);
4030                 return -ENOTSUP;
4031         }
4032
4033         if (pf->vmdq != NULL) {
4034                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4035                 return 0;
4036         }
4037
4038         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4039                                 sizeof(*vmdq_info) * conf_vsis, 0);
4040
4041         if (pf->vmdq == NULL) {
4042                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4043                 return -ENOMEM;
4044         }
4045
4046         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4047
4048         /* Create VMDQ VSI */
4049         for (i = 0; i < conf_vsis; i++) {
4050                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4051                                 vmdq_conf->enable_loop_back);
4052                 if (vsi == NULL) {
4053                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4054                         err = -1;
4055                         goto err_vsi_setup;
4056                 }
4057                 vmdq_info = &pf->vmdq[i];
4058                 vmdq_info->pf = pf;
4059                 vmdq_info->vsi = vsi;
4060         }
4061         pf->nb_cfg_vmdq_vsi = conf_vsis;
4062
4063         /* Configure Vlan */
4064         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4065         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4066                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4067                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4068                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4069                                         vmdq_conf->pool_map[i].vlan_id, j);
4070
4071                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4072                                                 vmdq_conf->pool_map[i].vlan_id);
4073                                 if (err) {
4074                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4075                                         err = -1;
4076                                         goto err_vsi_setup;
4077                                 }
4078                         }
4079                 }
4080         }
4081
4082         i40e_pf_enable_irq0(hw);
4083
4084         return 0;
4085
4086 err_vsi_setup:
4087         for (i = 0; i < conf_vsis; i++)
4088                 if (pf->vmdq[i].vsi == NULL)
4089                         break;
4090                 else
4091                         i40e_vsi_release(pf->vmdq[i].vsi);
4092
4093         rte_free(pf->vmdq);
4094         pf->vmdq = NULL;
4095         i40e_pf_enable_irq0(hw);
4096         return err;
4097 }
4098
4099 static void
4100 i40e_stat_update_32(struct i40e_hw *hw,
4101                    uint32_t reg,
4102                    bool offset_loaded,
4103                    uint64_t *offset,
4104                    uint64_t *stat)
4105 {
4106         uint64_t new_data;
4107
4108         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4109         if (!offset_loaded)
4110                 *offset = new_data;
4111
4112         if (new_data >= *offset)
4113                 *stat = (uint64_t)(new_data - *offset);
4114         else
4115                 *stat = (uint64_t)((new_data +
4116                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4117 }
4118
4119 static void
4120 i40e_stat_update_48(struct i40e_hw *hw,
4121                    uint32_t hireg,
4122                    uint32_t loreg,
4123                    bool offset_loaded,
4124                    uint64_t *offset,
4125                    uint64_t *stat)
4126 {
4127         uint64_t new_data;
4128
4129         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4130         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4131                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4132
4133         if (!offset_loaded)
4134                 *offset = new_data;
4135
4136         if (new_data >= *offset)
4137                 *stat = new_data - *offset;
4138         else
4139                 *stat = (uint64_t)((new_data +
4140                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4141
4142         *stat &= I40E_48_BIT_MASK;
4143 }
4144
4145 /* Disable IRQ0 */
4146 void
4147 i40e_pf_disable_irq0(struct i40e_hw *hw)
4148 {
4149         /* Disable all interrupt types */
4150         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4151         I40E_WRITE_FLUSH(hw);
4152 }
4153
4154 /* Enable IRQ0 */
4155 void
4156 i40e_pf_enable_irq0(struct i40e_hw *hw)
4157 {
4158         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4159                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4160                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4161                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4162         I40E_WRITE_FLUSH(hw);
4163 }
4164
4165 static void
4166 i40e_pf_config_irq0(struct i40e_hw *hw)
4167 {
4168         /* read pending request and disable first */
4169         i40e_pf_disable_irq0(hw);
4170         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4171         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4172                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4173
4174         /* Link no queues with irq0 */
4175         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4176                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4177 }
4178
4179 static void
4180 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4181 {
4182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4183         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4184         int i;
4185         uint16_t abs_vf_id;
4186         uint32_t index, offset, val;
4187
4188         if (!pf->vfs)
4189                 return;
4190         /**
4191          * Try to find which VF trigger a reset, use absolute VF id to access
4192          * since the reg is global register.
4193          */
4194         for (i = 0; i < pf->vf_num; i++) {
4195                 abs_vf_id = hw->func_caps.vf_base_id + i;
4196                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4197                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4198                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4199                 /* VFR event occured */
4200                 if (val & (0x1 << offset)) {
4201                         int ret;
4202
4203                         /* Clear the event first */
4204                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4205                                                         (0x1 << offset));
4206                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4207                         /**
4208                          * Only notify a VF reset event occured,
4209                          * don't trigger another SW reset
4210                          */
4211                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4212                         if (ret != I40E_SUCCESS)
4213                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4214                 }
4215         }
4216 }
4217
4218 static void
4219 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4220 {
4221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4222         struct i40e_arq_event_info info;
4223         uint16_t pending, opcode;
4224         int ret;
4225
4226         info.buf_len = I40E_AQ_BUF_SZ;
4227         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4228         if (!info.msg_buf) {
4229                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4230                 return;
4231         }
4232
4233         pending = 1;
4234         while (pending) {
4235                 ret = i40e_clean_arq_element(hw, &info, &pending);
4236
4237                 if (ret != I40E_SUCCESS) {
4238                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4239                                     "aq_err: %u", hw->aq.asq_last_status);
4240                         break;
4241                 }
4242                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4243
4244                 switch (opcode) {
4245                 case i40e_aqc_opc_send_msg_to_pf:
4246                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4247                         i40e_pf_host_handle_vf_msg(dev,
4248                                         rte_le_to_cpu_16(info.desc.retval),
4249                                         rte_le_to_cpu_32(info.desc.cookie_high),
4250                                         rte_le_to_cpu_32(info.desc.cookie_low),
4251                                         info.msg_buf,
4252                                         info.msg_len);
4253                         break;
4254                 default:
4255                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4256                                     opcode);
4257                         break;
4258                 }
4259         }
4260         rte_free(info.msg_buf);
4261 }
4262
4263 /*
4264  * Interrupt handler is registered as the alarm callback for handling LSC
4265  * interrupt in a definite of time, in order to wait the NIC into a stable
4266  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4267  * no need for link down interrupt.
4268  */
4269 static void
4270 i40e_dev_interrupt_delayed_handler(void *param)
4271 {
4272         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4274         uint32_t icr0;
4275
4276         /* read interrupt causes again */
4277         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4278
4279 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4280         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4281                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4282         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4283                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4284         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4285                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4286         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4287                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4288         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4289                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4290                                                                 "state\n");
4291         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4292                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4293         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4294                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4295 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4296
4297         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4298                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4299                 i40e_dev_handle_vfr_event(dev);
4300         }
4301         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4302                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4303                 i40e_dev_handle_aq_msg(dev);
4304         }
4305
4306         /* handle the link up interrupt in an alarm callback */
4307         i40e_dev_link_update(dev, 0);
4308         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4309
4310         i40e_pf_enable_irq0(hw);
4311         rte_intr_enable(&(dev->pci_dev->intr_handle));
4312 }
4313
4314 /**
4315  * Interrupt handler triggered by NIC  for handling
4316  * specific interrupt.
4317  *
4318  * @param handle
4319  *  Pointer to interrupt handle.
4320  * @param param
4321  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4322  *
4323  * @return
4324  *  void
4325  */
4326 static void
4327 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4328                            void *param)
4329 {
4330         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4332         uint32_t icr0;
4333
4334         /* Disable interrupt */
4335         i40e_pf_disable_irq0(hw);
4336
4337         /* read out interrupt causes */
4338         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4339
4340         /* No interrupt event indicated */
4341         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4342                 PMD_DRV_LOG(INFO, "No interrupt event");
4343                 goto done;
4344         }
4345 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4346         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4347                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4348         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4349                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4350         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4351                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4352         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4353                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4354         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4355                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4356         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4357                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4358         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4359                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4360 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4361
4362         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4363                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4364                 i40e_dev_handle_vfr_event(dev);
4365         }
4366         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4367                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4368                 i40e_dev_handle_aq_msg(dev);
4369         }
4370
4371         /* Link Status Change interrupt */
4372         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4373 #define I40E_US_PER_SECOND 1000000
4374                 struct rte_eth_link link;
4375
4376                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4377                 memset(&link, 0, sizeof(link));
4378                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4379                 i40e_dev_link_update(dev, 0);
4380
4381                 /*
4382                  * For link up interrupt, it needs to wait 1 second to let the
4383                  * hardware be a stable state. Otherwise several consecutive
4384                  * interrupts can be observed.
4385                  * For link down interrupt, no need to wait.
4386                  */
4387                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4388                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4389                         return;
4390                 else
4391                         _rte_eth_dev_callback_process(dev,
4392                                 RTE_ETH_EVENT_INTR_LSC);
4393         }
4394
4395 done:
4396         /* Enable interrupt */
4397         i40e_pf_enable_irq0(hw);
4398         rte_intr_enable(&(dev->pci_dev->intr_handle));
4399 }
4400
4401 static int
4402 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4403                          struct i40e_macvlan_filter *filter,
4404                          int total)
4405 {
4406         int ele_num, ele_buff_size;
4407         int num, actual_num, i;
4408         uint16_t flags;
4409         int ret = I40E_SUCCESS;
4410         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4411         struct i40e_aqc_add_macvlan_element_data *req_list;
4412
4413         if (filter == NULL  || total == 0)
4414                 return I40E_ERR_PARAM;
4415         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4416         ele_buff_size = hw->aq.asq_buf_size;
4417
4418         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4419         if (req_list == NULL) {
4420                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4421                 return I40E_ERR_NO_MEMORY;
4422         }
4423
4424         num = 0;
4425         do {
4426                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4427                 memset(req_list, 0, ele_buff_size);
4428
4429                 for (i = 0; i < actual_num; i++) {
4430                         (void)rte_memcpy(req_list[i].mac_addr,
4431                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4432                         req_list[i].vlan_tag =
4433                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4434
4435                         switch (filter[num + i].filter_type) {
4436                         case RTE_MAC_PERFECT_MATCH:
4437                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4438                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4439                                 break;
4440                         case RTE_MACVLAN_PERFECT_MATCH:
4441                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4442                                 break;
4443                         case RTE_MAC_HASH_MATCH:
4444                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4445                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4446                                 break;
4447                         case RTE_MACVLAN_HASH_MATCH:
4448                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4449                                 break;
4450                         default:
4451                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4452                                 ret = I40E_ERR_PARAM;
4453                                 goto DONE;
4454                         }
4455
4456                         req_list[i].queue_number = 0;
4457
4458                         req_list[i].flags = rte_cpu_to_le_16(flags);
4459                 }
4460
4461                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4462                                                 actual_num, NULL);
4463                 if (ret != I40E_SUCCESS) {
4464                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4465                         goto DONE;
4466                 }
4467                 num += actual_num;
4468         } while (num < total);
4469
4470 DONE:
4471         rte_free(req_list);
4472         return ret;
4473 }
4474
4475 static int
4476 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4477                             struct i40e_macvlan_filter *filter,
4478                             int total)
4479 {
4480         int ele_num, ele_buff_size;
4481         int num, actual_num, i;
4482         uint16_t flags;
4483         int ret = I40E_SUCCESS;
4484         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4485         struct i40e_aqc_remove_macvlan_element_data *req_list;
4486
4487         if (filter == NULL  || total == 0)
4488                 return I40E_ERR_PARAM;
4489
4490         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4491         ele_buff_size = hw->aq.asq_buf_size;
4492
4493         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4494         if (req_list == NULL) {
4495                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4496                 return I40E_ERR_NO_MEMORY;
4497         }
4498
4499         num = 0;
4500         do {
4501                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4502                 memset(req_list, 0, ele_buff_size);
4503
4504                 for (i = 0; i < actual_num; i++) {
4505                         (void)rte_memcpy(req_list[i].mac_addr,
4506                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4507                         req_list[i].vlan_tag =
4508                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4509
4510                         switch (filter[num + i].filter_type) {
4511                         case RTE_MAC_PERFECT_MATCH:
4512                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4513                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4514                                 break;
4515                         case RTE_MACVLAN_PERFECT_MATCH:
4516                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4517                                 break;
4518                         case RTE_MAC_HASH_MATCH:
4519                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4520                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4521                                 break;
4522                         case RTE_MACVLAN_HASH_MATCH:
4523                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4524                                 break;
4525                         default:
4526                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4527                                 ret = I40E_ERR_PARAM;
4528                                 goto DONE;
4529                         }
4530                         req_list[i].flags = rte_cpu_to_le_16(flags);
4531                 }
4532
4533                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4534                                                 actual_num, NULL);
4535                 if (ret != I40E_SUCCESS) {
4536                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4537                         goto DONE;
4538                 }
4539                 num += actual_num;
4540         } while (num < total);
4541
4542 DONE:
4543         rte_free(req_list);
4544         return ret;
4545 }
4546
4547 /* Find out specific MAC filter */
4548 static struct i40e_mac_filter *
4549 i40e_find_mac_filter(struct i40e_vsi *vsi,
4550                          struct ether_addr *macaddr)
4551 {
4552         struct i40e_mac_filter *f;
4553
4554         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4555                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4556                         return f;
4557         }
4558
4559         return NULL;
4560 }
4561
4562 static bool
4563 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4564                          uint16_t vlan_id)
4565 {
4566         uint32_t vid_idx, vid_bit;
4567
4568         if (vlan_id > ETH_VLAN_ID_MAX)
4569                 return 0;
4570
4571         vid_idx = I40E_VFTA_IDX(vlan_id);
4572         vid_bit = I40E_VFTA_BIT(vlan_id);
4573
4574         if (vsi->vfta[vid_idx] & vid_bit)
4575                 return 1;
4576         else
4577                 return 0;
4578 }
4579
4580 static void
4581 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4582                          uint16_t vlan_id, bool on)
4583 {
4584         uint32_t vid_idx, vid_bit;
4585
4586         if (vlan_id > ETH_VLAN_ID_MAX)
4587                 return;
4588
4589         vid_idx = I40E_VFTA_IDX(vlan_id);
4590         vid_bit = I40E_VFTA_BIT(vlan_id);
4591
4592         if (on)
4593                 vsi->vfta[vid_idx] |= vid_bit;
4594         else
4595                 vsi->vfta[vid_idx] &= ~vid_bit;
4596 }
4597
4598 /**
4599  * Find all vlan options for specific mac addr,
4600  * return with actual vlan found.
4601  */
4602 static inline int
4603 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4604                            struct i40e_macvlan_filter *mv_f,
4605                            int num, struct ether_addr *addr)
4606 {
4607         int i;
4608         uint32_t j, k;
4609
4610         /**
4611          * Not to use i40e_find_vlan_filter to decrease the loop time,
4612          * although the code looks complex.
4613           */
4614         if (num < vsi->vlan_num)
4615                 return I40E_ERR_PARAM;
4616
4617         i = 0;
4618         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4619                 if (vsi->vfta[j]) {
4620                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4621                                 if (vsi->vfta[j] & (1 << k)) {
4622                                         if (i > num - 1) {
4623                                                 PMD_DRV_LOG(ERR, "vlan number "
4624                                                             "not match");
4625                                                 return I40E_ERR_PARAM;
4626                                         }
4627                                         (void)rte_memcpy(&mv_f[i].macaddr,
4628                                                         addr, ETH_ADDR_LEN);
4629                                         mv_f[i].vlan_id =
4630                                                 j * I40E_UINT32_BIT_SIZE + k;
4631                                         i++;
4632                                 }
4633                         }
4634                 }
4635         }
4636         return I40E_SUCCESS;
4637 }
4638
4639 static inline int
4640 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4641                            struct i40e_macvlan_filter *mv_f,
4642                            int num,
4643                            uint16_t vlan)
4644 {
4645         int i = 0;
4646         struct i40e_mac_filter *f;
4647
4648         if (num < vsi->mac_num)
4649                 return I40E_ERR_PARAM;
4650
4651         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4652                 if (i > num - 1) {
4653                         PMD_DRV_LOG(ERR, "buffer number not match");
4654                         return I40E_ERR_PARAM;
4655                 }
4656                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4657                                 ETH_ADDR_LEN);
4658                 mv_f[i].vlan_id = vlan;
4659                 mv_f[i].filter_type = f->mac_info.filter_type;
4660                 i++;
4661         }
4662
4663         return I40E_SUCCESS;
4664 }
4665
4666 static int
4667 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4668 {
4669         int i, num;
4670         struct i40e_mac_filter *f;
4671         struct i40e_macvlan_filter *mv_f;
4672         int ret = I40E_SUCCESS;
4673
4674         if (vsi == NULL || vsi->mac_num == 0)
4675                 return I40E_ERR_PARAM;
4676
4677         /* Case that no vlan is set */
4678         if (vsi->vlan_num == 0)
4679                 num = vsi->mac_num;
4680         else
4681                 num = vsi->mac_num * vsi->vlan_num;
4682
4683         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4684         if (mv_f == NULL) {
4685                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4686                 return I40E_ERR_NO_MEMORY;
4687         }
4688
4689         i = 0;
4690         if (vsi->vlan_num == 0) {
4691                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4692                         (void)rte_memcpy(&mv_f[i].macaddr,
4693                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4694                         mv_f[i].vlan_id = 0;
4695                         i++;
4696                 }
4697         } else {
4698                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4699                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4700                                         vsi->vlan_num, &f->mac_info.mac_addr);
4701                         if (ret != I40E_SUCCESS)
4702                                 goto DONE;
4703                         i += vsi->vlan_num;
4704                 }
4705         }
4706
4707         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4708 DONE:
4709         rte_free(mv_f);
4710
4711         return ret;
4712 }
4713
4714 int
4715 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4716 {
4717         struct i40e_macvlan_filter *mv_f;
4718         int mac_num;
4719         int ret = I40E_SUCCESS;
4720
4721         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4722                 return I40E_ERR_PARAM;
4723
4724         /* If it's already set, just return */
4725         if (i40e_find_vlan_filter(vsi,vlan))
4726                 return I40E_SUCCESS;
4727
4728         mac_num = vsi->mac_num;
4729
4730         if (mac_num == 0) {
4731                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4732                 return I40E_ERR_PARAM;
4733         }
4734
4735         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4736
4737         if (mv_f == NULL) {
4738                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4739                 return I40E_ERR_NO_MEMORY;
4740         }
4741
4742         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4743
4744         if (ret != I40E_SUCCESS)
4745                 goto DONE;
4746
4747         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4748
4749         if (ret != I40E_SUCCESS)
4750                 goto DONE;
4751
4752         i40e_set_vlan_filter(vsi, vlan, 1);
4753
4754         vsi->vlan_num++;
4755         ret = I40E_SUCCESS;
4756 DONE:
4757         rte_free(mv_f);
4758         return ret;
4759 }
4760
4761 int
4762 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4763 {
4764         struct i40e_macvlan_filter *mv_f;
4765         int mac_num;
4766         int ret = I40E_SUCCESS;
4767
4768         /**
4769          * Vlan 0 is the generic filter for untagged packets
4770          * and can't be removed.
4771          */
4772         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4773                 return I40E_ERR_PARAM;
4774
4775         /* If can't find it, just return */
4776         if (!i40e_find_vlan_filter(vsi, vlan))
4777                 return I40E_ERR_PARAM;
4778
4779         mac_num = vsi->mac_num;
4780
4781         if (mac_num == 0) {
4782                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4783                 return I40E_ERR_PARAM;
4784         }
4785
4786         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4787
4788         if (mv_f == NULL) {
4789                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4790                 return I40E_ERR_NO_MEMORY;
4791         }
4792
4793         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4794
4795         if (ret != I40E_SUCCESS)
4796                 goto DONE;
4797
4798         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4799
4800         if (ret != I40E_SUCCESS)
4801                 goto DONE;
4802
4803         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4804         if (vsi->vlan_num == 1) {
4805                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4806                 if (ret != I40E_SUCCESS)
4807                         goto DONE;
4808
4809                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4810                 if (ret != I40E_SUCCESS)
4811                         goto DONE;
4812         }
4813
4814         i40e_set_vlan_filter(vsi, vlan, 0);
4815
4816         vsi->vlan_num--;
4817         ret = I40E_SUCCESS;
4818 DONE:
4819         rte_free(mv_f);
4820         return ret;
4821 }
4822
4823 int
4824 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4825 {
4826         struct i40e_mac_filter *f;
4827         struct i40e_macvlan_filter *mv_f;
4828         int i, vlan_num = 0;
4829         int ret = I40E_SUCCESS;
4830
4831         /* If it's add and we've config it, return */
4832         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4833         if (f != NULL)
4834                 return I40E_SUCCESS;
4835         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4836                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4837
4838                 /**
4839                  * If vlan_num is 0, that's the first time to add mac,
4840                  * set mask for vlan_id 0.
4841                  */
4842                 if (vsi->vlan_num == 0) {
4843                         i40e_set_vlan_filter(vsi, 0, 1);
4844                         vsi->vlan_num = 1;
4845                 }
4846                 vlan_num = vsi->vlan_num;
4847         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4848                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4849                 vlan_num = 1;
4850
4851         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4852         if (mv_f == NULL) {
4853                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4854                 return I40E_ERR_NO_MEMORY;
4855         }
4856
4857         for (i = 0; i < vlan_num; i++) {
4858                 mv_f[i].filter_type = mac_filter->filter_type;
4859                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4860                                 ETH_ADDR_LEN);
4861         }
4862
4863         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4864                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4865                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4866                                         &mac_filter->mac_addr);
4867                 if (ret != I40E_SUCCESS)
4868                         goto DONE;
4869         }
4870
4871         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4872         if (ret != I40E_SUCCESS)
4873                 goto DONE;
4874
4875         /* Add the mac addr into mac list */
4876         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4877         if (f == NULL) {
4878                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4879                 ret = I40E_ERR_NO_MEMORY;
4880                 goto DONE;
4881         }
4882         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4883                         ETH_ADDR_LEN);
4884         f->mac_info.filter_type = mac_filter->filter_type;
4885         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4886         vsi->mac_num++;
4887
4888         ret = I40E_SUCCESS;
4889 DONE:
4890         rte_free(mv_f);
4891
4892         return ret;
4893 }
4894
4895 int
4896 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4897 {
4898         struct i40e_mac_filter *f;
4899         struct i40e_macvlan_filter *mv_f;
4900         int i, vlan_num;
4901         enum rte_mac_filter_type filter_type;
4902         int ret = I40E_SUCCESS;
4903
4904         /* Can't find it, return an error */
4905         f = i40e_find_mac_filter(vsi, addr);
4906         if (f == NULL)
4907                 return I40E_ERR_PARAM;
4908
4909         vlan_num = vsi->vlan_num;
4910         filter_type = f->mac_info.filter_type;
4911         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4912                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4913                 if (vlan_num == 0) {
4914                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4915                         return I40E_ERR_PARAM;
4916                 }
4917         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4918                         filter_type == RTE_MAC_HASH_MATCH)
4919                 vlan_num = 1;
4920
4921         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4922         if (mv_f == NULL) {
4923                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4924                 return I40E_ERR_NO_MEMORY;
4925         }
4926
4927         for (i = 0; i < vlan_num; i++) {
4928                 mv_f[i].filter_type = filter_type;
4929                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4930                                 ETH_ADDR_LEN);
4931         }
4932         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4933                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4934                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4935                 if (ret != I40E_SUCCESS)
4936                         goto DONE;
4937         }
4938
4939         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4940         if (ret != I40E_SUCCESS)
4941                 goto DONE;
4942
4943         /* Remove the mac addr into mac list */
4944         TAILQ_REMOVE(&vsi->mac_list, f, next);
4945         rte_free(f);
4946         vsi->mac_num--;
4947
4948         ret = I40E_SUCCESS;
4949 DONE:
4950         rte_free(mv_f);
4951         return ret;
4952 }
4953
4954 /* Configure hash enable flags for RSS */
4955 uint64_t
4956 i40e_config_hena(uint64_t flags)
4957 {
4958         uint64_t hena = 0;
4959
4960         if (!flags)
4961                 return hena;
4962
4963         if (flags & ETH_RSS_FRAG_IPV4)
4964                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4965         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4966                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4967         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4968                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4969         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4970                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4971         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4972                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4973         if (flags & ETH_RSS_FRAG_IPV6)
4974                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4975         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4976                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4977         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4978                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4979         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4980                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4981         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4982                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4983         if (flags & ETH_RSS_L2_PAYLOAD)
4984                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4985
4986         return hena;
4987 }
4988
4989 /* Parse the hash enable flags */
4990 uint64_t
4991 i40e_parse_hena(uint64_t flags)
4992 {
4993         uint64_t rss_hf = 0;
4994
4995         if (!flags)
4996                 return rss_hf;
4997         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4998                 rss_hf |= ETH_RSS_FRAG_IPV4;
4999         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5000                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5001         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5002                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5003         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5004                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5005         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5006                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5007         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5008                 rss_hf |= ETH_RSS_FRAG_IPV6;
5009         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5010                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5011         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5012                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5013         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5014                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5015         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5016                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5017         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5018                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5019
5020         return rss_hf;
5021 }
5022
5023 /* Disable RSS */
5024 static void
5025 i40e_pf_disable_rss(struct i40e_pf *pf)
5026 {
5027         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5028         uint64_t hena;
5029
5030         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5031         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5032         hena &= ~I40E_RSS_HENA_ALL;
5033         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5034         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5035         I40E_WRITE_FLUSH(hw);
5036 }
5037
5038 static int
5039 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
5040 {
5041         uint32_t *hash_key;
5042         uint8_t hash_key_len;
5043         uint64_t rss_hf;
5044         uint16_t i;
5045         uint64_t hena;
5046
5047         hash_key = (uint32_t *)(rss_conf->rss_key);
5048         hash_key_len = rss_conf->rss_key_len;
5049         if (hash_key != NULL && hash_key_len >=
5050                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5051                 /* Fill in RSS hash key */
5052                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5053                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5054         }
5055
5056         rss_hf = rss_conf->rss_hf;
5057         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5058         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5059         hena &= ~I40E_RSS_HENA_ALL;
5060         hena |= i40e_config_hena(rss_hf);
5061         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5062         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5063         I40E_WRITE_FLUSH(hw);
5064
5065         return 0;
5066 }
5067
5068 static int
5069 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5070                          struct rte_eth_rss_conf *rss_conf)
5071 {
5072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5074         uint64_t hena;
5075
5076         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5077         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5078         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5079                 if (rss_hf != 0) /* Enable RSS */
5080                         return -EINVAL;
5081                 return 0; /* Nothing to do */
5082         }
5083         /* RSS enabled */
5084         if (rss_hf == 0) /* Disable RSS */
5085                 return -EINVAL;
5086
5087         return i40e_hw_rss_hash_set(hw, rss_conf);
5088 }
5089
5090 static int
5091 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5092                            struct rte_eth_rss_conf *rss_conf)
5093 {
5094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5095         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
5096         uint64_t hena;
5097         uint16_t i;
5098
5099         if (hash_key != NULL) {
5100                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5101                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5102                 rss_conf->rss_key_len = i * sizeof(uint32_t);
5103         }
5104         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5105         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5106         rss_conf->rss_hf = i40e_parse_hena(hena);
5107
5108         return 0;
5109 }
5110
5111 static int
5112 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5113 {
5114         switch (filter_type) {
5115         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5116                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5117                 break;
5118         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5119                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5120                 break;
5121         case RTE_TUNNEL_FILTER_IMAC_TENID:
5122                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5123                 break;
5124         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5125                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5126                 break;
5127         case ETH_TUNNEL_FILTER_IMAC:
5128                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5129                 break;
5130         default:
5131                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5132                 return -EINVAL;
5133         }
5134
5135         return 0;
5136 }
5137
5138 static int
5139 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5140                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5141                         uint8_t add)
5142 {
5143         uint16_t ip_type;
5144         uint8_t tun_type = 0;
5145         int val, ret = 0;
5146         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5147         struct i40e_vsi *vsi = pf->main_vsi;
5148         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5149         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5150
5151         cld_filter = rte_zmalloc("tunnel_filter",
5152                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5153                 0);
5154
5155         if (NULL == cld_filter) {
5156                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5157                 return -EINVAL;
5158         }
5159         pfilter = cld_filter;
5160
5161         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5162                         sizeof(struct ether_addr));
5163         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5164                         sizeof(struct ether_addr));
5165
5166         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5167         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5168                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5169                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5170                                 &tunnel_filter->ip_addr,
5171                                 sizeof(pfilter->ipaddr.v4.data));
5172         } else {
5173                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5174                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5175                                 &tunnel_filter->ip_addr,
5176                                 sizeof(pfilter->ipaddr.v6.data));
5177         }
5178
5179         /* check tunneled type */
5180         switch (tunnel_filter->tunnel_type) {
5181         case RTE_TUNNEL_TYPE_VXLAN:
5182                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5183                 break;
5184         case RTE_TUNNEL_TYPE_NVGRE:
5185                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5186                 break;
5187         default:
5188                 /* Other tunnel types is not supported. */
5189                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5190                 rte_free(cld_filter);
5191                 return -EINVAL;
5192         }
5193
5194         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5195                                                 &pfilter->flags);
5196         if (val < 0) {
5197                 rte_free(cld_filter);
5198                 return -EINVAL;
5199         }
5200
5201         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5202                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5203         pfilter->tenant_id = tunnel_filter->tenant_id;
5204         pfilter->queue_number = tunnel_filter->queue_id;
5205
5206         if (add)
5207                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5208         else
5209                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5210                                                 cld_filter, 1);
5211
5212         rte_free(cld_filter);
5213         return ret;
5214 }
5215
5216 static int
5217 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5218 {
5219         uint8_t i;
5220
5221         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5222                 if (pf->vxlan_ports[i] == port)
5223                         return i;
5224         }
5225
5226         return -1;
5227 }
5228
5229 static int
5230 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5231 {
5232         int  idx, ret;
5233         uint8_t filter_idx;
5234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5235
5236         idx = i40e_get_vxlan_port_idx(pf, port);
5237
5238         /* Check if port already exists */
5239         if (idx >= 0) {
5240                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5241                 return -EINVAL;
5242         }
5243
5244         /* Now check if there is space to add the new port */
5245         idx = i40e_get_vxlan_port_idx(pf, 0);
5246         if (idx < 0) {
5247                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5248                         "not adding port %d", port);
5249                 return -ENOSPC;
5250         }
5251
5252         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5253                                         &filter_idx, NULL);
5254         if (ret < 0) {
5255                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5256                 return -1;
5257         }
5258
5259         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5260                          port,  filter_idx);
5261
5262         /* New port: add it and mark its index in the bitmap */
5263         pf->vxlan_ports[idx] = port;
5264         pf->vxlan_bitmap |= (1 << idx);
5265
5266         if (!(pf->flags & I40E_FLAG_VXLAN))
5267                 pf->flags |= I40E_FLAG_VXLAN;
5268
5269         return 0;
5270 }
5271
5272 static int
5273 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5274 {
5275         int idx;
5276         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5277
5278         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5279                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5280                 return -EINVAL;
5281         }
5282
5283         idx = i40e_get_vxlan_port_idx(pf, port);
5284
5285         if (idx < 0) {
5286                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5287                 return -EINVAL;
5288         }
5289
5290         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5291                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5292                 return -1;
5293         }
5294
5295         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5296                         port, idx);
5297
5298         pf->vxlan_ports[idx] = 0;
5299         pf->vxlan_bitmap &= ~(1 << idx);
5300
5301         if (!pf->vxlan_bitmap)
5302                 pf->flags &= ~I40E_FLAG_VXLAN;
5303
5304         return 0;
5305 }
5306
5307 /* Add UDP tunneling port */
5308 static int
5309 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5310                         struct rte_eth_udp_tunnel *udp_tunnel)
5311 {
5312         int ret = 0;
5313         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5314
5315         if (udp_tunnel == NULL)
5316                 return -EINVAL;
5317
5318         switch (udp_tunnel->prot_type) {
5319         case RTE_TUNNEL_TYPE_VXLAN:
5320                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5321                 break;
5322
5323         case RTE_TUNNEL_TYPE_GENEVE:
5324         case RTE_TUNNEL_TYPE_TEREDO:
5325                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5326                 ret = -1;
5327                 break;
5328
5329         default:
5330                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5331                 ret = -1;
5332                 break;
5333         }
5334
5335         return ret;
5336 }
5337
5338 /* Remove UDP tunneling port */
5339 static int
5340 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5341                         struct rte_eth_udp_tunnel *udp_tunnel)
5342 {
5343         int ret = 0;
5344         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5345
5346         if (udp_tunnel == NULL)
5347                 return -EINVAL;
5348
5349         switch (udp_tunnel->prot_type) {
5350         case RTE_TUNNEL_TYPE_VXLAN:
5351                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5352                 break;
5353         case RTE_TUNNEL_TYPE_GENEVE:
5354         case RTE_TUNNEL_TYPE_TEREDO:
5355                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5356                 ret = -1;
5357                 break;
5358         default:
5359                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5360                 ret = -1;
5361                 break;
5362         }
5363
5364         return ret;
5365 }
5366
5367 /* Calculate the maximum number of contiguous PF queues that are configured */
5368 static int
5369 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5370 {
5371         struct rte_eth_dev_data *data = pf->dev_data;
5372         int i, num;
5373         struct i40e_rx_queue *rxq;
5374
5375         num = 0;
5376         for (i = 0; i < pf->lan_nb_qps; i++) {
5377                 rxq = data->rx_queues[i];
5378                 if (rxq && rxq->q_set)
5379                         num++;
5380                 else
5381                         break;
5382         }
5383
5384         return num;
5385 }
5386
5387 /* Configure RSS */
5388 static int
5389 i40e_pf_config_rss(struct i40e_pf *pf)
5390 {
5391         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5392         struct rte_eth_rss_conf rss_conf;
5393         uint32_t i, lut = 0;
5394         uint16_t j, num;
5395
5396         /*
5397          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5398          * It's necessary to calulate the actual PF queues that are configured.
5399          */
5400         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5401                 num = i40e_pf_calc_configured_queues_num(pf);
5402                 num = i40e_align_floor(num);
5403         } else
5404                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5405
5406         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5407                         num);
5408
5409         if (num == 0) {
5410                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5411                 return -ENOTSUP;
5412         }
5413
5414         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5415                 if (j == num)
5416                         j = 0;
5417                 lut = (lut << 8) | (j & ((0x1 <<
5418                         hw->func_caps.rss_table_entry_width) - 1));
5419                 if ((i & 3) == 3)
5420                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5421         }
5422
5423         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5424         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5425                 i40e_pf_disable_rss(pf);
5426                 return 0;
5427         }
5428         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5429                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5430                 /* Random default keys */
5431                 static uint32_t rss_key_default[] = {0x6b793944,
5432                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5433                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5434                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5435
5436                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5437                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5438                                                         sizeof(uint32_t);
5439         }
5440
5441         return i40e_hw_rss_hash_set(hw, &rss_conf);
5442 }
5443
5444 static int
5445 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5446                         struct rte_eth_tunnel_filter_conf *filter)
5447 {
5448         if (pf == NULL || filter == NULL) {
5449                 PMD_DRV_LOG(ERR, "Invalid parameter");
5450                 return -EINVAL;
5451         }
5452
5453         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5454                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5455                 return -EINVAL;
5456         }
5457
5458         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5459                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5460                 return -EINVAL;
5461         }
5462
5463         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5464                 (is_zero_ether_addr(filter->outer_mac))) {
5465                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5466                 return -EINVAL;
5467         }
5468
5469         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5470                 (is_zero_ether_addr(filter->inner_mac))) {
5471                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5472                 return -EINVAL;
5473         }
5474
5475         return 0;
5476 }
5477
5478 static int
5479 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5480                         void *arg)
5481 {
5482         struct rte_eth_tunnel_filter_conf *filter;
5483         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5484         int ret = I40E_SUCCESS;
5485
5486         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5487
5488         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5489                 return I40E_ERR_PARAM;
5490
5491         switch (filter_op) {
5492         case RTE_ETH_FILTER_NOP:
5493                 if (!(pf->flags & I40E_FLAG_VXLAN))
5494                         ret = I40E_NOT_SUPPORTED;
5495         case RTE_ETH_FILTER_ADD:
5496                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5497                 break;
5498         case RTE_ETH_FILTER_DELETE:
5499                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5500                 break;
5501         default:
5502                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5503                 ret = I40E_ERR_PARAM;
5504                 break;
5505         }
5506
5507         return ret;
5508 }
5509
5510 static int
5511 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5512 {
5513         int ret = 0;
5514         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5515
5516         /* RSS setup */
5517         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5518                 ret = i40e_pf_config_rss(pf);
5519         else
5520                 i40e_pf_disable_rss(pf);
5521
5522         return ret;
5523 }
5524
5525 /* Get the symmetric hash enable configurations per port */
5526 static void
5527 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5528 {
5529         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5530
5531         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5532 }
5533
5534 /* Set the symmetric hash enable configurations per port */
5535 static void
5536 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5537 {
5538         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5539
5540         if (enable > 0) {
5541                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5542                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5543                                                         "been enabled");
5544                         return;
5545                 }
5546                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5547         } else {
5548                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5549                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5550                                                         "been disabled");
5551                         return;
5552                 }
5553                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5554         }
5555         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5556         I40E_WRITE_FLUSH(hw);
5557 }
5558
5559 /*
5560  * Get global configurations of hash function type and symmetric hash enable
5561  * per flow type (pctype). Note that global configuration means it affects all
5562  * the ports on the same NIC.
5563  */
5564 static int
5565 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5566                                    struct rte_eth_hash_global_conf *g_cfg)
5567 {
5568         uint32_t reg, mask = I40E_FLOW_TYPES;
5569         uint16_t i;
5570         enum i40e_filter_pctype pctype;
5571
5572         memset(g_cfg, 0, sizeof(*g_cfg));
5573         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5574         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5575                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5576         else
5577                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5578         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5579                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5580
5581         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5582                 if (!(mask & (1UL << i)))
5583                         continue;
5584                 mask &= ~(1UL << i);
5585                 /* Bit set indicats the coresponding flow type is supported */
5586                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5587                 pctype = i40e_flowtype_to_pctype(i);
5588                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5589                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5590                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5591         }
5592
5593         return 0;
5594 }
5595
5596 static int
5597 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5598 {
5599         uint32_t i;
5600         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5601
5602         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5603                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5604                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5605                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5606                                                 g_cfg->hash_func);
5607                 return -EINVAL;
5608         }
5609
5610         /*
5611          * As i40e supports less than 32 flow types, only first 32 bits need to
5612          * be checked.
5613          */
5614         mask0 = g_cfg->valid_bit_mask[0];
5615         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5616                 if (i == 0) {
5617                         /* Check if any unsupported flow type configured */
5618                         if ((mask0 | i40e_mask) ^ i40e_mask)
5619                                 goto mask_err;
5620                 } else {
5621                         if (g_cfg->valid_bit_mask[i])
5622                                 goto mask_err;
5623                 }
5624         }
5625
5626         return 0;
5627
5628 mask_err:
5629         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5630
5631         return -EINVAL;
5632 }
5633
5634 /*
5635  * Set global configurations of hash function type and symmetric hash enable
5636  * per flow type (pctype). Note any modifying global configuration will affect
5637  * all the ports on the same NIC.
5638  */
5639 static int
5640 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5641                                    struct rte_eth_hash_global_conf *g_cfg)
5642 {
5643         int ret;
5644         uint16_t i;
5645         uint32_t reg;
5646         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5647         enum i40e_filter_pctype pctype;
5648
5649         /* Check the input parameters */
5650         ret = i40e_hash_global_config_check(g_cfg);
5651         if (ret < 0)
5652                 return ret;
5653
5654         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5655                 if (!(mask0 & (1UL << i)))
5656                         continue;
5657                 mask0 &= ~(1UL << i);
5658                 pctype = i40e_flowtype_to_pctype(i);
5659                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5660                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5661                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5662         }
5663
5664         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5665         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5666                 /* Toeplitz */
5667                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5668                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5669                                                                 "Toeplitz");
5670                         goto out;
5671                 }
5672                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5673         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5674                 /* Simple XOR */
5675                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5676                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5677                                                         "Simple XOR");
5678                         goto out;
5679                 }
5680                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5681         } else
5682                 /* Use the default, and keep it as it is */
5683                 goto out;
5684
5685         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5686
5687 out:
5688         I40E_WRITE_FLUSH(hw);
5689
5690         return 0;
5691 }
5692
5693 static int
5694 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5695 {
5696         int ret = 0;
5697
5698         if (!hw || !info) {
5699                 PMD_DRV_LOG(ERR, "Invalid pointer");
5700                 return -EFAULT;
5701         }
5702
5703         switch (info->info_type) {
5704         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5705                 i40e_get_symmetric_hash_enable_per_port(hw,
5706                                         &(info->info.enable));
5707                 break;
5708         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5709                 ret = i40e_get_hash_filter_global_config(hw,
5710                                 &(info->info.global_conf));
5711                 break;
5712         default:
5713                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5714                                                         info->info_type);
5715                 ret = -EINVAL;
5716                 break;
5717         }
5718
5719         return ret;
5720 }
5721
5722 static int
5723 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5724 {
5725         int ret = 0;
5726
5727         if (!hw || !info) {
5728                 PMD_DRV_LOG(ERR, "Invalid pointer");
5729                 return -EFAULT;
5730         }
5731
5732         switch (info->info_type) {
5733         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5734                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5735                 break;
5736         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5737                 ret = i40e_set_hash_filter_global_config(hw,
5738                                 &(info->info.global_conf));
5739                 break;
5740         default:
5741                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5742                                                         info->info_type);
5743                 ret = -EINVAL;
5744                 break;
5745         }
5746
5747         return ret;
5748 }
5749
5750 /* Operations for hash function */
5751 static int
5752 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5753                       enum rte_filter_op filter_op,
5754                       void *arg)
5755 {
5756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5757         int ret = 0;
5758
5759         switch (filter_op) {
5760         case RTE_ETH_FILTER_NOP:
5761                 break;
5762         case RTE_ETH_FILTER_GET:
5763                 ret = i40e_hash_filter_get(hw,
5764                         (struct rte_eth_hash_filter_info *)arg);
5765                 break;
5766         case RTE_ETH_FILTER_SET:
5767                 ret = i40e_hash_filter_set(hw,
5768                         (struct rte_eth_hash_filter_info *)arg);
5769                 break;
5770         default:
5771                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5772                                                                 filter_op);
5773                 ret = -ENOTSUP;
5774                 break;
5775         }
5776
5777         return ret;
5778 }
5779
5780 /*
5781  * Configure ethertype filter, which can director packet by filtering
5782  * with mac address and ether_type or only ether_type
5783  */
5784 static int
5785 i40e_ethertype_filter_set(struct i40e_pf *pf,
5786                         struct rte_eth_ethertype_filter *filter,
5787                         bool add)
5788 {
5789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5790         struct i40e_control_filter_stats stats;
5791         uint16_t flags = 0;
5792         int ret;
5793
5794         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5795                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5796                 return -EINVAL;
5797         }
5798         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5799                 filter->ether_type == ETHER_TYPE_IPv6) {
5800                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5801                         " control packet filter.", filter->ether_type);
5802                 return -EINVAL;
5803         }
5804         if (filter->ether_type == ETHER_TYPE_VLAN)
5805                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5806                         " not supported.");
5807
5808         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5809                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5810         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5811                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5812         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5813
5814         memset(&stats, 0, sizeof(stats));
5815         ret = i40e_aq_add_rem_control_packet_filter(hw,
5816                         filter->mac_addr.addr_bytes,
5817                         filter->ether_type, flags,
5818                         pf->main_vsi->seid,
5819                         filter->queue, add, &stats, NULL);
5820
5821         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5822                          " mac_etype_used = %u, etype_used = %u,"
5823                          " mac_etype_free = %u, etype_free = %u\n",
5824                          ret, stats.mac_etype_used, stats.etype_used,
5825                          stats.mac_etype_free, stats.etype_free);
5826         if (ret < 0)
5827                 return -ENOSYS;
5828         return 0;
5829 }
5830
5831 /*
5832  * Handle operations for ethertype filter.
5833  */
5834 static int
5835 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5836                                 enum rte_filter_op filter_op,
5837                                 void *arg)
5838 {
5839         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5840         int ret = 0;
5841
5842         if (filter_op == RTE_ETH_FILTER_NOP)
5843                 return ret;
5844
5845         if (arg == NULL) {
5846                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5847                             filter_op);
5848                 return -EINVAL;
5849         }
5850
5851         switch (filter_op) {
5852         case RTE_ETH_FILTER_ADD:
5853                 ret = i40e_ethertype_filter_set(pf,
5854                         (struct rte_eth_ethertype_filter *)arg,
5855                         TRUE);
5856                 break;
5857         case RTE_ETH_FILTER_DELETE:
5858                 ret = i40e_ethertype_filter_set(pf,
5859                         (struct rte_eth_ethertype_filter *)arg,
5860                         FALSE);
5861                 break;
5862         default:
5863                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5864                 ret = -ENOSYS;
5865                 break;
5866         }
5867         return ret;
5868 }
5869
5870 static int
5871 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5872                      enum rte_filter_type filter_type,
5873                      enum rte_filter_op filter_op,
5874                      void *arg)
5875 {
5876         int ret = 0;
5877
5878         if (dev == NULL)
5879                 return -EINVAL;
5880
5881         switch (filter_type) {
5882         case RTE_ETH_FILTER_HASH:
5883                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5884                 break;
5885         case RTE_ETH_FILTER_MACVLAN:
5886                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5887                 break;
5888         case RTE_ETH_FILTER_ETHERTYPE:
5889                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5890                 break;
5891         case RTE_ETH_FILTER_TUNNEL:
5892                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5893                 break;
5894         case RTE_ETH_FILTER_FDIR:
5895                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5896                 break;
5897         default:
5898                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5899                                                         filter_type);
5900                 ret = -EINVAL;
5901                 break;
5902         }
5903
5904         return ret;
5905 }
5906
5907 /*
5908  * As some registers wouldn't be reset unless a global hardware reset,
5909  * hardware initialization is needed to put those registers into an
5910  * expected initial state.
5911  */
5912 static void
5913 i40e_hw_init(struct i40e_hw *hw)
5914 {
5915         /* clear the PF Queue Filter control register */
5916         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5917
5918         /* Disable symmetric hash per port */
5919         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5920 }
5921
5922 enum i40e_filter_pctype
5923 i40e_flowtype_to_pctype(uint16_t flow_type)
5924 {
5925         static const enum i40e_filter_pctype pctype_table[] = {
5926                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5927                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5928                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5929                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5930                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5931                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5932                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5933                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5934                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5935                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5936                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5937                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5938                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5939                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5940                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5941                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5942                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5943                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5944                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5945         };
5946
5947         return pctype_table[flow_type];
5948 }
5949
5950 uint16_t
5951 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5952 {
5953         static const uint16_t flowtype_table[] = {
5954                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5955                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5956                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5957                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5958                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5959                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5960                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5961                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5962                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5963                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5964                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5965                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5966                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5967                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5968                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5969                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5970                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5971                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5972                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5973         };
5974
5975         return flowtype_table[pctype];
5976 }
5977
5978 /*
5979  * On X710, performance number is far from the expectation on recent firmware
5980  * versions; on XL710, performance number is also far from the expectation on
5981  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5982  * mode is enabled and port MAC address is equal to the packet destination MAC
5983  * address. The fix for this issue may not be integrated in the following
5984  * firmware version. So the workaround in software driver is needed. It needs
5985  * to modify the initial values of 3 internal only registers for both X710 and
5986  * XL710. Note that the values for X710 or XL710 could be different, and the
5987  * workaround can be removed when it is fixed in firmware in the future.
5988  */
5989
5990 /* For both X710 and XL710 */
5991 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5992 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5993
5994 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5995 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5996
5997 /* For X710 */
5998 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5999 /* For XL710 */
6000 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
6001 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
6002
6003 static void
6004 i40e_configure_registers(struct i40e_hw *hw)
6005 {
6006         static struct {
6007                 uint32_t addr;
6008                 uint64_t val;
6009         } reg_table[] = {
6010                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6011                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6012                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6013         };
6014         uint64_t reg;
6015         uint32_t i;
6016         int ret;
6017
6018         for (i = 0; i < RTE_DIM(reg_table); i++) {
6019                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6020                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6021                                 reg_table[i].val =
6022                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6023                         else /* For X710 */
6024                                 reg_table[i].val =
6025                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6026                 }
6027
6028                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6029                                                         &reg, NULL);
6030                 if (ret < 0) {
6031                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6032                                                         reg_table[i].addr);
6033                         break;
6034                 }
6035                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6036                                                 reg_table[i].addr, reg);
6037                 if (reg == reg_table[i].val)
6038                         continue;
6039
6040                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6041                                                 reg_table[i].val, NULL);
6042                 if (ret < 0) {
6043                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6044                                 "address of 0x%"PRIx32, reg_table[i].val,
6045                                                         reg_table[i].addr);
6046                         break;
6047                 }
6048                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6049                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6050         }
6051 }
6052
6053 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6054 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6055 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6056 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6057 static int
6058 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6059 {
6060         uint32_t reg;
6061         int ret;
6062
6063         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6064                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6065                 return -EINVAL;
6066         }
6067
6068         /* Configure for double VLAN RX stripping */
6069         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6070         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6071                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6072                 ret = i40e_aq_debug_write_register(hw,
6073                                                    I40E_VSI_TSR(vsi->vsi_id),
6074                                                    reg, NULL);
6075                 if (ret < 0) {
6076                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6077                                     vsi->vsi_id);
6078                         return I40E_ERR_CONFIG;
6079                 }
6080         }
6081
6082         /* Configure for double VLAN TX insertion */
6083         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6084         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6085                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6086                 ret = i40e_aq_debug_write_register(hw,
6087                                                    I40E_VSI_L2TAGSTXVALID(
6088                                                    vsi->vsi_id), reg, NULL);
6089                 if (ret < 0) {
6090                         PMD_DRV_LOG(ERR, "Failed to update "
6091                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6092                         return I40E_ERR_CONFIG;
6093                 }
6094         }
6095
6096         return 0;
6097 }
6098
6099 /**
6100  * i40e_aq_add_mirror_rule
6101  * @hw: pointer to the hardware structure
6102  * @seid: VEB seid to add mirror rule to
6103  * @dst_id: destination vsi seid
6104  * @entries: Buffer which contains the entities to be mirrored
6105  * @count: number of entities contained in the buffer
6106  * @rule_id:the rule_id of the rule to be added
6107  *
6108  * Add a mirror rule for a given veb.
6109  *
6110  **/
6111 static enum i40e_status_code
6112 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6113                         uint16_t seid, uint16_t dst_id,
6114                         uint16_t rule_type, uint16_t *entries,
6115                         uint16_t count, uint16_t *rule_id)
6116 {
6117         struct i40e_aq_desc desc;
6118         struct i40e_aqc_add_delete_mirror_rule cmd;
6119         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6120                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6121                 &desc.params.raw;
6122         uint16_t buff_len;
6123         enum i40e_status_code status;
6124
6125         i40e_fill_default_direct_cmd_desc(&desc,
6126                                           i40e_aqc_opc_add_mirror_rule);
6127         memset(&cmd, 0, sizeof(cmd));
6128
6129         buff_len = sizeof(uint16_t) * count;
6130         desc.datalen = rte_cpu_to_le_16(buff_len);
6131         if (buff_len > 0)
6132                 desc.flags |= rte_cpu_to_le_16(
6133                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6134         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6135                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6136         cmd.num_entries = rte_cpu_to_le_16(count);
6137         cmd.seid = rte_cpu_to_le_16(seid);
6138         cmd.destination = rte_cpu_to_le_16(dst_id);
6139
6140         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6141         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6142         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6143                          "rule_id = %u"
6144                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6145                          hw->aq.asq_last_status, resp->rule_id,
6146                          resp->mirror_rules_used, resp->mirror_rules_free);
6147         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6148
6149         return status;
6150 }
6151
6152 /**
6153  * i40e_aq_del_mirror_rule
6154  * @hw: pointer to the hardware structure
6155  * @seid: VEB seid to add mirror rule to
6156  * @entries: Buffer which contains the entities to be mirrored
6157  * @count: number of entities contained in the buffer
6158  * @rule_id:the rule_id of the rule to be delete
6159  *
6160  * Delete a mirror rule for a given veb.
6161  *
6162  **/
6163 static enum i40e_status_code
6164 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6165                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6166                 uint16_t count, uint16_t rule_id)
6167 {
6168         struct i40e_aq_desc desc;
6169         struct i40e_aqc_add_delete_mirror_rule cmd;
6170         uint16_t buff_len = 0;
6171         enum i40e_status_code status;
6172         void *buff = NULL;
6173
6174         i40e_fill_default_direct_cmd_desc(&desc,
6175                                           i40e_aqc_opc_delete_mirror_rule);
6176         memset(&cmd, 0, sizeof(cmd));
6177         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6178                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6179                                                           I40E_AQ_FLAG_RD));
6180                 cmd.num_entries = count;
6181                 buff_len = sizeof(uint16_t) * count;
6182                 desc.datalen = rte_cpu_to_le_16(buff_len);
6183                 buff = (void *)entries;
6184         } else
6185                 /* rule id is filled in destination field for deleting mirror rule */
6186                 cmd.destination = rte_cpu_to_le_16(rule_id);
6187
6188         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6189                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6190         cmd.seid = rte_cpu_to_le_16(seid);
6191
6192         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6193         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6194
6195         return status;
6196 }
6197
6198 /**
6199  * i40e_mirror_rule_set
6200  * @dev: pointer to the hardware structure
6201  * @mirror_conf: mirror rule info
6202  * @sw_id: mirror rule's sw_id
6203  * @on: enable/disable
6204  *
6205  * set a mirror rule.
6206  *
6207  **/
6208 static int
6209 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6210                         struct rte_eth_mirror_conf *mirror_conf,
6211                         uint8_t sw_id, uint8_t on)
6212 {
6213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6214         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6215         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6216         struct i40e_mirror_rule *parent = NULL;
6217         uint16_t seid, dst_seid, rule_id;
6218         uint16_t i, j = 0;
6219         int ret;
6220
6221         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6222
6223         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6224                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6225                         " without veb or vfs.");
6226                 return -ENOSYS;
6227         }
6228         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6229                 PMD_DRV_LOG(ERR, "mirror table is full.");
6230                 return -ENOSPC;
6231         }
6232         if (mirror_conf->dst_pool > pf->vf_num) {
6233                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6234                                  mirror_conf->dst_pool);
6235                 return -EINVAL;
6236         }
6237
6238         seid = pf->main_vsi->veb->seid;
6239
6240         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6241                 if (sw_id <= it->index) {
6242                         mirr_rule = it;
6243                         break;
6244                 }
6245                 parent = it;
6246         }
6247         if (mirr_rule && sw_id == mirr_rule->index) {
6248                 if (on) {
6249                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6250                         return -EEXIST;
6251                 } else {
6252                         ret = i40e_aq_del_mirror_rule(hw, seid,
6253                                         mirr_rule->rule_type,
6254                                         mirr_rule->entries,
6255                                         mirr_rule->num_entries, mirr_rule->id);
6256                         if (ret < 0) {
6257                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6258                                                    " ret = %d, aq_err = %d.",
6259                                                    ret, hw->aq.asq_last_status);
6260                                 return -ENOSYS;
6261                         }
6262                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6263                         rte_free(mirr_rule);
6264                         pf->nb_mirror_rule--;
6265                         return 0;
6266                 }
6267         } else if (!on) {
6268                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6269                 return -ENOENT;
6270         }
6271
6272         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6273                                 sizeof(struct i40e_mirror_rule) , 0);
6274         if (!mirr_rule) {
6275                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6276                 return I40E_ERR_NO_MEMORY;
6277         }
6278         switch (mirror_conf->rule_type) {
6279         case ETH_MIRROR_VLAN:
6280                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6281                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6282                                 mirr_rule->entries[j] =
6283                                         mirror_conf->vlan.vlan_id[i];
6284                                 j++;
6285                         }
6286                 }
6287                 if (j == 0) {
6288                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6289                         rte_free(mirr_rule);
6290                         return -EINVAL;
6291                 }
6292                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6293                 break;
6294         case ETH_MIRROR_VIRTUAL_POOL_UP:
6295         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6296                 /* check if the specified pool bit is out of range */
6297                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6298                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6299                         rte_free(mirr_rule);
6300                         return -EINVAL;
6301                 }
6302                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6303                         if (mirror_conf->pool_mask & (1ULL << i)) {
6304                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6305                                 j++;
6306                         }
6307                 }
6308                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6309                         /* add pf vsi to entries */
6310                         mirr_rule->entries[j] = pf->main_vsi_seid;
6311                         j++;
6312                 }
6313                 if (j == 0) {
6314                         PMD_DRV_LOG(ERR, "pool is not specified.");
6315                         rte_free(mirr_rule);
6316                         return -EINVAL;
6317                 }
6318                 /* egress and ingress in aq commands means from switch but not port */
6319                 mirr_rule->rule_type =
6320                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6321                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6322                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6323                 break;
6324         case ETH_MIRROR_UPLINK_PORT:
6325                 /* egress and ingress in aq commands means from switch but not port*/
6326                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6327                 break;
6328         case ETH_MIRROR_DOWNLINK_PORT:
6329                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6330                 break;
6331         default:
6332                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6333                         mirror_conf->rule_type);
6334                 rte_free(mirr_rule);
6335                 return -EINVAL;
6336         }
6337
6338         /* If the dst_pool is equal to vf_num, consider it as PF */
6339         if (mirror_conf->dst_pool == pf->vf_num)
6340                 dst_seid = pf->main_vsi_seid;
6341         else
6342                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6343
6344         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6345                                       mirr_rule->rule_type, mirr_rule->entries,
6346                                       j, &rule_id);
6347         if (ret < 0) {
6348                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6349                                    " ret = %d, aq_err = %d.",
6350                                    ret, hw->aq.asq_last_status);
6351                 rte_free(mirr_rule);
6352                 return -ENOSYS;
6353         }
6354
6355         mirr_rule->index = sw_id;
6356         mirr_rule->num_entries = j;
6357         mirr_rule->id = rule_id;
6358         mirr_rule->dst_vsi_seid = dst_seid;
6359
6360         if (parent)
6361                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6362         else
6363                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6364
6365         pf->nb_mirror_rule++;
6366         return 0;
6367 }
6368
6369 /**
6370  * i40e_mirror_rule_reset
6371  * @dev: pointer to the device
6372  * @sw_id: mirror rule's sw_id
6373  *
6374  * reset a mirror rule.
6375  *
6376  **/
6377 static int
6378 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6379 {
6380         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6381         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6382         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6383         uint16_t seid;
6384         int ret;
6385
6386         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6387
6388         seid = pf->main_vsi->veb->seid;
6389
6390         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6391                 if (sw_id == it->index) {
6392                         mirr_rule = it;
6393                         break;
6394                 }
6395         }
6396         if (mirr_rule) {
6397                 ret = i40e_aq_del_mirror_rule(hw, seid,
6398                                 mirr_rule->rule_type,
6399                                 mirr_rule->entries,
6400                                 mirr_rule->num_entries, mirr_rule->id);
6401                 if (ret < 0) {
6402                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6403                                            " status = %d, aq_err = %d.",
6404                                            ret, hw->aq.asq_last_status);
6405                         return -ENOSYS;
6406                 }
6407                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6408                 rte_free(mirr_rule);
6409                 pf->nb_mirror_rule--;
6410         } else {
6411                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6412                 return -ENOENT;
6413         }
6414         return 0;
6415 }
6416
6417 static int
6418 i40e_timesync_enable(struct rte_eth_dev *dev)
6419 {
6420         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6421         struct rte_eth_link *link = &dev->data->dev_link;
6422         uint32_t tsync_ctl_l;
6423         uint32_t tsync_ctl_h;
6424         uint32_t tsync_inc_l;
6425         uint32_t tsync_inc_h;
6426
6427         switch (link->link_speed) {
6428         case ETH_LINK_SPEED_40G:
6429                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6430                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6431                 break;
6432         case ETH_LINK_SPEED_10G:
6433                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6434                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6435                 break;
6436         case ETH_LINK_SPEED_1000:
6437                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6438                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6439                 break;
6440         default:
6441                 tsync_inc_l = 0x0;
6442                 tsync_inc_h = 0x0;
6443         }
6444
6445         /* Clear timesync registers. */
6446         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6447         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6448         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6449         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6450         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6451         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6452         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6453
6454         /* Set the timesync increment value. */
6455         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6456         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6457
6458         /* Enable timestamping of PTP packets. */
6459         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6460         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6461
6462         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6463         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6464         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6465
6466         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6467         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6468
6469         return 0;
6470 }
6471
6472 static int
6473 i40e_timesync_disable(struct rte_eth_dev *dev)
6474 {
6475         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6476         uint32_t tsync_ctl_l;
6477         uint32_t tsync_ctl_h;
6478
6479         /* Disable timestamping of transmitted PTP packets. */
6480         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6481         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6482
6483         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6484         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6485
6486         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6487         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6488
6489         /* Set the timesync increment value. */
6490         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6491         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6492
6493         return 0;
6494 }
6495
6496 static int
6497 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6498                                 struct timespec *timestamp, uint32_t flags)
6499 {
6500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6501         uint32_t sync_status;
6502         uint32_t rx_stmpl;
6503         uint32_t rx_stmph;
6504         uint32_t index = flags & 0x03;
6505
6506         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6507         if ((sync_status & (1 << index)) == 0)
6508                 return -EINVAL;
6509
6510         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6511         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6512
6513         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6514         timestamp->tv_nsec = 0;
6515
6516         return  0;
6517 }
6518
6519 static int
6520 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6521                                 struct timespec *timestamp)
6522 {
6523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6524         uint32_t sync_status;
6525         uint32_t tx_stmpl;
6526         uint32_t tx_stmph;
6527
6528         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6529         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6530                 return -EINVAL;
6531
6532         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6533         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6534
6535         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6536         timestamp->tv_nsec = 0;
6537
6538         return  0;
6539 }
6540
6541 /*
6542  * i40e_parse_dcb_configure - parse dcb configure from user
6543  * @dev: the device being configured
6544  * @dcb_cfg: pointer of the result of parse
6545  * @*tc_map: bit map of enabled traffic classes
6546  *
6547  * Returns 0 on success, negative value on failure
6548  */
6549 static int
6550 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6551                          struct i40e_dcbx_config *dcb_cfg,
6552                          uint8_t *tc_map)
6553 {
6554         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6555         uint8_t i, tc_bw, bw_lf;
6556
6557         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6558
6559         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6560         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6561                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6562                 return -EINVAL;
6563         }
6564
6565         /* assume each tc has the same bw */
6566         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6567         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6568                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6569         /* to ensure the sum of tcbw is equal to 100 */
6570         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6571         for (i = 0; i < bw_lf; i++)
6572                 dcb_cfg->etscfg.tcbwtable[i]++;
6573
6574         /* assume each tc has the same Transmission Selection Algorithm */
6575         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6576                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6577
6578         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6579                 dcb_cfg->etscfg.prioritytable[i] =
6580                                 dcb_rx_conf->dcb_tc[i];
6581
6582         /* FW needs one App to configure HW */
6583         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6584         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6585         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6586         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6587
6588         if (dcb_rx_conf->nb_tcs == 0)
6589                 *tc_map = 1; /* tc0 only */
6590         else
6591                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6592
6593         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6594                 dcb_cfg->pfc.willing = 0;
6595                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6596                 dcb_cfg->pfc.pfcenable = *tc_map;
6597         }
6598         return 0;
6599 }
6600
6601 /*
6602  * i40e_vsi_get_bw_info - Query VSI BW Information
6603  * @vsi: the VSI being queried
6604  *
6605  * Returns 0 on success, negative value on failure
6606  */
6607 static int
6608 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6609 {
6610         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6611         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6612         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6613         int i, ret;
6614         uint32_t tc_bw_max;
6615
6616         /* Get the VSI level BW configuration */
6617         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6618         if (ret) {
6619                 PMD_INIT_LOG(ERR,
6620                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
6621                          i40e_stat_str(hw, ret),
6622                          i40e_aq_str(hw, hw->aq.asq_last_status));
6623                 return -EINVAL;
6624         }
6625
6626         /* Get the VSI level BW configuration per TC */
6627         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6628                                                   NULL);
6629         if (ret) {
6630                 PMD_INIT_LOG(ERR,
6631                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6632                          i40e_stat_str(hw, ret),
6633                          i40e_aq_str(hw, hw->aq.asq_last_status));
6634                 return -EINVAL;
6635         }
6636
6637         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6638                 PMD_INIT_LOG(WARNING,
6639                          "Enabled TCs mismatch from querying VSI BW info"
6640                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6641                          bw_ets_config.tc_valid_bits);
6642                 /* Still continuing */
6643         }
6644
6645         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6646         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6647         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6648                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6649         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6650                 vsi->bw_info.bw_ets_share_credits[i] =
6651                                 bw_ets_config.share_credits[i];
6652                 vsi->bw_info.bw_ets_limit_credits[i] =
6653                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6654                 /* 3 bits out of 4 for each TC */
6655                 vsi->bw_info.bw_ets_max_quanta[i] =
6656                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6657                 PMD_INIT_LOG(DEBUG,
6658                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6659                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
6660         }
6661
6662         return 0;
6663 }
6664
6665 static int
6666 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6667                               struct i40e_aqc_vsi_properties_data *info,
6668                               uint8_t enabled_tcmap)
6669 {
6670         int ret, i, total_tc = 0;
6671         uint16_t qpnum_per_tc, bsf, qp_idx;
6672         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
6673
6674         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
6675         if (ret != I40E_SUCCESS)
6676                 return ret;
6677
6678         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6679                 if (enabled_tcmap & (1 << i))
6680                         total_tc++;
6681         }
6682         if (total_tc == 0)
6683                 total_tc = 1;
6684         vsi->enabled_tc = enabled_tcmap;
6685
6686         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
6687         /* Number of queues per enabled TC */
6688         if (qpnum_per_tc == 0) {
6689                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
6690                 return I40E_ERR_INVALID_QP_ID;
6691         }
6692         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
6693                                 I40E_MAX_Q_PER_TC);
6694         bsf = rte_bsf32(qpnum_per_tc);
6695
6696         /**
6697          * Configure TC and queue mapping parameters, for enabled TC,
6698          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
6699          * default queue will serve it.
6700          */
6701         qp_idx = 0;
6702         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6703                 if (vsi->enabled_tc & (1 << i)) {
6704                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
6705                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
6706                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
6707                         qp_idx += qpnum_per_tc;
6708                 } else
6709                         info->tc_mapping[i] = 0;
6710         }
6711
6712         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
6713         if (vsi->type == I40E_VSI_SRIOV) {
6714                 info->mapping_flags |=
6715                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
6716                 for (i = 0; i < vsi->nb_qps; i++)
6717                         info->queue_mapping[i] =
6718                                 rte_cpu_to_le_16(vsi->base_queue + i);
6719         } else {
6720                 info->mapping_flags |=
6721                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
6722                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
6723         }
6724         info->valid_sections |=
6725                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
6726
6727         return I40E_SUCCESS;
6728 }
6729
6730 /*
6731  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
6732  * @vsi: VSI to be configured
6733  * @tc_map: enabled TC bitmap
6734  *
6735  * Returns 0 on success, negative value on failure
6736  */
6737 static int
6738 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
6739 {
6740         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
6741         struct i40e_vsi_context ctxt;
6742         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6743         int ret = 0;
6744         int i;
6745
6746         /* Check if enabled_tc is same as existing or new TCs */
6747         if (vsi->enabled_tc == tc_map)
6748                 return ret;
6749
6750         /* configure tc bandwidth */
6751         memset(&bw_data, 0, sizeof(bw_data));
6752         bw_data.tc_valid_bits = tc_map;
6753         /* Enable ETS TCs with equal BW Share for now across all VSIs */
6754         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6755                 if (tc_map & BIT_ULL(i))
6756                         bw_data.tc_bw_credits[i] = 1;
6757         }
6758         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
6759         if (ret) {
6760                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
6761                         " per TC failed = %d",
6762                         hw->aq.asq_last_status);
6763                 goto out;
6764         }
6765         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
6766                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
6767
6768         /* Update Queue Pairs Mapping for currently enabled UPs */
6769         ctxt.seid = vsi->seid;
6770         ctxt.pf_num = hw->pf_id;
6771         ctxt.vf_num = 0;
6772         ctxt.uplink_seid = vsi->uplink_seid;
6773         ctxt.info = vsi->info;
6774         i40e_get_cap(hw);
6775         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
6776         if (ret)
6777                 goto out;
6778
6779         /* Update the VSI after updating the VSI queue-mapping information */
6780         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6781         if (ret) {
6782                 PMD_INIT_LOG(ERR, "Failed to configure "
6783                             "TC queue mapping = %d",
6784                             hw->aq.asq_last_status);
6785                 goto out;
6786         }
6787         /* update the local VSI info with updated queue map */
6788         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
6789                                         sizeof(vsi->info.tc_mapping));
6790         (void)rte_memcpy(&vsi->info.queue_mapping,
6791                         &ctxt.info.queue_mapping,
6792                 sizeof(vsi->info.queue_mapping));
6793         vsi->info.mapping_flags = ctxt.info.mapping_flags;
6794         vsi->info.valid_sections = 0;
6795
6796         /* Update current VSI BW information */
6797         ret = i40e_vsi_get_bw_info(vsi);
6798         if (ret) {
6799                 PMD_INIT_LOG(ERR,
6800                          "Failed updating vsi bw info, err %s aq_err %s",
6801                          i40e_stat_str(hw, ret),
6802                          i40e_aq_str(hw, hw->aq.asq_last_status));
6803                 goto out;
6804         }
6805
6806         vsi->enabled_tc = tc_map;
6807
6808 out:
6809         return ret;
6810 }
6811
6812 /*
6813  * i40e_dcb_hw_configure - program the dcb setting to hw
6814  * @pf: pf the configuration is taken on
6815  * @new_cfg: new configuration
6816  * @tc_map: enabled TC bitmap
6817  *
6818  * Returns 0 on success, negative value on failure
6819  */
6820 static enum i40e_status_code
6821 i40e_dcb_hw_configure(struct i40e_pf *pf,
6822                       struct i40e_dcbx_config *new_cfg,
6823                       uint8_t tc_map)
6824 {
6825         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6826         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
6827         struct i40e_vsi *main_vsi = pf->main_vsi;
6828         struct i40e_vsi_list *vsi_list;
6829         int i, ret;
6830         uint32_t val;
6831
6832         /* Use the FW API if FW > v4.4*/
6833         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
6834                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
6835                                   " to configure DCB");
6836                 return I40E_ERR_FIRMWARE_API_VERSION;
6837         }
6838
6839         /* Check if need reconfiguration */
6840         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
6841                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
6842                 return I40E_SUCCESS;
6843         }
6844
6845         /* Copy the new config to the current config */
6846         *old_cfg = *new_cfg;
6847         old_cfg->etsrec = old_cfg->etscfg;
6848         ret = i40e_set_dcb_config(hw);
6849         if (ret) {
6850                 PMD_INIT_LOG(ERR,
6851                          "Set DCB Config failed, err %s aq_err %s\n",
6852                          i40e_stat_str(hw, ret),
6853                          i40e_aq_str(hw, hw->aq.asq_last_status));
6854                 return ret;
6855         }
6856         /* set receive Arbiter to RR mode and ETS scheme by default */
6857         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
6858                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
6859                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
6860                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
6861                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
6862                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
6863                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
6864                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
6865                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
6866                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
6867                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
6868                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
6869                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
6870         }
6871         /* get local mib to check whether it is configured correctly */
6872         /* IEEE mode */
6873         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
6874         /* Get Local DCB Config */
6875         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
6876                                      &hw->local_dcbx_config);
6877
6878         /* Update each VSI */
6879         i40e_vsi_config_tc(main_vsi, tc_map);
6880         if (main_vsi->veb) {
6881                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
6882                         /* Beside main VSI, only enable default
6883                          * TC for other VSIs
6884                          */
6885                         ret = i40e_vsi_config_tc(vsi_list->vsi,
6886                                                 I40E_DEFAULT_TCMAP);
6887                         if (ret)
6888                                 PMD_INIT_LOG(WARNING,
6889                                          "Failed configuring TC for VSI seid=%d\n",
6890                                          vsi_list->vsi->seid);
6891                         /* continue */
6892                 }
6893         }
6894         return I40E_SUCCESS;
6895 }
6896
6897 /*
6898  * i40e_dcb_init_configure - initial dcb config
6899  * @dev: device being configured
6900  * @sw_dcb: indicate whether dcb is sw configured or hw offload
6901  *
6902  * Returns 0 on success, negative value on failure
6903  */
6904 static int
6905 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
6906 {
6907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6909         int ret = 0;
6910
6911         if ((pf->flags & I40E_FLAG_DCB) == 0) {
6912                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
6913                 return -ENOTSUP;
6914         }
6915
6916         /* DCB initialization:
6917          * Update DCB configuration from the Firmware and configure
6918          * LLDP MIB change event.
6919          */
6920         if (sw_dcb == TRUE) {
6921                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
6922                 if (ret != I40E_SUCCESS)
6923                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
6924
6925                 ret = i40e_init_dcb(hw);
6926                 /* if sw_dcb, lldp agent is stopped, the return from
6927                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
6928                  * adminq status.
6929                  */
6930                 if (ret != I40E_SUCCESS &&
6931                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
6932                         memset(&hw->local_dcbx_config, 0,
6933                                 sizeof(struct i40e_dcbx_config));
6934                         /* set dcb default configuration */
6935                         hw->local_dcbx_config.etscfg.willing = 0;
6936                         hw->local_dcbx_config.etscfg.maxtcs = 0;
6937                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
6938                         hw->local_dcbx_config.etscfg.tsatable[0] =
6939                                                 I40E_IEEE_TSA_ETS;
6940                         hw->local_dcbx_config.etsrec =
6941                                 hw->local_dcbx_config.etscfg;
6942                         hw->local_dcbx_config.pfc.willing = 0;
6943                         hw->local_dcbx_config.pfc.pfccap =
6944                                                 I40E_MAX_TRAFFIC_CLASS;
6945                         /* FW needs one App to configure HW */
6946                         hw->local_dcbx_config.numapps = 1;
6947                         hw->local_dcbx_config.app[0].selector =
6948                                                 I40E_APP_SEL_ETHTYPE;
6949                         hw->local_dcbx_config.app[0].priority = 3;
6950                         hw->local_dcbx_config.app[0].protocolid =
6951                                                 I40E_APP_PROTOID_FCOE;
6952                         ret = i40e_set_dcb_config(hw);
6953                         if (ret) {
6954                                 PMD_INIT_LOG(ERR, "default dcb config fails."
6955                                         " err = %d, aq_err = %d.", ret,
6956                                           hw->aq.asq_last_status);
6957                                 return -ENOSYS;
6958                         }
6959                 } else {
6960                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
6961                                           " aq_err = %d.", ret,
6962                                           hw->aq.asq_last_status);
6963                         return -ENOTSUP;
6964                 }
6965         } else {
6966                 ret = i40e_aq_start_lldp(hw, NULL);
6967                 if (ret != I40E_SUCCESS)
6968                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
6969
6970                 ret = i40e_init_dcb(hw);
6971                 if (!ret) {
6972                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
6973                                 PMD_INIT_LOG(ERR, "HW doesn't support"
6974                                                   " DCBX offload.");
6975                                 return -ENOTSUP;
6976                         }
6977                 } else {
6978                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
6979                                           " aq_err = %d.", ret,
6980                                           hw->aq.asq_last_status);
6981                         return -ENOTSUP;
6982                 }
6983         }
6984         return 0;
6985 }
6986
6987 /*
6988  * i40e_dcb_setup - setup dcb related config
6989  * @dev: device being configured
6990  *
6991  * Returns 0 on success, negative value on failure
6992  */
6993 static int
6994 i40e_dcb_setup(struct rte_eth_dev *dev)
6995 {
6996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6997         struct i40e_dcbx_config dcb_cfg;
6998         uint8_t tc_map = 0;
6999         int ret = 0;
7000
7001         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7002                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7003                 return -ENOTSUP;
7004         }
7005
7006         if (pf->vf_num != 0 ||
7007             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7008                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7009
7010         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7011         if (ret) {
7012                 PMD_INIT_LOG(ERR, "invalid dcb config");
7013                 return -EINVAL;
7014         }
7015         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7016         if (ret) {
7017                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7018                 return -ENOSYS;
7019         }
7020         return 0;
7021 }
7022
7023 static int
7024 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
7025                       struct rte_eth_dcb_info *dcb_info)
7026 {
7027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7029         struct i40e_vsi *vsi = pf->main_vsi;
7030         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
7031         uint16_t bsf, tc_mapping;
7032         int i;
7033
7034         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7035                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
7036         else
7037                 dcb_info->nb_tcs = 1;
7038         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7039                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
7040         for (i = 0; i < dcb_info->nb_tcs; i++)
7041                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
7042
7043         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7044                 if (vsi->enabled_tc & (1 << i)) {
7045                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
7046                         /* only main vsi support multi TCs */
7047                         dcb_info->tc_queue.tc_rxq[0][i].base =
7048                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
7049                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
7050                         dcb_info->tc_queue.tc_txq[0][i].base =
7051                                 dcb_info->tc_queue.tc_rxq[0][i].base;
7052                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
7053                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
7054                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
7055                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
7056                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
7057                 }
7058         }
7059         return 0;
7060 }