drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* Source IPv4 address for X722 */
 215 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 216 /* Destination IPv4 address for X722 */
 217 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 218 /* IPv4 Protocol for X722 */
 219 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 220 /* IPv4 Time to Live for X722 */
 221 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 222 /* IPv4 Type of Service (TOS) */
 223 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 224 /* IPv4 Protocol */
 225 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 226 /* IPv4 Time to Live */
 227 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 228 /* Source IPv6 address */
 229 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 230 /* Destination IPv6 address */
 231 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 232 /* IPv6 Traffic Class (TC) */
 233 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 234 /* IPv6 Next Header */
 235 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 236 /* IPv6 Hop Limit */
 237 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 238 /* Source L4 port */
 239 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 240 /* Destination L4 port */
 241 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 242 /* SCTP verification tag */
 243 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 244 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 245 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 246 /* Source port of tunneling UDP */
 247 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 248 /* Destination port of tunneling UDP */
 249 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 250 /* UDP Tunneling ID, NVGRE/GRE key */
 251 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 252 /* Last ether type */
 253 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 254 /* Tunneling outer destination IPv4 address */
 255 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 256 /* Tunneling outer destination IPv6 address */
 257 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 258 /* 1st word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 260 /* 2nd word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 262 /* 3rd word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 264 /* 4th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 266 /* 5th word of flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 268 /* 6th word of flex payload */
 269 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 270 /* 7th word of flex payload */
 271 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 272 /* 8th word of flex payload */
 273 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 274 /* all 8 words flex payload */
 275 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 276 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 277
 278 #define I40E_TRANSLATE_INSET 0
 279 #define I40E_TRANSLATE_REG   1
 280
 281 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 282 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 283 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 284 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 285 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 286 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 287
 288 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 290 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 291         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 292
 293 /* PCI offset for querying capability */
 294 #define PCI_DEV_CAP_REG            0xA4
 295 /* PCI offset for enabling/disabling Extended Tag */
 296 #define PCI_DEV_CTRL_REG           0xA8
 297 /* Bit mask of Extended Tag capability */
 298 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 299 /* Bit shift of Extended Tag enable/disable */
 300 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 301 /* Bit mask of Extended Tag enable/disable */
 302 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 303
 304 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 305 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 306 static int i40e_dev_configure(struct rte_eth_dev *dev);
 307 static int i40e_dev_start(struct rte_eth_dev *dev);
 308 static void i40e_dev_stop(struct rte_eth_dev *dev);
 309 static void i40e_dev_close(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 311 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 313 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 315 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 316 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 317                                struct rte_eth_stats *stats);
 318 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 319                                struct rte_eth_xstat *xstats, unsigned n);
 320 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 321                                      struct rte_eth_xstat_name *xstats_names,
 322                                      unsigned limit);
 323 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 324 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 325                                             uint16_t queue_id,
 326                                             uint8_t stat_idx,
 327                                             uint8_t is_rx);
 328 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 329                                 char *fw_version, size_t fw_size);
 330 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 331                               struct rte_eth_dev_info *dev_info);
 332 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 333                                 uint16_t vlan_id,
 334                                 int on);
 335 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 336                               enum rte_vlan_type vlan_type,
 337                               uint16_t tpid);
 338 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 339 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 340                                       uint16_t queue,
 341                                       int on);
 342 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 343 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 344 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 345 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 346                               struct rte_eth_fc_conf *fc_conf);
 347 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 348                               struct rte_eth_fc_conf *fc_conf);
 349 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 350                                        struct rte_eth_pfc_conf *pfc_conf);
 351 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 352                           struct ether_addr *mac_addr,
 353                           uint32_t index,
 354                           uint32_t pool);
 355 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 356 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 357                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                     uint16_t reta_size);
 359 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 360                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 361                                    uint16_t reta_size);
 362
 363 static int i40e_get_cap(struct i40e_hw *hw);
 364 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 365 static int i40e_pf_setup(struct i40e_pf *pf);
 366 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 367 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 368 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 369 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 370 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 371                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 372 static void i40e_stat_update_48(struct i40e_hw *hw,
 373                                uint32_t hireg,
 374                                uint32_t loreg,
 375                                bool offset_loaded,
 376                                uint64_t *offset,
 377                                uint64_t *stat);
 378 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 379 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 380                                        void *param);
 381 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 382                                 uint32_t base, uint32_t num);
 383 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 384 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 385                         uint32_t base);
 386 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 387                         uint16_t num);
 388 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 389 static int i40e_veb_release(struct i40e_veb *veb);
 390 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 391                                                 struct i40e_vsi *vsi);
 392 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 393 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 394 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 395                                              struct i40e_macvlan_filter *mv_f,
 396                                              int num,
 397                                              struct ether_addr *addr);
 398 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 399                                              struct i40e_macvlan_filter *mv_f,
 400                                              int num,
 401                                              uint16_t vlan);
 402 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 403 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 404                                     struct rte_eth_rss_conf *rss_conf);
 405 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 406                                       struct rte_eth_rss_conf *rss_conf);
 407 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 408                                         struct rte_eth_udp_tunnel *udp_tunnel);
 409 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 410                                         struct rte_eth_udp_tunnel *udp_tunnel);
 411 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 412 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 413                         struct rte_eth_ethertype_filter *filter,
 414                         bool add);
 415 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 416                                 enum rte_filter_op filter_op,
 417                                 void *arg);
 418 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 419                                 enum rte_filter_type filter_type,
 420                                 enum rte_filter_op filter_op,
 421                                 void *arg);
 422 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 423                                   struct rte_eth_dcb_info *dcb_info);
 424 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 425 static void i40e_configure_registers(struct i40e_hw *hw);
 426 static void i40e_hw_init(struct rte_eth_dev *dev);
 427 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 428 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 429                         struct rte_eth_mirror_conf *mirror_conf,
 430                         uint8_t sw_id, uint8_t on);
 431 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 432
 433 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 434 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 435 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp,
 437                                            uint32_t flags);
 438 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp);
 440 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 441
 442 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 443
 444 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 445                                    struct timespec *timestamp);
 446 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 447                                     const struct timespec *timestamp);
 448
 449 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 450                                          uint16_t queue_id);
 451 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 452                                           uint16_t queue_id);
 453
 454 static int i40e_get_regs(struct rte_eth_dev *dev,
 455                          struct rte_dev_reg_info *regs);
 456
 457 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 458
 459 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 460                            struct rte_dev_eeprom_info *eeprom);
 461
 462 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 463                                       struct ether_addr *mac_addr);
 464
 465 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 466
 467 static int i40e_ethertype_filter_convert(
 468         const struct rte_eth_ethertype_filter *input,
 469         struct i40e_ethertype_filter *filter);
 470 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 471                                    struct i40e_ethertype_filter *filter);
 472
 473 static int i40e_tunnel_filter_convert(
 474         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 475         struct i40e_tunnel_filter *tunnel_filter);
 476 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 477                                 struct i40e_tunnel_filter *tunnel_filter);
 478
 479 static const struct rte_pci_id pci_id_i40e_map[] = {
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 492         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 493         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 494         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 495         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 496         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 497         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 498         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 499         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 500         { .vendor_id = 0, /* sentinel */ },
 501 };
 502
 503 static const struct eth_dev_ops i40e_eth_dev_ops = {
 504         .dev_configure                = i40e_dev_configure,
 505         .dev_start                    = i40e_dev_start,
 506         .dev_stop                     = i40e_dev_stop,
 507         .dev_close                    = i40e_dev_close,
 508         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 509         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 510         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 511         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 512         .dev_set_link_up              = i40e_dev_set_link_up,
 513         .dev_set_link_down            = i40e_dev_set_link_down,
 514         .link_update                  = i40e_dev_link_update,
 515         .stats_get                    = i40e_dev_stats_get,
 516         .xstats_get                   = i40e_dev_xstats_get,
 517         .xstats_get_names             = i40e_dev_xstats_get_names,
 518         .stats_reset                  = i40e_dev_stats_reset,
 519         .xstats_reset                 = i40e_dev_stats_reset,
 520         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 521         .fw_version_get               = i40e_fw_version_get,
 522         .dev_infos_get                = i40e_dev_info_get,
 523         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 524         .vlan_filter_set              = i40e_vlan_filter_set,
 525         .vlan_tpid_set                = i40e_vlan_tpid_set,
 526         .vlan_offload_set             = i40e_vlan_offload_set,
 527         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 528         .vlan_pvid_set                = i40e_vlan_pvid_set,
 529         .rx_queue_start               = i40e_dev_rx_queue_start,
 530         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 531         .tx_queue_start               = i40e_dev_tx_queue_start,
 532         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 533         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 534         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 535         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 536         .rx_queue_release             = i40e_dev_rx_queue_release,
 537         .rx_queue_count               = i40e_dev_rx_queue_count,
 538         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 539         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 540         .tx_queue_release             = i40e_dev_tx_queue_release,
 541         .dev_led_on                   = i40e_dev_led_on,
 542         .dev_led_off                  = i40e_dev_led_off,
 543         .flow_ctrl_get                = i40e_flow_ctrl_get,
 544         .flow_ctrl_set                = i40e_flow_ctrl_set,
 545         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 546         .mac_addr_add                 = i40e_macaddr_add,
 547         .mac_addr_remove              = i40e_macaddr_remove,
 548         .reta_update                  = i40e_dev_rss_reta_update,
 549         .reta_query                   = i40e_dev_rss_reta_query,
 550         .rss_hash_update              = i40e_dev_rss_hash_update,
 551         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 552         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 553         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 554         .filter_ctrl                  = i40e_dev_filter_ctrl,
 555         .rxq_info_get                 = i40e_rxq_info_get,
 556         .txq_info_get                 = i40e_txq_info_get,
 557         .mirror_rule_set              = i40e_mirror_rule_set,
 558         .mirror_rule_reset            = i40e_mirror_rule_reset,
 559         .timesync_enable              = i40e_timesync_enable,
 560         .timesync_disable             = i40e_timesync_disable,
 561         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 562         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 563         .get_dcb_info                 = i40e_dev_get_dcb_info,
 564         .timesync_adjust_time         = i40e_timesync_adjust_time,
 565         .timesync_read_time           = i40e_timesync_read_time,
 566         .timesync_write_time          = i40e_timesync_write_time,
 567         .get_reg                      = i40e_get_regs,
 568         .get_eeprom_length            = i40e_get_eeprom_length,
 569         .get_eeprom                   = i40e_get_eeprom,
 570         .mac_addr_set                 = i40e_set_default_mac_addr,
 571         .mtu_set                      = i40e_dev_mtu_set,
 572 };
 573
 574 /* store statistics names and its offset in stats structure */
 575 struct rte_i40e_xstats_name_off {
 576         char name[RTE_ETH_XSTATS_NAME_SIZE];
 577         unsigned offset;
 578 };
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 581         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 582         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 583         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 584         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 585         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 586                 rx_unknown_protocol)},
 587         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 588         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 589         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 590         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 591 };
 592
 593 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 594                 sizeof(rte_i40e_stats_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 597         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 598                 tx_dropped_link_down)},
 599         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 600         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 601                 illegal_bytes)},
 602         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 603         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 604                 mac_local_faults)},
 605         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 606                 mac_remote_faults)},
 607         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 608                 rx_length_errors)},
 609         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 610         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 611         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 612         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 613         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 614         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 615                 rx_size_127)},
 616         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 617                 rx_size_255)},
 618         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 619                 rx_size_511)},
 620         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 621                 rx_size_1023)},
 622         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 623                 rx_size_1522)},
 624         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 625                 rx_size_big)},
 626         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 627                 rx_undersize)},
 628         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 629                 rx_oversize)},
 630         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 631                 mac_short_packet_dropped)},
 632         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 633                 rx_fragments)},
 634         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 635         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 636         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 637                 tx_size_127)},
 638         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 639                 tx_size_255)},
 640         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 641                 tx_size_511)},
 642         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 643                 tx_size_1023)},
 644         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 645                 tx_size_1522)},
 646         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 647                 tx_size_big)},
 648         {"rx_flow_director_atr_match_packets",
 649                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 650         {"rx_flow_director_sb_match_packets",
 651                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 652         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 653                 tx_lpi_status)},
 654         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 655                 rx_lpi_status)},
 656         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 657                 tx_lpi_count)},
 658         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 659                 rx_lpi_count)},
 660 };
 661
 662 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 663                 sizeof(rte_i40e_hw_port_strings[0]))
 664
 665 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 666         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 667                 priority_xon_rx)},
 668         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 669                 priority_xoff_rx)},
 670 };
 671
 672 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 673                 sizeof(rte_i40e_rxq_prio_strings[0]))
 674
 675 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 676         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 677                 priority_xon_tx)},
 678         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 679                 priority_xoff_tx)},
 680         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 681                 priority_xon_2_xoff)},
 682 };
 683
 684 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 685                 sizeof(rte_i40e_txq_prio_strings[0]))
 686
 687 static struct eth_driver rte_i40e_pmd = {
 688         .pci_drv = {
 689                 .id_table = pci_id_i40e_map,
 690                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 691                 .probe = rte_eth_dev_pci_probe,
 692                 .remove = rte_eth_dev_pci_remove,
 693         },
 694         .eth_dev_init = eth_i40e_dev_init,
 695         .eth_dev_uninit = eth_i40e_dev_uninit,
 696         .dev_private_size = sizeof(struct i40e_adapter),
 697 };
 698
 699 static inline int
 700 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 701                                      struct rte_eth_link *link)
 702 {
 703         struct rte_eth_link *dst = link;
 704         struct rte_eth_link *src = &(dev->data->dev_link);
 705
 706         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 707                                         *(uint64_t *)src) == 0)
 708                 return -1;
 709
 710         return 0;
 711 }
 712
 713 static inline int
 714 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 715                                       struct rte_eth_link *link)
 716 {
 717         struct rte_eth_link *dst = &(dev->data->dev_link);
 718         struct rte_eth_link *src = link;
 719
 720         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 721                                         *(uint64_t *)src) == 0)
 722                 return -1;
 723
 724         return 0;
 725 }
 726
 727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737
 738 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 739 {
 740         /*
 741          * Initialize registers for flexible payload, which should be set by NVM.
 742          * This should be removed from code once it is fixed in NVM.
 743          */
 744         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 745         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 746         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 747         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 749         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 750         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 751         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 752         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 753         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 754         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 755         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 756
 757         /* Initialize registers for parsing packet type of QinQ */
 758         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 759         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 760 }
 761
 762 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 763
 764 /*
 765  * Add a ethertype filter to drop all flow control frames transmitted
 766  * from VSIs.
 767 */
 768 static void
 769 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 770 {
 771         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 772         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 773                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 774                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 775         int ret;
 776
 777         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 778                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 779                                 pf->main_vsi_seid, 0,
 780                                 TRUE, NULL, NULL);
 781         if (ret)
 782                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 783                                   " frames from VSIs.");
 784 }
 785
 786 static int
 787 floating_veb_list_handler(__rte_unused const char *key,
 788                           const char *floating_veb_value,
 789                           void *opaque)
 790 {
 791         int idx = 0;
 792         unsigned int count = 0;
 793         char *end = NULL;
 794         int min, max;
 795         bool *vf_floating_veb = opaque;
 796
 797         while (isblank(*floating_veb_value))
 798                 floating_veb_value++;
 799
 800         /* Reset floating VEB configuration for VFs */
 801         for (idx = 0; idx < I40E_MAX_VF; idx++)
 802                 vf_floating_veb[idx] = false;
 803
 804         min = I40E_MAX_VF;
 805         do {
 806                 while (isblank(*floating_veb_value))
 807                         floating_veb_value++;
 808                 if (*floating_veb_value == '\0')
 809                         return -1;
 810                 errno = 0;
 811                 idx = strtoul(floating_veb_value, &end, 10);
 812                 if (errno || end == NULL)
 813                         return -1;
 814                 while (isblank(*end))
 815                         end++;
 816                 if (*end == '-') {
 817                         min = idx;
 818                 } else if ((*end == ';') || (*end == '\0')) {
 819                         max = idx;
 820                         if (min == I40E_MAX_VF)
 821                                 min = idx;
 822                         if (max >= I40E_MAX_VF)
 823                                 max = I40E_MAX_VF - 1;
 824                         for (idx = min; idx <= max; idx++) {
 825                                 vf_floating_veb[idx] = true;
 826                                 count++;
 827                         }
 828                         min = I40E_MAX_VF;
 829                 } else {
 830                         return -1;
 831                 }
 832                 floating_veb_value = end + 1;
 833         } while (*end != '\0');
 834
 835         if (count == 0)
 836                 return -1;
 837
 838         return 0;
 839 }
 840
 841 static void
 842 config_vf_floating_veb(struct rte_devargs *devargs,
 843                        uint16_t floating_veb,
 844                        bool *vf_floating_veb)
 845 {
 846         struct rte_kvargs *kvlist;
 847         int i;
 848         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 849
 850         if (!floating_veb)
 851                 return;
 852         /* All the VFs attach to the floating VEB by default
 853          * when the floating VEB is enabled.
 854          */
 855         for (i = 0; i < I40E_MAX_VF; i++)
 856                 vf_floating_veb[i] = true;
 857
 858         if (devargs == NULL)
 859                 return;
 860
 861         kvlist = rte_kvargs_parse(devargs->args, NULL);
 862         if (kvlist == NULL)
 863                 return;
 864
 865         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 866                 rte_kvargs_free(kvlist);
 867                 return;
 868         }
 869         /* When the floating_veb_list parameter exists, all the VFs
 870          * will attach to the legacy VEB firstly, then configure VFs
 871          * to the floating VEB according to the floating_veb_list.
 872          */
 873         if (rte_kvargs_process(kvlist, floating_veb_list,
 874                                floating_veb_list_handler,
 875                                vf_floating_veb) < 0) {
 876                 rte_kvargs_free(kvlist);
 877                 return;
 878         }
 879         rte_kvargs_free(kvlist);
 880 }
 881
 882 static int
 883 i40e_check_floating_handler(__rte_unused const char *key,
 884                             const char *value,
 885                             __rte_unused void *opaque)
 886 {
 887         if (strcmp(value, "1"))
 888                 return -1;
 889
 890         return 0;
 891 }
 892
 893 static int
 894 is_floating_veb_supported(struct rte_devargs *devargs)
 895 {
 896         struct rte_kvargs *kvlist;
 897         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 898
 899         if (devargs == NULL)
 900                 return 0;
 901
 902         kvlist = rte_kvargs_parse(devargs->args, NULL);
 903         if (kvlist == NULL)
 904                 return 0;
 905
 906         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 907                 rte_kvargs_free(kvlist);
 908                 return 0;
 909         }
 910         /* Floating VEB is enabled when there's key-value:
 911          * enable_floating_veb=1
 912          */
 913         if (rte_kvargs_process(kvlist, floating_veb_key,
 914                                i40e_check_floating_handler, NULL) < 0) {
 915                 rte_kvargs_free(kvlist);
 916                 return 0;
 917         }
 918         rte_kvargs_free(kvlist);
 919
 920         return 1;
 921 }
 922
 923 static void
 924 config_floating_veb(struct rte_eth_dev *dev)
 925 {
 926         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 929
 930         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 931
 932         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 933                 pf->floating_veb =
 934                         is_floating_veb_supported(pci_dev->device.devargs);
 935                 config_vf_floating_veb(pci_dev->device.devargs,
 936                                        pf->floating_veb,
 937                                        pf->floating_veb_list);
 938         } else {
 939                 pf->floating_veb = false;
 940         }
 941 }
 942
 943 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 944 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 945
 946 static int
 947 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 948 {
 949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 950         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 951         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 952         int ret;
 953
 954         struct rte_hash_parameters ethertype_hash_params = {
 955                 .name = ethertype_hash_name,
 956                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 957                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 958                 .hash_func = rte_hash_crc,
 959         };
 960
 961         /* Initialize ethertype filter rule list and hash */
 962         TAILQ_INIT(&ethertype_rule->ethertype_list);
 963         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 964                  "ethertype_%s", dev->data->name);
 965         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 966         if (!ethertype_rule->hash_table) {
 967                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 968                 return -EINVAL;
 969         }
 970         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 971                                        sizeof(struct i40e_ethertype_filter *) *
 972                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 973                                        0);
 974         if (!ethertype_rule->hash_map) {
 975                 PMD_INIT_LOG(ERR,
 976                              "Failed to allocate memory for ethertype hash map!");
 977                 ret = -ENOMEM;
 978                 goto err_ethertype_hash_map_alloc;
 979         }
 980
 981         return 0;
 982
 983 err_ethertype_hash_map_alloc:
 984         rte_hash_free(ethertype_rule->hash_table);
 985
 986         return ret;
 987 }
 988
 989 static int
 990 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 991 {
 992         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 993         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 994         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 995         int ret;
 996
 997         struct rte_hash_parameters tunnel_hash_params = {
 998                 .name = tunnel_hash_name,
 999                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1000                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1001                 .hash_func = rte_hash_crc,
1002         };
1003
1004         /* Initialize tunnel filter rule list and hash */
1005         TAILQ_INIT(&tunnel_rule->tunnel_list);
1006         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1007                  "tunnel_%s", dev->data->name);
1008         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1009         if (!tunnel_rule->hash_table) {
1010                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1011                 return -EINVAL;
1012         }
1013         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1014                                     sizeof(struct i40e_tunnel_filter *) *
1015                                     I40E_MAX_TUNNEL_FILTER_NUM,
1016                                     0);
1017         if (!tunnel_rule->hash_map) {
1018                 PMD_INIT_LOG(ERR,
1019                              "Failed to allocate memory for tunnel hash map!");
1020                 ret = -ENOMEM;
1021                 goto err_tunnel_hash_map_alloc;
1022         }
1023
1024         return 0;
1025
1026 err_tunnel_hash_map_alloc:
1027         rte_hash_free(tunnel_rule->hash_table);
1028
1029         return ret;
1030 }
1031
1032 static int
1033 eth_i40e_dev_init(struct rte_eth_dev *dev)
1034 {
1035         struct rte_pci_device *pci_dev;
1036         struct rte_intr_handle *intr_handle;
1037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039         struct i40e_vsi *vsi;
1040         int ret;
1041         uint32_t len;
1042         uint8_t aq_fail = 0;
1043
1044         PMD_INIT_FUNC_TRACE();
1045
1046         dev->dev_ops = &i40e_eth_dev_ops;
1047         dev->rx_pkt_burst = i40e_recv_pkts;
1048         dev->tx_pkt_burst = i40e_xmit_pkts;
1049         dev->tx_pkt_prepare = i40e_prep_pkts;
1050
1051         /* for secondary processes, we don't initialise any further as primary
1052          * has already done this work. Only check we don't need a different
1053          * RX function */
1054         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1055                 i40e_set_rx_function(dev);
1056                 i40e_set_tx_function(dev);
1057                 return 0;
1058         }
1059         pci_dev = I40E_DEV_TO_PCI(dev);
1060         intr_handle = &pci_dev->intr_handle;
1061
1062         rte_eth_copy_pci_info(dev, pci_dev);
1063         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1064
1065         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066         pf->adapter->eth_dev = dev;
1067         pf->dev_data = dev->data;
1068
1069         hw->back = I40E_PF_TO_ADAPTER(pf);
1070         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1071         if (!hw->hw_addr) {
1072                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1073                              "as address is NULL");
1074                 return -ENODEV;
1075         }
1076
1077         hw->vendor_id = pci_dev->id.vendor_id;
1078         hw->device_id = pci_dev->id.device_id;
1079         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1080         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1081         hw->bus.device = pci_dev->addr.devid;
1082         hw->bus.func = pci_dev->addr.function;
1083         hw->adapter_stopped = 0;
1084
1085         /* Make sure all is clean before doing PF reset */
1086         i40e_clear_hw(hw);
1087
1088         /* Initialize the hardware */
1089         i40e_hw_init(dev);
1090
1091         /* Reset here to make sure all is clean for each PF */
1092         ret = i40e_pf_reset(hw);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1095                 return ret;
1096         }
1097
1098         /* Initialize the shared code (base driver) */
1099         ret = i40e_init_shared_code(hw);
1100         if (ret) {
1101                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1102                 return ret;
1103         }
1104
1105         /*
1106          * To work around the NVM issue, initialize registers
1107          * for flexible payload and packet type of QinQ by
1108          * software. It should be removed once issues are fixed
1109          * in NVM.
1110          */
1111         i40e_GLQF_reg_init(hw);
1112
1113         /* Initialize the input set for filters (hash and fd) to default value */
1114         i40e_filter_input_set_init(pf);
1115
1116         /* Initialize the parameters for adminq */
1117         i40e_init_adminq_parameter(hw);
1118         ret = i40e_init_adminq(hw);
1119         if (ret != I40E_SUCCESS) {
1120                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1121                 return -EIO;
1122         }
1123         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1124                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1125                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1126                      ((hw->nvm.version >> 12) & 0xf),
1127                      ((hw->nvm.version >> 4) & 0xff),
1128                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1129
1130         /* Need the special FW version to support floating VEB */
1131         config_floating_veb(dev);
1132         /* Clear PXE mode */
1133         i40e_clear_pxe_mode(hw);
1134         ret = i40e_dev_sync_phy_type(hw);
1135         if (ret) {
1136                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1137                 goto err_sync_phy_type;
1138         }
1139         /*
1140          * On X710, performance number is far from the expectation on recent
1141          * firmware versions. The fix for this issue may not be integrated in
1142          * the following firmware version. So the workaround in software driver
1143          * is needed. It needs to modify the initial values of 3 internal only
1144          * registers. Note that the workaround can be removed when it is fixed
1145          * in firmware in the future.
1146          */
1147         i40e_configure_registers(hw);
1148
1149         /* Get hw capabilities */
1150         ret = i40e_get_cap(hw);
1151         if (ret != I40E_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1153                 goto err_get_capabilities;
1154         }
1155
1156         /* Initialize parameters for PF */
1157         ret = i40e_pf_parameter_init(dev);
1158         if (ret != 0) {
1159                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1160                 goto err_parameter_init;
1161         }
1162
1163         /* Initialize the queue management */
1164         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1165         if (ret < 0) {
1166                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1167                 goto err_qp_pool_init;
1168         }
1169         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1170                                 hw->func_caps.num_msix_vectors - 1);
1171         if (ret < 0) {
1172                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1173                 goto err_msix_pool_init;
1174         }
1175
1176         /* Initialize lan hmc */
1177         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1178                                 hw->func_caps.num_rx_qp, 0, 0);
1179         if (ret != I40E_SUCCESS) {
1180                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1181                 goto err_init_lan_hmc;
1182         }
1183
1184         /* Configure lan hmc */
1185         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1186         if (ret != I40E_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1188                 goto err_configure_lan_hmc;
1189         }
1190
1191         /* Get and check the mac address */
1192         i40e_get_mac_addr(hw, hw->mac.addr);
1193         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR, "mac address is not valid");
1195                 ret = -EIO;
1196                 goto err_get_mac_addr;
1197         }
1198         /* Copy the permanent MAC address */
1199         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1200                         (struct ether_addr *) hw->mac.perm_addr);
1201
1202         /* Disable flow control */
1203         hw->fc.requested_mode = I40E_FC_NONE;
1204         i40e_set_fc(hw, &aq_fail, TRUE);
1205
1206         /* Set the global registers with default ether type value */
1207         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1208         if (ret != I40E_SUCCESS) {
1209                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1210                              "VLAN ether type");
1211                 goto err_setup_pf_switch;
1212         }
1213
1214         /* PF setup, which includes VSI setup */
1215         ret = i40e_pf_setup(pf);
1216         if (ret) {
1217                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1218                 goto err_setup_pf_switch;
1219         }
1220
1221         /* reset all stats of the device, including pf and main vsi */
1222         i40e_dev_stats_reset(dev);
1223
1224         vsi = pf->main_vsi;
1225
1226         /* Disable double vlan by default */
1227         i40e_vsi_config_double_vlan(vsi, FALSE);
1228
1229         /* Disable S-TAG identification when floating_veb is disabled */
1230         if (!pf->floating_veb) {
1231                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1232                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1233                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1234                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1235                 }
1236         }
1237
1238         if (!vsi->max_macaddrs)
1239                 len = ETHER_ADDR_LEN;
1240         else
1241                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1242
1243         /* Should be after VSI initialized */
1244         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1245         if (!dev->data->mac_addrs) {
1246                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1247                                         "for storing mac address");
1248                 goto err_mac_alloc;
1249         }
1250         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1251                                         &dev->data->mac_addrs[0]);
1252
1253         /* initialize pf host driver to setup SRIOV resource if applicable */
1254         i40e_pf_host_init(dev);
1255
1256         /* register callback func to eal lib */
1257         rte_intr_callback_register(intr_handle,
1258                                    i40e_dev_interrupt_handler, dev);
1259
1260         /* configure and enable device interrupt */
1261         i40e_pf_config_irq0(hw, TRUE);
1262         i40e_pf_enable_irq0(hw);
1263
1264         /* enable uio intr after callback register */
1265         rte_intr_enable(intr_handle);
1266         /*
1267          * Add an ethertype filter to drop all flow control frames transmitted
1268          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1269          * frames to wire.
1270          */
1271         i40e_add_tx_flow_control_drop_filter(pf);
1272
1273         /* Set the max frame size to 0x2600 by default,
1274          * in case other drivers changed the default value.
1275          */
1276         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1277
1278         /* initialize mirror rule list */
1279         TAILQ_INIT(&pf->mirror_list);
1280
1281         /* Init dcb to sw mode by default */
1282         ret = i40e_dcb_init_configure(dev, TRUE);
1283         if (ret != I40E_SUCCESS) {
1284                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1285                 pf->flags &= ~I40E_FLAG_DCB;
1286         }
1287
1288         ret = i40e_init_ethtype_filter_list(dev);
1289         if (ret < 0)
1290                 goto err_init_ethtype_filter_list;
1291         ret = i40e_init_tunnel_filter_list(dev);
1292         if (ret < 0)
1293                 goto err_init_tunnel_filter_list;
1294
1295         return 0;
1296
1297 err_init_tunnel_filter_list:
1298         rte_free(pf->ethertype.hash_table);
1299         rte_free(pf->ethertype.hash_map);
1300 err_init_ethtype_filter_list:
1301         rte_free(dev->data->mac_addrs);
1302 err_mac_alloc:
1303         i40e_vsi_release(pf->main_vsi);
1304 err_setup_pf_switch:
1305 err_get_mac_addr:
1306 err_configure_lan_hmc:
1307         (void)i40e_shutdown_lan_hmc(hw);
1308 err_init_lan_hmc:
1309         i40e_res_pool_destroy(&pf->msix_pool);
1310 err_msix_pool_init:
1311         i40e_res_pool_destroy(&pf->qp_pool);
1312 err_qp_pool_init:
1313 err_parameter_init:
1314 err_get_capabilities:
1315 err_sync_phy_type:
1316         (void)i40e_shutdown_adminq(hw);
1317
1318         return ret;
1319 }
1320
1321 static void
1322 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1323 {
1324         struct i40e_ethertype_filter *p_ethertype;
1325         struct i40e_ethertype_rule *ethertype_rule;
1326
1327         ethertype_rule = &pf->ethertype;
1328         /* Remove all ethertype filter rules and hash */
1329         if (ethertype_rule->hash_map)
1330                 rte_free(ethertype_rule->hash_map);
1331         if (ethertype_rule->hash_table)
1332                 rte_hash_free(ethertype_rule->hash_table);
1333
1334         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1335                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1336                              p_ethertype, rules);
1337                 rte_free(p_ethertype);
1338         }
1339 }
1340
1341 static void
1342 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1343 {
1344         struct i40e_tunnel_filter *p_tunnel;
1345         struct i40e_tunnel_rule *tunnel_rule;
1346
1347         tunnel_rule = &pf->tunnel;
1348         /* Remove all tunnel director rules and hash */
1349         if (tunnel_rule->hash_map)
1350                 rte_free(tunnel_rule->hash_map);
1351         if (tunnel_rule->hash_table)
1352                 rte_hash_free(tunnel_rule->hash_table);
1353
1354         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1355                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1356                 rte_free(p_tunnel);
1357         }
1358 }
1359
1360 static int
1361 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1362 {
1363         struct i40e_pf *pf;
1364         struct rte_pci_device *pci_dev;
1365         struct rte_intr_handle *intr_handle;
1366         struct i40e_hw *hw;
1367         struct i40e_filter_control_settings settings;
1368         int ret;
1369         uint8_t aq_fail = 0;
1370
1371         PMD_INIT_FUNC_TRACE();
1372
1373         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1374                 return 0;
1375
1376         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1377         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1378         pci_dev = I40E_DEV_TO_PCI(dev);
1379         intr_handle = &pci_dev->intr_handle;
1380
1381         if (hw->adapter_stopped == 0)
1382                 i40e_dev_close(dev);
1383
1384         dev->dev_ops = NULL;
1385         dev->rx_pkt_burst = NULL;
1386         dev->tx_pkt_burst = NULL;
1387
1388         /* Clear PXE mode */
1389         i40e_clear_pxe_mode(hw);
1390
1391         /* Unconfigure filter control */
1392         memset(&settings, 0, sizeof(settings));
1393         ret = i40e_set_filter_control(hw, &settings);
1394         if (ret)
1395                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1396                                         ret);
1397
1398         /* Disable flow control */
1399         hw->fc.requested_mode = I40E_FC_NONE;
1400         i40e_set_fc(hw, &aq_fail, TRUE);
1401
1402         /* uninitialize pf host driver */
1403         i40e_pf_host_uninit(dev);
1404
1405         rte_free(dev->data->mac_addrs);
1406         dev->data->mac_addrs = NULL;
1407
1408         /* disable uio intr before callback unregister */
1409         rte_intr_disable(intr_handle);
1410
1411         /* register callback func to eal lib */
1412         rte_intr_callback_unregister(intr_handle,
1413                                      i40e_dev_interrupt_handler, dev);
1414
1415         i40e_rm_ethtype_filter_list(pf);
1416         i40e_rm_tunnel_filter_list(pf);
1417
1418         return 0;
1419 }
1420
1421 static int
1422 i40e_dev_configure(struct rte_eth_dev *dev)
1423 {
1424         struct i40e_adapter *ad =
1425                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1428         int i, ret;
1429
1430         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1431          * bulk allocation or vector Rx preconditions we will reset it.
1432          */
1433         ad->rx_bulk_alloc_allowed = true;
1434         ad->rx_vec_allowed = true;
1435         ad->tx_simple_allowed = true;
1436         ad->tx_vec_allowed = true;
1437
1438         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1439                 ret = i40e_fdir_setup(pf);
1440                 if (ret != I40E_SUCCESS) {
1441                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1442                         return -ENOTSUP;
1443                 }
1444                 ret = i40e_fdir_configure(dev);
1445                 if (ret < 0) {
1446                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1447                         goto err;
1448                 }
1449         } else
1450                 i40e_fdir_teardown(pf);
1451
1452         ret = i40e_dev_init_vlan(dev);
1453         if (ret < 0)
1454                 goto err;
1455
1456         /* VMDQ setup.
1457          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1458          *  RSS setting have different requirements.
1459          *  General PMD driver call sequence are NIC init, configure,
1460          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1461          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1462          *  applicable. So, VMDQ setting has to be done before
1463          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1464          *  For RSS setting, it will try to calculate actual configured RX queue
1465          *  number, which will be available after rx_queue_setup(). dev_start()
1466          *  function is good to place RSS setup.
1467          */
1468         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1469                 ret = i40e_vmdq_setup(dev);
1470                 if (ret)
1471                         goto err;
1472         }
1473
1474         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1475                 ret = i40e_dcb_setup(dev);
1476                 if (ret) {
1477                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1478                         goto err_dcb;
1479                 }
1480         }
1481
1482         return 0;
1483
1484 err_dcb:
1485         /* need to release vmdq resource if exists */
1486         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1487                 i40e_vsi_release(pf->vmdq[i].vsi);
1488                 pf->vmdq[i].vsi = NULL;
1489         }
1490         rte_free(pf->vmdq);
1491         pf->vmdq = NULL;
1492 err:
1493         /* need to release fdir resource if exists */
1494         i40e_fdir_teardown(pf);
1495         return ret;
1496 }
1497
1498 void
1499 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1500 {
1501         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1502         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1503         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1504         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1505         uint16_t msix_vect = vsi->msix_intr;
1506         uint16_t i;
1507
1508         for (i = 0; i < vsi->nb_qps; i++) {
1509                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1510                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1511                 rte_wmb();
1512         }
1513
1514         if (vsi->type != I40E_VSI_SRIOV) {
1515                 if (!rte_intr_allow_others(intr_handle)) {
1516                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1517                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1518                         I40E_WRITE_REG(hw,
1519                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1520                                        0);
1521                 } else {
1522                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1523                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1524                         I40E_WRITE_REG(hw,
1525                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1526                                                        msix_vect - 1), 0);
1527                 }
1528         } else {
1529                 uint32_t reg;
1530                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1531                         vsi->user_param + (msix_vect - 1);
1532
1533                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1534                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1535         }
1536         I40E_WRITE_FLUSH(hw);
1537 }
1538
1539 static void
1540 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1541                        int base_queue, int nb_queue)
1542 {
1543         int i;
1544         uint32_t val;
1545         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1546
1547         /* Bind all RX queues to allocated MSIX interrupt */
1548         for (i = 0; i < nb_queue; i++) {
1549                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1550                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1551                         ((base_queue + i + 1) <<
1552                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1553                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1554                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1555
1556                 if (i == nb_queue - 1)
1557                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1558                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1559         }
1560
1561         /* Write first RX queue to Link list register as the head element */
1562         if (vsi->type != I40E_VSI_SRIOV) {
1563                 uint16_t interval =
1564                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1565
1566                 if (msix_vect == I40E_MISC_VEC_ID) {
1567                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1568                                        (base_queue <<
1569                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1570                                        (0x0 <<
1571                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1572                         I40E_WRITE_REG(hw,
1573                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1574                                        interval);
1575                 } else {
1576                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1577                                        (base_queue <<
1578                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1579                                        (0x0 <<
1580                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1581                         I40E_WRITE_REG(hw,
1582                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1583                                                        msix_vect - 1),
1584                                        interval);
1585                 }
1586         } else {
1587                 uint32_t reg;
1588
1589                 if (msix_vect == I40E_MISC_VEC_ID) {
1590                         I40E_WRITE_REG(hw,
1591                                        I40E_VPINT_LNKLST0(vsi->user_param),
1592                                        (base_queue <<
1593                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1594                                        (0x0 <<
1595                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1596                 } else {
1597                         /* num_msix_vectors_vf needs to minus irq0 */
1598                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1599                                 vsi->user_param + (msix_vect - 1);
1600
1601                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1602                                        (base_queue <<
1603                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1604                                        (0x0 <<
1605                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1606                 }
1607         }
1608
1609         I40E_WRITE_FLUSH(hw);
1610 }
1611
1612 void
1613 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1614 {
1615         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1616         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1618         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1619         uint16_t msix_vect = vsi->msix_intr;
1620         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1621         uint16_t queue_idx = 0;
1622         int record = 0;
1623         uint32_t val;
1624         int i;
1625
1626         for (i = 0; i < vsi->nb_qps; i++) {
1627                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1628                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1629         }
1630
1631         /* INTENA flag is not auto-cleared for interrupt */
1632         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1633         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1634                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1635                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1636         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1637
1638         /* VF bind interrupt */
1639         if (vsi->type == I40E_VSI_SRIOV) {
1640                 __vsi_queues_bind_intr(vsi, msix_vect,
1641                                        vsi->base_queue, vsi->nb_qps);
1642                 return;
1643         }
1644
1645         /* PF & VMDq bind interrupt */
1646         if (rte_intr_dp_is_en(intr_handle)) {
1647                 if (vsi->type == I40E_VSI_MAIN) {
1648                         queue_idx = 0;
1649                         record = 1;
1650                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1651                         struct i40e_vsi *main_vsi =
1652                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1653                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1654                         record = 1;
1655                 }
1656         }
1657
1658         for (i = 0; i < vsi->nb_used_qps; i++) {
1659                 if (nb_msix <= 1) {
1660                         if (!rte_intr_allow_others(intr_handle))
1661                                 /* allow to share MISC_VEC_ID */
1662                                 msix_vect = I40E_MISC_VEC_ID;
1663
1664                         /* no enough msix_vect, map all to one */
1665                         __vsi_queues_bind_intr(vsi, msix_vect,
1666                                                vsi->base_queue + i,
1667                                                vsi->nb_used_qps - i);
1668                         for (; !!record && i < vsi->nb_used_qps; i++)
1669                                 intr_handle->intr_vec[queue_idx + i] =
1670                                         msix_vect;
1671                         break;
1672                 }
1673                 /* 1:1 queue/msix_vect mapping */
1674                 __vsi_queues_bind_intr(vsi, msix_vect,
1675                                        vsi->base_queue + i, 1);
1676                 if (!!record)
1677                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1678
1679                 msix_vect++;
1680                 nb_msix--;
1681         }
1682 }
1683
1684 static void
1685 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1686 {
1687         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1688         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1691         uint16_t interval = i40e_calc_itr_interval(\
1692                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1693         uint16_t msix_intr, i;
1694
1695         if (rte_intr_allow_others(intr_handle))
1696                 for (i = 0; i < vsi->nb_msix; i++) {
1697                         msix_intr = vsi->msix_intr + i;
1698                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1699                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1700                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1701                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1702                                 (interval <<
1703                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1704                 }
1705         else
1706                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1707                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1708                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1709                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1710                                (interval <<
1711                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1712
1713         I40E_WRITE_FLUSH(hw);
1714 }
1715
1716 static void
1717 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1718 {
1719         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1720         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1721         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1722         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1723         uint16_t msix_intr, i;
1724
1725         if (rte_intr_allow_others(intr_handle))
1726                 for (i = 0; i < vsi->nb_msix; i++) {
1727                         msix_intr = vsi->msix_intr + i;
1728                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1729                                        0);
1730                 }
1731         else
1732                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1733
1734         I40E_WRITE_FLUSH(hw);
1735 }
1736
1737 static inline uint8_t
1738 i40e_parse_link_speeds(uint16_t link_speeds)
1739 {
1740         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1741
1742         if (link_speeds & ETH_LINK_SPEED_40G)
1743                 link_speed |= I40E_LINK_SPEED_40GB;
1744         if (link_speeds & ETH_LINK_SPEED_25G)
1745                 link_speed |= I40E_LINK_SPEED_25GB;
1746         if (link_speeds & ETH_LINK_SPEED_20G)
1747                 link_speed |= I40E_LINK_SPEED_20GB;
1748         if (link_speeds & ETH_LINK_SPEED_10G)
1749                 link_speed |= I40E_LINK_SPEED_10GB;
1750         if (link_speeds & ETH_LINK_SPEED_1G)
1751                 link_speed |= I40E_LINK_SPEED_1GB;
1752         if (link_speeds & ETH_LINK_SPEED_100M)
1753                 link_speed |= I40E_LINK_SPEED_100MB;
1754
1755         return link_speed;
1756 }
1757
1758 static int
1759 i40e_phy_conf_link(struct i40e_hw *hw,
1760                    uint8_t abilities,
1761                    uint8_t force_speed)
1762 {
1763         enum i40e_status_code status;
1764         struct i40e_aq_get_phy_abilities_resp phy_ab;
1765         struct i40e_aq_set_phy_config phy_conf;
1766         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1767                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1768                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1769                         I40E_AQ_PHY_FLAG_LOW_POWER;
1770         const uint8_t advt = I40E_LINK_SPEED_40GB |
1771                         I40E_LINK_SPEED_25GB |
1772                         I40E_LINK_SPEED_10GB |
1773                         I40E_LINK_SPEED_1GB |
1774                         I40E_LINK_SPEED_100MB;
1775         int ret = -ENOTSUP;
1776
1777
1778         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1779                                               NULL);
1780         if (status)
1781                 return ret;
1782
1783         memset(&phy_conf, 0, sizeof(phy_conf));
1784
1785         /* bits 0-2 use the values from get_phy_abilities_resp */
1786         abilities &= ~mask;
1787         abilities |= phy_ab.abilities & mask;
1788
1789         /* update ablities and speed */
1790         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1791                 phy_conf.link_speed = advt;
1792         else
1793                 phy_conf.link_speed = force_speed;
1794
1795         phy_conf.abilities = abilities;
1796
1797         /* use get_phy_abilities_resp value for the rest */
1798         phy_conf.phy_type = phy_ab.phy_type;
1799         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1800         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1801         phy_conf.eee_capability = phy_ab.eee_capability;
1802         phy_conf.eeer = phy_ab.eeer_val;
1803         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1804
1805         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1806                     phy_ab.abilities, phy_ab.link_speed);
1807         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1808                     phy_conf.abilities, phy_conf.link_speed);
1809
1810         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1811         if (status)
1812                 return ret;
1813
1814         return I40E_SUCCESS;
1815 }
1816
1817 static int
1818 i40e_apply_link_speed(struct rte_eth_dev *dev)
1819 {
1820         uint8_t speed;
1821         uint8_t abilities = 0;
1822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         struct rte_eth_conf *conf = &dev->data->dev_conf;
1824
1825         speed = i40e_parse_link_speeds(conf->link_speeds);
1826         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1827         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1828                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1829         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1830
1831         /* Skip changing speed on 40G interfaces, FW does not support */
1832         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1833                 speed =  I40E_LINK_SPEED_UNKNOWN;
1834                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1835         }
1836
1837         return i40e_phy_conf_link(hw, abilities, speed);
1838 }
1839
1840 static int
1841 i40e_dev_start(struct rte_eth_dev *dev)
1842 {
1843         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct i40e_vsi *main_vsi = pf->main_vsi;
1846         int ret, i;
1847         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1848         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1849         uint32_t intr_vector = 0;
1850
1851         hw->adapter_stopped = 0;
1852
1853         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1854                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1855                              dev->data->port_id);
1856                 return -EINVAL;
1857         }
1858
1859         rte_intr_disable(intr_handle);
1860
1861         if ((rte_intr_cap_multiple(intr_handle) ||
1862              !RTE_ETH_DEV_SRIOV(dev).active) &&
1863             dev->data->dev_conf.intr_conf.rxq != 0) {
1864                 intr_vector = dev->data->nb_rx_queues;
1865                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1866                         return -1;
1867         }
1868
1869         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1870                 intr_handle->intr_vec =
1871                         rte_zmalloc("intr_vec",
1872                                     dev->data->nb_rx_queues * sizeof(int),
1873                                     0);
1874                 if (!intr_handle->intr_vec) {
1875                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1876                                      " intr_vec\n", dev->data->nb_rx_queues);
1877                         return -ENOMEM;
1878                 }
1879         }
1880
1881         /* Initialize VSI */
1882         ret = i40e_dev_rxtx_init(pf);
1883         if (ret != I40E_SUCCESS) {
1884                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1885                 goto err_up;
1886         }
1887
1888         /* Map queues with MSIX interrupt */
1889         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1890                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1891         i40e_vsi_queues_bind_intr(main_vsi);
1892         i40e_vsi_enable_queues_intr(main_vsi);
1893
1894         /* Map VMDQ VSI queues with MSIX interrupt */
1895         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1896                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1897                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1898                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1899         }
1900
1901         /* enable FDIR MSIX interrupt */
1902         if (pf->fdir.fdir_vsi) {
1903                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1904                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1905         }
1906
1907         /* Enable all queues which have been configured */
1908         ret = i40e_dev_switch_queues(pf, TRUE);
1909         if (ret != I40E_SUCCESS) {
1910                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1911                 goto err_up;
1912         }
1913
1914         /* Enable receiving broadcast packets */
1915         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1916         if (ret != I40E_SUCCESS)
1917                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1918
1919         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1920                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1921                                                 true, NULL);
1922                 if (ret != I40E_SUCCESS)
1923                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1924         }
1925
1926         /* Apply link configure */
1927         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1928                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1929                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1930                                 ETH_LINK_SPEED_40G)) {
1931                 PMD_DRV_LOG(ERR, "Invalid link setting");
1932                 goto err_up;
1933         }
1934         ret = i40e_apply_link_speed(dev);
1935         if (I40E_SUCCESS != ret) {
1936                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1937                 goto err_up;
1938         }
1939
1940         if (!rte_intr_allow_others(intr_handle)) {
1941                 rte_intr_callback_unregister(intr_handle,
1942                                              i40e_dev_interrupt_handler,
1943                                              (void *)dev);
1944                 /* configure and enable device interrupt */
1945                 i40e_pf_config_irq0(hw, FALSE);
1946                 i40e_pf_enable_irq0(hw);
1947
1948                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1949                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1950                                      " no intr multiplex\n");
1951         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1952                 ret = i40e_aq_set_phy_int_mask(hw,
1953                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1954                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1955                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1956                 if (ret != I40E_SUCCESS)
1957                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1958
1959                 /* Call get_link_info aq commond to enable LSE */
1960                 i40e_dev_link_update(dev, 0);
1961         }
1962
1963         /* enable uio intr after callback register */
1964         rte_intr_enable(intr_handle);
1965
1966         return I40E_SUCCESS;
1967
1968 err_up:
1969         i40e_dev_switch_queues(pf, FALSE);
1970         i40e_dev_clear_queues(dev);
1971
1972         return ret;
1973 }
1974
1975 static void
1976 i40e_dev_stop(struct rte_eth_dev *dev)
1977 {
1978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1979         struct i40e_vsi *main_vsi = pf->main_vsi;
1980         struct i40e_mirror_rule *p_mirror;
1981         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1982         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1983         int i;
1984
1985         /* Disable all queues */
1986         i40e_dev_switch_queues(pf, FALSE);
1987
1988         /* un-map queues with interrupt registers */
1989         i40e_vsi_disable_queues_intr(main_vsi);
1990         i40e_vsi_queues_unbind_intr(main_vsi);
1991
1992         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1993                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1994                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1995         }
1996
1997         if (pf->fdir.fdir_vsi) {
1998                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1999                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2000         }
2001         /* Clear all queues and release memory */
2002         i40e_dev_clear_queues(dev);
2003
2004         /* Set link down */
2005         i40e_dev_set_link_down(dev);
2006
2007         /* Remove all mirror rules */
2008         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2009                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2010                 rte_free(p_mirror);
2011         }
2012         pf->nb_mirror_rule = 0;
2013
2014         if (!rte_intr_allow_others(intr_handle))
2015                 /* resume to the default handler */
2016                 rte_intr_callback_register(intr_handle,
2017                                            i40e_dev_interrupt_handler,
2018                                            (void *)dev);
2019
2020         /* Clean datapath event and queue/vec mapping */
2021         rte_intr_efd_disable(intr_handle);
2022         if (intr_handle->intr_vec) {
2023                 rte_free(intr_handle->intr_vec);
2024                 intr_handle->intr_vec = NULL;
2025         }
2026 }
2027
2028 static void
2029 i40e_dev_close(struct rte_eth_dev *dev)
2030 {
2031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2032         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2034         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2035         uint32_t reg;
2036         int i;
2037
2038         PMD_INIT_FUNC_TRACE();
2039
2040         i40e_dev_stop(dev);
2041         hw->adapter_stopped = 1;
2042         i40e_dev_free_queues(dev);
2043
2044         /* Disable interrupt */
2045         i40e_pf_disable_irq0(hw);
2046         rte_intr_disable(intr_handle);
2047
2048         /* shutdown and destroy the HMC */
2049         i40e_shutdown_lan_hmc(hw);
2050
2051         /* release all the existing VSIs and VEBs */
2052         i40e_fdir_teardown(pf);
2053         i40e_vsi_release(pf->main_vsi);
2054
2055         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2056                 i40e_vsi_release(pf->vmdq[i].vsi);
2057                 pf->vmdq[i].vsi = NULL;
2058         }
2059
2060         rte_free(pf->vmdq);
2061         pf->vmdq = NULL;
2062
2063         /* shutdown the adminq */
2064         i40e_aq_queue_shutdown(hw, true);
2065         i40e_shutdown_adminq(hw);
2066
2067         i40e_res_pool_destroy(&pf->qp_pool);
2068         i40e_res_pool_destroy(&pf->msix_pool);
2069
2070         /* force a PF reset to clean anything leftover */
2071         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2072         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2073                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2074         I40E_WRITE_FLUSH(hw);
2075 }
2076
2077 static void
2078 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2079 {
2080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2082         struct i40e_vsi *vsi = pf->main_vsi;
2083         int status;
2084
2085         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2086                                                      true, NULL, true);
2087         if (status != I40E_SUCCESS)
2088                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2089
2090         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2091                                                         TRUE, NULL);
2092         if (status != I40E_SUCCESS)
2093                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2094
2095 }
2096
2097 static void
2098 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2099 {
2100         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102         struct i40e_vsi *vsi = pf->main_vsi;
2103         int status;
2104
2105         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2106                                                      false, NULL, true);
2107         if (status != I40E_SUCCESS)
2108                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2109
2110         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2111                                                         false, NULL);
2112         if (status != I40E_SUCCESS)
2113                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2114 }
2115
2116 static void
2117 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2118 {
2119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2121         struct i40e_vsi *vsi = pf->main_vsi;
2122         int ret;
2123
2124         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2125         if (ret != I40E_SUCCESS)
2126                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2127 }
2128
2129 static void
2130 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2131 {
2132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct i40e_vsi *vsi = pf->main_vsi;
2135         int ret;
2136
2137         if (dev->data->promiscuous == 1)
2138                 return; /* must remain in all_multicast mode */
2139
2140         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2141                                 vsi->seid, FALSE, NULL);
2142         if (ret != I40E_SUCCESS)
2143                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2144 }
2145
2146 /*
2147  * Set device link up.
2148  */
2149 static int
2150 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2151 {
2152         /* re-apply link speed setting */
2153         return i40e_apply_link_speed(dev);
2154 }
2155
2156 /*
2157  * Set device link down.
2158  */
2159 static int
2160 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2161 {
2162         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2163         uint8_t abilities = 0;
2164         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2165
2166         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2167         return i40e_phy_conf_link(hw, abilities, speed);
2168 }
2169
2170 int
2171 i40e_dev_link_update(struct rte_eth_dev *dev,
2172                      int wait_to_complete)
2173 {
2174 #define CHECK_INTERVAL 100  /* 100ms */
2175 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2176         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         struct i40e_link_status link_status;
2178         struct rte_eth_link link, old;
2179         int status;
2180         unsigned rep_cnt = MAX_REPEAT_TIME;
2181         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2182
2183         memset(&link, 0, sizeof(link));
2184         memset(&old, 0, sizeof(old));
2185         memset(&link_status, 0, sizeof(link_status));
2186         rte_i40e_dev_atomic_read_link_status(dev, &old);
2187
2188         do {
2189                 /* Get link status information from hardware */
2190                 status = i40e_aq_get_link_info(hw, enable_lse,
2191                                                 &link_status, NULL);
2192                 if (status != I40E_SUCCESS) {
2193                         link.link_speed = ETH_SPEED_NUM_100M;
2194                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2195                         PMD_DRV_LOG(ERR, "Failed to get link info");
2196                         goto out;
2197                 }
2198
2199                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2200                 if (!wait_to_complete)
2201                         break;
2202
2203                 rte_delay_ms(CHECK_INTERVAL);
2204         } while (!link.link_status && rep_cnt--);
2205
2206         if (!link.link_status)
2207                 goto out;
2208
2209         /* i40e uses full duplex only */
2210         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2211
2212         /* Parse the link status */
2213         switch (link_status.link_speed) {
2214         case I40E_LINK_SPEED_100MB:
2215                 link.link_speed = ETH_SPEED_NUM_100M;
2216                 break;
2217         case I40E_LINK_SPEED_1GB:
2218                 link.link_speed = ETH_SPEED_NUM_1G;
2219                 break;
2220         case I40E_LINK_SPEED_10GB:
2221                 link.link_speed = ETH_SPEED_NUM_10G;
2222                 break;
2223         case I40E_LINK_SPEED_20GB:
2224                 link.link_speed = ETH_SPEED_NUM_20G;
2225                 break;
2226         case I40E_LINK_SPEED_25GB:
2227                 link.link_speed = ETH_SPEED_NUM_25G;
2228                 break;
2229         case I40E_LINK_SPEED_40GB:
2230                 link.link_speed = ETH_SPEED_NUM_40G;
2231                 break;
2232         default:
2233                 link.link_speed = ETH_SPEED_NUM_100M;
2234                 break;
2235         }
2236
2237         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2238                         ETH_LINK_SPEED_FIXED);
2239
2240 out:
2241         rte_i40e_dev_atomic_write_link_status(dev, &link);
2242         if (link.link_status == old.link_status)
2243                 return -1;
2244
2245         return 0;
2246 }
2247
2248 /* Get all the statistics of a VSI */
2249 void
2250 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2251 {
2252         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2253         struct i40e_eth_stats *nes = &vsi->eth_stats;
2254         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2255         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2256
2257         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2258                             vsi->offset_loaded, &oes->rx_bytes,
2259                             &nes->rx_bytes);
2260         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2261                             vsi->offset_loaded, &oes->rx_unicast,
2262                             &nes->rx_unicast);
2263         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2264                             vsi->offset_loaded, &oes->rx_multicast,
2265                             &nes->rx_multicast);
2266         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2267                             vsi->offset_loaded, &oes->rx_broadcast,
2268                             &nes->rx_broadcast);
2269         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2270                             &oes->rx_discards, &nes->rx_discards);
2271         /* GLV_REPC not supported */
2272         /* GLV_RMPC not supported */
2273         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2274                             &oes->rx_unknown_protocol,
2275                             &nes->rx_unknown_protocol);
2276         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2277                             vsi->offset_loaded, &oes->tx_bytes,
2278                             &nes->tx_bytes);
2279         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2280                             vsi->offset_loaded, &oes->tx_unicast,
2281                             &nes->tx_unicast);
2282         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2283                             vsi->offset_loaded, &oes->tx_multicast,
2284                             &nes->tx_multicast);
2285         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2286                             vsi->offset_loaded,  &oes->tx_broadcast,
2287                             &nes->tx_broadcast);
2288         /* GLV_TDPC not supported */
2289         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2290                             &oes->tx_errors, &nes->tx_errors);
2291         vsi->offset_loaded = true;
2292
2293         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2294                     vsi->vsi_id);
2295         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2296         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2297         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2298         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2299         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2300         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2301                     nes->rx_unknown_protocol);
2302         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2303         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2304         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2305         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2306         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2307         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2308         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2309                     vsi->vsi_id);
2310 }
2311
2312 static void
2313 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2314 {
2315         unsigned int i;
2316         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2317         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2318
2319         /* Get statistics of struct i40e_eth_stats */
2320         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2321                             I40E_GLPRT_GORCL(hw->port),
2322                             pf->offset_loaded, &os->eth.rx_bytes,
2323                             &ns->eth.rx_bytes);
2324         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2325                             I40E_GLPRT_UPRCL(hw->port),
2326                             pf->offset_loaded, &os->eth.rx_unicast,
2327                             &ns->eth.rx_unicast);
2328         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2329                             I40E_GLPRT_MPRCL(hw->port),
2330                             pf->offset_loaded, &os->eth.rx_multicast,
2331                             &ns->eth.rx_multicast);
2332         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2333                             I40E_GLPRT_BPRCL(hw->port),
2334                             pf->offset_loaded, &os->eth.rx_broadcast,
2335                             &ns->eth.rx_broadcast);
2336         /* Workaround: CRC size should not be included in byte statistics,
2337          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2338          */
2339         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2340                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2341
2342         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2343                             pf->offset_loaded, &os->eth.rx_discards,
2344                             &ns->eth.rx_discards);
2345         /* GLPRT_REPC not supported */
2346         /* GLPRT_RMPC not supported */
2347         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2348                             pf->offset_loaded,
2349                             &os->eth.rx_unknown_protocol,
2350                             &ns->eth.rx_unknown_protocol);
2351         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2352                             I40E_GLPRT_GOTCL(hw->port),
2353                             pf->offset_loaded, &os->eth.tx_bytes,
2354                             &ns->eth.tx_bytes);
2355         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2356                             I40E_GLPRT_UPTCL(hw->port),
2357                             pf->offset_loaded, &os->eth.tx_unicast,
2358                             &ns->eth.tx_unicast);
2359         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2360                             I40E_GLPRT_MPTCL(hw->port),
2361                             pf->offset_loaded, &os->eth.tx_multicast,
2362                             &ns->eth.tx_multicast);
2363         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2364                             I40E_GLPRT_BPTCL(hw->port),
2365                             pf->offset_loaded, &os->eth.tx_broadcast,
2366                             &ns->eth.tx_broadcast);
2367         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2368                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2369         /* GLPRT_TEPC not supported */
2370
2371         /* additional port specific stats */
2372         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2373                             pf->offset_loaded, &os->tx_dropped_link_down,
2374                             &ns->tx_dropped_link_down);
2375         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2376                             pf->offset_loaded, &os->crc_errors,
2377                             &ns->crc_errors);
2378         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2379                             pf->offset_loaded, &os->illegal_bytes,
2380                             &ns->illegal_bytes);
2381         /* GLPRT_ERRBC not supported */
2382         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2383                             pf->offset_loaded, &os->mac_local_faults,
2384                             &ns->mac_local_faults);
2385         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2386                             pf->offset_loaded, &os->mac_remote_faults,
2387                             &ns->mac_remote_faults);
2388         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2389                             pf->offset_loaded, &os->rx_length_errors,
2390                             &ns->rx_length_errors);
2391         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2392                             pf->offset_loaded, &os->link_xon_rx,
2393                             &ns->link_xon_rx);
2394         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2395                             pf->offset_loaded, &os->link_xoff_rx,
2396                             &ns->link_xoff_rx);
2397         for (i = 0; i < 8; i++) {
2398                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2399                                     pf->offset_loaded,
2400                                     &os->priority_xon_rx[i],
2401                                     &ns->priority_xon_rx[i]);
2402                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2403                                     pf->offset_loaded,
2404                                     &os->priority_xoff_rx[i],
2405                                     &ns->priority_xoff_rx[i]);
2406         }
2407         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2408                             pf->offset_loaded, &os->link_xon_tx,
2409                             &ns->link_xon_tx);
2410         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2411                             pf->offset_loaded, &os->link_xoff_tx,
2412                             &ns->link_xoff_tx);
2413         for (i = 0; i < 8; i++) {
2414                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2415                                     pf->offset_loaded,
2416                                     &os->priority_xon_tx[i],
2417                                     &ns->priority_xon_tx[i]);
2418                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2419                                     pf->offset_loaded,
2420                                     &os->priority_xoff_tx[i],
2421                                     &ns->priority_xoff_tx[i]);
2422                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2423                                     pf->offset_loaded,
2424                                     &os->priority_xon_2_xoff[i],
2425                                     &ns->priority_xon_2_xoff[i]);
2426         }
2427         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2428                             I40E_GLPRT_PRC64L(hw->port),
2429                             pf->offset_loaded, &os->rx_size_64,
2430                             &ns->rx_size_64);
2431         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2432                             I40E_GLPRT_PRC127L(hw->port),
2433                             pf->offset_loaded, &os->rx_size_127,
2434                             &ns->rx_size_127);
2435         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2436                             I40E_GLPRT_PRC255L(hw->port),
2437                             pf->offset_loaded, &os->rx_size_255,
2438                             &ns->rx_size_255);
2439         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2440                             I40E_GLPRT_PRC511L(hw->port),
2441                             pf->offset_loaded, &os->rx_size_511,
2442                             &ns->rx_size_511);
2443         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2444                             I40E_GLPRT_PRC1023L(hw->port),
2445                             pf->offset_loaded, &os->rx_size_1023,
2446                             &ns->rx_size_1023);
2447         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2448                             I40E_GLPRT_PRC1522L(hw->port),
2449                             pf->offset_loaded, &os->rx_size_1522,
2450                             &ns->rx_size_1522);
2451         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2452                             I40E_GLPRT_PRC9522L(hw->port),
2453                             pf->offset_loaded, &os->rx_size_big,
2454                             &ns->rx_size_big);
2455         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2456                             pf->offset_loaded, &os->rx_undersize,
2457                             &ns->rx_undersize);
2458         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2459                             pf->offset_loaded, &os->rx_fragments,
2460                             &ns->rx_fragments);
2461         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2462                             pf->offset_loaded, &os->rx_oversize,
2463                             &ns->rx_oversize);
2464         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2465                             pf->offset_loaded, &os->rx_jabber,
2466                             &ns->rx_jabber);
2467         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2468                             I40E_GLPRT_PTC64L(hw->port),
2469                             pf->offset_loaded, &os->tx_size_64,
2470                             &ns->tx_size_64);
2471         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2472                             I40E_GLPRT_PTC127L(hw->port),
2473                             pf->offset_loaded, &os->tx_size_127,
2474                             &ns->tx_size_127);
2475         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2476                             I40E_GLPRT_PTC255L(hw->port),
2477                             pf->offset_loaded, &os->tx_size_255,
2478                             &ns->tx_size_255);
2479         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2480                             I40E_GLPRT_PTC511L(hw->port),
2481                             pf->offset_loaded, &os->tx_size_511,
2482                             &ns->tx_size_511);
2483         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2484                             I40E_GLPRT_PTC1023L(hw->port),
2485                             pf->offset_loaded, &os->tx_size_1023,
2486                             &ns->tx_size_1023);
2487         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2488                             I40E_GLPRT_PTC1522L(hw->port),
2489                             pf->offset_loaded, &os->tx_size_1522,
2490                             &ns->tx_size_1522);
2491         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2492                             I40E_GLPRT_PTC9522L(hw->port),
2493                             pf->offset_loaded, &os->tx_size_big,
2494                             &ns->tx_size_big);
2495         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2496                            pf->offset_loaded,
2497                            &os->fd_sb_match, &ns->fd_sb_match);
2498         /* GLPRT_MSPDC not supported */
2499         /* GLPRT_XEC not supported */
2500
2501         pf->offset_loaded = true;
2502
2503         if (pf->main_vsi)
2504                 i40e_update_vsi_stats(pf->main_vsi);
2505 }
2506
2507 /* Get all statistics of a port */
2508 static void
2509 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2510 {
2511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2512         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2514         unsigned i;
2515
2516         /* call read registers - updates values, now write them to struct */
2517         i40e_read_stats_registers(pf, hw);
2518
2519         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2520                         pf->main_vsi->eth_stats.rx_multicast +
2521                         pf->main_vsi->eth_stats.rx_broadcast -
2522                         pf->main_vsi->eth_stats.rx_discards;
2523         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2524                         pf->main_vsi->eth_stats.tx_multicast +
2525                         pf->main_vsi->eth_stats.tx_broadcast;
2526         stats->ibytes   = ns->eth.rx_bytes;
2527         stats->obytes   = ns->eth.tx_bytes;
2528         stats->oerrors  = ns->eth.tx_errors +
2529                         pf->main_vsi->eth_stats.tx_errors;
2530
2531         /* Rx Errors */
2532         stats->imissed  = ns->eth.rx_discards +
2533                         pf->main_vsi->eth_stats.rx_discards;
2534         stats->ierrors  = ns->crc_errors +
2535                         ns->rx_length_errors + ns->rx_undersize +
2536                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2537
2538         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2539         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2540         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2541         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2542         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2543         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2544         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2545                     ns->eth.rx_unknown_protocol);
2546         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2547         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2548         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2549         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2550         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2551         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2552
2553         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2554                     ns->tx_dropped_link_down);
2555         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2556         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2557                     ns->illegal_bytes);
2558         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2559         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2560                     ns->mac_local_faults);
2561         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2562                     ns->mac_remote_faults);
2563         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2564                     ns->rx_length_errors);
2565         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2566         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2567         for (i = 0; i < 8; i++) {
2568                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2569                                 i, ns->priority_xon_rx[i]);
2570                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2571                                 i, ns->priority_xoff_rx[i]);
2572         }
2573         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2574         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2575         for (i = 0; i < 8; i++) {
2576                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2577                                 i, ns->priority_xon_tx[i]);
2578                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2579                                 i, ns->priority_xoff_tx[i]);
2580                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2581                                 i, ns->priority_xon_2_xoff[i]);
2582         }
2583         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2584         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2585         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2586         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2587         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2588         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2589         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2590         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2591         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2592         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2593         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2594         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2595         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2596         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2597         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2598         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2599         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2600         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2601         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2602                         ns->mac_short_packet_dropped);
2603         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2604                     ns->checksum_error);
2605         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2606         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2607 }
2608
2609 /* Reset the statistics */
2610 static void
2611 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2612 {
2613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615
2616         /* Mark PF and VSI stats to update the offset, aka "reset" */
2617         pf->offset_loaded = false;
2618         if (pf->main_vsi)
2619                 pf->main_vsi->offset_loaded = false;
2620
2621         /* read the stats, reading current register values into offset */
2622         i40e_read_stats_registers(pf, hw);
2623 }
2624
2625 static uint32_t
2626 i40e_xstats_calc_num(void)
2627 {
2628         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2629                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2630                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2631 }
2632
2633 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2634                                      struct rte_eth_xstat_name *xstats_names,
2635                                      __rte_unused unsigned limit)
2636 {
2637         unsigned count = 0;
2638         unsigned i, prio;
2639
2640         if (xstats_names == NULL)
2641                 return i40e_xstats_calc_num();
2642
2643         /* Note: limit checked in rte_eth_xstats_names() */
2644
2645         /* Get stats from i40e_eth_stats struct */
2646         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2647                 snprintf(xstats_names[count].name,
2648                          sizeof(xstats_names[count].name),
2649                          "%s", rte_i40e_stats_strings[i].name);
2650                 count++;
2651         }
2652
2653         /* Get individiual stats from i40e_hw_port struct */
2654         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2655                 snprintf(xstats_names[count].name,
2656                         sizeof(xstats_names[count].name),
2657                          "%s", rte_i40e_hw_port_strings[i].name);
2658                 count++;
2659         }
2660
2661         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2662                 for (prio = 0; prio < 8; prio++) {
2663                         snprintf(xstats_names[count].name,
2664                                  sizeof(xstats_names[count].name),
2665                                  "rx_priority%u_%s", prio,
2666                                  rte_i40e_rxq_prio_strings[i].name);
2667                         count++;
2668                 }
2669         }
2670
2671         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2672                 for (prio = 0; prio < 8; prio++) {
2673                         snprintf(xstats_names[count].name,
2674                                  sizeof(xstats_names[count].name),
2675                                  "tx_priority%u_%s", prio,
2676                                  rte_i40e_txq_prio_strings[i].name);
2677                         count++;
2678                 }
2679         }
2680         return count;
2681 }
2682
2683 static int
2684 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2685                     unsigned n)
2686 {
2687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         unsigned i, count, prio;
2690         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2691
2692         count = i40e_xstats_calc_num();
2693         if (n < count)
2694                 return count;
2695
2696         i40e_read_stats_registers(pf, hw);
2697
2698         if (xstats == NULL)
2699                 return 0;
2700
2701         count = 0;
2702
2703         /* Get stats from i40e_eth_stats struct */
2704         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2705                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2706                         rte_i40e_stats_strings[i].offset);
2707                 xstats[count].id = count;
2708                 count++;
2709         }
2710
2711         /* Get individiual stats from i40e_hw_port struct */
2712         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2713                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2714                         rte_i40e_hw_port_strings[i].offset);
2715                 xstats[count].id = count;
2716                 count++;
2717         }
2718
2719         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2720                 for (prio = 0; prio < 8; prio++) {
2721                         xstats[count].value =
2722                                 *(uint64_t *)(((char *)hw_stats) +
2723                                 rte_i40e_rxq_prio_strings[i].offset +
2724                                 (sizeof(uint64_t) * prio));
2725                         xstats[count].id = count;
2726                         count++;
2727                 }
2728         }
2729
2730         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2731                 for (prio = 0; prio < 8; prio++) {
2732                         xstats[count].value =
2733                                 *(uint64_t *)(((char *)hw_stats) +
2734                                 rte_i40e_txq_prio_strings[i].offset +
2735                                 (sizeof(uint64_t) * prio));
2736                         xstats[count].id = count;
2737                         count++;
2738                 }
2739         }
2740
2741         return count;
2742 }
2743
2744 static int
2745 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2746                                  __rte_unused uint16_t queue_id,
2747                                  __rte_unused uint8_t stat_idx,
2748                                  __rte_unused uint8_t is_rx)
2749 {
2750         PMD_INIT_FUNC_TRACE();
2751
2752         return -ENOSYS;
2753 }
2754
2755 static int
2756 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2757 {
2758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759         u32 full_ver;
2760         u8 ver, patch;
2761         u16 build;
2762         int ret;
2763
2764         full_ver = hw->nvm.oem_ver;
2765         ver = (u8)(full_ver >> 24);
2766         build = (u16)((full_ver >> 8) & 0xffff);
2767         patch = (u8)(full_ver & 0xff);
2768
2769         ret = snprintf(fw_version, fw_size,
2770                  "%d.%d%d 0x%08x %d.%d.%d",
2771                  ((hw->nvm.version >> 12) & 0xf),
2772                  ((hw->nvm.version >> 4) & 0xff),
2773                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2774                  ver, build, patch);
2775
2776         ret += 1; /* add the size of '\0' */
2777         if (fw_size < (u32)ret)
2778                 return ret;
2779         else
2780                 return 0;
2781 }
2782
2783 static void
2784 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2785 {
2786         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2787         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788         struct i40e_vsi *vsi = pf->main_vsi;
2789         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2790
2791         dev_info->pci_dev = pci_dev;
2792         dev_info->max_rx_queues = vsi->nb_qps;
2793         dev_info->max_tx_queues = vsi->nb_qps;
2794         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2795         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2796         dev_info->max_mac_addrs = vsi->max_macaddrs;
2797         dev_info->max_vfs = pci_dev->max_vfs;
2798         dev_info->rx_offload_capa =
2799                 DEV_RX_OFFLOAD_VLAN_STRIP |
2800                 DEV_RX_OFFLOAD_QINQ_STRIP |
2801                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2802                 DEV_RX_OFFLOAD_UDP_CKSUM |
2803                 DEV_RX_OFFLOAD_TCP_CKSUM;
2804         dev_info->tx_offload_capa =
2805                 DEV_TX_OFFLOAD_VLAN_INSERT |
2806                 DEV_TX_OFFLOAD_QINQ_INSERT |
2807                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2808                 DEV_TX_OFFLOAD_UDP_CKSUM |
2809                 DEV_TX_OFFLOAD_TCP_CKSUM |
2810                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2811                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2812                 DEV_TX_OFFLOAD_TCP_TSO |
2813                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2814                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2815                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2816                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2817         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2818                                                 sizeof(uint32_t);
2819         dev_info->reta_size = pf->hash_lut_size;
2820         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2821
2822         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2823                 .rx_thresh = {
2824                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2825                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2826                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2827                 },
2828                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2829                 .rx_drop_en = 0,
2830         };
2831
2832         dev_info->default_txconf = (struct rte_eth_txconf) {
2833                 .tx_thresh = {
2834                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2835                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2836                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2837                 },
2838                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2839                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2840                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2841                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2842         };
2843
2844         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2845                 .nb_max = I40E_MAX_RING_DESC,
2846                 .nb_min = I40E_MIN_RING_DESC,
2847                 .nb_align = I40E_ALIGN_RING_DESC,
2848         };
2849
2850         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2851                 .nb_max = I40E_MAX_RING_DESC,
2852                 .nb_min = I40E_MIN_RING_DESC,
2853                 .nb_align = I40E_ALIGN_RING_DESC,
2854                 .nb_seg_max = I40E_TX_MAX_SEG,
2855                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2856         };
2857
2858         if (pf->flags & I40E_FLAG_VMDQ) {
2859                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2860                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2861                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2862                                                 pf->max_nb_vmdq_vsi;
2863                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2864                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2865                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2866         }
2867
2868         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2869                 /* For XL710 */
2870                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2871         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2872                 /* For XXV710 */
2873                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2874         else
2875                 /* For X710 */
2876                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2877 }
2878
2879 static int
2880 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2881 {
2882         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2883         struct i40e_vsi *vsi = pf->main_vsi;
2884         PMD_INIT_FUNC_TRACE();
2885
2886         if (on)
2887                 return i40e_vsi_add_vlan(vsi, vlan_id);
2888         else
2889                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2890 }
2891
2892 static int
2893 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2894                    enum rte_vlan_type vlan_type,
2895                    uint16_t tpid)
2896 {
2897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898         uint64_t reg_r = 0, reg_w = 0;
2899         uint16_t reg_id = 0;
2900         int ret = 0;
2901         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2902
2903         switch (vlan_type) {
2904         case ETH_VLAN_TYPE_OUTER:
2905                 if (qinq)
2906                         reg_id = 2;
2907                 else
2908                         reg_id = 3;
2909                 break;
2910         case ETH_VLAN_TYPE_INNER:
2911                 if (qinq)
2912                         reg_id = 3;
2913                 else {
2914                         ret = -EINVAL;
2915                         PMD_DRV_LOG(ERR,
2916                                 "Unsupported vlan type in single vlan.\n");
2917                         return ret;
2918                 }
2919                 break;
2920         default:
2921                 ret = -EINVAL;
2922                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2923                 return ret;
2924         }
2925         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2926                                           &reg_r, NULL);
2927         if (ret != I40E_SUCCESS) {
2928                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2929                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2930                 ret = -EIO;
2931                 return ret;
2932         }
2933         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2934                     "0x%08"PRIx64"", reg_id, reg_r);
2935
2936         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2937         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2938         if (reg_r == reg_w) {
2939                 ret = 0;
2940                 PMD_DRV_LOG(DEBUG, "No need to write");
2941                 return ret;
2942         }
2943
2944         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2945                                            reg_w, NULL);
2946         if (ret != I40E_SUCCESS) {
2947                 ret = -EIO;
2948                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2949                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2950                 return ret;
2951         }
2952         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2953                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2954
2955         return ret;
2956 }
2957
2958 static void
2959 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2960 {
2961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2962         struct i40e_vsi *vsi = pf->main_vsi;
2963
2964         if (mask & ETH_VLAN_FILTER_MASK) {
2965                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2966                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2967                 else
2968                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2969         }
2970
2971         if (mask & ETH_VLAN_STRIP_MASK) {
2972                 /* Enable or disable VLAN stripping */
2973                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2974                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2975                 else
2976                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2977         }
2978
2979         if (mask & ETH_VLAN_EXTEND_MASK) {
2980                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2981                         i40e_vsi_config_double_vlan(vsi, TRUE);
2982                         /* Set global registers with default ether type value */
2983                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2984                                            ETHER_TYPE_VLAN);
2985                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2986                                            ETHER_TYPE_VLAN);
2987                 }
2988                 else
2989                         i40e_vsi_config_double_vlan(vsi, FALSE);
2990         }
2991 }
2992
2993 static void
2994 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2995                           __rte_unused uint16_t queue,
2996                           __rte_unused int on)
2997 {
2998         PMD_INIT_FUNC_TRACE();
2999 }
3000
3001 static int
3002 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3003 {
3004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3005         struct i40e_vsi *vsi = pf->main_vsi;
3006         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3007         struct i40e_vsi_vlan_pvid_info info;
3008
3009         memset(&info, 0, sizeof(info));
3010         info.on = on;
3011         if (info.on)
3012                 info.config.pvid = pvid;
3013         else {
3014                 info.config.reject.tagged =
3015                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3016                 info.config.reject.untagged =
3017                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3018         }
3019
3020         return i40e_vsi_vlan_pvid_set(vsi, &info);
3021 }
3022
3023 static int
3024 i40e_dev_led_on(struct rte_eth_dev *dev)
3025 {
3026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         uint32_t mode = i40e_led_get(hw);
3028
3029         if (mode == 0)
3030                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3031
3032         return 0;
3033 }
3034
3035 static int
3036 i40e_dev_led_off(struct rte_eth_dev *dev)
3037 {
3038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039         uint32_t mode = i40e_led_get(hw);
3040
3041         if (mode != 0)
3042                 i40e_led_set(hw, 0, false);
3043
3044         return 0;
3045 }
3046
3047 static int
3048 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3049 {
3050         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3051         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3052
3053         fc_conf->pause_time = pf->fc_conf.pause_time;
3054         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3055         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3056
3057          /* Return current mode according to actual setting*/
3058         switch (hw->fc.current_mode) {
3059         case I40E_FC_FULL:
3060                 fc_conf->mode = RTE_FC_FULL;
3061                 break;
3062         case I40E_FC_TX_PAUSE:
3063                 fc_conf->mode = RTE_FC_TX_PAUSE;
3064                 break;
3065         case I40E_FC_RX_PAUSE:
3066                 fc_conf->mode = RTE_FC_RX_PAUSE;
3067                 break;
3068         case I40E_FC_NONE:
3069         default:
3070                 fc_conf->mode = RTE_FC_NONE;
3071         };
3072
3073         return 0;
3074 }
3075
3076 static int
3077 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3078 {
3079         uint32_t mflcn_reg, fctrl_reg, reg;
3080         uint32_t max_high_water;
3081         uint8_t i, aq_failure;
3082         int err;
3083         struct i40e_hw *hw;
3084         struct i40e_pf *pf;
3085         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3086                 [RTE_FC_NONE] = I40E_FC_NONE,
3087                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3088                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3089                 [RTE_FC_FULL] = I40E_FC_FULL
3090         };
3091
3092         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3093
3094         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3095         if ((fc_conf->high_water > max_high_water) ||
3096                         (fc_conf->high_water < fc_conf->low_water)) {
3097                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3098                         "High_water must <= %d.", max_high_water);
3099                 return -EINVAL;
3100         }
3101
3102         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3103         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3104         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3105
3106         pf->fc_conf.pause_time = fc_conf->pause_time;
3107         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3108         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3109
3110         PMD_INIT_FUNC_TRACE();
3111
3112         /* All the link flow control related enable/disable register
3113          * configuration is handle by the F/W
3114          */
3115         err = i40e_set_fc(hw, &aq_failure, true);
3116         if (err < 0)
3117                 return -ENOSYS;
3118
3119         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3120                 /* Configure flow control refresh threshold,
3121                  * the value for stat_tx_pause_refresh_timer[8]
3122                  * is used for global pause operation.
3123                  */
3124
3125                 I40E_WRITE_REG(hw,
3126                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3127                                pf->fc_conf.pause_time);
3128
3129                 /* configure the timer value included in transmitted pause
3130                  * frame,
3131                  * the value for stat_tx_pause_quanta[8] is used for global
3132                  * pause operation
3133                  */
3134                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3135                                pf->fc_conf.pause_time);
3136
3137                 fctrl_reg = I40E_READ_REG(hw,
3138                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3139
3140                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3141                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3142                 else
3143                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3144
3145                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3146                                fctrl_reg);
3147         } else {
3148                 /* Configure pause time (2 TCs per register) */
3149                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3150                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3151                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3152
3153                 /* Configure flow control refresh threshold value */
3154                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3155                                pf->fc_conf.pause_time / 2);
3156
3157                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3158
3159                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3160                  *depending on configuration
3161                  */
3162                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3163                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3164                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3165                 } else {
3166                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3167                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3168                 }
3169
3170                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3171         }
3172
3173         /* config the water marker both based on the packets and bytes */
3174         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3175                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3176                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3177         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3178                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3179                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3180         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3181                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3182                        << I40E_KILOSHIFT);
3183         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3184                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3185                        << I40E_KILOSHIFT);
3186
3187         I40E_WRITE_FLUSH(hw);
3188
3189         return 0;
3190 }
3191
3192 static int
3193 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3194                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3195 {
3196         PMD_INIT_FUNC_TRACE();
3197
3198         return -ENOSYS;
3199 }
3200
3201 /* Add a MAC address, and update filters */
3202 static void
3203 i40e_macaddr_add(struct rte_eth_dev *dev,
3204                  struct ether_addr *mac_addr,
3205                  __rte_unused uint32_t index,
3206                  uint32_t pool)
3207 {
3208         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209         struct i40e_mac_filter_info mac_filter;
3210         struct i40e_vsi *vsi;
3211         int ret;
3212
3213         /* If VMDQ not enabled or configured, return */
3214         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3215                           !pf->nb_cfg_vmdq_vsi)) {
3216                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3217                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3218                         pool);
3219                 return;
3220         }
3221
3222         if (pool > pf->nb_cfg_vmdq_vsi) {
3223                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3224                                 pool, pf->nb_cfg_vmdq_vsi);
3225                 return;
3226         }
3227
3228         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3229         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3230                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3231         else
3232                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3233
3234         if (pool == 0)
3235                 vsi = pf->main_vsi;
3236         else
3237                 vsi = pf->vmdq[pool - 1].vsi;
3238
3239         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3240         if (ret != I40E_SUCCESS) {
3241                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3242                 return;
3243         }
3244 }
3245
3246 /* Remove a MAC address, and update filters */
3247 static void
3248 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3249 {
3250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3251         struct i40e_vsi *vsi;
3252         struct rte_eth_dev_data *data = dev->data;
3253         struct ether_addr *macaddr;
3254         int ret;
3255         uint32_t i;
3256         uint64_t pool_sel;
3257
3258         macaddr = &(data->mac_addrs[index]);
3259
3260         pool_sel = dev->data->mac_pool_sel[index];
3261
3262         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3263                 if (pool_sel & (1ULL << i)) {
3264                         if (i == 0)
3265                                 vsi = pf->main_vsi;
3266                         else {
3267                                 /* No VMDQ pool enabled or configured */
3268                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3269                                         (i > pf->nb_cfg_vmdq_vsi)) {
3270                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3271                                                         "/configured");
3272                                         return;
3273                                 }
3274                                 vsi = pf->vmdq[i - 1].vsi;
3275                         }
3276                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3277
3278                         if (ret) {
3279                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3280                                 return;
3281                         }
3282                 }
3283         }
3284 }
3285
3286 /* Set perfect match or hash match of MAC and VLAN for a VF */
3287 static int
3288 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3289                  struct rte_eth_mac_filter *filter,
3290                  bool add)
3291 {
3292         struct i40e_hw *hw;
3293         struct i40e_mac_filter_info mac_filter;
3294         struct ether_addr old_mac;
3295         struct ether_addr *new_mac;
3296         struct i40e_pf_vf *vf = NULL;
3297         uint16_t vf_id;
3298         int ret;
3299
3300         if (pf == NULL) {
3301                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3302                 return -EINVAL;
3303         }
3304         hw = I40E_PF_TO_HW(pf);
3305
3306         if (filter == NULL) {
3307                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3308                 return -EINVAL;
3309         }
3310
3311         new_mac = &filter->mac_addr;
3312
3313         if (is_zero_ether_addr(new_mac)) {
3314                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3315                 return -EINVAL;
3316         }
3317
3318         vf_id = filter->dst_id;
3319
3320         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3321                 PMD_DRV_LOG(ERR, "Invalid argument.");
3322                 return -EINVAL;
3323         }
3324         vf = &pf->vfs[vf_id];
3325
3326         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3327                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3328                 return -EINVAL;
3329         }
3330
3331         if (add) {
3332                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3333                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3334                                 ETHER_ADDR_LEN);
3335                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3336                                  ETHER_ADDR_LEN);
3337
3338                 mac_filter.filter_type = filter->filter_type;
3339                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3340                 if (ret != I40E_SUCCESS) {
3341                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3342                         return -1;
3343                 }
3344                 ether_addr_copy(new_mac, &pf->dev_addr);
3345         } else {
3346                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3347                                 ETHER_ADDR_LEN);
3348                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3349                 if (ret != I40E_SUCCESS) {
3350                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3351                         return -1;
3352                 }
3353
3354                 /* Clear device address as it has been removed */
3355                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3356                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3357         }
3358
3359         return 0;
3360 }
3361
3362 /* MAC filter handle */
3363 static int
3364 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3365                 void *arg)
3366 {
3367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3368         struct rte_eth_mac_filter *filter;
3369         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3370         int ret = I40E_NOT_SUPPORTED;
3371
3372         filter = (struct rte_eth_mac_filter *)(arg);
3373
3374         switch (filter_op) {
3375         case RTE_ETH_FILTER_NOP:
3376                 ret = I40E_SUCCESS;
3377                 break;
3378         case RTE_ETH_FILTER_ADD:
3379                 i40e_pf_disable_irq0(hw);
3380                 if (filter->is_vf)
3381                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3382                 i40e_pf_enable_irq0(hw);
3383                 break;
3384         case RTE_ETH_FILTER_DELETE:
3385                 i40e_pf_disable_irq0(hw);
3386                 if (filter->is_vf)
3387                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3388                 i40e_pf_enable_irq0(hw);
3389                 break;
3390         default:
3391                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3392                 ret = I40E_ERR_PARAM;
3393                 break;
3394         }
3395
3396         return ret;
3397 }
3398
3399 static int
3400 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3401 {
3402         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3403         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3404         int ret;
3405
3406         if (!lut)
3407                 return -EINVAL;
3408
3409         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3410                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3411                                           lut, lut_size);
3412                 if (ret) {
3413                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3414                         return ret;
3415                 }
3416         } else {
3417                 uint32_t *lut_dw = (uint32_t *)lut;
3418                 uint16_t i, lut_size_dw = lut_size / 4;
3419
3420                 for (i = 0; i < lut_size_dw; i++)
3421                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3422         }
3423
3424         return 0;
3425 }
3426
3427 static int
3428 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3429 {
3430         struct i40e_pf *pf;
3431         struct i40e_hw *hw;
3432         int ret;
3433
3434         if (!vsi || !lut)
3435                 return -EINVAL;
3436
3437         pf = I40E_VSI_TO_PF(vsi);
3438         hw = I40E_VSI_TO_HW(vsi);
3439
3440         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3441                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3442                                           lut, lut_size);
3443                 if (ret) {
3444                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3445                         return ret;
3446                 }
3447         } else {
3448                 uint32_t *lut_dw = (uint32_t *)lut;
3449                 uint16_t i, lut_size_dw = lut_size / 4;
3450
3451                 for (i = 0; i < lut_size_dw; i++)
3452                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3453                 I40E_WRITE_FLUSH(hw);
3454         }
3455
3456         return 0;
3457 }
3458
3459 static int
3460 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3461                          struct rte_eth_rss_reta_entry64 *reta_conf,
3462                          uint16_t reta_size)
3463 {
3464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3465         uint16_t i, lut_size = pf->hash_lut_size;
3466         uint16_t idx, shift;
3467         uint8_t *lut;
3468         int ret;
3469
3470         if (reta_size != lut_size ||
3471                 reta_size > ETH_RSS_RETA_SIZE_512) {
3472                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3473                         "(%d) doesn't match the number hardware can supported "
3474                                         "(%d)\n", reta_size, lut_size);
3475                 return -EINVAL;
3476         }
3477
3478         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3479         if (!lut) {
3480                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3481                 return -ENOMEM;
3482         }
3483         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3484         if (ret)
3485                 goto out;
3486         for (i = 0; i < reta_size; i++) {
3487                 idx = i / RTE_RETA_GROUP_SIZE;
3488                 shift = i % RTE_RETA_GROUP_SIZE;
3489                 if (reta_conf[idx].mask & (1ULL << shift))
3490                         lut[i] = reta_conf[idx].reta[shift];
3491         }
3492         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3493
3494 out:
3495         rte_free(lut);
3496
3497         return ret;
3498 }
3499
3500 static int
3501 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3502                         struct rte_eth_rss_reta_entry64 *reta_conf,
3503                         uint16_t reta_size)
3504 {
3505         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3506         uint16_t i, lut_size = pf->hash_lut_size;
3507         uint16_t idx, shift;
3508         uint8_t *lut;
3509         int ret;
3510
3511         if (reta_size != lut_size ||
3512                 reta_size > ETH_RSS_RETA_SIZE_512) {
3513                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3514                         "(%d) doesn't match the number hardware can supported "
3515                                         "(%d)\n", reta_size, lut_size);
3516                 return -EINVAL;
3517         }
3518
3519         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3520         if (!lut) {
3521                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3522                 return -ENOMEM;
3523         }
3524
3525         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3526         if (ret)
3527                 goto out;
3528         for (i = 0; i < reta_size; i++) {
3529                 idx = i / RTE_RETA_GROUP_SIZE;
3530                 shift = i % RTE_RETA_GROUP_SIZE;
3531                 if (reta_conf[idx].mask & (1ULL << shift))
3532                         reta_conf[idx].reta[shift] = lut[i];
3533         }
3534
3535 out:
3536         rte_free(lut);
3537
3538         return ret;
3539 }
3540
3541 /**
3542  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3543  * @hw:   pointer to the HW structure
3544  * @mem:  pointer to mem struct to fill out
3545  * @size: size of memory requested
3546  * @alignment: what to align the allocation to
3547  **/
3548 enum i40e_status_code
3549 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3550                         struct i40e_dma_mem *mem,
3551                         u64 size,
3552                         u32 alignment)
3553 {
3554         const struct rte_memzone *mz = NULL;
3555         char z_name[RTE_MEMZONE_NAMESIZE];
3556
3557         if (!mem)
3558                 return I40E_ERR_PARAM;
3559
3560         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3561         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3562                                          alignment, RTE_PGSIZE_2M);
3563         if (!mz)
3564                 return I40E_ERR_NO_MEMORY;
3565
3566         mem->size = size;
3567         mem->va = mz->addr;
3568         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3569         mem->zone = (const void *)mz;
3570         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3571                     "%"PRIu64, mz->name, mem->pa);
3572
3573         return I40E_SUCCESS;
3574 }
3575
3576 /**
3577  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3578  * @hw:   pointer to the HW structure
3579  * @mem:  ptr to mem struct to free
3580  **/
3581 enum i40e_status_code
3582 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3583                     struct i40e_dma_mem *mem)
3584 {
3585         if (!mem)
3586                 return I40E_ERR_PARAM;
3587
3588         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3589                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3590                     mem->pa);
3591         rte_memzone_free((const struct rte_memzone *)mem->zone);
3592         mem->zone = NULL;
3593         mem->va = NULL;
3594         mem->pa = (u64)0;
3595
3596         return I40E_SUCCESS;
3597 }
3598
3599 /**
3600  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3601  * @hw:   pointer to the HW structure
3602  * @mem:  pointer to mem struct to fill out
3603  * @size: size of memory requested
3604  **/
3605 enum i40e_status_code
3606 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3607                          struct i40e_virt_mem *mem,
3608                          u32 size)
3609 {
3610         if (!mem)
3611                 return I40E_ERR_PARAM;
3612
3613         mem->size = size;
3614         mem->va = rte_zmalloc("i40e", size, 0);
3615
3616         if (mem->va)
3617                 return I40E_SUCCESS;
3618         else
3619                 return I40E_ERR_NO_MEMORY;
3620 }
3621
3622 /**
3623  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3624  * @hw:   pointer to the HW structure
3625  * @mem:  pointer to mem struct to free
3626  **/
3627 enum i40e_status_code
3628 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3629                      struct i40e_virt_mem *mem)
3630 {
3631         if (!mem)
3632                 return I40E_ERR_PARAM;
3633
3634         rte_free(mem->va);
3635         mem->va = NULL;
3636
3637         return I40E_SUCCESS;
3638 }
3639
3640 void
3641 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3642 {
3643         rte_spinlock_init(&sp->spinlock);
3644 }
3645
3646 void
3647 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3648 {
3649         rte_spinlock_lock(&sp->spinlock);
3650 }
3651
3652 void
3653 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3654 {
3655         rte_spinlock_unlock(&sp->spinlock);
3656 }
3657
3658 void
3659 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3660 {
3661         return;
3662 }
3663
3664 /**
3665  * Get the hardware capabilities, which will be parsed
3666  * and saved into struct i40e_hw.
3667  */
3668 static int
3669 i40e_get_cap(struct i40e_hw *hw)
3670 {
3671         struct i40e_aqc_list_capabilities_element_resp *buf;
3672         uint16_t len, size = 0;
3673         int ret;
3674
3675         /* Calculate a huge enough buff for saving response data temporarily */
3676         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3677                                                 I40E_MAX_CAP_ELE_NUM;
3678         buf = rte_zmalloc("i40e", len, 0);
3679         if (!buf) {
3680                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3681                 return I40E_ERR_NO_MEMORY;
3682         }
3683
3684         /* Get, parse the capabilities and save it to hw */
3685         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3686                         i40e_aqc_opc_list_func_capabilities, NULL);
3687         if (ret != I40E_SUCCESS)
3688                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3689
3690         /* Free the temporary buffer after being used */
3691         rte_free(buf);
3692
3693         return ret;
3694 }
3695
3696 static int
3697 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3698 {
3699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3700         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3701         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3702         uint16_t qp_count = 0, vsi_count = 0;
3703
3704         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3705                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3706                 return -EINVAL;
3707         }
3708         /* Add the parameter init for LFC */
3709         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3710         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3711         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3712
3713         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3714         pf->max_num_vsi = hw->func_caps.num_vsis;
3715         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3716         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3717         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3718
3719         /* FDir queue/VSI allocation */
3720         pf->fdir_qp_offset = 0;
3721         if (hw->func_caps.fd) {
3722                 pf->flags |= I40E_FLAG_FDIR;
3723                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3724         } else {
3725                 pf->fdir_nb_qps = 0;
3726         }
3727         qp_count += pf->fdir_nb_qps;
3728         vsi_count += 1;
3729
3730         /* LAN queue/VSI allocation */
3731         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3732         if (!hw->func_caps.rss) {
3733                 pf->lan_nb_qps = 1;
3734         } else {
3735                 pf->flags |= I40E_FLAG_RSS;
3736                 if (hw->mac.type == I40E_MAC_X722)
3737                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3738                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3739         }
3740         qp_count += pf->lan_nb_qps;
3741         vsi_count += 1;
3742
3743         /* VF queue/VSI allocation */
3744         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3745         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3746                 pf->flags |= I40E_FLAG_SRIOV;
3747                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3748                 pf->vf_num = pci_dev->max_vfs;
3749                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3750                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3751                             pf->vf_nb_qps * pf->vf_num);
3752         } else {
3753                 pf->vf_nb_qps = 0;
3754                 pf->vf_num = 0;
3755         }
3756         qp_count += pf->vf_nb_qps * pf->vf_num;
3757         vsi_count += pf->vf_num;
3758
3759         /* VMDq queue/VSI allocation */
3760         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3761         pf->vmdq_nb_qps = 0;
3762         pf->max_nb_vmdq_vsi = 0;
3763         if (hw->func_caps.vmdq) {
3764                 if (qp_count < hw->func_caps.num_tx_qp &&
3765                         vsi_count < hw->func_caps.num_vsis) {
3766                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3767                                 qp_count) / pf->vmdq_nb_qp_max;
3768
3769                         /* Limit the maximum number of VMDq vsi to the maximum
3770                          * ethdev can support
3771                          */
3772                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3773                                 hw->func_caps.num_vsis - vsi_count);
3774                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3775                                 ETH_64_POOLS);
3776                         if (pf->max_nb_vmdq_vsi) {
3777                                 pf->flags |= I40E_FLAG_VMDQ;
3778                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3779                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3780                                             "per VMDQ VSI, in total %u queues",
3781                                             pf->max_nb_vmdq_vsi,
3782                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3783                                             pf->max_nb_vmdq_vsi);
3784                         } else {
3785                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3786                                             "VMDq");
3787                         }
3788                 } else {
3789                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3790                 }
3791         }
3792         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3793         vsi_count += pf->max_nb_vmdq_vsi;
3794
3795         if (hw->func_caps.dcb)
3796                 pf->flags |= I40E_FLAG_DCB;
3797
3798         if (qp_count > hw->func_caps.num_tx_qp) {
3799                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3800                             "the hardware maximum %u", qp_count,
3801                             hw->func_caps.num_tx_qp);
3802                 return -EINVAL;
3803         }
3804         if (vsi_count > hw->func_caps.num_vsis) {
3805                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3806                             "the hardware maximum %u", vsi_count,
3807                             hw->func_caps.num_vsis);
3808                 return -EINVAL;
3809         }
3810
3811         return 0;
3812 }
3813
3814 static int
3815 i40e_pf_get_switch_config(struct i40e_pf *pf)
3816 {
3817         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3818         struct i40e_aqc_get_switch_config_resp *switch_config;
3819         struct i40e_aqc_switch_config_element_resp *element;
3820         uint16_t start_seid = 0, num_reported;
3821         int ret;
3822
3823         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3824                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3825         if (!switch_config) {
3826                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3827                 return -ENOMEM;
3828         }
3829
3830         /* Get the switch configurations */
3831         ret = i40e_aq_get_switch_config(hw, switch_config,
3832                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3833         if (ret != I40E_SUCCESS) {
3834                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3835                 goto fail;
3836         }
3837         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3838         if (num_reported != 1) { /* The number should be 1 */
3839                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3840                 goto fail;
3841         }
3842
3843         /* Parse the switch configuration elements */
3844         element = &(switch_config->element[0]);
3845         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3846                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3847                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3848         } else
3849                 PMD_DRV_LOG(INFO, "Unknown element type");
3850
3851 fail:
3852         rte_free(switch_config);
3853
3854         return ret;
3855 }
3856
3857 static int
3858 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3859                         uint32_t num)
3860 {
3861         struct pool_entry *entry;
3862
3863         if (pool == NULL || num == 0)
3864                 return -EINVAL;
3865
3866         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3867         if (entry == NULL) {
3868                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3869                 return -ENOMEM;
3870         }
3871
3872         /* queue heap initialize */
3873         pool->num_free = num;
3874         pool->num_alloc = 0;
3875         pool->base = base;
3876         LIST_INIT(&pool->alloc_list);
3877         LIST_INIT(&pool->free_list);
3878
3879         /* Initialize element  */
3880         entry->base = 0;
3881         entry->len = num;
3882
3883         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3884         return 0;
3885 }
3886
3887 static void
3888 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3889 {
3890         struct pool_entry *entry, *next_entry;
3891
3892         if (pool == NULL)
3893                 return;
3894
3895         for (entry = LIST_FIRST(&pool->alloc_list);
3896                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3897                         entry = next_entry) {
3898                 LIST_REMOVE(entry, next);
3899                 rte_free(entry);
3900         }
3901
3902         for (entry = LIST_FIRST(&pool->free_list);
3903                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3904                         entry = next_entry) {
3905                 LIST_REMOVE(entry, next);
3906                 rte_free(entry);
3907         }
3908
3909         pool->num_free = 0;
3910         pool->num_alloc = 0;
3911         pool->base = 0;
3912         LIST_INIT(&pool->alloc_list);
3913         LIST_INIT(&pool->free_list);
3914 }
3915
3916 static int
3917 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3918                        uint32_t base)
3919 {
3920         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3921         uint32_t pool_offset;
3922         int insert;
3923
3924         if (pool == NULL) {
3925                 PMD_DRV_LOG(ERR, "Invalid parameter");
3926                 return -EINVAL;
3927         }
3928
3929         pool_offset = base - pool->base;
3930         /* Lookup in alloc list */
3931         LIST_FOREACH(entry, &pool->alloc_list, next) {
3932                 if (entry->base == pool_offset) {
3933                         valid_entry = entry;
3934                         LIST_REMOVE(entry, next);
3935                         break;
3936                 }
3937         }
3938
3939         /* Not find, return */
3940         if (valid_entry == NULL) {
3941                 PMD_DRV_LOG(ERR, "Failed to find entry");
3942                 return -EINVAL;
3943         }
3944
3945         /**
3946          * Found it, move it to free list  and try to merge.
3947          * In order to make merge easier, always sort it by qbase.
3948          * Find adjacent prev and last entries.
3949          */
3950         prev = next = NULL;
3951         LIST_FOREACH(entry, &pool->free_list, next) {
3952                 if (entry->base > valid_entry->base) {
3953                         next = entry;
3954                         break;
3955                 }
3956                 prev = entry;
3957         }
3958
3959         insert = 0;
3960         /* Try to merge with next one*/
3961         if (next != NULL) {
3962                 /* Merge with next one */
3963                 if (valid_entry->base + valid_entry->len == next->base) {
3964                         next->base = valid_entry->base;
3965                         next->len += valid_entry->len;
3966                         rte_free(valid_entry);
3967                         valid_entry = next;
3968                         insert = 1;
3969                 }
3970         }
3971
3972         if (prev != NULL) {
3973                 /* Merge with previous one */
3974                 if (prev->base + prev->len == valid_entry->base) {
3975                         prev->len += valid_entry->len;
3976                         /* If it merge with next one, remove next node */
3977                         if (insert == 1) {
3978                                 LIST_REMOVE(valid_entry, next);
3979                                 rte_free(valid_entry);
3980                         } else {
3981                                 rte_free(valid_entry);
3982                                 insert = 1;
3983                         }
3984                 }
3985         }
3986
3987         /* Not find any entry to merge, insert */
3988         if (insert == 0) {
3989                 if (prev != NULL)
3990                         LIST_INSERT_AFTER(prev, valid_entry, next);
3991                 else if (next != NULL)
3992                         LIST_INSERT_BEFORE(next, valid_entry, next);
3993                 else /* It's empty list, insert to head */
3994                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3995         }
3996
3997         pool->num_free += valid_entry->len;
3998         pool->num_alloc -= valid_entry->len;
3999
4000         return 0;
4001 }
4002
4003 static int
4004 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4005                        uint16_t num)
4006 {
4007         struct pool_entry *entry, *valid_entry;
4008
4009         if (pool == NULL || num == 0) {
4010                 PMD_DRV_LOG(ERR, "Invalid parameter");
4011                 return -EINVAL;
4012         }
4013
4014         if (pool->num_free < num) {
4015                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4016                             num, pool->num_free);
4017                 return -ENOMEM;
4018         }
4019
4020         valid_entry = NULL;
4021         /* Lookup  in free list and find most fit one */
4022         LIST_FOREACH(entry, &pool->free_list, next) {
4023                 if (entry->len >= num) {
4024                         /* Find best one */
4025                         if (entry->len == num) {
4026                                 valid_entry = entry;
4027                                 break;
4028                         }
4029                         if (valid_entry == NULL || valid_entry->len > entry->len)
4030                                 valid_entry = entry;
4031                 }
4032         }
4033
4034         /* Not find one to satisfy the request, return */
4035         if (valid_entry == NULL) {
4036                 PMD_DRV_LOG(ERR, "No valid entry found");
4037                 return -ENOMEM;
4038         }
4039         /**
4040          * The entry have equal queue number as requested,
4041          * remove it from alloc_list.
4042          */
4043         if (valid_entry->len == num) {
4044                 LIST_REMOVE(valid_entry, next);
4045         } else {
4046                 /**
4047                  * The entry have more numbers than requested,
4048                  * create a new entry for alloc_list and minus its
4049                  * queue base and number in free_list.
4050                  */
4051                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4052                 if (entry == NULL) {
4053                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4054                                     "resource pool");
4055                         return -ENOMEM;
4056                 }
4057                 entry->base = valid_entry->base;
4058                 entry->len = num;
4059                 valid_entry->base += num;
4060                 valid_entry->len -= num;
4061                 valid_entry = entry;
4062         }
4063
4064         /* Insert it into alloc list, not sorted */
4065         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4066
4067         pool->num_free -= valid_entry->len;
4068         pool->num_alloc += valid_entry->len;
4069
4070         return valid_entry->base + pool->base;
4071 }
4072
4073 /**
4074  * bitmap_is_subset - Check whether src2 is subset of src1
4075  **/
4076 static inline int
4077 bitmap_is_subset(uint8_t src1, uint8_t src2)
4078 {
4079         return !((src1 ^ src2) & src2);
4080 }
4081
4082 static enum i40e_status_code
4083 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4084 {
4085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4086
4087         /* If DCB is not supported, only default TC is supported */
4088         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4089                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4090                 return I40E_NOT_SUPPORTED;
4091         }
4092
4093         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4094                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4095                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4096                             enabled_tcmap);
4097                 return I40E_NOT_SUPPORTED;
4098         }
4099         return I40E_SUCCESS;
4100 }
4101
4102 int
4103 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4104                                 struct i40e_vsi_vlan_pvid_info *info)
4105 {
4106         struct i40e_hw *hw;
4107         struct i40e_vsi_context ctxt;
4108         uint8_t vlan_flags = 0;
4109         int ret;
4110
4111         if (vsi == NULL || info == NULL) {
4112                 PMD_DRV_LOG(ERR, "invalid parameters");
4113                 return I40E_ERR_PARAM;
4114         }
4115
4116         if (info->on) {
4117                 vsi->info.pvid = info->config.pvid;
4118                 /**
4119                  * If insert pvid is enabled, only tagged pkts are
4120                  * allowed to be sent out.
4121                  */
4122                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4123                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4124         } else {
4125                 vsi->info.pvid = 0;
4126                 if (info->config.reject.tagged == 0)
4127                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4128
4129                 if (info->config.reject.untagged == 0)
4130                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4131         }
4132         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4133                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4134         vsi->info.port_vlan_flags |= vlan_flags;
4135         vsi->info.valid_sections =
4136                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4137         memset(&ctxt, 0, sizeof(ctxt));
4138         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4139         ctxt.seid = vsi->seid;
4140
4141         hw = I40E_VSI_TO_HW(vsi);
4142         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4143         if (ret != I40E_SUCCESS)
4144                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4145
4146         return ret;
4147 }
4148
4149 static int
4150 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4151 {
4152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4153         int i, ret;
4154         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4155
4156         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4157         if (ret != I40E_SUCCESS)
4158                 return ret;
4159
4160         if (!vsi->seid) {
4161                 PMD_DRV_LOG(ERR, "seid not valid");
4162                 return -EINVAL;
4163         }
4164
4165         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4166         tc_bw_data.tc_valid_bits = enabled_tcmap;
4167         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4168                 tc_bw_data.tc_bw_credits[i] =
4169                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4170
4171         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4172         if (ret != I40E_SUCCESS) {
4173                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4174                 return ret;
4175         }
4176
4177         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4178                                         sizeof(vsi->info.qs_handle));
4179         return I40E_SUCCESS;
4180 }
4181
4182 static enum i40e_status_code
4183 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4184                                  struct i40e_aqc_vsi_properties_data *info,
4185                                  uint8_t enabled_tcmap)
4186 {
4187         enum i40e_status_code ret;
4188         int i, total_tc = 0;
4189         uint16_t qpnum_per_tc, bsf, qp_idx;
4190
4191         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4192         if (ret != I40E_SUCCESS)
4193                 return ret;
4194
4195         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4196                 if (enabled_tcmap & (1 << i))
4197                         total_tc++;
4198         vsi->enabled_tc = enabled_tcmap;
4199
4200         /* Number of queues per enabled TC */
4201         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4202         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4203         bsf = rte_bsf32(qpnum_per_tc);
4204
4205         /* Adjust the queue number to actual queues that can be applied */
4206         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4207                 vsi->nb_qps = qpnum_per_tc * total_tc;
4208
4209         /**
4210          * Configure TC and queue mapping parameters, for enabled TC,
4211          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4212          * default queue will serve it.
4213          */
4214         qp_idx = 0;
4215         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4216                 if (vsi->enabled_tc & (1 << i)) {
4217                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4218                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4219                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4220                         qp_idx += qpnum_per_tc;
4221                 } else
4222                         info->tc_mapping[i] = 0;
4223         }
4224
4225         /* Associate queue number with VSI */
4226         if (vsi->type == I40E_VSI_SRIOV) {
4227                 info->mapping_flags |=
4228                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4229                 for (i = 0; i < vsi->nb_qps; i++)
4230                         info->queue_mapping[i] =
4231                                 rte_cpu_to_le_16(vsi->base_queue + i);
4232         } else {
4233                 info->mapping_flags |=
4234                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4235                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4236         }
4237         info->valid_sections |=
4238                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4239
4240         return I40E_SUCCESS;
4241 }
4242
4243 static int
4244 i40e_veb_release(struct i40e_veb *veb)
4245 {
4246         struct i40e_vsi *vsi;
4247         struct i40e_hw *hw;
4248
4249         if (veb == NULL)
4250                 return -EINVAL;
4251
4252         if (!TAILQ_EMPTY(&veb->head)) {
4253                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4254                 return -EACCES;
4255         }
4256         /* associate_vsi field is NULL for floating VEB */
4257         if (veb->associate_vsi != NULL) {
4258                 vsi = veb->associate_vsi;
4259                 hw = I40E_VSI_TO_HW(vsi);
4260
4261                 vsi->uplink_seid = veb->uplink_seid;
4262                 vsi->veb = NULL;
4263         } else {
4264                 veb->associate_pf->main_vsi->floating_veb = NULL;
4265                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4266         }
4267
4268         i40e_aq_delete_element(hw, veb->seid, NULL);
4269         rte_free(veb);
4270         return I40E_SUCCESS;
4271 }
4272
4273 /* Setup a veb */
4274 static struct i40e_veb *
4275 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4276 {
4277         struct i40e_veb *veb;
4278         int ret;
4279         struct i40e_hw *hw;
4280
4281         if (pf == NULL) {
4282                 PMD_DRV_LOG(ERR,
4283                             "veb setup failed, associated PF shouldn't null");
4284                 return NULL;
4285         }
4286         hw = I40E_PF_TO_HW(pf);
4287
4288         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4289         if (!veb) {
4290                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4291                 goto fail;
4292         }
4293
4294         veb->associate_vsi = vsi;
4295         veb->associate_pf = pf;
4296         TAILQ_INIT(&veb->head);
4297         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4298
4299         /* create floating veb if vsi is NULL */
4300         if (vsi != NULL) {
4301                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4302                                       I40E_DEFAULT_TCMAP, false,
4303                                       &veb->seid, false, NULL);
4304         } else {
4305                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4306                                       true, &veb->seid, false, NULL);
4307         }
4308
4309         if (ret != I40E_SUCCESS) {
4310                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4311                             hw->aq.asq_last_status);
4312                 goto fail;
4313         }
4314
4315         /* get statistics index */
4316         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4317                                 &veb->stats_idx, NULL, NULL, NULL);
4318         if (ret != I40E_SUCCESS) {
4319                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4320                             hw->aq.asq_last_status);
4321                 goto fail;
4322         }
4323         /* Get VEB bandwidth, to be implemented */
4324         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4325         if (vsi)
4326                 vsi->uplink_seid = veb->seid;
4327
4328         return veb;
4329 fail:
4330         rte_free(veb);
4331         return NULL;
4332 }
4333
4334 int
4335 i40e_vsi_release(struct i40e_vsi *vsi)
4336 {
4337         struct i40e_pf *pf;
4338         struct i40e_hw *hw;
4339         struct i40e_vsi_list *vsi_list;
4340         void *temp;
4341         int ret;
4342         struct i40e_mac_filter *f;
4343         uint16_t user_param;
4344
4345         if (!vsi)
4346                 return I40E_SUCCESS;
4347
4348         user_param = vsi->user_param;
4349
4350         pf = I40E_VSI_TO_PF(vsi);
4351         hw = I40E_VSI_TO_HW(vsi);
4352
4353         /* VSI has child to attach, release child first */
4354         if (vsi->veb) {
4355                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4356                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4357                                 return -1;
4358                 }
4359                 i40e_veb_release(vsi->veb);
4360         }
4361
4362         if (vsi->floating_veb) {
4363                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4364                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4365                                 return -1;
4366                 }
4367         }
4368
4369         /* Remove all macvlan filters of the VSI */
4370         i40e_vsi_remove_all_macvlan_filter(vsi);
4371         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4372                 rte_free(f);
4373
4374         if (vsi->type != I40E_VSI_MAIN &&
4375             ((vsi->type != I40E_VSI_SRIOV) ||
4376             !pf->floating_veb_list[user_param])) {
4377                 /* Remove vsi from parent's sibling list */
4378                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4379                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4380                         return I40E_ERR_PARAM;
4381                 }
4382                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4383                                 &vsi->sib_vsi_list, list);
4384
4385                 /* Remove all switch element of the VSI */
4386                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4387                 if (ret != I40E_SUCCESS)
4388                         PMD_DRV_LOG(ERR, "Failed to delete element");
4389         }
4390
4391         if ((vsi->type == I40E_VSI_SRIOV) &&
4392             pf->floating_veb_list[user_param]) {
4393                 /* Remove vsi from parent's sibling list */
4394                 if (vsi->parent_vsi == NULL ||
4395                     vsi->parent_vsi->floating_veb == NULL) {
4396                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4397                         return I40E_ERR_PARAM;
4398                 }
4399                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4400                              &vsi->sib_vsi_list, list);
4401
4402                 /* Remove all switch element of the VSI */
4403                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4404                 if (ret != I40E_SUCCESS)
4405                         PMD_DRV_LOG(ERR, "Failed to delete element");
4406         }
4407
4408         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4409
4410         if (vsi->type != I40E_VSI_SRIOV)
4411                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4412         rte_free(vsi);
4413
4414         return I40E_SUCCESS;
4415 }
4416
4417 static int
4418 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4419 {
4420         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4421         struct i40e_aqc_remove_macvlan_element_data def_filter;
4422         struct i40e_mac_filter_info filter;
4423         int ret;
4424
4425         if (vsi->type != I40E_VSI_MAIN)
4426                 return I40E_ERR_CONFIG;
4427         memset(&def_filter, 0, sizeof(def_filter));
4428         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4429                                         ETH_ADDR_LEN);
4430         def_filter.vlan_tag = 0;
4431         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4432                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4433         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4434         if (ret != I40E_SUCCESS) {
4435                 struct i40e_mac_filter *f;
4436                 struct ether_addr *mac;
4437
4438                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4439                             "macvlan filter");
4440                 /* It needs to add the permanent mac into mac list */
4441                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4442                 if (f == NULL) {
4443                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4444                         return I40E_ERR_NO_MEMORY;
4445                 }
4446                 mac = &f->mac_info.mac_addr;
4447                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4448                                 ETH_ADDR_LEN);
4449                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4450                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4451                 vsi->mac_num++;
4452
4453                 return ret;
4454         }
4455         (void)rte_memcpy(&filter.mac_addr,
4456                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4457         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4458         return i40e_vsi_add_mac(vsi, &filter);
4459 }
4460
4461 /*
4462  * i40e_vsi_get_bw_config - Query VSI BW Information
4463  * @vsi: the VSI to be queried
4464  *
4465  * Returns 0 on success, negative value on failure
4466  */
4467 static enum i40e_status_code
4468 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4469 {
4470         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4471         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4472         struct i40e_hw *hw = &vsi->adapter->hw;
4473         i40e_status ret;
4474         int i;
4475         uint32_t bw_max;
4476
4477         memset(&bw_config, 0, sizeof(bw_config));
4478         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4479         if (ret != I40E_SUCCESS) {
4480                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4481                             hw->aq.asq_last_status);
4482                 return ret;
4483         }
4484
4485         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4486         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4487                                         &ets_sla_config, NULL);
4488         if (ret != I40E_SUCCESS) {
4489                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4490                             "configuration %u", hw->aq.asq_last_status);
4491                 return ret;
4492         }
4493
4494         /* store and print out BW info */
4495         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4496         vsi->bw_info.bw_max = bw_config.max_bw;
4497         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4498         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4499         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4500                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4501                      I40E_16_BIT_WIDTH);
4502         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4503                 vsi->bw_info.bw_ets_share_credits[i] =
4504                                 ets_sla_config.share_credits[i];
4505                 vsi->bw_info.bw_ets_credits[i] =
4506                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4507                 /* 4 bits per TC, 4th bit is reserved */
4508                 vsi->bw_info.bw_ets_max[i] =
4509                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4510                                   RTE_LEN2MASK(3, uint8_t));
4511                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4512                             vsi->bw_info.bw_ets_share_credits[i]);
4513                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4514                             vsi->bw_info.bw_ets_credits[i]);
4515                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4516                             vsi->bw_info.bw_ets_max[i]);
4517         }
4518
4519         return I40E_SUCCESS;
4520 }
4521
4522 /* i40e_enable_pf_lb
4523  * @pf: pointer to the pf structure
4524  *
4525  * allow loopback on pf
4526  */
4527 static inline void
4528 i40e_enable_pf_lb(struct i40e_pf *pf)
4529 {
4530         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4531         struct i40e_vsi_context ctxt;
4532         int ret;
4533
4534         /* Use the FW API if FW >= v5.0 */
4535         if (hw->aq.fw_maj_ver < 5) {
4536                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4537                 return;
4538         }
4539
4540         memset(&ctxt, 0, sizeof(ctxt));
4541         ctxt.seid = pf->main_vsi_seid;
4542         ctxt.pf_num = hw->pf_id;
4543         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4544         if (ret) {
4545                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4546                             ret, hw->aq.asq_last_status);
4547                 return;
4548         }
4549         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4550         ctxt.info.valid_sections =
4551                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4552         ctxt.info.switch_id |=
4553                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4554
4555         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4556         if (ret)
4557                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4558                             hw->aq.asq_last_status);
4559 }
4560
4561 /* Setup a VSI */
4562 struct i40e_vsi *
4563 i40e_vsi_setup(struct i40e_pf *pf,
4564                enum i40e_vsi_type type,
4565                struct i40e_vsi *uplink_vsi,
4566                uint16_t user_param)
4567 {
4568         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4569         struct i40e_vsi *vsi;
4570         struct i40e_mac_filter_info filter;
4571         int ret;
4572         struct i40e_vsi_context ctxt;
4573         struct ether_addr broadcast =
4574                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4575
4576         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4577             uplink_vsi == NULL) {
4578                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4579                             "VSI link shouldn't be NULL");
4580                 return NULL;
4581         }
4582
4583         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4584                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4585                             "uplink VSI should be NULL");
4586                 return NULL;
4587         }
4588
4589         /* two situations
4590          * 1.type is not MAIN and uplink vsi is not NULL
4591          * If uplink vsi didn't setup VEB, create one first under veb field
4592          * 2.type is SRIOV and the uplink is NULL
4593          * If floating VEB is NULL, create one veb under floating veb field
4594          */
4595
4596         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4597             uplink_vsi->veb == NULL) {
4598                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4599
4600                 if (uplink_vsi->veb == NULL) {
4601                         PMD_DRV_LOG(ERR, "VEB setup failed");
4602                         return NULL;
4603                 }
4604                 /* set ALLOWLOOPBACk on pf, when veb is created */
4605                 i40e_enable_pf_lb(pf);
4606         }
4607
4608         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4609             pf->main_vsi->floating_veb == NULL) {
4610                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4611
4612                 if (pf->main_vsi->floating_veb == NULL) {
4613                         PMD_DRV_LOG(ERR, "VEB setup failed");
4614                         return NULL;
4615                 }
4616         }
4617
4618         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4619         if (!vsi) {
4620                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4621                 return NULL;
4622         }
4623         TAILQ_INIT(&vsi->mac_list);
4624         vsi->type = type;
4625         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4626         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4627         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4628         vsi->user_param = user_param;
4629         /* Allocate queues */
4630         switch (vsi->type) {
4631         case I40E_VSI_MAIN  :
4632                 vsi->nb_qps = pf->lan_nb_qps;
4633                 break;
4634         case I40E_VSI_SRIOV :
4635                 vsi->nb_qps = pf->vf_nb_qps;
4636                 break;
4637         case I40E_VSI_VMDQ2:
4638                 vsi->nb_qps = pf->vmdq_nb_qps;
4639                 break;
4640         case I40E_VSI_FDIR:
4641                 vsi->nb_qps = pf->fdir_nb_qps;
4642                 break;
4643         default:
4644                 goto fail_mem;
4645         }
4646         /*
4647          * The filter status descriptor is reported in rx queue 0,
4648          * while the tx queue for fdir filter programming has no
4649          * such constraints, can be non-zero queues.
4650          * To simplify it, choose FDIR vsi use queue 0 pair.
4651          * To make sure it will use queue 0 pair, queue allocation
4652          * need be done before this function is called
4653          */
4654         if (type != I40E_VSI_FDIR) {
4655                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4656                         if (ret < 0) {
4657                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4658                                                 vsi->seid, ret);
4659                                 goto fail_mem;
4660                         }
4661                         vsi->base_queue = ret;
4662         } else
4663                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4664
4665         /* VF has MSIX interrupt in VF range, don't allocate here */
4666         if (type == I40E_VSI_MAIN) {
4667                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4668                                           RTE_MIN(vsi->nb_qps,
4669                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4670                 if (ret < 0) {
4671                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4672                                     vsi->seid, ret);
4673                         goto fail_queue_alloc;
4674                 }
4675                 vsi->msix_intr = ret;
4676                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4677         } else if (type != I40E_VSI_SRIOV) {
4678                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4679                 if (ret < 0) {
4680                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4681                         goto fail_queue_alloc;
4682                 }
4683                 vsi->msix_intr = ret;
4684                 vsi->nb_msix = 1;
4685         } else {
4686                 vsi->msix_intr = 0;
4687                 vsi->nb_msix = 0;
4688         }
4689
4690         /* Add VSI */
4691         if (type == I40E_VSI_MAIN) {
4692                 /* For main VSI, no need to add since it's default one */
4693                 vsi->uplink_seid = pf->mac_seid;
4694                 vsi->seid = pf->main_vsi_seid;
4695                 /* Bind queues with specific MSIX interrupt */
4696                 /**
4697                  * Needs 2 interrupt at least, one for misc cause which will
4698                  * enabled from OS side, Another for queues binding the
4699                  * interrupt from device side only.
4700                  */
4701
4702                 /* Get default VSI parameters from hardware */
4703                 memset(&ctxt, 0, sizeof(ctxt));
4704                 ctxt.seid = vsi->seid;
4705                 ctxt.pf_num = hw->pf_id;
4706                 ctxt.uplink_seid = vsi->uplink_seid;
4707                 ctxt.vf_num = 0;
4708                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4709                 if (ret != I40E_SUCCESS) {
4710                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4711                         goto fail_msix_alloc;
4712                 }
4713                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4714                         sizeof(struct i40e_aqc_vsi_properties_data));
4715                 vsi->vsi_id = ctxt.vsi_number;
4716                 vsi->info.valid_sections = 0;
4717
4718                 /* Configure tc, enabled TC0 only */
4719                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4720                         I40E_SUCCESS) {
4721                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4722                         goto fail_msix_alloc;
4723                 }
4724
4725                 /* TC, queue mapping */
4726                 memset(&ctxt, 0, sizeof(ctxt));
4727                 vsi->info.valid_sections |=
4728                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4729                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4730                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4731                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4732                         sizeof(struct i40e_aqc_vsi_properties_data));
4733                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4734                                                 I40E_DEFAULT_TCMAP);
4735                 if (ret != I40E_SUCCESS) {
4736                         PMD_DRV_LOG(ERR, "Failed to configure "
4737                                     "TC queue mapping");
4738                         goto fail_msix_alloc;
4739                 }
4740                 ctxt.seid = vsi->seid;
4741                 ctxt.pf_num = hw->pf_id;
4742                 ctxt.uplink_seid = vsi->uplink_seid;
4743                 ctxt.vf_num = 0;
4744
4745                 /* Update VSI parameters */
4746                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4747                 if (ret != I40E_SUCCESS) {
4748                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4749                         goto fail_msix_alloc;
4750                 }
4751
4752                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4753                                                 sizeof(vsi->info.tc_mapping));
4754                 (void)rte_memcpy(&vsi->info.queue_mapping,
4755                                 &ctxt.info.queue_mapping,
4756                         sizeof(vsi->info.queue_mapping));
4757                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4758                 vsi->info.valid_sections = 0;
4759
4760                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4761                                 ETH_ADDR_LEN);
4762
4763                 /**
4764                  * Updating default filter settings are necessary to prevent
4765                  * reception of tagged packets.
4766                  * Some old firmware configurations load a default macvlan
4767                  * filter which accepts both tagged and untagged packets.
4768                  * The updating is to use a normal filter instead if needed.
4769                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4770                  * The firmware with correct configurations load the default
4771                  * macvlan filter which is expected and cannot be removed.
4772                  */
4773                 i40e_update_default_filter_setting(vsi);
4774                 i40e_config_qinq(hw, vsi);
4775         } else if (type == I40E_VSI_SRIOV) {
4776                 memset(&ctxt, 0, sizeof(ctxt));
4777                 /**
4778                  * For other VSI, the uplink_seid equals to uplink VSI's
4779                  * uplink_seid since they share same VEB
4780                  */
4781                 if (uplink_vsi == NULL)
4782                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4783                 else
4784                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4785                 ctxt.pf_num = hw->pf_id;
4786                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4787                 ctxt.uplink_seid = vsi->uplink_seid;
4788                 ctxt.connection_type = 0x1;
4789                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4790
4791                 /* Use the VEB configuration if FW >= v5.0 */
4792                 if (hw->aq.fw_maj_ver >= 5) {
4793                         /* Configure switch ID */
4794                         ctxt.info.valid_sections |=
4795                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4796                         ctxt.info.switch_id =
4797                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4798                 }
4799
4800                 /* Configure port/vlan */
4801                 ctxt.info.valid_sections |=
4802                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4803                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4804                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4805                                                 I40E_DEFAULT_TCMAP);
4806                 if (ret != I40E_SUCCESS) {
4807                         PMD_DRV_LOG(ERR, "Failed to configure "
4808                                     "TC queue mapping");
4809                         goto fail_msix_alloc;
4810                 }
4811                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4812                 ctxt.info.valid_sections |=
4813                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4814                 /**
4815                  * Since VSI is not created yet, only configure parameter,
4816                  * will add vsi below.
4817                  */
4818
4819                 i40e_config_qinq(hw, vsi);
4820         } else if (type == I40E_VSI_VMDQ2) {
4821                 memset(&ctxt, 0, sizeof(ctxt));
4822                 /*
4823                  * For other VSI, the uplink_seid equals to uplink VSI's
4824                  * uplink_seid since they share same VEB
4825                  */
4826                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4827                 ctxt.pf_num = hw->pf_id;
4828                 ctxt.vf_num = 0;
4829                 ctxt.uplink_seid = vsi->uplink_seid;
4830                 ctxt.connection_type = 0x1;
4831                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4832
4833                 ctxt.info.valid_sections |=
4834                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4835                 /* user_param carries flag to enable loop back */
4836                 if (user_param) {
4837                         ctxt.info.switch_id =
4838                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4839                         ctxt.info.switch_id |=
4840                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4841                 }
4842
4843                 /* Configure port/vlan */
4844                 ctxt.info.valid_sections |=
4845                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4846                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4847                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4848                                                 I40E_DEFAULT_TCMAP);
4849                 if (ret != I40E_SUCCESS) {
4850                         PMD_DRV_LOG(ERR, "Failed to configure "
4851                                         "TC queue mapping");
4852                         goto fail_msix_alloc;
4853                 }
4854                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4855                 ctxt.info.valid_sections |=
4856                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4857         } else if (type == I40E_VSI_FDIR) {
4858                 memset(&ctxt, 0, sizeof(ctxt));
4859                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4860                 ctxt.pf_num = hw->pf_id;
4861                 ctxt.vf_num = 0;
4862                 ctxt.uplink_seid = vsi->uplink_seid;
4863                 ctxt.connection_type = 0x1;     /* regular data port */
4864                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4865                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4866                                                 I40E_DEFAULT_TCMAP);
4867                 if (ret != I40E_SUCCESS) {
4868                         PMD_DRV_LOG(ERR, "Failed to configure "
4869                                         "TC queue mapping.");
4870                         goto fail_msix_alloc;
4871                 }
4872                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4873                 ctxt.info.valid_sections |=
4874                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4875         } else {
4876                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4877                 goto fail_msix_alloc;
4878         }
4879
4880         if (vsi->type != I40E_VSI_MAIN) {
4881                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4882                 if (ret != I40E_SUCCESS) {
4883                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4884                                     hw->aq.asq_last_status);
4885                         goto fail_msix_alloc;
4886                 }
4887                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4888                 vsi->info.valid_sections = 0;
4889                 vsi->seid = ctxt.seid;
4890                 vsi->vsi_id = ctxt.vsi_number;
4891                 vsi->sib_vsi_list.vsi = vsi;
4892                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4893                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4894                                           &vsi->sib_vsi_list, list);
4895                 } else {
4896                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4897                                           &vsi->sib_vsi_list, list);
4898                 }
4899         }
4900
4901         /* MAC/VLAN configuration */
4902         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4903         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4904
4905         ret = i40e_vsi_add_mac(vsi, &filter);
4906         if (ret != I40E_SUCCESS) {
4907                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4908                 goto fail_msix_alloc;
4909         }
4910
4911         /* Get VSI BW information */
4912         i40e_vsi_get_bw_config(vsi);
4913         return vsi;
4914 fail_msix_alloc:
4915         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4916 fail_queue_alloc:
4917         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4918 fail_mem:
4919         rte_free(vsi);
4920         return NULL;
4921 }
4922
4923 /* Configure vlan filter on or off */
4924 int
4925 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4926 {
4927         int i, num;
4928         struct i40e_mac_filter *f;
4929         void *temp;
4930         struct i40e_mac_filter_info *mac_filter;
4931         enum rte_mac_filter_type desired_filter;
4932         int ret = I40E_SUCCESS;
4933
4934         if (on) {
4935                 /* Filter to match MAC and VLAN */
4936                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4937         } else {
4938                 /* Filter to match only MAC */
4939                 desired_filter = RTE_MAC_PERFECT_MATCH;
4940         }
4941
4942         num = vsi->mac_num;
4943
4944         mac_filter = rte_zmalloc("mac_filter_info_data",
4945                                  num * sizeof(*mac_filter), 0);
4946         if (mac_filter == NULL) {
4947                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4948                 return I40E_ERR_NO_MEMORY;
4949         }
4950
4951         i = 0;
4952
4953         /* Remove all existing mac */
4954         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4955                 mac_filter[i] = f->mac_info;
4956                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4957                 if (ret) {
4958                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4959                                     on ? "enable" : "disable");
4960                         goto DONE;
4961                 }
4962                 i++;
4963         }
4964
4965         /* Override with new filter */
4966         for (i = 0; i < num; i++) {
4967                 mac_filter[i].filter_type = desired_filter;
4968                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4969                 if (ret) {
4970                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4971                                     on ? "enable" : "disable");
4972                         goto DONE;
4973                 }
4974         }
4975
4976 DONE:
4977         rte_free(mac_filter);
4978         return ret;
4979 }
4980
4981 /* Configure vlan stripping on or off */
4982 int
4983 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4984 {
4985         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4986         struct i40e_vsi_context ctxt;
4987         uint8_t vlan_flags;
4988         int ret = I40E_SUCCESS;
4989
4990         /* Check if it has been already on or off */
4991         if (vsi->info.valid_sections &
4992                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4993                 if (on) {
4994                         if ((vsi->info.port_vlan_flags &
4995                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4996                                 return 0; /* already on */
4997                 } else {
4998                         if ((vsi->info.port_vlan_flags &
4999                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5000                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5001                                 return 0; /* already off */
5002                 }
5003         }
5004
5005         if (on)
5006                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5007         else
5008                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5009         vsi->info.valid_sections =
5010                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5011         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5012         vsi->info.port_vlan_flags |= vlan_flags;
5013         ctxt.seid = vsi->seid;
5014         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5015         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5016         if (ret)
5017                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5018                             on ? "enable" : "disable");
5019
5020         return ret;
5021 }
5022
5023 static int
5024 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5025 {
5026         struct rte_eth_dev_data *data = dev->data;
5027         int ret;
5028         int mask = 0;
5029
5030         /* Apply vlan offload setting */
5031         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5032         i40e_vlan_offload_set(dev, mask);
5033
5034         /* Apply double-vlan setting, not implemented yet */
5035
5036         /* Apply pvid setting */
5037         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5038                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5039         if (ret)
5040                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5041
5042         return ret;
5043 }
5044
5045 static int
5046 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5047 {
5048         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5049
5050         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5051 }
5052
5053 static int
5054 i40e_update_flow_control(struct i40e_hw *hw)
5055 {
5056 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5057         struct i40e_link_status link_status;
5058         uint32_t rxfc = 0, txfc = 0, reg;
5059         uint8_t an_info;
5060         int ret;
5061
5062         memset(&link_status, 0, sizeof(link_status));
5063         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5064         if (ret != I40E_SUCCESS) {
5065                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5066                 goto write_reg; /* Disable flow control */
5067         }
5068
5069         an_info = hw->phy.link_info.an_info;
5070         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5071                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5072                 ret = I40E_ERR_NOT_READY;
5073                 goto write_reg; /* Disable flow control */
5074         }
5075         /**
5076          * If link auto negotiation is enabled, flow control needs to
5077          * be configured according to it
5078          */
5079         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5080         case I40E_LINK_PAUSE_RXTX:
5081                 rxfc = 1;
5082                 txfc = 1;
5083                 hw->fc.current_mode = I40E_FC_FULL;
5084                 break;
5085         case I40E_AQ_LINK_PAUSE_RX:
5086                 rxfc = 1;
5087                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5088                 break;
5089         case I40E_AQ_LINK_PAUSE_TX:
5090                 txfc = 1;
5091                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5092                 break;
5093         default:
5094                 hw->fc.current_mode = I40E_FC_NONE;
5095                 break;
5096         }
5097
5098 write_reg:
5099         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5100                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5101         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5102         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5103         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5104         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5105
5106         return ret;
5107 }
5108
5109 /* PF setup */
5110 static int
5111 i40e_pf_setup(struct i40e_pf *pf)
5112 {
5113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5114         struct i40e_filter_control_settings settings;
5115         struct i40e_vsi *vsi;
5116         int ret;
5117
5118         /* Clear all stats counters */
5119         pf->offset_loaded = FALSE;
5120         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5121         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5122
5123         ret = i40e_pf_get_switch_config(pf);
5124         if (ret != I40E_SUCCESS) {
5125                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5126                 return ret;
5127         }
5128         if (pf->flags & I40E_FLAG_FDIR) {
5129                 /* make queue allocated first, let FDIR use queue pair 0*/
5130                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5131                 if (ret != I40E_FDIR_QUEUE_ID) {
5132                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5133                                     " ret =%d", ret);
5134                         pf->flags &= ~I40E_FLAG_FDIR;
5135                 }
5136         }
5137         /*  main VSI setup */
5138         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5139         if (!vsi) {
5140                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5141                 return I40E_ERR_NOT_READY;
5142         }
5143         pf->main_vsi = vsi;
5144
5145         /* Configure filter control */
5146         memset(&settings, 0, sizeof(settings));
5147         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5148                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5149         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5150                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5151         else {
5152                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5153                                                 hw->func_caps.rss_table_size);
5154                 return I40E_ERR_PARAM;
5155         }
5156         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5157                         "size: %u\n", hw->func_caps.rss_table_size);
5158         pf->hash_lut_size = hw->func_caps.rss_table_size;
5159
5160         /* Enable ethtype and macvlan filters */
5161         settings.enable_ethtype = TRUE;
5162         settings.enable_macvlan = TRUE;
5163         ret = i40e_set_filter_control(hw, &settings);
5164         if (ret)
5165                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5166                                                                 ret);
5167
5168         /* Update flow control according to the auto negotiation */
5169         i40e_update_flow_control(hw);
5170
5171         return I40E_SUCCESS;
5172 }
5173
5174 int
5175 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5176 {
5177         uint32_t reg;
5178         uint16_t j;
5179
5180         /**
5181          * Set or clear TX Queue Disable flags,
5182          * which is required by hardware.
5183          */
5184         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5185         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5186
5187         /* Wait until the request is finished */
5188         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5189                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5190                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5191                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5192                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5193                                                         & 0x1))) {
5194                         break;
5195                 }
5196         }
5197         if (on) {
5198                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5199                         return I40E_SUCCESS; /* already on, skip next steps */
5200
5201                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5202                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5203         } else {
5204                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5205                         return I40E_SUCCESS; /* already off, skip next steps */
5206                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5207         }
5208         /* Write the register */
5209         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5210         /* Check the result */
5211         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5212                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5213                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5214                 if (on) {
5215                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5216                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5217                                 break;
5218                 } else {
5219                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5220                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5221                                 break;
5222                 }
5223         }
5224         /* Check if it is timeout */
5225         if (j >= I40E_CHK_Q_ENA_COUNT) {
5226                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5227                             (on ? "enable" : "disable"), q_idx);
5228                 return I40E_ERR_TIMEOUT;
5229         }
5230
5231         return I40E_SUCCESS;
5232 }
5233
5234 /* Swith on or off the tx queues */
5235 static int
5236 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5237 {
5238         struct rte_eth_dev_data *dev_data = pf->dev_data;
5239         struct i40e_tx_queue *txq;
5240         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5241         uint16_t i;
5242         int ret;
5243
5244         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5245                 txq = dev_data->tx_queues[i];
5246                 /* Don't operate the queue if not configured or
5247                  * if starting only per queue */
5248                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5249                         continue;
5250                 if (on)
5251                         ret = i40e_dev_tx_queue_start(dev, i);
5252                 else
5253                         ret = i40e_dev_tx_queue_stop(dev, i);
5254                 if ( ret != I40E_SUCCESS)
5255                         return ret;
5256         }
5257
5258         return I40E_SUCCESS;
5259 }
5260
5261 int
5262 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5263 {
5264         uint32_t reg;
5265         uint16_t j;
5266
5267         /* Wait until the request is finished */
5268         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5269                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5270                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5271                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5272                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5273                         break;
5274         }
5275
5276         if (on) {
5277                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5278                         return I40E_SUCCESS; /* Already on, skip next steps */
5279                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5280         } else {
5281                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5282                         return I40E_SUCCESS; /* Already off, skip next steps */
5283                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5284         }
5285
5286         /* Write the register */
5287         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5288         /* Check the result */
5289         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5290                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5291                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5292                 if (on) {
5293                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5294                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5295                                 break;
5296                 } else {
5297                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5298                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5299                                 break;
5300                 }
5301         }
5302
5303         /* Check if it is timeout */
5304         if (j >= I40E_CHK_Q_ENA_COUNT) {
5305                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5306                             (on ? "enable" : "disable"), q_idx);
5307                 return I40E_ERR_TIMEOUT;
5308         }
5309
5310         return I40E_SUCCESS;
5311 }
5312 /* Switch on or off the rx queues */
5313 static int
5314 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5315 {
5316         struct rte_eth_dev_data *dev_data = pf->dev_data;
5317         struct i40e_rx_queue *rxq;
5318         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5319         uint16_t i;
5320         int ret;
5321
5322         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5323                 rxq = dev_data->rx_queues[i];
5324                 /* Don't operate the queue if not configured or
5325                  * if starting only per queue */
5326                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5327                         continue;
5328                 if (on)
5329                         ret = i40e_dev_rx_queue_start(dev, i);
5330                 else
5331                         ret = i40e_dev_rx_queue_stop(dev, i);
5332                 if (ret != I40E_SUCCESS)
5333                         return ret;
5334         }
5335
5336         return I40E_SUCCESS;
5337 }
5338
5339 /* Switch on or off all the rx/tx queues */
5340 int
5341 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5342 {
5343         int ret;
5344
5345         if (on) {
5346                 /* enable rx queues before enabling tx queues */
5347                 ret = i40e_dev_switch_rx_queues(pf, on);
5348                 if (ret) {
5349                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5350                         return ret;
5351                 }
5352                 ret = i40e_dev_switch_tx_queues(pf, on);
5353         } else {
5354                 /* Stop tx queues before stopping rx queues */
5355                 ret = i40e_dev_switch_tx_queues(pf, on);
5356                 if (ret) {
5357                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5358                         return ret;
5359                 }
5360                 ret = i40e_dev_switch_rx_queues(pf, on);
5361         }
5362
5363         return ret;
5364 }
5365
5366 /* Initialize VSI for TX */
5367 static int
5368 i40e_dev_tx_init(struct i40e_pf *pf)
5369 {
5370         struct rte_eth_dev_data *data = pf->dev_data;
5371         uint16_t i;
5372         uint32_t ret = I40E_SUCCESS;
5373         struct i40e_tx_queue *txq;
5374
5375         for (i = 0; i < data->nb_tx_queues; i++) {
5376                 txq = data->tx_queues[i];
5377                 if (!txq || !txq->q_set)
5378                         continue;
5379                 ret = i40e_tx_queue_init(txq);
5380                 if (ret != I40E_SUCCESS)
5381                         break;
5382         }
5383         if (ret == I40E_SUCCESS)
5384                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5385                                      ->eth_dev);
5386
5387         return ret;
5388 }
5389
5390 /* Initialize VSI for RX */
5391 static int
5392 i40e_dev_rx_init(struct i40e_pf *pf)
5393 {
5394         struct rte_eth_dev_data *data = pf->dev_data;
5395         int ret = I40E_SUCCESS;
5396         uint16_t i;
5397         struct i40e_rx_queue *rxq;
5398
5399         i40e_pf_config_mq_rx(pf);
5400         for (i = 0; i < data->nb_rx_queues; i++) {
5401                 rxq = data->rx_queues[i];
5402                 if (!rxq || !rxq->q_set)
5403                         continue;
5404
5405                 ret = i40e_rx_queue_init(rxq);
5406                 if (ret != I40E_SUCCESS) {
5407                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5408                                     "initialization");
5409                         break;
5410                 }
5411         }
5412         if (ret == I40E_SUCCESS)
5413                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5414                                      ->eth_dev);
5415
5416         return ret;
5417 }
5418
5419 static int
5420 i40e_dev_rxtx_init(struct i40e_pf *pf)
5421 {
5422         int err;
5423
5424         err = i40e_dev_tx_init(pf);
5425         if (err) {
5426                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5427                 return err;
5428         }
5429         err = i40e_dev_rx_init(pf);
5430         if (err) {
5431                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5432                 return err;
5433         }
5434
5435         return err;
5436 }
5437
5438 static int
5439 i40e_vmdq_setup(struct rte_eth_dev *dev)
5440 {
5441         struct rte_eth_conf *conf = &dev->data->dev_conf;
5442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5443         int i, err, conf_vsis, j, loop;
5444         struct i40e_vsi *vsi;
5445         struct i40e_vmdq_info *vmdq_info;
5446         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5448
5449         /*
5450          * Disable interrupt to avoid message from VF. Furthermore, it will
5451          * avoid race condition in VSI creation/destroy.
5452          */
5453         i40e_pf_disable_irq0(hw);
5454
5455         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5456                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5457                 return -ENOTSUP;
5458         }
5459
5460         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5461         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5462                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5463                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5464                         pf->max_nb_vmdq_vsi);
5465                 return -ENOTSUP;
5466         }
5467
5468         if (pf->vmdq != NULL) {
5469                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5470                 return 0;
5471         }
5472
5473         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5474                                 sizeof(*vmdq_info) * conf_vsis, 0);
5475
5476         if (pf->vmdq == NULL) {
5477                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5478                 return -ENOMEM;
5479         }
5480
5481         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5482
5483         /* Create VMDQ VSI */
5484         for (i = 0; i < conf_vsis; i++) {
5485                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5486                                 vmdq_conf->enable_loop_back);
5487                 if (vsi == NULL) {
5488                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5489                         err = -1;
5490                         goto err_vsi_setup;
5491                 }
5492                 vmdq_info = &pf->vmdq[i];
5493                 vmdq_info->pf = pf;
5494                 vmdq_info->vsi = vsi;
5495         }
5496         pf->nb_cfg_vmdq_vsi = conf_vsis;
5497
5498         /* Configure Vlan */
5499         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5500         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5501                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5502                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5503                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5504                                         vmdq_conf->pool_map[i].vlan_id, j);
5505
5506                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5507                                                 vmdq_conf->pool_map[i].vlan_id);
5508                                 if (err) {
5509                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5510                                         err = -1;
5511                                         goto err_vsi_setup;
5512                                 }
5513                         }
5514                 }
5515         }
5516
5517         i40e_pf_enable_irq0(hw);
5518
5519         return 0;
5520
5521 err_vsi_setup:
5522         for (i = 0; i < conf_vsis; i++)
5523                 if (pf->vmdq[i].vsi == NULL)
5524                         break;
5525                 else
5526                         i40e_vsi_release(pf->vmdq[i].vsi);
5527
5528         rte_free(pf->vmdq);
5529         pf->vmdq = NULL;
5530         i40e_pf_enable_irq0(hw);
5531         return err;
5532 }
5533
5534 static void
5535 i40e_stat_update_32(struct i40e_hw *hw,
5536                    uint32_t reg,
5537                    bool offset_loaded,
5538                    uint64_t *offset,
5539                    uint64_t *stat)
5540 {
5541         uint64_t new_data;
5542
5543         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5544         if (!offset_loaded)
5545                 *offset = new_data;
5546
5547         if (new_data >= *offset)
5548                 *stat = (uint64_t)(new_data - *offset);
5549         else
5550                 *stat = (uint64_t)((new_data +
5551                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5552 }
5553
5554 static void
5555 i40e_stat_update_48(struct i40e_hw *hw,
5556                    uint32_t hireg,
5557                    uint32_t loreg,
5558                    bool offset_loaded,
5559                    uint64_t *offset,
5560                    uint64_t *stat)
5561 {
5562         uint64_t new_data;
5563
5564         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5565         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5566                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5567
5568         if (!offset_loaded)
5569                 *offset = new_data;
5570
5571         if (new_data >= *offset)
5572                 *stat = new_data - *offset;
5573         else
5574                 *stat = (uint64_t)((new_data +
5575                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5576
5577         *stat &= I40E_48_BIT_MASK;
5578 }
5579
5580 /* Disable IRQ0 */
5581 void
5582 i40e_pf_disable_irq0(struct i40e_hw *hw)
5583 {
5584         /* Disable all interrupt types */
5585         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5586         I40E_WRITE_FLUSH(hw);
5587 }
5588
5589 /* Enable IRQ0 */
5590 void
5591 i40e_pf_enable_irq0(struct i40e_hw *hw)
5592 {
5593         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5594                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5595                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5596                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5597         I40E_WRITE_FLUSH(hw);
5598 }
5599
5600 static void
5601 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5602 {
5603         /* read pending request and disable first */
5604         i40e_pf_disable_irq0(hw);
5605         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5606         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5607                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5608
5609         if (no_queue)
5610                 /* Link no queues with irq0 */
5611                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5612                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5613 }
5614
5615 static void
5616 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5617 {
5618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5619         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5620         int i;
5621         uint16_t abs_vf_id;
5622         uint32_t index, offset, val;
5623
5624         if (!pf->vfs)
5625                 return;
5626         /**
5627          * Try to find which VF trigger a reset, use absolute VF id to access
5628          * since the reg is global register.
5629          */
5630         for (i = 0; i < pf->vf_num; i++) {
5631                 abs_vf_id = hw->func_caps.vf_base_id + i;
5632                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5633                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5634                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5635                 /* VFR event occured */
5636                 if (val & (0x1 << offset)) {
5637                         int ret;
5638
5639                         /* Clear the event first */
5640                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5641                                                         (0x1 << offset));
5642                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5643                         /**
5644                          * Only notify a VF reset event occured,
5645                          * don't trigger another SW reset
5646                          */
5647                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5648                         if (ret != I40E_SUCCESS)
5649                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5650                 }
5651         }
5652 }
5653
5654 static void
5655 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5656 {
5657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5658         struct i40e_virtchnl_pf_event event;
5659         int i;
5660
5661         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5662         event.event_data.link_event.link_status =
5663                 dev->data->dev_link.link_status;
5664         event.event_data.link_event.link_speed =
5665                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5666
5667         for (i = 0; i < pf->vf_num; i++)
5668                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5669                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5670 }
5671
5672 static void
5673 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5674 {
5675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5676         struct i40e_arq_event_info info;
5677         uint16_t pending, opcode;
5678         int ret;
5679
5680         info.buf_len = I40E_AQ_BUF_SZ;
5681         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5682         if (!info.msg_buf) {
5683                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5684                 return;
5685         }
5686
5687         pending = 1;
5688         while (pending) {
5689                 ret = i40e_clean_arq_element(hw, &info, &pending);
5690
5691                 if (ret != I40E_SUCCESS) {
5692                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5693                                     "aq_err: %u", hw->aq.asq_last_status);
5694                         break;
5695                 }
5696                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5697
5698                 switch (opcode) {
5699                 case i40e_aqc_opc_send_msg_to_pf:
5700                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5701                         i40e_pf_host_handle_vf_msg(dev,
5702                                         rte_le_to_cpu_16(info.desc.retval),
5703                                         rte_le_to_cpu_32(info.desc.cookie_high),
5704                                         rte_le_to_cpu_32(info.desc.cookie_low),
5705                                         info.msg_buf,
5706                                         info.msg_len);
5707                         break;
5708                 case i40e_aqc_opc_get_link_status:
5709                         ret = i40e_dev_link_update(dev, 0);
5710                         if (!ret) {
5711                                 i40e_notify_all_vfs_link_status(dev);
5712                                 _rte_eth_dev_callback_process(dev,
5713                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5714                         }
5715                         break;
5716                 default:
5717                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5718                                     opcode);
5719                         break;
5720                 }
5721         }
5722         rte_free(info.msg_buf);
5723 }
5724
5725 /**
5726  * Interrupt handler triggered by NIC  for handling
5727  * specific interrupt.
5728  *
5729  * @param handle
5730  *  Pointer to interrupt handle.
5731  * @param param
5732  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5733  *
5734  * @return
5735  *  void
5736  */
5737 static void
5738 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5739                            void *param)
5740 {
5741         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5742         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5743         uint32_t icr0;
5744
5745         /* Disable interrupt */
5746         i40e_pf_disable_irq0(hw);
5747
5748         /* read out interrupt causes */
5749         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5750
5751         /* No interrupt event indicated */
5752         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5753                 PMD_DRV_LOG(INFO, "No interrupt event");
5754                 goto done;
5755         }
5756 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5757         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5758                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5759         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5760                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5761         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5762                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5763         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5764                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5765         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5766                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5767         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5768                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5769         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5770                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5771 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5772
5773         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5774                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5775                 i40e_dev_handle_vfr_event(dev);
5776         }
5777         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5778                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5779                 i40e_dev_handle_aq_msg(dev);
5780         }
5781
5782 done:
5783         /* Enable interrupt */
5784         i40e_pf_enable_irq0(hw);
5785         rte_intr_enable(intr_handle);
5786 }
5787
5788 static int
5789 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5790                          struct i40e_macvlan_filter *filter,
5791                          int total)
5792 {
5793         int ele_num, ele_buff_size;
5794         int num, actual_num, i;
5795         uint16_t flags;
5796         int ret = I40E_SUCCESS;
5797         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5798         struct i40e_aqc_add_macvlan_element_data *req_list;
5799
5800         if (filter == NULL  || total == 0)
5801                 return I40E_ERR_PARAM;
5802         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5803         ele_buff_size = hw->aq.asq_buf_size;
5804
5805         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5806         if (req_list == NULL) {
5807                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5808                 return I40E_ERR_NO_MEMORY;
5809         }
5810
5811         num = 0;
5812         do {
5813                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5814                 memset(req_list, 0, ele_buff_size);
5815
5816                 for (i = 0; i < actual_num; i++) {
5817                         (void)rte_memcpy(req_list[i].mac_addr,
5818                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5819                         req_list[i].vlan_tag =
5820                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5821
5822                         switch (filter[num + i].filter_type) {
5823                         case RTE_MAC_PERFECT_MATCH:
5824                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5825                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5826                                 break;
5827                         case RTE_MACVLAN_PERFECT_MATCH:
5828                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5829                                 break;
5830                         case RTE_MAC_HASH_MATCH:
5831                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5832                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5833                                 break;
5834                         case RTE_MACVLAN_HASH_MATCH:
5835                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5836                                 break;
5837                         default:
5838                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5839                                 ret = I40E_ERR_PARAM;
5840                                 goto DONE;
5841                         }
5842
5843                         req_list[i].queue_number = 0;
5844
5845                         req_list[i].flags = rte_cpu_to_le_16(flags);
5846                 }
5847
5848                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5849                                                 actual_num, NULL);
5850                 if (ret != I40E_SUCCESS) {
5851                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5852                         goto DONE;
5853                 }
5854                 num += actual_num;
5855         } while (num < total);
5856
5857 DONE:
5858         rte_free(req_list);
5859         return ret;
5860 }
5861
5862 static int
5863 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5864                             struct i40e_macvlan_filter *filter,
5865                             int total)
5866 {
5867         int ele_num, ele_buff_size;
5868         int num, actual_num, i;
5869         uint16_t flags;
5870         int ret = I40E_SUCCESS;
5871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5872         struct i40e_aqc_remove_macvlan_element_data *req_list;
5873
5874         if (filter == NULL  || total == 0)
5875                 return I40E_ERR_PARAM;
5876
5877         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5878         ele_buff_size = hw->aq.asq_buf_size;
5879
5880         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5881         if (req_list == NULL) {
5882                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5883                 return I40E_ERR_NO_MEMORY;
5884         }
5885
5886         num = 0;
5887         do {
5888                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5889                 memset(req_list, 0, ele_buff_size);
5890
5891                 for (i = 0; i < actual_num; i++) {
5892                         (void)rte_memcpy(req_list[i].mac_addr,
5893                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5894                         req_list[i].vlan_tag =
5895                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5896
5897                         switch (filter[num + i].filter_type) {
5898                         case RTE_MAC_PERFECT_MATCH:
5899                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5900                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5901                                 break;
5902                         case RTE_MACVLAN_PERFECT_MATCH:
5903                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5904                                 break;
5905                         case RTE_MAC_HASH_MATCH:
5906                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5907                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5908                                 break;
5909                         case RTE_MACVLAN_HASH_MATCH:
5910                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5911                                 break;
5912                         default:
5913                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5914                                 ret = I40E_ERR_PARAM;
5915                                 goto DONE;
5916                         }
5917                         req_list[i].flags = rte_cpu_to_le_16(flags);
5918                 }
5919
5920                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5921                                                 actual_num, NULL);
5922                 if (ret != I40E_SUCCESS) {
5923                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5924                         goto DONE;
5925                 }
5926                 num += actual_num;
5927         } while (num < total);
5928
5929 DONE:
5930         rte_free(req_list);
5931         return ret;
5932 }
5933
5934 /* Find out specific MAC filter */
5935 static struct i40e_mac_filter *
5936 i40e_find_mac_filter(struct i40e_vsi *vsi,
5937                          struct ether_addr *macaddr)
5938 {
5939         struct i40e_mac_filter *f;
5940
5941         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5942                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5943                         return f;
5944         }
5945
5946         return NULL;
5947 }
5948
5949 static bool
5950 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5951                          uint16_t vlan_id)
5952 {
5953         uint32_t vid_idx, vid_bit;
5954
5955         if (vlan_id > ETH_VLAN_ID_MAX)
5956                 return 0;
5957
5958         vid_idx = I40E_VFTA_IDX(vlan_id);
5959         vid_bit = I40E_VFTA_BIT(vlan_id);
5960
5961         if (vsi->vfta[vid_idx] & vid_bit)
5962                 return 1;
5963         else
5964                 return 0;
5965 }
5966
5967 static void
5968 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5969                          uint16_t vlan_id, bool on)
5970 {
5971         uint32_t vid_idx, vid_bit;
5972
5973         if (vlan_id > ETH_VLAN_ID_MAX)
5974                 return;
5975
5976         vid_idx = I40E_VFTA_IDX(vlan_id);
5977         vid_bit = I40E_VFTA_BIT(vlan_id);
5978
5979         if (on)
5980                 vsi->vfta[vid_idx] |= vid_bit;
5981         else
5982                 vsi->vfta[vid_idx] &= ~vid_bit;
5983 }
5984
5985 /**
5986  * Find all vlan options for specific mac addr,
5987  * return with actual vlan found.
5988  */
5989 static inline int
5990 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5991                            struct i40e_macvlan_filter *mv_f,
5992                            int num, struct ether_addr *addr)
5993 {
5994         int i;
5995         uint32_t j, k;
5996
5997         /**
5998          * Not to use i40e_find_vlan_filter to decrease the loop time,
5999          * although the code looks complex.
6000           */
6001         if (num < vsi->vlan_num)
6002                 return I40E_ERR_PARAM;
6003
6004         i = 0;
6005         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6006                 if (vsi->vfta[j]) {
6007                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6008                                 if (vsi->vfta[j] & (1 << k)) {
6009                                         if (i > num - 1) {
6010                                                 PMD_DRV_LOG(ERR, "vlan number "
6011                                                             "not match");
6012                                                 return I40E_ERR_PARAM;
6013                                         }
6014                                         (void)rte_memcpy(&mv_f[i].macaddr,
6015                                                         addr, ETH_ADDR_LEN);
6016                                         mv_f[i].vlan_id =
6017                                                 j * I40E_UINT32_BIT_SIZE + k;
6018                                         i++;
6019                                 }
6020                         }
6021                 }
6022         }
6023         return I40E_SUCCESS;
6024 }
6025
6026 static inline int
6027 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6028                            struct i40e_macvlan_filter *mv_f,
6029                            int num,
6030                            uint16_t vlan)
6031 {
6032         int i = 0;
6033         struct i40e_mac_filter *f;
6034
6035         if (num < vsi->mac_num)
6036                 return I40E_ERR_PARAM;
6037
6038         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6039                 if (i > num - 1) {
6040                         PMD_DRV_LOG(ERR, "buffer number not match");
6041                         return I40E_ERR_PARAM;
6042                 }
6043                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6044                                 ETH_ADDR_LEN);
6045                 mv_f[i].vlan_id = vlan;
6046                 mv_f[i].filter_type = f->mac_info.filter_type;
6047                 i++;
6048         }
6049
6050         return I40E_SUCCESS;
6051 }
6052
6053 static int
6054 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6055 {
6056         int i, num;
6057         struct i40e_mac_filter *f;
6058         struct i40e_macvlan_filter *mv_f;
6059         int ret = I40E_SUCCESS;
6060
6061         if (vsi == NULL || vsi->mac_num == 0)
6062                 return I40E_ERR_PARAM;
6063
6064         /* Case that no vlan is set */
6065         if (vsi->vlan_num == 0)
6066                 num = vsi->mac_num;
6067         else
6068                 num = vsi->mac_num * vsi->vlan_num;
6069
6070         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6071         if (mv_f == NULL) {
6072                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6073                 return I40E_ERR_NO_MEMORY;
6074         }
6075
6076         i = 0;
6077         if (vsi->vlan_num == 0) {
6078                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6079                         (void)rte_memcpy(&mv_f[i].macaddr,
6080                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6081                         mv_f[i].vlan_id = 0;
6082                         i++;
6083                 }
6084         } else {
6085                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6086                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6087                                         vsi->vlan_num, &f->mac_info.mac_addr);
6088                         if (ret != I40E_SUCCESS)
6089                                 goto DONE;
6090                         i += vsi->vlan_num;
6091                 }
6092         }
6093
6094         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6095 DONE:
6096         rte_free(mv_f);
6097
6098         return ret;
6099 }
6100
6101 int
6102 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6103 {
6104         struct i40e_macvlan_filter *mv_f;
6105         int mac_num;
6106         int ret = I40E_SUCCESS;
6107
6108         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6109                 return I40E_ERR_PARAM;
6110
6111         /* If it's already set, just return */
6112         if (i40e_find_vlan_filter(vsi,vlan))
6113                 return I40E_SUCCESS;
6114
6115         mac_num = vsi->mac_num;
6116
6117         if (mac_num == 0) {
6118                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6119                 return I40E_ERR_PARAM;
6120         }
6121
6122         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6123
6124         if (mv_f == NULL) {
6125                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6126                 return I40E_ERR_NO_MEMORY;
6127         }
6128
6129         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6130
6131         if (ret != I40E_SUCCESS)
6132                 goto DONE;
6133
6134         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6135
6136         if (ret != I40E_SUCCESS)
6137                 goto DONE;
6138
6139         i40e_set_vlan_filter(vsi, vlan, 1);
6140
6141         vsi->vlan_num++;
6142         ret = I40E_SUCCESS;
6143 DONE:
6144         rte_free(mv_f);
6145         return ret;
6146 }
6147
6148 int
6149 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6150 {
6151         struct i40e_macvlan_filter *mv_f;
6152         int mac_num;
6153         int ret = I40E_SUCCESS;
6154
6155         /**
6156          * Vlan 0 is the generic filter for untagged packets
6157          * and can't be removed.
6158          */
6159         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6160                 return I40E_ERR_PARAM;
6161
6162         /* If can't find it, just return */
6163         if (!i40e_find_vlan_filter(vsi, vlan))
6164                 return I40E_ERR_PARAM;
6165
6166         mac_num = vsi->mac_num;
6167
6168         if (mac_num == 0) {
6169                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6170                 return I40E_ERR_PARAM;
6171         }
6172
6173         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6174
6175         if (mv_f == NULL) {
6176                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6177                 return I40E_ERR_NO_MEMORY;
6178         }
6179
6180         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6181
6182         if (ret != I40E_SUCCESS)
6183                 goto DONE;
6184
6185         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6186
6187         if (ret != I40E_SUCCESS)
6188                 goto DONE;
6189
6190         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6191         if (vsi->vlan_num == 1) {
6192                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6193                 if (ret != I40E_SUCCESS)
6194                         goto DONE;
6195
6196                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6197                 if (ret != I40E_SUCCESS)
6198                         goto DONE;
6199         }
6200
6201         i40e_set_vlan_filter(vsi, vlan, 0);
6202
6203         vsi->vlan_num--;
6204         ret = I40E_SUCCESS;
6205 DONE:
6206         rte_free(mv_f);
6207         return ret;
6208 }
6209
6210 int
6211 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6212 {
6213         struct i40e_mac_filter *f;
6214         struct i40e_macvlan_filter *mv_f;
6215         int i, vlan_num = 0;
6216         int ret = I40E_SUCCESS;
6217
6218         /* If it's add and we've config it, return */
6219         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6220         if (f != NULL)
6221                 return I40E_SUCCESS;
6222         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6223                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6224
6225                 /**
6226                  * If vlan_num is 0, that's the first time to add mac,
6227                  * set mask for vlan_id 0.
6228                  */
6229                 if (vsi->vlan_num == 0) {
6230                         i40e_set_vlan_filter(vsi, 0, 1);
6231                         vsi->vlan_num = 1;
6232                 }
6233                 vlan_num = vsi->vlan_num;
6234         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6235                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6236                 vlan_num = 1;
6237
6238         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6239         if (mv_f == NULL) {
6240                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6241                 return I40E_ERR_NO_MEMORY;
6242         }
6243
6244         for (i = 0; i < vlan_num; i++) {
6245                 mv_f[i].filter_type = mac_filter->filter_type;
6246                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6247                                 ETH_ADDR_LEN);
6248         }
6249
6250         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6251                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6252                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6253                                         &mac_filter->mac_addr);
6254                 if (ret != I40E_SUCCESS)
6255                         goto DONE;
6256         }
6257
6258         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6259         if (ret != I40E_SUCCESS)
6260                 goto DONE;
6261
6262         /* Add the mac addr into mac list */
6263         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6264         if (f == NULL) {
6265                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6266                 ret = I40E_ERR_NO_MEMORY;
6267                 goto DONE;
6268         }
6269         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6270                         ETH_ADDR_LEN);
6271         f->mac_info.filter_type = mac_filter->filter_type;
6272         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6273         vsi->mac_num++;
6274
6275         ret = I40E_SUCCESS;
6276 DONE:
6277         rte_free(mv_f);
6278
6279         return ret;
6280 }
6281
6282 int
6283 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6284 {
6285         struct i40e_mac_filter *f;
6286         struct i40e_macvlan_filter *mv_f;
6287         int i, vlan_num;
6288         enum rte_mac_filter_type filter_type;
6289         int ret = I40E_SUCCESS;
6290
6291         /* Can't find it, return an error */
6292         f = i40e_find_mac_filter(vsi, addr);
6293         if (f == NULL)
6294                 return I40E_ERR_PARAM;
6295
6296         vlan_num = vsi->vlan_num;
6297         filter_type = f->mac_info.filter_type;
6298         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6299                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6300                 if (vlan_num == 0) {
6301                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6302                         return I40E_ERR_PARAM;
6303                 }
6304         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6305                         filter_type == RTE_MAC_HASH_MATCH)
6306                 vlan_num = 1;
6307
6308         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6309         if (mv_f == NULL) {
6310                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6311                 return I40E_ERR_NO_MEMORY;
6312         }
6313
6314         for (i = 0; i < vlan_num; i++) {
6315                 mv_f[i].filter_type = filter_type;
6316                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6317                                 ETH_ADDR_LEN);
6318         }
6319         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6320                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6321                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6322                 if (ret != I40E_SUCCESS)
6323                         goto DONE;
6324         }
6325
6326         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6327         if (ret != I40E_SUCCESS)
6328                 goto DONE;
6329
6330         /* Remove the mac addr into mac list */
6331         TAILQ_REMOVE(&vsi->mac_list, f, next);
6332         rte_free(f);
6333         vsi->mac_num--;
6334
6335         ret = I40E_SUCCESS;
6336 DONE:
6337         rte_free(mv_f);
6338         return ret;
6339 }
6340
6341 /* Configure hash enable flags for RSS */
6342 uint64_t
6343 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6344 {
6345         uint64_t hena = 0;
6346
6347         if (!flags)
6348                 return hena;
6349
6350         if (flags & ETH_RSS_FRAG_IPV4)
6351                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6352         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6353                 if (type == I40E_MAC_X722) {
6354                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6355                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6356                 } else
6357                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6358         }
6359         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6360                 if (type == I40E_MAC_X722) {
6361                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6362                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6363                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6364                 } else
6365                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6366         }
6367         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6368                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6369         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6370                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6371         if (flags & ETH_RSS_FRAG_IPV6)
6372                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6373         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6374                 if (type == I40E_MAC_X722) {
6375                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6376                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6377                 } else
6378                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6379         }
6380         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6381                 if (type == I40E_MAC_X722) {
6382                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6383                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6384                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6385                 } else
6386                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6387         }
6388         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6389                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6390         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6391                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6392         if (flags & ETH_RSS_L2_PAYLOAD)
6393                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6394
6395         return hena;
6396 }
6397
6398 /* Parse the hash enable flags */
6399 uint64_t
6400 i40e_parse_hena(uint64_t flags)
6401 {
6402         uint64_t rss_hf = 0;
6403
6404         if (!flags)
6405                 return rss_hf;
6406         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6407                 rss_hf |= ETH_RSS_FRAG_IPV4;
6408         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6409                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6410         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6411                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6412         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6413                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6414         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6415                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6416         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6417                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6418         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6419                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6420         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6421                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6422         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6423                 rss_hf |= ETH_RSS_FRAG_IPV6;
6424         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6425                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6426         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6427                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6428         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6429                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6430         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6431                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6432         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6433                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6434         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6435                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6436         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6437                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6438         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6439                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6440
6441         return rss_hf;
6442 }
6443
6444 /* Disable RSS */
6445 static void
6446 i40e_pf_disable_rss(struct i40e_pf *pf)
6447 {
6448         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6449         uint64_t hena;
6450
6451         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6452         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6453         if (hw->mac.type == I40E_MAC_X722)
6454                 hena &= ~I40E_RSS_HENA_ALL_X722;
6455         else
6456                 hena &= ~I40E_RSS_HENA_ALL;
6457         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6458         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6459         I40E_WRITE_FLUSH(hw);
6460 }
6461
6462 static int
6463 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6464 {
6465         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6466         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6467         int ret = 0;
6468
6469         if (!key || key_len == 0) {
6470                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6471                 return 0;
6472         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6473                 sizeof(uint32_t)) {
6474                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6475                 return -EINVAL;
6476         }
6477
6478         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6479                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6480                         (struct i40e_aqc_get_set_rss_key_data *)key;
6481
6482                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6483                 if (ret)
6484                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6485                                      "via AQ");
6486         } else {
6487                 uint32_t *hash_key = (uint32_t *)key;
6488                 uint16_t i;
6489
6490                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6491                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6492                 I40E_WRITE_FLUSH(hw);
6493         }
6494
6495         return ret;
6496 }
6497
6498 static int
6499 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6500 {
6501         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6503         int ret;
6504
6505         if (!key || !key_len)
6506                 return -EINVAL;
6507
6508         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6509                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6510                         (struct i40e_aqc_get_set_rss_key_data *)key);
6511                 if (ret) {
6512                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6513                         return ret;
6514                 }
6515         } else {
6516                 uint32_t *key_dw = (uint32_t *)key;
6517                 uint16_t i;
6518
6519                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6520                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6521         }
6522         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6523
6524         return 0;
6525 }
6526
6527 static int
6528 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6529 {
6530         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6531         uint64_t rss_hf;
6532         uint64_t hena;
6533         int ret;
6534
6535         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6536                                rss_conf->rss_key_len);
6537         if (ret)
6538                 return ret;
6539
6540         rss_hf = rss_conf->rss_hf;
6541         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6542         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6543         if (hw->mac.type == I40E_MAC_X722)
6544                 hena &= ~I40E_RSS_HENA_ALL_X722;
6545         else
6546                 hena &= ~I40E_RSS_HENA_ALL;
6547         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6548         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6549         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6550         I40E_WRITE_FLUSH(hw);
6551
6552         return 0;
6553 }
6554
6555 static int
6556 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6557                          struct rte_eth_rss_conf *rss_conf)
6558 {
6559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6561         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6562         uint64_t hena;
6563
6564         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6565         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6566         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6567                  ? I40E_RSS_HENA_ALL_X722
6568                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6569                 if (rss_hf != 0) /* Enable RSS */
6570                         return -EINVAL;
6571                 return 0; /* Nothing to do */
6572         }
6573         /* RSS enabled */
6574         if (rss_hf == 0) /* Disable RSS */
6575                 return -EINVAL;
6576
6577         return i40e_hw_rss_hash_set(pf, rss_conf);
6578 }
6579
6580 static int
6581 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6582                            struct rte_eth_rss_conf *rss_conf)
6583 {
6584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6586         uint64_t hena;
6587
6588         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6589                          &rss_conf->rss_key_len);
6590
6591         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6592         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6593         rss_conf->rss_hf = i40e_parse_hena(hena);
6594
6595         return 0;
6596 }
6597
6598 static int
6599 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6600 {
6601         switch (filter_type) {
6602         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6603                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6604                 break;
6605         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6606                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6607                 break;
6608         case RTE_TUNNEL_FILTER_IMAC_TENID:
6609                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6610                 break;
6611         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6612                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6613                 break;
6614         case ETH_TUNNEL_FILTER_IMAC:
6615                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6616                 break;
6617         case ETH_TUNNEL_FILTER_OIP:
6618                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6619                 break;
6620         case ETH_TUNNEL_FILTER_IIP:
6621                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6622                 break;
6623         default:
6624                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6625                 return -EINVAL;
6626         }
6627
6628         return 0;
6629 }
6630
6631 /* Convert tunnel filter structure */
6632 static int
6633 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6634                            *cld_filter,
6635                            struct i40e_tunnel_filter *tunnel_filter)
6636 {
6637         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6638                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6639         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6640                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6641         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6642         tunnel_filter->input.flags = cld_filter->flags;
6643         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6644         tunnel_filter->queue = cld_filter->queue_number;
6645
6646         return 0;
6647 }
6648
6649 /* Check if there exists the tunnel filter */
6650 struct i40e_tunnel_filter *
6651 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6652                              const struct i40e_tunnel_filter_input *input)
6653 {
6654         int ret;
6655
6656         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6657         if (ret < 0)
6658                 return NULL;
6659
6660         return tunnel_rule->hash_map[ret];
6661 }
6662
6663 /* Add a tunnel filter into the SW list */
6664 static int
6665 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6666                              struct i40e_tunnel_filter *tunnel_filter)
6667 {
6668         struct i40e_tunnel_rule *rule = &pf->tunnel;
6669         int ret;
6670
6671         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6672         if (ret < 0) {
6673                 PMD_DRV_LOG(ERR,
6674                             "Failed to insert tunnel filter to hash table %d!",
6675                             ret);
6676                 return ret;
6677         }
6678         rule->hash_map[ret] = tunnel_filter;
6679
6680         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6681
6682         return 0;
6683 }
6684
6685 /* Delete a tunnel filter from the SW list */
6686 int
6687 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6688                           struct i40e_tunnel_filter_input *input)
6689 {
6690         struct i40e_tunnel_rule *rule = &pf->tunnel;
6691         struct i40e_tunnel_filter *tunnel_filter;
6692         int ret;
6693
6694         ret = rte_hash_del_key(rule->hash_table, input);
6695         if (ret < 0) {
6696                 PMD_DRV_LOG(ERR,
6697                             "Failed to delete tunnel filter to hash table %d!",
6698                             ret);
6699                 return ret;
6700         }
6701         tunnel_filter = rule->hash_map[ret];
6702         rule->hash_map[ret] = NULL;
6703
6704         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6705         rte_free(tunnel_filter);
6706
6707         return 0;
6708 }
6709
6710 static int
6711 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6712                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6713                         uint8_t add)
6714 {
6715         uint16_t ip_type;
6716         uint32_t ipv4_addr;
6717         uint8_t i, tun_type = 0;
6718         /* internal varialbe to convert ipv6 byte order */
6719         uint32_t convert_ipv6[4];
6720         int val, ret = 0;
6721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6722         struct i40e_vsi *vsi = pf->main_vsi;
6723         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6724         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6725         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6726         struct i40e_tunnel_filter *tunnel, *node;
6727         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6728
6729         cld_filter = rte_zmalloc("tunnel_filter",
6730                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6731                 0);
6732
6733         if (NULL == cld_filter) {
6734                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6735                 return -EINVAL;
6736         }
6737         pfilter = cld_filter;
6738
6739         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6740         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6741
6742         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6743         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6744                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6745                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6746                 rte_memcpy(&pfilter->ipaddr.v4.data,
6747                                 &rte_cpu_to_le_32(ipv4_addr),
6748                                 sizeof(pfilter->ipaddr.v4.data));
6749         } else {
6750                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6751                 for (i = 0; i < 4; i++) {
6752                         convert_ipv6[i] =
6753                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6754                 }
6755                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6756                                 sizeof(pfilter->ipaddr.v6.data));
6757         }
6758
6759         /* check tunneled type */
6760         switch (tunnel_filter->tunnel_type) {
6761         case RTE_TUNNEL_TYPE_VXLAN:
6762                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6763                 break;
6764         case RTE_TUNNEL_TYPE_NVGRE:
6765                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6766                 break;
6767         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6768                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6769                 break;
6770         default:
6771                 /* Other tunnel types is not supported. */
6772                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6773                 rte_free(cld_filter);
6774                 return -EINVAL;
6775         }
6776
6777         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6778                                                 &pfilter->flags);
6779         if (val < 0) {
6780                 rte_free(cld_filter);
6781                 return -EINVAL;
6782         }
6783
6784         pfilter->flags |= rte_cpu_to_le_16(
6785                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6786                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6787         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6788         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6789
6790         /* Check if there is the filter in SW list */
6791         memset(&check_filter, 0, sizeof(check_filter));
6792         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6793         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6794         if (add && node) {
6795                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6796                 return -EINVAL;
6797         }
6798
6799         if (!add && !node) {
6800                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6801                 return -EINVAL;
6802         }
6803
6804         if (add) {
6805                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6806                 if (ret < 0) {
6807                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6808                         return ret;
6809                 }
6810                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6811                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6812                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6813         } else {
6814                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6815                                                    cld_filter, 1);
6816                 if (ret < 0) {
6817                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6818                         return ret;
6819                 }
6820                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6821         }
6822
6823         rte_free(cld_filter);
6824         return ret;
6825 }
6826
6827 static int
6828 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6829 {
6830         uint8_t i;
6831
6832         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6833                 if (pf->vxlan_ports[i] == port)
6834                         return i;
6835         }
6836
6837         return -1;
6838 }
6839
6840 static int
6841 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6842 {
6843         int  idx, ret;
6844         uint8_t filter_idx;
6845         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6846
6847         idx = i40e_get_vxlan_port_idx(pf, port);
6848
6849         /* Check if port already exists */
6850         if (idx >= 0) {
6851                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6852                 return -EINVAL;
6853         }
6854
6855         /* Now check if there is space to add the new port */
6856         idx = i40e_get_vxlan_port_idx(pf, 0);
6857         if (idx < 0) {
6858                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6859                         "not adding port %d", port);
6860                 return -ENOSPC;
6861         }
6862
6863         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6864                                         &filter_idx, NULL);
6865         if (ret < 0) {
6866                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6867                 return -1;
6868         }
6869
6870         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6871                          port,  filter_idx);
6872
6873         /* New port: add it and mark its index in the bitmap */
6874         pf->vxlan_ports[idx] = port;
6875         pf->vxlan_bitmap |= (1 << idx);
6876
6877         if (!(pf->flags & I40E_FLAG_VXLAN))
6878                 pf->flags |= I40E_FLAG_VXLAN;
6879
6880         return 0;
6881 }
6882
6883 static int
6884 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6885 {
6886         int idx;
6887         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6888
6889         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6890                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6891                 return -EINVAL;
6892         }
6893
6894         idx = i40e_get_vxlan_port_idx(pf, port);
6895
6896         if (idx < 0) {
6897                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6898                 return -EINVAL;
6899         }
6900
6901         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6902                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6903                 return -1;
6904         }
6905
6906         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6907                         port, idx);
6908
6909         pf->vxlan_ports[idx] = 0;
6910         pf->vxlan_bitmap &= ~(1 << idx);
6911
6912         if (!pf->vxlan_bitmap)
6913                 pf->flags &= ~I40E_FLAG_VXLAN;
6914
6915         return 0;
6916 }
6917
6918 /* Add UDP tunneling port */
6919 static int
6920 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6921                              struct rte_eth_udp_tunnel *udp_tunnel)
6922 {
6923         int ret = 0;
6924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6925
6926         if (udp_tunnel == NULL)
6927                 return -EINVAL;
6928
6929         switch (udp_tunnel->prot_type) {
6930         case RTE_TUNNEL_TYPE_VXLAN:
6931                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6932                 break;
6933
6934         case RTE_TUNNEL_TYPE_GENEVE:
6935         case RTE_TUNNEL_TYPE_TEREDO:
6936                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6937                 ret = -1;
6938                 break;
6939
6940         default:
6941                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6942                 ret = -1;
6943                 break;
6944         }
6945
6946         return ret;
6947 }
6948
6949 /* Remove UDP tunneling port */
6950 static int
6951 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6952                              struct rte_eth_udp_tunnel *udp_tunnel)
6953 {
6954         int ret = 0;
6955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6956
6957         if (udp_tunnel == NULL)
6958                 return -EINVAL;
6959
6960         switch (udp_tunnel->prot_type) {
6961         case RTE_TUNNEL_TYPE_VXLAN:
6962                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6963                 break;
6964         case RTE_TUNNEL_TYPE_GENEVE:
6965         case RTE_TUNNEL_TYPE_TEREDO:
6966                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6967                 ret = -1;
6968                 break;
6969         default:
6970                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6971                 ret = -1;
6972                 break;
6973         }
6974
6975         return ret;
6976 }
6977
6978 /* Calculate the maximum number of contiguous PF queues that are configured */
6979 static int
6980 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6981 {
6982         struct rte_eth_dev_data *data = pf->dev_data;
6983         int i, num;
6984         struct i40e_rx_queue *rxq;
6985
6986         num = 0;
6987         for (i = 0; i < pf->lan_nb_qps; i++) {
6988                 rxq = data->rx_queues[i];
6989                 if (rxq && rxq->q_set)
6990                         num++;
6991                 else
6992                         break;
6993         }
6994
6995         return num;
6996 }
6997
6998 /* Configure RSS */
6999 static int
7000 i40e_pf_config_rss(struct i40e_pf *pf)
7001 {
7002         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7003         struct rte_eth_rss_conf rss_conf;
7004         uint32_t i, lut = 0;
7005         uint16_t j, num;
7006
7007         /*
7008          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7009          * It's necessary to calulate the actual PF queues that are configured.
7010          */
7011         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7012                 num = i40e_pf_calc_configured_queues_num(pf);
7013         else
7014                 num = pf->dev_data->nb_rx_queues;
7015
7016         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7017         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7018                         num);
7019
7020         if (num == 0) {
7021                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7022                 return -ENOTSUP;
7023         }
7024
7025         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7026                 if (j == num)
7027                         j = 0;
7028                 lut = (lut << 8) | (j & ((0x1 <<
7029                         hw->func_caps.rss_table_entry_width) - 1));
7030                 if ((i & 3) == 3)
7031                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7032         }
7033
7034         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7035         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7036                 i40e_pf_disable_rss(pf);
7037                 return 0;
7038         }
7039         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7040                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7041                 /* Random default keys */
7042                 static uint32_t rss_key_default[] = {0x6b793944,
7043                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7044                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7045                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7046
7047                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7048                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7049                                                         sizeof(uint32_t);
7050         }
7051
7052         return i40e_hw_rss_hash_set(pf, &rss_conf);
7053 }
7054
7055 static int
7056 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7057                                struct rte_eth_tunnel_filter_conf *filter)
7058 {
7059         if (pf == NULL || filter == NULL) {
7060                 PMD_DRV_LOG(ERR, "Invalid parameter");
7061                 return -EINVAL;
7062         }
7063
7064         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7065                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7066                 return -EINVAL;
7067         }
7068
7069         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7070                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7071                 return -EINVAL;
7072         }
7073
7074         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7075                 (is_zero_ether_addr(&filter->outer_mac))) {
7076                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7077                 return -EINVAL;
7078         }
7079
7080         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7081                 (is_zero_ether_addr(&filter->inner_mac))) {
7082                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7083                 return -EINVAL;
7084         }
7085
7086         return 0;
7087 }
7088
7089 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7090 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7091 static int
7092 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7093 {
7094         uint32_t val, reg;
7095         int ret = -EINVAL;
7096
7097         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7098         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7099
7100         if (len == 3) {
7101                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7102         } else if (len == 4) {
7103                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7104         } else {
7105                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7106                 return ret;
7107         }
7108
7109         if (reg != val) {
7110                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7111                                                    reg, NULL);
7112                 if (ret != 0)
7113                         return ret;
7114         } else {
7115                 ret = 0;
7116         }
7117         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7118                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7119
7120         return ret;
7121 }
7122
7123 static int
7124 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7125 {
7126         int ret = -EINVAL;
7127
7128         if (!hw || !cfg)
7129                 return -EINVAL;
7130
7131         switch (cfg->cfg_type) {
7132         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7133                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7134                 break;
7135         default:
7136                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7137                 break;
7138         }
7139
7140         return ret;
7141 }
7142
7143 static int
7144 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7145                                enum rte_filter_op filter_op,
7146                                void *arg)
7147 {
7148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7149         int ret = I40E_ERR_PARAM;
7150
7151         switch (filter_op) {
7152         case RTE_ETH_FILTER_SET:
7153                 ret = i40e_dev_global_config_set(hw,
7154                         (struct rte_eth_global_cfg *)arg);
7155                 break;
7156         default:
7157                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7158                 break;
7159         }
7160
7161         return ret;
7162 }
7163
7164 static int
7165 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7166                           enum rte_filter_op filter_op,
7167                           void *arg)
7168 {
7169         struct rte_eth_tunnel_filter_conf *filter;
7170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7171         int ret = I40E_SUCCESS;
7172
7173         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7174
7175         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7176                 return I40E_ERR_PARAM;
7177
7178         switch (filter_op) {
7179         case RTE_ETH_FILTER_NOP:
7180                 if (!(pf->flags & I40E_FLAG_VXLAN))
7181                         ret = I40E_NOT_SUPPORTED;
7182                 break;
7183         case RTE_ETH_FILTER_ADD:
7184                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7185                 break;
7186         case RTE_ETH_FILTER_DELETE:
7187                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7188                 break;
7189         default:
7190                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7191                 ret = I40E_ERR_PARAM;
7192                 break;
7193         }
7194
7195         return ret;
7196 }
7197
7198 static int
7199 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7200 {
7201         int ret = 0;
7202         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7203
7204         /* RSS setup */
7205         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7206                 ret = i40e_pf_config_rss(pf);
7207         else
7208                 i40e_pf_disable_rss(pf);
7209
7210         return ret;
7211 }
7212
7213 /* Get the symmetric hash enable configurations per port */
7214 static void
7215 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7216 {
7217         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7218
7219         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7220 }
7221
7222 /* Set the symmetric hash enable configurations per port */
7223 static void
7224 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7225 {
7226         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7227
7228         if (enable > 0) {
7229                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7230                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7231                                                         "been enabled");
7232                         return;
7233                 }
7234                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7235         } else {
7236                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7237                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7238                                                         "been disabled");
7239                         return;
7240                 }
7241                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7242         }
7243         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7244         I40E_WRITE_FLUSH(hw);
7245 }
7246
7247 /*
7248  * Get global configurations of hash function type and symmetric hash enable
7249  * per flow type (pctype). Note that global configuration means it affects all
7250  * the ports on the same NIC.
7251  */
7252 static int
7253 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7254                                    struct rte_eth_hash_global_conf *g_cfg)
7255 {
7256         uint32_t reg, mask = I40E_FLOW_TYPES;
7257         uint16_t i;
7258         enum i40e_filter_pctype pctype;
7259
7260         memset(g_cfg, 0, sizeof(*g_cfg));
7261         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7262         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7263                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7264         else
7265                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7266         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7267                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7268
7269         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7270                 if (!(mask & (1UL << i)))
7271                         continue;
7272                 mask &= ~(1UL << i);
7273                 /* Bit set indicats the coresponding flow type is supported */
7274                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7275                 /* if flowtype is invalid, continue */
7276                 if (!I40E_VALID_FLOW(i))
7277                         continue;
7278                 pctype = i40e_flowtype_to_pctype(i);
7279                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7280                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7281                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7282         }
7283
7284         return 0;
7285 }
7286
7287 static int
7288 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7289 {
7290         uint32_t i;
7291         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7292
7293         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7294                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7295                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7296                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7297                                                 g_cfg->hash_func);
7298                 return -EINVAL;
7299         }
7300
7301         /*
7302          * As i40e supports less than 32 flow types, only first 32 bits need to
7303          * be checked.
7304          */
7305         mask0 = g_cfg->valid_bit_mask[0];
7306         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7307                 if (i == 0) {
7308                         /* Check if any unsupported flow type configured */
7309                         if ((mask0 | i40e_mask) ^ i40e_mask)
7310                                 goto mask_err;
7311                 } else {
7312                         if (g_cfg->valid_bit_mask[i])
7313                                 goto mask_err;
7314                 }
7315         }
7316
7317         return 0;
7318
7319 mask_err:
7320         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7321
7322         return -EINVAL;
7323 }
7324
7325 /*
7326  * Set global configurations of hash function type and symmetric hash enable
7327  * per flow type (pctype). Note any modifying global configuration will affect
7328  * all the ports on the same NIC.
7329  */
7330 static int
7331 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7332                                    struct rte_eth_hash_global_conf *g_cfg)
7333 {
7334         int ret;
7335         uint16_t i;
7336         uint32_t reg;
7337         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7338         enum i40e_filter_pctype pctype;
7339
7340         /* Check the input parameters */
7341         ret = i40e_hash_global_config_check(g_cfg);
7342         if (ret < 0)
7343                 return ret;
7344
7345         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7346                 if (!(mask0 & (1UL << i)))
7347                         continue;
7348                 mask0 &= ~(1UL << i);
7349                 /* if flowtype is invalid, continue */
7350                 if (!I40E_VALID_FLOW(i))
7351                         continue;
7352                 pctype = i40e_flowtype_to_pctype(i);
7353                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7354                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7355                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7356         }
7357
7358         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7359         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7360                 /* Toeplitz */
7361                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7362                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7363                                                                 "Toeplitz");
7364                         goto out;
7365                 }
7366                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7367         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7368                 /* Simple XOR */
7369                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7370                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7371                                                         "Simple XOR");
7372                         goto out;
7373                 }
7374                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7375         } else
7376                 /* Use the default, and keep it as it is */
7377                 goto out;
7378
7379         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7380
7381 out:
7382         I40E_WRITE_FLUSH(hw);
7383
7384         return 0;
7385 }
7386
7387 /**
7388  * Valid input sets for hash and flow director filters per PCTYPE
7389  */
7390 static uint64_t
7391 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7392                 enum rte_filter_type filter)
7393 {
7394         uint64_t valid;
7395
7396         static const uint64_t valid_hash_inset_table[] = {
7397                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7398                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7399                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7400                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7401                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7402                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7403                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7404                         I40E_INSET_FLEX_PAYLOAD,
7405                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7406                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7407                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7408                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7409                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7410                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7411                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7412                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7413                         I40E_INSET_FLEX_PAYLOAD,
7414                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7415                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7416                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7417                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7418                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7419                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7420                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7421                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7422                         I40E_INSET_FLEX_PAYLOAD,
7423                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7424                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7425                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7426                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7427                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7428                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7429                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7430                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7431                         I40E_INSET_FLEX_PAYLOAD,
7432                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7433                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7434                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7435                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7436                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7437                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7438                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7439                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7440                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7441                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7442                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7443                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7444                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7445                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7446                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7447                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7448                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7449                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7450                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7451                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7452                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7453                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7454                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7455                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7456                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7457                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7458                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7459                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7460                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7461                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7462                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7463                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7464                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7465                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7466                         I40E_INSET_FLEX_PAYLOAD,
7467                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7468                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7469                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7470                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7471                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7472                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7473                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7474                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7475                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7476                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7477                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7478                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7479                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7480                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7481                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7482                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7483                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7484                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7485                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7486                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7487                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7488                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7489                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7490                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7491                         I40E_INSET_FLEX_PAYLOAD,
7492                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7493                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7494                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7495                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7496                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7497                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7498                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7499                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7500                         I40E_INSET_FLEX_PAYLOAD,
7501                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7502                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7503                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7504                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7505                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7506                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7507                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7508                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7509                         I40E_INSET_FLEX_PAYLOAD,
7510                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7511                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7512                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7513                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7514                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7515                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7516                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7517                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7518                         I40E_INSET_FLEX_PAYLOAD,
7519                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7520                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7521                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7522                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7523                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7524                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7525                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7526                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7527                         I40E_INSET_FLEX_PAYLOAD,
7528                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7529                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7530                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7531                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7532                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7533                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7534                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7535                         I40E_INSET_FLEX_PAYLOAD,
7536                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7537                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7538                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7539                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7540                         I40E_INSET_FLEX_PAYLOAD,
7541         };
7542
7543         /**
7544          * Flow director supports only fields defined in
7545          * union rte_eth_fdir_flow.
7546          */
7547         static const uint64_t valid_fdir_inset_table[] = {
7548                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7549                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7550                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7551                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7552                 I40E_INSET_IPV4_TTL,
7553                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7554                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7555                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7556                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7557                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7558                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7559                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7560                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7561                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7562                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7563                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7564                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7565                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7566                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7567                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7568                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7569                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7570                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7571                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7572                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7573                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7574                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7575                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7576                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7577                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7578                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7579                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7580                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7581                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7582                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7583                 I40E_INSET_SCTP_VT,
7584                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7585                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7587                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7588                 I40E_INSET_IPV4_TTL,
7589                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7590                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7591                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7592                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7593                 I40E_INSET_IPV6_HOP_LIMIT,
7594                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7595                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7596                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7597                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7598                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7599                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7600                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7601                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7602                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7603                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7604                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7605                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7606                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7607                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7608                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7609                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7610                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7611                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7612                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7613                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7614                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7615                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7616                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7617                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7618                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7619                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7620                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7621                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7622                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7623                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7624                 I40E_INSET_SCTP_VT,
7625                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7626                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7627                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7628                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7629                 I40E_INSET_IPV6_HOP_LIMIT,
7630                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7631                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                 I40E_INSET_LAST_ETHER_TYPE,
7633         };
7634
7635         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7636                 return 0;
7637         if (filter == RTE_ETH_FILTER_HASH)
7638                 valid = valid_hash_inset_table[pctype];
7639         else
7640                 valid = valid_fdir_inset_table[pctype];
7641
7642         return valid;
7643 }
7644
7645 /**
7646  * Validate if the input set is allowed for a specific PCTYPE
7647  */
7648 static int
7649 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7650                 enum rte_filter_type filter, uint64_t inset)
7651 {
7652         uint64_t valid;
7653
7654         valid = i40e_get_valid_input_set(pctype, filter);
7655         if (inset & (~valid))
7656                 return -EINVAL;
7657
7658         return 0;
7659 }
7660
7661 /* default input set fields combination per pctype */
7662 static uint64_t
7663 i40e_get_default_input_set(uint16_t pctype)
7664 {
7665         static const uint64_t default_inset_table[] = {
7666                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7667                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7668                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7669                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7670                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7671                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7672                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7673                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7674                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7675                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7676                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7677                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7678                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7679                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7680                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7681                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7682                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7683                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7684                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7685                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7686                         I40E_INSET_SCTP_VT,
7687                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7688                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7689                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7690                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7691                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7692                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7693                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7694                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7695                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7696                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7697                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7698                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7699                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7700                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7701                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7702                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7703                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7704                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7705                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7706                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7707                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7708                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7709                         I40E_INSET_SCTP_VT,
7710                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7711                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7712                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7713                         I40E_INSET_LAST_ETHER_TYPE,
7714         };
7715
7716         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7717                 return 0;
7718
7719         return default_inset_table[pctype];
7720 }
7721
7722 /**
7723  * Parse the input set from index to logical bit masks
7724  */
7725 static int
7726 i40e_parse_input_set(uint64_t *inset,
7727                      enum i40e_filter_pctype pctype,
7728                      enum rte_eth_input_set_field *field,
7729                      uint16_t size)
7730 {
7731         uint16_t i, j;
7732         int ret = -EINVAL;
7733
7734         static const struct {
7735                 enum rte_eth_input_set_field field;
7736                 uint64_t inset;
7737         } inset_convert_table[] = {
7738                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7739                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7740                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7741                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7742                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7743                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7744                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7745                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7746                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7747                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7748                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7749                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7750                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7751                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7752                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7753                         I40E_INSET_IPV6_NEXT_HDR},
7754                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7755                         I40E_INSET_IPV6_HOP_LIMIT},
7756                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7757                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7758                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7759                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7760                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7761                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7762                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7763                         I40E_INSET_SCTP_VT},
7764                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7765                         I40E_INSET_TUNNEL_DMAC},
7766                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7767                         I40E_INSET_VLAN_TUNNEL},
7768                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7769                         I40E_INSET_TUNNEL_ID},
7770                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7771                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7772                         I40E_INSET_FLEX_PAYLOAD_W1},
7773                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7774                         I40E_INSET_FLEX_PAYLOAD_W2},
7775                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7776                         I40E_INSET_FLEX_PAYLOAD_W3},
7777                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7778                         I40E_INSET_FLEX_PAYLOAD_W4},
7779                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7780                         I40E_INSET_FLEX_PAYLOAD_W5},
7781                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7782                         I40E_INSET_FLEX_PAYLOAD_W6},
7783                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7784                         I40E_INSET_FLEX_PAYLOAD_W7},
7785                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7786                         I40E_INSET_FLEX_PAYLOAD_W8},
7787         };
7788
7789         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7790                 return ret;
7791
7792         /* Only one item allowed for default or all */
7793         if (size == 1) {
7794                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7795                         *inset = i40e_get_default_input_set(pctype);
7796                         return 0;
7797                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7798                         *inset = I40E_INSET_NONE;
7799                         return 0;
7800                 }
7801         }
7802
7803         for (i = 0, *inset = 0; i < size; i++) {
7804                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7805                         if (field[i] == inset_convert_table[j].field) {
7806                                 *inset |= inset_convert_table[j].inset;
7807                                 break;
7808                         }
7809                 }
7810
7811                 /* It contains unsupported input set, return immediately */
7812                 if (j == RTE_DIM(inset_convert_table))
7813                         return ret;
7814         }
7815
7816         return 0;
7817 }
7818
7819 /**
7820  * Translate the input set from bit masks to register aware bit masks
7821  * and vice versa
7822  */
7823 static uint64_t
7824 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7825 {
7826         uint64_t val = 0;
7827         uint16_t i;
7828
7829         struct inset_map {
7830                 uint64_t inset;
7831                 uint64_t inset_reg;
7832         };
7833
7834         static const struct inset_map inset_map_common[] = {
7835                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7836                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7837                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7838                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7839                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7840                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7841                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7842                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7843                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7844                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7845                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7846                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7847                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7848                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7849                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7850                 {I40E_INSET_TUNNEL_DMAC,
7851                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7852                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7853                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7854                 {I40E_INSET_TUNNEL_SRC_PORT,
7855                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7856                 {I40E_INSET_TUNNEL_DST_PORT,
7857                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7858                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7859                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7860                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7861                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7862                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7863                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7864                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7865                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7866                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7867         };
7868
7869     /* some different registers map in x722*/
7870         static const struct inset_map inset_map_diff_x722[] = {
7871                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7872                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7873                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7874                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7875         };
7876
7877         static const struct inset_map inset_map_diff_not_x722[] = {
7878                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7879                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7880                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7881                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7882         };
7883
7884         if (input == 0)
7885                 return val;
7886
7887         /* Translate input set to register aware inset */
7888         if (type == I40E_MAC_X722) {
7889                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7890                         if (input & inset_map_diff_x722[i].inset)
7891                                 val |= inset_map_diff_x722[i].inset_reg;
7892                 }
7893         } else {
7894                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7895                         if (input & inset_map_diff_not_x722[i].inset)
7896                                 val |= inset_map_diff_not_x722[i].inset_reg;
7897                 }
7898         }
7899
7900         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7901                 if (input & inset_map_common[i].inset)
7902                         val |= inset_map_common[i].inset_reg;
7903         }
7904
7905         return val;
7906 }
7907
7908 static int
7909 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7910 {
7911         uint8_t i, idx = 0;
7912         uint64_t inset_need_mask = inset;
7913
7914         static const struct {
7915                 uint64_t inset;
7916                 uint32_t mask;
7917         } inset_mask_map[] = {
7918                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7919                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7920                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7921                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7922                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7923                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7924                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7925                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7926         };
7927
7928         if (!inset || !mask || !nb_elem)
7929                 return 0;
7930
7931         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7932                 /* Clear the inset bit, if no MASK is required,
7933                  * for example proto + ttl
7934                  */
7935                 if ((inset & inset_mask_map[i].inset) ==
7936                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7937                         inset_need_mask &= ~inset_mask_map[i].inset;
7938                 if (!inset_need_mask)
7939                         return 0;
7940         }
7941         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7942                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7943                     inset_mask_map[i].inset) {
7944                         if (idx >= nb_elem) {
7945                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7946                                 return -EINVAL;
7947                         }
7948                         mask[idx] = inset_mask_map[i].mask;
7949                         idx++;
7950                 }
7951         }
7952
7953         return idx;
7954 }
7955
7956 static void
7957 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7958 {
7959         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7960
7961         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7962         if (reg != val)
7963                 i40e_write_rx_ctl(hw, addr, val);
7964         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7965                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7966 }
7967
7968 static void
7969 i40e_filter_input_set_init(struct i40e_pf *pf)
7970 {
7971         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7972         enum i40e_filter_pctype pctype;
7973         uint64_t input_set, inset_reg;
7974         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7975         int num, i;
7976
7977         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7978              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7979                 if (hw->mac.type == I40E_MAC_X722) {
7980                         if (!I40E_VALID_PCTYPE_X722(pctype))
7981                                 continue;
7982                 } else {
7983                         if (!I40E_VALID_PCTYPE(pctype))
7984                                 continue;
7985                 }
7986
7987                 input_set = i40e_get_default_input_set(pctype);
7988
7989                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7990                                                    I40E_INSET_MASK_NUM_REG);
7991                 if (num < 0)
7992                         return;
7993                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7994                                         input_set);
7995
7996                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7997                                       (uint32_t)(inset_reg & UINT32_MAX));
7998                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7999                                      (uint32_t)((inset_reg >>
8000                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8001                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8002                                       (uint32_t)(inset_reg & UINT32_MAX));
8003                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8004                                      (uint32_t)((inset_reg >>
8005                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8006
8007                 for (i = 0; i < num; i++) {
8008                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8009                                              mask_reg[i]);
8010                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8011                                              mask_reg[i]);
8012                 }
8013                 /*clear unused mask registers of the pctype */
8014                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8015                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8016                                              0);
8017                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8018                                              0);
8019                 }
8020                 I40E_WRITE_FLUSH(hw);
8021
8022                 /* store the default input set */
8023                 pf->hash_input_set[pctype] = input_set;
8024                 pf->fdir.input_set[pctype] = input_set;
8025         }
8026 }
8027
8028 int
8029 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8030                          struct rte_eth_input_set_conf *conf)
8031 {
8032         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8033         enum i40e_filter_pctype pctype;
8034         uint64_t input_set, inset_reg = 0;
8035         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8036         int ret, i, num;
8037
8038         if (!conf) {
8039                 PMD_DRV_LOG(ERR, "Invalid pointer");
8040                 return -EFAULT;
8041         }
8042         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8043             conf->op != RTE_ETH_INPUT_SET_ADD) {
8044                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8045                 return -EINVAL;
8046         }
8047
8048         if (!I40E_VALID_FLOW(conf->flow_type)) {
8049                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8050                 return -EINVAL;
8051         }
8052
8053         if (hw->mac.type == I40E_MAC_X722) {
8054                 /* get translated pctype value in fd pctype register */
8055                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8056                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8057                         conf->flow_type)));
8058         } else
8059                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8060
8061         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8062                                    conf->inset_size);
8063         if (ret) {
8064                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8065                 return -EINVAL;
8066         }
8067         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8068                                     input_set) != 0) {
8069                 PMD_DRV_LOG(ERR, "Invalid input set");
8070                 return -EINVAL;
8071         }
8072         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8073                 /* get inset value in register */
8074                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8075                 inset_reg <<= I40E_32_BIT_WIDTH;
8076                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8077                 input_set |= pf->hash_input_set[pctype];
8078         }
8079         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8080                                            I40E_INSET_MASK_NUM_REG);
8081         if (num < 0)
8082                 return -EINVAL;
8083
8084         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8085
8086         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8087                               (uint32_t)(inset_reg & UINT32_MAX));
8088         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8089                              (uint32_t)((inset_reg >>
8090                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8091
8092         for (i = 0; i < num; i++)
8093                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8094                                      mask_reg[i]);
8095         /*clear unused mask registers of the pctype */
8096         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8097                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8098                                      0);
8099         I40E_WRITE_FLUSH(hw);
8100
8101         pf->hash_input_set[pctype] = input_set;
8102         return 0;
8103 }
8104
8105 int
8106 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8107                          struct rte_eth_input_set_conf *conf)
8108 {
8109         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8110         enum i40e_filter_pctype pctype;
8111         uint64_t input_set, inset_reg = 0;
8112         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8113         int ret, i, num;
8114
8115         if (!hw || !conf) {
8116                 PMD_DRV_LOG(ERR, "Invalid pointer");
8117                 return -EFAULT;
8118         }
8119         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8120             conf->op != RTE_ETH_INPUT_SET_ADD) {
8121                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8122                 return -EINVAL;
8123         }
8124
8125         if (!I40E_VALID_FLOW(conf->flow_type)) {
8126                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8127                 return -EINVAL;
8128         }
8129
8130         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8131
8132         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8133                                    conf->inset_size);
8134         if (ret) {
8135                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8136                 return -EINVAL;
8137         }
8138         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8139                                     input_set) != 0) {
8140                 PMD_DRV_LOG(ERR, "Invalid input set");
8141                 return -EINVAL;
8142         }
8143
8144         /* get inset value in register */
8145         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8146         inset_reg <<= I40E_32_BIT_WIDTH;
8147         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8148
8149         /* Can not change the inset reg for flex payload for fdir,
8150          * it is done by writing I40E_PRTQF_FD_FLXINSET
8151          * in i40e_set_flex_mask_on_pctype.
8152          */
8153         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8154                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8155         else
8156                 input_set |= pf->fdir.input_set[pctype];
8157         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8158                                            I40E_INSET_MASK_NUM_REG);
8159         if (num < 0)
8160                 return -EINVAL;
8161
8162         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8163
8164         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8165                               (uint32_t)(inset_reg & UINT32_MAX));
8166         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8167                              (uint32_t)((inset_reg >>
8168                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8169
8170         for (i = 0; i < num; i++)
8171                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8172                                      mask_reg[i]);
8173         /*clear unused mask registers of the pctype */
8174         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8175                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8176                                      0);
8177         I40E_WRITE_FLUSH(hw);
8178
8179         pf->fdir.input_set[pctype] = input_set;
8180         return 0;
8181 }
8182
8183 static int
8184 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8185 {
8186         int ret = 0;
8187
8188         if (!hw || !info) {
8189                 PMD_DRV_LOG(ERR, "Invalid pointer");
8190                 return -EFAULT;
8191         }
8192
8193         switch (info->info_type) {
8194         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8195                 i40e_get_symmetric_hash_enable_per_port(hw,
8196                                         &(info->info.enable));
8197                 break;
8198         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8199                 ret = i40e_get_hash_filter_global_config(hw,
8200                                 &(info->info.global_conf));
8201                 break;
8202         default:
8203                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8204                                                         info->info_type);
8205                 ret = -EINVAL;
8206                 break;
8207         }
8208
8209         return ret;
8210 }
8211
8212 static int
8213 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8214 {
8215         int ret = 0;
8216
8217         if (!hw || !info) {
8218                 PMD_DRV_LOG(ERR, "Invalid pointer");
8219                 return -EFAULT;
8220         }
8221
8222         switch (info->info_type) {
8223         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8224                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8225                 break;
8226         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8227                 ret = i40e_set_hash_filter_global_config(hw,
8228                                 &(info->info.global_conf));
8229                 break;
8230         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8231                 ret = i40e_hash_filter_inset_select(hw,
8232                                                &(info->info.input_set_conf));
8233                 break;
8234
8235         default:
8236                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8237                                                         info->info_type);
8238                 ret = -EINVAL;
8239                 break;
8240         }
8241
8242         return ret;
8243 }
8244
8245 /* Operations for hash function */
8246 static int
8247 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8248                       enum rte_filter_op filter_op,
8249                       void *arg)
8250 {
8251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8252         int ret = 0;
8253
8254         switch (filter_op) {
8255         case RTE_ETH_FILTER_NOP:
8256                 break;
8257         case RTE_ETH_FILTER_GET:
8258                 ret = i40e_hash_filter_get(hw,
8259                         (struct rte_eth_hash_filter_info *)arg);
8260                 break;
8261         case RTE_ETH_FILTER_SET:
8262                 ret = i40e_hash_filter_set(hw,
8263                         (struct rte_eth_hash_filter_info *)arg);
8264                 break;
8265         default:
8266                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8267                                                                 filter_op);
8268                 ret = -ENOTSUP;
8269                 break;
8270         }
8271
8272         return ret;
8273 }
8274
8275 /* Convert ethertype filter structure */
8276 static int
8277 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8278                               struct i40e_ethertype_filter *filter)
8279 {
8280         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8281         filter->input.ether_type = input->ether_type;
8282         filter->flags = input->flags;
8283         filter->queue = input->queue;
8284
8285         return 0;
8286 }
8287
8288 /* Check if there exists the ehtertype filter */
8289 struct i40e_ethertype_filter *
8290 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8291                                 const struct i40e_ethertype_filter_input *input)
8292 {
8293         int ret;
8294
8295         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8296         if (ret < 0)
8297                 return NULL;
8298
8299         return ethertype_rule->hash_map[ret];
8300 }
8301
8302 /* Add ethertype filter in SW list */
8303 static int
8304 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8305                                 struct i40e_ethertype_filter *filter)
8306 {
8307         struct i40e_ethertype_rule *rule = &pf->ethertype;
8308         int ret;
8309
8310         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8311         if (ret < 0) {
8312                 PMD_DRV_LOG(ERR,
8313                             "Failed to insert ethertype filter"
8314                             " to hash table %d!",
8315                             ret);
8316                 return ret;
8317         }
8318         rule->hash_map[ret] = filter;
8319
8320         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8321
8322         return 0;
8323 }
8324
8325 /* Delete ethertype filter in SW list */
8326 int
8327 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8328                              struct i40e_ethertype_filter_input *input)
8329 {
8330         struct i40e_ethertype_rule *rule = &pf->ethertype;
8331         struct i40e_ethertype_filter *filter;
8332         int ret;
8333
8334         ret = rte_hash_del_key(rule->hash_table, input);
8335         if (ret < 0) {
8336                 PMD_DRV_LOG(ERR,
8337                             "Failed to delete ethertype filter"
8338                             " to hash table %d!",
8339                             ret);
8340                 return ret;
8341         }
8342         filter = rule->hash_map[ret];
8343         rule->hash_map[ret] = NULL;
8344
8345         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8346         rte_free(filter);
8347
8348         return 0;
8349 }
8350
8351 /*
8352  * Configure ethertype filter, which can director packet by filtering
8353  * with mac address and ether_type or only ether_type
8354  */
8355 static int
8356 i40e_ethertype_filter_set(struct i40e_pf *pf,
8357                         struct rte_eth_ethertype_filter *filter,
8358                         bool add)
8359 {
8360         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8361         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8362         struct i40e_ethertype_filter *ethertype_filter, *node;
8363         struct i40e_ethertype_filter check_filter;
8364         struct i40e_control_filter_stats stats;
8365         uint16_t flags = 0;
8366         int ret;
8367
8368         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8369                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8370                 return -EINVAL;
8371         }
8372         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8373                 filter->ether_type == ETHER_TYPE_IPv6) {
8374                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8375                         " control packet filter.", filter->ether_type);
8376                 return -EINVAL;
8377         }
8378         if (filter->ether_type == ETHER_TYPE_VLAN)
8379                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8380                         " not supported.");
8381
8382         /* Check if there is the filter in SW list */
8383         memset(&check_filter, 0, sizeof(check_filter));
8384         i40e_ethertype_filter_convert(filter, &check_filter);
8385         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8386                                                &check_filter.input);
8387         if (add && node) {
8388                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8389                 return -EINVAL;
8390         }
8391
8392         if (!add && !node) {
8393                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8394                 return -EINVAL;
8395         }
8396
8397         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8398                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8399         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8400                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8401         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8402
8403         memset(&stats, 0, sizeof(stats));
8404         ret = i40e_aq_add_rem_control_packet_filter(hw,
8405                         filter->mac_addr.addr_bytes,
8406                         filter->ether_type, flags,
8407                         pf->main_vsi->seid,
8408                         filter->queue, add, &stats, NULL);
8409
8410         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8411                          " mac_etype_used = %u, etype_used = %u,"
8412                          " mac_etype_free = %u, etype_free = %u\n",
8413                          ret, stats.mac_etype_used, stats.etype_used,
8414                          stats.mac_etype_free, stats.etype_free);
8415         if (ret < 0)
8416                 return -ENOSYS;
8417
8418         /* Add or delete a filter in SW list */
8419         if (add) {
8420                 ethertype_filter = rte_zmalloc("ethertype_filter",
8421                                        sizeof(*ethertype_filter), 0);
8422                 rte_memcpy(ethertype_filter, &check_filter,
8423                            sizeof(check_filter));
8424                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8425         } else {
8426                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8427         }
8428
8429         return ret;
8430 }
8431
8432 /*
8433  * Handle operations for ethertype filter.
8434  */
8435 static int
8436 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8437                                 enum rte_filter_op filter_op,
8438                                 void *arg)
8439 {
8440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8441         int ret = 0;
8442
8443         if (filter_op == RTE_ETH_FILTER_NOP)
8444                 return ret;
8445
8446         if (arg == NULL) {
8447                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8448                             filter_op);
8449                 return -EINVAL;
8450         }
8451
8452         switch (filter_op) {
8453         case RTE_ETH_FILTER_ADD:
8454                 ret = i40e_ethertype_filter_set(pf,
8455                         (struct rte_eth_ethertype_filter *)arg,
8456                         TRUE);
8457                 break;
8458         case RTE_ETH_FILTER_DELETE:
8459                 ret = i40e_ethertype_filter_set(pf,
8460                         (struct rte_eth_ethertype_filter *)arg,
8461                         FALSE);
8462                 break;
8463         default:
8464                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8465                 ret = -ENOSYS;
8466                 break;
8467         }
8468         return ret;
8469 }
8470
8471 static int
8472 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8473                      enum rte_filter_type filter_type,
8474                      enum rte_filter_op filter_op,
8475                      void *arg)
8476 {
8477         int ret = 0;
8478
8479         if (dev == NULL)
8480                 return -EINVAL;
8481
8482         switch (filter_type) {
8483         case RTE_ETH_FILTER_NONE:
8484                 /* For global configuration */
8485                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8486                 break;
8487         case RTE_ETH_FILTER_HASH:
8488                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8489                 break;
8490         case RTE_ETH_FILTER_MACVLAN:
8491                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8492                 break;
8493         case RTE_ETH_FILTER_ETHERTYPE:
8494                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8495                 break;
8496         case RTE_ETH_FILTER_TUNNEL:
8497                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8498                 break;
8499         case RTE_ETH_FILTER_FDIR:
8500                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8501                 break;
8502         default:
8503                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8504                                                         filter_type);
8505                 ret = -EINVAL;
8506                 break;
8507         }
8508
8509         return ret;
8510 }
8511
8512 /*
8513  * Check and enable Extended Tag.
8514  * Enabling Extended Tag is important for 40G performance.
8515  */
8516 static void
8517 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8518 {
8519         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8520         uint32_t buf = 0;
8521         int ret;
8522
8523         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8524                                       PCI_DEV_CAP_REG);
8525         if (ret < 0) {
8526                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8527                             PCI_DEV_CAP_REG);
8528                 return;
8529         }
8530         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8531                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8532                 return;
8533         }
8534
8535         buf = 0;
8536         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8537                                       PCI_DEV_CTRL_REG);
8538         if (ret < 0) {
8539                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8540                             PCI_DEV_CTRL_REG);
8541                 return;
8542         }
8543         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8544                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8545                 return;
8546         }
8547         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8548         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8549                                        PCI_DEV_CTRL_REG);
8550         if (ret < 0) {
8551                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8552                             PCI_DEV_CTRL_REG);
8553                 return;
8554         }
8555 }
8556
8557 /*
8558  * As some registers wouldn't be reset unless a global hardware reset,
8559  * hardware initialization is needed to put those registers into an
8560  * expected initial state.
8561  */
8562 static void
8563 i40e_hw_init(struct rte_eth_dev *dev)
8564 {
8565         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8566
8567         i40e_enable_extended_tag(dev);
8568
8569         /* clear the PF Queue Filter control register */
8570         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8571
8572         /* Disable symmetric hash per port */
8573         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8574 }
8575
8576 enum i40e_filter_pctype
8577 i40e_flowtype_to_pctype(uint16_t flow_type)
8578 {
8579         static const enum i40e_filter_pctype pctype_table[] = {
8580                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8581                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8582                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8583                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8584                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8585                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8586                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8587                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8588                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8589                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8590                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8591                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8592                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8593                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8594                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8595                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8596                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8597                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8598                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8599         };
8600
8601         return pctype_table[flow_type];
8602 }
8603
8604 uint16_t
8605 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8606 {
8607         static const uint16_t flowtype_table[] = {
8608                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8609                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8610                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8611                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8612                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8613                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8614                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8615                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8616                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8617                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8618                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8619                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8620                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8621                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8622                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8623                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8624                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8625                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8626                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8627                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8628                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8629                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8630                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8631                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8632                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8633                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8634                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8635                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8636                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8637                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8638                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8639         };
8640
8641         return flowtype_table[pctype];
8642 }
8643
8644 /*
8645  * On X710, performance number is far from the expectation on recent firmware
8646  * versions; on XL710, performance number is also far from the expectation on
8647  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8648  * mode is enabled and port MAC address is equal to the packet destination MAC
8649  * address. The fix for this issue may not be integrated in the following
8650  * firmware version. So the workaround in software driver is needed. It needs
8651  * to modify the initial values of 3 internal only registers for both X710 and
8652  * XL710. Note that the values for X710 or XL710 could be different, and the
8653  * workaround can be removed when it is fixed in firmware in the future.
8654  */
8655
8656 /* For both X710 and XL710 */
8657 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8658 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8659
8660 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8661 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8662
8663 /* For X710 */
8664 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8665 /* For XL710 */
8666 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8667 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8668
8669 static int
8670 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8671 {
8672         enum i40e_status_code status;
8673         struct i40e_aq_get_phy_abilities_resp phy_ab;
8674         int ret = -ENOTSUP;
8675
8676         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8677                                               NULL);
8678
8679         if (status)
8680                 return ret;
8681
8682         return 0;
8683 }
8684
8685
8686 static void
8687 i40e_configure_registers(struct i40e_hw *hw)
8688 {
8689         static struct {
8690                 uint32_t addr;
8691                 uint64_t val;
8692         } reg_table[] = {
8693                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8694                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8695                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8696         };
8697         uint64_t reg;
8698         uint32_t i;
8699         int ret;
8700
8701         for (i = 0; i < RTE_DIM(reg_table); i++) {
8702                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8703                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8704                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8705                                 reg_table[i].val =
8706                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8707                         else /* For X710 */
8708                                 reg_table[i].val =
8709                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8710                 }
8711
8712                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8713                                                         &reg, NULL);
8714                 if (ret < 0) {
8715                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8716                                                         reg_table[i].addr);
8717                         break;
8718                 }
8719                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8720                                                 reg_table[i].addr, reg);
8721                 if (reg == reg_table[i].val)
8722                         continue;
8723
8724                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8725                                                 reg_table[i].val, NULL);
8726                 if (ret < 0) {
8727                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8728                                 "address of 0x%"PRIx32, reg_table[i].val,
8729                                                         reg_table[i].addr);
8730                         break;
8731                 }
8732                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8733                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8734         }
8735 }
8736
8737 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8738 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8739 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8740 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8741 static int
8742 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8743 {
8744         uint32_t reg;
8745         int ret;
8746
8747         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8748                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8749                 return -EINVAL;
8750         }
8751
8752         /* Configure for double VLAN RX stripping */
8753         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8754         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8755                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8756                 ret = i40e_aq_debug_write_register(hw,
8757                                                    I40E_VSI_TSR(vsi->vsi_id),
8758                                                    reg, NULL);
8759                 if (ret < 0) {
8760                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8761                                     vsi->vsi_id);
8762                         return I40E_ERR_CONFIG;
8763                 }
8764         }
8765
8766         /* Configure for double VLAN TX insertion */
8767         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8768         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8769                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8770                 ret = i40e_aq_debug_write_register(hw,
8771                                                    I40E_VSI_L2TAGSTXVALID(
8772                                                    vsi->vsi_id), reg, NULL);
8773                 if (ret < 0) {
8774                         PMD_DRV_LOG(ERR, "Failed to update "
8775                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8776                         return I40E_ERR_CONFIG;
8777                 }
8778         }
8779
8780         return 0;
8781 }
8782
8783 /**
8784  * i40e_aq_add_mirror_rule
8785  * @hw: pointer to the hardware structure
8786  * @seid: VEB seid to add mirror rule to
8787  * @dst_id: destination vsi seid
8788  * @entries: Buffer which contains the entities to be mirrored
8789  * @count: number of entities contained in the buffer
8790  * @rule_id:the rule_id of the rule to be added
8791  *
8792  * Add a mirror rule for a given veb.
8793  *
8794  **/
8795 static enum i40e_status_code
8796 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8797                         uint16_t seid, uint16_t dst_id,
8798                         uint16_t rule_type, uint16_t *entries,
8799                         uint16_t count, uint16_t *rule_id)
8800 {
8801         struct i40e_aq_desc desc;
8802         struct i40e_aqc_add_delete_mirror_rule cmd;
8803         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8804                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8805                 &desc.params.raw;
8806         uint16_t buff_len;
8807         enum i40e_status_code status;
8808
8809         i40e_fill_default_direct_cmd_desc(&desc,
8810                                           i40e_aqc_opc_add_mirror_rule);
8811         memset(&cmd, 0, sizeof(cmd));
8812
8813         buff_len = sizeof(uint16_t) * count;
8814         desc.datalen = rte_cpu_to_le_16(buff_len);
8815         if (buff_len > 0)
8816                 desc.flags |= rte_cpu_to_le_16(
8817                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8818         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8819                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8820         cmd.num_entries = rte_cpu_to_le_16(count);
8821         cmd.seid = rte_cpu_to_le_16(seid);
8822         cmd.destination = rte_cpu_to_le_16(dst_id);
8823
8824         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8825         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8826         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8827                          "rule_id = %u"
8828                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8829                          hw->aq.asq_last_status, resp->rule_id,
8830                          resp->mirror_rules_used, resp->mirror_rules_free);
8831         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8832
8833         return status;
8834 }
8835
8836 /**
8837  * i40e_aq_del_mirror_rule
8838  * @hw: pointer to the hardware structure
8839  * @seid: VEB seid to add mirror rule to
8840  * @entries: Buffer which contains the entities to be mirrored
8841  * @count: number of entities contained in the buffer
8842  * @rule_id:the rule_id of the rule to be delete
8843  *
8844  * Delete a mirror rule for a given veb.
8845  *
8846  **/
8847 static enum i40e_status_code
8848 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8849                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8850                 uint16_t count, uint16_t rule_id)
8851 {
8852         struct i40e_aq_desc desc;
8853         struct i40e_aqc_add_delete_mirror_rule cmd;
8854         uint16_t buff_len = 0;
8855         enum i40e_status_code status;
8856         void *buff = NULL;
8857
8858         i40e_fill_default_direct_cmd_desc(&desc,
8859                                           i40e_aqc_opc_delete_mirror_rule);
8860         memset(&cmd, 0, sizeof(cmd));
8861         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8862                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8863                                                           I40E_AQ_FLAG_RD));
8864                 cmd.num_entries = count;
8865                 buff_len = sizeof(uint16_t) * count;
8866                 desc.datalen = rte_cpu_to_le_16(buff_len);
8867                 buff = (void *)entries;
8868         } else
8869                 /* rule id is filled in destination field for deleting mirror rule */
8870                 cmd.destination = rte_cpu_to_le_16(rule_id);
8871
8872         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8873                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8874         cmd.seid = rte_cpu_to_le_16(seid);
8875
8876         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8877         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8878
8879         return status;
8880 }
8881
8882 /**
8883  * i40e_mirror_rule_set
8884  * @dev: pointer to the hardware structure
8885  * @mirror_conf: mirror rule info
8886  * @sw_id: mirror rule's sw_id
8887  * @on: enable/disable
8888  *
8889  * set a mirror rule.
8890  *
8891  **/
8892 static int
8893 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8894                         struct rte_eth_mirror_conf *mirror_conf,
8895                         uint8_t sw_id, uint8_t on)
8896 {
8897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8899         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8900         struct i40e_mirror_rule *parent = NULL;
8901         uint16_t seid, dst_seid, rule_id;
8902         uint16_t i, j = 0;
8903         int ret;
8904
8905         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8906
8907         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8908                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8909                         " without veb or vfs.");
8910                 return -ENOSYS;
8911         }
8912         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8913                 PMD_DRV_LOG(ERR, "mirror table is full.");
8914                 return -ENOSPC;
8915         }
8916         if (mirror_conf->dst_pool > pf->vf_num) {
8917                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8918                                  mirror_conf->dst_pool);
8919                 return -EINVAL;
8920         }
8921
8922         seid = pf->main_vsi->veb->seid;
8923
8924         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8925                 if (sw_id <= it->index) {
8926                         mirr_rule = it;
8927                         break;
8928                 }
8929                 parent = it;
8930         }
8931         if (mirr_rule && sw_id == mirr_rule->index) {
8932                 if (on) {
8933                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8934                         return -EEXIST;
8935                 } else {
8936                         ret = i40e_aq_del_mirror_rule(hw, seid,
8937                                         mirr_rule->rule_type,
8938                                         mirr_rule->entries,
8939                                         mirr_rule->num_entries, mirr_rule->id);
8940                         if (ret < 0) {
8941                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8942                                                    " ret = %d, aq_err = %d.",
8943                                                    ret, hw->aq.asq_last_status);
8944                                 return -ENOSYS;
8945                         }
8946                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8947                         rte_free(mirr_rule);
8948                         pf->nb_mirror_rule--;
8949                         return 0;
8950                 }
8951         } else if (!on) {
8952                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8953                 return -ENOENT;
8954         }
8955
8956         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8957                                 sizeof(struct i40e_mirror_rule) , 0);
8958         if (!mirr_rule) {
8959                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8960                 return I40E_ERR_NO_MEMORY;
8961         }
8962         switch (mirror_conf->rule_type) {
8963         case ETH_MIRROR_VLAN:
8964                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8965                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8966                                 mirr_rule->entries[j] =
8967                                         mirror_conf->vlan.vlan_id[i];
8968                                 j++;
8969                         }
8970                 }
8971                 if (j == 0) {
8972                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8973                         rte_free(mirr_rule);
8974                         return -EINVAL;
8975                 }
8976                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8977                 break;
8978         case ETH_MIRROR_VIRTUAL_POOL_UP:
8979         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8980                 /* check if the specified pool bit is out of range */
8981                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8982                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8983                         rte_free(mirr_rule);
8984                         return -EINVAL;
8985                 }
8986                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8987                         if (mirror_conf->pool_mask & (1ULL << i)) {
8988                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8989                                 j++;
8990                         }
8991                 }
8992                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8993                         /* add pf vsi to entries */
8994                         mirr_rule->entries[j] = pf->main_vsi_seid;
8995                         j++;
8996                 }
8997                 if (j == 0) {
8998                         PMD_DRV_LOG(ERR, "pool is not specified.");
8999                         rte_free(mirr_rule);
9000                         return -EINVAL;
9001                 }
9002                 /* egress and ingress in aq commands means from switch but not port */
9003                 mirr_rule->rule_type =
9004                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9005                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9006                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9007                 break;
9008         case ETH_MIRROR_UPLINK_PORT:
9009                 /* egress and ingress in aq commands means from switch but not port*/
9010                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9011                 break;
9012         case ETH_MIRROR_DOWNLINK_PORT:
9013                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9014                 break;
9015         default:
9016                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9017                         mirror_conf->rule_type);
9018                 rte_free(mirr_rule);
9019                 return -EINVAL;
9020         }
9021
9022         /* If the dst_pool is equal to vf_num, consider it as PF */
9023         if (mirror_conf->dst_pool == pf->vf_num)
9024                 dst_seid = pf->main_vsi_seid;
9025         else
9026                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9027
9028         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9029                                       mirr_rule->rule_type, mirr_rule->entries,
9030                                       j, &rule_id);
9031         if (ret < 0) {
9032                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9033                                    " ret = %d, aq_err = %d.",
9034                                    ret, hw->aq.asq_last_status);
9035                 rte_free(mirr_rule);
9036                 return -ENOSYS;
9037         }
9038
9039         mirr_rule->index = sw_id;
9040         mirr_rule->num_entries = j;
9041         mirr_rule->id = rule_id;
9042         mirr_rule->dst_vsi_seid = dst_seid;
9043
9044         if (parent)
9045                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9046         else
9047                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9048
9049         pf->nb_mirror_rule++;
9050         return 0;
9051 }
9052
9053 /**
9054  * i40e_mirror_rule_reset
9055  * @dev: pointer to the device
9056  * @sw_id: mirror rule's sw_id
9057  *
9058  * reset a mirror rule.
9059  *
9060  **/
9061 static int
9062 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9063 {
9064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9065         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9066         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9067         uint16_t seid;
9068         int ret;
9069
9070         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9071
9072         seid = pf->main_vsi->veb->seid;
9073
9074         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9075                 if (sw_id == it->index) {
9076                         mirr_rule = it;
9077                         break;
9078                 }
9079         }
9080         if (mirr_rule) {
9081                 ret = i40e_aq_del_mirror_rule(hw, seid,
9082                                 mirr_rule->rule_type,
9083                                 mirr_rule->entries,
9084                                 mirr_rule->num_entries, mirr_rule->id);
9085                 if (ret < 0) {
9086                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9087                                            " status = %d, aq_err = %d.",
9088                                            ret, hw->aq.asq_last_status);
9089                         return -ENOSYS;
9090                 }
9091                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9092                 rte_free(mirr_rule);
9093                 pf->nb_mirror_rule--;
9094         } else {
9095                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9096                 return -ENOENT;
9097         }
9098         return 0;
9099 }
9100
9101 static uint64_t
9102 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9103 {
9104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9105         uint64_t systim_cycles;
9106
9107         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9108         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9109                         << 32;
9110
9111         return systim_cycles;
9112 }
9113
9114 static uint64_t
9115 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9116 {
9117         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9118         uint64_t rx_tstamp;
9119
9120         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9121         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9122                         << 32;
9123
9124         return rx_tstamp;
9125 }
9126
9127 static uint64_t
9128 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9129 {
9130         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9131         uint64_t tx_tstamp;
9132
9133         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9134         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9135                         << 32;
9136
9137         return tx_tstamp;
9138 }
9139
9140 static void
9141 i40e_start_timecounters(struct rte_eth_dev *dev)
9142 {
9143         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9144         struct i40e_adapter *adapter =
9145                         (struct i40e_adapter *)dev->data->dev_private;
9146         struct rte_eth_link link;
9147         uint32_t tsync_inc_l;
9148         uint32_t tsync_inc_h;
9149
9150         /* Get current link speed. */
9151         memset(&link, 0, sizeof(link));
9152         i40e_dev_link_update(dev, 1);
9153         rte_i40e_dev_atomic_read_link_status(dev, &link);
9154
9155         switch (link.link_speed) {
9156         case ETH_SPEED_NUM_40G:
9157                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9158                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9159                 break;
9160         case ETH_SPEED_NUM_10G:
9161                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9162                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9163                 break;
9164         case ETH_SPEED_NUM_1G:
9165                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9166                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9167                 break;
9168         default:
9169                 tsync_inc_l = 0x0;
9170                 tsync_inc_h = 0x0;
9171         }
9172
9173         /* Set the timesync increment value. */
9174         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9175         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9176
9177         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9178         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9179         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9180
9181         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9182         adapter->systime_tc.cc_shift = 0;
9183         adapter->systime_tc.nsec_mask = 0;
9184
9185         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9186         adapter->rx_tstamp_tc.cc_shift = 0;
9187         adapter->rx_tstamp_tc.nsec_mask = 0;
9188
9189         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9190         adapter->tx_tstamp_tc.cc_shift = 0;
9191         adapter->tx_tstamp_tc.nsec_mask = 0;
9192 }
9193
9194 static int
9195 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9196 {
9197         struct i40e_adapter *adapter =
9198                         (struct i40e_adapter *)dev->data->dev_private;
9199
9200         adapter->systime_tc.nsec += delta;
9201         adapter->rx_tstamp_tc.nsec += delta;
9202         adapter->tx_tstamp_tc.nsec += delta;
9203
9204         return 0;
9205 }
9206
9207 static int
9208 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9209 {
9210         uint64_t ns;
9211         struct i40e_adapter *adapter =
9212                         (struct i40e_adapter *)dev->data->dev_private;
9213
9214         ns = rte_timespec_to_ns(ts);
9215
9216         /* Set the timecounters to a new value. */
9217         adapter->systime_tc.nsec = ns;
9218         adapter->rx_tstamp_tc.nsec = ns;
9219         adapter->tx_tstamp_tc.nsec = ns;
9220
9221         return 0;
9222 }
9223
9224 static int
9225 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9226 {
9227         uint64_t ns, systime_cycles;
9228         struct i40e_adapter *adapter =
9229                         (struct i40e_adapter *)dev->data->dev_private;
9230
9231         systime_cycles = i40e_read_systime_cyclecounter(dev);
9232         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9233         *ts = rte_ns_to_timespec(ns);
9234
9235         return 0;
9236 }
9237
9238 static int
9239 i40e_timesync_enable(struct rte_eth_dev *dev)
9240 {
9241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9242         uint32_t tsync_ctl_l;
9243         uint32_t tsync_ctl_h;
9244
9245         /* Stop the timesync system time. */
9246         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9247         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9248         /* Reset the timesync system time value. */
9249         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9250         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9251
9252         i40e_start_timecounters(dev);
9253
9254         /* Clear timesync registers. */
9255         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9256         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9257         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9258         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9259         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9260         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9261
9262         /* Enable timestamping of PTP packets. */
9263         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9264         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9265
9266         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9267         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9268         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9269
9270         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9271         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9272
9273         return 0;
9274 }
9275
9276 static int
9277 i40e_timesync_disable(struct rte_eth_dev *dev)
9278 {
9279         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9280         uint32_t tsync_ctl_l;
9281         uint32_t tsync_ctl_h;
9282
9283         /* Disable timestamping of transmitted PTP packets. */
9284         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9285         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9286
9287         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9288         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9289
9290         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9291         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9292
9293         /* Reset the timesync increment value. */
9294         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9295         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9296
9297         return 0;
9298 }
9299
9300 static int
9301 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9302                                 struct timespec *timestamp, uint32_t flags)
9303 {
9304         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9305         struct i40e_adapter *adapter =
9306                 (struct i40e_adapter *)dev->data->dev_private;
9307
9308         uint32_t sync_status;
9309         uint32_t index = flags & 0x03;
9310         uint64_t rx_tstamp_cycles;
9311         uint64_t ns;
9312
9313         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9314         if ((sync_status & (1 << index)) == 0)
9315                 return -EINVAL;
9316
9317         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9318         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9319         *timestamp = rte_ns_to_timespec(ns);
9320
9321         return 0;
9322 }
9323
9324 static int
9325 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9326                                 struct timespec *timestamp)
9327 {
9328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9329         struct i40e_adapter *adapter =
9330                 (struct i40e_adapter *)dev->data->dev_private;
9331
9332         uint32_t sync_status;
9333         uint64_t tx_tstamp_cycles;
9334         uint64_t ns;
9335
9336         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9337         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9338                 return -EINVAL;
9339
9340         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9341         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9342         *timestamp = rte_ns_to_timespec(ns);
9343
9344         return 0;
9345 }
9346
9347 /*
9348  * i40e_parse_dcb_configure - parse dcb configure from user
9349  * @dev: the device being configured
9350  * @dcb_cfg: pointer of the result of parse
9351  * @*tc_map: bit map of enabled traffic classes
9352  *
9353  * Returns 0 on success, negative value on failure
9354  */
9355 static int
9356 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9357                          struct i40e_dcbx_config *dcb_cfg,
9358                          uint8_t *tc_map)
9359 {
9360         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9361         uint8_t i, tc_bw, bw_lf;
9362
9363         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9364
9365         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9366         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9367                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9368                 return -EINVAL;
9369         }
9370
9371         /* assume each tc has the same bw */
9372         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9373         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9374                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9375         /* to ensure the sum of tcbw is equal to 100 */
9376         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9377         for (i = 0; i < bw_lf; i++)
9378                 dcb_cfg->etscfg.tcbwtable[i]++;
9379
9380         /* assume each tc has the same Transmission Selection Algorithm */
9381         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9382                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9383
9384         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9385                 dcb_cfg->etscfg.prioritytable[i] =
9386                                 dcb_rx_conf->dcb_tc[i];
9387
9388         /* FW needs one App to configure HW */
9389         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9390         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9391         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9392         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9393
9394         if (dcb_rx_conf->nb_tcs == 0)
9395                 *tc_map = 1; /* tc0 only */
9396         else
9397                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9398
9399         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9400                 dcb_cfg->pfc.willing = 0;
9401                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9402                 dcb_cfg->pfc.pfcenable = *tc_map;
9403         }
9404         return 0;
9405 }
9406
9407
9408 static enum i40e_status_code
9409 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9410                               struct i40e_aqc_vsi_properties_data *info,
9411                               uint8_t enabled_tcmap)
9412 {
9413         enum i40e_status_code ret;
9414         int i, total_tc = 0;
9415         uint16_t qpnum_per_tc, bsf, qp_idx;
9416         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9417         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9418         uint16_t used_queues;
9419
9420         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9421         if (ret != I40E_SUCCESS)
9422                 return ret;
9423
9424         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9425                 if (enabled_tcmap & (1 << i))
9426                         total_tc++;
9427         }
9428         if (total_tc == 0)
9429                 total_tc = 1;
9430         vsi->enabled_tc = enabled_tcmap;
9431
9432         /* different VSI has different queues assigned */
9433         if (vsi->type == I40E_VSI_MAIN)
9434                 used_queues = dev_data->nb_rx_queues -
9435                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9436         else if (vsi->type == I40E_VSI_VMDQ2)
9437                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9438         else {
9439                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9440                 return I40E_ERR_NO_AVAILABLE_VSI;
9441         }
9442
9443         qpnum_per_tc = used_queues / total_tc;
9444         /* Number of queues per enabled TC */
9445         if (qpnum_per_tc == 0) {
9446                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9447                 return I40E_ERR_INVALID_QP_ID;
9448         }
9449         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9450                                 I40E_MAX_Q_PER_TC);
9451         bsf = rte_bsf32(qpnum_per_tc);
9452
9453         /**
9454          * Configure TC and queue mapping parameters, for enabled TC,
9455          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9456          * default queue will serve it.
9457          */
9458         qp_idx = 0;
9459         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9460                 if (vsi->enabled_tc & (1 << i)) {
9461                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9462                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9463                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9464                         qp_idx += qpnum_per_tc;
9465                 } else
9466                         info->tc_mapping[i] = 0;
9467         }
9468
9469         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9470         if (vsi->type == I40E_VSI_SRIOV) {
9471                 info->mapping_flags |=
9472                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9473                 for (i = 0; i < vsi->nb_qps; i++)
9474                         info->queue_mapping[i] =
9475                                 rte_cpu_to_le_16(vsi->base_queue + i);
9476         } else {
9477                 info->mapping_flags |=
9478                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9479                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9480         }
9481         info->valid_sections |=
9482                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9483
9484         return I40E_SUCCESS;
9485 }
9486
9487 /*
9488  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9489  * @veb: VEB to be configured
9490  * @tc_map: enabled TC bitmap
9491  *
9492  * Returns 0 on success, negative value on failure
9493  */
9494 static enum i40e_status_code
9495 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9496 {
9497         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9498         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9499         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9500         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9501         enum i40e_status_code ret = I40E_SUCCESS;
9502         int i;
9503         uint32_t bw_max;
9504
9505         /* Check if enabled_tc is same as existing or new TCs */
9506         if (veb->enabled_tc == tc_map)
9507                 return ret;
9508
9509         /* configure tc bandwidth */
9510         memset(&veb_bw, 0, sizeof(veb_bw));
9511         veb_bw.tc_valid_bits = tc_map;
9512         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9513         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9514                 if (tc_map & BIT_ULL(i))
9515                         veb_bw.tc_bw_share_credits[i] = 1;
9516         }
9517         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9518                                                    &veb_bw, NULL);
9519         if (ret) {
9520                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9521                                   " per TC failed = %d",
9522                                   hw->aq.asq_last_status);
9523                 return ret;
9524         }
9525
9526         memset(&ets_query, 0, sizeof(ets_query));
9527         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9528                                                    &ets_query, NULL);
9529         if (ret != I40E_SUCCESS) {
9530                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9531                                  " configuration %u", hw->aq.asq_last_status);
9532                 return ret;
9533         }
9534         memset(&bw_query, 0, sizeof(bw_query));
9535         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9536                                                   &bw_query, NULL);
9537         if (ret != I40E_SUCCESS) {
9538                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9539                                  " configuration %u", hw->aq.asq_last_status);
9540                 return ret;
9541         }
9542
9543         /* store and print out BW info */
9544         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9545         veb->bw_info.bw_max = ets_query.tc_bw_max;
9546         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9547         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9548         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9549                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9550                      I40E_16_BIT_WIDTH);
9551         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9552                 veb->bw_info.bw_ets_share_credits[i] =
9553                                 bw_query.tc_bw_share_credits[i];
9554                 veb->bw_info.bw_ets_credits[i] =
9555                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9556                 /* 4 bits per TC, 4th bit is reserved */
9557                 veb->bw_info.bw_ets_max[i] =
9558                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9559                                   RTE_LEN2MASK(3, uint8_t));
9560                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9561                             veb->bw_info.bw_ets_share_credits[i]);
9562                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9563                             veb->bw_info.bw_ets_credits[i]);
9564                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9565                             veb->bw_info.bw_ets_max[i]);
9566         }
9567
9568         veb->enabled_tc = tc_map;
9569
9570         return ret;
9571 }
9572
9573
9574 /*
9575  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9576  * @vsi: VSI to be configured
9577  * @tc_map: enabled TC bitmap
9578  *
9579  * Returns 0 on success, negative value on failure
9580  */
9581 static enum i40e_status_code
9582 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9583 {
9584         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9585         struct i40e_vsi_context ctxt;
9586         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9587         enum i40e_status_code ret = I40E_SUCCESS;
9588         int i;
9589
9590         /* Check if enabled_tc is same as existing or new TCs */
9591         if (vsi->enabled_tc == tc_map)
9592                 return ret;
9593
9594         /* configure tc bandwidth */
9595         memset(&bw_data, 0, sizeof(bw_data));
9596         bw_data.tc_valid_bits = tc_map;
9597         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9598         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9599                 if (tc_map & BIT_ULL(i))
9600                         bw_data.tc_bw_credits[i] = 1;
9601         }
9602         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9603         if (ret) {
9604                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9605                         " per TC failed = %d",
9606                         hw->aq.asq_last_status);
9607                 goto out;
9608         }
9609         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9610                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9611
9612         /* Update Queue Pairs Mapping for currently enabled UPs */
9613         ctxt.seid = vsi->seid;
9614         ctxt.pf_num = hw->pf_id;
9615         ctxt.vf_num = 0;
9616         ctxt.uplink_seid = vsi->uplink_seid;
9617         ctxt.info = vsi->info;
9618         i40e_get_cap(hw);
9619         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9620         if (ret)
9621                 goto out;
9622
9623         /* Update the VSI after updating the VSI queue-mapping information */
9624         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9625         if (ret) {
9626                 PMD_INIT_LOG(ERR, "Failed to configure "
9627                             "TC queue mapping = %d",
9628                             hw->aq.asq_last_status);
9629                 goto out;
9630         }
9631         /* update the local VSI info with updated queue map */
9632         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9633                                         sizeof(vsi->info.tc_mapping));
9634         (void)rte_memcpy(&vsi->info.queue_mapping,
9635                         &ctxt.info.queue_mapping,
9636                 sizeof(vsi->info.queue_mapping));
9637         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9638         vsi->info.valid_sections = 0;
9639
9640         /* query and update current VSI BW information */
9641         ret = i40e_vsi_get_bw_config(vsi);
9642         if (ret) {
9643                 PMD_INIT_LOG(ERR,
9644                          "Failed updating vsi bw info, err %s aq_err %s",
9645                          i40e_stat_str(hw, ret),
9646                          i40e_aq_str(hw, hw->aq.asq_last_status));
9647                 goto out;
9648         }
9649
9650         vsi->enabled_tc = tc_map;
9651
9652 out:
9653         return ret;
9654 }
9655
9656 /*
9657  * i40e_dcb_hw_configure - program the dcb setting to hw
9658  * @pf: pf the configuration is taken on
9659  * @new_cfg: new configuration
9660  * @tc_map: enabled TC bitmap
9661  *
9662  * Returns 0 on success, negative value on failure
9663  */
9664 static enum i40e_status_code
9665 i40e_dcb_hw_configure(struct i40e_pf *pf,
9666                       struct i40e_dcbx_config *new_cfg,
9667                       uint8_t tc_map)
9668 {
9669         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9670         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9671         struct i40e_vsi *main_vsi = pf->main_vsi;
9672         struct i40e_vsi_list *vsi_list;
9673         enum i40e_status_code ret;
9674         int i;
9675         uint32_t val;
9676
9677         /* Use the FW API if FW > v4.4*/
9678         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9679               (hw->aq.fw_maj_ver >= 5))) {
9680                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9681                                   " to configure DCB");
9682                 return I40E_ERR_FIRMWARE_API_VERSION;
9683         }
9684
9685         /* Check if need reconfiguration */
9686         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9687                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9688                 return I40E_SUCCESS;
9689         }
9690
9691         /* Copy the new config to the current config */
9692         *old_cfg = *new_cfg;
9693         old_cfg->etsrec = old_cfg->etscfg;
9694         ret = i40e_set_dcb_config(hw);
9695         if (ret) {
9696                 PMD_INIT_LOG(ERR,
9697                          "Set DCB Config failed, err %s aq_err %s\n",
9698                          i40e_stat_str(hw, ret),
9699                          i40e_aq_str(hw, hw->aq.asq_last_status));
9700                 return ret;
9701         }
9702         /* set receive Arbiter to RR mode and ETS scheme by default */
9703         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9704                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9705                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9706                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9707                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9708                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9709                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9710                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9711                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9712                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9713                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9714                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9715                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9716         }
9717         /* get local mib to check whether it is configured correctly */
9718         /* IEEE mode */
9719         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9720         /* Get Local DCB Config */
9721         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9722                                      &hw->local_dcbx_config);
9723
9724         /* if Veb is created, need to update TC of it at first */
9725         if (main_vsi->veb) {
9726                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9727                 if (ret)
9728                         PMD_INIT_LOG(WARNING,
9729                                  "Failed configuring TC for VEB seid=%d\n",
9730                                  main_vsi->veb->seid);
9731         }
9732         /* Update each VSI */
9733         i40e_vsi_config_tc(main_vsi, tc_map);
9734         if (main_vsi->veb) {
9735                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9736                         /* Beside main VSI and VMDQ VSIs, only enable default
9737                          * TC for other VSIs
9738                          */
9739                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9740                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9741                                                          tc_map);
9742                         else
9743                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9744                                                          I40E_DEFAULT_TCMAP);
9745                         if (ret)
9746                                 PMD_INIT_LOG(WARNING,
9747                                          "Failed configuring TC for VSI seid=%d\n",
9748                                          vsi_list->vsi->seid);
9749                         /* continue */
9750                 }
9751         }
9752         return I40E_SUCCESS;
9753 }
9754
9755 /*
9756  * i40e_dcb_init_configure - initial dcb config
9757  * @dev: device being configured
9758  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9759  *
9760  * Returns 0 on success, negative value on failure
9761  */
9762 static int
9763 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9764 {
9765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9767         int ret = 0;
9768
9769         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9770                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9771                 return -ENOTSUP;
9772         }
9773
9774         /* DCB initialization:
9775          * Update DCB configuration from the Firmware and configure
9776          * LLDP MIB change event.
9777          */
9778         if (sw_dcb == TRUE) {
9779                 ret = i40e_init_dcb(hw);
9780                 /* If lldp agent is stopped, the return value from
9781                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9782                  * adminq status. Otherwise, it should return success.
9783                  */
9784                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9785                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9786                         memset(&hw->local_dcbx_config, 0,
9787                                 sizeof(struct i40e_dcbx_config));
9788                         /* set dcb default configuration */
9789                         hw->local_dcbx_config.etscfg.willing = 0;
9790                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9791                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9792                         hw->local_dcbx_config.etscfg.tsatable[0] =
9793                                                 I40E_IEEE_TSA_ETS;
9794                         hw->local_dcbx_config.etsrec =
9795                                 hw->local_dcbx_config.etscfg;
9796                         hw->local_dcbx_config.pfc.willing = 0;
9797                         hw->local_dcbx_config.pfc.pfccap =
9798                                                 I40E_MAX_TRAFFIC_CLASS;
9799                         /* FW needs one App to configure HW */
9800                         hw->local_dcbx_config.numapps = 1;
9801                         hw->local_dcbx_config.app[0].selector =
9802                                                 I40E_APP_SEL_ETHTYPE;
9803                         hw->local_dcbx_config.app[0].priority = 3;
9804                         hw->local_dcbx_config.app[0].protocolid =
9805                                                 I40E_APP_PROTOID_FCOE;
9806                         ret = i40e_set_dcb_config(hw);
9807                         if (ret) {
9808                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9809                                         " err = %d, aq_err = %d.", ret,
9810                                           hw->aq.asq_last_status);
9811                                 return -ENOSYS;
9812                         }
9813                 } else {
9814                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9815                                           " err = %d, aq_err = %d.", ret,
9816                                           hw->aq.asq_last_status);
9817                         return -ENOTSUP;
9818                 }
9819         } else {
9820                 ret = i40e_aq_start_lldp(hw, NULL);
9821                 if (ret != I40E_SUCCESS)
9822                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9823
9824                 ret = i40e_init_dcb(hw);
9825                 if (!ret) {
9826                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9827                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9828                                                   " DCBX offload.");
9829                                 return -ENOTSUP;
9830                         }
9831                 } else {
9832                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9833                                           " aq_err = %d.", ret,
9834                                           hw->aq.asq_last_status);
9835                         return -ENOTSUP;
9836                 }
9837         }
9838         return 0;
9839 }
9840
9841 /*
9842  * i40e_dcb_setup - setup dcb related config
9843  * @dev: device being configured
9844  *
9845  * Returns 0 on success, negative value on failure
9846  */
9847 static int
9848 i40e_dcb_setup(struct rte_eth_dev *dev)
9849 {
9850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9851         struct i40e_dcbx_config dcb_cfg;
9852         uint8_t tc_map = 0;
9853         int ret = 0;
9854
9855         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9856                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9857                 return -ENOTSUP;
9858         }
9859
9860         if (pf->vf_num != 0)
9861                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9862
9863         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9864         if (ret) {
9865                 PMD_INIT_LOG(ERR, "invalid dcb config");
9866                 return -EINVAL;
9867         }
9868         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9869         if (ret) {
9870                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9871                 return -ENOSYS;
9872         }
9873
9874         return 0;
9875 }
9876
9877 static int
9878 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9879                       struct rte_eth_dcb_info *dcb_info)
9880 {
9881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9883         struct i40e_vsi *vsi = pf->main_vsi;
9884         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9885         uint16_t bsf, tc_mapping;
9886         int i, j = 0;
9887
9888         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9889                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9890         else
9891                 dcb_info->nb_tcs = 1;
9892         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9893                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9894         for (i = 0; i < dcb_info->nb_tcs; i++)
9895                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9896
9897         /* get queue mapping if vmdq is disabled */
9898         if (!pf->nb_cfg_vmdq_vsi) {
9899                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9900                         if (!(vsi->enabled_tc & (1 << i)))
9901                                 continue;
9902                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9903                         dcb_info->tc_queue.tc_rxq[j][i].base =
9904                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9905                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9906                         dcb_info->tc_queue.tc_txq[j][i].base =
9907                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9908                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9909                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9910                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9911                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9912                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9913                 }
9914                 return 0;
9915         }
9916
9917         /* get queue mapping if vmdq is enabled */
9918         do {
9919                 vsi = pf->vmdq[j].vsi;
9920                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9921                         if (!(vsi->enabled_tc & (1 << i)))
9922                                 continue;
9923                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9924                         dcb_info->tc_queue.tc_rxq[j][i].base =
9925                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9926                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9927                         dcb_info->tc_queue.tc_txq[j][i].base =
9928                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9929                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9930                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9931                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9932                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9933                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9934                 }
9935                 j++;
9936         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9937         return 0;
9938 }
9939
9940 static int
9941 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9942 {
9943         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9944         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9946         uint16_t interval =
9947                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9948         uint16_t msix_intr;
9949
9950         msix_intr = intr_handle->intr_vec[queue_id];
9951         if (msix_intr == I40E_MISC_VEC_ID)
9952                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9953                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9954                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9955                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9956                                (interval <<
9957                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9958         else
9959                 I40E_WRITE_REG(hw,
9960                                I40E_PFINT_DYN_CTLN(msix_intr -
9961                                                    I40E_RX_VEC_START),
9962                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9963                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9964                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9965                                (interval <<
9966                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9967
9968         I40E_WRITE_FLUSH(hw);
9969         rte_intr_enable(&pci_dev->intr_handle);
9970
9971         return 0;
9972 }
9973
9974 static int
9975 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9976 {
9977         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9978         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9979         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9980         uint16_t msix_intr;
9981
9982         msix_intr = intr_handle->intr_vec[queue_id];
9983         if (msix_intr == I40E_MISC_VEC_ID)
9984                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9985         else
9986                 I40E_WRITE_REG(hw,
9987                                I40E_PFINT_DYN_CTLN(msix_intr -
9988                                                    I40E_RX_VEC_START),
9989                                0);
9990         I40E_WRITE_FLUSH(hw);
9991
9992         return 0;
9993 }
9994
9995 static int i40e_get_regs(struct rte_eth_dev *dev,
9996                          struct rte_dev_reg_info *regs)
9997 {
9998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9999         uint32_t *ptr_data = regs->data;
10000         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10001         const struct i40e_reg_info *reg_info;
10002
10003         if (ptr_data == NULL) {
10004                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10005                 regs->width = sizeof(uint32_t);
10006                 return 0;
10007         }
10008
10009         /* The first few registers have to be read using AQ operations */
10010         reg_idx = 0;
10011         while (i40e_regs_adminq[reg_idx].name) {
10012                 reg_info = &i40e_regs_adminq[reg_idx++];
10013                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10014                         for (arr_idx2 = 0;
10015                                         arr_idx2 <= reg_info->count2;
10016                                         arr_idx2++) {
10017                                 reg_offset = arr_idx * reg_info->stride1 +
10018                                         arr_idx2 * reg_info->stride2;
10019                                 reg_offset += reg_info->base_addr;
10020                                 ptr_data[reg_offset >> 2] =
10021                                         i40e_read_rx_ctl(hw, reg_offset);
10022                         }
10023         }
10024
10025         /* The remaining registers can be read using primitives */
10026         reg_idx = 0;
10027         while (i40e_regs_others[reg_idx].name) {
10028                 reg_info = &i40e_regs_others[reg_idx++];
10029                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10030                         for (arr_idx2 = 0;
10031                                         arr_idx2 <= reg_info->count2;
10032                                         arr_idx2++) {
10033                                 reg_offset = arr_idx * reg_info->stride1 +
10034                                         arr_idx2 * reg_info->stride2;
10035                                 reg_offset += reg_info->base_addr;
10036                                 ptr_data[reg_offset >> 2] =
10037                                         I40E_READ_REG(hw, reg_offset);
10038                         }
10039         }
10040
10041         return 0;
10042 }
10043
10044 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10045 {
10046         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10047
10048         /* Convert word count to byte count */
10049         return hw->nvm.sr_size << 1;
10050 }
10051
10052 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10053                            struct rte_dev_eeprom_info *eeprom)
10054 {
10055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10056         uint16_t *data = eeprom->data;
10057         uint16_t offset, length, cnt_words;
10058         int ret_code;
10059
10060         offset = eeprom->offset >> 1;
10061         length = eeprom->length >> 1;
10062         cnt_words = length;
10063
10064         if (offset > hw->nvm.sr_size ||
10065                 offset + length > hw->nvm.sr_size) {
10066                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10067                 return -EINVAL;
10068         }
10069
10070         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10071
10072         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10073         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10074                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10075                 return -EIO;
10076         }
10077
10078         return 0;
10079 }
10080
10081 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10082                                       struct ether_addr *mac_addr)
10083 {
10084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10085
10086         if (!is_valid_assigned_ether_addr(mac_addr)) {
10087                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10088                 return;
10089         }
10090
10091         /* Flags: 0x3 updates port address */
10092         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10093 }
10094
10095 static int
10096 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10097 {
10098         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10099         struct rte_eth_dev_data *dev_data = pf->dev_data;
10100         uint32_t frame_size = mtu + ETHER_HDR_LEN
10101                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10102         int ret = 0;
10103
10104         /* check if mtu is within the allowed range */
10105         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10106                 return -EINVAL;
10107
10108         /* mtu setting is forbidden if port is start */
10109         if (dev_data->dev_started) {
10110                 PMD_DRV_LOG(ERR,
10111                             "port %d must be stopped before configuration\n",
10112                             dev_data->port_id);
10113                 return -EBUSY;
10114         }
10115
10116         if (frame_size > ETHER_MAX_LEN)
10117                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10118         else
10119                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10120
10121         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10122
10123         return ret;
10124 }