drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  52 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  53
  54 /* Maximun number of capability elements */
  55 #define I40E_MAX_CAP_ELE_NUM       128
  56
  57 /* Wait count and interval */
  58 #define I40E_CHK_Q_ENA_COUNT       1000
  59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  60
  61 /* Maximun number of VSI */
  62 #define I40E_MAX_NUM_VSIS          (384UL)
  63
  64 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  65
  66 /* Flow control default timer */
  67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  68
  69 /* Flow control enable fwd bit */
  70 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  71
  72 /* Receive Packet Buffer size */
  73 #define I40E_RXPBSIZE (968 * 1024)
  74
  75 /* Kilobytes shift */
  76 #define I40E_KILOSHIFT 10
  77
  78 /* Flow control default high water */
  79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Flow control default low water */
  82 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  83
  84 /* Receive Average Packet Size in Byte*/
  85 #define I40E_PACKET_AVERAGE_SIZE 128
  86
  87 /* Mask of PF interrupt causes */
  88 #define I40E_PFINT_ICR0_ENA_MASK ( \
  89                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  93                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  94                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  98
  99 #define I40E_FLOW_TYPES ( \
 100         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 105         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 110         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 111
 112 /* Additional timesync values. */
 113 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 114 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 115 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 116 #define I40E_PRTTSYN_TSYNENA     0x80000000
 117 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 118 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 119
 120 /**
 121  * Below are values for writing un-exposed registers suggested
 122  * by silicon experts
 123  */
 124 /* Destination MAC address */
 125 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 126 /* Source MAC address */
 127 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 131 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 132 /* Single VLAN tag in the inner L2 header */
 133 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 134 /* Source IPv4 address */
 135 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 136 /* Destination IPv4 address */
 137 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 138 /* Source IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 140 /* Destination IPv4 address for X722 */
 141 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 142 /* IPv4 Protocol for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 144 /* IPv4 Time to Live for X722 */
 145 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 146 /* IPv4 Type of Service (TOS) */
 147 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 148 /* IPv4 Protocol */
 149 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 150 /* IPv4 Time to Live */
 151 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 152 /* Source IPv6 address */
 153 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 154 /* Destination IPv6 address */
 155 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 156 /* IPv6 Traffic Class (TC) */
 157 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 158 /* IPv6 Next Header */
 159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 160 /* IPv6 Hop Limit */
 161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 162 /* Source L4 port */
 163 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 164 /* Destination L4 port */
 165 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 166 /* SCTP verification tag */
 167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 170 /* Source port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 172 /* Destination port of tunneling UDP */
 173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 174 /* UDP Tunneling ID, NVGRE/GRE key */
 175 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 176 /* Last ether type */
 177 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 178 /* Tunneling outer destination IPv4 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 180 /* Tunneling outer destination IPv6 address */
 181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 182 /* 1st word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 184 /* 2nd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 186 /* 3rd word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 188 /* 4th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 190 /* 5th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 192 /* 6th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 194 /* 7th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 196 /* 8th word of flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 198 /* all 8 words flex payload */
 199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 200 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 201
 202 #define I40E_TRANSLATE_INSET 0
 203 #define I40E_TRANSLATE_REG   1
 204
 205 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 206 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 207 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 208 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 210 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 211
 212 /* PCI offset for querying capability */
 213 #define PCI_DEV_CAP_REG            0xA4
 214 /* PCI offset for enabling/disabling Extended Tag */
 215 #define PCI_DEV_CTRL_REG           0xA8
 216 /* Bit mask of Extended Tag capability */
 217 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 218 /* Bit shift of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 220 /* Bit mask of Extended Tag enable/disable */
 221 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 222
 223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 225 static int i40e_dev_configure(struct rte_eth_dev *dev);
 226 static int i40e_dev_start(struct rte_eth_dev *dev);
 227 static int i40e_dev_stop(struct rte_eth_dev *dev);
 228 static int i40e_dev_close(struct rte_eth_dev *dev);
 229 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_stats *stats);
 238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 239                                struct rte_eth_xstat *xstats, unsigned n);
 240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 241                                      struct rte_eth_xstat_name *xstats_names,
 242                                      unsigned limit);
 243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 247                              struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 309                                              struct i40e_macvlan_filter *mv_f,
 310                                              int num,
 311                                              uint16_t vlan);
 312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 314                                     struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 316                                       struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_get_module_info(struct rte_eth_dev *dev,
 373                                 struct rte_eth_dev_module_info *modinfo);
 374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 375                                   struct rte_dev_eeprom_info *info);
 376
 377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 378                                       struct rte_ether_addr *mac_addr);
 379
 380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 381
 382 static int i40e_ethertype_filter_convert(
 383         const struct rte_eth_ethertype_filter *input,
 384         struct i40e_ethertype_filter *filter);
 385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 386                                    struct i40e_ethertype_filter *filter);
 387
 388 static int i40e_tunnel_filter_convert(
 389         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 390         struct i40e_tunnel_filter *tunnel_filter);
 391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 392                                 struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 394
 395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 397 static void i40e_filter_restore(struct i40e_pf *pf);
 398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 399 static int i40e_pf_config_rss(struct i40e_pf *pf);
 400
 401 static const char *const valid_keys[] = {
 402         ETH_I40E_FLOATING_VEB_ARG,
 403         ETH_I40E_FLOATING_VEB_LIST_ARG,
 404         ETH_I40E_SUPPORT_MULTI_DRIVER,
 405         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 406         ETH_I40E_USE_LATEST_VEC,
 407         ETH_I40E_VF_MSG_CFG,
 408         NULL};
 409
 410 static const struct rte_pci_id pci_id_i40e_map[] = {
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .fw_version_get               = i40e_fw_version_get,
 459         .dev_infos_get                = i40e_dev_info_get,
 460         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 461         .vlan_filter_set              = i40e_vlan_filter_set,
 462         .vlan_tpid_set                = i40e_vlan_tpid_set,
 463         .vlan_offload_set             = i40e_vlan_offload_set,
 464         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 465         .vlan_pvid_set                = i40e_vlan_pvid_set,
 466         .rx_queue_start               = i40e_dev_rx_queue_start,
 467         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 468         .tx_queue_start               = i40e_dev_tx_queue_start,
 469         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 470         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 471         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 472         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 473         .rx_queue_release             = i40e_dev_rx_queue_release,
 474         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 475         .tx_queue_release             = i40e_dev_tx_queue_release,
 476         .dev_led_on                   = i40e_dev_led_on,
 477         .dev_led_off                  = i40e_dev_led_off,
 478         .flow_ctrl_get                = i40e_flow_ctrl_get,
 479         .flow_ctrl_set                = i40e_flow_ctrl_set,
 480         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 481         .mac_addr_add                 = i40e_macaddr_add,
 482         .mac_addr_remove              = i40e_macaddr_remove,
 483         .reta_update                  = i40e_dev_rss_reta_update,
 484         .reta_query                   = i40e_dev_rss_reta_query,
 485         .rss_hash_update              = i40e_dev_rss_hash_update,
 486         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 487         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 488         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 489         .filter_ctrl                  = i40e_dev_filter_ctrl,
 490         .rxq_info_get                 = i40e_rxq_info_get,
 491         .txq_info_get                 = i40e_txq_info_get,
 492         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 493         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 494         .mirror_rule_set              = i40e_mirror_rule_set,
 495         .mirror_rule_reset            = i40e_mirror_rule_reset,
 496         .timesync_enable              = i40e_timesync_enable,
 497         .timesync_disable             = i40e_timesync_disable,
 498         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 499         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 500         .get_dcb_info                 = i40e_dev_get_dcb_info,
 501         .timesync_adjust_time         = i40e_timesync_adjust_time,
 502         .timesync_read_time           = i40e_timesync_read_time,
 503         .timesync_write_time          = i40e_timesync_write_time,
 504         .get_reg                      = i40e_get_regs,
 505         .get_eeprom_length            = i40e_get_eeprom_length,
 506         .get_eeprom                   = i40e_get_eeprom,
 507         .get_module_info              = i40e_get_module_info,
 508         .get_module_eeprom            = i40e_get_module_eeprom,
 509         .mac_addr_set                 = i40e_set_default_mac_addr,
 510         .mtu_set                      = i40e_dev_mtu_set,
 511         .tm_ops_get                   = i40e_tm_ops_get,
 512         .tx_done_cleanup              = i40e_tx_done_cleanup,
 513 };
 514
 515 /* store statistics names and its offset in stats structure */
 516 struct rte_i40e_xstats_name_off {
 517         char name[RTE_ETH_XSTATS_NAME_SIZE];
 518         unsigned offset;
 519 };
 520
 521 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 522         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 523         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 524         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 525         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 526         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 527                 rx_unknown_protocol)},
 528         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 529         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 530         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 531         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 532 };
 533
 534 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 535                 sizeof(rte_i40e_stats_strings[0]))
 536
 537 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 538         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 539                 tx_dropped_link_down)},
 540         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 541         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 542                 illegal_bytes)},
 543         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 544         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 545                 mac_local_faults)},
 546         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_remote_faults)},
 548         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 549                 rx_length_errors)},
 550         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 551         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 552         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 553         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 554         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 555         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_127)},
 557         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_255)},
 559         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_1023)},
 563         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1522)},
 565         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_big)},
 567         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 568                 rx_undersize)},
 569         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_oversize)},
 571         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 572                 mac_short_packet_dropped)},
 573         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_fragments)},
 575         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 576         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 577         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_255)},
 581         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_511)},
 583         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_1023)},
 585         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1522)},
 587         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_big)},
 589         {"rx_flow_director_atr_match_packets",
 590                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 591         {"rx_flow_director_sb_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 593         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 594                 tx_lpi_status)},
 595         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 rx_lpi_status)},
 597         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_count)},
 599         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_count)},
 601 };
 602
 603 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 604                 sizeof(rte_i40e_hw_port_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_rx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_rx)},
 611 };
 612
 613 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 614                 sizeof(rte_i40e_rxq_prio_strings[0]))
 615
 616 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 617         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xon_tx)},
 619         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xoff_tx)},
 621         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_2_xoff)},
 623 };
 624
 625 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 626                 sizeof(rte_i40e_txq_prio_strings[0]))
 627
 628 static int
 629 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 630         struct rte_pci_device *pci_dev)
 631 {
 632         char name[RTE_ETH_NAME_MAX_LEN];
 633         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 634         int i, retval;
 635
 636         if (pci_dev->device.devargs) {
 637                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 638                                 &eth_da);
 639                 if (retval)
 640                         return retval;
 641         }
 642
 643         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 644                 sizeof(struct i40e_adapter),
 645                 eth_dev_pci_specific_init, pci_dev,
 646                 eth_i40e_dev_init, NULL);
 647
 648         if (retval || eth_da.nb_representor_ports < 1)
 649                 return retval;
 650
 651         /* probe VF representor ports */
 652         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 653                 pci_dev->device.name);
 654
 655         if (pf_ethdev == NULL)
 656                 return -ENODEV;
 657
 658         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 659                 struct i40e_vf_representor representor = {
 660                         .vf_id = eth_da.representor_ports[i],
 661                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 662                                 pf_ethdev->data->dev_private)->switch_domain_id,
 663                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 664                                 pf_ethdev->data->dev_private)
 665                 };
 666
 667                 /* representor port net_bdf_port */
 668                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 669                         pci_dev->device.name, eth_da.representor_ports[i]);
 670
 671                 retval = rte_eth_dev_create(&pci_dev->device, name,
 672                         sizeof(struct i40e_vf_representor), NULL, NULL,
 673                         i40e_vf_representor_init, &representor);
 674
 675                 if (retval)
 676                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 677                                 "representor %s.", name);
 678         }
 679
 680         return 0;
 681 }
 682
 683 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 684 {
 685         struct rte_eth_dev *ethdev;
 686
 687         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 688         if (!ethdev)
 689                 return 0;
 690
 691         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 692                 return rte_eth_dev_pci_generic_remove(pci_dev,
 693                                         i40e_vf_representor_uninit);
 694         else
 695                 return rte_eth_dev_pci_generic_remove(pci_dev,
 696                                                 eth_i40e_dev_uninit);
 697 }
 698
 699 static struct rte_pci_driver rte_i40e_pmd = {
 700         .id_table = pci_id_i40e_map,
 701         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 702         .probe = eth_i40e_pci_probe,
 703         .remove = eth_i40e_pci_remove,
 704 };
 705
 706 static inline void
 707 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 708                          uint32_t reg_val)
 709 {
 710         uint32_t ori_reg_val;
 711         struct rte_eth_dev *dev;
 712
 713         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 714         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 715         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 716         if (ori_reg_val != reg_val)
 717                 PMD_DRV_LOG(WARNING,
 718                             "i40e device %s changed global register [0x%08x]."
 719                             " original: 0x%08x, new: 0x%08x",
 720                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 721 }
 722
 723 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 724 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 725 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 726
 727 #ifndef I40E_GLQF_ORT
 728 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 729 #endif
 730 #ifndef I40E_GLQF_PIT
 731 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 732 #endif
 733 #ifndef I40E_GLQF_L3_MAP
 734 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 735 #endif
 736
 737 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 738 {
 739         /*
 740          * Initialize registers for parsing packet type of QinQ
 741          * This should be removed from code once proper
 742          * configuration API is added to avoid configuration conflicts
 743          * between ports of the same device.
 744          */
 745         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 746         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 747 }
 748
 749 static inline void i40e_config_automask(struct i40e_pf *pf)
 750 {
 751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 752         uint32_t val;
 753
 754         /* INTENA flag is not auto-cleared for interrupt */
 755         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 756         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 757                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 758
 759         /* If support multi-driver, PF will use INT0. */
 760         if (!pf->support_multi_driver)
 761                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 762
 763         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 764 }
 765
 766 static inline void i40e_clear_automask(struct i40e_pf *pf)
 767 {
 768         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 769         uint32_t val;
 770
 771         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 772         val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 773                  I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
 774
 775         if (!pf->support_multi_driver)
 776                 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 777
 778         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 779 }
 780
 781 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 782
 783 /*
 784  * Add a ethertype filter to drop all flow control frames transmitted
 785  * from VSIs.
 786 */
 787 static void
 788 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 789 {
 790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 791         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 792                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 793                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 794         int ret;
 795
 796         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 797                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 798                                 pf->main_vsi_seid, 0,
 799                                 TRUE, NULL, NULL);
 800         if (ret)
 801                 PMD_INIT_LOG(ERR,
 802                         "Failed to add filter to drop flow control frames from VSIs.");
 803 }
 804
 805 static int
 806 floating_veb_list_handler(__rte_unused const char *key,
 807                           const char *floating_veb_value,
 808                           void *opaque)
 809 {
 810         int idx = 0;
 811         unsigned int count = 0;
 812         char *end = NULL;
 813         int min, max;
 814         bool *vf_floating_veb = opaque;
 815
 816         while (isblank(*floating_veb_value))
 817                 floating_veb_value++;
 818
 819         /* Reset floating VEB configuration for VFs */
 820         for (idx = 0; idx < I40E_MAX_VF; idx++)
 821                 vf_floating_veb[idx] = false;
 822
 823         min = I40E_MAX_VF;
 824         do {
 825                 while (isblank(*floating_veb_value))
 826                         floating_veb_value++;
 827                 if (*floating_veb_value == '\0')
 828                         return -1;
 829                 errno = 0;
 830                 idx = strtoul(floating_veb_value, &end, 10);
 831                 if (errno || end == NULL)
 832                         return -1;
 833                 while (isblank(*end))
 834                         end++;
 835                 if (*end == '-') {
 836                         min = idx;
 837                 } else if ((*end == ';') || (*end == '\0')) {
 838                         max = idx;
 839                         if (min == I40E_MAX_VF)
 840                                 min = idx;
 841                         if (max >= I40E_MAX_VF)
 842                                 max = I40E_MAX_VF - 1;
 843                         for (idx = min; idx <= max; idx++) {
 844                                 vf_floating_veb[idx] = true;
 845                                 count++;
 846                         }
 847                         min = I40E_MAX_VF;
 848                 } else {
 849                         return -1;
 850                 }
 851                 floating_veb_value = end + 1;
 852         } while (*end != '\0');
 853
 854         if (count == 0)
 855                 return -1;
 856
 857         return 0;
 858 }
 859
 860 static void
 861 config_vf_floating_veb(struct rte_devargs *devargs,
 862                        uint16_t floating_veb,
 863                        bool *vf_floating_veb)
 864 {
 865         struct rte_kvargs *kvlist;
 866         int i;
 867         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 868
 869         if (!floating_veb)
 870                 return;
 871         /* All the VFs attach to the floating VEB by default
 872          * when the floating VEB is enabled.
 873          */
 874         for (i = 0; i < I40E_MAX_VF; i++)
 875                 vf_floating_veb[i] = true;
 876
 877         if (devargs == NULL)
 878                 return;
 879
 880         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 881         if (kvlist == NULL)
 882                 return;
 883
 884         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 885                 rte_kvargs_free(kvlist);
 886                 return;
 887         }
 888         /* When the floating_veb_list parameter exists, all the VFs
 889          * will attach to the legacy VEB firstly, then configure VFs
 890          * to the floating VEB according to the floating_veb_list.
 891          */
 892         if (rte_kvargs_process(kvlist, floating_veb_list,
 893                                floating_veb_list_handler,
 894                                vf_floating_veb) < 0) {
 895                 rte_kvargs_free(kvlist);
 896                 return;
 897         }
 898         rte_kvargs_free(kvlist);
 899 }
 900
 901 static int
 902 i40e_check_floating_handler(__rte_unused const char *key,
 903                             const char *value,
 904                             __rte_unused void *opaque)
 905 {
 906         if (strcmp(value, "1"))
 907                 return -1;
 908
 909         return 0;
 910 }
 911
 912 static int
 913 is_floating_veb_supported(struct rte_devargs *devargs)
 914 {
 915         struct rte_kvargs *kvlist;
 916         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 917
 918         if (devargs == NULL)
 919                 return 0;
 920
 921         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 922         if (kvlist == NULL)
 923                 return 0;
 924
 925         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 926                 rte_kvargs_free(kvlist);
 927                 return 0;
 928         }
 929         /* Floating VEB is enabled when there's key-value:
 930          * enable_floating_veb=1
 931          */
 932         if (rte_kvargs_process(kvlist, floating_veb_key,
 933                                i40e_check_floating_handler, NULL) < 0) {
 934                 rte_kvargs_free(kvlist);
 935                 return 0;
 936         }
 937         rte_kvargs_free(kvlist);
 938
 939         return 1;
 940 }
 941
 942 static void
 943 config_floating_veb(struct rte_eth_dev *dev)
 944 {
 945         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 947         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 948
 949         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 950
 951         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 952                 pf->floating_veb =
 953                         is_floating_veb_supported(pci_dev->device.devargs);
 954                 config_vf_floating_veb(pci_dev->device.devargs,
 955                                        pf->floating_veb,
 956                                        pf->floating_veb_list);
 957         } else {
 958                 pf->floating_veb = false;
 959         }
 960 }
 961
 962 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 963 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 964
 965 static int
 966 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 967 {
 968         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 969         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 970         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 971         int ret;
 972
 973         struct rte_hash_parameters ethertype_hash_params = {
 974                 .name = ethertype_hash_name,
 975                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 976                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 977                 .hash_func = rte_hash_crc,
 978                 .hash_func_init_val = 0,
 979                 .socket_id = rte_socket_id(),
 980         };
 981
 982         /* Initialize ethertype filter rule list and hash */
 983         TAILQ_INIT(&ethertype_rule->ethertype_list);
 984         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 985                  "ethertype_%s", dev->device->name);
 986         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 987         if (!ethertype_rule->hash_table) {
 988                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 989                 return -EINVAL;
 990         }
 991         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 992                                        sizeof(struct i40e_ethertype_filter *) *
 993                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 994                                        0);
 995         if (!ethertype_rule->hash_map) {
 996                 PMD_INIT_LOG(ERR,
 997                              "Failed to allocate memory for ethertype hash map!");
 998                 ret = -ENOMEM;
 999                 goto err_ethertype_hash_map_alloc;
1000         }
1001
1002         return 0;
1003
1004 err_ethertype_hash_map_alloc:
1005         rte_hash_free(ethertype_rule->hash_table);
1006
1007         return ret;
1008 }
1009
1010 static int
1011 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1012 {
1013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1015         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1016         int ret;
1017
1018         struct rte_hash_parameters tunnel_hash_params = {
1019                 .name = tunnel_hash_name,
1020                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1021                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1022                 .hash_func = rte_hash_crc,
1023                 .hash_func_init_val = 0,
1024                 .socket_id = rte_socket_id(),
1025         };
1026
1027         /* Initialize tunnel filter rule list and hash */
1028         TAILQ_INIT(&tunnel_rule->tunnel_list);
1029         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1030                  "tunnel_%s", dev->device->name);
1031         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1032         if (!tunnel_rule->hash_table) {
1033                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1034                 return -EINVAL;
1035         }
1036         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1037                                     sizeof(struct i40e_tunnel_filter *) *
1038                                     I40E_MAX_TUNNEL_FILTER_NUM,
1039                                     0);
1040         if (!tunnel_rule->hash_map) {
1041                 PMD_INIT_LOG(ERR,
1042                              "Failed to allocate memory for tunnel hash map!");
1043                 ret = -ENOMEM;
1044                 goto err_tunnel_hash_map_alloc;
1045         }
1046
1047         return 0;
1048
1049 err_tunnel_hash_map_alloc:
1050         rte_hash_free(tunnel_rule->hash_table);
1051
1052         return ret;
1053 }
1054
1055 static int
1056 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1057 {
1058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1059         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1060         struct i40e_fdir_info *fdir_info = &pf->fdir;
1061         char fdir_hash_name[RTE_HASH_NAMESIZE];
1062         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1063         uint32_t best = hw->func_caps.fd_filters_best_effort;
1064         struct rte_bitmap *bmp = NULL;
1065         uint32_t bmp_size;
1066         void *mem = NULL;
1067         uint32_t i = 0;
1068         int ret;
1069
1070         struct rte_hash_parameters fdir_hash_params = {
1071                 .name = fdir_hash_name,
1072                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1073                 .key_len = sizeof(struct i40e_fdir_input),
1074                 .hash_func = rte_hash_crc,
1075                 .hash_func_init_val = 0,
1076                 .socket_id = rte_socket_id(),
1077         };
1078
1079         /* Initialize flow director filter rule list and hash */
1080         TAILQ_INIT(&fdir_info->fdir_list);
1081         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1082                  "fdir_%s", dev->device->name);
1083         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1084         if (!fdir_info->hash_table) {
1085                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1086                 return -EINVAL;
1087         }
1088
1089         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1090                                           sizeof(struct i40e_fdir_filter *) *
1091                                           I40E_MAX_FDIR_FILTER_NUM,
1092                                           0);
1093         if (!fdir_info->hash_map) {
1094                 PMD_INIT_LOG(ERR,
1095                              "Failed to allocate memory for fdir hash map!");
1096                 ret = -ENOMEM;
1097                 goto err_fdir_hash_map_alloc;
1098         }
1099
1100         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1101                         sizeof(struct i40e_fdir_filter) *
1102                         I40E_MAX_FDIR_FILTER_NUM,
1103                         0);
1104
1105         if (!fdir_info->fdir_filter_array) {
1106                 PMD_INIT_LOG(ERR,
1107                              "Failed to allocate memory for fdir filter array!");
1108                 ret = -ENOMEM;
1109                 goto err_fdir_filter_array_alloc;
1110         }
1111
1112         fdir_info->fdir_space_size = alloc + best;
1113         fdir_info->fdir_actual_cnt = 0;
1114         fdir_info->fdir_guarantee_total_space = alloc;
1115         fdir_info->fdir_guarantee_free_space =
1116                 fdir_info->fdir_guarantee_total_space;
1117
1118         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1119
1120         fdir_info->fdir_flow_pool.pool =
1121                         rte_zmalloc("i40e_fdir_entry",
1122                                 sizeof(struct i40e_fdir_entry) *
1123                                 fdir_info->fdir_space_size,
1124                                 0);
1125
1126         if (!fdir_info->fdir_flow_pool.pool) {
1127                 PMD_INIT_LOG(ERR,
1128                              "Failed to allocate memory for bitmap flow!");
1129                 ret = -ENOMEM;
1130                 goto err_fdir_bitmap_flow_alloc;
1131         }
1132
1133         for (i = 0; i < fdir_info->fdir_space_size; i++)
1134                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1135
1136         bmp_size =
1137                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1138         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1139         if (mem == NULL) {
1140                 PMD_INIT_LOG(ERR,
1141                              "Failed to allocate memory for fdir bitmap!");
1142                 ret = -ENOMEM;
1143                 goto err_fdir_mem_alloc;
1144         }
1145         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1146         if (bmp == NULL) {
1147                 PMD_INIT_LOG(ERR,
1148                              "Failed to initialization fdir bitmap!");
1149                 ret = -ENOMEM;
1150                 goto err_fdir_bmp_alloc;
1151         }
1152         for (i = 0; i < fdir_info->fdir_space_size; i++)
1153                 rte_bitmap_set(bmp, i);
1154
1155         fdir_info->fdir_flow_pool.bitmap = bmp;
1156
1157         return 0;
1158
1159 err_fdir_bmp_alloc:
1160         rte_free(mem);
1161 err_fdir_mem_alloc:
1162         rte_free(fdir_info->fdir_flow_pool.pool);
1163 err_fdir_bitmap_flow_alloc:
1164         rte_free(fdir_info->fdir_filter_array);
1165 err_fdir_filter_array_alloc:
1166         rte_free(fdir_info->hash_map);
1167 err_fdir_hash_map_alloc:
1168         rte_hash_free(fdir_info->hash_table);
1169
1170         return ret;
1171 }
1172
1173 static void
1174 i40e_init_customized_info(struct i40e_pf *pf)
1175 {
1176         int i;
1177
1178         /* Initialize customized pctype */
1179         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1180                 pf->customized_pctype[i].index = i;
1181                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1182                 pf->customized_pctype[i].valid = false;
1183         }
1184
1185         pf->gtp_support = false;
1186         pf->esp_support = false;
1187 }
1188
1189 static void
1190 i40e_init_filter_invalidation(struct i40e_pf *pf)
1191 {
1192         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1193         struct i40e_fdir_info *fdir_info = &pf->fdir;
1194         uint32_t glqf_ctl_reg = 0;
1195
1196         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1197         if (!pf->support_multi_driver) {
1198                 fdir_info->fdir_invalprio = 1;
1199                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1200                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1201                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1202         } else {
1203                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1204                         fdir_info->fdir_invalprio = 1;
1205                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1206                 } else {
1207                         fdir_info->fdir_invalprio = 0;
1208                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1209                 }
1210         }
1211 }
1212
1213 void
1214 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1215 {
1216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1218         struct i40e_queue_regions *info = &pf->queue_region;
1219         uint16_t i;
1220
1221         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1222                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1223
1224         memset(info, 0, sizeof(struct i40e_queue_regions));
1225 }
1226
1227 static int
1228 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1229                                const char *value,
1230                                void *opaque)
1231 {
1232         struct i40e_pf *pf;
1233         unsigned long support_multi_driver;
1234         char *end;
1235
1236         pf = (struct i40e_pf *)opaque;
1237
1238         errno = 0;
1239         support_multi_driver = strtoul(value, &end, 10);
1240         if (errno != 0 || end == value || *end != 0) {
1241                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1242                 return -(EINVAL);
1243         }
1244
1245         if (support_multi_driver == 1 || support_multi_driver == 0)
1246                 pf->support_multi_driver = (bool)support_multi_driver;
1247         else
1248                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1249                             "enable global configuration by default."
1250                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1251         return 0;
1252 }
1253
1254 static int
1255 i40e_support_multi_driver(struct rte_eth_dev *dev)
1256 {
1257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1258         struct rte_kvargs *kvlist;
1259         int kvargs_count;
1260
1261         /* Enable global configuration by default */
1262         pf->support_multi_driver = false;
1263
1264         if (!dev->device->devargs)
1265                 return 0;
1266
1267         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1268         if (!kvlist)
1269                 return -EINVAL;
1270
1271         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1272         if (!kvargs_count) {
1273                 rte_kvargs_free(kvlist);
1274                 return 0;
1275         }
1276
1277         if (kvargs_count > 1)
1278                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1279                             "the first invalid or last valid one is used !",
1280                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1281
1282         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1283                                i40e_parse_multi_drv_handler, pf) < 0) {
1284                 rte_kvargs_free(kvlist);
1285                 return -EINVAL;
1286         }
1287
1288         rte_kvargs_free(kvlist);
1289         return 0;
1290 }
1291
1292 static int
1293 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1294                                     uint32_t reg_addr, uint64_t reg_val,
1295                                     struct i40e_asq_cmd_details *cmd_details)
1296 {
1297         uint64_t ori_reg_val;
1298         struct rte_eth_dev *dev;
1299         int ret;
1300
1301         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1302         if (ret != I40E_SUCCESS) {
1303                 PMD_DRV_LOG(ERR,
1304                             "Fail to debug read from 0x%08x",
1305                             reg_addr);
1306                 return -EIO;
1307         }
1308         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1309
1310         if (ori_reg_val != reg_val)
1311                 PMD_DRV_LOG(WARNING,
1312                             "i40e device %s changed global register [0x%08x]."
1313                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1314                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1315
1316         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1317 }
1318
1319 static int
1320 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1321                                 const char *value,
1322                                 void *opaque)
1323 {
1324         struct i40e_adapter *ad = opaque;
1325         int use_latest_vec;
1326
1327         use_latest_vec = atoi(value);
1328
1329         if (use_latest_vec != 0 && use_latest_vec != 1)
1330                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1331
1332         ad->use_latest_vec = (uint8_t)use_latest_vec;
1333
1334         return 0;
1335 }
1336
1337 static int
1338 i40e_use_latest_vec(struct rte_eth_dev *dev)
1339 {
1340         struct i40e_adapter *ad =
1341                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1342         struct rte_kvargs *kvlist;
1343         int kvargs_count;
1344
1345         ad->use_latest_vec = false;
1346
1347         if (!dev->device->devargs)
1348                 return 0;
1349
1350         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1351         if (!kvlist)
1352                 return -EINVAL;
1353
1354         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1355         if (!kvargs_count) {
1356                 rte_kvargs_free(kvlist);
1357                 return 0;
1358         }
1359
1360         if (kvargs_count > 1)
1361                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1362                             "the first invalid or last valid one is used !",
1363                             ETH_I40E_USE_LATEST_VEC);
1364
1365         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1366                                 i40e_parse_latest_vec_handler, ad) < 0) {
1367                 rte_kvargs_free(kvlist);
1368                 return -EINVAL;
1369         }
1370
1371         rte_kvargs_free(kvlist);
1372         return 0;
1373 }
1374
1375 static int
1376 read_vf_msg_config(__rte_unused const char *key,
1377                                const char *value,
1378                                void *opaque)
1379 {
1380         struct i40e_vf_msg_cfg *cfg = opaque;
1381
1382         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1383                         &cfg->ignore_second) != 3) {
1384                 memset(cfg, 0, sizeof(*cfg));
1385                 PMD_DRV_LOG(ERR, "format error! example: "
1386                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1387                 return -EINVAL;
1388         }
1389
1390         /*
1391          * If the message validation function been enabled, the 'period'
1392          * and 'ignore_second' must greater than 0.
1393          */
1394         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1395                 memset(cfg, 0, sizeof(*cfg));
1396                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1397                                 " number must be greater than 0!",
1398                                 ETH_I40E_VF_MSG_CFG);
1399                 return -EINVAL;
1400         }
1401
1402         return 0;
1403 }
1404
1405 static int
1406 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1407                 struct i40e_vf_msg_cfg *msg_cfg)
1408 {
1409         struct rte_kvargs *kvlist;
1410         int kvargs_count;
1411         int ret = 0;
1412
1413         memset(msg_cfg, 0, sizeof(*msg_cfg));
1414
1415         if (!dev->device->devargs)
1416                 return ret;
1417
1418         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1419         if (!kvlist)
1420                 return -EINVAL;
1421
1422         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1423         if (!kvargs_count)
1424                 goto free_end;
1425
1426         if (kvargs_count > 1) {
1427                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1428                                 ETH_I40E_VF_MSG_CFG);
1429                 ret = -EINVAL;
1430                 goto free_end;
1431         }
1432
1433         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1434                         read_vf_msg_config, msg_cfg) < 0)
1435                 ret = -EINVAL;
1436
1437 free_end:
1438         rte_kvargs_free(kvlist);
1439         return ret;
1440 }
1441
1442 #define I40E_ALARM_INTERVAL 50000 /* us */
1443
1444 static int
1445 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1446 {
1447         struct rte_pci_device *pci_dev;
1448         struct rte_intr_handle *intr_handle;
1449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1451         struct i40e_vsi *vsi;
1452         int ret;
1453         uint32_t len, val;
1454         uint8_t aq_fail = 0;
1455
1456         PMD_INIT_FUNC_TRACE();
1457
1458         dev->dev_ops = &i40e_eth_dev_ops;
1459         dev->rx_queue_count = i40e_dev_rx_queue_count;
1460         dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1461         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1462         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1463         dev->rx_pkt_burst = i40e_recv_pkts;
1464         dev->tx_pkt_burst = i40e_xmit_pkts;
1465         dev->tx_pkt_prepare = i40e_prep_pkts;
1466
1467         /* for secondary processes, we don't initialise any further as primary
1468          * has already done this work. Only check we don't need a different
1469          * RX function */
1470         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1471                 i40e_set_rx_function(dev);
1472                 i40e_set_tx_function(dev);
1473                 return 0;
1474         }
1475         i40e_set_default_ptype_table(dev);
1476         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1477         intr_handle = &pci_dev->intr_handle;
1478
1479         rte_eth_copy_pci_info(dev, pci_dev);
1480         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1481
1482         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1483         pf->adapter->eth_dev = dev;
1484         pf->dev_data = dev->data;
1485
1486         hw->back = I40E_PF_TO_ADAPTER(pf);
1487         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1488         if (!hw->hw_addr) {
1489                 PMD_INIT_LOG(ERR,
1490                         "Hardware is not available, as address is NULL");
1491                 return -ENODEV;
1492         }
1493
1494         hw->vendor_id = pci_dev->id.vendor_id;
1495         hw->device_id = pci_dev->id.device_id;
1496         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1497         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1498         hw->bus.device = pci_dev->addr.devid;
1499         hw->bus.func = pci_dev->addr.function;
1500         hw->adapter_stopped = 0;
1501         hw->adapter_closed = 0;
1502
1503         /* Init switch device pointer */
1504         hw->switch_dev = NULL;
1505
1506         /*
1507          * Switch Tag value should not be identical to either the First Tag
1508          * or Second Tag values. So set something other than common Ethertype
1509          * for internal switching.
1510          */
1511         hw->switch_tag = 0xffff;
1512
1513         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1514         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1515                 PMD_INIT_LOG(ERR, "\nERROR: "
1516                         "Firmware recovery mode detected. Limiting functionality.\n"
1517                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1518                         "User Guide for details on firmware recovery mode.");
1519                 return -EIO;
1520         }
1521
1522         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1523         /* Check if need to support multi-driver */
1524         i40e_support_multi_driver(dev);
1525         /* Check if users want the latest supported vec path */
1526         i40e_use_latest_vec(dev);
1527
1528         /* Make sure all is clean before doing PF reset */
1529         i40e_clear_hw(hw);
1530
1531         /* Reset here to make sure all is clean for each PF */
1532         ret = i40e_pf_reset(hw);
1533         if (ret) {
1534                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1535                 return ret;
1536         }
1537
1538         /* Initialize the shared code (base driver) */
1539         ret = i40e_init_shared_code(hw);
1540         if (ret) {
1541                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1542                 return ret;
1543         }
1544
1545         /* Initialize the parameters for adminq */
1546         i40e_init_adminq_parameter(hw);
1547         ret = i40e_init_adminq(hw);
1548         if (ret != I40E_SUCCESS) {
1549                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1550                 return -EIO;
1551         }
1552         /* Firmware of SFP x722 does not support adminq option */
1553         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1554                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1555
1556         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1557                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1558                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1559                      ((hw->nvm.version >> 12) & 0xf),
1560                      ((hw->nvm.version >> 4) & 0xff),
1561                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1562
1563         /* Initialize the hardware */
1564         i40e_hw_init(dev);
1565
1566         i40e_config_automask(pf);
1567
1568         i40e_set_default_pctype_table(dev);
1569
1570         /*
1571          * To work around the NVM issue, initialize registers
1572          * for packet type of QinQ by software.
1573          * It should be removed once issues are fixed in NVM.
1574          */
1575         if (!pf->support_multi_driver)
1576                 i40e_GLQF_reg_init(hw);
1577
1578         /* Initialize the input set for filters (hash and fd) to default value */
1579         i40e_filter_input_set_init(pf);
1580
1581         /* initialise the L3_MAP register */
1582         if (!pf->support_multi_driver) {
1583                 ret = i40e_aq_debug_write_global_register(hw,
1584                                                    I40E_GLQF_L3_MAP(40),
1585                                                    0x00000028,  NULL);
1586                 if (ret)
1587                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1588                                      ret);
1589                 PMD_INIT_LOG(DEBUG,
1590                              "Global register 0x%08x is changed with 0x28",
1591                              I40E_GLQF_L3_MAP(40));
1592         }
1593
1594         /* Need the special FW version to support floating VEB */
1595         config_floating_veb(dev);
1596         /* Clear PXE mode */
1597         i40e_clear_pxe_mode(hw);
1598         i40e_dev_sync_phy_type(hw);
1599
1600         /*
1601          * On X710, performance number is far from the expectation on recent
1602          * firmware versions. The fix for this issue may not be integrated in
1603          * the following firmware version. So the workaround in software driver
1604          * is needed. It needs to modify the initial values of 3 internal only
1605          * registers. Note that the workaround can be removed when it is fixed
1606          * in firmware in the future.
1607          */
1608         i40e_configure_registers(hw);
1609
1610         /* Get hw capabilities */
1611         ret = i40e_get_cap(hw);
1612         if (ret != I40E_SUCCESS) {
1613                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1614                 goto err_get_capabilities;
1615         }
1616
1617         /* Initialize parameters for PF */
1618         ret = i40e_pf_parameter_init(dev);
1619         if (ret != 0) {
1620                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1621                 goto err_parameter_init;
1622         }
1623
1624         /* Initialize the queue management */
1625         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1626         if (ret < 0) {
1627                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1628                 goto err_qp_pool_init;
1629         }
1630         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1631                                 hw->func_caps.num_msix_vectors - 1);
1632         if (ret < 0) {
1633                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1634                 goto err_msix_pool_init;
1635         }
1636
1637         /* Initialize lan hmc */
1638         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1639                                 hw->func_caps.num_rx_qp, 0, 0);
1640         if (ret != I40E_SUCCESS) {
1641                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1642                 goto err_init_lan_hmc;
1643         }
1644
1645         /* Configure lan hmc */
1646         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1647         if (ret != I40E_SUCCESS) {
1648                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1649                 goto err_configure_lan_hmc;
1650         }
1651
1652         /* Get and check the mac address */
1653         i40e_get_mac_addr(hw, hw->mac.addr);
1654         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1655                 PMD_INIT_LOG(ERR, "mac address is not valid");
1656                 ret = -EIO;
1657                 goto err_get_mac_addr;
1658         }
1659         /* Copy the permanent MAC address */
1660         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1661                         (struct rte_ether_addr *)hw->mac.perm_addr);
1662
1663         /* Disable flow control */
1664         hw->fc.requested_mode = I40E_FC_NONE;
1665         i40e_set_fc(hw, &aq_fail, TRUE);
1666
1667         /* Set the global registers with default ether type value */
1668         if (!pf->support_multi_driver) {
1669                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1670                                          RTE_ETHER_TYPE_VLAN);
1671                 if (ret != I40E_SUCCESS) {
1672                         PMD_INIT_LOG(ERR,
1673                                      "Failed to set the default outer "
1674                                      "VLAN ether type");
1675                         goto err_setup_pf_switch;
1676                 }
1677         }
1678
1679         /* PF setup, which includes VSI setup */
1680         ret = i40e_pf_setup(pf);
1681         if (ret) {
1682                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1683                 goto err_setup_pf_switch;
1684         }
1685
1686         vsi = pf->main_vsi;
1687
1688         /* Disable double vlan by default */
1689         i40e_vsi_config_double_vlan(vsi, FALSE);
1690
1691         /* Disable S-TAG identification when floating_veb is disabled */
1692         if (!pf->floating_veb) {
1693                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1694                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1695                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1696                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1697                 }
1698         }
1699
1700         if (!vsi->max_macaddrs)
1701                 len = RTE_ETHER_ADDR_LEN;
1702         else
1703                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1704
1705         /* Should be after VSI initialized */
1706         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1707         if (!dev->data->mac_addrs) {
1708                 PMD_INIT_LOG(ERR,
1709                         "Failed to allocated memory for storing mac address");
1710                 goto err_mac_alloc;
1711         }
1712         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1713                                         &dev->data->mac_addrs[0]);
1714
1715         /* Init dcb to sw mode by default */
1716         ret = i40e_dcb_init_configure(dev, TRUE);
1717         if (ret != I40E_SUCCESS) {
1718                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1719                 pf->flags &= ~I40E_FLAG_DCB;
1720         }
1721         /* Update HW struct after DCB configuration */
1722         i40e_get_cap(hw);
1723
1724         /* initialize pf host driver to setup SRIOV resource if applicable */
1725         i40e_pf_host_init(dev);
1726
1727         /* register callback func to eal lib */
1728         rte_intr_callback_register(intr_handle,
1729                                    i40e_dev_interrupt_handler, dev);
1730
1731         /* configure and enable device interrupt */
1732         i40e_pf_config_irq0(hw, TRUE);
1733         i40e_pf_enable_irq0(hw);
1734
1735         /* enable uio intr after callback register */
1736         rte_intr_enable(intr_handle);
1737
1738         /* By default disable flexible payload in global configuration */
1739         if (!pf->support_multi_driver)
1740                 i40e_flex_payload_reg_set_default(hw);
1741
1742         /*
1743          * Add an ethertype filter to drop all flow control frames transmitted
1744          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1745          * frames to wire.
1746          */
1747         i40e_add_tx_flow_control_drop_filter(pf);
1748
1749         /* Set the max frame size to 0x2600 by default,
1750          * in case other drivers changed the default value.
1751          */
1752         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1753
1754         /* initialize mirror rule list */
1755         TAILQ_INIT(&pf->mirror_list);
1756
1757         /* initialize RSS rule list */
1758         TAILQ_INIT(&pf->rss_config_list);
1759
1760         /* initialize Traffic Manager configuration */
1761         i40e_tm_conf_init(dev);
1762
1763         /* Initialize customized information */
1764         i40e_init_customized_info(pf);
1765
1766         /* Initialize the filter invalidation configuration */
1767         i40e_init_filter_invalidation(pf);
1768
1769         ret = i40e_init_ethtype_filter_list(dev);
1770         if (ret < 0)
1771                 goto err_init_ethtype_filter_list;
1772         ret = i40e_init_tunnel_filter_list(dev);
1773         if (ret < 0)
1774                 goto err_init_tunnel_filter_list;
1775         ret = i40e_init_fdir_filter_list(dev);
1776         if (ret < 0)
1777                 goto err_init_fdir_filter_list;
1778
1779         /* initialize queue region configuration */
1780         i40e_init_queue_region_conf(dev);
1781
1782         /* initialize RSS configuration from rte_flow */
1783         memset(&pf->rss_info, 0,
1784                 sizeof(struct i40e_rte_flow_rss_conf));
1785
1786         /* reset all stats of the device, including pf and main vsi */
1787         i40e_dev_stats_reset(dev);
1788
1789         return 0;
1790
1791 err_init_fdir_filter_list:
1792         rte_free(pf->tunnel.hash_table);
1793         rte_free(pf->tunnel.hash_map);
1794 err_init_tunnel_filter_list:
1795         rte_free(pf->ethertype.hash_table);
1796         rte_free(pf->ethertype.hash_map);
1797 err_init_ethtype_filter_list:
1798         rte_free(dev->data->mac_addrs);
1799         dev->data->mac_addrs = NULL;
1800 err_mac_alloc:
1801         i40e_vsi_release(pf->main_vsi);
1802 err_setup_pf_switch:
1803 err_get_mac_addr:
1804 err_configure_lan_hmc:
1805         (void)i40e_shutdown_lan_hmc(hw);
1806 err_init_lan_hmc:
1807         i40e_res_pool_destroy(&pf->msix_pool);
1808 err_msix_pool_init:
1809         i40e_res_pool_destroy(&pf->qp_pool);
1810 err_qp_pool_init:
1811 err_parameter_init:
1812 err_get_capabilities:
1813         (void)i40e_shutdown_adminq(hw);
1814
1815         return ret;
1816 }
1817
1818 static void
1819 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1820 {
1821         struct i40e_ethertype_filter *p_ethertype;
1822         struct i40e_ethertype_rule *ethertype_rule;
1823
1824         ethertype_rule = &pf->ethertype;
1825         /* Remove all ethertype filter rules and hash */
1826         if (ethertype_rule->hash_map)
1827                 rte_free(ethertype_rule->hash_map);
1828         if (ethertype_rule->hash_table)
1829                 rte_hash_free(ethertype_rule->hash_table);
1830
1831         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1832                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1833                              p_ethertype, rules);
1834                 rte_free(p_ethertype);
1835         }
1836 }
1837
1838 static void
1839 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1840 {
1841         struct i40e_tunnel_filter *p_tunnel;
1842         struct i40e_tunnel_rule *tunnel_rule;
1843
1844         tunnel_rule = &pf->tunnel;
1845         /* Remove all tunnel director rules and hash */
1846         if (tunnel_rule->hash_map)
1847                 rte_free(tunnel_rule->hash_map);
1848         if (tunnel_rule->hash_table)
1849                 rte_hash_free(tunnel_rule->hash_table);
1850
1851         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1852                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1853                 rte_free(p_tunnel);
1854         }
1855 }
1856
1857 static void
1858 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1859 {
1860         struct i40e_fdir_filter *p_fdir;
1861         struct i40e_fdir_info *fdir_info;
1862
1863         fdir_info = &pf->fdir;
1864
1865         /* Remove all flow director rules */
1866         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1867                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1868 }
1869
1870 static void
1871 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1872 {
1873         struct i40e_fdir_info *fdir_info;
1874
1875         fdir_info = &pf->fdir;
1876
1877         /* flow director memory cleanup */
1878         if (fdir_info->hash_map)
1879                 rte_free(fdir_info->hash_map);
1880         if (fdir_info->hash_table)
1881                 rte_hash_free(fdir_info->hash_table);
1882         if (fdir_info->fdir_flow_pool.bitmap)
1883                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1884         if (fdir_info->fdir_flow_pool.pool)
1885                 rte_free(fdir_info->fdir_flow_pool.pool);
1886         if (fdir_info->fdir_filter_array)
1887                 rte_free(fdir_info->fdir_filter_array);
1888 }
1889
1890 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1891 {
1892         /*
1893          * Disable by default flexible payload
1894          * for corresponding L2/L3/L4 layers.
1895          */
1896         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1897         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1898         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1899 }
1900
1901 static int
1902 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1903 {
1904         struct i40e_hw *hw;
1905
1906         PMD_INIT_FUNC_TRACE();
1907
1908         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1909                 return 0;
1910
1911         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1912
1913         if (hw->adapter_closed == 0)
1914                 i40e_dev_close(dev);
1915
1916         return 0;
1917 }
1918
1919 static int
1920 i40e_dev_configure(struct rte_eth_dev *dev)
1921 {
1922         struct i40e_adapter *ad =
1923                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1927         int i, ret;
1928
1929         ret = i40e_dev_sync_phy_type(hw);
1930         if (ret)
1931                 return ret;
1932
1933         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1934          * bulk allocation or vector Rx preconditions we will reset it.
1935          */
1936         ad->rx_bulk_alloc_allowed = true;
1937         ad->rx_vec_allowed = true;
1938         ad->tx_simple_allowed = true;
1939         ad->tx_vec_allowed = true;
1940
1941         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1942                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1943
1944         /* Only legacy filter API needs the following fdir config. So when the
1945          * legacy filter API is deprecated, the following codes should also be
1946          * removed.
1947          */
1948         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1949                 ret = i40e_fdir_setup(pf);
1950                 if (ret != I40E_SUCCESS) {
1951                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1952                         return -ENOTSUP;
1953                 }
1954                 ret = i40e_fdir_configure(dev);
1955                 if (ret < 0) {
1956                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1957                         goto err;
1958                 }
1959         } else
1960                 i40e_fdir_teardown(pf);
1961
1962         ret = i40e_dev_init_vlan(dev);
1963         if (ret < 0)
1964                 goto err;
1965
1966         /* VMDQ setup.
1967          *  General PMD driver call sequence are NIC init, configure,
1968          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1969          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1970          *  applicable. So, VMDQ setting has to be done before
1971          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1972          *  For RSS setting, it will try to calculate actual configured RX queue
1973          *  number, which will be available after rx_queue_setup(). dev_start()
1974          *  function is good to place RSS setup.
1975          */
1976         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1977                 ret = i40e_vmdq_setup(dev);
1978                 if (ret)
1979                         goto err;
1980         }
1981
1982         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1983                 ret = i40e_dcb_setup(dev);
1984                 if (ret) {
1985                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1986                         goto err_dcb;
1987                 }
1988         }
1989
1990         TAILQ_INIT(&pf->flow_list);
1991
1992         return 0;
1993
1994 err_dcb:
1995         /* need to release vmdq resource if exists */
1996         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1997                 i40e_vsi_release(pf->vmdq[i].vsi);
1998                 pf->vmdq[i].vsi = NULL;
1999         }
2000         rte_free(pf->vmdq);
2001         pf->vmdq = NULL;
2002 err:
2003         /* Need to release fdir resource if exists.
2004          * Only legacy filter API needs the following fdir config. So when the
2005          * legacy filter API is deprecated, the following code should also be
2006          * removed.
2007          */
2008         i40e_fdir_teardown(pf);
2009         return ret;
2010 }
2011
2012 void
2013 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2014 {
2015         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2016         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2017         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2018         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2019         uint16_t msix_vect = vsi->msix_intr;
2020         uint16_t i;
2021
2022         for (i = 0; i < vsi->nb_qps; i++) {
2023                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2024                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2025                 rte_wmb();
2026         }
2027
2028         if (vsi->type != I40E_VSI_SRIOV) {
2029                 if (!rte_intr_allow_others(intr_handle)) {
2030                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2031                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2032                         I40E_WRITE_REG(hw,
2033                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2034                                        0);
2035                 } else {
2036                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2037                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2038                         I40E_WRITE_REG(hw,
2039                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2040                                                        msix_vect - 1), 0);
2041                 }
2042         } else {
2043                 uint32_t reg;
2044                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2045                         vsi->user_param + (msix_vect - 1);
2046
2047                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2048                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2049         }
2050         I40E_WRITE_FLUSH(hw);
2051 }
2052
2053 static void
2054 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2055                        int base_queue, int nb_queue,
2056                        uint16_t itr_idx)
2057 {
2058         int i;
2059         uint32_t val;
2060         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2061         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2062
2063         /* Bind all RX queues to allocated MSIX interrupt */
2064         for (i = 0; i < nb_queue; i++) {
2065                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2066                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2067                         ((base_queue + i + 1) <<
2068                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2069                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2070                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2071
2072                 if (i == nb_queue - 1)
2073                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2074                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2075         }
2076
2077         /* Write first RX queue to Link list register as the head element */
2078         if (vsi->type != I40E_VSI_SRIOV) {
2079                 uint16_t interval =
2080                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2081
2082                 if (msix_vect == I40E_MISC_VEC_ID) {
2083                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2084                                        (base_queue <<
2085                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2086                                        (0x0 <<
2087                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2088                         I40E_WRITE_REG(hw,
2089                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2090                                        interval);
2091                 } else {
2092                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2093                                        (base_queue <<
2094                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2095                                        (0x0 <<
2096                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2097                         I40E_WRITE_REG(hw,
2098                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2099                                                        msix_vect - 1),
2100                                        interval);
2101                 }
2102         } else {
2103                 uint32_t reg;
2104
2105                 if (msix_vect == I40E_MISC_VEC_ID) {
2106                         I40E_WRITE_REG(hw,
2107                                        I40E_VPINT_LNKLST0(vsi->user_param),
2108                                        (base_queue <<
2109                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2110                                        (0x0 <<
2111                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2112                 } else {
2113                         /* num_msix_vectors_vf needs to minus irq0 */
2114                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2115                                 vsi->user_param + (msix_vect - 1);
2116
2117                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2118                                        (base_queue <<
2119                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2120                                        (0x0 <<
2121                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2122                 }
2123         }
2124
2125         I40E_WRITE_FLUSH(hw);
2126 }
2127
2128 int
2129 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2130 {
2131         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2132         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2133         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2134         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2135         uint16_t msix_vect = vsi->msix_intr;
2136         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2137         uint16_t queue_idx = 0;
2138         int record = 0;
2139         int i;
2140
2141         for (i = 0; i < vsi->nb_qps; i++) {
2142                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2143                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2144         }
2145
2146         /* VF bind interrupt */
2147         if (vsi->type == I40E_VSI_SRIOV) {
2148                 if (vsi->nb_msix == 0) {
2149                         PMD_DRV_LOG(ERR, "No msix resource");
2150                         return -EINVAL;
2151                 }
2152                 __vsi_queues_bind_intr(vsi, msix_vect,
2153                                        vsi->base_queue, vsi->nb_qps,
2154                                        itr_idx);
2155                 return 0;
2156         }
2157
2158         /* PF & VMDq bind interrupt */
2159         if (rte_intr_dp_is_en(intr_handle)) {
2160                 if (vsi->type == I40E_VSI_MAIN) {
2161                         queue_idx = 0;
2162                         record = 1;
2163                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2164                         struct i40e_vsi *main_vsi =
2165                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2166                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2167                         record = 1;
2168                 }
2169         }
2170
2171         for (i = 0; i < vsi->nb_used_qps; i++) {
2172                 if (vsi->nb_msix == 0) {
2173                         PMD_DRV_LOG(ERR, "No msix resource");
2174                         return -EINVAL;
2175                 } else if (nb_msix <= 1) {
2176                         if (!rte_intr_allow_others(intr_handle))
2177                                 /* allow to share MISC_VEC_ID */
2178                                 msix_vect = I40E_MISC_VEC_ID;
2179
2180                         /* no enough msix_vect, map all to one */
2181                         __vsi_queues_bind_intr(vsi, msix_vect,
2182                                                vsi->base_queue + i,
2183                                                vsi->nb_used_qps - i,
2184                                                itr_idx);
2185                         for (; !!record && i < vsi->nb_used_qps; i++)
2186                                 intr_handle->intr_vec[queue_idx + i] =
2187                                         msix_vect;
2188                         break;
2189                 }
2190                 /* 1:1 queue/msix_vect mapping */
2191                 __vsi_queues_bind_intr(vsi, msix_vect,
2192                                        vsi->base_queue + i, 1,
2193                                        itr_idx);
2194                 if (!!record)
2195                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2196
2197                 msix_vect++;
2198                 nb_msix--;
2199         }
2200
2201         return 0;
2202 }
2203
2204 void
2205 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2206 {
2207         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2208         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2209         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2210         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2211         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2212         uint16_t msix_intr, i;
2213
2214         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2215                 for (i = 0; i < vsi->nb_msix; i++) {
2216                         msix_intr = vsi->msix_intr + i;
2217                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2218                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2219                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2220                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2221                 }
2222         else
2223                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2224                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2225                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2226                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2227
2228         I40E_WRITE_FLUSH(hw);
2229 }
2230
2231 void
2232 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2233 {
2234         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2235         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2236         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2237         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2238         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2239         uint16_t msix_intr, i;
2240
2241         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2242                 for (i = 0; i < vsi->nb_msix; i++) {
2243                         msix_intr = vsi->msix_intr + i;
2244                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2245                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2246                 }
2247         else
2248                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2249                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2250
2251         I40E_WRITE_FLUSH(hw);
2252 }
2253
2254 static inline uint8_t
2255 i40e_parse_link_speeds(uint16_t link_speeds)
2256 {
2257         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2258
2259         if (link_speeds & ETH_LINK_SPEED_40G)
2260                 link_speed |= I40E_LINK_SPEED_40GB;
2261         if (link_speeds & ETH_LINK_SPEED_25G)
2262                 link_speed |= I40E_LINK_SPEED_25GB;
2263         if (link_speeds & ETH_LINK_SPEED_20G)
2264                 link_speed |= I40E_LINK_SPEED_20GB;
2265         if (link_speeds & ETH_LINK_SPEED_10G)
2266                 link_speed |= I40E_LINK_SPEED_10GB;
2267         if (link_speeds & ETH_LINK_SPEED_1G)
2268                 link_speed |= I40E_LINK_SPEED_1GB;
2269         if (link_speeds & ETH_LINK_SPEED_100M)
2270                 link_speed |= I40E_LINK_SPEED_100MB;
2271
2272         return link_speed;
2273 }
2274
2275 static int
2276 i40e_phy_conf_link(struct i40e_hw *hw,
2277                    uint8_t abilities,
2278                    uint8_t force_speed,
2279                    bool is_up)
2280 {
2281         enum i40e_status_code status;
2282         struct i40e_aq_get_phy_abilities_resp phy_ab;
2283         struct i40e_aq_set_phy_config phy_conf;
2284         enum i40e_aq_phy_type cnt;
2285         uint8_t avail_speed;
2286         uint32_t phy_type_mask = 0;
2287
2288         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2289                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2290                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2291                         I40E_AQ_PHY_FLAG_LOW_POWER;
2292         int ret = -ENOTSUP;
2293
2294         /* To get phy capabilities of available speeds. */
2295         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2296                                               NULL);
2297         if (status) {
2298                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2299                                 status);
2300                 return ret;
2301         }
2302         avail_speed = phy_ab.link_speed;
2303
2304         /* To get the current phy config. */
2305         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2306                                               NULL);
2307         if (status) {
2308                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2309                                 status);
2310                 return ret;
2311         }
2312
2313         /* If link needs to go up and it is in autoneg mode the speed is OK,
2314          * no need to set up again.
2315          */
2316         if (is_up && phy_ab.phy_type != 0 &&
2317                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2318                      phy_ab.link_speed != 0)
2319                 return I40E_SUCCESS;
2320
2321         memset(&phy_conf, 0, sizeof(phy_conf));
2322
2323         /* bits 0-2 use the values from get_phy_abilities_resp */
2324         abilities &= ~mask;
2325         abilities |= phy_ab.abilities & mask;
2326
2327         phy_conf.abilities = abilities;
2328
2329         /* If link needs to go up, but the force speed is not supported,
2330          * Warn users and config the default available speeds.
2331          */
2332         if (is_up && !(force_speed & avail_speed)) {
2333                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2334                 phy_conf.link_speed = avail_speed;
2335         } else {
2336                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2337         }
2338
2339         /* PHY type mask needs to include each type except PHY type extension */
2340         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2341                 phy_type_mask |= 1 << cnt;
2342
2343         /* use get_phy_abilities_resp value for the rest */
2344         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2345         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2346                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2347                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2348         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2349         phy_conf.eee_capability = phy_ab.eee_capability;
2350         phy_conf.eeer = phy_ab.eeer_val;
2351         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2352
2353         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2354                     phy_ab.abilities, phy_ab.link_speed);
2355         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2356                     phy_conf.abilities, phy_conf.link_speed);
2357
2358         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2359         if (status)
2360                 return ret;
2361
2362         return I40E_SUCCESS;
2363 }
2364
2365 static int
2366 i40e_apply_link_speed(struct rte_eth_dev *dev)
2367 {
2368         uint8_t speed;
2369         uint8_t abilities = 0;
2370         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         struct rte_eth_conf *conf = &dev->data->dev_conf;
2372
2373         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2374                      I40E_AQ_PHY_LINK_ENABLED;
2375
2376         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2377                 conf->link_speeds = ETH_LINK_SPEED_40G |
2378                                     ETH_LINK_SPEED_25G |
2379                                     ETH_LINK_SPEED_20G |
2380                                     ETH_LINK_SPEED_10G |
2381                                     ETH_LINK_SPEED_1G |
2382                                     ETH_LINK_SPEED_100M;
2383
2384                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2385         } else {
2386                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2387         }
2388         speed = i40e_parse_link_speeds(conf->link_speeds);
2389
2390         return i40e_phy_conf_link(hw, abilities, speed, true);
2391 }
2392
2393 static int
2394 i40e_dev_start(struct rte_eth_dev *dev)
2395 {
2396         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2397         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2398         struct i40e_vsi *main_vsi = pf->main_vsi;
2399         int ret, i;
2400         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2401         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2402         uint32_t intr_vector = 0;
2403         struct i40e_vsi *vsi;
2404         uint16_t nb_rxq, nb_txq;
2405
2406         hw->adapter_stopped = 0;
2407
2408         rte_intr_disable(intr_handle);
2409
2410         if ((rte_intr_cap_multiple(intr_handle) ||
2411              !RTE_ETH_DEV_SRIOV(dev).active) &&
2412             dev->data->dev_conf.intr_conf.rxq != 0) {
2413                 intr_vector = dev->data->nb_rx_queues;
2414                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2415                 if (ret)
2416                         return ret;
2417         }
2418
2419         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2420                 intr_handle->intr_vec =
2421                         rte_zmalloc("intr_vec",
2422                                     dev->data->nb_rx_queues * sizeof(int),
2423                                     0);
2424                 if (!intr_handle->intr_vec) {
2425                         PMD_INIT_LOG(ERR,
2426                                 "Failed to allocate %d rx_queues intr_vec",
2427                                 dev->data->nb_rx_queues);
2428                         return -ENOMEM;
2429                 }
2430         }
2431
2432         /* Initialize VSI */
2433         ret = i40e_dev_rxtx_init(pf);
2434         if (ret != I40E_SUCCESS) {
2435                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2436                 return ret;
2437         }
2438
2439         /* Map queues with MSIX interrupt */
2440         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2441                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2442         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2443         if (ret < 0)
2444                 return ret;
2445         i40e_vsi_enable_queues_intr(main_vsi);
2446
2447         /* Map VMDQ VSI queues with MSIX interrupt */
2448         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2449                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2450                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2451                                                 I40E_ITR_INDEX_DEFAULT);
2452                 if (ret < 0)
2453                         return ret;
2454                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2455         }
2456
2457         /* Enable all queues which have been configured */
2458         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2459                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2460                 if (ret)
2461                         goto rx_err;
2462         }
2463
2464         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2465                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2466                 if (ret)
2467                         goto tx_err;
2468         }
2469
2470         /* Enable receiving broadcast packets */
2471         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2472         if (ret != I40E_SUCCESS)
2473                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2474
2475         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2476                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2477                                                 true, NULL);
2478                 if (ret != I40E_SUCCESS)
2479                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2480         }
2481
2482         /* Enable the VLAN promiscuous mode. */
2483         if (pf->vfs) {
2484                 for (i = 0; i < pf->vf_num; i++) {
2485                         vsi = pf->vfs[i].vsi;
2486                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2487                                                      true, NULL);
2488                 }
2489         }
2490
2491         /* Enable mac loopback mode */
2492         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2493             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2494                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2495                 if (ret != I40E_SUCCESS) {
2496                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2497                         goto tx_err;
2498                 }
2499         }
2500
2501         /* Apply link configure */
2502         ret = i40e_apply_link_speed(dev);
2503         if (I40E_SUCCESS != ret) {
2504                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2505                 goto tx_err;
2506         }
2507
2508         if (!rte_intr_allow_others(intr_handle)) {
2509                 rte_intr_callback_unregister(intr_handle,
2510                                              i40e_dev_interrupt_handler,
2511                                              (void *)dev);
2512                 /* configure and enable device interrupt */
2513                 i40e_pf_config_irq0(hw, FALSE);
2514                 i40e_pf_enable_irq0(hw);
2515
2516                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2517                         PMD_INIT_LOG(INFO,
2518                                 "lsc won't enable because of no intr multiplex");
2519         } else {
2520                 ret = i40e_aq_set_phy_int_mask(hw,
2521                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2522                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2523                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2524                 if (ret != I40E_SUCCESS)
2525                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2526
2527                 /* Call get_link_info aq commond to enable/disable LSE */
2528                 i40e_dev_link_update(dev, 0);
2529         }
2530
2531         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2532                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2533                                   i40e_dev_alarm_handler, dev);
2534         } else {
2535                 /* enable uio intr after callback register */
2536                 rte_intr_enable(intr_handle);
2537         }
2538
2539         i40e_filter_restore(pf);
2540
2541         if (pf->tm_conf.root && !pf->tm_conf.committed)
2542                 PMD_DRV_LOG(WARNING,
2543                             "please call hierarchy_commit() "
2544                             "before starting the port");
2545
2546         return I40E_SUCCESS;
2547
2548 tx_err:
2549         for (i = 0; i < nb_txq; i++)
2550                 i40e_dev_tx_queue_stop(dev, i);
2551 rx_err:
2552         for (i = 0; i < nb_rxq; i++)
2553                 i40e_dev_rx_queue_stop(dev, i);
2554
2555         return ret;
2556 }
2557
2558 static int
2559 i40e_dev_stop(struct rte_eth_dev *dev)
2560 {
2561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2562         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2563         struct i40e_vsi *main_vsi = pf->main_vsi;
2564         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2565         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2566         int i;
2567
2568         if (hw->adapter_stopped == 1)
2569                 return 0;
2570
2571         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2572                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2573                 rte_intr_enable(intr_handle);
2574         }
2575
2576         /* Disable all queues */
2577         for (i = 0; i < dev->data->nb_tx_queues; i++)
2578                 i40e_dev_tx_queue_stop(dev, i);
2579
2580         for (i = 0; i < dev->data->nb_rx_queues; i++)
2581                 i40e_dev_rx_queue_stop(dev, i);
2582
2583         /* un-map queues with interrupt registers */
2584         i40e_vsi_disable_queues_intr(main_vsi);
2585         i40e_vsi_queues_unbind_intr(main_vsi);
2586
2587         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2588                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2589                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2590         }
2591
2592         /* Clear all queues and release memory */
2593         i40e_dev_clear_queues(dev);
2594
2595         /* Set link down */
2596         i40e_dev_set_link_down(dev);
2597
2598         if (!rte_intr_allow_others(intr_handle))
2599                 /* resume to the default handler */
2600                 rte_intr_callback_register(intr_handle,
2601                                            i40e_dev_interrupt_handler,
2602                                            (void *)dev);
2603
2604         /* Clean datapath event and queue/vec mapping */
2605         rte_intr_efd_disable(intr_handle);
2606         if (intr_handle->intr_vec) {
2607                 rte_free(intr_handle->intr_vec);
2608                 intr_handle->intr_vec = NULL;
2609         }
2610
2611         /* reset hierarchy commit */
2612         pf->tm_conf.committed = false;
2613
2614         hw->adapter_stopped = 1;
2615         dev->data->dev_started = 0;
2616
2617         pf->adapter->rss_reta_updated = 0;
2618
2619         return 0;
2620 }
2621
2622 static int
2623 i40e_dev_close(struct rte_eth_dev *dev)
2624 {
2625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2626         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2627         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2628         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2629         struct i40e_mirror_rule *p_mirror;
2630         struct i40e_filter_control_settings settings;
2631         struct rte_flow *p_flow;
2632         uint32_t reg;
2633         int i;
2634         int ret;
2635         uint8_t aq_fail = 0;
2636         int retries = 0;
2637
2638         PMD_INIT_FUNC_TRACE();
2639         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2640                 return 0;
2641
2642         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2643         if (ret)
2644                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2645
2646
2647         ret = i40e_dev_stop(dev);
2648
2649         /* Remove all mirror rules */
2650         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2651                 ret = i40e_aq_del_mirror_rule(hw,
2652                                               pf->main_vsi->veb->seid,
2653                                               p_mirror->rule_type,
2654                                               p_mirror->entries,
2655                                               p_mirror->num_entries,
2656                                               p_mirror->id);
2657                 if (ret < 0)
2658                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2659                                     "status = %d, aq_err = %d.", ret,
2660                                     hw->aq.asq_last_status);
2661
2662                 /* remove mirror software resource anyway */
2663                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2664                 rte_free(p_mirror);
2665                 pf->nb_mirror_rule--;
2666         }
2667
2668         i40e_dev_free_queues(dev);
2669
2670         /* Disable interrupt */
2671         i40e_pf_disable_irq0(hw);
2672         rte_intr_disable(intr_handle);
2673
2674         /*
2675          * Only legacy filter API needs the following fdir config. So when the
2676          * legacy filter API is deprecated, the following code should also be
2677          * removed.
2678          */
2679         i40e_fdir_teardown(pf);
2680
2681         /* shutdown and destroy the HMC */
2682         i40e_shutdown_lan_hmc(hw);
2683
2684         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2685                 i40e_vsi_release(pf->vmdq[i].vsi);
2686                 pf->vmdq[i].vsi = NULL;
2687         }
2688         rte_free(pf->vmdq);
2689         pf->vmdq = NULL;
2690
2691         /* release all the existing VSIs and VEBs */
2692         i40e_vsi_release(pf->main_vsi);
2693
2694         /* shutdown the adminq */
2695         i40e_aq_queue_shutdown(hw, true);
2696         i40e_shutdown_adminq(hw);
2697
2698         i40e_res_pool_destroy(&pf->qp_pool);
2699         i40e_res_pool_destroy(&pf->msix_pool);
2700
2701         /* Disable flexible payload in global configuration */
2702         if (!pf->support_multi_driver)
2703                 i40e_flex_payload_reg_set_default(hw);
2704
2705         /* force a PF reset to clean anything leftover */
2706         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2707         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2708                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2709         I40E_WRITE_FLUSH(hw);
2710
2711         /* Clear PXE mode */
2712         i40e_clear_pxe_mode(hw);
2713
2714         /* Unconfigure filter control */
2715         memset(&settings, 0, sizeof(settings));
2716         ret = i40e_set_filter_control(hw, &settings);
2717         if (ret)
2718                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2719                                         ret);
2720
2721         /* Disable flow control */
2722         hw->fc.requested_mode = I40E_FC_NONE;
2723         i40e_set_fc(hw, &aq_fail, TRUE);
2724
2725         /* uninitialize pf host driver */
2726         i40e_pf_host_uninit(dev);
2727
2728         do {
2729                 ret = rte_intr_callback_unregister(intr_handle,
2730                                 i40e_dev_interrupt_handler, dev);
2731                 if (ret >= 0 || ret == -ENOENT) {
2732                         break;
2733                 } else if (ret != -EAGAIN) {
2734                         PMD_INIT_LOG(ERR,
2735                                  "intr callback unregister failed: %d",
2736                                  ret);
2737                 }
2738                 i40e_msec_delay(500);
2739         } while (retries++ < 5);
2740
2741         i40e_rm_ethtype_filter_list(pf);
2742         i40e_rm_tunnel_filter_list(pf);
2743         i40e_rm_fdir_filter_list(pf);
2744
2745         /* Remove all flows */
2746         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2747                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2748                 /* Do not free FDIR flows since they are static allocated */
2749                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2750                         rte_free(p_flow);
2751         }
2752
2753         /* release the fdir static allocated memory */
2754         i40e_fdir_memory_cleanup(pf);
2755
2756         /* Remove all Traffic Manager configuration */
2757         i40e_tm_conf_uninit(dev);
2758
2759         i40e_clear_automask(pf);
2760
2761         hw->adapter_closed = 1;
2762         return ret;
2763 }
2764
2765 /*
2766  * Reset PF device only to re-initialize resources in PMD layer
2767  */
2768 static int
2769 i40e_dev_reset(struct rte_eth_dev *dev)
2770 {
2771         int ret;
2772
2773         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2774          * its VF to make them align with it. The detailed notification
2775          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2776          * To avoid unexpected behavior in VF, currently reset of PF with
2777          * SR-IOV activation is not supported. It might be supported later.
2778          */
2779         if (dev->data->sriov.active)
2780                 return -ENOTSUP;
2781
2782         ret = eth_i40e_dev_uninit(dev);
2783         if (ret)
2784                 return ret;
2785
2786         ret = eth_i40e_dev_init(dev, NULL);
2787
2788         return ret;
2789 }
2790
2791 static int
2792 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2793 {
2794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796         struct i40e_vsi *vsi = pf->main_vsi;
2797         int status;
2798
2799         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2800                                                      true, NULL, true);
2801         if (status != I40E_SUCCESS) {
2802                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2803                 return -EAGAIN;
2804         }
2805
2806         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2807                                                         TRUE, NULL);
2808         if (status != I40E_SUCCESS) {
2809                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2810                 /* Rollback unicast promiscuous mode */
2811                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2812                                                     false, NULL, true);
2813                 return -EAGAIN;
2814         }
2815
2816         return 0;
2817 }
2818
2819 static int
2820 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2821 {
2822         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2823         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2824         struct i40e_vsi *vsi = pf->main_vsi;
2825         int status;
2826
2827         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2828                                                      false, NULL, true);
2829         if (status != I40E_SUCCESS) {
2830                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2831                 return -EAGAIN;
2832         }
2833
2834         /* must remain in all_multicast mode */
2835         if (dev->data->all_multicast == 1)
2836                 return 0;
2837
2838         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2839                                                         false, NULL);
2840         if (status != I40E_SUCCESS) {
2841                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2842                 /* Rollback unicast promiscuous mode */
2843                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2844                                                     true, NULL, true);
2845                 return -EAGAIN;
2846         }
2847
2848         return 0;
2849 }
2850
2851 static int
2852 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2853 {
2854         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2855         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856         struct i40e_vsi *vsi = pf->main_vsi;
2857         int ret;
2858
2859         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2860         if (ret != I40E_SUCCESS) {
2861                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2862                 return -EAGAIN;
2863         }
2864
2865         return 0;
2866 }
2867
2868 static int
2869 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2870 {
2871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         struct i40e_vsi *vsi = pf->main_vsi;
2874         int ret;
2875
2876         if (dev->data->promiscuous == 1)
2877                 return 0; /* must remain in all_multicast mode */
2878
2879         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2880                                 vsi->seid, FALSE, NULL);
2881         if (ret != I40E_SUCCESS) {
2882                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2883                 return -EAGAIN;
2884         }
2885
2886         return 0;
2887 }
2888
2889 /*
2890  * Set device link up.
2891  */
2892 static int
2893 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2894 {
2895         /* re-apply link speed setting */
2896         return i40e_apply_link_speed(dev);
2897 }
2898
2899 /*
2900  * Set device link down.
2901  */
2902 static int
2903 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2904 {
2905         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2906         uint8_t abilities = 0;
2907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2908
2909         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2910         return i40e_phy_conf_link(hw, abilities, speed, false);
2911 }
2912
2913 static __rte_always_inline void
2914 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2915 {
2916 /* Link status registers and values*/
2917 #define I40E_PRTMAC_LINKSTA             0x001E2420
2918 #define I40E_REG_LINK_UP                0x40000080
2919 #define I40E_PRTMAC_MACC                0x001E24E0
2920 #define I40E_REG_MACC_25GB              0x00020000
2921 #define I40E_REG_SPEED_MASK             0x38000000
2922 #define I40E_REG_SPEED_0                0x00000000
2923 #define I40E_REG_SPEED_1                0x08000000
2924 #define I40E_REG_SPEED_2                0x10000000
2925 #define I40E_REG_SPEED_3                0x18000000
2926 #define I40E_REG_SPEED_4                0x20000000
2927         uint32_t link_speed;
2928         uint32_t reg_val;
2929
2930         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2931         link_speed = reg_val & I40E_REG_SPEED_MASK;
2932         reg_val &= I40E_REG_LINK_UP;
2933         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2934
2935         if (unlikely(link->link_status == 0))
2936                 return;
2937
2938         /* Parse the link status */
2939         switch (link_speed) {
2940         case I40E_REG_SPEED_0:
2941                 link->link_speed = ETH_SPEED_NUM_100M;
2942                 break;
2943         case I40E_REG_SPEED_1:
2944                 link->link_speed = ETH_SPEED_NUM_1G;
2945                 break;
2946         case I40E_REG_SPEED_2:
2947                 if (hw->mac.type == I40E_MAC_X722)
2948                         link->link_speed = ETH_SPEED_NUM_2_5G;
2949                 else
2950                         link->link_speed = ETH_SPEED_NUM_10G;
2951                 break;
2952         case I40E_REG_SPEED_3:
2953                 if (hw->mac.type == I40E_MAC_X722) {
2954                         link->link_speed = ETH_SPEED_NUM_5G;
2955                 } else {
2956                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2957
2958                         if (reg_val & I40E_REG_MACC_25GB)
2959                                 link->link_speed = ETH_SPEED_NUM_25G;
2960                         else
2961                                 link->link_speed = ETH_SPEED_NUM_40G;
2962                 }
2963                 break;
2964         case I40E_REG_SPEED_4:
2965                 if (hw->mac.type == I40E_MAC_X722)
2966                         link->link_speed = ETH_SPEED_NUM_10G;
2967                 else
2968                         link->link_speed = ETH_SPEED_NUM_20G;
2969                 break;
2970         default:
2971                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2972                 break;
2973         }
2974 }
2975
2976 static __rte_always_inline void
2977 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2978         bool enable_lse, int wait_to_complete)
2979 {
2980 #define CHECK_INTERVAL             100  /* 100ms */
2981 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2982         uint32_t rep_cnt = MAX_REPEAT_TIME;
2983         struct i40e_link_status link_status;
2984         int status;
2985
2986         memset(&link_status, 0, sizeof(link_status));
2987
2988         do {
2989                 memset(&link_status, 0, sizeof(link_status));
2990
2991                 /* Get link status information from hardware */
2992                 status = i40e_aq_get_link_info(hw, enable_lse,
2993                                                 &link_status, NULL);
2994                 if (unlikely(status != I40E_SUCCESS)) {
2995                         link->link_speed = ETH_SPEED_NUM_NONE;
2996                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2997                         PMD_DRV_LOG(ERR, "Failed to get link info");
2998                         return;
2999                 }
3000
3001                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
3002                 if (!wait_to_complete || link->link_status)
3003                         break;
3004
3005                 rte_delay_ms(CHECK_INTERVAL);
3006         } while (--rep_cnt);
3007
3008         /* Parse the link status */
3009         switch (link_status.link_speed) {
3010         case I40E_LINK_SPEED_100MB:
3011                 link->link_speed = ETH_SPEED_NUM_100M;
3012                 break;
3013         case I40E_LINK_SPEED_1GB:
3014                 link->link_speed = ETH_SPEED_NUM_1G;
3015                 break;
3016         case I40E_LINK_SPEED_10GB:
3017                 link->link_speed = ETH_SPEED_NUM_10G;
3018                 break;
3019         case I40E_LINK_SPEED_20GB:
3020                 link->link_speed = ETH_SPEED_NUM_20G;
3021                 break;
3022         case I40E_LINK_SPEED_25GB:
3023                 link->link_speed = ETH_SPEED_NUM_25G;
3024                 break;
3025         case I40E_LINK_SPEED_40GB:
3026                 link->link_speed = ETH_SPEED_NUM_40G;
3027                 break;
3028         default:
3029                 if (link->link_status)
3030                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3031                 else
3032                         link->link_speed = ETH_SPEED_NUM_NONE;
3033                 break;
3034         }
3035 }
3036
3037 int
3038 i40e_dev_link_update(struct rte_eth_dev *dev,
3039                      int wait_to_complete)
3040 {
3041         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         struct rte_eth_link link;
3043         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3044         int ret;
3045
3046         memset(&link, 0, sizeof(link));
3047
3048         /* i40e uses full duplex only */
3049         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3050         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3051                         ETH_LINK_SPEED_FIXED);
3052
3053         if (!wait_to_complete && !enable_lse)
3054                 update_link_reg(hw, &link);
3055         else
3056                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3057
3058         if (hw->switch_dev)
3059                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3060
3061         ret = rte_eth_linkstatus_set(dev, &link);
3062         i40e_notify_all_vfs_link_status(dev);
3063
3064         return ret;
3065 }
3066
3067 static void
3068 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3069                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3070                           uint64_t *stat, uint64_t *prev_stat)
3071 {
3072         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3073         /* enlarge the limitation when statistics counters overflowed */
3074         if (offset_loaded) {
3075                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3076                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3077                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3078         }
3079         *prev_stat = *stat;
3080 }
3081
3082 /* Get all the statistics of a VSI */
3083 void
3084 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3085 {
3086         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3087         struct i40e_eth_stats *nes = &vsi->eth_stats;
3088         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3089         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3090
3091         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3092                                   vsi->offset_loaded, &oes->rx_bytes,
3093                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3094         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3095                             vsi->offset_loaded, &oes->rx_unicast,
3096                             &nes->rx_unicast);
3097         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3098                             vsi->offset_loaded, &oes->rx_multicast,
3099                             &nes->rx_multicast);
3100         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3101                             vsi->offset_loaded, &oes->rx_broadcast,
3102                             &nes->rx_broadcast);
3103         /* exclude CRC bytes */
3104         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3105                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3106
3107         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3108                             &oes->rx_discards, &nes->rx_discards);
3109         /* GLV_REPC not supported */
3110         /* GLV_RMPC not supported */
3111         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3112                             &oes->rx_unknown_protocol,
3113                             &nes->rx_unknown_protocol);
3114         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3115                                   vsi->offset_loaded, &oes->tx_bytes,
3116                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3117         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3118                             vsi->offset_loaded, &oes->tx_unicast,
3119                             &nes->tx_unicast);
3120         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3121                             vsi->offset_loaded, &oes->tx_multicast,
3122                             &nes->tx_multicast);
3123         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3124                             vsi->offset_loaded,  &oes->tx_broadcast,
3125                             &nes->tx_broadcast);
3126         /* GLV_TDPC not supported */
3127         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3128                             &oes->tx_errors, &nes->tx_errors);
3129         vsi->offset_loaded = true;
3130
3131         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3132                     vsi->vsi_id);
3133         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3134         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3135         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3136         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3137         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3138         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3139                     nes->rx_unknown_protocol);
3140         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3141         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3142         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3143         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3144         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3145         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3146         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3147                     vsi->vsi_id);
3148 }
3149
3150 static void
3151 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3152 {
3153         unsigned int i;
3154         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3155         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3156
3157         /* Get rx/tx bytes of internal transfer packets */
3158         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3159                                   I40E_GLV_GORCL(hw->port),
3160                                   pf->offset_loaded,
3161                                   &pf->internal_stats_offset.rx_bytes,
3162                                   &pf->internal_stats.rx_bytes,
3163                                   &pf->internal_prev_rx_bytes);
3164         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3165                                   I40E_GLV_GOTCL(hw->port),
3166                                   pf->offset_loaded,
3167                                   &pf->internal_stats_offset.tx_bytes,
3168                                   &pf->internal_stats.tx_bytes,
3169                                   &pf->internal_prev_tx_bytes);
3170         /* Get total internal rx packet count */
3171         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3172                             I40E_GLV_UPRCL(hw->port),
3173                             pf->offset_loaded,
3174                             &pf->internal_stats_offset.rx_unicast,
3175                             &pf->internal_stats.rx_unicast);
3176         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3177                             I40E_GLV_MPRCL(hw->port),
3178                             pf->offset_loaded,
3179                             &pf->internal_stats_offset.rx_multicast,
3180                             &pf->internal_stats.rx_multicast);
3181         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3182                             I40E_GLV_BPRCL(hw->port),
3183                             pf->offset_loaded,
3184                             &pf->internal_stats_offset.rx_broadcast,
3185                             &pf->internal_stats.rx_broadcast);
3186         /* Get total internal tx packet count */
3187         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3188                             I40E_GLV_UPTCL(hw->port),
3189                             pf->offset_loaded,
3190                             &pf->internal_stats_offset.tx_unicast,
3191                             &pf->internal_stats.tx_unicast);
3192         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3193                             I40E_GLV_MPTCL(hw->port),
3194                             pf->offset_loaded,
3195                             &pf->internal_stats_offset.tx_multicast,
3196                             &pf->internal_stats.tx_multicast);
3197         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3198                             I40E_GLV_BPTCL(hw->port),
3199                             pf->offset_loaded,
3200                             &pf->internal_stats_offset.tx_broadcast,
3201                             &pf->internal_stats.tx_broadcast);
3202
3203         /* exclude CRC size */
3204         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3205                 pf->internal_stats.rx_multicast +
3206                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3207
3208         /* Get statistics of struct i40e_eth_stats */
3209         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3210                                   I40E_GLPRT_GORCL(hw->port),
3211                                   pf->offset_loaded, &os->eth.rx_bytes,
3212                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3213         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3214                             I40E_GLPRT_UPRCL(hw->port),
3215                             pf->offset_loaded, &os->eth.rx_unicast,
3216                             &ns->eth.rx_unicast);
3217         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3218                             I40E_GLPRT_MPRCL(hw->port),
3219                             pf->offset_loaded, &os->eth.rx_multicast,
3220                             &ns->eth.rx_multicast);
3221         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3222                             I40E_GLPRT_BPRCL(hw->port),
3223                             pf->offset_loaded, &os->eth.rx_broadcast,
3224                             &ns->eth.rx_broadcast);
3225         /* Workaround: CRC size should not be included in byte statistics,
3226          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3227          * packet.
3228          */
3229         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3230                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3231
3232         /* exclude internal rx bytes
3233          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3234          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3235          * value.
3236          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3237          */
3238         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3239                 ns->eth.rx_bytes = 0;
3240         else
3241                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3242
3243         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3244                 ns->eth.rx_unicast = 0;
3245         else
3246                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3247
3248         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3249                 ns->eth.rx_multicast = 0;
3250         else
3251                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3252
3253         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3254                 ns->eth.rx_broadcast = 0;
3255         else
3256                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3257
3258         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3259                             pf->offset_loaded, &os->eth.rx_discards,
3260                             &ns->eth.rx_discards);
3261         /* GLPRT_REPC not supported */
3262         /* GLPRT_RMPC not supported */
3263         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3264                             pf->offset_loaded,
3265                             &os->eth.rx_unknown_protocol,
3266                             &ns->eth.rx_unknown_protocol);
3267         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3268                                   I40E_GLPRT_GOTCL(hw->port),
3269                                   pf->offset_loaded, &os->eth.tx_bytes,
3270                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3271         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3272                             I40E_GLPRT_UPTCL(hw->port),
3273                             pf->offset_loaded, &os->eth.tx_unicast,
3274                             &ns->eth.tx_unicast);
3275         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3276                             I40E_GLPRT_MPTCL(hw->port),
3277                             pf->offset_loaded, &os->eth.tx_multicast,
3278                             &ns->eth.tx_multicast);
3279         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3280                             I40E_GLPRT_BPTCL(hw->port),
3281                             pf->offset_loaded, &os->eth.tx_broadcast,
3282                             &ns->eth.tx_broadcast);
3283         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3284                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3285
3286         /* exclude internal tx bytes
3287          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3288          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3289          * value.
3290          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3291          */
3292         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3293                 ns->eth.tx_bytes = 0;
3294         else
3295                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3296
3297         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3298                 ns->eth.tx_unicast = 0;
3299         else
3300                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3301
3302         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3303                 ns->eth.tx_multicast = 0;
3304         else
3305                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3306
3307         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3308                 ns->eth.tx_broadcast = 0;
3309         else
3310                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3311
3312         /* GLPRT_TEPC not supported */
3313
3314         /* additional port specific stats */
3315         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3316                             pf->offset_loaded, &os->tx_dropped_link_down,
3317                             &ns->tx_dropped_link_down);
3318         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3319                             pf->offset_loaded, &os->crc_errors,
3320                             &ns->crc_errors);
3321         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3322                             pf->offset_loaded, &os->illegal_bytes,
3323                             &ns->illegal_bytes);
3324         /* GLPRT_ERRBC not supported */
3325         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3326                             pf->offset_loaded, &os->mac_local_faults,
3327                             &ns->mac_local_faults);
3328         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3329                             pf->offset_loaded, &os->mac_remote_faults,
3330                             &ns->mac_remote_faults);
3331         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3332                             pf->offset_loaded, &os->rx_length_errors,
3333                             &ns->rx_length_errors);
3334         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3335                             pf->offset_loaded, &os->link_xon_rx,
3336                             &ns->link_xon_rx);
3337         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3338                             pf->offset_loaded, &os->link_xoff_rx,
3339                             &ns->link_xoff_rx);
3340         for (i = 0; i < 8; i++) {
3341                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3342                                     pf->offset_loaded,
3343                                     &os->priority_xon_rx[i],
3344                                     &ns->priority_xon_rx[i]);
3345                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3346                                     pf->offset_loaded,
3347                                     &os->priority_xoff_rx[i],
3348                                     &ns->priority_xoff_rx[i]);
3349         }
3350         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3351                             pf->offset_loaded, &os->link_xon_tx,
3352                             &ns->link_xon_tx);
3353         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3354                             pf->offset_loaded, &os->link_xoff_tx,
3355                             &ns->link_xoff_tx);
3356         for (i = 0; i < 8; i++) {
3357                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3358                                     pf->offset_loaded,
3359                                     &os->priority_xon_tx[i],
3360                                     &ns->priority_xon_tx[i]);
3361                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3362                                     pf->offset_loaded,
3363                                     &os->priority_xoff_tx[i],
3364                                     &ns->priority_xoff_tx[i]);
3365                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3366                                     pf->offset_loaded,
3367                                     &os->priority_xon_2_xoff[i],
3368                                     &ns->priority_xon_2_xoff[i]);
3369         }
3370         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3371                             I40E_GLPRT_PRC64L(hw->port),
3372                             pf->offset_loaded, &os->rx_size_64,
3373                             &ns->rx_size_64);
3374         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3375                             I40E_GLPRT_PRC127L(hw->port),
3376                             pf->offset_loaded, &os->rx_size_127,
3377                             &ns->rx_size_127);
3378         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3379                             I40E_GLPRT_PRC255L(hw->port),
3380                             pf->offset_loaded, &os->rx_size_255,
3381                             &ns->rx_size_255);
3382         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3383                             I40E_GLPRT_PRC511L(hw->port),
3384                             pf->offset_loaded, &os->rx_size_511,
3385                             &ns->rx_size_511);
3386         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3387                             I40E_GLPRT_PRC1023L(hw->port),
3388                             pf->offset_loaded, &os->rx_size_1023,
3389                             &ns->rx_size_1023);
3390         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3391                             I40E_GLPRT_PRC1522L(hw->port),
3392                             pf->offset_loaded, &os->rx_size_1522,
3393                             &ns->rx_size_1522);
3394         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3395                             I40E_GLPRT_PRC9522L(hw->port),
3396                             pf->offset_loaded, &os->rx_size_big,
3397                             &ns->rx_size_big);
3398         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3399                             pf->offset_loaded, &os->rx_undersize,
3400                             &ns->rx_undersize);
3401         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3402                             pf->offset_loaded, &os->rx_fragments,
3403                             &ns->rx_fragments);
3404         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3405                             pf->offset_loaded, &os->rx_oversize,
3406                             &ns->rx_oversize);
3407         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3408                             pf->offset_loaded, &os->rx_jabber,
3409                             &ns->rx_jabber);
3410         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3411                             I40E_GLPRT_PTC64L(hw->port),
3412                             pf->offset_loaded, &os->tx_size_64,
3413                             &ns->tx_size_64);
3414         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3415                             I40E_GLPRT_PTC127L(hw->port),
3416                             pf->offset_loaded, &os->tx_size_127,
3417                             &ns->tx_size_127);
3418         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3419                             I40E_GLPRT_PTC255L(hw->port),
3420                             pf->offset_loaded, &os->tx_size_255,
3421                             &ns->tx_size_255);
3422         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3423                             I40E_GLPRT_PTC511L(hw->port),
3424                             pf->offset_loaded, &os->tx_size_511,
3425                             &ns->tx_size_511);
3426         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3427                             I40E_GLPRT_PTC1023L(hw->port),
3428                             pf->offset_loaded, &os->tx_size_1023,
3429                             &ns->tx_size_1023);
3430         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3431                             I40E_GLPRT_PTC1522L(hw->port),
3432                             pf->offset_loaded, &os->tx_size_1522,
3433                             &ns->tx_size_1522);
3434         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3435                             I40E_GLPRT_PTC9522L(hw->port),
3436                             pf->offset_loaded, &os->tx_size_big,
3437                             &ns->tx_size_big);
3438         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3439                            pf->offset_loaded,
3440                            &os->fd_sb_match, &ns->fd_sb_match);
3441         /* GLPRT_MSPDC not supported */
3442         /* GLPRT_XEC not supported */
3443
3444         pf->offset_loaded = true;
3445
3446         if (pf->main_vsi)
3447                 i40e_update_vsi_stats(pf->main_vsi);
3448 }
3449
3450 /* Get all statistics of a port */
3451 static int
3452 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3453 {
3454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3457         struct i40e_vsi *vsi;
3458         unsigned i;
3459
3460         /* call read registers - updates values, now write them to struct */
3461         i40e_read_stats_registers(pf, hw);
3462
3463         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3464                         pf->main_vsi->eth_stats.rx_multicast +
3465                         pf->main_vsi->eth_stats.rx_broadcast -
3466                         pf->main_vsi->eth_stats.rx_discards;
3467         stats->opackets = ns->eth.tx_unicast +
3468                         ns->eth.tx_multicast +
3469                         ns->eth.tx_broadcast;
3470         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3471         stats->obytes   = ns->eth.tx_bytes;
3472         stats->oerrors  = ns->eth.tx_errors +
3473                         pf->main_vsi->eth_stats.tx_errors;
3474
3475         /* Rx Errors */
3476         stats->imissed  = ns->eth.rx_discards +
3477                         pf->main_vsi->eth_stats.rx_discards;
3478         stats->ierrors  = ns->crc_errors +
3479                         ns->rx_length_errors + ns->rx_undersize +
3480                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3481
3482         if (pf->vfs) {
3483                 for (i = 0; i < pf->vf_num; i++) {
3484                         vsi = pf->vfs[i].vsi;
3485                         i40e_update_vsi_stats(vsi);
3486
3487                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3488                                         vsi->eth_stats.rx_multicast +
3489                                         vsi->eth_stats.rx_broadcast -
3490                                         vsi->eth_stats.rx_discards);
3491                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3492                         stats->oerrors  += vsi->eth_stats.tx_errors;
3493                         stats->imissed  += vsi->eth_stats.rx_discards;
3494                 }
3495         }
3496
3497         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3498         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3499         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3500         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3501         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3502         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3503         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3504                     ns->eth.rx_unknown_protocol);
3505         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3506         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3507         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3508         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3509         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3510         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3511
3512         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3513                     ns->tx_dropped_link_down);
3514         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3515         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3516                     ns->illegal_bytes);
3517         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3518         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3519                     ns->mac_local_faults);
3520         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3521                     ns->mac_remote_faults);
3522         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3523                     ns->rx_length_errors);
3524         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3525         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3526         for (i = 0; i < 8; i++) {
3527                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3528                                 i, ns->priority_xon_rx[i]);
3529                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3530                                 i, ns->priority_xoff_rx[i]);
3531         }
3532         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3533         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3534         for (i = 0; i < 8; i++) {
3535                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3536                                 i, ns->priority_xon_tx[i]);
3537                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3538                                 i, ns->priority_xoff_tx[i]);
3539                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3540                                 i, ns->priority_xon_2_xoff[i]);
3541         }
3542         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3543         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3544         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3545         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3546         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3547         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3548         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3549         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3550         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3551         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3552         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3553         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3554         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3555         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3556         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3557         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3558         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3559         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3560         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3561                         ns->mac_short_packet_dropped);
3562         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3563                     ns->checksum_error);
3564         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3565         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3566         return 0;
3567 }
3568
3569 /* Reset the statistics */
3570 static int
3571 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3572 {
3573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3575
3576         /* Mark PF and VSI stats to update the offset, aka "reset" */
3577         pf->offset_loaded = false;
3578         if (pf->main_vsi)
3579                 pf->main_vsi->offset_loaded = false;
3580
3581         /* read the stats, reading current register values into offset */
3582         i40e_read_stats_registers(pf, hw);
3583
3584         return 0;
3585 }
3586
3587 static uint32_t
3588 i40e_xstats_calc_num(void)
3589 {
3590         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3591                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3592                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3593 }
3594
3595 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3596                                      struct rte_eth_xstat_name *xstats_names,
3597                                      __rte_unused unsigned limit)
3598 {
3599         unsigned count = 0;
3600         unsigned i, prio;
3601
3602         if (xstats_names == NULL)
3603                 return i40e_xstats_calc_num();
3604
3605         /* Note: limit checked in rte_eth_xstats_names() */
3606
3607         /* Get stats from i40e_eth_stats struct */
3608         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3609                 strlcpy(xstats_names[count].name,
3610                         rte_i40e_stats_strings[i].name,
3611                         sizeof(xstats_names[count].name));
3612                 count++;
3613         }
3614
3615         /* Get individiual stats from i40e_hw_port struct */
3616         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3617                 strlcpy(xstats_names[count].name,
3618                         rte_i40e_hw_port_strings[i].name,
3619                         sizeof(xstats_names[count].name));
3620                 count++;
3621         }
3622
3623         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3624                 for (prio = 0; prio < 8; prio++) {
3625                         snprintf(xstats_names[count].name,
3626                                  sizeof(xstats_names[count].name),
3627                                  "rx_priority%u_%s", prio,
3628                                  rte_i40e_rxq_prio_strings[i].name);
3629                         count++;
3630                 }
3631         }
3632
3633         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3634                 for (prio = 0; prio < 8; prio++) {
3635                         snprintf(xstats_names[count].name,
3636                                  sizeof(xstats_names[count].name),
3637                                  "tx_priority%u_%s", prio,
3638                                  rte_i40e_txq_prio_strings[i].name);
3639                         count++;
3640                 }
3641         }
3642         return count;
3643 }
3644
3645 static int
3646 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3647                     unsigned n)
3648 {
3649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651         unsigned i, count, prio;
3652         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3653
3654         count = i40e_xstats_calc_num();
3655         if (n < count)
3656                 return count;
3657
3658         i40e_read_stats_registers(pf, hw);
3659
3660         if (xstats == NULL)
3661                 return 0;
3662
3663         count = 0;
3664
3665         /* Get stats from i40e_eth_stats struct */
3666         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3667                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3668                         rte_i40e_stats_strings[i].offset);
3669                 xstats[count].id = count;
3670                 count++;
3671         }
3672
3673         /* Get individiual stats from i40e_hw_port struct */
3674         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3675                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3676                         rte_i40e_hw_port_strings[i].offset);
3677                 xstats[count].id = count;
3678                 count++;
3679         }
3680
3681         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3682                 for (prio = 0; prio < 8; prio++) {
3683                         xstats[count].value =
3684                                 *(uint64_t *)(((char *)hw_stats) +
3685                                 rte_i40e_rxq_prio_strings[i].offset +
3686                                 (sizeof(uint64_t) * prio));
3687                         xstats[count].id = count;
3688                         count++;
3689                 }
3690         }
3691
3692         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3693                 for (prio = 0; prio < 8; prio++) {
3694                         xstats[count].value =
3695                                 *(uint64_t *)(((char *)hw_stats) +
3696                                 rte_i40e_txq_prio_strings[i].offset +
3697                                 (sizeof(uint64_t) * prio));
3698                         xstats[count].id = count;
3699                         count++;
3700                 }
3701         }
3702
3703         return count;
3704 }
3705
3706 static int
3707 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3708 {
3709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         u32 full_ver;
3711         u8 ver, patch;
3712         u16 build;
3713         int ret;
3714
3715         full_ver = hw->nvm.oem_ver;
3716         ver = (u8)(full_ver >> 24);
3717         build = (u16)((full_ver >> 8) & 0xffff);
3718         patch = (u8)(full_ver & 0xff);
3719
3720         ret = snprintf(fw_version, fw_size,
3721                  "%d.%d%d 0x%08x %d.%d.%d",
3722                  ((hw->nvm.version >> 12) & 0xf),
3723                  ((hw->nvm.version >> 4) & 0xff),
3724                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3725                  ver, build, patch);
3726
3727         ret += 1; /* add the size of '\0' */
3728         if (fw_size < (u32)ret)
3729                 return ret;
3730         else
3731                 return 0;
3732 }
3733
3734 /*
3735  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3736  * the Rx data path does not hang if the FW LLDP is stopped.
3737  * return true if lldp need to stop
3738  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3739  */
3740 static bool
3741 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3742 {
3743         double nvm_ver;
3744         char ver_str[64] = {0};
3745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3746
3747         i40e_fw_version_get(dev, ver_str, 64);
3748         nvm_ver = atof(ver_str);
3749         if ((hw->mac.type == I40E_MAC_X722 ||
3750              hw->mac.type == I40E_MAC_X722_VF) &&
3751              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3752                 return true;
3753         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3754                 return true;
3755
3756         return false;
3757 }
3758
3759 static int
3760 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3761 {
3762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         struct i40e_vsi *vsi = pf->main_vsi;
3765         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3766
3767         dev_info->max_rx_queues = vsi->nb_qps;
3768         dev_info->max_tx_queues = vsi->nb_qps;
3769         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3770         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3771         dev_info->max_mac_addrs = vsi->max_macaddrs;
3772         dev_info->max_vfs = pci_dev->max_vfs;
3773         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3774         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3775         dev_info->rx_queue_offload_capa = 0;
3776         dev_info->rx_offload_capa =
3777                 DEV_RX_OFFLOAD_VLAN_STRIP |
3778                 DEV_RX_OFFLOAD_QINQ_STRIP |
3779                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3780                 DEV_RX_OFFLOAD_UDP_CKSUM |
3781                 DEV_RX_OFFLOAD_TCP_CKSUM |
3782                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3783                 DEV_RX_OFFLOAD_KEEP_CRC |
3784                 DEV_RX_OFFLOAD_SCATTER |
3785                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3786                 DEV_RX_OFFLOAD_VLAN_FILTER |
3787                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3788                 DEV_RX_OFFLOAD_RSS_HASH;
3789
3790         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3791         dev_info->tx_offload_capa =
3792                 DEV_TX_OFFLOAD_VLAN_INSERT |
3793                 DEV_TX_OFFLOAD_QINQ_INSERT |
3794                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3795                 DEV_TX_OFFLOAD_UDP_CKSUM |
3796                 DEV_TX_OFFLOAD_TCP_CKSUM |
3797                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3798                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3799                 DEV_TX_OFFLOAD_TCP_TSO |
3800                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3801                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3802                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3803                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3804                 DEV_TX_OFFLOAD_MULTI_SEGS |
3805                 dev_info->tx_queue_offload_capa;
3806         dev_info->dev_capa =
3807                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3808                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3809
3810         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3811                                                 sizeof(uint32_t);
3812         dev_info->reta_size = pf->hash_lut_size;
3813         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3814
3815         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3816                 .rx_thresh = {
3817                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3818                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3819                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3820                 },
3821                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3822                 .rx_drop_en = 0,
3823                 .offloads = 0,
3824         };
3825
3826         dev_info->default_txconf = (struct rte_eth_txconf) {
3827                 .tx_thresh = {
3828                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3829                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3830                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3831                 },
3832                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3833                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3834                 .offloads = 0,
3835         };
3836
3837         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3838                 .nb_max = I40E_MAX_RING_DESC,
3839                 .nb_min = I40E_MIN_RING_DESC,
3840                 .nb_align = I40E_ALIGN_RING_DESC,
3841         };
3842
3843         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3844                 .nb_max = I40E_MAX_RING_DESC,
3845                 .nb_min = I40E_MIN_RING_DESC,
3846                 .nb_align = I40E_ALIGN_RING_DESC,
3847                 .nb_seg_max = I40E_TX_MAX_SEG,
3848                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3849         };
3850
3851         if (pf->flags & I40E_FLAG_VMDQ) {
3852                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3853                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3854                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3855                                                 pf->max_nb_vmdq_vsi;
3856                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3857                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3858                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3859         }
3860
3861         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3862                 /* For XL710 */
3863                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3864                 dev_info->default_rxportconf.nb_queues = 2;
3865                 dev_info->default_txportconf.nb_queues = 2;
3866                 if (dev->data->nb_rx_queues == 1)
3867                         dev_info->default_rxportconf.ring_size = 2048;
3868                 else
3869                         dev_info->default_rxportconf.ring_size = 1024;
3870                 if (dev->data->nb_tx_queues == 1)
3871                         dev_info->default_txportconf.ring_size = 1024;
3872                 else
3873                         dev_info->default_txportconf.ring_size = 512;
3874
3875         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3876                 /* For XXV710 */
3877                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3878                 dev_info->default_rxportconf.nb_queues = 1;
3879                 dev_info->default_txportconf.nb_queues = 1;
3880                 dev_info->default_rxportconf.ring_size = 256;
3881                 dev_info->default_txportconf.ring_size = 256;
3882         } else {
3883                 /* For X710 */
3884                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3885                 dev_info->default_rxportconf.nb_queues = 1;
3886                 dev_info->default_txportconf.nb_queues = 1;
3887                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3888                         dev_info->default_rxportconf.ring_size = 512;
3889                         dev_info->default_txportconf.ring_size = 256;
3890                 } else {
3891                         dev_info->default_rxportconf.ring_size = 256;
3892                         dev_info->default_txportconf.ring_size = 256;
3893                 }
3894         }
3895         dev_info->default_rxportconf.burst_size = 32;
3896         dev_info->default_txportconf.burst_size = 32;
3897
3898         return 0;
3899 }
3900
3901 static int
3902 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3903 {
3904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3905         struct i40e_vsi *vsi = pf->main_vsi;
3906         PMD_INIT_FUNC_TRACE();
3907
3908         if (on)
3909                 return i40e_vsi_add_vlan(vsi, vlan_id);
3910         else
3911                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3912 }
3913
3914 static int
3915 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3916                                 enum rte_vlan_type vlan_type,
3917                                 uint16_t tpid, int qinq)
3918 {
3919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3920         uint64_t reg_r = 0;
3921         uint64_t reg_w = 0;
3922         uint16_t reg_id = 3;
3923         int ret;
3924
3925         if (qinq) {
3926                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3927                         reg_id = 2;
3928         }
3929
3930         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3931                                           &reg_r, NULL);
3932         if (ret != I40E_SUCCESS) {
3933                 PMD_DRV_LOG(ERR,
3934                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3935                            reg_id);
3936                 return -EIO;
3937         }
3938         PMD_DRV_LOG(DEBUG,
3939                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3940                     reg_id, reg_r);
3941
3942         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3943         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3944         if (reg_r == reg_w) {
3945                 PMD_DRV_LOG(DEBUG, "No need to write");
3946                 return 0;
3947         }
3948
3949         ret = i40e_aq_debug_write_global_register(hw,
3950                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3951                                            reg_w, NULL);
3952         if (ret != I40E_SUCCESS) {
3953                 PMD_DRV_LOG(ERR,
3954                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3955                             reg_id);
3956                 return -EIO;
3957         }
3958         PMD_DRV_LOG(DEBUG,
3959                     "Global register 0x%08x is changed with value 0x%08x",
3960                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3961
3962         return 0;
3963 }
3964
3965 static int
3966 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3967                    enum rte_vlan_type vlan_type,
3968                    uint16_t tpid)
3969 {
3970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3971         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3972         int qinq = dev->data->dev_conf.rxmode.offloads &
3973                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3974         int ret = 0;
3975
3976         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3977              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3978             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3979                 PMD_DRV_LOG(ERR,
3980                             "Unsupported vlan type.");
3981                 return -EINVAL;
3982         }
3983
3984         if (pf->support_multi_driver) {
3985                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3986                 return -ENOTSUP;
3987         }
3988
3989         /* 802.1ad frames ability is added in NVM API 1.7*/
3990         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3991                 if (qinq) {
3992                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3993                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3994                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3995                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3996                 } else {
3997                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3998                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3999                 }
4000                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
4001                 if (ret != I40E_SUCCESS) {
4002                         PMD_DRV_LOG(ERR,
4003                                     "Set switch config failed aq_err: %d",
4004                                     hw->aq.asq_last_status);
4005                         ret = -EIO;
4006                 }
4007         } else
4008                 /* If NVM API < 1.7, keep the register setting */
4009                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
4010                                                       tpid, qinq);
4011
4012         return ret;
4013 }
4014
4015 /* Configure outer vlan stripping on or off in QinQ mode */
4016 static int
4017 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4018 {
4019         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4020         int ret = I40E_SUCCESS;
4021         uint32_t reg;
4022
4023         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4024                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4025                 return -EINVAL;
4026         }
4027
4028         /* Configure for outer VLAN RX stripping */
4029         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4030
4031         if (on)
4032                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4033         else
4034                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4035
4036         ret = i40e_aq_debug_write_register(hw,
4037                                                    I40E_VSI_TSR(vsi->vsi_id),
4038                                                    reg, NULL);
4039         if (ret < 0) {
4040                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4041                                     vsi->vsi_id);
4042                 return I40E_ERR_CONFIG;
4043         }
4044
4045         return ret;
4046 }
4047
4048 static int
4049 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4050 {
4051         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4052         struct i40e_vsi *vsi = pf->main_vsi;
4053         struct rte_eth_rxmode *rxmode;
4054
4055         rxmode = &dev->data->dev_conf.rxmode;
4056         if (mask & ETH_VLAN_FILTER_MASK) {
4057                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4058                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4059                 else
4060                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4061         }
4062
4063         if (mask & ETH_VLAN_STRIP_MASK) {
4064                 /* Enable or disable VLAN stripping */
4065                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4066                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4067                 else
4068                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4069         }
4070
4071         if (mask & ETH_VLAN_EXTEND_MASK) {
4072                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4073                         i40e_vsi_config_double_vlan(vsi, TRUE);
4074                         /* Set global registers with default ethertype. */
4075                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4076                                            RTE_ETHER_TYPE_VLAN);
4077                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4078                                            RTE_ETHER_TYPE_VLAN);
4079                 }
4080                 else
4081                         i40e_vsi_config_double_vlan(vsi, FALSE);
4082         }
4083
4084         if (mask & ETH_QINQ_STRIP_MASK) {
4085                 /* Enable or disable outer VLAN stripping */
4086                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4087                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4088                 else
4089                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4090         }
4091
4092         return 0;
4093 }
4094
4095 static void
4096 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4097                           __rte_unused uint16_t queue,
4098                           __rte_unused int on)
4099 {
4100         PMD_INIT_FUNC_TRACE();
4101 }
4102
4103 static int
4104 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4105 {
4106         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4107         struct i40e_vsi *vsi = pf->main_vsi;
4108         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4109         struct i40e_vsi_vlan_pvid_info info;
4110
4111         memset(&info, 0, sizeof(info));
4112         info.on = on;
4113         if (info.on)
4114                 info.config.pvid = pvid;
4115         else {
4116                 info.config.reject.tagged =
4117                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4118                 info.config.reject.untagged =
4119                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4120         }
4121
4122         return i40e_vsi_vlan_pvid_set(vsi, &info);
4123 }
4124
4125 static int
4126 i40e_dev_led_on(struct rte_eth_dev *dev)
4127 {
4128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4129         uint32_t mode = i40e_led_get(hw);
4130
4131         if (mode == 0)
4132                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4133
4134         return 0;
4135 }
4136
4137 static int
4138 i40e_dev_led_off(struct rte_eth_dev *dev)
4139 {
4140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4141         uint32_t mode = i40e_led_get(hw);
4142
4143         if (mode != 0)
4144                 i40e_led_set(hw, 0, false);
4145
4146         return 0;
4147 }
4148
4149 static int
4150 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4151 {
4152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4154
4155         fc_conf->pause_time = pf->fc_conf.pause_time;
4156
4157         /* read out from register, in case they are modified by other port */
4158         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4159                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4160         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4161                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4162
4163         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4164         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4165
4166          /* Return current mode according to actual setting*/
4167         switch (hw->fc.current_mode) {
4168         case I40E_FC_FULL:
4169                 fc_conf->mode = RTE_FC_FULL;
4170                 break;
4171         case I40E_FC_TX_PAUSE:
4172                 fc_conf->mode = RTE_FC_TX_PAUSE;
4173                 break;
4174         case I40E_FC_RX_PAUSE:
4175                 fc_conf->mode = RTE_FC_RX_PAUSE;
4176                 break;
4177         case I40E_FC_NONE:
4178         default:
4179                 fc_conf->mode = RTE_FC_NONE;
4180         };
4181
4182         return 0;
4183 }
4184
4185 static int
4186 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4187 {
4188         uint32_t mflcn_reg, fctrl_reg, reg;
4189         uint32_t max_high_water;
4190         uint8_t i, aq_failure;
4191         int err;
4192         struct i40e_hw *hw;
4193         struct i40e_pf *pf;
4194         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4195                 [RTE_FC_NONE] = I40E_FC_NONE,
4196                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4197                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4198                 [RTE_FC_FULL] = I40E_FC_FULL
4199         };
4200
4201         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4202
4203         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4204         if ((fc_conf->high_water > max_high_water) ||
4205                         (fc_conf->high_water < fc_conf->low_water)) {
4206                 PMD_INIT_LOG(ERR,
4207                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4208                         max_high_water);
4209                 return -EINVAL;
4210         }
4211
4212         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4213         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4214         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4215
4216         pf->fc_conf.pause_time = fc_conf->pause_time;
4217         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4218         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4219
4220         PMD_INIT_FUNC_TRACE();
4221
4222         /* All the link flow control related enable/disable register
4223          * configuration is handle by the F/W
4224          */
4225         err = i40e_set_fc(hw, &aq_failure, true);
4226         if (err < 0)
4227                 return -ENOSYS;
4228
4229         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4230                 /* Configure flow control refresh threshold,
4231                  * the value for stat_tx_pause_refresh_timer[8]
4232                  * is used for global pause operation.
4233                  */
4234
4235                 I40E_WRITE_REG(hw,
4236                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4237                                pf->fc_conf.pause_time);
4238
4239                 /* configure the timer value included in transmitted pause
4240                  * frame,
4241                  * the value for stat_tx_pause_quanta[8] is used for global
4242                  * pause operation
4243                  */
4244                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4245                                pf->fc_conf.pause_time);
4246
4247                 fctrl_reg = I40E_READ_REG(hw,
4248                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4249
4250                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4251                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4252                 else
4253                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4254
4255                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4256                                fctrl_reg);
4257         } else {
4258                 /* Configure pause time (2 TCs per register) */
4259                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4260                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4261                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4262
4263                 /* Configure flow control refresh threshold value */
4264                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4265                                pf->fc_conf.pause_time / 2);
4266
4267                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4268
4269                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4270                  *depending on configuration
4271                  */
4272                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4273                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4274                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4275                 } else {
4276                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4277                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4278                 }
4279
4280                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4281         }
4282
4283         if (!pf->support_multi_driver) {
4284                 /* config water marker both based on the packets and bytes */
4285                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4286                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4287                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4288                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4289                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4290                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4291                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4292                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4293                                   << I40E_KILOSHIFT);
4294                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4295                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4296                                    << I40E_KILOSHIFT);
4297         } else {
4298                 PMD_DRV_LOG(ERR,
4299                             "Water marker configuration is not supported.");
4300         }
4301
4302         I40E_WRITE_FLUSH(hw);
4303
4304         return 0;
4305 }
4306
4307 static int
4308 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4309                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4310 {
4311         PMD_INIT_FUNC_TRACE();
4312
4313         return -ENOSYS;
4314 }
4315
4316 /* Add a MAC address, and update filters */
4317 static int
4318 i40e_macaddr_add(struct rte_eth_dev *dev,
4319                  struct rte_ether_addr *mac_addr,
4320                  __rte_unused uint32_t index,
4321                  uint32_t pool)
4322 {
4323         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4324         struct i40e_mac_filter_info mac_filter;
4325         struct i40e_vsi *vsi;
4326         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4327         int ret;
4328
4329         /* If VMDQ not enabled or configured, return */
4330         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4331                           !pf->nb_cfg_vmdq_vsi)) {
4332                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4333                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4334                         pool);
4335                 return -ENOTSUP;
4336         }
4337
4338         if (pool > pf->nb_cfg_vmdq_vsi) {
4339                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4340                                 pool, pf->nb_cfg_vmdq_vsi);
4341                 return -EINVAL;
4342         }
4343
4344         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4345         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4346                 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4347         else
4348                 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4349
4350         if (pool == 0)
4351                 vsi = pf->main_vsi;
4352         else
4353                 vsi = pf->vmdq[pool - 1].vsi;
4354
4355         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4356         if (ret != I40E_SUCCESS) {
4357                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4358                 return -ENODEV;
4359         }
4360         return 0;
4361 }
4362
4363 /* Remove a MAC address, and update filters */
4364 static void
4365 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4366 {
4367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4368         struct i40e_vsi *vsi;
4369         struct rte_eth_dev_data *data = dev->data;
4370         struct rte_ether_addr *macaddr;
4371         int ret;
4372         uint32_t i;
4373         uint64_t pool_sel;
4374
4375         macaddr = &(data->mac_addrs[index]);
4376
4377         pool_sel = dev->data->mac_pool_sel[index];
4378
4379         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4380                 if (pool_sel & (1ULL << i)) {
4381                         if (i == 0)
4382                                 vsi = pf->main_vsi;
4383                         else {
4384                                 /* No VMDQ pool enabled or configured */
4385                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4386                                         (i > pf->nb_cfg_vmdq_vsi)) {
4387                                         PMD_DRV_LOG(ERR,
4388                                                 "No VMDQ pool enabled/configured");
4389                                         return;
4390                                 }
4391                                 vsi = pf->vmdq[i - 1].vsi;
4392                         }
4393                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4394
4395                         if (ret) {
4396                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4397                                 return;
4398                         }
4399                 }
4400         }
4401 }
4402
4403 static int
4404 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4405 {
4406         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4407         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4408         uint32_t reg;
4409         int ret;
4410
4411         if (!lut)
4412                 return -EINVAL;
4413
4414         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4415                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4416                                           vsi->type != I40E_VSI_SRIOV,
4417                                           lut, lut_size);
4418                 if (ret) {
4419                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4420                         return ret;
4421                 }
4422         } else {
4423                 uint32_t *lut_dw = (uint32_t *)lut;
4424                 uint16_t i, lut_size_dw = lut_size / 4;
4425
4426                 if (vsi->type == I40E_VSI_SRIOV) {
4427                         for (i = 0; i <= lut_size_dw; i++) {
4428                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4429                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4430                         }
4431                 } else {
4432                         for (i = 0; i < lut_size_dw; i++)
4433                                 lut_dw[i] = I40E_READ_REG(hw,
4434                                                           I40E_PFQF_HLUT(i));
4435                 }
4436         }
4437
4438         return 0;
4439 }
4440
4441 int
4442 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4443 {
4444         struct i40e_pf *pf;
4445         struct i40e_hw *hw;
4446
4447         if (!vsi || !lut)
4448                 return -EINVAL;
4449
4450         pf = I40E_VSI_TO_PF(vsi);
4451         hw = I40E_VSI_TO_HW(vsi);
4452
4453         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4454                 enum i40e_status_code status;
4455
4456                 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4457                                              vsi->type != I40E_VSI_SRIOV,
4458                                              lut, lut_size);
4459                 if (status) {
4460                         PMD_DRV_LOG(ERR,
4461                                     "Failed to update RSS lookup table, error status: %d",
4462                                     status);
4463                         return -EIO;
4464                 }
4465         } else {
4466                 uint32_t *lut_dw = (uint32_t *)lut;
4467                 uint16_t i, lut_size_dw = lut_size / 4;
4468
4469                 if (vsi->type == I40E_VSI_SRIOV) {
4470                         for (i = 0; i < lut_size_dw; i++)
4471                                 I40E_WRITE_REG(
4472                                         hw,
4473                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4474                                         lut_dw[i]);
4475                 } else {
4476                         for (i = 0; i < lut_size_dw; i++)
4477                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4478                                                lut_dw[i]);
4479                 }
4480                 I40E_WRITE_FLUSH(hw);
4481         }
4482
4483         return 0;
4484 }
4485
4486 static int
4487 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4488                          struct rte_eth_rss_reta_entry64 *reta_conf,
4489                          uint16_t reta_size)
4490 {
4491         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4492         uint16_t i, lut_size = pf->hash_lut_size;
4493         uint16_t idx, shift;
4494         uint8_t *lut;
4495         int ret;
4496
4497         if (reta_size != lut_size ||
4498                 reta_size > ETH_RSS_RETA_SIZE_512) {
4499                 PMD_DRV_LOG(ERR,
4500                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4501                         reta_size, lut_size);
4502                 return -EINVAL;
4503         }
4504
4505         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4506         if (!lut) {
4507                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4508                 return -ENOMEM;
4509         }
4510         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4511         if (ret)
4512                 goto out;
4513         for (i = 0; i < reta_size; i++) {
4514                 idx = i / RTE_RETA_GROUP_SIZE;
4515                 shift = i % RTE_RETA_GROUP_SIZE;
4516                 if (reta_conf[idx].mask & (1ULL << shift))
4517                         lut[i] = reta_conf[idx].reta[shift];
4518         }
4519         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4520
4521         pf->adapter->rss_reta_updated = 1;
4522
4523 out:
4524         rte_free(lut);
4525
4526         return ret;
4527 }
4528
4529 static int
4530 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4531                         struct rte_eth_rss_reta_entry64 *reta_conf,
4532                         uint16_t reta_size)
4533 {
4534         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4535         uint16_t i, lut_size = pf->hash_lut_size;
4536         uint16_t idx, shift;
4537         uint8_t *lut;
4538         int ret;
4539
4540         if (reta_size != lut_size ||
4541                 reta_size > ETH_RSS_RETA_SIZE_512) {
4542                 PMD_DRV_LOG(ERR,
4543                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4544                         reta_size, lut_size);
4545                 return -EINVAL;
4546         }
4547
4548         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4549         if (!lut) {
4550                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4551                 return -ENOMEM;
4552         }
4553
4554         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4555         if (ret)
4556                 goto out;
4557         for (i = 0; i < reta_size; i++) {
4558                 idx = i / RTE_RETA_GROUP_SIZE;
4559                 shift = i % RTE_RETA_GROUP_SIZE;
4560                 if (reta_conf[idx].mask & (1ULL << shift))
4561                         reta_conf[idx].reta[shift] = lut[i];
4562         }
4563
4564 out:
4565         rte_free(lut);
4566
4567         return ret;
4568 }
4569
4570 /**
4571  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4572  * @hw:   pointer to the HW structure
4573  * @mem:  pointer to mem struct to fill out
4574  * @size: size of memory requested
4575  * @alignment: what to align the allocation to
4576  **/
4577 enum i40e_status_code
4578 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4579                         struct i40e_dma_mem *mem,
4580                         u64 size,
4581                         u32 alignment)
4582 {
4583         const struct rte_memzone *mz = NULL;
4584         char z_name[RTE_MEMZONE_NAMESIZE];
4585
4586         if (!mem)
4587                 return I40E_ERR_PARAM;
4588
4589         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4590         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4591                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4592         if (!mz)
4593                 return I40E_ERR_NO_MEMORY;
4594
4595         mem->size = size;
4596         mem->va = mz->addr;
4597         mem->pa = mz->iova;
4598         mem->zone = (const void *)mz;
4599         PMD_DRV_LOG(DEBUG,
4600                 "memzone %s allocated with physical address: %"PRIu64,
4601                 mz->name, mem->pa);
4602
4603         return I40E_SUCCESS;
4604 }
4605
4606 /**
4607  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4608  * @hw:   pointer to the HW structure
4609  * @mem:  ptr to mem struct to free
4610  **/
4611 enum i40e_status_code
4612 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4613                     struct i40e_dma_mem *mem)
4614 {
4615         if (!mem)
4616                 return I40E_ERR_PARAM;
4617
4618         PMD_DRV_LOG(DEBUG,
4619                 "memzone %s to be freed with physical address: %"PRIu64,
4620                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4621         rte_memzone_free((const struct rte_memzone *)mem->zone);
4622         mem->zone = NULL;
4623         mem->va = NULL;
4624         mem->pa = (u64)0;
4625
4626         return I40E_SUCCESS;
4627 }
4628
4629 /**
4630  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4631  * @hw:   pointer to the HW structure
4632  * @mem:  pointer to mem struct to fill out
4633  * @size: size of memory requested
4634  **/
4635 enum i40e_status_code
4636 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4637                          struct i40e_virt_mem *mem,
4638                          u32 size)
4639 {
4640         if (!mem)
4641                 return I40E_ERR_PARAM;
4642
4643         mem->size = size;
4644         mem->va = rte_zmalloc("i40e", size, 0);
4645
4646         if (mem->va)
4647                 return I40E_SUCCESS;
4648         else
4649                 return I40E_ERR_NO_MEMORY;
4650 }
4651
4652 /**
4653  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4654  * @hw:   pointer to the HW structure
4655  * @mem:  pointer to mem struct to free
4656  **/
4657 enum i40e_status_code
4658 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4659                      struct i40e_virt_mem *mem)
4660 {
4661         if (!mem)
4662                 return I40E_ERR_PARAM;
4663
4664         rte_free(mem->va);
4665         mem->va = NULL;
4666
4667         return I40E_SUCCESS;
4668 }
4669
4670 void
4671 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4672 {
4673         rte_spinlock_init(&sp->spinlock);
4674 }
4675
4676 void
4677 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4678 {
4679         rte_spinlock_lock(&sp->spinlock);
4680 }
4681
4682 void
4683 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4684 {
4685         rte_spinlock_unlock(&sp->spinlock);
4686 }
4687
4688 void
4689 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4690 {
4691         return;
4692 }
4693
4694 /**
4695  * Get the hardware capabilities, which will be parsed
4696  * and saved into struct i40e_hw.
4697  */
4698 static int
4699 i40e_get_cap(struct i40e_hw *hw)
4700 {
4701         struct i40e_aqc_list_capabilities_element_resp *buf;
4702         uint16_t len, size = 0;
4703         int ret;
4704
4705         /* Calculate a huge enough buff for saving response data temporarily */
4706         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4707                                                 I40E_MAX_CAP_ELE_NUM;
4708         buf = rte_zmalloc("i40e", len, 0);
4709         if (!buf) {
4710                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4711                 return I40E_ERR_NO_MEMORY;
4712         }
4713
4714         /* Get, parse the capabilities and save it to hw */
4715         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4716                         i40e_aqc_opc_list_func_capabilities, NULL);
4717         if (ret != I40E_SUCCESS)
4718                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4719
4720         /* Free the temporary buffer after being used */
4721         rte_free(buf);
4722
4723         return ret;
4724 }
4725
4726 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4727
4728 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4729                 const char *value,
4730                 void *opaque)
4731 {
4732         struct i40e_pf *pf;
4733         unsigned long num;
4734         char *end;
4735
4736         pf = (struct i40e_pf *)opaque;
4737         RTE_SET_USED(key);
4738
4739         errno = 0;
4740         num = strtoul(value, &end, 0);
4741         if (errno != 0 || end == value || *end != 0) {
4742                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4743                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4744                 return -(EINVAL);
4745         }
4746
4747         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4748                 pf->vf_nb_qp_max = (uint16_t)num;
4749         else
4750                 /* here return 0 to make next valid same argument work */
4751                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4752                             "power of 2 and equal or less than 16 !, Now it is "
4753                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4754
4755         return 0;
4756 }
4757
4758 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4759 {
4760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4761         struct rte_kvargs *kvlist;
4762         int kvargs_count;
4763
4764         /* set default queue number per VF as 4 */
4765         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4766
4767         if (dev->device->devargs == NULL)
4768                 return 0;
4769
4770         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4771         if (kvlist == NULL)
4772                 return -(EINVAL);
4773
4774         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4775         if (!kvargs_count) {
4776                 rte_kvargs_free(kvlist);
4777                 return 0;
4778         }
4779
4780         if (kvargs_count > 1)
4781                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4782                             "the first invalid or last valid one is used !",
4783                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4784
4785         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4786                            i40e_pf_parse_vf_queue_number_handler, pf);
4787
4788         rte_kvargs_free(kvlist);
4789
4790         return 0;
4791 }
4792
4793 static int
4794 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4795 {
4796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4797         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4798         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4799         uint16_t qp_count = 0, vsi_count = 0;
4800
4801         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4802                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4803                 return -EINVAL;
4804         }
4805
4806         i40e_pf_config_vf_rxq_number(dev);
4807
4808         /* Add the parameter init for LFC */
4809         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4810         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4811         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4812
4813         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4814         pf->max_num_vsi = hw->func_caps.num_vsis;
4815         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4816         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4817
4818         /* FDir queue/VSI allocation */
4819         pf->fdir_qp_offset = 0;
4820         if (hw->func_caps.fd) {
4821                 pf->flags |= I40E_FLAG_FDIR;
4822                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4823         } else {
4824                 pf->fdir_nb_qps = 0;
4825         }
4826         qp_count += pf->fdir_nb_qps;
4827         vsi_count += 1;
4828
4829         /* LAN queue/VSI allocation */
4830         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4831         if (!hw->func_caps.rss) {
4832                 pf->lan_nb_qps = 1;
4833         } else {
4834                 pf->flags |= I40E_FLAG_RSS;
4835                 if (hw->mac.type == I40E_MAC_X722)
4836                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4837                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4838         }
4839         qp_count += pf->lan_nb_qps;
4840         vsi_count += 1;
4841
4842         /* VF queue/VSI allocation */
4843         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4844         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4845                 pf->flags |= I40E_FLAG_SRIOV;
4846                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4847                 pf->vf_num = pci_dev->max_vfs;
4848                 PMD_DRV_LOG(DEBUG,
4849                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4850                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4851         } else {
4852                 pf->vf_nb_qps = 0;
4853                 pf->vf_num = 0;
4854         }
4855         qp_count += pf->vf_nb_qps * pf->vf_num;
4856         vsi_count += pf->vf_num;
4857
4858         /* VMDq queue/VSI allocation */
4859         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4860         pf->vmdq_nb_qps = 0;
4861         pf->max_nb_vmdq_vsi = 0;
4862         if (hw->func_caps.vmdq) {
4863                 if (qp_count < hw->func_caps.num_tx_qp &&
4864                         vsi_count < hw->func_caps.num_vsis) {
4865                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4866                                 qp_count) / pf->vmdq_nb_qp_max;
4867
4868                         /* Limit the maximum number of VMDq vsi to the maximum
4869                          * ethdev can support
4870                          */
4871                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4872                                 hw->func_caps.num_vsis - vsi_count);
4873                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4874                                 ETH_64_POOLS);
4875                         if (pf->max_nb_vmdq_vsi) {
4876                                 pf->flags |= I40E_FLAG_VMDQ;
4877                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4878                                 PMD_DRV_LOG(DEBUG,
4879                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4880                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4881                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4882                         } else {
4883                                 PMD_DRV_LOG(INFO,
4884                                         "No enough queues left for VMDq");
4885                         }
4886                 } else {
4887                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4888                 }
4889         }
4890         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4891         vsi_count += pf->max_nb_vmdq_vsi;
4892
4893         if (hw->func_caps.dcb)
4894                 pf->flags |= I40E_FLAG_DCB;
4895
4896         if (qp_count > hw->func_caps.num_tx_qp) {
4897                 PMD_DRV_LOG(ERR,
4898                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4899                         qp_count, hw->func_caps.num_tx_qp);
4900                 return -EINVAL;
4901         }
4902         if (vsi_count > hw->func_caps.num_vsis) {
4903                 PMD_DRV_LOG(ERR,
4904                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4905                         vsi_count, hw->func_caps.num_vsis);
4906                 return -EINVAL;
4907         }
4908
4909         return 0;
4910 }
4911
4912 static int
4913 i40e_pf_get_switch_config(struct i40e_pf *pf)
4914 {
4915         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4916         struct i40e_aqc_get_switch_config_resp *switch_config;
4917         struct i40e_aqc_switch_config_element_resp *element;
4918         uint16_t start_seid = 0, num_reported;
4919         int ret;
4920
4921         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4922                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4923         if (!switch_config) {
4924                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4925                 return -ENOMEM;
4926         }
4927
4928         /* Get the switch configurations */
4929         ret = i40e_aq_get_switch_config(hw, switch_config,
4930                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4931         if (ret != I40E_SUCCESS) {
4932                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4933                 goto fail;
4934         }
4935         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4936         if (num_reported != 1) { /* The number should be 1 */
4937                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4938                 goto fail;
4939         }
4940
4941         /* Parse the switch configuration elements */
4942         element = &(switch_config->element[0]);
4943         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4944                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4945                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4946         } else
4947                 PMD_DRV_LOG(INFO, "Unknown element type");
4948
4949 fail:
4950         rte_free(switch_config);
4951
4952         return ret;
4953 }
4954
4955 static int
4956 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4957                         uint32_t num)
4958 {
4959         struct pool_entry *entry;
4960
4961         if (pool == NULL || num == 0)
4962                 return -EINVAL;
4963
4964         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4965         if (entry == NULL) {
4966                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4967                 return -ENOMEM;
4968         }
4969
4970         /* queue heap initialize */
4971         pool->num_free = num;
4972         pool->num_alloc = 0;
4973         pool->base = base;
4974         LIST_INIT(&pool->alloc_list);
4975         LIST_INIT(&pool->free_list);
4976
4977         /* Initialize element  */
4978         entry->base = 0;
4979         entry->len = num;
4980
4981         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4982         return 0;
4983 }
4984
4985 static void
4986 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4987 {
4988         struct pool_entry *entry, *next_entry;
4989
4990         if (pool == NULL)
4991                 return;
4992
4993         for (entry = LIST_FIRST(&pool->alloc_list);
4994                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4995                         entry = next_entry) {
4996                 LIST_REMOVE(entry, next);
4997                 rte_free(entry);
4998         }
4999
5000         for (entry = LIST_FIRST(&pool->free_list);
5001                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5002                         entry = next_entry) {
5003                 LIST_REMOVE(entry, next);
5004                 rte_free(entry);
5005         }
5006
5007         pool->num_free = 0;
5008         pool->num_alloc = 0;
5009         pool->base = 0;
5010         LIST_INIT(&pool->alloc_list);
5011         LIST_INIT(&pool->free_list);
5012 }
5013
5014 static int
5015 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5016                        uint32_t base)
5017 {
5018         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5019         uint32_t pool_offset;
5020         uint16_t len;
5021         int insert;
5022
5023         if (pool == NULL) {
5024                 PMD_DRV_LOG(ERR, "Invalid parameter");
5025                 return -EINVAL;
5026         }
5027
5028         pool_offset = base - pool->base;
5029         /* Lookup in alloc list */
5030         LIST_FOREACH(entry, &pool->alloc_list, next) {
5031                 if (entry->base == pool_offset) {
5032                         valid_entry = entry;
5033                         LIST_REMOVE(entry, next);
5034                         break;
5035                 }
5036         }
5037
5038         /* Not find, return */
5039         if (valid_entry == NULL) {
5040                 PMD_DRV_LOG(ERR, "Failed to find entry");
5041                 return -EINVAL;
5042         }
5043
5044         /**
5045          * Found it, move it to free list  and try to merge.
5046          * In order to make merge easier, always sort it by qbase.
5047          * Find adjacent prev and last entries.
5048          */
5049         prev = next = NULL;
5050         LIST_FOREACH(entry, &pool->free_list, next) {
5051                 if (entry->base > valid_entry->base) {
5052                         next = entry;
5053                         break;
5054                 }
5055                 prev = entry;
5056         }
5057
5058         insert = 0;
5059         len = valid_entry->len;
5060         /* Try to merge with next one*/
5061         if (next != NULL) {
5062                 /* Merge with next one */
5063                 if (valid_entry->base + len == next->base) {
5064                         next->base = valid_entry->base;
5065                         next->len += len;
5066                         rte_free(valid_entry);
5067                         valid_entry = next;
5068                         insert = 1;
5069                 }
5070         }
5071
5072         if (prev != NULL) {
5073                 /* Merge with previous one */
5074                 if (prev->base + prev->len == valid_entry->base) {
5075                         prev->len += len;
5076                         /* If it merge with next one, remove next node */
5077                         if (insert == 1) {
5078                                 LIST_REMOVE(valid_entry, next);
5079                                 rte_free(valid_entry);
5080                                 valid_entry = NULL;
5081                         } else {
5082                                 rte_free(valid_entry);
5083                                 valid_entry = NULL;
5084                                 insert = 1;
5085                         }
5086                 }
5087         }
5088
5089         /* Not find any entry to merge, insert */
5090         if (insert == 0) {
5091                 if (prev != NULL)
5092                         LIST_INSERT_AFTER(prev, valid_entry, next);
5093                 else if (next != NULL)
5094                         LIST_INSERT_BEFORE(next, valid_entry, next);
5095                 else /* It's empty list, insert to head */
5096                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5097         }
5098
5099         pool->num_free += len;
5100         pool->num_alloc -= len;
5101
5102         return 0;
5103 }
5104
5105 static int
5106 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5107                        uint16_t num)
5108 {
5109         struct pool_entry *entry, *valid_entry;
5110
5111         if (pool == NULL || num == 0) {
5112                 PMD_DRV_LOG(ERR, "Invalid parameter");
5113                 return -EINVAL;
5114         }
5115
5116         if (pool->num_free < num) {
5117                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5118                             num, pool->num_free);
5119                 return -ENOMEM;
5120         }
5121
5122         valid_entry = NULL;
5123         /* Lookup  in free list and find most fit one */
5124         LIST_FOREACH(entry, &pool->free_list, next) {
5125                 if (entry->len >= num) {
5126                         /* Find best one */
5127                         if (entry->len == num) {
5128                                 valid_entry = entry;
5129                                 break;
5130                         }
5131                         if (valid_entry == NULL || valid_entry->len > entry->len)
5132                                 valid_entry = entry;
5133                 }
5134         }
5135
5136         /* Not find one to satisfy the request, return */
5137         if (valid_entry == NULL) {
5138                 PMD_DRV_LOG(ERR, "No valid entry found");
5139                 return -ENOMEM;
5140         }
5141         /**
5142          * The entry have equal queue number as requested,
5143          * remove it from alloc_list.
5144          */
5145         if (valid_entry->len == num) {
5146                 LIST_REMOVE(valid_entry, next);
5147         } else {
5148                 /**
5149                  * The entry have more numbers than requested,
5150                  * create a new entry for alloc_list and minus its
5151                  * queue base and number in free_list.
5152                  */
5153                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5154                 if (entry == NULL) {
5155                         PMD_DRV_LOG(ERR,
5156                                 "Failed to allocate memory for resource pool");
5157                         return -ENOMEM;
5158                 }
5159                 entry->base = valid_entry->base;
5160                 entry->len = num;
5161                 valid_entry->base += num;
5162                 valid_entry->len -= num;
5163                 valid_entry = entry;
5164         }
5165
5166         /* Insert it into alloc list, not sorted */
5167         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5168
5169         pool->num_free -= valid_entry->len;
5170         pool->num_alloc += valid_entry->len;
5171
5172         return valid_entry->base + pool->base;
5173 }
5174
5175 /**
5176  * bitmap_is_subset - Check whether src2 is subset of src1
5177  **/
5178 static inline int
5179 bitmap_is_subset(uint8_t src1, uint8_t src2)
5180 {
5181         return !((src1 ^ src2) & src2);
5182 }
5183
5184 static enum i40e_status_code
5185 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5186 {
5187         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5188
5189         /* If DCB is not supported, only default TC is supported */
5190         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5191                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5192                 return I40E_NOT_SUPPORTED;
5193         }
5194
5195         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5196                 PMD_DRV_LOG(ERR,
5197                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5198                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5199                 return I40E_NOT_SUPPORTED;
5200         }
5201         return I40E_SUCCESS;
5202 }
5203
5204 int
5205 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5206                                 struct i40e_vsi_vlan_pvid_info *info)
5207 {
5208         struct i40e_hw *hw;
5209         struct i40e_vsi_context ctxt;
5210         uint8_t vlan_flags = 0;
5211         int ret;
5212
5213         if (vsi == NULL || info == NULL) {
5214                 PMD_DRV_LOG(ERR, "invalid parameters");
5215                 return I40E_ERR_PARAM;
5216         }
5217
5218         if (info->on) {
5219                 vsi->info.pvid = info->config.pvid;
5220                 /**
5221                  * If insert pvid is enabled, only tagged pkts are
5222                  * allowed to be sent out.
5223                  */
5224                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5225                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5226         } else {
5227                 vsi->info.pvid = 0;
5228                 if (info->config.reject.tagged == 0)
5229                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5230
5231                 if (info->config.reject.untagged == 0)
5232                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5233         }
5234         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5235                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5236         vsi->info.port_vlan_flags |= vlan_flags;
5237         vsi->info.valid_sections =
5238                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5239         memset(&ctxt, 0, sizeof(ctxt));
5240         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5241         ctxt.seid = vsi->seid;
5242
5243         hw = I40E_VSI_TO_HW(vsi);
5244         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5245         if (ret != I40E_SUCCESS)
5246                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5247
5248         return ret;
5249 }
5250
5251 static int
5252 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5253 {
5254         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5255         int i, ret;
5256         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5257
5258         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5259         if (ret != I40E_SUCCESS)
5260                 return ret;
5261
5262         if (!vsi->seid) {
5263                 PMD_DRV_LOG(ERR, "seid not valid");
5264                 return -EINVAL;
5265         }
5266
5267         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5268         tc_bw_data.tc_valid_bits = enabled_tcmap;
5269         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5270                 tc_bw_data.tc_bw_credits[i] =
5271                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5272
5273         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5274         if (ret != I40E_SUCCESS) {
5275                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5276                 return ret;
5277         }
5278
5279         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5280                                         sizeof(vsi->info.qs_handle));
5281         return I40E_SUCCESS;
5282 }
5283
5284 static enum i40e_status_code
5285 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5286                                  struct i40e_aqc_vsi_properties_data *info,
5287                                  uint8_t enabled_tcmap)
5288 {
5289         enum i40e_status_code ret;
5290         int i, total_tc = 0;
5291         uint16_t qpnum_per_tc, bsf, qp_idx;
5292
5293         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5294         if (ret != I40E_SUCCESS)
5295                 return ret;
5296
5297         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5298                 if (enabled_tcmap & (1 << i))
5299                         total_tc++;
5300         if (total_tc == 0)
5301                 total_tc = 1;
5302         vsi->enabled_tc = enabled_tcmap;
5303
5304         /* Number of queues per enabled TC */
5305         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5306         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5307         bsf = rte_bsf32(qpnum_per_tc);
5308
5309         /* Adjust the queue number to actual queues that can be applied */
5310         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5311                 vsi->nb_qps = qpnum_per_tc * total_tc;
5312
5313         /**
5314          * Configure TC and queue mapping parameters, for enabled TC,
5315          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5316          * default queue will serve it.
5317          */
5318         qp_idx = 0;
5319         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5320                 if (vsi->enabled_tc & (1 << i)) {
5321                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5322                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5323                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5324                         qp_idx += qpnum_per_tc;
5325                 } else
5326                         info->tc_mapping[i] = 0;
5327         }
5328
5329         /* Associate queue number with VSI */
5330         if (vsi->type == I40E_VSI_SRIOV) {
5331                 info->mapping_flags |=
5332                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5333                 for (i = 0; i < vsi->nb_qps; i++)
5334                         info->queue_mapping[i] =
5335                                 rte_cpu_to_le_16(vsi->base_queue + i);
5336         } else {
5337                 info->mapping_flags |=
5338                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5339                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5340         }
5341         info->valid_sections |=
5342                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5343
5344         return I40E_SUCCESS;
5345 }
5346
5347 static int
5348 i40e_veb_release(struct i40e_veb *veb)
5349 {
5350         struct i40e_vsi *vsi;
5351         struct i40e_hw *hw;
5352
5353         if (veb == NULL)
5354                 return -EINVAL;
5355
5356         if (!TAILQ_EMPTY(&veb->head)) {
5357                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5358                 return -EACCES;
5359         }
5360         /* associate_vsi field is NULL for floating VEB */
5361         if (veb->associate_vsi != NULL) {
5362                 vsi = veb->associate_vsi;
5363                 hw = I40E_VSI_TO_HW(vsi);
5364
5365                 vsi->uplink_seid = veb->uplink_seid;
5366                 vsi->veb = NULL;
5367         } else {
5368                 veb->associate_pf->main_vsi->floating_veb = NULL;
5369                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5370         }
5371
5372         i40e_aq_delete_element(hw, veb->seid, NULL);
5373         rte_free(veb);
5374         return I40E_SUCCESS;
5375 }
5376
5377 /* Setup a veb */
5378 static struct i40e_veb *
5379 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5380 {
5381         struct i40e_veb *veb;
5382         int ret;
5383         struct i40e_hw *hw;
5384
5385         if (pf == NULL) {
5386                 PMD_DRV_LOG(ERR,
5387                             "veb setup failed, associated PF shouldn't null");
5388                 return NULL;
5389         }
5390         hw = I40E_PF_TO_HW(pf);
5391
5392         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5393         if (!veb) {
5394                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5395                 goto fail;
5396         }
5397
5398         veb->associate_vsi = vsi;
5399         veb->associate_pf = pf;
5400         TAILQ_INIT(&veb->head);
5401         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5402
5403         /* create floating veb if vsi is NULL */
5404         if (vsi != NULL) {
5405                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5406                                       I40E_DEFAULT_TCMAP, false,
5407                                       &veb->seid, false, NULL);
5408         } else {
5409                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5410                                       true, &veb->seid, false, NULL);
5411         }
5412
5413         if (ret != I40E_SUCCESS) {
5414                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5415                             hw->aq.asq_last_status);
5416                 goto fail;
5417         }
5418         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5419
5420         /* get statistics index */
5421         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5422                                 &veb->stats_idx, NULL, NULL, NULL);
5423         if (ret != I40E_SUCCESS) {
5424                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5425                             hw->aq.asq_last_status);
5426                 goto fail;
5427         }
5428         /* Get VEB bandwidth, to be implemented */
5429         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5430         if (vsi)
5431                 vsi->uplink_seid = veb->seid;
5432
5433         return veb;
5434 fail:
5435         rte_free(veb);
5436         return NULL;
5437 }
5438
5439 int
5440 i40e_vsi_release(struct i40e_vsi *vsi)
5441 {
5442         struct i40e_pf *pf;
5443         struct i40e_hw *hw;
5444         struct i40e_vsi_list *vsi_list;
5445         void *temp;
5446         int ret;
5447         struct i40e_mac_filter *f;
5448         uint16_t user_param;
5449
5450         if (!vsi)
5451                 return I40E_SUCCESS;
5452
5453         if (!vsi->adapter)
5454                 return -EFAULT;
5455
5456         user_param = vsi->user_param;
5457
5458         pf = I40E_VSI_TO_PF(vsi);
5459         hw = I40E_VSI_TO_HW(vsi);
5460
5461         /* VSI has child to attach, release child first */
5462         if (vsi->veb) {
5463                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5464                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5465                                 return -1;
5466                 }
5467                 i40e_veb_release(vsi->veb);
5468         }
5469
5470         if (vsi->floating_veb) {
5471                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5472                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5473                                 return -1;
5474                 }
5475         }
5476
5477         /* Remove all macvlan filters of the VSI */
5478         i40e_vsi_remove_all_macvlan_filter(vsi);
5479         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5480                 rte_free(f);
5481
5482         if (vsi->type != I40E_VSI_MAIN &&
5483             ((vsi->type != I40E_VSI_SRIOV) ||
5484             !pf->floating_veb_list[user_param])) {
5485                 /* Remove vsi from parent's sibling list */
5486                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5487                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5488                         return I40E_ERR_PARAM;
5489                 }
5490                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5491                                 &vsi->sib_vsi_list, list);
5492
5493                 /* Remove all switch element of the VSI */
5494                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5495                 if (ret != I40E_SUCCESS)
5496                         PMD_DRV_LOG(ERR, "Failed to delete element");
5497         }
5498
5499         if ((vsi->type == I40E_VSI_SRIOV) &&
5500             pf->floating_veb_list[user_param]) {
5501                 /* Remove vsi from parent's sibling list */
5502                 if (vsi->parent_vsi == NULL ||
5503                     vsi->parent_vsi->floating_veb == NULL) {
5504                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5505                         return I40E_ERR_PARAM;
5506                 }
5507                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5508                              &vsi->sib_vsi_list, list);
5509
5510                 /* Remove all switch element of the VSI */
5511                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5512                 if (ret != I40E_SUCCESS)
5513                         PMD_DRV_LOG(ERR, "Failed to delete element");
5514         }
5515
5516         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5517
5518         if (vsi->type != I40E_VSI_SRIOV)
5519                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5520         rte_free(vsi);
5521
5522         return I40E_SUCCESS;
5523 }
5524
5525 static int
5526 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5527 {
5528         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5529         struct i40e_aqc_remove_macvlan_element_data def_filter;
5530         struct i40e_mac_filter_info filter;
5531         int ret;
5532
5533         if (vsi->type != I40E_VSI_MAIN)
5534                 return I40E_ERR_CONFIG;
5535         memset(&def_filter, 0, sizeof(def_filter));
5536         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5537                                         ETH_ADDR_LEN);
5538         def_filter.vlan_tag = 0;
5539         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5540                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5541         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5542         if (ret != I40E_SUCCESS) {
5543                 struct i40e_mac_filter *f;
5544                 struct rte_ether_addr *mac;
5545
5546                 PMD_DRV_LOG(DEBUG,
5547                             "Cannot remove the default macvlan filter");
5548                 /* It needs to add the permanent mac into mac list */
5549                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5550                 if (f == NULL) {
5551                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5552                         return I40E_ERR_NO_MEMORY;
5553                 }
5554                 mac = &f->mac_info.mac_addr;
5555                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5556                                 ETH_ADDR_LEN);
5557                 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5558                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5559                 vsi->mac_num++;
5560
5561                 return ret;
5562         }
5563         rte_memcpy(&filter.mac_addr,
5564                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5565         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5566         return i40e_vsi_add_mac(vsi, &filter);
5567 }
5568
5569 /*
5570  * i40e_vsi_get_bw_config - Query VSI BW Information
5571  * @vsi: the VSI to be queried
5572  *
5573  * Returns 0 on success, negative value on failure
5574  */
5575 static enum i40e_status_code
5576 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5577 {
5578         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5579         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5580         struct i40e_hw *hw = &vsi->adapter->hw;
5581         i40e_status ret;
5582         int i;
5583         uint32_t bw_max;
5584
5585         memset(&bw_config, 0, sizeof(bw_config));
5586         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5587         if (ret != I40E_SUCCESS) {
5588                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5589                             hw->aq.asq_last_status);
5590                 return ret;
5591         }
5592
5593         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5594         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5595                                         &ets_sla_config, NULL);
5596         if (ret != I40E_SUCCESS) {
5597                 PMD_DRV_LOG(ERR,
5598                         "VSI failed to get TC bandwdith configuration %u",
5599                         hw->aq.asq_last_status);
5600                 return ret;
5601         }
5602
5603         /* store and print out BW info */
5604         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5605         vsi->bw_info.bw_max = bw_config.max_bw;
5606         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5607         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5608         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5609                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5610                      I40E_16_BIT_WIDTH);
5611         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5612                 vsi->bw_info.bw_ets_share_credits[i] =
5613                                 ets_sla_config.share_credits[i];
5614                 vsi->bw_info.bw_ets_credits[i] =
5615                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5616                 /* 4 bits per TC, 4th bit is reserved */
5617                 vsi->bw_info.bw_ets_max[i] =
5618                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5619                                   RTE_LEN2MASK(3, uint8_t));
5620                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5621                             vsi->bw_info.bw_ets_share_credits[i]);
5622                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5623                             vsi->bw_info.bw_ets_credits[i]);
5624                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5625                             vsi->bw_info.bw_ets_max[i]);
5626         }
5627
5628         return I40E_SUCCESS;
5629 }
5630
5631 /* i40e_enable_pf_lb
5632  * @pf: pointer to the pf structure
5633  *
5634  * allow loopback on pf
5635  */
5636 static inline void
5637 i40e_enable_pf_lb(struct i40e_pf *pf)
5638 {
5639         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5640         struct i40e_vsi_context ctxt;
5641         int ret;
5642
5643         /* Use the FW API if FW >= v5.0 */
5644         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5645                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5646                 return;
5647         }
5648
5649         memset(&ctxt, 0, sizeof(ctxt));
5650         ctxt.seid = pf->main_vsi_seid;
5651         ctxt.pf_num = hw->pf_id;
5652         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5653         if (ret) {
5654                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5655                             ret, hw->aq.asq_last_status);
5656                 return;
5657         }
5658         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5659         ctxt.info.valid_sections =
5660                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5661         ctxt.info.switch_id |=
5662                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5663
5664         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5665         if (ret)
5666                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5667                             hw->aq.asq_last_status);
5668 }
5669
5670 /* Setup a VSI */
5671 struct i40e_vsi *
5672 i40e_vsi_setup(struct i40e_pf *pf,
5673                enum i40e_vsi_type type,
5674                struct i40e_vsi *uplink_vsi,
5675                uint16_t user_param)
5676 {
5677         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5678         struct i40e_vsi *vsi;
5679         struct i40e_mac_filter_info filter;
5680         int ret;
5681         struct i40e_vsi_context ctxt;
5682         struct rte_ether_addr broadcast =
5683                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5684
5685         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5686             uplink_vsi == NULL) {
5687                 PMD_DRV_LOG(ERR,
5688                         "VSI setup failed, VSI link shouldn't be NULL");
5689                 return NULL;
5690         }
5691
5692         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5693                 PMD_DRV_LOG(ERR,
5694                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5695                 return NULL;
5696         }
5697
5698         /* two situations
5699          * 1.type is not MAIN and uplink vsi is not NULL
5700          * If uplink vsi didn't setup VEB, create one first under veb field
5701          * 2.type is SRIOV and the uplink is NULL
5702          * If floating VEB is NULL, create one veb under floating veb field
5703          */
5704
5705         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5706             uplink_vsi->veb == NULL) {
5707                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5708
5709                 if (uplink_vsi->veb == NULL) {
5710                         PMD_DRV_LOG(ERR, "VEB setup failed");
5711                         return NULL;
5712                 }
5713                 /* set ALLOWLOOPBACk on pf, when veb is created */
5714                 i40e_enable_pf_lb(pf);
5715         }
5716
5717         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5718             pf->main_vsi->floating_veb == NULL) {
5719                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5720
5721                 if (pf->main_vsi->floating_veb == NULL) {
5722                         PMD_DRV_LOG(ERR, "VEB setup failed");
5723                         return NULL;
5724                 }
5725         }
5726
5727         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5728         if (!vsi) {
5729                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5730                 return NULL;
5731         }
5732         TAILQ_INIT(&vsi->mac_list);
5733         vsi->type = type;
5734         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5735         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5736         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5737         vsi->user_param = user_param;
5738         vsi->vlan_anti_spoof_on = 0;
5739         vsi->vlan_filter_on = 0;
5740         /* Allocate queues */
5741         switch (vsi->type) {
5742         case I40E_VSI_MAIN  :
5743                 vsi->nb_qps = pf->lan_nb_qps;
5744                 break;
5745         case I40E_VSI_SRIOV :
5746                 vsi->nb_qps = pf->vf_nb_qps;
5747                 break;
5748         case I40E_VSI_VMDQ2:
5749                 vsi->nb_qps = pf->vmdq_nb_qps;
5750                 break;
5751         case I40E_VSI_FDIR:
5752                 vsi->nb_qps = pf->fdir_nb_qps;
5753                 break;
5754         default:
5755                 goto fail_mem;
5756         }
5757         /*
5758          * The filter status descriptor is reported in rx queue 0,
5759          * while the tx queue for fdir filter programming has no
5760          * such constraints, can be non-zero queues.
5761          * To simplify it, choose FDIR vsi use queue 0 pair.
5762          * To make sure it will use queue 0 pair, queue allocation
5763          * need be done before this function is called
5764          */
5765         if (type != I40E_VSI_FDIR) {
5766                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5767                         if (ret < 0) {
5768                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5769                                                 vsi->seid, ret);
5770                                 goto fail_mem;
5771                         }
5772                         vsi->base_queue = ret;
5773         } else
5774                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5775
5776         /* VF has MSIX interrupt in VF range, don't allocate here */
5777         if (type == I40E_VSI_MAIN) {
5778                 if (pf->support_multi_driver) {
5779                         /* If support multi-driver, need to use INT0 instead of
5780                          * allocating from msix pool. The Msix pool is init from
5781                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5782                          * to 1 without calling i40e_res_pool_alloc.
5783                          */
5784                         vsi->msix_intr = 0;
5785                         vsi->nb_msix = 1;
5786                 } else {
5787                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5788                                                   RTE_MIN(vsi->nb_qps,
5789                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5790                         if (ret < 0) {
5791                                 PMD_DRV_LOG(ERR,
5792                                             "VSI MAIN %d get heap failed %d",
5793                                             vsi->seid, ret);
5794                                 goto fail_queue_alloc;
5795                         }
5796                         vsi->msix_intr = ret;
5797                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5798                                                RTE_MAX_RXTX_INTR_VEC_ID);
5799                 }
5800         } else if (type != I40E_VSI_SRIOV) {
5801                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5802                 if (ret < 0) {
5803                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5804                         if (type != I40E_VSI_FDIR)
5805                                 goto fail_queue_alloc;
5806                         vsi->msix_intr = 0;
5807                         vsi->nb_msix = 0;
5808                 } else {
5809                         vsi->msix_intr = ret;
5810                         vsi->nb_msix = 1;
5811                 }
5812         } else {
5813                 vsi->msix_intr = 0;
5814                 vsi->nb_msix = 0;
5815         }
5816
5817         /* Add VSI */
5818         if (type == I40E_VSI_MAIN) {
5819                 /* For main VSI, no need to add since it's default one */
5820                 vsi->uplink_seid = pf->mac_seid;
5821                 vsi->seid = pf->main_vsi_seid;
5822                 /* Bind queues with specific MSIX interrupt */
5823                 /**
5824                  * Needs 2 interrupt at least, one for misc cause which will
5825                  * enabled from OS side, Another for queues binding the
5826                  * interrupt from device side only.
5827                  */
5828
5829                 /* Get default VSI parameters from hardware */
5830                 memset(&ctxt, 0, sizeof(ctxt));
5831                 ctxt.seid = vsi->seid;
5832                 ctxt.pf_num = hw->pf_id;
5833                 ctxt.uplink_seid = vsi->uplink_seid;
5834                 ctxt.vf_num = 0;
5835                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5836                 if (ret != I40E_SUCCESS) {
5837                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5838                         goto fail_msix_alloc;
5839                 }
5840                 rte_memcpy(&vsi->info, &ctxt.info,
5841                         sizeof(struct i40e_aqc_vsi_properties_data));
5842                 vsi->vsi_id = ctxt.vsi_number;
5843                 vsi->info.valid_sections = 0;
5844
5845                 /* Configure tc, enabled TC0 only */
5846                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5847                         I40E_SUCCESS) {
5848                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5849                         goto fail_msix_alloc;
5850                 }
5851
5852                 /* TC, queue mapping */
5853                 memset(&ctxt, 0, sizeof(ctxt));
5854                 vsi->info.valid_sections |=
5855                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5856                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5857                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5858                 rte_memcpy(&ctxt.info, &vsi->info,
5859                         sizeof(struct i40e_aqc_vsi_properties_data));
5860                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5861                                                 I40E_DEFAULT_TCMAP);
5862                 if (ret != I40E_SUCCESS) {
5863                         PMD_DRV_LOG(ERR,
5864                                 "Failed to configure TC queue mapping");
5865                         goto fail_msix_alloc;
5866                 }
5867                 ctxt.seid = vsi->seid;
5868                 ctxt.pf_num = hw->pf_id;
5869                 ctxt.uplink_seid = vsi->uplink_seid;
5870                 ctxt.vf_num = 0;
5871
5872                 /* Update VSI parameters */
5873                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5874                 if (ret != I40E_SUCCESS) {
5875                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5876                         goto fail_msix_alloc;
5877                 }
5878
5879                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5880                                                 sizeof(vsi->info.tc_mapping));
5881                 rte_memcpy(&vsi->info.queue_mapping,
5882                                 &ctxt.info.queue_mapping,
5883                         sizeof(vsi->info.queue_mapping));
5884                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5885                 vsi->info.valid_sections = 0;
5886
5887                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5888                                 ETH_ADDR_LEN);
5889
5890                 /**
5891                  * Updating default filter settings are necessary to prevent
5892                  * reception of tagged packets.
5893                  * Some old firmware configurations load a default macvlan
5894                  * filter which accepts both tagged and untagged packets.
5895                  * The updating is to use a normal filter instead if needed.
5896                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5897                  * The firmware with correct configurations load the default
5898                  * macvlan filter which is expected and cannot be removed.
5899                  */
5900                 i40e_update_default_filter_setting(vsi);
5901                 i40e_config_qinq(hw, vsi);
5902         } else if (type == I40E_VSI_SRIOV) {
5903                 memset(&ctxt, 0, sizeof(ctxt));
5904                 /**
5905                  * For other VSI, the uplink_seid equals to uplink VSI's
5906                  * uplink_seid since they share same VEB
5907                  */
5908                 if (uplink_vsi == NULL)
5909                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5910                 else
5911                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5912                 ctxt.pf_num = hw->pf_id;
5913                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5914                 ctxt.uplink_seid = vsi->uplink_seid;
5915                 ctxt.connection_type = 0x1;
5916                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5917
5918                 /* Use the VEB configuration if FW >= v5.0 */
5919                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5920                         /* Configure switch ID */
5921                         ctxt.info.valid_sections |=
5922                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5923                         ctxt.info.switch_id =
5924                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5925                 }
5926
5927                 /* Configure port/vlan */
5928                 ctxt.info.valid_sections |=
5929                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5930                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5931                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5932                                                 hw->func_caps.enabled_tcmap);
5933                 if (ret != I40E_SUCCESS) {
5934                         PMD_DRV_LOG(ERR,
5935                                 "Failed to configure TC queue mapping");
5936                         goto fail_msix_alloc;
5937                 }
5938
5939                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5940                 ctxt.info.valid_sections |=
5941                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5942                 /**
5943                  * Since VSI is not created yet, only configure parameter,
5944                  * will add vsi below.
5945                  */
5946
5947                 i40e_config_qinq(hw, vsi);
5948         } else if (type == I40E_VSI_VMDQ2) {
5949                 memset(&ctxt, 0, sizeof(ctxt));
5950                 /*
5951                  * For other VSI, the uplink_seid equals to uplink VSI's
5952                  * uplink_seid since they share same VEB
5953                  */
5954                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5955                 ctxt.pf_num = hw->pf_id;
5956                 ctxt.vf_num = 0;
5957                 ctxt.uplink_seid = vsi->uplink_seid;
5958                 ctxt.connection_type = 0x1;
5959                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5960
5961                 ctxt.info.valid_sections |=
5962                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5963                 /* user_param carries flag to enable loop back */
5964                 if (user_param) {
5965                         ctxt.info.switch_id =
5966                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5967                         ctxt.info.switch_id |=
5968                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5969                 }
5970
5971                 /* Configure port/vlan */
5972                 ctxt.info.valid_sections |=
5973                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5974                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5975                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5976                                                 I40E_DEFAULT_TCMAP);
5977                 if (ret != I40E_SUCCESS) {
5978                         PMD_DRV_LOG(ERR,
5979                                 "Failed to configure TC queue mapping");
5980                         goto fail_msix_alloc;
5981                 }
5982                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5983                 ctxt.info.valid_sections |=
5984                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5985         } else if (type == I40E_VSI_FDIR) {
5986                 memset(&ctxt, 0, sizeof(ctxt));
5987                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5988                 ctxt.pf_num = hw->pf_id;
5989                 ctxt.vf_num = 0;
5990                 ctxt.uplink_seid = vsi->uplink_seid;
5991                 ctxt.connection_type = 0x1;     /* regular data port */
5992                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5993                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5994                                                 I40E_DEFAULT_TCMAP);
5995                 if (ret != I40E_SUCCESS) {
5996                         PMD_DRV_LOG(ERR,
5997                                 "Failed to configure TC queue mapping.");
5998                         goto fail_msix_alloc;
5999                 }
6000                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6001                 ctxt.info.valid_sections |=
6002                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6003         } else {
6004                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6005                 goto fail_msix_alloc;
6006         }
6007
6008         if (vsi->type != I40E_VSI_MAIN) {
6009                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6010                 if (ret != I40E_SUCCESS) {
6011                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6012                                     hw->aq.asq_last_status);
6013                         goto fail_msix_alloc;
6014                 }
6015                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6016                 vsi->info.valid_sections = 0;
6017                 vsi->seid = ctxt.seid;
6018                 vsi->vsi_id = ctxt.vsi_number;
6019                 vsi->sib_vsi_list.vsi = vsi;
6020                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6021                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6022                                           &vsi->sib_vsi_list, list);
6023                 } else {
6024                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6025                                           &vsi->sib_vsi_list, list);
6026                 }
6027         }
6028
6029         /* MAC/VLAN configuration */
6030         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6031         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6032
6033         ret = i40e_vsi_add_mac(vsi, &filter);
6034         if (ret != I40E_SUCCESS) {
6035                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6036                 goto fail_msix_alloc;
6037         }
6038
6039         /* Get VSI BW information */
6040         i40e_vsi_get_bw_config(vsi);
6041         return vsi;
6042 fail_msix_alloc:
6043         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6044 fail_queue_alloc:
6045         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6046 fail_mem:
6047         rte_free(vsi);
6048         return NULL;
6049 }
6050
6051 /* Configure vlan filter on or off */
6052 int
6053 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6054 {
6055         int i, num;
6056         struct i40e_mac_filter *f;
6057         void *temp;
6058         struct i40e_mac_filter_info *mac_filter;
6059         enum i40e_mac_filter_type desired_filter;
6060         int ret = I40E_SUCCESS;
6061
6062         if (on) {
6063                 /* Filter to match MAC and VLAN */
6064                 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6065         } else {
6066                 /* Filter to match only MAC */
6067                 desired_filter = I40E_MAC_PERFECT_MATCH;
6068         }
6069
6070         num = vsi->mac_num;
6071
6072         mac_filter = rte_zmalloc("mac_filter_info_data",
6073                                  num * sizeof(*mac_filter), 0);
6074         if (mac_filter == NULL) {
6075                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6076                 return I40E_ERR_NO_MEMORY;
6077         }
6078
6079         i = 0;
6080
6081         /* Remove all existing mac */
6082         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6083                 mac_filter[i] = f->mac_info;
6084                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6085                 if (ret) {
6086                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6087                                     on ? "enable" : "disable");
6088                         goto DONE;
6089                 }
6090                 i++;
6091         }
6092
6093         /* Override with new filter */
6094         for (i = 0; i < num; i++) {
6095                 mac_filter[i].filter_type = desired_filter;
6096                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6097                 if (ret) {
6098                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6099                                     on ? "enable" : "disable");
6100                         goto DONE;
6101                 }
6102         }
6103
6104 DONE:
6105         rte_free(mac_filter);
6106         return ret;
6107 }
6108
6109 /* Configure vlan stripping on or off */
6110 int
6111 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6112 {
6113         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6114         struct i40e_vsi_context ctxt;
6115         uint8_t vlan_flags;
6116         int ret = I40E_SUCCESS;
6117
6118         /* Check if it has been already on or off */
6119         if (vsi->info.valid_sections &
6120                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6121                 if (on) {
6122                         if ((vsi->info.port_vlan_flags &
6123                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6124                                 return 0; /* already on */
6125                 } else {
6126                         if ((vsi->info.port_vlan_flags &
6127                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6128                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6129                                 return 0; /* already off */
6130                 }
6131         }
6132
6133         if (on)
6134                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6135         else
6136                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6137         vsi->info.valid_sections =
6138                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6139         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6140         vsi->info.port_vlan_flags |= vlan_flags;
6141         ctxt.seid = vsi->seid;
6142         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6143         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6144         if (ret)
6145                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6146                             on ? "enable" : "disable");
6147
6148         return ret;
6149 }
6150
6151 static int
6152 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6153 {
6154         struct rte_eth_dev_data *data = dev->data;
6155         int ret;
6156         int mask = 0;
6157
6158         /* Apply vlan offload setting */
6159         mask = ETH_VLAN_STRIP_MASK |
6160                ETH_QINQ_STRIP_MASK |
6161                ETH_VLAN_FILTER_MASK |
6162                ETH_VLAN_EXTEND_MASK;
6163         ret = i40e_vlan_offload_set(dev, mask);
6164         if (ret) {
6165                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6166                 return ret;
6167         }
6168
6169         /* Apply pvid setting */
6170         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6171                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6172         if (ret)
6173                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6174
6175         return ret;
6176 }
6177
6178 static int
6179 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6180 {
6181         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6182
6183         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6184 }
6185
6186 static int
6187 i40e_update_flow_control(struct i40e_hw *hw)
6188 {
6189 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6190         struct i40e_link_status link_status;
6191         uint32_t rxfc = 0, txfc = 0, reg;
6192         uint8_t an_info;
6193         int ret;
6194
6195         memset(&link_status, 0, sizeof(link_status));
6196         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6197         if (ret != I40E_SUCCESS) {
6198                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6199                 goto write_reg; /* Disable flow control */
6200         }
6201
6202         an_info = hw->phy.link_info.an_info;
6203         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6204                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6205                 ret = I40E_ERR_NOT_READY;
6206                 goto write_reg; /* Disable flow control */
6207         }
6208         /**
6209          * If link auto negotiation is enabled, flow control needs to
6210          * be configured according to it
6211          */
6212         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6213         case I40E_LINK_PAUSE_RXTX:
6214                 rxfc = 1;
6215                 txfc = 1;
6216                 hw->fc.current_mode = I40E_FC_FULL;
6217                 break;
6218         case I40E_AQ_LINK_PAUSE_RX:
6219                 rxfc = 1;
6220                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6221                 break;
6222         case I40E_AQ_LINK_PAUSE_TX:
6223                 txfc = 1;
6224                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6225                 break;
6226         default:
6227                 hw->fc.current_mode = I40E_FC_NONE;
6228                 break;
6229         }
6230
6231 write_reg:
6232         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6233                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6234         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6235         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6236         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6237         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6238
6239         return ret;
6240 }
6241
6242 /* PF setup */
6243 static int
6244 i40e_pf_setup(struct i40e_pf *pf)
6245 {
6246         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6247         struct i40e_filter_control_settings settings;
6248         struct i40e_vsi *vsi;
6249         int ret;
6250
6251         /* Clear all stats counters */
6252         pf->offset_loaded = FALSE;
6253         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6254         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6255         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6256         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6257
6258         ret = i40e_pf_get_switch_config(pf);
6259         if (ret != I40E_SUCCESS) {
6260                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6261                 return ret;
6262         }
6263
6264         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6265         if (ret)
6266                 PMD_INIT_LOG(WARNING,
6267                         "failed to allocate switch domain for device %d", ret);
6268
6269         if (pf->flags & I40E_FLAG_FDIR) {
6270                 /* make queue allocated first, let FDIR use queue pair 0*/
6271                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6272                 if (ret != I40E_FDIR_QUEUE_ID) {
6273                         PMD_DRV_LOG(ERR,
6274                                 "queue allocation fails for FDIR: ret =%d",
6275                                 ret);
6276                         pf->flags &= ~I40E_FLAG_FDIR;
6277                 }
6278         }
6279         /*  main VSI setup */
6280         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6281         if (!vsi) {
6282                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6283                 return I40E_ERR_NOT_READY;
6284         }
6285         pf->main_vsi = vsi;
6286
6287         /* Configure filter control */
6288         memset(&settings, 0, sizeof(settings));
6289         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6290                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6291         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6292                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6293         else {
6294                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6295                         hw->func_caps.rss_table_size);
6296                 return I40E_ERR_PARAM;
6297         }
6298         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6299                 hw->func_caps.rss_table_size);
6300         pf->hash_lut_size = hw->func_caps.rss_table_size;
6301
6302         /* Enable ethtype and macvlan filters */
6303         settings.enable_ethtype = TRUE;
6304         settings.enable_macvlan = TRUE;
6305         ret = i40e_set_filter_control(hw, &settings);
6306         if (ret)
6307                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6308                                                                 ret);
6309
6310         /* Update flow control according to the auto negotiation */
6311         i40e_update_flow_control(hw);
6312
6313         return I40E_SUCCESS;
6314 }
6315
6316 int
6317 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6318 {
6319         uint32_t reg;
6320         uint16_t j;
6321
6322         /**
6323          * Set or clear TX Queue Disable flags,
6324          * which is required by hardware.
6325          */
6326         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6327         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6328
6329         /* Wait until the request is finished */
6330         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6331                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6332                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6333                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6334                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6335                                                         & 0x1))) {
6336                         break;
6337                 }
6338         }
6339         if (on) {
6340                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6341                         return I40E_SUCCESS; /* already on, skip next steps */
6342
6343                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6344                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6345         } else {
6346                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6347                         return I40E_SUCCESS; /* already off, skip next steps */
6348                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6349         }
6350         /* Write the register */
6351         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6352         /* Check the result */
6353         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6354                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6355                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6356                 if (on) {
6357                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6358                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6359                                 break;
6360                 } else {
6361                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6362                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6363                                 break;
6364                 }
6365         }
6366         /* Check if it is timeout */
6367         if (j >= I40E_CHK_Q_ENA_COUNT) {
6368                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6369                             (on ? "enable" : "disable"), q_idx);
6370                 return I40E_ERR_TIMEOUT;
6371         }
6372
6373         return I40E_SUCCESS;
6374 }
6375
6376 int
6377 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6378 {
6379         uint32_t reg;
6380         uint16_t j;
6381
6382         /* Wait until the request is finished */
6383         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6384                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6385                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6386                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6387                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6388                         break;
6389         }
6390
6391         if (on) {
6392                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6393                         return I40E_SUCCESS; /* Already on, skip next steps */
6394                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6395         } else {
6396                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6397                         return I40E_SUCCESS; /* Already off, skip next steps */
6398                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6399         }
6400
6401         /* Write the register */
6402         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6403         /* Check the result */
6404         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6405                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6406                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6407                 if (on) {
6408                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6409                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6410                                 break;
6411                 } else {
6412                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6413                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6414                                 break;
6415                 }
6416         }
6417
6418         /* Check if it is timeout */
6419         if (j >= I40E_CHK_Q_ENA_COUNT) {
6420                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6421                             (on ? "enable" : "disable"), q_idx);
6422                 return I40E_ERR_TIMEOUT;
6423         }
6424
6425         return I40E_SUCCESS;
6426 }
6427
6428 /* Initialize VSI for TX */
6429 static int
6430 i40e_dev_tx_init(struct i40e_pf *pf)
6431 {
6432         struct rte_eth_dev_data *data = pf->dev_data;
6433         uint16_t i;
6434         uint32_t ret = I40E_SUCCESS;
6435         struct i40e_tx_queue *txq;
6436
6437         for (i = 0; i < data->nb_tx_queues; i++) {
6438                 txq = data->tx_queues[i];
6439                 if (!txq || !txq->q_set)
6440                         continue;
6441                 ret = i40e_tx_queue_init(txq);
6442                 if (ret != I40E_SUCCESS)
6443                         break;
6444         }
6445         if (ret == I40E_SUCCESS)
6446                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6447                                      ->eth_dev);
6448
6449         return ret;
6450 }
6451
6452 /* Initialize VSI for RX */
6453 static int
6454 i40e_dev_rx_init(struct i40e_pf *pf)
6455 {
6456         struct rte_eth_dev_data *data = pf->dev_data;
6457         int ret = I40E_SUCCESS;
6458         uint16_t i;
6459         struct i40e_rx_queue *rxq;
6460
6461         i40e_pf_config_rss(pf);
6462         for (i = 0; i < data->nb_rx_queues; i++) {
6463                 rxq = data->rx_queues[i];
6464                 if (!rxq || !rxq->q_set)
6465                         continue;
6466
6467                 ret = i40e_rx_queue_init(rxq);
6468                 if (ret != I40E_SUCCESS) {
6469                         PMD_DRV_LOG(ERR,
6470                                 "Failed to do RX queue initialization");
6471                         break;
6472                 }
6473         }
6474         if (ret == I40E_SUCCESS)
6475                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6476                                      ->eth_dev);
6477
6478         return ret;
6479 }
6480
6481 static int
6482 i40e_dev_rxtx_init(struct i40e_pf *pf)
6483 {
6484         int err;
6485
6486         err = i40e_dev_tx_init(pf);
6487         if (err) {
6488                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6489                 return err;
6490         }
6491         err = i40e_dev_rx_init(pf);
6492         if (err) {
6493                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6494                 return err;
6495         }
6496
6497         return err;
6498 }
6499
6500 static int
6501 i40e_vmdq_setup(struct rte_eth_dev *dev)
6502 {
6503         struct rte_eth_conf *conf = &dev->data->dev_conf;
6504         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6505         int i, err, conf_vsis, j, loop;
6506         struct i40e_vsi *vsi;
6507         struct i40e_vmdq_info *vmdq_info;
6508         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6509         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6510
6511         /*
6512          * Disable interrupt to avoid message from VF. Furthermore, it will
6513          * avoid race condition in VSI creation/destroy.
6514          */
6515         i40e_pf_disable_irq0(hw);
6516
6517         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6518                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6519                 return -ENOTSUP;
6520         }
6521
6522         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6523         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6524                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6525                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6526                         pf->max_nb_vmdq_vsi);
6527                 return -ENOTSUP;
6528         }
6529
6530         if (pf->vmdq != NULL) {
6531                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6532                 return 0;
6533         }
6534
6535         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6536                                 sizeof(*vmdq_info) * conf_vsis, 0);
6537
6538         if (pf->vmdq == NULL) {
6539                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6540                 return -ENOMEM;
6541         }
6542
6543         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6544
6545         /* Create VMDQ VSI */
6546         for (i = 0; i < conf_vsis; i++) {
6547                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6548                                 vmdq_conf->enable_loop_back);
6549                 if (vsi == NULL) {
6550                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6551                         err = -1;
6552                         goto err_vsi_setup;
6553                 }
6554                 vmdq_info = &pf->vmdq[i];
6555                 vmdq_info->pf = pf;
6556                 vmdq_info->vsi = vsi;
6557         }
6558         pf->nb_cfg_vmdq_vsi = conf_vsis;
6559
6560         /* Configure Vlan */
6561         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6562         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6563                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6564                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6565                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6566                                         vmdq_conf->pool_map[i].vlan_id, j);
6567
6568                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6569                                                 vmdq_conf->pool_map[i].vlan_id);
6570                                 if (err) {
6571                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6572                                         err = -1;
6573                                         goto err_vsi_setup;
6574                                 }
6575                         }
6576                 }
6577         }
6578
6579         i40e_pf_enable_irq0(hw);
6580
6581         return 0;
6582
6583 err_vsi_setup:
6584         for (i = 0; i < conf_vsis; i++)
6585                 if (pf->vmdq[i].vsi == NULL)
6586                         break;
6587                 else
6588                         i40e_vsi_release(pf->vmdq[i].vsi);
6589
6590         rte_free(pf->vmdq);
6591         pf->vmdq = NULL;
6592         i40e_pf_enable_irq0(hw);
6593         return err;
6594 }
6595
6596 static void
6597 i40e_stat_update_32(struct i40e_hw *hw,
6598                    uint32_t reg,
6599                    bool offset_loaded,
6600                    uint64_t *offset,
6601                    uint64_t *stat)
6602 {
6603         uint64_t new_data;
6604
6605         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6606         if (!offset_loaded)
6607                 *offset = new_data;
6608
6609         if (new_data >= *offset)
6610                 *stat = (uint64_t)(new_data - *offset);
6611         else
6612                 *stat = (uint64_t)((new_data +
6613                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6614 }
6615
6616 static void
6617 i40e_stat_update_48(struct i40e_hw *hw,
6618                    uint32_t hireg,
6619                    uint32_t loreg,
6620                    bool offset_loaded,
6621                    uint64_t *offset,
6622                    uint64_t *stat)
6623 {
6624         uint64_t new_data;
6625
6626         if (hw->device_id == I40E_DEV_ID_QEMU) {
6627                 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6628                 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6629                                 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6630         } else {
6631                 new_data = I40E_READ_REG64(hw, loreg);
6632         }
6633
6634         if (!offset_loaded)
6635                 *offset = new_data;
6636
6637         if (new_data >= *offset)
6638                 *stat = new_data - *offset;
6639         else
6640                 *stat = (uint64_t)((new_data +
6641                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6642
6643         *stat &= I40E_48_BIT_MASK;
6644 }
6645
6646 /* Disable IRQ0 */
6647 void
6648 i40e_pf_disable_irq0(struct i40e_hw *hw)
6649 {
6650         /* Disable all interrupt types */
6651         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6652                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6653         I40E_WRITE_FLUSH(hw);
6654 }
6655
6656 /* Enable IRQ0 */
6657 void
6658 i40e_pf_enable_irq0(struct i40e_hw *hw)
6659 {
6660         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6661                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6662                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6663                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6664         I40E_WRITE_FLUSH(hw);
6665 }
6666
6667 static void
6668 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6669 {
6670         /* read pending request and disable first */
6671         i40e_pf_disable_irq0(hw);
6672         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6673         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6674                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6675
6676         if (no_queue)
6677                 /* Link no queues with irq0 */
6678                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6679                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6680 }
6681
6682 static void
6683 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6684 {
6685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6686         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6687         int i;
6688         uint16_t abs_vf_id;
6689         uint32_t index, offset, val;
6690
6691         if (!pf->vfs)
6692                 return;
6693         /**
6694          * Try to find which VF trigger a reset, use absolute VF id to access
6695          * since the reg is global register.
6696          */
6697         for (i = 0; i < pf->vf_num; i++) {
6698                 abs_vf_id = hw->func_caps.vf_base_id + i;
6699                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6700                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6701                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6702                 /* VFR event occurred */
6703                 if (val & (0x1 << offset)) {
6704                         int ret;
6705
6706                         /* Clear the event first */
6707                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6708                                                         (0x1 << offset));
6709                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6710                         /**
6711                          * Only notify a VF reset event occurred,
6712                          * don't trigger another SW reset
6713                          */
6714                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6715                         if (ret != I40E_SUCCESS)
6716                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6717                 }
6718         }
6719 }
6720
6721 static void
6722 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6723 {
6724         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6725         int i;
6726
6727         for (i = 0; i < pf->vf_num; i++)
6728                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6729 }
6730
6731 static void
6732 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6733 {
6734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6735         struct i40e_arq_event_info info;
6736         uint16_t pending, opcode;
6737         int ret;
6738
6739         info.buf_len = I40E_AQ_BUF_SZ;
6740         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6741         if (!info.msg_buf) {
6742                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6743                 return;
6744         }
6745
6746         pending = 1;
6747         while (pending) {
6748                 ret = i40e_clean_arq_element(hw, &info, &pending);
6749
6750                 if (ret != I40E_SUCCESS) {
6751                         PMD_DRV_LOG(INFO,
6752                                 "Failed to read msg from AdminQ, aq_err: %u",
6753                                 hw->aq.asq_last_status);
6754                         break;
6755                 }
6756                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6757
6758                 switch (opcode) {
6759                 case i40e_aqc_opc_send_msg_to_pf:
6760                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6761                         i40e_pf_host_handle_vf_msg(dev,
6762                                         rte_le_to_cpu_16(info.desc.retval),
6763                                         rte_le_to_cpu_32(info.desc.cookie_high),
6764                                         rte_le_to_cpu_32(info.desc.cookie_low),
6765                                         info.msg_buf,
6766                                         info.msg_len);
6767                         break;
6768                 case i40e_aqc_opc_get_link_status:
6769                         ret = i40e_dev_link_update(dev, 0);
6770                         if (!ret)
6771                                 rte_eth_dev_callback_process(dev,
6772                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6773                         break;
6774                 default:
6775                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6776                                     opcode);
6777                         break;
6778                 }
6779         }
6780         rte_free(info.msg_buf);
6781 }
6782
6783 static void
6784 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6785 {
6786 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6787 #define I40E_MDD_CLEAR16 0xFFFF
6788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6790         bool mdd_detected = false;
6791         struct i40e_pf_vf *vf;
6792         uint32_t reg;
6793         int i;
6794
6795         /* find what triggered the MDD event */
6796         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6797         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6798                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6799                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6800                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6801                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6802                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6803                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6804                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6805                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6806                                         hw->func_caps.base_queue;
6807                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6808                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6809                                 event, queue, pf_num, vf_num, dev->data->name);
6810                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6811                 mdd_detected = true;
6812         }
6813         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6814         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6815                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6816                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6817                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6818                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6819                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6820                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6821                                         hw->func_caps.base_queue;
6822
6823                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6824                                 "queue %d of function 0x%02x device %s\n",
6825                                         event, queue, func, dev->data->name);
6826                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6827                 mdd_detected = true;
6828         }
6829
6830         if (mdd_detected) {
6831                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6832                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6833                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6834                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6835                 }
6836                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6837                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6838                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6839                                         I40E_MDD_CLEAR16);
6840                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6841                 }
6842         }
6843
6844         /* see if one of the VFs needs its hand slapped */
6845         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6846                 vf = &pf->vfs[i];
6847                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6848                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6849                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6850                                         I40E_MDD_CLEAR16);
6851                         vf->num_mdd_events++;
6852                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6853                                         PRIu64 "times\n",
6854                                         i, vf->num_mdd_events);
6855                 }
6856
6857                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6858                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6859                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6860                                         I40E_MDD_CLEAR16);
6861                         vf->num_mdd_events++;
6862                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6863                                         PRIu64 "times\n",
6864                                         i, vf->num_mdd_events);
6865                 }
6866         }
6867 }
6868
6869 /**
6870  * Interrupt handler triggered by NIC  for handling
6871  * specific interrupt.
6872  *
6873  * @param handle
6874  *  Pointer to interrupt handle.
6875  * @param param
6876  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6877  *
6878  * @return
6879  *  void
6880  */
6881 static void
6882 i40e_dev_interrupt_handler(void *param)
6883 {
6884         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886         uint32_t icr0;
6887
6888         /* Disable interrupt */
6889         i40e_pf_disable_irq0(hw);
6890
6891         /* read out interrupt causes */
6892         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6893
6894         /* No interrupt event indicated */
6895         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6896                 PMD_DRV_LOG(INFO, "No interrupt event");
6897                 goto done;
6898         }
6899         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6900                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6901         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6902                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6903                 i40e_handle_mdd_event(dev);
6904         }
6905         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6906                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6907         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6908                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6909         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6910                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6911         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6912                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6913         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6914                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6915
6916         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6917                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6918                 i40e_dev_handle_vfr_event(dev);
6919         }
6920         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6921                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6922                 i40e_dev_handle_aq_msg(dev);
6923         }
6924
6925 done:
6926         /* Enable interrupt */
6927         i40e_pf_enable_irq0(hw);
6928 }
6929
6930 static void
6931 i40e_dev_alarm_handler(void *param)
6932 {
6933         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6935         uint32_t icr0;
6936
6937         /* Disable interrupt */
6938         i40e_pf_disable_irq0(hw);
6939
6940         /* read out interrupt causes */
6941         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6942
6943         /* No interrupt event indicated */
6944         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6945                 goto done;
6946         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6947                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6948         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6949                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6950                 i40e_handle_mdd_event(dev);
6951         }
6952         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6953                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6954         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6955                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6956         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6957                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6958         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6959                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6960         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6961                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6962
6963         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6964                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6965                 i40e_dev_handle_vfr_event(dev);
6966         }
6967         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6968                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6969                 i40e_dev_handle_aq_msg(dev);
6970         }
6971
6972 done:
6973         /* Enable interrupt */
6974         i40e_pf_enable_irq0(hw);
6975         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6976                           i40e_dev_alarm_handler, dev);
6977 }
6978
6979 int
6980 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6981                          struct i40e_macvlan_filter *filter,
6982                          int total)
6983 {
6984         int ele_num, ele_buff_size;
6985         int num, actual_num, i;
6986         uint16_t flags;
6987         int ret = I40E_SUCCESS;
6988         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6989         struct i40e_aqc_add_macvlan_element_data *req_list;
6990
6991         if (filter == NULL  || total == 0)
6992                 return I40E_ERR_PARAM;
6993         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6994         ele_buff_size = hw->aq.asq_buf_size;
6995
6996         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6997         if (req_list == NULL) {
6998                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6999                 return I40E_ERR_NO_MEMORY;
7000         }
7001
7002         num = 0;
7003         do {
7004                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7005                 memset(req_list, 0, ele_buff_size);
7006
7007                 for (i = 0; i < actual_num; i++) {
7008                         rte_memcpy(req_list[i].mac_addr,
7009                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7010                         req_list[i].vlan_tag =
7011                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7012
7013                         switch (filter[num + i].filter_type) {
7014                         case I40E_MAC_PERFECT_MATCH:
7015                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7016                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7017                                 break;
7018                         case I40E_MACVLAN_PERFECT_MATCH:
7019                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7020                                 break;
7021                         case I40E_MAC_HASH_MATCH:
7022                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7023                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7024                                 break;
7025                         case I40E_MACVLAN_HASH_MATCH:
7026                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7027                                 break;
7028                         default:
7029                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7030                                 ret = I40E_ERR_PARAM;
7031                                 goto DONE;
7032                         }
7033
7034                         req_list[i].queue_number = 0;
7035
7036                         req_list[i].flags = rte_cpu_to_le_16(flags);
7037                 }
7038
7039                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7040                                                 actual_num, NULL);
7041                 if (ret != I40E_SUCCESS) {
7042                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7043                         goto DONE;
7044                 }
7045                 num += actual_num;
7046         } while (num < total);
7047
7048 DONE:
7049         rte_free(req_list);
7050         return ret;
7051 }
7052
7053 int
7054 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7055                             struct i40e_macvlan_filter *filter,
7056                             int total)
7057 {
7058         int ele_num, ele_buff_size;
7059         int num, actual_num, i;
7060         uint16_t flags;
7061         int ret = I40E_SUCCESS;
7062         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7063         struct i40e_aqc_remove_macvlan_element_data *req_list;
7064
7065         if (filter == NULL  || total == 0)
7066                 return I40E_ERR_PARAM;
7067
7068         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7069         ele_buff_size = hw->aq.asq_buf_size;
7070
7071         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7072         if (req_list == NULL) {
7073                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7074                 return I40E_ERR_NO_MEMORY;
7075         }
7076
7077         num = 0;
7078         do {
7079                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7080                 memset(req_list, 0, ele_buff_size);
7081
7082                 for (i = 0; i < actual_num; i++) {
7083                         rte_memcpy(req_list[i].mac_addr,
7084                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7085                         req_list[i].vlan_tag =
7086                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7087
7088                         switch (filter[num + i].filter_type) {
7089                         case I40E_MAC_PERFECT_MATCH:
7090                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7091                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7092                                 break;
7093                         case I40E_MACVLAN_PERFECT_MATCH:
7094                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7095                                 break;
7096                         case I40E_MAC_HASH_MATCH:
7097                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7098                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7099                                 break;
7100                         case I40E_MACVLAN_HASH_MATCH:
7101                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7102                                 break;
7103                         default:
7104                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7105                                 ret = I40E_ERR_PARAM;
7106                                 goto DONE;
7107                         }
7108                         req_list[i].flags = rte_cpu_to_le_16(flags);
7109                 }
7110
7111                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7112                                                 actual_num, NULL);
7113                 if (ret != I40E_SUCCESS) {
7114                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7115                         goto DONE;
7116                 }
7117                 num += actual_num;
7118         } while (num < total);
7119
7120 DONE:
7121         rte_free(req_list);
7122         return ret;
7123 }
7124
7125 /* Find out specific MAC filter */
7126 static struct i40e_mac_filter *
7127 i40e_find_mac_filter(struct i40e_vsi *vsi,
7128                          struct rte_ether_addr *macaddr)
7129 {
7130         struct i40e_mac_filter *f;
7131
7132         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7133                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7134                         return f;
7135         }
7136
7137         return NULL;
7138 }
7139
7140 static bool
7141 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7142                          uint16_t vlan_id)
7143 {
7144         uint32_t vid_idx, vid_bit;
7145
7146         if (vlan_id > ETH_VLAN_ID_MAX)
7147                 return 0;
7148
7149         vid_idx = I40E_VFTA_IDX(vlan_id);
7150         vid_bit = I40E_VFTA_BIT(vlan_id);
7151
7152         if (vsi->vfta[vid_idx] & vid_bit)
7153                 return 1;
7154         else
7155                 return 0;
7156 }
7157
7158 static void
7159 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7160                        uint16_t vlan_id, bool on)
7161 {
7162         uint32_t vid_idx, vid_bit;
7163
7164         vid_idx = I40E_VFTA_IDX(vlan_id);
7165         vid_bit = I40E_VFTA_BIT(vlan_id);
7166
7167         if (on)
7168                 vsi->vfta[vid_idx] |= vid_bit;
7169         else
7170                 vsi->vfta[vid_idx] &= ~vid_bit;
7171 }
7172
7173 void
7174 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7175                      uint16_t vlan_id, bool on)
7176 {
7177         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7178         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7179         int ret;
7180
7181         if (vlan_id > ETH_VLAN_ID_MAX)
7182                 return;
7183
7184         i40e_store_vlan_filter(vsi, vlan_id, on);
7185
7186         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7187                 return;
7188
7189         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7190
7191         if (on) {
7192                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7193                                        &vlan_data, 1, NULL);
7194                 if (ret != I40E_SUCCESS)
7195                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7196         } else {
7197                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7198                                           &vlan_data, 1, NULL);
7199                 if (ret != I40E_SUCCESS)
7200                         PMD_DRV_LOG(ERR,
7201                                     "Failed to remove vlan filter");
7202         }
7203 }
7204
7205 /**
7206  * Find all vlan options for specific mac addr,
7207  * return with actual vlan found.
7208  */
7209 int
7210 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7211                            struct i40e_macvlan_filter *mv_f,
7212                            int num, struct rte_ether_addr *addr)
7213 {
7214         int i;
7215         uint32_t j, k;
7216
7217         /**
7218          * Not to use i40e_find_vlan_filter to decrease the loop time,
7219          * although the code looks complex.
7220           */
7221         if (num < vsi->vlan_num)
7222                 return I40E_ERR_PARAM;
7223
7224         i = 0;
7225         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7226                 if (vsi->vfta[j]) {
7227                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7228                                 if (vsi->vfta[j] & (1 << k)) {
7229                                         if (i > num - 1) {
7230                                                 PMD_DRV_LOG(ERR,
7231                                                         "vlan number doesn't match");
7232                                                 return I40E_ERR_PARAM;
7233                                         }
7234                                         rte_memcpy(&mv_f[i].macaddr,
7235                                                         addr, ETH_ADDR_LEN);
7236                                         mv_f[i].vlan_id =
7237                                                 j * I40E_UINT32_BIT_SIZE + k;
7238                                         i++;
7239                                 }
7240                         }
7241                 }
7242         }
7243         return I40E_SUCCESS;
7244 }
7245
7246 static inline int
7247 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7248                            struct i40e_macvlan_filter *mv_f,
7249                            int num,
7250                            uint16_t vlan)
7251 {
7252         int i = 0;
7253         struct i40e_mac_filter *f;
7254
7255         if (num < vsi->mac_num)
7256                 return I40E_ERR_PARAM;
7257
7258         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7259                 if (i > num - 1) {
7260                         PMD_DRV_LOG(ERR, "buffer number not match");
7261                         return I40E_ERR_PARAM;
7262                 }
7263                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7264                                 ETH_ADDR_LEN);
7265                 mv_f[i].vlan_id = vlan;
7266                 mv_f[i].filter_type = f->mac_info.filter_type;
7267                 i++;
7268         }
7269
7270         return I40E_SUCCESS;
7271 }
7272
7273 static int
7274 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7275 {
7276         int i, j, num;
7277         struct i40e_mac_filter *f;
7278         struct i40e_macvlan_filter *mv_f;
7279         int ret = I40E_SUCCESS;
7280
7281         if (vsi == NULL || vsi->mac_num == 0)
7282                 return I40E_ERR_PARAM;
7283
7284         /* Case that no vlan is set */
7285         if (vsi->vlan_num == 0)
7286                 num = vsi->mac_num;
7287         else
7288                 num = vsi->mac_num * vsi->vlan_num;
7289
7290         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7291         if (mv_f == NULL) {
7292                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7293                 return I40E_ERR_NO_MEMORY;
7294         }
7295
7296         i = 0;
7297         if (vsi->vlan_num == 0) {
7298                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7299                         rte_memcpy(&mv_f[i].macaddr,
7300                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7301                         mv_f[i].filter_type = f->mac_info.filter_type;
7302                         mv_f[i].vlan_id = 0;
7303                         i++;
7304                 }
7305         } else {
7306                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7307                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7308                                         vsi->vlan_num, &f->mac_info.mac_addr);
7309                         if (ret != I40E_SUCCESS)
7310                                 goto DONE;
7311                         for (j = i; j < i + vsi->vlan_num; j++)
7312                                 mv_f[j].filter_type = f->mac_info.filter_type;
7313                         i += vsi->vlan_num;
7314                 }
7315         }
7316
7317         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7318 DONE:
7319         rte_free(mv_f);
7320
7321         return ret;
7322 }
7323
7324 int
7325 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7326 {
7327         struct i40e_macvlan_filter *mv_f;
7328         int mac_num;
7329         int ret = I40E_SUCCESS;
7330
7331         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7332                 return I40E_ERR_PARAM;
7333
7334         /* If it's already set, just return */
7335         if (i40e_find_vlan_filter(vsi,vlan))
7336                 return I40E_SUCCESS;
7337
7338         mac_num = vsi->mac_num;
7339
7340         if (mac_num == 0) {
7341                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7342                 return I40E_ERR_PARAM;
7343         }
7344
7345         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7346
7347         if (mv_f == NULL) {
7348                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7349                 return I40E_ERR_NO_MEMORY;
7350         }
7351
7352         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7353
7354         if (ret != I40E_SUCCESS)
7355                 goto DONE;
7356
7357         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7358
7359         if (ret != I40E_SUCCESS)
7360                 goto DONE;
7361
7362         i40e_set_vlan_filter(vsi, vlan, 1);
7363
7364         vsi->vlan_num++;
7365         ret = I40E_SUCCESS;
7366 DONE:
7367         rte_free(mv_f);
7368         return ret;
7369 }
7370
7371 int
7372 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7373 {
7374         struct i40e_macvlan_filter *mv_f;
7375         int mac_num;
7376         int ret = I40E_SUCCESS;
7377
7378         /**
7379          * Vlan 0 is the generic filter for untagged packets
7380          * and can't be removed.
7381          */
7382         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7383                 return I40E_ERR_PARAM;
7384
7385         /* If can't find it, just return */
7386         if (!i40e_find_vlan_filter(vsi, vlan))
7387                 return I40E_ERR_PARAM;
7388
7389         mac_num = vsi->mac_num;
7390
7391         if (mac_num == 0) {
7392                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7393                 return I40E_ERR_PARAM;
7394         }
7395
7396         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7397
7398         if (mv_f == NULL) {
7399                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7400                 return I40E_ERR_NO_MEMORY;
7401         }
7402
7403         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7404
7405         if (ret != I40E_SUCCESS)
7406                 goto DONE;
7407
7408         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7409
7410         if (ret != I40E_SUCCESS)
7411                 goto DONE;
7412
7413         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7414         if (vsi->vlan_num == 1) {
7415                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7416                 if (ret != I40E_SUCCESS)
7417                         goto DONE;
7418
7419                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7420                 if (ret != I40E_SUCCESS)
7421                         goto DONE;
7422         }
7423
7424         i40e_set_vlan_filter(vsi, vlan, 0);
7425
7426         vsi->vlan_num--;
7427         ret = I40E_SUCCESS;
7428 DONE:
7429         rte_free(mv_f);
7430         return ret;
7431 }
7432
7433 int
7434 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7435 {
7436         struct i40e_mac_filter *f;
7437         struct i40e_macvlan_filter *mv_f;
7438         int i, vlan_num = 0;
7439         int ret = I40E_SUCCESS;
7440
7441         /* If it's add and we've config it, return */
7442         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7443         if (f != NULL)
7444                 return I40E_SUCCESS;
7445         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7446                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7447
7448                 /**
7449                  * If vlan_num is 0, that's the first time to add mac,
7450                  * set mask for vlan_id 0.
7451                  */
7452                 if (vsi->vlan_num == 0) {
7453                         i40e_set_vlan_filter(vsi, 0, 1);
7454                         vsi->vlan_num = 1;
7455                 }
7456                 vlan_num = vsi->vlan_num;
7457         } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7458                         mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7459                 vlan_num = 1;
7460
7461         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7462         if (mv_f == NULL) {
7463                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7464                 return I40E_ERR_NO_MEMORY;
7465         }
7466
7467         for (i = 0; i < vlan_num; i++) {
7468                 mv_f[i].filter_type = mac_filter->filter_type;
7469                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7470                                 ETH_ADDR_LEN);
7471         }
7472
7473         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7474                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7475                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7476                                         &mac_filter->mac_addr);
7477                 if (ret != I40E_SUCCESS)
7478                         goto DONE;
7479         }
7480
7481         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7482         if (ret != I40E_SUCCESS)
7483                 goto DONE;
7484
7485         /* Add the mac addr into mac list */
7486         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7487         if (f == NULL) {
7488                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7489                 ret = I40E_ERR_NO_MEMORY;
7490                 goto DONE;
7491         }
7492         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7493                         ETH_ADDR_LEN);
7494         f->mac_info.filter_type = mac_filter->filter_type;
7495         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7496         vsi->mac_num++;
7497
7498         ret = I40E_SUCCESS;
7499 DONE:
7500         rte_free(mv_f);
7501
7502         return ret;
7503 }
7504
7505 int
7506 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7507 {
7508         struct i40e_mac_filter *f;
7509         struct i40e_macvlan_filter *mv_f;
7510         int i, vlan_num;
7511         enum i40e_mac_filter_type filter_type;
7512         int ret = I40E_SUCCESS;
7513
7514         /* Can't find it, return an error */
7515         f = i40e_find_mac_filter(vsi, addr);
7516         if (f == NULL)
7517                 return I40E_ERR_PARAM;
7518
7519         vlan_num = vsi->vlan_num;
7520         filter_type = f->mac_info.filter_type;
7521         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7522                 filter_type == I40E_MACVLAN_HASH_MATCH) {
7523                 if (vlan_num == 0) {
7524                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7525                         return I40E_ERR_PARAM;
7526                 }
7527         } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7528                         filter_type == I40E_MAC_HASH_MATCH)
7529                 vlan_num = 1;
7530
7531         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7532         if (mv_f == NULL) {
7533                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7534                 return I40E_ERR_NO_MEMORY;
7535         }
7536
7537         for (i = 0; i < vlan_num; i++) {
7538                 mv_f[i].filter_type = filter_type;
7539                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7540                                 ETH_ADDR_LEN);
7541         }
7542         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7543                         filter_type == I40E_MACVLAN_HASH_MATCH) {
7544                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7545                 if (ret != I40E_SUCCESS)
7546                         goto DONE;
7547         }
7548
7549         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7550         if (ret != I40E_SUCCESS)
7551                 goto DONE;
7552
7553         /* Remove the mac addr into mac list */
7554         TAILQ_REMOVE(&vsi->mac_list, f, next);
7555         rte_free(f);
7556         vsi->mac_num--;
7557
7558         ret = I40E_SUCCESS;
7559 DONE:
7560         rte_free(mv_f);
7561         return ret;
7562 }
7563
7564 /* Configure hash enable flags for RSS */
7565 uint64_t
7566 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7567 {
7568         uint64_t hena = 0;
7569         int i;
7570
7571         if (!flags)
7572                 return hena;
7573
7574         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7575                 if (flags & (1ULL << i))
7576                         hena |= adapter->pctypes_tbl[i];
7577         }
7578
7579         return hena;
7580 }
7581
7582 /* Parse the hash enable flags */
7583 uint64_t
7584 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7585 {
7586         uint64_t rss_hf = 0;
7587
7588         if (!flags)
7589                 return rss_hf;
7590         int i;
7591
7592         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7593                 if (flags & adapter->pctypes_tbl[i])
7594                         rss_hf |= (1ULL << i);
7595         }
7596         return rss_hf;
7597 }
7598
7599 /* Disable RSS */
7600 static void
7601 i40e_pf_disable_rss(struct i40e_pf *pf)
7602 {
7603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7604
7605         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7606         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7607         I40E_WRITE_FLUSH(hw);
7608 }
7609
7610 int
7611 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7612 {
7613         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7614         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7615         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7616                            I40E_VFQF_HKEY_MAX_INDEX :
7617                            I40E_PFQF_HKEY_MAX_INDEX;
7618
7619         if (!key || key_len == 0) {
7620                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7621                 return 0;
7622         } else if (key_len != (key_idx + 1) *
7623                 sizeof(uint32_t)) {
7624                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7625                 return -EINVAL;
7626         }
7627
7628         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7629                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7630                                 (struct i40e_aqc_get_set_rss_key_data *)key;
7631                 enum i40e_status_code status =
7632                                 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7633
7634                 if (status) {
7635                         PMD_DRV_LOG(ERR,
7636                                     "Failed to configure RSS key via AQ, error status: %d",
7637                                     status);
7638                         return -EIO;
7639                 }
7640         } else {
7641                 uint32_t *hash_key = (uint32_t *)key;
7642                 uint16_t i;
7643
7644                 if (vsi->type == I40E_VSI_SRIOV) {
7645                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7646                                 I40E_WRITE_REG(
7647                                         hw,
7648                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7649                                         hash_key[i]);
7650
7651                 } else {
7652                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7653                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7654                                                hash_key[i]);
7655                 }
7656                 I40E_WRITE_FLUSH(hw);
7657         }
7658
7659         return 0;
7660 }
7661
7662 static int
7663 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7664 {
7665         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7666         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7667         uint32_t reg;
7668         int ret;
7669
7670         if (!key || !key_len)
7671                 return 0;
7672
7673         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7674                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7675                         (struct i40e_aqc_get_set_rss_key_data *)key);
7676                 if (ret) {
7677                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7678                         return ret;
7679                 }
7680         } else {
7681                 uint32_t *key_dw = (uint32_t *)key;
7682                 uint16_t i;
7683
7684                 if (vsi->type == I40E_VSI_SRIOV) {
7685                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7686                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7687                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7688                         }
7689                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7690                                    sizeof(uint32_t);
7691                 } else {
7692                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7693                                 reg = I40E_PFQF_HKEY(i);
7694                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7695                         }
7696                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7697                                    sizeof(uint32_t);
7698                 }
7699         }
7700         return 0;
7701 }
7702
7703 static int
7704 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7705 {
7706         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7707         uint64_t hena;
7708         int ret;
7709
7710         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7711                                rss_conf->rss_key_len);
7712         if (ret)
7713                 return ret;
7714
7715         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7716         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7717         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7718         I40E_WRITE_FLUSH(hw);
7719
7720         return 0;
7721 }
7722
7723 static int
7724 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7725                          struct rte_eth_rss_conf *rss_conf)
7726 {
7727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7728         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7729         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7730         uint64_t hena;
7731
7732         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7733         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7734
7735         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7736                 if (rss_hf != 0) /* Enable RSS */
7737                         return -EINVAL;
7738                 return 0; /* Nothing to do */
7739         }
7740         /* RSS enabled */
7741         if (rss_hf == 0) /* Disable RSS */
7742                 return -EINVAL;
7743
7744         return i40e_hw_rss_hash_set(pf, rss_conf);
7745 }
7746
7747 static int
7748 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7749                            struct rte_eth_rss_conf *rss_conf)
7750 {
7751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7753         uint64_t hena;
7754         int ret;
7755
7756         if (!rss_conf)
7757                 return -EINVAL;
7758
7759         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7760                          &rss_conf->rss_key_len);
7761         if (ret)
7762                 return ret;
7763
7764         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7765         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7766         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7767
7768         return 0;
7769 }
7770
7771 static int
7772 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7773 {
7774         switch (filter_type) {
7775         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7776                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7777                 break;
7778         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7779                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7780                 break;
7781         case RTE_TUNNEL_FILTER_IMAC_TENID:
7782                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7783                 break;
7784         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7785                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7786                 break;
7787         case ETH_TUNNEL_FILTER_IMAC:
7788                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7789                 break;
7790         case ETH_TUNNEL_FILTER_OIP:
7791                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7792                 break;
7793         case ETH_TUNNEL_FILTER_IIP:
7794                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7795                 break;
7796         default:
7797                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7798                 return -EINVAL;
7799         }
7800
7801         return 0;
7802 }
7803
7804 /* Convert tunnel filter structure */
7805 static int
7806 i40e_tunnel_filter_convert(
7807         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7808         struct i40e_tunnel_filter *tunnel_filter)
7809 {
7810         rte_ether_addr_copy((struct rte_ether_addr *)
7811                         &cld_filter->element.outer_mac,
7812                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7813         rte_ether_addr_copy((struct rte_ether_addr *)
7814                         &cld_filter->element.inner_mac,
7815                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7816         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7817         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7818              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7819             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7820                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7821         else
7822                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7823         tunnel_filter->input.flags = cld_filter->element.flags;
7824         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7825         tunnel_filter->queue = cld_filter->element.queue_number;
7826         rte_memcpy(tunnel_filter->input.general_fields,
7827                    cld_filter->general_fields,
7828                    sizeof(cld_filter->general_fields));
7829
7830         return 0;
7831 }
7832
7833 /* Check if there exists the tunnel filter */
7834 struct i40e_tunnel_filter *
7835 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7836                              const struct i40e_tunnel_filter_input *input)
7837 {
7838         int ret;
7839
7840         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7841         if (ret < 0)
7842                 return NULL;
7843
7844         return tunnel_rule->hash_map[ret];
7845 }
7846
7847 /* Add a tunnel filter into the SW list */
7848 static int
7849 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7850                              struct i40e_tunnel_filter *tunnel_filter)
7851 {
7852         struct i40e_tunnel_rule *rule = &pf->tunnel;
7853         int ret;
7854
7855         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7856         if (ret < 0) {
7857                 PMD_DRV_LOG(ERR,
7858                             "Failed to insert tunnel filter to hash table %d!",
7859                             ret);
7860                 return ret;
7861         }
7862         rule->hash_map[ret] = tunnel_filter;
7863
7864         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7865
7866         return 0;
7867 }
7868
7869 /* Delete a tunnel filter from the SW list */
7870 int
7871 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7872                           struct i40e_tunnel_filter_input *input)
7873 {
7874         struct i40e_tunnel_rule *rule = &pf->tunnel;
7875         struct i40e_tunnel_filter *tunnel_filter;
7876         int ret;
7877
7878         ret = rte_hash_del_key(rule->hash_table, input);
7879         if (ret < 0) {
7880                 PMD_DRV_LOG(ERR,
7881                             "Failed to delete tunnel filter to hash table %d!",
7882                             ret);
7883                 return ret;
7884         }
7885         tunnel_filter = rule->hash_map[ret];
7886         rule->hash_map[ret] = NULL;
7887
7888         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7889         rte_free(tunnel_filter);
7890
7891         return 0;
7892 }
7893
7894 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7895 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7896 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7897 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7898 #define I40E_TR_GRE_KEY_MASK                    0x400
7899 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7900 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7901 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7902 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7903 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7904 #define I40E_DIRECTION_INGRESS_KEY              0x8000
7905 #define I40E_TR_L4_TYPE_TCP                     0x2
7906 #define I40E_TR_L4_TYPE_UDP                     0x4
7907 #define I40E_TR_L4_TYPE_SCTP                    0x8
7908
7909 static enum
7910 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7911 {
7912         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7913         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7914         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7915         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7916         enum i40e_status_code status = I40E_SUCCESS;
7917
7918         if (pf->support_multi_driver) {
7919                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7920                 return I40E_NOT_SUPPORTED;
7921         }
7922
7923         memset(&filter_replace, 0,
7924                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7925         memset(&filter_replace_buf, 0,
7926                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7927
7928         /* create L1 filter */
7929         filter_replace.old_filter_type =
7930                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7931         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7932         filter_replace.tr_bit = 0;
7933
7934         /* Prepare the buffer, 3 entries */
7935         filter_replace_buf.data[0] =
7936                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7937         filter_replace_buf.data[0] |=
7938                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7939         filter_replace_buf.data[2] = 0xFF;
7940         filter_replace_buf.data[3] = 0xFF;
7941         filter_replace_buf.data[4] =
7942                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7943         filter_replace_buf.data[4] |=
7944                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7945         filter_replace_buf.data[7] = 0xF0;
7946         filter_replace_buf.data[8]
7947                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7948         filter_replace_buf.data[8] |=
7949                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7950         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7951                 I40E_TR_GENEVE_KEY_MASK |
7952                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7953         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7954                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7955                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7956
7957         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7958                                                &filter_replace_buf);
7959         if (!status && (filter_replace.old_filter_type !=
7960                         filter_replace.new_filter_type))
7961                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7962                             " original: 0x%x, new: 0x%x",
7963                             dev->device->name,
7964                             filter_replace.old_filter_type,
7965                             filter_replace.new_filter_type);
7966
7967         return status;
7968 }
7969
7970 static enum
7971 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7972 {
7973         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7974         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7975         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7976         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7977         enum i40e_status_code status = I40E_SUCCESS;
7978
7979         if (pf->support_multi_driver) {
7980                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7981                 return I40E_NOT_SUPPORTED;
7982         }
7983
7984         /* For MPLSoUDP */
7985         memset(&filter_replace, 0,
7986                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7987         memset(&filter_replace_buf, 0,
7988                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7989         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7990                 I40E_AQC_MIRROR_CLOUD_FILTER;
7991         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7992         filter_replace.new_filter_type =
7993                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7994         /* Prepare the buffer, 2 entries */
7995         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7996         filter_replace_buf.data[0] |=
7997                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7998         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7999         filter_replace_buf.data[4] |=
8000                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8001         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8002                                                &filter_replace_buf);
8003         if (status < 0)
8004                 return status;
8005         if (filter_replace.old_filter_type !=
8006             filter_replace.new_filter_type)
8007                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8008                             " original: 0x%x, new: 0x%x",
8009                             dev->device->name,
8010                             filter_replace.old_filter_type,
8011                             filter_replace.new_filter_type);
8012
8013         /* For MPLSoGRE */
8014         memset(&filter_replace, 0,
8015                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8016         memset(&filter_replace_buf, 0,
8017                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8018
8019         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8020                 I40E_AQC_MIRROR_CLOUD_FILTER;
8021         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8022         filter_replace.new_filter_type =
8023                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8024         /* Prepare the buffer, 2 entries */
8025         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8026         filter_replace_buf.data[0] |=
8027                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8028         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8029         filter_replace_buf.data[4] |=
8030                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8031
8032         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8033                                                &filter_replace_buf);
8034         if (!status && (filter_replace.old_filter_type !=
8035                         filter_replace.new_filter_type))
8036                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8037                             " original: 0x%x, new: 0x%x",
8038                             dev->device->name,
8039                             filter_replace.old_filter_type,
8040                             filter_replace.new_filter_type);
8041
8042         return status;
8043 }
8044
8045 static enum i40e_status_code
8046 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8047 {
8048         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8049         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8050         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8051         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8052         enum i40e_status_code status = I40E_SUCCESS;
8053
8054         if (pf->support_multi_driver) {
8055                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8056                 return I40E_NOT_SUPPORTED;
8057         }
8058
8059         /* For GTP-C */
8060         memset(&filter_replace, 0,
8061                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8062         memset(&filter_replace_buf, 0,
8063                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8064         /* create L1 filter */
8065         filter_replace.old_filter_type =
8066                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8067         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8068         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8069                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8070         /* Prepare the buffer, 2 entries */
8071         filter_replace_buf.data[0] =
8072                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8073         filter_replace_buf.data[0] |=
8074                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8075         filter_replace_buf.data[2] = 0xFF;
8076         filter_replace_buf.data[3] = 0xFF;
8077         filter_replace_buf.data[4] =
8078                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8079         filter_replace_buf.data[4] |=
8080                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8081         filter_replace_buf.data[6] = 0xFF;
8082         filter_replace_buf.data[7] = 0xFF;
8083         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8084                                                &filter_replace_buf);
8085         if (status < 0)
8086                 return status;
8087         if (filter_replace.old_filter_type !=
8088             filter_replace.new_filter_type)
8089                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8090                             " original: 0x%x, new: 0x%x",
8091                             dev->device->name,
8092                             filter_replace.old_filter_type,
8093                             filter_replace.new_filter_type);
8094
8095         /* for GTP-U */
8096         memset(&filter_replace, 0,
8097                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8098         memset(&filter_replace_buf, 0,
8099                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8100         /* create L1 filter */
8101         filter_replace.old_filter_type =
8102                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8103         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8104         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8106         /* Prepare the buffer, 2 entries */
8107         filter_replace_buf.data[0] =
8108                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8109         filter_replace_buf.data[0] |=
8110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8111         filter_replace_buf.data[2] = 0xFF;
8112         filter_replace_buf.data[3] = 0xFF;
8113         filter_replace_buf.data[4] =
8114                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8115         filter_replace_buf.data[4] |=
8116                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8117         filter_replace_buf.data[6] = 0xFF;
8118         filter_replace_buf.data[7] = 0xFF;
8119
8120         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8121                                                &filter_replace_buf);
8122         if (!status && (filter_replace.old_filter_type !=
8123                         filter_replace.new_filter_type))
8124                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8125                             " original: 0x%x, new: 0x%x",
8126                             dev->device->name,
8127                             filter_replace.old_filter_type,
8128                             filter_replace.new_filter_type);
8129
8130         return status;
8131 }
8132
8133 static enum
8134 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8135 {
8136         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8137         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8138         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8139         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8140         enum i40e_status_code status = I40E_SUCCESS;
8141
8142         if (pf->support_multi_driver) {
8143                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8144                 return I40E_NOT_SUPPORTED;
8145         }
8146
8147         /* for GTP-C */
8148         memset(&filter_replace, 0,
8149                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8150         memset(&filter_replace_buf, 0,
8151                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8152         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8153         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8154         filter_replace.new_filter_type =
8155                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8156         /* Prepare the buffer, 2 entries */
8157         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8158         filter_replace_buf.data[0] |=
8159                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8160         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8161         filter_replace_buf.data[4] |=
8162                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8163         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8164                                                &filter_replace_buf);
8165         if (status < 0)
8166                 return status;
8167         if (filter_replace.old_filter_type !=
8168             filter_replace.new_filter_type)
8169                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8170                             " original: 0x%x, new: 0x%x",
8171                             dev->device->name,
8172                             filter_replace.old_filter_type,
8173                             filter_replace.new_filter_type);
8174
8175         /* for GTP-U */
8176         memset(&filter_replace, 0,
8177                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8178         memset(&filter_replace_buf, 0,
8179                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8180         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8181         filter_replace.old_filter_type =
8182                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8183         filter_replace.new_filter_type =
8184                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8185         /* Prepare the buffer, 2 entries */
8186         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8187         filter_replace_buf.data[0] |=
8188                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8189         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8190         filter_replace_buf.data[4] |=
8191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8192
8193         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8194                                                &filter_replace_buf);
8195         if (!status && (filter_replace.old_filter_type !=
8196                         filter_replace.new_filter_type))
8197                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8198                             " original: 0x%x, new: 0x%x",
8199                             dev->device->name,
8200                             filter_replace.old_filter_type,
8201                             filter_replace.new_filter_type);
8202
8203         return status;
8204 }
8205
8206 static enum i40e_status_code
8207 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8208                             enum i40e_l4_port_type l4_port_type)
8209 {
8210         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8211         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8212         enum i40e_status_code status = I40E_SUCCESS;
8213         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8214         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8215
8216         if (pf->support_multi_driver) {
8217                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8218                 return I40E_NOT_SUPPORTED;
8219         }
8220
8221         memset(&filter_replace, 0,
8222                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8223         memset(&filter_replace_buf, 0,
8224                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8225
8226         /* create L1 filter */
8227         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8228                 filter_replace.old_filter_type =
8229                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8230                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8231                 filter_replace_buf.data[8] =
8232                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8233         } else {
8234                 filter_replace.old_filter_type =
8235                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8236                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8237                 filter_replace_buf.data[8] =
8238                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8239         }
8240
8241         filter_replace.tr_bit = 0;
8242         /* Prepare the buffer, 3 entries */
8243         filter_replace_buf.data[0] =
8244                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8245         filter_replace_buf.data[0] |=
8246                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8247         filter_replace_buf.data[2] = 0x00;
8248         filter_replace_buf.data[3] =
8249                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8250         filter_replace_buf.data[4] =
8251                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8252         filter_replace_buf.data[4] |=
8253                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8254         filter_replace_buf.data[5] = 0x00;
8255         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8256                 I40E_TR_L4_TYPE_TCP |
8257                 I40E_TR_L4_TYPE_SCTP;
8258         filter_replace_buf.data[7] = 0x00;
8259         filter_replace_buf.data[8] |=
8260                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8261         filter_replace_buf.data[9] = 0x00;
8262         filter_replace_buf.data[10] = 0xFF;
8263         filter_replace_buf.data[11] = 0xFF;
8264
8265         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8266                                                &filter_replace_buf);
8267         if (!status && filter_replace.old_filter_type !=
8268             filter_replace.new_filter_type)
8269                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8270                             " original: 0x%x, new: 0x%x",
8271                             dev->device->name,
8272                             filter_replace.old_filter_type,
8273                             filter_replace.new_filter_type);
8274
8275         return status;
8276 }
8277
8278 static enum i40e_status_code
8279 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8280                                enum i40e_l4_port_type l4_port_type)
8281 {
8282         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8283         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8284         enum i40e_status_code status = I40E_SUCCESS;
8285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8286         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8287
8288         if (pf->support_multi_driver) {
8289                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8290                 return I40E_NOT_SUPPORTED;
8291         }
8292
8293         memset(&filter_replace, 0,
8294                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8295         memset(&filter_replace_buf, 0,
8296                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8297
8298         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8299                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8300                 filter_replace.new_filter_type =
8301                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8302                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8303         } else {
8304                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8305                 filter_replace.new_filter_type =
8306                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8307                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8308         }
8309
8310         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8311         filter_replace.tr_bit = 0;
8312         /* Prepare the buffer, 2 entries */
8313         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8314         filter_replace_buf.data[0] |=
8315                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8316         filter_replace_buf.data[4] |=
8317                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8318         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8319                                                &filter_replace_buf);
8320
8321         if (!status && filter_replace.old_filter_type !=
8322             filter_replace.new_filter_type)
8323                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8324                             " original: 0x%x, new: 0x%x",
8325                             dev->device->name,
8326                             filter_replace.old_filter_type,
8327                             filter_replace.new_filter_type);
8328
8329         return status;
8330 }
8331
8332 int
8333 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8334                       struct i40e_tunnel_filter_conf *tunnel_filter,
8335                       uint8_t add)
8336 {
8337         uint16_t ip_type;
8338         uint32_t ipv4_addr, ipv4_addr_le;
8339         uint8_t i, tun_type = 0;
8340         /* internal variable to convert ipv6 byte order */
8341         uint32_t convert_ipv6[4];
8342         int val, ret = 0;
8343         struct i40e_pf_vf *vf = NULL;
8344         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8345         struct i40e_vsi *vsi;
8346         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8347         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8348         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8349         struct i40e_tunnel_filter *tunnel, *node;
8350         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8351         uint32_t teid_le;
8352         bool big_buffer = 0;
8353
8354         cld_filter = rte_zmalloc("tunnel_filter",
8355                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8356                          0);
8357
8358         if (cld_filter == NULL) {
8359                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8360                 return -ENOMEM;
8361         }
8362         pfilter = cld_filter;
8363
8364         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8365                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8366         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8367                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8368
8369         pfilter->element.inner_vlan =
8370                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8371         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8372                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8373                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8374                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8375                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8376                                 &ipv4_addr_le,
8377                                 sizeof(pfilter->element.ipaddr.v4.data));
8378         } else {
8379                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8380                 for (i = 0; i < 4; i++) {
8381                         convert_ipv6[i] =
8382                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8383                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8384                 }
8385                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8386                            &convert_ipv6,
8387                            sizeof(pfilter->element.ipaddr.v6.data));
8388         }
8389
8390         /* check tunneled type */
8391         switch (tunnel_filter->tunnel_type) {
8392         case I40E_TUNNEL_TYPE_VXLAN:
8393                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8394                 break;
8395         case I40E_TUNNEL_TYPE_NVGRE:
8396                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8397                 break;
8398         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8399                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8400                 break;
8401         case I40E_TUNNEL_TYPE_MPLSoUDP:
8402                 if (!pf->mpls_replace_flag) {
8403                         i40e_replace_mpls_l1_filter(pf);
8404                         i40e_replace_mpls_cloud_filter(pf);
8405                         pf->mpls_replace_flag = 1;
8406                 }
8407                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8408                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8409                         teid_le >> 4;
8410                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8411                         (teid_le & 0xF) << 12;
8412                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8413                         0x40;
8414                 big_buffer = 1;
8415                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8416                 break;
8417         case I40E_TUNNEL_TYPE_MPLSoGRE:
8418                 if (!pf->mpls_replace_flag) {
8419                         i40e_replace_mpls_l1_filter(pf);
8420                         i40e_replace_mpls_cloud_filter(pf);
8421                         pf->mpls_replace_flag = 1;
8422                 }
8423                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8424                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8425                         teid_le >> 4;
8426                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8427                         (teid_le & 0xF) << 12;
8428                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8429                         0x0;
8430                 big_buffer = 1;
8431                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8432                 break;
8433         case I40E_TUNNEL_TYPE_GTPC:
8434                 if (!pf->gtp_replace_flag) {
8435                         i40e_replace_gtp_l1_filter(pf);
8436                         i40e_replace_gtp_cloud_filter(pf);
8437                         pf->gtp_replace_flag = 1;
8438                 }
8439                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8440                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8441                         (teid_le >> 16) & 0xFFFF;
8442                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8443                         teid_le & 0xFFFF;
8444                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8445                         0x0;
8446                 big_buffer = 1;
8447                 break;
8448         case I40E_TUNNEL_TYPE_GTPU:
8449                 if (!pf->gtp_replace_flag) {
8450                         i40e_replace_gtp_l1_filter(pf);
8451                         i40e_replace_gtp_cloud_filter(pf);
8452                         pf->gtp_replace_flag = 1;
8453                 }
8454                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8455                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8456                         (teid_le >> 16) & 0xFFFF;
8457                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8458                         teid_le & 0xFFFF;
8459                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8460                         0x0;
8461                 big_buffer = 1;
8462                 break;
8463         case I40E_TUNNEL_TYPE_QINQ:
8464                 if (!pf->qinq_replace_flag) {
8465                         ret = i40e_cloud_filter_qinq_create(pf);
8466                         if (ret < 0)
8467                                 PMD_DRV_LOG(DEBUG,
8468                                             "QinQ tunnel filter already created.");
8469                         pf->qinq_replace_flag = 1;
8470                 }
8471                 /*      Add in the General fields the values of
8472                  *      the Outer and Inner VLAN
8473                  *      Big Buffer should be set, see changes in
8474                  *      i40e_aq_add_cloud_filters
8475                  */
8476                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8477                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8478                 big_buffer = 1;
8479                 break;
8480         case I40E_CLOUD_TYPE_UDP:
8481         case I40E_CLOUD_TYPE_TCP:
8482         case I40E_CLOUD_TYPE_SCTP:
8483                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8484                         if (!pf->sport_replace_flag) {
8485                                 i40e_replace_port_l1_filter(pf,
8486                                                 tunnel_filter->l4_port_type);
8487                                 i40e_replace_port_cloud_filter(pf,
8488                                                 tunnel_filter->l4_port_type);
8489                                 pf->sport_replace_flag = 1;
8490                         }
8491                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8492                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8493                                 I40E_DIRECTION_INGRESS_KEY;
8494
8495                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8496                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8497                                         I40E_TR_L4_TYPE_UDP;
8498                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8499                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8500                                         I40E_TR_L4_TYPE_TCP;
8501                         else
8502                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8503                                         I40E_TR_L4_TYPE_SCTP;
8504
8505                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8506                                 (teid_le >> 16) & 0xFFFF;
8507                         big_buffer = 1;
8508                 } else {
8509                         if (!pf->dport_replace_flag) {
8510                                 i40e_replace_port_l1_filter(pf,
8511                                                 tunnel_filter->l4_port_type);
8512                                 i40e_replace_port_cloud_filter(pf,
8513                                                 tunnel_filter->l4_port_type);
8514                                 pf->dport_replace_flag = 1;
8515                         }
8516                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8517                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8518                                 I40E_DIRECTION_INGRESS_KEY;
8519
8520                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8521                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8522                                         I40E_TR_L4_TYPE_UDP;
8523                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8524                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8525                                         I40E_TR_L4_TYPE_TCP;
8526                         else
8527                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8528                                         I40E_TR_L4_TYPE_SCTP;
8529
8530                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8531                                 (teid_le >> 16) & 0xFFFF;
8532                         big_buffer = 1;
8533                 }
8534
8535                 break;
8536         default:
8537                 /* Other tunnel types is not supported. */
8538                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8539                 rte_free(cld_filter);
8540                 return -EINVAL;
8541         }
8542
8543         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8544                 pfilter->element.flags =
8545                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8546         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8547                 pfilter->element.flags =
8548                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8549         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8550                 pfilter->element.flags =
8551                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8552         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8553                 pfilter->element.flags =
8554                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8555         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8556                 pfilter->element.flags |=
8557                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8558         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8559                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8560                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8561                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8562                         pfilter->element.flags |=
8563                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8564                 else
8565                         pfilter->element.flags |=
8566                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8567         } else {
8568                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8569                                                 &pfilter->element.flags);
8570                 if (val < 0) {
8571                         rte_free(cld_filter);
8572                         return -EINVAL;
8573                 }
8574         }
8575
8576         pfilter->element.flags |= rte_cpu_to_le_16(
8577                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8578                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8579         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8580         pfilter->element.queue_number =
8581                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8582
8583         if (!tunnel_filter->is_to_vf)
8584                 vsi = pf->main_vsi;
8585         else {
8586                 if (tunnel_filter->vf_id >= pf->vf_num) {
8587                         PMD_DRV_LOG(ERR, "Invalid argument.");
8588                         rte_free(cld_filter);
8589                         return -EINVAL;
8590                 }
8591                 vf = &pf->vfs[tunnel_filter->vf_id];
8592                 vsi = vf->vsi;
8593         }
8594
8595         /* Check if there is the filter in SW list */
8596         memset(&check_filter, 0, sizeof(check_filter));
8597         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8598         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8599         check_filter.vf_id = tunnel_filter->vf_id;
8600         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8601         if (add && node) {
8602                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8603                 rte_free(cld_filter);
8604                 return -EINVAL;
8605         }
8606
8607         if (!add && !node) {
8608                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8609                 rte_free(cld_filter);
8610                 return -EINVAL;
8611         }
8612
8613         if (add) {
8614                 if (big_buffer)
8615                         ret = i40e_aq_add_cloud_filters_bb(hw,
8616                                                    vsi->seid, cld_filter, 1);
8617                 else
8618                         ret = i40e_aq_add_cloud_filters(hw,
8619                                         vsi->seid, &cld_filter->element, 1);
8620                 if (ret < 0) {
8621                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8622                         rte_free(cld_filter);
8623                         return -ENOTSUP;
8624                 }
8625                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8626                 if (tunnel == NULL) {
8627                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8628                         rte_free(cld_filter);
8629                         return -ENOMEM;
8630                 }
8631
8632                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8633                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8634                 if (ret < 0)
8635                         rte_free(tunnel);
8636         } else {
8637                 if (big_buffer)
8638                         ret = i40e_aq_rem_cloud_filters_bb(
8639                                 hw, vsi->seid, cld_filter, 1);
8640                 else
8641                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8642                                                 &cld_filter->element, 1);
8643                 if (ret < 0) {
8644                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8645                         rte_free(cld_filter);
8646                         return -ENOTSUP;
8647                 }
8648                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8649         }
8650
8651         rte_free(cld_filter);
8652         return ret;
8653 }
8654
8655 static int
8656 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8657 {
8658         uint8_t i;
8659
8660         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8661                 if (pf->vxlan_ports[i] == port)
8662                         return i;
8663         }
8664
8665         return -1;
8666 }
8667
8668 static int
8669 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8670 {
8671         int  idx, ret;
8672         uint8_t filter_idx = 0;
8673         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8674
8675         idx = i40e_get_vxlan_port_idx(pf, port);
8676
8677         /* Check if port already exists */
8678         if (idx >= 0) {
8679                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8680                 return -EINVAL;
8681         }
8682
8683         /* Now check if there is space to add the new port */
8684         idx = i40e_get_vxlan_port_idx(pf, 0);
8685         if (idx < 0) {
8686                 PMD_DRV_LOG(ERR,
8687                         "Maximum number of UDP ports reached, not adding port %d",
8688                         port);
8689                 return -ENOSPC;
8690         }
8691
8692         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8693                                         &filter_idx, NULL);
8694         if (ret < 0) {
8695                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8696                 return -1;
8697         }
8698
8699         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8700                          port,  filter_idx);
8701
8702         /* New port: add it and mark its index in the bitmap */
8703         pf->vxlan_ports[idx] = port;
8704         pf->vxlan_bitmap |= (1 << idx);
8705
8706         if (!(pf->flags & I40E_FLAG_VXLAN))
8707                 pf->flags |= I40E_FLAG_VXLAN;
8708
8709         return 0;
8710 }
8711
8712 static int
8713 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8714 {
8715         int idx;
8716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8717
8718         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8719                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8720                 return -EINVAL;
8721         }
8722
8723         idx = i40e_get_vxlan_port_idx(pf, port);
8724
8725         if (idx < 0) {
8726                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8727                 return -EINVAL;
8728         }
8729
8730         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8731                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8732                 return -1;
8733         }
8734
8735         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8736                         port, idx);
8737
8738         pf->vxlan_ports[idx] = 0;
8739         pf->vxlan_bitmap &= ~(1 << idx);
8740
8741         if (!pf->vxlan_bitmap)
8742                 pf->flags &= ~I40E_FLAG_VXLAN;
8743
8744         return 0;
8745 }
8746
8747 /* Add UDP tunneling port */
8748 static int
8749 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8750                              struct rte_eth_udp_tunnel *udp_tunnel)
8751 {
8752         int ret = 0;
8753         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8754
8755         if (udp_tunnel == NULL)
8756                 return -EINVAL;
8757
8758         switch (udp_tunnel->prot_type) {
8759         case RTE_TUNNEL_TYPE_VXLAN:
8760                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8761                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8762                 break;
8763         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8764                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8765                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8766                 break;
8767         case RTE_TUNNEL_TYPE_GENEVE:
8768         case RTE_TUNNEL_TYPE_TEREDO:
8769                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8770                 ret = -1;
8771                 break;
8772
8773         default:
8774                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8775                 ret = -1;
8776                 break;
8777         }
8778
8779         return ret;
8780 }
8781
8782 /* Remove UDP tunneling port */
8783 static int
8784 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8785                              struct rte_eth_udp_tunnel *udp_tunnel)
8786 {
8787         int ret = 0;
8788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8789
8790         if (udp_tunnel == NULL)
8791                 return -EINVAL;
8792
8793         switch (udp_tunnel->prot_type) {
8794         case RTE_TUNNEL_TYPE_VXLAN:
8795         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8796                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8797                 break;
8798         case RTE_TUNNEL_TYPE_GENEVE:
8799         case RTE_TUNNEL_TYPE_TEREDO:
8800                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8801                 ret = -1;
8802                 break;
8803         default:
8804                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8805                 ret = -1;
8806                 break;
8807         }
8808
8809         return ret;
8810 }
8811
8812 /* Calculate the maximum number of contiguous PF queues that are configured */
8813 static int
8814 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8815 {
8816         struct rte_eth_dev_data *data = pf->dev_data;
8817         int i, num;
8818         struct i40e_rx_queue *rxq;
8819
8820         num = 0;
8821         for (i = 0; i < pf->lan_nb_qps; i++) {
8822                 rxq = data->rx_queues[i];
8823                 if (rxq && rxq->q_set)
8824                         num++;
8825                 else
8826                         break;
8827         }
8828
8829         return num;
8830 }
8831
8832 /* Configure RSS */
8833 static int
8834 i40e_pf_config_rss(struct i40e_pf *pf)
8835 {
8836         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8837         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8838         struct rte_eth_rss_conf rss_conf;
8839         uint32_t i, lut = 0;
8840         uint16_t j, num;
8841
8842         /*
8843          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8844          * It's necessary to calculate the actual PF queues that are configured.
8845          */
8846         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8847                 num = i40e_pf_calc_configured_queues_num(pf);
8848         else
8849                 num = pf->dev_data->nb_rx_queues;
8850
8851         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8852         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8853                         num);
8854
8855         if (num == 0) {
8856                 PMD_INIT_LOG(ERR,
8857                         "No PF queues are configured to enable RSS for port %u",
8858                         pf->dev_data->port_id);
8859                 return -ENOTSUP;
8860         }
8861
8862         if (pf->adapter->rss_reta_updated == 0) {
8863                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8864                         if (j == num)
8865                                 j = 0;
8866                         lut = (lut << 8) | (j & ((0x1 <<
8867                                 hw->func_caps.rss_table_entry_width) - 1));
8868                         if ((i & 3) == 3)
8869                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8870                                                rte_bswap32(lut));
8871                 }
8872         }
8873
8874         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8875         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
8876             !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
8877                 i40e_pf_disable_rss(pf);
8878                 return 0;
8879         }
8880         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8881                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8882                 /* Random default keys */
8883                 static uint32_t rss_key_default[] = {0x6b793944,
8884                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8885                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8886                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8887
8888                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8889                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8890                                                         sizeof(uint32_t);
8891         }
8892
8893         return i40e_hw_rss_hash_set(pf, &rss_conf);
8894 }
8895
8896 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8897 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8898 int
8899 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8900 {
8901         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8902         uint32_t val, reg;
8903         int ret = -EINVAL;
8904
8905         if (pf->support_multi_driver) {
8906                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8907                 return -ENOTSUP;
8908         }
8909
8910         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8911         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8912
8913         if (len == 3) {
8914                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8915         } else if (len == 4) {
8916                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8917         } else {
8918                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8919                 return ret;
8920         }
8921
8922         if (reg != val) {
8923                 ret = i40e_aq_debug_write_global_register(hw,
8924                                                    I40E_GL_PRS_FVBM(2),
8925                                                    reg, NULL);
8926                 if (ret != 0)
8927                         return ret;
8928                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8929                             "with value 0x%08x",
8930                             I40E_GL_PRS_FVBM(2), reg);
8931         } else {
8932                 ret = 0;
8933         }
8934         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8935                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8936
8937         return ret;
8938 }
8939
8940 /* Set the symmetric hash enable configurations per port */
8941 static void
8942 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8943 {
8944         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8945
8946         if (enable > 0) {
8947                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8948                         PMD_DRV_LOG(INFO,
8949                                 "Symmetric hash has already been enabled");
8950                         return;
8951                 }
8952                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8953         } else {
8954                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8955                         PMD_DRV_LOG(INFO,
8956                                 "Symmetric hash has already been disabled");
8957                         return;
8958                 }
8959                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8960         }
8961         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8962         I40E_WRITE_FLUSH(hw);
8963 }
8964
8965 /**
8966  * Valid input sets for hash and flow director filters per PCTYPE
8967  */
8968 static uint64_t
8969 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8970                 enum rte_filter_type filter)
8971 {
8972         uint64_t valid;
8973
8974         static const uint64_t valid_hash_inset_table[] = {
8975                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8976                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8977                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8978                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8979                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8980                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8981                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8982                         I40E_INSET_FLEX_PAYLOAD,
8983                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8984                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8985                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8986                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8987                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8988                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8989                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8990                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8991                         I40E_INSET_FLEX_PAYLOAD,
8992                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8993                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8994                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8995                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8996                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8997                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8998                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8999                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9000                         I40E_INSET_FLEX_PAYLOAD,
9001                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9002                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9003                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9004                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9005                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9006                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9007                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9008                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9009                         I40E_INSET_FLEX_PAYLOAD,
9010                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9011                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9012                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9013                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9014                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9015                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9016                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9017                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9018                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9019                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9020                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9021                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9022                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9023                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9024                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9025                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9026                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9027                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9028                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9029                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9030                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9031                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9032                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9033                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9034                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9035                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9036                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9037                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9038                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9039                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9040                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9041                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9042                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9043                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9044                         I40E_INSET_FLEX_PAYLOAD,
9045                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9046                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9047                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9048                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9049                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9050                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9051                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9052                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9053                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9054                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9055                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9056                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9057                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9058                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9059                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9060                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9061                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9062                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9063                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9064                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9065                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9066                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9067                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9068                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9069                         I40E_INSET_FLEX_PAYLOAD,
9070                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9071                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9072                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9073                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9074                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9075                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9076                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9077                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9078                         I40E_INSET_FLEX_PAYLOAD,
9079                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9080                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9081                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9082                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9083                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9084                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9085                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9086                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9087                         I40E_INSET_FLEX_PAYLOAD,
9088                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9092                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9093                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9094                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9095                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9096                         I40E_INSET_FLEX_PAYLOAD,
9097                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9098                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9099                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9100                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9101                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9102                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9103                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9104                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9105                         I40E_INSET_FLEX_PAYLOAD,
9106                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9110                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9111                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9112                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9113                         I40E_INSET_FLEX_PAYLOAD,
9114                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9118                         I40E_INSET_FLEX_PAYLOAD,
9119         };
9120
9121         /**
9122          * Flow director supports only fields defined in
9123          * union rte_eth_fdir_flow.
9124          */
9125         static const uint64_t valid_fdir_inset_table[] = {
9126                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9127                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9128                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9129                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9130                 I40E_INSET_IPV4_TTL,
9131                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9132                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9133                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9134                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9135                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9136                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9137                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9138                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9139                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9140                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9141                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9142                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9143                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9145                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9146                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9147                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9148                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9149                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9151                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9152                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9153                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9154                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9156                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9157                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9158                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9159                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9160                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9161                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9162                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9163                 I40E_INSET_SCTP_VT,
9164                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9165                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9166                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9168                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9169                 I40E_INSET_IPV4_TTL,
9170                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9173                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9174                 I40E_INSET_IPV6_HOP_LIMIT,
9175                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9176                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9177                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9178                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9179                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9180                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9181                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9182                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9183                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9184                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9185                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9186                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9187                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9188                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9189                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9190                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9191                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9192                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9193                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9194                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9195                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9196                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9197                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9198                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9199                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9201                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9203                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9204                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9205                 I40E_INSET_SCTP_VT,
9206                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9207                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9210                 I40E_INSET_IPV6_HOP_LIMIT,
9211                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9212                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                 I40E_INSET_LAST_ETHER_TYPE,
9214         };
9215
9216         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9217                 return 0;
9218         if (filter == RTE_ETH_FILTER_HASH)
9219                 valid = valid_hash_inset_table[pctype];
9220         else
9221                 valid = valid_fdir_inset_table[pctype];
9222
9223         return valid;
9224 }
9225
9226 /**
9227  * Validate if the input set is allowed for a specific PCTYPE
9228  */
9229 int
9230 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9231                 enum rte_filter_type filter, uint64_t inset)
9232 {
9233         uint64_t valid;
9234
9235         valid = i40e_get_valid_input_set(pctype, filter);
9236         if (inset & (~valid))
9237                 return -EINVAL;
9238
9239         return 0;
9240 }
9241
9242 /* default input set fields combination per pctype */
9243 uint64_t
9244 i40e_get_default_input_set(uint16_t pctype)
9245 {
9246         static const uint64_t default_inset_table[] = {
9247                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9248                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9249                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9250                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9251                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9252                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9253                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9254                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9255                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9256                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9257                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9258                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9259                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9261                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9262                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9263                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9264                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9265                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9266                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9267                         I40E_INSET_SCTP_VT,
9268                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9269                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9270                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9271                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9272                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9273                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9274                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9275                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9276                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9277                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9278                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9279                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9280                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9281                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9282                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9283                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9284                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9285                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9286                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9287                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9288                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9289                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9290                         I40E_INSET_SCTP_VT,
9291                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9292                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9293                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9294                         I40E_INSET_LAST_ETHER_TYPE,
9295         };
9296
9297         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9298                 return 0;
9299
9300         return default_inset_table[pctype];
9301 }
9302
9303 /**
9304  * Parse the input set from index to logical bit masks
9305  */
9306 static int
9307 i40e_parse_input_set(uint64_t *inset,
9308                      enum i40e_filter_pctype pctype,
9309                      enum rte_eth_input_set_field *field,
9310                      uint16_t size)
9311 {
9312         uint16_t i, j;
9313         int ret = -EINVAL;
9314
9315         static const struct {
9316                 enum rte_eth_input_set_field field;
9317                 uint64_t inset;
9318         } inset_convert_table[] = {
9319                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9320                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9321                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9322                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9323                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9324                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9325                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9326                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9327                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9328                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9329                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9330                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9331                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9332                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9333                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9334                         I40E_INSET_IPV6_NEXT_HDR},
9335                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9336                         I40E_INSET_IPV6_HOP_LIMIT},
9337                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9338                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9339                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9340                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9341                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9342                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9343                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9344                         I40E_INSET_SCTP_VT},
9345                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9346                         I40E_INSET_TUNNEL_DMAC},
9347                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9348                         I40E_INSET_VLAN_TUNNEL},
9349                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9350                         I40E_INSET_TUNNEL_ID},
9351                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9352                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9353                         I40E_INSET_FLEX_PAYLOAD_W1},
9354                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9355                         I40E_INSET_FLEX_PAYLOAD_W2},
9356                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9357                         I40E_INSET_FLEX_PAYLOAD_W3},
9358                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9359                         I40E_INSET_FLEX_PAYLOAD_W4},
9360                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9361                         I40E_INSET_FLEX_PAYLOAD_W5},
9362                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9363                         I40E_INSET_FLEX_PAYLOAD_W6},
9364                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9365                         I40E_INSET_FLEX_PAYLOAD_W7},
9366                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9367                         I40E_INSET_FLEX_PAYLOAD_W8},
9368         };
9369
9370         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9371                 return ret;
9372
9373         /* Only one item allowed for default or all */
9374         if (size == 1) {
9375                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9376                         *inset = i40e_get_default_input_set(pctype);
9377                         return 0;
9378                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9379                         *inset = I40E_INSET_NONE;
9380                         return 0;
9381                 }
9382         }
9383
9384         for (i = 0, *inset = 0; i < size; i++) {
9385                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9386                         if (field[i] == inset_convert_table[j].field) {
9387                                 *inset |= inset_convert_table[j].inset;
9388                                 break;
9389                         }
9390                 }
9391
9392                 /* It contains unsupported input set, return immediately */
9393                 if (j == RTE_DIM(inset_convert_table))
9394                         return ret;
9395         }
9396
9397         return 0;
9398 }
9399
9400 /**
9401  * Translate the input set from bit masks to register aware bit masks
9402  * and vice versa
9403  */
9404 uint64_t
9405 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9406 {
9407         uint64_t val = 0;
9408         uint16_t i;
9409
9410         struct inset_map {
9411                 uint64_t inset;
9412                 uint64_t inset_reg;
9413         };
9414
9415         static const struct inset_map inset_map_common[] = {
9416                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9417                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9418                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9419                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9420                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9421                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9422                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9423                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9424                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9425                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9426                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9427                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9428                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9429                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9430                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9431                 {I40E_INSET_TUNNEL_DMAC,
9432                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9433                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9434                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9435                 {I40E_INSET_TUNNEL_SRC_PORT,
9436                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9437                 {I40E_INSET_TUNNEL_DST_PORT,
9438                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9439                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9440                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9441                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9442                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9443                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9444                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9445                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9446                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9447                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9448         };
9449
9450     /* some different registers map in x722*/
9451         static const struct inset_map inset_map_diff_x722[] = {
9452                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9453                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9454                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9455                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9456         };
9457
9458         static const struct inset_map inset_map_diff_not_x722[] = {
9459                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9460                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9461                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9462                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9463         };
9464
9465         if (input == 0)
9466                 return val;
9467
9468         /* Translate input set to register aware inset */
9469         if (type == I40E_MAC_X722) {
9470                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9471                         if (input & inset_map_diff_x722[i].inset)
9472                                 val |= inset_map_diff_x722[i].inset_reg;
9473                 }
9474         } else {
9475                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9476                         if (input & inset_map_diff_not_x722[i].inset)
9477                                 val |= inset_map_diff_not_x722[i].inset_reg;
9478                 }
9479         }
9480
9481         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9482                 if (input & inset_map_common[i].inset)
9483                         val |= inset_map_common[i].inset_reg;
9484         }
9485
9486         return val;
9487 }
9488
9489 int
9490 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9491 {
9492         uint8_t i, idx = 0;
9493         uint64_t inset_need_mask = inset;
9494
9495         static const struct {
9496                 uint64_t inset;
9497                 uint32_t mask;
9498         } inset_mask_map[] = {
9499                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9500                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9501                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9502                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9503                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9504                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9505                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9506                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9507         };
9508
9509         if (!inset || !mask || !nb_elem)
9510                 return 0;
9511
9512         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9513                 /* Clear the inset bit, if no MASK is required,
9514                  * for example proto + ttl
9515                  */
9516                 if ((inset & inset_mask_map[i].inset) ==
9517                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9518                         inset_need_mask &= ~inset_mask_map[i].inset;
9519                 if (!inset_need_mask)
9520                         return 0;
9521         }
9522         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9523                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9524                     inset_mask_map[i].inset) {
9525                         if (idx >= nb_elem) {
9526                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9527                                 return -EINVAL;
9528                         }
9529                         mask[idx] = inset_mask_map[i].mask;
9530                         idx++;
9531                 }
9532         }
9533
9534         return idx;
9535 }
9536
9537 void
9538 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9539 {
9540         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9541
9542         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9543         if (reg != val)
9544                 i40e_write_rx_ctl(hw, addr, val);
9545         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9546                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9547 }
9548
9549 void
9550 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9551 {
9552         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9553         struct rte_eth_dev *dev;
9554
9555         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9556         if (reg != val) {
9557                 i40e_write_rx_ctl(hw, addr, val);
9558                 PMD_DRV_LOG(WARNING,
9559                             "i40e device %s changed global register [0x%08x]."
9560                             " original: 0x%08x, new: 0x%08x",
9561                             dev->device->name, addr, reg,
9562                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9563         }
9564 }
9565
9566 static void
9567 i40e_filter_input_set_init(struct i40e_pf *pf)
9568 {
9569         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9570         enum i40e_filter_pctype pctype;
9571         uint64_t input_set, inset_reg;
9572         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9573         int num, i;
9574         uint16_t flow_type;
9575
9576         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9577              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9578                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9579
9580                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9581                         continue;
9582
9583                 input_set = i40e_get_default_input_set(pctype);
9584
9585                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9586                                                    I40E_INSET_MASK_NUM_REG);
9587                 if (num < 0)
9588                         return;
9589                 if (pf->support_multi_driver && num > 0) {
9590                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9591                         return;
9592                 }
9593                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9594                                         input_set);
9595
9596                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9597                                       (uint32_t)(inset_reg & UINT32_MAX));
9598                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9599                                      (uint32_t)((inset_reg >>
9600                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9601                 if (!pf->support_multi_driver) {
9602                         i40e_check_write_global_reg(hw,
9603                                             I40E_GLQF_HASH_INSET(0, pctype),
9604                                             (uint32_t)(inset_reg & UINT32_MAX));
9605                         i40e_check_write_global_reg(hw,
9606                                              I40E_GLQF_HASH_INSET(1, pctype),
9607                                              (uint32_t)((inset_reg >>
9608                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9609
9610                         for (i = 0; i < num; i++) {
9611                                 i40e_check_write_global_reg(hw,
9612                                                     I40E_GLQF_FD_MSK(i, pctype),
9613                                                     mask_reg[i]);
9614                                 i40e_check_write_global_reg(hw,
9615                                                   I40E_GLQF_HASH_MSK(i, pctype),
9616                                                   mask_reg[i]);
9617                         }
9618                         /*clear unused mask registers of the pctype */
9619                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9620                                 i40e_check_write_global_reg(hw,
9621                                                     I40E_GLQF_FD_MSK(i, pctype),
9622                                                     0);
9623                                 i40e_check_write_global_reg(hw,
9624                                                   I40E_GLQF_HASH_MSK(i, pctype),
9625                                                   0);
9626                         }
9627                 } else {
9628                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9629                 }
9630                 I40E_WRITE_FLUSH(hw);
9631
9632                 /* store the default input set */
9633                 if (!pf->support_multi_driver)
9634                         pf->hash_input_set[pctype] = input_set;
9635                 pf->fdir.input_set[pctype] = input_set;
9636         }
9637 }
9638
9639 int
9640 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9641                          struct rte_eth_input_set_conf *conf)
9642 {
9643         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9644         enum i40e_filter_pctype pctype;
9645         uint64_t input_set, inset_reg = 0;
9646         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9647         int ret, i, num;
9648
9649         if (!conf) {
9650                 PMD_DRV_LOG(ERR, "Invalid pointer");
9651                 return -EFAULT;
9652         }
9653         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9654             conf->op != RTE_ETH_INPUT_SET_ADD) {
9655                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9656                 return -EINVAL;
9657         }
9658
9659         if (pf->support_multi_driver) {
9660                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9661                 return -ENOTSUP;
9662         }
9663
9664         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9665         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9666                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9667                 return -EINVAL;
9668         }
9669
9670         if (hw->mac.type == I40E_MAC_X722) {
9671                 /* get translated pctype value in fd pctype register */
9672                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9673                         I40E_GLQF_FD_PCTYPES((int)pctype));
9674         }
9675
9676         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9677                                    conf->inset_size);
9678         if (ret) {
9679                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9680                 return -EINVAL;
9681         }
9682
9683         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9684                 /* get inset value in register */
9685                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9686                 inset_reg <<= I40E_32_BIT_WIDTH;
9687                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9688                 input_set |= pf->hash_input_set[pctype];
9689         }
9690         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9691                                            I40E_INSET_MASK_NUM_REG);
9692         if (num < 0)
9693                 return -EINVAL;
9694
9695         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9696
9697         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9698                                     (uint32_t)(inset_reg & UINT32_MAX));
9699         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9700                                     (uint32_t)((inset_reg >>
9701                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9702
9703         for (i = 0; i < num; i++)
9704                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9705                                             mask_reg[i]);
9706         /*clear unused mask registers of the pctype */
9707         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9708                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9709                                             0);
9710         I40E_WRITE_FLUSH(hw);
9711
9712         pf->hash_input_set[pctype] = input_set;
9713         return 0;
9714 }
9715
9716 /* Convert ethertype filter structure */
9717 static int
9718 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9719                               struct i40e_ethertype_filter *filter)
9720 {
9721         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9722                 RTE_ETHER_ADDR_LEN);
9723         filter->input.ether_type = input->ether_type;
9724         filter->flags = input->flags;
9725         filter->queue = input->queue;
9726
9727         return 0;
9728 }
9729
9730 /* Check if there exists the ehtertype filter */
9731 struct i40e_ethertype_filter *
9732 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9733                                 const struct i40e_ethertype_filter_input *input)
9734 {
9735         int ret;
9736
9737         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9738         if (ret < 0)
9739                 return NULL;
9740
9741         return ethertype_rule->hash_map[ret];
9742 }
9743
9744 /* Add ethertype filter in SW list */
9745 static int
9746 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9747                                 struct i40e_ethertype_filter *filter)
9748 {
9749         struct i40e_ethertype_rule *rule = &pf->ethertype;
9750         int ret;
9751
9752         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9753         if (ret < 0) {
9754                 PMD_DRV_LOG(ERR,
9755                             "Failed to insert ethertype filter"
9756                             " to hash table %d!",
9757                             ret);
9758                 return ret;
9759         }
9760         rule->hash_map[ret] = filter;
9761
9762         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9763
9764         return 0;
9765 }
9766
9767 /* Delete ethertype filter in SW list */
9768 int
9769 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9770                              struct i40e_ethertype_filter_input *input)
9771 {
9772         struct i40e_ethertype_rule *rule = &pf->ethertype;
9773         struct i40e_ethertype_filter *filter;
9774         int ret;
9775
9776         ret = rte_hash_del_key(rule->hash_table, input);
9777         if (ret < 0) {
9778                 PMD_DRV_LOG(ERR,
9779                             "Failed to delete ethertype filter"
9780                             " to hash table %d!",
9781                             ret);
9782                 return ret;
9783         }
9784         filter = rule->hash_map[ret];
9785         rule->hash_map[ret] = NULL;
9786
9787         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9788         rte_free(filter);
9789
9790         return 0;
9791 }
9792
9793 /*
9794  * Configure ethertype filter, which can director packet by filtering
9795  * with mac address and ether_type or only ether_type
9796  */
9797 int
9798 i40e_ethertype_filter_set(struct i40e_pf *pf,
9799                         struct rte_eth_ethertype_filter *filter,
9800                         bool add)
9801 {
9802         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9803         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9804         struct i40e_ethertype_filter *ethertype_filter, *node;
9805         struct i40e_ethertype_filter check_filter;
9806         struct i40e_control_filter_stats stats;
9807         uint16_t flags = 0;
9808         int ret;
9809
9810         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9811                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9812                 return -EINVAL;
9813         }
9814         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9815                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9816                 PMD_DRV_LOG(ERR,
9817                         "unsupported ether_type(0x%04x) in control packet filter.",
9818                         filter->ether_type);
9819                 return -EINVAL;
9820         }
9821         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9822                 PMD_DRV_LOG(WARNING,
9823                         "filter vlan ether_type in first tag is not supported.");
9824
9825         /* Check if there is the filter in SW list */
9826         memset(&check_filter, 0, sizeof(check_filter));
9827         i40e_ethertype_filter_convert(filter, &check_filter);
9828         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9829                                                &check_filter.input);
9830         if (add && node) {
9831                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9832                 return -EINVAL;
9833         }
9834
9835         if (!add && !node) {
9836                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9837                 return -EINVAL;
9838         }
9839
9840         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9841                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9842         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9843                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9844         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9845
9846         memset(&stats, 0, sizeof(stats));
9847         ret = i40e_aq_add_rem_control_packet_filter(hw,
9848                         filter->mac_addr.addr_bytes,
9849                         filter->ether_type, flags,
9850                         pf->main_vsi->seid,
9851                         filter->queue, add, &stats, NULL);
9852
9853         PMD_DRV_LOG(INFO,
9854                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9855                 ret, stats.mac_etype_used, stats.etype_used,
9856                 stats.mac_etype_free, stats.etype_free);
9857         if (ret < 0)
9858                 return -ENOSYS;
9859
9860         /* Add or delete a filter in SW list */
9861         if (add) {
9862                 ethertype_filter = rte_zmalloc("ethertype_filter",
9863                                        sizeof(*ethertype_filter), 0);
9864                 if (ethertype_filter == NULL) {
9865                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9866                         return -ENOMEM;
9867                 }
9868
9869                 rte_memcpy(ethertype_filter, &check_filter,
9870                            sizeof(check_filter));
9871                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9872                 if (ret < 0)
9873                         rte_free(ethertype_filter);
9874         } else {
9875                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9876         }
9877
9878         return ret;
9879 }
9880
9881 static int
9882 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9883                      enum rte_filter_type filter_type,
9884                      enum rte_filter_op filter_op,
9885                      void *arg)
9886 {
9887         int ret = 0;
9888
9889         if (dev == NULL)
9890                 return -EINVAL;
9891
9892         switch (filter_type) {
9893         case RTE_ETH_FILTER_GENERIC:
9894                 if (filter_op != RTE_ETH_FILTER_GET)
9895                         return -EINVAL;
9896                 *(const void **)arg = &i40e_flow_ops;
9897                 break;
9898         default:
9899                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9900                                                         filter_type);
9901                 ret = -EINVAL;
9902                 break;
9903         }
9904
9905         return ret;
9906 }
9907
9908 /*
9909  * Check and enable Extended Tag.
9910  * Enabling Extended Tag is important for 40G performance.
9911  */
9912 static void
9913 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9914 {
9915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9916         uint32_t buf = 0;
9917         int ret;
9918
9919         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9920                                       PCI_DEV_CAP_REG);
9921         if (ret < 0) {
9922                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9923                             PCI_DEV_CAP_REG);
9924                 return;
9925         }
9926         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9927                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9928                 return;
9929         }
9930
9931         buf = 0;
9932         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9933                                       PCI_DEV_CTRL_REG);
9934         if (ret < 0) {
9935                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9936                             PCI_DEV_CTRL_REG);
9937                 return;
9938         }
9939         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9940                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9941                 return;
9942         }
9943         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9944         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9945                                        PCI_DEV_CTRL_REG);
9946         if (ret < 0) {
9947                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9948                             PCI_DEV_CTRL_REG);
9949                 return;
9950         }
9951 }
9952
9953 /*
9954  * As some registers wouldn't be reset unless a global hardware reset,
9955  * hardware initialization is needed to put those registers into an
9956  * expected initial state.
9957  */
9958 static void
9959 i40e_hw_init(struct rte_eth_dev *dev)
9960 {
9961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9962
9963         i40e_enable_extended_tag(dev);
9964
9965         /* clear the PF Queue Filter control register */
9966         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9967
9968         /* Disable symmetric hash per port */
9969         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9970 }
9971
9972 /*
9973  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9974  * however this function will return only one highest pctype index,
9975  * which is not quite correct. This is known problem of i40e driver
9976  * and needs to be fixed later.
9977  */
9978 enum i40e_filter_pctype
9979 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9980 {
9981         int i;
9982         uint64_t pctype_mask;
9983
9984         if (flow_type < I40E_FLOW_TYPE_MAX) {
9985                 pctype_mask = adapter->pctypes_tbl[flow_type];
9986                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9987                         if (pctype_mask & (1ULL << i))
9988                                 return (enum i40e_filter_pctype)i;
9989                 }
9990         }
9991         return I40E_FILTER_PCTYPE_INVALID;
9992 }
9993
9994 uint16_t
9995 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9996                         enum i40e_filter_pctype pctype)
9997 {
9998         uint16_t flowtype;
9999         uint64_t pctype_mask = 1ULL << pctype;
10000
10001         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10002              flowtype++) {
10003                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10004                         return flowtype;
10005         }
10006
10007         return RTE_ETH_FLOW_UNKNOWN;
10008 }
10009
10010 /*
10011  * On X710, performance number is far from the expectation on recent firmware
10012  * versions; on XL710, performance number is also far from the expectation on
10013  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10014  * mode is enabled and port MAC address is equal to the packet destination MAC
10015  * address. The fix for this issue may not be integrated in the following
10016  * firmware version. So the workaround in software driver is needed. It needs
10017  * to modify the initial values of 3 internal only registers for both X710 and
10018  * XL710. Note that the values for X710 or XL710 could be different, and the
10019  * workaround can be removed when it is fixed in firmware in the future.
10020  */
10021
10022 /* For both X710 and XL710 */
10023 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10024 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10025 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10026
10027 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10028 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10029
10030 /* For X722 */
10031 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10032 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10033
10034 /* For X710 */
10035 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10036 /* For XL710 */
10037 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10038 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10039
10040 /*
10041  * GL_SWR_PM_UP_THR:
10042  * The value is not impacted from the link speed, its value is set according
10043  * to the total number of ports for a better pipe-monitor configuration.
10044  */
10045 static bool
10046 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10047 {
10048 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10049                 .device_id = (dev),   \
10050                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10051
10052 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10053                 .device_id = (dev),   \
10054                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10055
10056         static const struct {
10057                 uint16_t device_id;
10058                 uint32_t val;
10059         } swr_pm_table[] = {
10060                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10061                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10062                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10063                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10064                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10065
10066                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10067                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10068                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10069                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10070                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10071                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10072                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10073         };
10074         uint32_t i;
10075
10076         if (value == NULL) {
10077                 PMD_DRV_LOG(ERR, "value is NULL");
10078                 return false;
10079         }
10080
10081         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10082                 if (hw->device_id == swr_pm_table[i].device_id) {
10083                         *value = swr_pm_table[i].val;
10084
10085                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10086                                     "value - 0x%08x",
10087                                     hw->device_id, *value);
10088                         return true;
10089                 }
10090         }
10091
10092         return false;
10093 }
10094
10095 static int
10096 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10097 {
10098         enum i40e_status_code status;
10099         struct i40e_aq_get_phy_abilities_resp phy_ab;
10100         int ret = -ENOTSUP;
10101         int retries = 0;
10102
10103         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10104                                               NULL);
10105
10106         while (status) {
10107                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10108                         status);
10109                 retries++;
10110                 rte_delay_us(100000);
10111                 if  (retries < 5)
10112                         status = i40e_aq_get_phy_capabilities(hw, false,
10113                                         true, &phy_ab, NULL);
10114                 else
10115                         return ret;
10116         }
10117         return 0;
10118 }
10119
10120 static void
10121 i40e_configure_registers(struct i40e_hw *hw)
10122 {
10123         static struct {
10124                 uint32_t addr;
10125                 uint64_t val;
10126         } reg_table[] = {
10127                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10128                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10129                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10130         };
10131         uint64_t reg;
10132         uint32_t i;
10133         int ret;
10134
10135         for (i = 0; i < RTE_DIM(reg_table); i++) {
10136                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10137                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10138                                 reg_table[i].val =
10139                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10140                         else /* For X710/XL710/XXV710 */
10141                                 if (hw->aq.fw_maj_ver < 6)
10142                                         reg_table[i].val =
10143                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10144                                 else
10145                                         reg_table[i].val =
10146                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10147                 }
10148
10149                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10150                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10151                                 reg_table[i].val =
10152                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10153                         else /* For X710/XL710/XXV710 */
10154                                 reg_table[i].val =
10155                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10156                 }
10157
10158                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10159                         uint32_t cfg_val;
10160
10161                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10162                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10163                                             "GL_SWR_PM_UP_THR value fixup",
10164                                             hw->device_id);
10165                                 continue;
10166                         }
10167
10168                         reg_table[i].val = cfg_val;
10169                 }
10170
10171                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10172                                                         &reg, NULL);
10173                 if (ret < 0) {
10174                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10175                                                         reg_table[i].addr);
10176                         break;
10177                 }
10178                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10179                                                 reg_table[i].addr, reg);
10180                 if (reg == reg_table[i].val)
10181                         continue;
10182
10183                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10184                                                 reg_table[i].val, NULL);
10185                 if (ret < 0) {
10186                         PMD_DRV_LOG(ERR,
10187                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10188                                 reg_table[i].val, reg_table[i].addr);
10189                         break;
10190                 }
10191                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10192                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10193         }
10194 }
10195
10196 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10197 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10198 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10199 static int
10200 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10201 {
10202         uint32_t reg;
10203         int ret;
10204
10205         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10206                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10207                 return -EINVAL;
10208         }
10209
10210         /* Configure for double VLAN RX stripping */
10211         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10212         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10213                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10214                 ret = i40e_aq_debug_write_register(hw,
10215                                                    I40E_VSI_TSR(vsi->vsi_id),
10216                                                    reg, NULL);
10217                 if (ret < 0) {
10218                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10219                                     vsi->vsi_id);
10220                         return I40E_ERR_CONFIG;
10221                 }
10222         }
10223
10224         /* Configure for double VLAN TX insertion */
10225         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10226         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10227                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10228                 ret = i40e_aq_debug_write_register(hw,
10229                                                    I40E_VSI_L2TAGSTXVALID(
10230                                                    vsi->vsi_id), reg, NULL);
10231                 if (ret < 0) {
10232                         PMD_DRV_LOG(ERR,
10233                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10234                                 vsi->vsi_id);
10235                         return I40E_ERR_CONFIG;
10236                 }
10237         }
10238
10239         return 0;
10240 }
10241
10242 /**
10243  * i40e_aq_add_mirror_rule
10244  * @hw: pointer to the hardware structure
10245  * @seid: VEB seid to add mirror rule to
10246  * @dst_id: destination vsi seid
10247  * @entries: Buffer which contains the entities to be mirrored
10248  * @count: number of entities contained in the buffer
10249  * @rule_id:the rule_id of the rule to be added
10250  *
10251  * Add a mirror rule for a given veb.
10252  *
10253  **/
10254 static enum i40e_status_code
10255 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10256                         uint16_t seid, uint16_t dst_id,
10257                         uint16_t rule_type, uint16_t *entries,
10258                         uint16_t count, uint16_t *rule_id)
10259 {
10260         struct i40e_aq_desc desc;
10261         struct i40e_aqc_add_delete_mirror_rule cmd;
10262         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10263                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10264                 &desc.params.raw;
10265         uint16_t buff_len;
10266         enum i40e_status_code status;
10267
10268         i40e_fill_default_direct_cmd_desc(&desc,
10269                                           i40e_aqc_opc_add_mirror_rule);
10270         memset(&cmd, 0, sizeof(cmd));
10271
10272         buff_len = sizeof(uint16_t) * count;
10273         desc.datalen = rte_cpu_to_le_16(buff_len);
10274         if (buff_len > 0)
10275                 desc.flags |= rte_cpu_to_le_16(
10276                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10277         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10278                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10279         cmd.num_entries = rte_cpu_to_le_16(count);
10280         cmd.seid = rte_cpu_to_le_16(seid);
10281         cmd.destination = rte_cpu_to_le_16(dst_id);
10282
10283         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10284         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10285         PMD_DRV_LOG(INFO,
10286                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10287                 hw->aq.asq_last_status, resp->rule_id,
10288                 resp->mirror_rules_used, resp->mirror_rules_free);
10289         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10290
10291         return status;
10292 }
10293
10294 /**
10295  * i40e_aq_del_mirror_rule
10296  * @hw: pointer to the hardware structure
10297  * @seid: VEB seid to add mirror rule to
10298  * @entries: Buffer which contains the entities to be mirrored
10299  * @count: number of entities contained in the buffer
10300  * @rule_id:the rule_id of the rule to be delete
10301  *
10302  * Delete a mirror rule for a given veb.
10303  *
10304  **/
10305 static enum i40e_status_code
10306 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10307                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10308                 uint16_t count, uint16_t rule_id)
10309 {
10310         struct i40e_aq_desc desc;
10311         struct i40e_aqc_add_delete_mirror_rule cmd;
10312         uint16_t buff_len = 0;
10313         enum i40e_status_code status;
10314         void *buff = NULL;
10315
10316         i40e_fill_default_direct_cmd_desc(&desc,
10317                                           i40e_aqc_opc_delete_mirror_rule);
10318         memset(&cmd, 0, sizeof(cmd));
10319         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10320                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10321                                                           I40E_AQ_FLAG_RD));
10322                 cmd.num_entries = count;
10323                 buff_len = sizeof(uint16_t) * count;
10324                 desc.datalen = rte_cpu_to_le_16(buff_len);
10325                 buff = (void *)entries;
10326         } else
10327                 /* rule id is filled in destination field for deleting mirror rule */
10328                 cmd.destination = rte_cpu_to_le_16(rule_id);
10329
10330         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10331                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10332         cmd.seid = rte_cpu_to_le_16(seid);
10333
10334         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10335         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10336
10337         return status;
10338 }
10339
10340 /**
10341  * i40e_mirror_rule_set
10342  * @dev: pointer to the hardware structure
10343  * @mirror_conf: mirror rule info
10344  * @sw_id: mirror rule's sw_id
10345  * @on: enable/disable
10346  *
10347  * set a mirror rule.
10348  *
10349  **/
10350 static int
10351 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10352                         struct rte_eth_mirror_conf *mirror_conf,
10353                         uint8_t sw_id, uint8_t on)
10354 {
10355         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10357         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10358         struct i40e_mirror_rule *parent = NULL;
10359         uint16_t seid, dst_seid, rule_id;
10360         uint16_t i, j = 0;
10361         int ret;
10362
10363         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10364
10365         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10366                 PMD_DRV_LOG(ERR,
10367                         "mirror rule can not be configured without veb or vfs.");
10368                 return -ENOSYS;
10369         }
10370         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10371                 PMD_DRV_LOG(ERR, "mirror table is full.");
10372                 return -ENOSPC;
10373         }
10374         if (mirror_conf->dst_pool > pf->vf_num) {
10375                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10376                                  mirror_conf->dst_pool);
10377                 return -EINVAL;
10378         }
10379
10380         seid = pf->main_vsi->veb->seid;
10381
10382         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10383                 if (sw_id <= it->index) {
10384                         mirr_rule = it;
10385                         break;
10386                 }
10387                 parent = it;
10388         }
10389         if (mirr_rule && sw_id == mirr_rule->index) {
10390                 if (on) {
10391                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10392                         return -EEXIST;
10393                 } else {
10394                         ret = i40e_aq_del_mirror_rule(hw, seid,
10395                                         mirr_rule->rule_type,
10396                                         mirr_rule->entries,
10397                                         mirr_rule->num_entries, mirr_rule->id);
10398                         if (ret < 0) {
10399                                 PMD_DRV_LOG(ERR,
10400                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10401                                         ret, hw->aq.asq_last_status);
10402                                 return -ENOSYS;
10403                         }
10404                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10405                         rte_free(mirr_rule);
10406                         pf->nb_mirror_rule--;
10407                         return 0;
10408                 }
10409         } else if (!on) {
10410                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10411                 return -ENOENT;
10412         }
10413
10414         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10415                                 sizeof(struct i40e_mirror_rule) , 0);
10416         if (!mirr_rule) {
10417                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10418                 return I40E_ERR_NO_MEMORY;
10419         }
10420         switch (mirror_conf->rule_type) {
10421         case ETH_MIRROR_VLAN:
10422                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10423                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10424                                 mirr_rule->entries[j] =
10425                                         mirror_conf->vlan.vlan_id[i];
10426                                 j++;
10427                         }
10428                 }
10429                 if (j == 0) {
10430                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10431                         rte_free(mirr_rule);
10432                         return -EINVAL;
10433                 }
10434                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10435                 break;
10436         case ETH_MIRROR_VIRTUAL_POOL_UP:
10437         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10438                 /* check if the specified pool bit is out of range */
10439                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10440                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10441                         rte_free(mirr_rule);
10442                         return -EINVAL;
10443                 }
10444                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10445                         if (mirror_conf->pool_mask & (1ULL << i)) {
10446                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10447                                 j++;
10448                         }
10449                 }
10450                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10451                         /* add pf vsi to entries */
10452                         mirr_rule->entries[j] = pf->main_vsi_seid;
10453                         j++;
10454                 }
10455                 if (j == 0) {
10456                         PMD_DRV_LOG(ERR, "pool is not specified.");
10457                         rte_free(mirr_rule);
10458                         return -EINVAL;
10459                 }
10460                 /* egress and ingress in aq commands means from switch but not port */
10461                 mirr_rule->rule_type =
10462                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10463                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10464                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10465                 break;
10466         case ETH_MIRROR_UPLINK_PORT:
10467                 /* egress and ingress in aq commands means from switch but not port*/
10468                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10469                 break;
10470         case ETH_MIRROR_DOWNLINK_PORT:
10471                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10472                 break;
10473         default:
10474                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10475                         mirror_conf->rule_type);
10476                 rte_free(mirr_rule);
10477                 return -EINVAL;
10478         }
10479
10480         /* If the dst_pool is equal to vf_num, consider it as PF */
10481         if (mirror_conf->dst_pool == pf->vf_num)
10482                 dst_seid = pf->main_vsi_seid;
10483         else
10484                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10485
10486         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10487                                       mirr_rule->rule_type, mirr_rule->entries,
10488                                       j, &rule_id);
10489         if (ret < 0) {
10490                 PMD_DRV_LOG(ERR,
10491                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10492                         ret, hw->aq.asq_last_status);
10493                 rte_free(mirr_rule);
10494                 return -ENOSYS;
10495         }
10496
10497         mirr_rule->index = sw_id;
10498         mirr_rule->num_entries = j;
10499         mirr_rule->id = rule_id;
10500         mirr_rule->dst_vsi_seid = dst_seid;
10501
10502         if (parent)
10503                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10504         else
10505                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10506
10507         pf->nb_mirror_rule++;
10508         return 0;
10509 }
10510
10511 /**
10512  * i40e_mirror_rule_reset
10513  * @dev: pointer to the device
10514  * @sw_id: mirror rule's sw_id
10515  *
10516  * reset a mirror rule.
10517  *
10518  **/
10519 static int
10520 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10521 {
10522         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10524         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10525         uint16_t seid;
10526         int ret;
10527
10528         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10529
10530         seid = pf->main_vsi->veb->seid;
10531
10532         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10533                 if (sw_id == it->index) {
10534                         mirr_rule = it;
10535                         break;
10536                 }
10537         }
10538         if (mirr_rule) {
10539                 ret = i40e_aq_del_mirror_rule(hw, seid,
10540                                 mirr_rule->rule_type,
10541                                 mirr_rule->entries,
10542                                 mirr_rule->num_entries, mirr_rule->id);
10543                 if (ret < 0) {
10544                         PMD_DRV_LOG(ERR,
10545                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10546                                 ret, hw->aq.asq_last_status);
10547                         return -ENOSYS;
10548                 }
10549                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10550                 rte_free(mirr_rule);
10551                 pf->nb_mirror_rule--;
10552         } else {
10553                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10554                 return -ENOENT;
10555         }
10556         return 0;
10557 }
10558
10559 static uint64_t
10560 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10561 {
10562         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10563         uint64_t systim_cycles;
10564
10565         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10566         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10567                         << 32;
10568
10569         return systim_cycles;
10570 }
10571
10572 static uint64_t
10573 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10574 {
10575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10576         uint64_t rx_tstamp;
10577
10578         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10579         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10580                         << 32;
10581
10582         return rx_tstamp;
10583 }
10584
10585 static uint64_t
10586 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10587 {
10588         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10589         uint64_t tx_tstamp;
10590
10591         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10592         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10593                         << 32;
10594
10595         return tx_tstamp;
10596 }
10597
10598 static void
10599 i40e_start_timecounters(struct rte_eth_dev *dev)
10600 {
10601         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602         struct i40e_adapter *adapter = dev->data->dev_private;
10603         struct rte_eth_link link;
10604         uint32_t tsync_inc_l;
10605         uint32_t tsync_inc_h;
10606
10607         /* Get current link speed. */
10608         i40e_dev_link_update(dev, 1);
10609         rte_eth_linkstatus_get(dev, &link);
10610
10611         switch (link.link_speed) {
10612         case ETH_SPEED_NUM_40G:
10613         case ETH_SPEED_NUM_25G:
10614                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10615                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10616                 break;
10617         case ETH_SPEED_NUM_10G:
10618                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10619                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10620                 break;
10621         case ETH_SPEED_NUM_1G:
10622                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10623                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10624                 break;
10625         default:
10626                 tsync_inc_l = 0x0;
10627                 tsync_inc_h = 0x0;
10628         }
10629
10630         /* Set the timesync increment value. */
10631         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10632         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10633
10634         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10635         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10636         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10637
10638         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10639         adapter->systime_tc.cc_shift = 0;
10640         adapter->systime_tc.nsec_mask = 0;
10641
10642         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10643         adapter->rx_tstamp_tc.cc_shift = 0;
10644         adapter->rx_tstamp_tc.nsec_mask = 0;
10645
10646         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10647         adapter->tx_tstamp_tc.cc_shift = 0;
10648         adapter->tx_tstamp_tc.nsec_mask = 0;
10649 }
10650
10651 static int
10652 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10653 {
10654         struct i40e_adapter *adapter = dev->data->dev_private;
10655
10656         adapter->systime_tc.nsec += delta;
10657         adapter->rx_tstamp_tc.nsec += delta;
10658         adapter->tx_tstamp_tc.nsec += delta;
10659
10660         return 0;
10661 }
10662
10663 static int
10664 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10665 {
10666         uint64_t ns;
10667         struct i40e_adapter *adapter = dev->data->dev_private;
10668
10669         ns = rte_timespec_to_ns(ts);
10670
10671         /* Set the timecounters to a new value. */
10672         adapter->systime_tc.nsec = ns;
10673         adapter->rx_tstamp_tc.nsec = ns;
10674         adapter->tx_tstamp_tc.nsec = ns;
10675
10676         return 0;
10677 }
10678
10679 static int
10680 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10681 {
10682         uint64_t ns, systime_cycles;
10683         struct i40e_adapter *adapter = dev->data->dev_private;
10684
10685         systime_cycles = i40e_read_systime_cyclecounter(dev);
10686         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10687         *ts = rte_ns_to_timespec(ns);
10688
10689         return 0;
10690 }
10691
10692 static int
10693 i40e_timesync_enable(struct rte_eth_dev *dev)
10694 {
10695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10696         uint32_t tsync_ctl_l;
10697         uint32_t tsync_ctl_h;
10698
10699         /* Stop the timesync system time. */
10700         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10701         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10702         /* Reset the timesync system time value. */
10703         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10704         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10705
10706         i40e_start_timecounters(dev);
10707
10708         /* Clear timesync registers. */
10709         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10710         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10711         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10712         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10713         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10714         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10715
10716         /* Enable timestamping of PTP packets. */
10717         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10718         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10719
10720         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10721         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10722         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10723
10724         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10725         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10726
10727         return 0;
10728 }
10729
10730 static int
10731 i40e_timesync_disable(struct rte_eth_dev *dev)
10732 {
10733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10734         uint32_t tsync_ctl_l;
10735         uint32_t tsync_ctl_h;
10736
10737         /* Disable timestamping of transmitted PTP packets. */
10738         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10739         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10740
10741         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10742         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10743
10744         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10745         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10746
10747         /* Reset the timesync increment value. */
10748         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10749         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10750
10751         return 0;
10752 }
10753
10754 static int
10755 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10756                                 struct timespec *timestamp, uint32_t flags)
10757 {
10758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10759         struct i40e_adapter *adapter = dev->data->dev_private;
10760         uint32_t sync_status;
10761         uint32_t index = flags & 0x03;
10762         uint64_t rx_tstamp_cycles;
10763         uint64_t ns;
10764
10765         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10766         if ((sync_status & (1 << index)) == 0)
10767                 return -EINVAL;
10768
10769         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10770         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10771         *timestamp = rte_ns_to_timespec(ns);
10772
10773         return 0;
10774 }
10775
10776 static int
10777 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10778                                 struct timespec *timestamp)
10779 {
10780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10781         struct i40e_adapter *adapter = dev->data->dev_private;
10782         uint32_t sync_status;
10783         uint64_t tx_tstamp_cycles;
10784         uint64_t ns;
10785
10786         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10787         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10788                 return -EINVAL;
10789
10790         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10791         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10792         *timestamp = rte_ns_to_timespec(ns);
10793
10794         return 0;
10795 }
10796
10797 /*
10798  * i40e_parse_dcb_configure - parse dcb configure from user
10799  * @dev: the device being configured
10800  * @dcb_cfg: pointer of the result of parse
10801  * @*tc_map: bit map of enabled traffic classes
10802  *
10803  * Returns 0 on success, negative value on failure
10804  */
10805 static int
10806 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10807                          struct i40e_dcbx_config *dcb_cfg,
10808                          uint8_t *tc_map)
10809 {
10810         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10811         uint8_t i, tc_bw, bw_lf;
10812
10813         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10814
10815         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10816         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10817                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10818                 return -EINVAL;
10819         }
10820
10821         /* assume each tc has the same bw */
10822         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10823         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10824                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10825         /* to ensure the sum of tcbw is equal to 100 */
10826         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10827         for (i = 0; i < bw_lf; i++)
10828                 dcb_cfg->etscfg.tcbwtable[i]++;
10829
10830         /* assume each tc has the same Transmission Selection Algorithm */
10831         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10832                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10833
10834         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10835                 dcb_cfg->etscfg.prioritytable[i] =
10836                                 dcb_rx_conf->dcb_tc[i];
10837
10838         /* FW needs one App to configure HW */
10839         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10840         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10841         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10842         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10843
10844         if (dcb_rx_conf->nb_tcs == 0)
10845                 *tc_map = 1; /* tc0 only */
10846         else
10847                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10848
10849         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10850                 dcb_cfg->pfc.willing = 0;
10851                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10852                 dcb_cfg->pfc.pfcenable = *tc_map;
10853         }
10854         return 0;
10855 }
10856
10857
10858 static enum i40e_status_code
10859 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10860                               struct i40e_aqc_vsi_properties_data *info,
10861                               uint8_t enabled_tcmap)
10862 {
10863         enum i40e_status_code ret;
10864         int i, total_tc = 0;
10865         uint16_t qpnum_per_tc, bsf, qp_idx;
10866         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10867         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10868         uint16_t used_queues;
10869
10870         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10871         if (ret != I40E_SUCCESS)
10872                 return ret;
10873
10874         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10875                 if (enabled_tcmap & (1 << i))
10876                         total_tc++;
10877         }
10878         if (total_tc == 0)
10879                 total_tc = 1;
10880         vsi->enabled_tc = enabled_tcmap;
10881
10882         /* different VSI has different queues assigned */
10883         if (vsi->type == I40E_VSI_MAIN)
10884                 used_queues = dev_data->nb_rx_queues -
10885                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10886         else if (vsi->type == I40E_VSI_VMDQ2)
10887                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10888         else {
10889                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10890                 return I40E_ERR_NO_AVAILABLE_VSI;
10891         }
10892
10893         qpnum_per_tc = used_queues / total_tc;
10894         /* Number of queues per enabled TC */
10895         if (qpnum_per_tc == 0) {
10896                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10897                 return I40E_ERR_INVALID_QP_ID;
10898         }
10899         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10900                                 I40E_MAX_Q_PER_TC);
10901         bsf = rte_bsf32(qpnum_per_tc);
10902
10903         /**
10904          * Configure TC and queue mapping parameters, for enabled TC,
10905          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10906          * default queue will serve it.
10907          */
10908         qp_idx = 0;
10909         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10910                 if (vsi->enabled_tc & (1 << i)) {
10911                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10912                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10913                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10914                         qp_idx += qpnum_per_tc;
10915                 } else
10916                         info->tc_mapping[i] = 0;
10917         }
10918
10919         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10920         if (vsi->type == I40E_VSI_SRIOV) {
10921                 info->mapping_flags |=
10922                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10923                 for (i = 0; i < vsi->nb_qps; i++)
10924                         info->queue_mapping[i] =
10925                                 rte_cpu_to_le_16(vsi->base_queue + i);
10926         } else {
10927                 info->mapping_flags |=
10928                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10929                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10930         }
10931         info->valid_sections |=
10932                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10933
10934         return I40E_SUCCESS;
10935 }
10936
10937 /*
10938  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10939  * @veb: VEB to be configured
10940  * @tc_map: enabled TC bitmap
10941  *
10942  * Returns 0 on success, negative value on failure
10943  */
10944 static enum i40e_status_code
10945 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10946 {
10947         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10948         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10949         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10950         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10951         enum i40e_status_code ret = I40E_SUCCESS;
10952         int i;
10953         uint32_t bw_max;
10954
10955         /* Check if enabled_tc is same as existing or new TCs */
10956         if (veb->enabled_tc == tc_map)
10957                 return ret;
10958
10959         /* configure tc bandwidth */
10960         memset(&veb_bw, 0, sizeof(veb_bw));
10961         veb_bw.tc_valid_bits = tc_map;
10962         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10963         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10964                 if (tc_map & BIT_ULL(i))
10965                         veb_bw.tc_bw_share_credits[i] = 1;
10966         }
10967         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10968                                                    &veb_bw, NULL);
10969         if (ret) {
10970                 PMD_INIT_LOG(ERR,
10971                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10972                         hw->aq.asq_last_status);
10973                 return ret;
10974         }
10975
10976         memset(&ets_query, 0, sizeof(ets_query));
10977         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10978                                                    &ets_query, NULL);
10979         if (ret != I40E_SUCCESS) {
10980                 PMD_DRV_LOG(ERR,
10981                         "Failed to get switch_comp ETS configuration %u",
10982                         hw->aq.asq_last_status);
10983                 return ret;
10984         }
10985         memset(&bw_query, 0, sizeof(bw_query));
10986         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10987                                                   &bw_query, NULL);
10988         if (ret != I40E_SUCCESS) {
10989                 PMD_DRV_LOG(ERR,
10990                         "Failed to get switch_comp bandwidth configuration %u",
10991                         hw->aq.asq_last_status);
10992                 return ret;
10993         }
10994
10995         /* store and print out BW info */
10996         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10997         veb->bw_info.bw_max = ets_query.tc_bw_max;
10998         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10999         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11000         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11001                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11002                      I40E_16_BIT_WIDTH);
11003         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11004                 veb->bw_info.bw_ets_share_credits[i] =
11005                                 bw_query.tc_bw_share_credits[i];
11006                 veb->bw_info.bw_ets_credits[i] =
11007                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11008                 /* 4 bits per TC, 4th bit is reserved */
11009                 veb->bw_info.bw_ets_max[i] =
11010                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11011                                   RTE_LEN2MASK(3, uint8_t));
11012                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11013                             veb->bw_info.bw_ets_share_credits[i]);
11014                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11015                             veb->bw_info.bw_ets_credits[i]);
11016                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11017                             veb->bw_info.bw_ets_max[i]);
11018         }
11019
11020         veb->enabled_tc = tc_map;
11021
11022         return ret;
11023 }
11024
11025
11026 /*
11027  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11028  * @vsi: VSI to be configured
11029  * @tc_map: enabled TC bitmap
11030  *
11031  * Returns 0 on success, negative value on failure
11032  */
11033 static enum i40e_status_code
11034 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11035 {
11036         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11037         struct i40e_vsi_context ctxt;
11038         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11039         enum i40e_status_code ret = I40E_SUCCESS;
11040         int i;
11041
11042         /* Check if enabled_tc is same as existing or new TCs */
11043         if (vsi->enabled_tc == tc_map)
11044                 return ret;
11045
11046         /* configure tc bandwidth */
11047         memset(&bw_data, 0, sizeof(bw_data));
11048         bw_data.tc_valid_bits = tc_map;
11049         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11050         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11051                 if (tc_map & BIT_ULL(i))
11052                         bw_data.tc_bw_credits[i] = 1;
11053         }
11054         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11055         if (ret) {
11056                 PMD_INIT_LOG(ERR,
11057                         "AQ command Config VSI BW allocation per TC failed = %d",
11058                         hw->aq.asq_last_status);
11059                 goto out;
11060         }
11061         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11062                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11063
11064         /* Update Queue Pairs Mapping for currently enabled UPs */
11065         ctxt.seid = vsi->seid;
11066         ctxt.pf_num = hw->pf_id;
11067         ctxt.vf_num = 0;
11068         ctxt.uplink_seid = vsi->uplink_seid;
11069         ctxt.info = vsi->info;
11070         i40e_get_cap(hw);
11071         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11072         if (ret)
11073                 goto out;
11074
11075         /* Update the VSI after updating the VSI queue-mapping information */
11076         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11077         if (ret) {
11078                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11079                         hw->aq.asq_last_status);
11080                 goto out;
11081         }
11082         /* update the local VSI info with updated queue map */
11083         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11084                                         sizeof(vsi->info.tc_mapping));
11085         rte_memcpy(&vsi->info.queue_mapping,
11086                         &ctxt.info.queue_mapping,
11087                 sizeof(vsi->info.queue_mapping));
11088         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11089         vsi->info.valid_sections = 0;
11090
11091         /* query and update current VSI BW information */
11092         ret = i40e_vsi_get_bw_config(vsi);
11093         if (ret) {
11094                 PMD_INIT_LOG(ERR,
11095                          "Failed updating vsi bw info, err %s aq_err %s",
11096                          i40e_stat_str(hw, ret),
11097                          i40e_aq_str(hw, hw->aq.asq_last_status));
11098                 goto out;
11099         }
11100
11101         vsi->enabled_tc = tc_map;
11102
11103 out:
11104         return ret;
11105 }
11106
11107 /*
11108  * i40e_dcb_hw_configure - program the dcb setting to hw
11109  * @pf: pf the configuration is taken on
11110  * @new_cfg: new configuration
11111  * @tc_map: enabled TC bitmap
11112  *
11113  * Returns 0 on success, negative value on failure
11114  */
11115 static enum i40e_status_code
11116 i40e_dcb_hw_configure(struct i40e_pf *pf,
11117                       struct i40e_dcbx_config *new_cfg,
11118                       uint8_t tc_map)
11119 {
11120         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11121         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11122         struct i40e_vsi *main_vsi = pf->main_vsi;
11123         struct i40e_vsi_list *vsi_list;
11124         enum i40e_status_code ret;
11125         int i;
11126         uint32_t val;
11127
11128         /* Use the FW API if FW > v4.4*/
11129         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11130               (hw->aq.fw_maj_ver >= 5))) {
11131                 PMD_INIT_LOG(ERR,
11132                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11133                 return I40E_ERR_FIRMWARE_API_VERSION;
11134         }
11135
11136         /* Check if need reconfiguration */
11137         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11138                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11139                 return I40E_SUCCESS;
11140         }
11141
11142         /* Copy the new config to the current config */
11143         *old_cfg = *new_cfg;
11144         old_cfg->etsrec = old_cfg->etscfg;
11145         ret = i40e_set_dcb_config(hw);
11146         if (ret) {
11147                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11148                          i40e_stat_str(hw, ret),
11149                          i40e_aq_str(hw, hw->aq.asq_last_status));
11150                 return ret;
11151         }
11152         /* set receive Arbiter to RR mode and ETS scheme by default */
11153         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11154                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11155                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11156                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11157                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11158                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11159                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11160                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11161                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11162                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11163                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11164                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11165                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11166         }
11167         /* get local mib to check whether it is configured correctly */
11168         /* IEEE mode */
11169         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11170         /* Get Local DCB Config */
11171         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11172                                      &hw->local_dcbx_config);
11173
11174         /* if Veb is created, need to update TC of it at first */
11175         if (main_vsi->veb) {
11176                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11177                 if (ret)
11178                         PMD_INIT_LOG(WARNING,
11179                                  "Failed configuring TC for VEB seid=%d",
11180                                  main_vsi->veb->seid);
11181         }
11182         /* Update each VSI */
11183         i40e_vsi_config_tc(main_vsi, tc_map);
11184         if (main_vsi->veb) {
11185                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11186                         /* Beside main VSI and VMDQ VSIs, only enable default
11187                          * TC for other VSIs
11188                          */
11189                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11190                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11191                                                          tc_map);
11192                         else
11193                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11194                                                          I40E_DEFAULT_TCMAP);
11195                         if (ret)
11196                                 PMD_INIT_LOG(WARNING,
11197                                         "Failed configuring TC for VSI seid=%d",
11198                                         vsi_list->vsi->seid);
11199                         /* continue */
11200                 }
11201         }
11202         return I40E_SUCCESS;
11203 }
11204
11205 /*
11206  * i40e_dcb_init_configure - initial dcb config
11207  * @dev: device being configured
11208  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11209  *
11210  * Returns 0 on success, negative value on failure
11211  */
11212 int
11213 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11214 {
11215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11217         int i, ret = 0;
11218
11219         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11220                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11221                 return -ENOTSUP;
11222         }
11223
11224         /* DCB initialization:
11225          * Update DCB configuration from the Firmware and configure
11226          * LLDP MIB change event.
11227          */
11228         if (sw_dcb == TRUE) {
11229                 /* Stopping lldp is necessary for DPDK, but it will cause
11230                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11231                  * for successful initialization of DCB is that LLDP is
11232                  * enabled. So it is needed to start lldp before DCB init
11233                  * and stop it after initialization.
11234                  */
11235                 ret = i40e_aq_start_lldp(hw, true, NULL);
11236                 if (ret != I40E_SUCCESS)
11237                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11238
11239                 ret = i40e_init_dcb(hw, true);
11240                 /* If lldp agent is stopped, the return value from
11241                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11242                  * adminq status. Otherwise, it should return success.
11243                  */
11244                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11245                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11246                         memset(&hw->local_dcbx_config, 0,
11247                                 sizeof(struct i40e_dcbx_config));
11248                         /* set dcb default configuration */
11249                         hw->local_dcbx_config.etscfg.willing = 0;
11250                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11251                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11252                         hw->local_dcbx_config.etscfg.tsatable[0] =
11253                                                 I40E_IEEE_TSA_ETS;
11254                         /* all UPs mapping to TC0 */
11255                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11256                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11257                         hw->local_dcbx_config.etsrec =
11258                                 hw->local_dcbx_config.etscfg;
11259                         hw->local_dcbx_config.pfc.willing = 0;
11260                         hw->local_dcbx_config.pfc.pfccap =
11261                                                 I40E_MAX_TRAFFIC_CLASS;
11262                         /* FW needs one App to configure HW */
11263                         hw->local_dcbx_config.numapps = 1;
11264                         hw->local_dcbx_config.app[0].selector =
11265                                                 I40E_APP_SEL_ETHTYPE;
11266                         hw->local_dcbx_config.app[0].priority = 3;
11267                         hw->local_dcbx_config.app[0].protocolid =
11268                                                 I40E_APP_PROTOID_FCOE;
11269                         ret = i40e_set_dcb_config(hw);
11270                         if (ret) {
11271                                 PMD_INIT_LOG(ERR,
11272                                         "default dcb config fails. err = %d, aq_err = %d.",
11273                                         ret, hw->aq.asq_last_status);
11274                                 return -ENOSYS;
11275                         }
11276                 } else {
11277                         PMD_INIT_LOG(ERR,
11278                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11279                                 ret, hw->aq.asq_last_status);
11280                         return -ENOTSUP;
11281                 }
11282
11283                 if (i40e_need_stop_lldp(dev)) {
11284                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11285                         if (ret != I40E_SUCCESS)
11286                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11287                 }
11288         } else {
11289                 ret = i40e_aq_start_lldp(hw, true, NULL);
11290                 if (ret != I40E_SUCCESS)
11291                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11292
11293                 ret = i40e_init_dcb(hw, true);
11294                 if (!ret) {
11295                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11296                                 PMD_INIT_LOG(ERR,
11297                                         "HW doesn't support DCBX offload.");
11298                                 return -ENOTSUP;
11299                         }
11300                 } else {
11301                         PMD_INIT_LOG(ERR,
11302                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11303                                 ret, hw->aq.asq_last_status);
11304                         return -ENOTSUP;
11305                 }
11306         }
11307         return 0;
11308 }
11309
11310 /*
11311  * i40e_dcb_setup - setup dcb related config
11312  * @dev: device being configured
11313  *
11314  * Returns 0 on success, negative value on failure
11315  */
11316 static int
11317 i40e_dcb_setup(struct rte_eth_dev *dev)
11318 {
11319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11320         struct i40e_dcbx_config dcb_cfg;
11321         uint8_t tc_map = 0;
11322         int ret = 0;
11323
11324         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11325                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11326                 return -ENOTSUP;
11327         }
11328
11329         if (pf->vf_num != 0)
11330                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11331
11332         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11333         if (ret) {
11334                 PMD_INIT_LOG(ERR, "invalid dcb config");
11335                 return -EINVAL;
11336         }
11337         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11338         if (ret) {
11339                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11340                 return -ENOSYS;
11341         }
11342
11343         return 0;
11344 }
11345
11346 static int
11347 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11348                       struct rte_eth_dcb_info *dcb_info)
11349 {
11350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11351         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11352         struct i40e_vsi *vsi = pf->main_vsi;
11353         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11354         uint16_t bsf, tc_mapping;
11355         int i, j = 0;
11356
11357         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11358                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11359         else
11360                 dcb_info->nb_tcs = 1;
11361         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11362                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11363         for (i = 0; i < dcb_info->nb_tcs; i++)
11364                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11365
11366         /* get queue mapping if vmdq is disabled */
11367         if (!pf->nb_cfg_vmdq_vsi) {
11368                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11369                         if (!(vsi->enabled_tc & (1 << i)))
11370                                 continue;
11371                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11372                         dcb_info->tc_queue.tc_rxq[j][i].base =
11373                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11374                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11375                         dcb_info->tc_queue.tc_txq[j][i].base =
11376                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11377                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11378                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11379                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11380                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11381                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11382                 }
11383                 return 0;
11384         }
11385
11386         /* get queue mapping if vmdq is enabled */
11387         do {
11388                 vsi = pf->vmdq[j].vsi;
11389                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11390                         if (!(vsi->enabled_tc & (1 << i)))
11391                                 continue;
11392                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11393                         dcb_info->tc_queue.tc_rxq[j][i].base =
11394                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11395                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11396                         dcb_info->tc_queue.tc_txq[j][i].base =
11397                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11398                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11399                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11400                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11401                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11402                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11403                 }
11404                 j++;
11405         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11406         return 0;
11407 }
11408
11409 static int
11410 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11411 {
11412         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11413         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11414         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11415         uint16_t msix_intr;
11416
11417         msix_intr = intr_handle->intr_vec[queue_id];
11418         if (msix_intr == I40E_MISC_VEC_ID)
11419                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11420                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11421                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11422                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11423         else
11424                 I40E_WRITE_REG(hw,
11425                                I40E_PFINT_DYN_CTLN(msix_intr -
11426                                                    I40E_RX_VEC_START),
11427                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11428                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11429                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11430
11431         I40E_WRITE_FLUSH(hw);
11432         rte_intr_ack(&pci_dev->intr_handle);
11433
11434         return 0;
11435 }
11436
11437 static int
11438 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11439 {
11440         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11441         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11442         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11443         uint16_t msix_intr;
11444
11445         msix_intr = intr_handle->intr_vec[queue_id];
11446         if (msix_intr == I40E_MISC_VEC_ID)
11447                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11448                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11449         else
11450                 I40E_WRITE_REG(hw,
11451                                I40E_PFINT_DYN_CTLN(msix_intr -
11452                                                    I40E_RX_VEC_START),
11453                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11454         I40E_WRITE_FLUSH(hw);
11455
11456         return 0;
11457 }
11458
11459 /**
11460  * This function is used to check if the register is valid.
11461  * Below is the valid registers list for X722 only:
11462  * 0x2b800--0x2bb00
11463  * 0x38700--0x38a00
11464  * 0x3d800--0x3db00
11465  * 0x208e00--0x209000
11466  * 0x20be00--0x20c000
11467  * 0x263c00--0x264000
11468  * 0x265c00--0x266000
11469  */
11470 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11471 {
11472         if ((type != I40E_MAC_X722) &&
11473             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11474              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11475              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11476              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11477              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11478              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11479              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11480                 return 0;
11481         else
11482                 return 1;
11483 }
11484
11485 static int i40e_get_regs(struct rte_eth_dev *dev,
11486                          struct rte_dev_reg_info *regs)
11487 {
11488         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11489         uint32_t *ptr_data = regs->data;
11490         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11491         const struct i40e_reg_info *reg_info;
11492
11493         if (ptr_data == NULL) {
11494                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11495                 regs->width = sizeof(uint32_t);
11496                 return 0;
11497         }
11498
11499         /* The first few registers have to be read using AQ operations */
11500         reg_idx = 0;
11501         while (i40e_regs_adminq[reg_idx].name) {
11502                 reg_info = &i40e_regs_adminq[reg_idx++];
11503                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11504                         for (arr_idx2 = 0;
11505                                         arr_idx2 <= reg_info->count2;
11506                                         arr_idx2++) {
11507                                 reg_offset = arr_idx * reg_info->stride1 +
11508                                         arr_idx2 * reg_info->stride2;
11509                                 reg_offset += reg_info->base_addr;
11510                                 ptr_data[reg_offset >> 2] =
11511                                         i40e_read_rx_ctl(hw, reg_offset);
11512                         }
11513         }
11514
11515         /* The remaining registers can be read using primitives */
11516         reg_idx = 0;
11517         while (i40e_regs_others[reg_idx].name) {
11518                 reg_info = &i40e_regs_others[reg_idx++];
11519                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11520                         for (arr_idx2 = 0;
11521                                         arr_idx2 <= reg_info->count2;
11522                                         arr_idx2++) {
11523                                 reg_offset = arr_idx * reg_info->stride1 +
11524                                         arr_idx2 * reg_info->stride2;
11525                                 reg_offset += reg_info->base_addr;
11526                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11527                                         ptr_data[reg_offset >> 2] = 0;
11528                                 else
11529                                         ptr_data[reg_offset >> 2] =
11530                                                 I40E_READ_REG(hw, reg_offset);
11531                         }
11532         }
11533
11534         return 0;
11535 }
11536
11537 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11538 {
11539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11540
11541         /* Convert word count to byte count */
11542         return hw->nvm.sr_size << 1;
11543 }
11544
11545 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11546                            struct rte_dev_eeprom_info *eeprom)
11547 {
11548         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11549         uint16_t *data = eeprom->data;
11550         uint16_t offset, length, cnt_words;
11551         int ret_code;
11552
11553         offset = eeprom->offset >> 1;
11554         length = eeprom->length >> 1;
11555         cnt_words = length;
11556
11557         if (offset > hw->nvm.sr_size ||
11558                 offset + length > hw->nvm.sr_size) {
11559                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11560                 return -EINVAL;
11561         }
11562
11563         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11564
11565         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11566         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11567                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11568                 return -EIO;
11569         }
11570
11571         return 0;
11572 }
11573
11574 static int i40e_get_module_info(struct rte_eth_dev *dev,
11575                                 struct rte_eth_dev_module_info *modinfo)
11576 {
11577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11578         uint32_t sff8472_comp = 0;
11579         uint32_t sff8472_swap = 0;
11580         uint32_t sff8636_rev = 0;
11581         i40e_status status;
11582         uint32_t type = 0;
11583
11584         /* Check if firmware supports reading module EEPROM. */
11585         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11586                 PMD_DRV_LOG(ERR,
11587                             "Module EEPROM memory read not supported. "
11588                             "Please update the NVM image.\n");
11589                 return -EINVAL;
11590         }
11591
11592         status = i40e_update_link_info(hw);
11593         if (status)
11594                 return -EIO;
11595
11596         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11597                 PMD_DRV_LOG(ERR,
11598                             "Cannot read module EEPROM memory. "
11599                             "No module connected.\n");
11600                 return -EINVAL;
11601         }
11602
11603         type = hw->phy.link_info.module_type[0];
11604
11605         switch (type) {
11606         case I40E_MODULE_TYPE_SFP:
11607                 status = i40e_aq_get_phy_register(hw,
11608                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11609                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11610                                 I40E_MODULE_SFF_8472_COMP,
11611                                 &sff8472_comp, NULL);
11612                 if (status)
11613                         return -EIO;
11614
11615                 status = i40e_aq_get_phy_register(hw,
11616                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11617                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11618                                 I40E_MODULE_SFF_8472_SWAP,
11619                                 &sff8472_swap, NULL);
11620                 if (status)
11621                         return -EIO;
11622
11623                 /* Check if the module requires address swap to access
11624                  * the other EEPROM memory page.
11625                  */
11626                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11627                         PMD_DRV_LOG(WARNING,
11628                                     "Module address swap to access "
11629                                     "page 0xA2 is not supported.\n");
11630                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11631                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11632                 } else if (sff8472_comp == 0x00) {
11633                         /* Module is not SFF-8472 compliant */
11634                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11635                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11636                 } else {
11637                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11638                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11639                 }
11640                 break;
11641         case I40E_MODULE_TYPE_QSFP_PLUS:
11642                 /* Read from memory page 0. */
11643                 status = i40e_aq_get_phy_register(hw,
11644                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11645                                 0, 1,
11646                                 I40E_MODULE_REVISION_ADDR,
11647                                 &sff8636_rev, NULL);
11648                 if (status)
11649                         return -EIO;
11650                 /* Determine revision compliance byte */
11651                 if (sff8636_rev > 0x02) {
11652                         /* Module is SFF-8636 compliant */
11653                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11654                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11655                 } else {
11656                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11657                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11658                 }
11659                 break;
11660         case I40E_MODULE_TYPE_QSFP28:
11661                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11662                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11663                 break;
11664         default:
11665                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11666                 return -EINVAL;
11667         }
11668         return 0;
11669 }
11670
11671 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11672                                   struct rte_dev_eeprom_info *info)
11673 {
11674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11675         bool is_sfp = false;
11676         i40e_status status;
11677         uint8_t *data;
11678         uint32_t value = 0;
11679         uint32_t i;
11680
11681         if (!info || !info->length || !info->data)
11682                 return -EINVAL;
11683
11684         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11685                 is_sfp = true;
11686
11687         data = info->data;
11688         for (i = 0; i < info->length; i++) {
11689                 u32 offset = i + info->offset;
11690                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11691
11692                 /* Check if we need to access the other memory page */
11693                 if (is_sfp) {
11694                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11695                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11696                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11697                         }
11698                 } else {
11699                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11700                                 /* Compute memory page number and offset. */
11701                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11702                                 addr++;
11703                         }
11704                 }
11705                 status = i40e_aq_get_phy_register(hw,
11706                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11707                                 addr, 1, offset, &value, NULL);
11708                 if (status)
11709                         return -EIO;
11710                 data[i] = (uint8_t)value;
11711         }
11712         return 0;
11713 }
11714
11715 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11716                                      struct rte_ether_addr *mac_addr)
11717 {
11718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11720         struct i40e_vsi *vsi = pf->main_vsi;
11721         struct i40e_mac_filter_info mac_filter;
11722         struct i40e_mac_filter *f;
11723         int ret;
11724
11725         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11726                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11727                 return -EINVAL;
11728         }
11729
11730         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11731                 if (rte_is_same_ether_addr(&pf->dev_addr,
11732                                                 &f->mac_info.mac_addr))
11733                         break;
11734         }
11735
11736         if (f == NULL) {
11737                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11738                 return -EIO;
11739         }
11740
11741         mac_filter = f->mac_info;
11742         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11743         if (ret != I40E_SUCCESS) {
11744                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11745                 return -EIO;
11746         }
11747         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11748         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11749         if (ret != I40E_SUCCESS) {
11750                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11751                 return -EIO;
11752         }
11753         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11754
11755         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11756                                         mac_addr->addr_bytes, NULL);
11757         if (ret != I40E_SUCCESS) {
11758                 PMD_DRV_LOG(ERR, "Failed to change mac");
11759                 return -EIO;
11760         }
11761
11762         return 0;
11763 }
11764
11765 static int
11766 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11767 {
11768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11769         struct rte_eth_dev_data *dev_data = pf->dev_data;
11770         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11771         int ret = 0;
11772
11773         /* check if mtu is within the allowed range */
11774         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11775                 return -EINVAL;
11776
11777         /* mtu setting is forbidden if port is start */
11778         if (dev_data->dev_started) {
11779                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11780                             dev_data->port_id);
11781                 return -EBUSY;
11782         }
11783
11784         if (frame_size > RTE_ETHER_MAX_LEN)
11785                 dev_data->dev_conf.rxmode.offloads |=
11786                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11787         else
11788                 dev_data->dev_conf.rxmode.offloads &=
11789                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11790
11791         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11792
11793         return ret;
11794 }
11795
11796 /* Restore ethertype filter */
11797 static void
11798 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11799 {
11800         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11801         struct i40e_ethertype_filter_list
11802                 *ethertype_list = &pf->ethertype.ethertype_list;
11803         struct i40e_ethertype_filter *f;
11804         struct i40e_control_filter_stats stats;
11805         uint16_t flags;
11806
11807         TAILQ_FOREACH(f, ethertype_list, rules) {
11808                 flags = 0;
11809                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11810                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11811                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11812                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11813                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11814
11815                 memset(&stats, 0, sizeof(stats));
11816                 i40e_aq_add_rem_control_packet_filter(hw,
11817                                             f->input.mac_addr.addr_bytes,
11818                                             f->input.ether_type,
11819                                             flags, pf->main_vsi->seid,
11820                                             f->queue, 1, &stats, NULL);
11821         }
11822         PMD_DRV_LOG(INFO, "Ethertype filter:"
11823                     " mac_etype_used = %u, etype_used = %u,"
11824                     " mac_etype_free = %u, etype_free = %u",
11825                     stats.mac_etype_used, stats.etype_used,
11826                     stats.mac_etype_free, stats.etype_free);
11827 }
11828
11829 /* Restore tunnel filter */
11830 static void
11831 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11832 {
11833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11834         struct i40e_vsi *vsi;
11835         struct i40e_pf_vf *vf;
11836         struct i40e_tunnel_filter_list
11837                 *tunnel_list = &pf->tunnel.tunnel_list;
11838         struct i40e_tunnel_filter *f;
11839         struct i40e_aqc_cloud_filters_element_bb cld_filter;
11840         bool big_buffer = 0;
11841
11842         TAILQ_FOREACH(f, tunnel_list, rules) {
11843                 if (!f->is_to_vf)
11844                         vsi = pf->main_vsi;
11845                 else {
11846                         vf = &pf->vfs[f->vf_id];
11847                         vsi = vf->vsi;
11848                 }
11849                 memset(&cld_filter, 0, sizeof(cld_filter));
11850                 rte_ether_addr_copy((struct rte_ether_addr *)
11851                                 &f->input.outer_mac,
11852                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11853                 rte_ether_addr_copy((struct rte_ether_addr *)
11854                                 &f->input.inner_mac,
11855                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11856                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11857                 cld_filter.element.flags = f->input.flags;
11858                 cld_filter.element.tenant_id = f->input.tenant_id;
11859                 cld_filter.element.queue_number = f->queue;
11860                 rte_memcpy(cld_filter.general_fields,
11861                            f->input.general_fields,
11862                            sizeof(f->input.general_fields));
11863
11864                 if (((f->input.flags &
11865                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11866                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11867                     ((f->input.flags &
11868                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11869                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11870                     ((f->input.flags &
11871                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11872                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11873                         big_buffer = 1;
11874
11875                 if (big_buffer)
11876                         i40e_aq_add_cloud_filters_bb(hw,
11877                                         vsi->seid, &cld_filter, 1);
11878                 else
11879                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11880                                                   &cld_filter.element, 1);
11881         }
11882 }
11883
11884 /* Restore RSS filter */
11885 static inline void
11886 i40e_rss_filter_restore(struct i40e_pf *pf)
11887 {
11888         struct i40e_rss_conf_list *list = &pf->rss_config_list;
11889         struct i40e_rss_filter *filter;
11890
11891         TAILQ_FOREACH(filter, list, next) {
11892                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
11893         }
11894 }
11895
11896 static void
11897 i40e_filter_restore(struct i40e_pf *pf)
11898 {
11899         i40e_ethertype_filter_restore(pf);
11900         i40e_tunnel_filter_restore(pf);
11901         i40e_fdir_filter_restore(pf);
11902         i40e_rss_filter_restore(pf);
11903 }
11904
11905 bool
11906 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11907 {
11908         if (strcmp(dev->device->driver->name, drv->driver.name))
11909                 return false;
11910
11911         return true;
11912 }
11913
11914 bool
11915 is_i40e_supported(struct rte_eth_dev *dev)
11916 {
11917         return is_device_supported(dev, &rte_i40e_pmd);
11918 }
11919
11920 struct i40e_customized_pctype*
11921 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11922 {
11923         int i;
11924
11925         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11926                 if (pf->customized_pctype[i].index == index)
11927                         return &pf->customized_pctype[i];
11928         }
11929         return NULL;
11930 }
11931
11932 static int
11933 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11934                               uint32_t pkg_size, uint32_t proto_num,
11935                               struct rte_pmd_i40e_proto_info *proto,
11936                               enum rte_pmd_i40e_package_op op)
11937 {
11938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11939         uint32_t pctype_num;
11940         struct rte_pmd_i40e_ptype_info *pctype;
11941         uint32_t buff_size;
11942         struct i40e_customized_pctype *new_pctype = NULL;
11943         uint8_t proto_id;
11944         uint8_t pctype_value;
11945         char name[64];
11946         uint32_t i, j, n;
11947         int ret;
11948
11949         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11950             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11951                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11952                 return -1;
11953         }
11954
11955         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11956                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11957                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11958         if (ret) {
11959                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11960                 return -1;
11961         }
11962         if (!pctype_num) {
11963                 PMD_DRV_LOG(INFO, "No new pctype added");
11964                 return -1;
11965         }
11966
11967         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11968         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11969         if (!pctype) {
11970                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11971                 return -1;
11972         }
11973         /* get information about new pctype list */
11974         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11975                                         (uint8_t *)pctype, buff_size,
11976                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11977         if (ret) {
11978                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11979                 rte_free(pctype);
11980                 return -1;
11981         }
11982
11983         /* Update customized pctype. */
11984         for (i = 0; i < pctype_num; i++) {
11985                 pctype_value = pctype[i].ptype_id;
11986                 memset(name, 0, sizeof(name));
11987                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11988                         proto_id = pctype[i].protocols[j];
11989                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11990                                 continue;
11991                         for (n = 0; n < proto_num; n++) {
11992                                 if (proto[n].proto_id != proto_id)
11993                                         continue;
11994                                 strlcat(name, proto[n].name, sizeof(name));
11995                                 strlcat(name, "_", sizeof(name));
11996                                 break;
11997                         }
11998                 }
11999                 name[strlen(name) - 1] = '\0';
12000                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12001                 if (!strcmp(name, "GTPC"))
12002                         new_pctype =
12003                                 i40e_find_customized_pctype(pf,
12004                                                       I40E_CUSTOMIZED_GTPC);
12005                 else if (!strcmp(name, "GTPU_IPV4"))
12006                         new_pctype =
12007                                 i40e_find_customized_pctype(pf,
12008                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12009                 else if (!strcmp(name, "GTPU_IPV6"))
12010                         new_pctype =
12011                                 i40e_find_customized_pctype(pf,
12012                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12013                 else if (!strcmp(name, "GTPU"))
12014                         new_pctype =
12015                                 i40e_find_customized_pctype(pf,
12016                                                       I40E_CUSTOMIZED_GTPU);
12017                 else if (!strcmp(name, "IPV4_L2TPV3"))
12018                         new_pctype =
12019                                 i40e_find_customized_pctype(pf,
12020                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12021                 else if (!strcmp(name, "IPV6_L2TPV3"))
12022                         new_pctype =
12023                                 i40e_find_customized_pctype(pf,
12024                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12025                 else if (!strcmp(name, "IPV4_ESP"))
12026                         new_pctype =
12027                                 i40e_find_customized_pctype(pf,
12028                                                 I40E_CUSTOMIZED_ESP_IPV4);
12029                 else if (!strcmp(name, "IPV6_ESP"))
12030                         new_pctype =
12031                                 i40e_find_customized_pctype(pf,
12032                                                 I40E_CUSTOMIZED_ESP_IPV6);
12033                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12034                         new_pctype =
12035                                 i40e_find_customized_pctype(pf,
12036                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12037                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12038                         new_pctype =
12039                                 i40e_find_customized_pctype(pf,
12040                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12041                 else if (!strcmp(name, "IPV4_AH"))
12042                         new_pctype =
12043                                 i40e_find_customized_pctype(pf,
12044                                                 I40E_CUSTOMIZED_AH_IPV4);
12045                 else if (!strcmp(name, "IPV6_AH"))
12046                         new_pctype =
12047                                 i40e_find_customized_pctype(pf,
12048                                                 I40E_CUSTOMIZED_AH_IPV6);
12049                 if (new_pctype) {
12050                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12051                                 new_pctype->pctype = pctype_value;
12052                                 new_pctype->valid = true;
12053                         } else {
12054                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12055                                 new_pctype->valid = false;
12056                         }
12057                 }
12058         }
12059
12060         rte_free(pctype);
12061         return 0;
12062 }
12063
12064 static int
12065 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12066                              uint32_t pkg_size, uint32_t proto_num,
12067                              struct rte_pmd_i40e_proto_info *proto,
12068                              enum rte_pmd_i40e_package_op op)
12069 {
12070         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12071         uint16_t port_id = dev->data->port_id;
12072         uint32_t ptype_num;
12073         struct rte_pmd_i40e_ptype_info *ptype;
12074         uint32_t buff_size;
12075         uint8_t proto_id;
12076         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12077         uint32_t i, j, n;
12078         bool in_tunnel;
12079         int ret;
12080
12081         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12082             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12083                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12084                 return -1;
12085         }
12086
12087         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12088                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12089                 return 0;
12090         }
12091
12092         /* get information about new ptype num */
12093         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12094                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12095                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12096         if (ret) {
12097                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12098                 return ret;
12099         }
12100         if (!ptype_num) {
12101                 PMD_DRV_LOG(INFO, "No new ptype added");
12102                 return -1;
12103         }
12104
12105         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12106         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12107         if (!ptype) {
12108                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12109                 return -1;
12110         }
12111
12112         /* get information about new ptype list */
12113         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12114                                         (uint8_t *)ptype, buff_size,
12115                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12116         if (ret) {
12117                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12118                 rte_free(ptype);
12119                 return ret;
12120         }
12121
12122         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12123         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12124         if (!ptype_mapping) {
12125                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12126                 rte_free(ptype);
12127                 return -1;
12128         }
12129
12130         /* Update ptype mapping table. */
12131         for (i = 0; i < ptype_num; i++) {
12132                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12133                 ptype_mapping[i].sw_ptype = 0;
12134                 in_tunnel = false;
12135                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12136                         proto_id = ptype[i].protocols[j];
12137                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12138                                 continue;
12139                         for (n = 0; n < proto_num; n++) {
12140                                 if (proto[n].proto_id != proto_id)
12141                                         continue;
12142                                 memset(name, 0, sizeof(name));
12143                                 strcpy(name, proto[n].name);
12144                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12145                                 if (!strncasecmp(name, "PPPOE", 5))
12146                                         ptype_mapping[i].sw_ptype |=
12147                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12148                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12149                                          !in_tunnel) {
12150                                         ptype_mapping[i].sw_ptype |=
12151                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12152                                         ptype_mapping[i].sw_ptype |=
12153                                                 RTE_PTYPE_L4_FRAG;
12154                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12155                                            in_tunnel) {
12156                                         ptype_mapping[i].sw_ptype |=
12157                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12158                                         ptype_mapping[i].sw_ptype |=
12159                                                 RTE_PTYPE_INNER_L4_FRAG;
12160                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12161                                         ptype_mapping[i].sw_ptype |=
12162                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12163                                         in_tunnel = true;
12164                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12165                                            !in_tunnel)
12166                                         ptype_mapping[i].sw_ptype |=
12167                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12168                                 else if (!strncasecmp(name, "IPV4", 4) &&
12169                                          in_tunnel)
12170                                         ptype_mapping[i].sw_ptype |=
12171                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12172                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12173                                          !in_tunnel) {
12174                                         ptype_mapping[i].sw_ptype |=
12175                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12176                                         ptype_mapping[i].sw_ptype |=
12177                                                 RTE_PTYPE_L4_FRAG;
12178                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12179                                            in_tunnel) {
12180                                         ptype_mapping[i].sw_ptype |=
12181                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12182                                         ptype_mapping[i].sw_ptype |=
12183                                                 RTE_PTYPE_INNER_L4_FRAG;
12184                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12185                                         ptype_mapping[i].sw_ptype |=
12186                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12187                                         in_tunnel = true;
12188                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12189                                            !in_tunnel)
12190                                         ptype_mapping[i].sw_ptype |=
12191                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12192                                 else if (!strncasecmp(name, "IPV6", 4) &&
12193                                          in_tunnel)
12194                                         ptype_mapping[i].sw_ptype |=
12195                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12196                                 else if (!strncasecmp(name, "UDP", 3) &&
12197                                          !in_tunnel)
12198                                         ptype_mapping[i].sw_ptype |=
12199                                                 RTE_PTYPE_L4_UDP;
12200                                 else if (!strncasecmp(name, "UDP", 3) &&
12201                                          in_tunnel)
12202                                         ptype_mapping[i].sw_ptype |=
12203                                                 RTE_PTYPE_INNER_L4_UDP;
12204                                 else if (!strncasecmp(name, "TCP", 3) &&
12205                                          !in_tunnel)
12206                                         ptype_mapping[i].sw_ptype |=
12207                                                 RTE_PTYPE_L4_TCP;
12208                                 else if (!strncasecmp(name, "TCP", 3) &&
12209                                          in_tunnel)
12210                                         ptype_mapping[i].sw_ptype |=
12211                                                 RTE_PTYPE_INNER_L4_TCP;
12212                                 else if (!strncasecmp(name, "SCTP", 4) &&
12213                                          !in_tunnel)
12214                                         ptype_mapping[i].sw_ptype |=
12215                                                 RTE_PTYPE_L4_SCTP;
12216                                 else if (!strncasecmp(name, "SCTP", 4) &&
12217                                          in_tunnel)
12218                                         ptype_mapping[i].sw_ptype |=
12219                                                 RTE_PTYPE_INNER_L4_SCTP;
12220                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12221                                           !strncasecmp(name, "ICMPV6", 6)) &&
12222                                          !in_tunnel)
12223                                         ptype_mapping[i].sw_ptype |=
12224                                                 RTE_PTYPE_L4_ICMP;
12225                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12226                                           !strncasecmp(name, "ICMPV6", 6)) &&
12227                                          in_tunnel)
12228                                         ptype_mapping[i].sw_ptype |=
12229                                                 RTE_PTYPE_INNER_L4_ICMP;
12230                                 else if (!strncasecmp(name, "GTPC", 4)) {
12231                                         ptype_mapping[i].sw_ptype |=
12232                                                 RTE_PTYPE_TUNNEL_GTPC;
12233                                         in_tunnel = true;
12234                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12235                                         ptype_mapping[i].sw_ptype |=
12236                                                 RTE_PTYPE_TUNNEL_GTPU;
12237                                         in_tunnel = true;
12238                                 } else if (!strncasecmp(name, "ESP", 3)) {
12239                                         ptype_mapping[i].sw_ptype |=
12240                                                 RTE_PTYPE_TUNNEL_ESP;
12241                                         in_tunnel = true;
12242                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12243                                         ptype_mapping[i].sw_ptype |=
12244                                                 RTE_PTYPE_TUNNEL_GRENAT;
12245                                         in_tunnel = true;
12246                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12247                                            !strncasecmp(name, "L2TPV2", 6) ||
12248                                            !strncasecmp(name, "L2TPV3", 6)) {
12249                                         ptype_mapping[i].sw_ptype |=
12250                                                 RTE_PTYPE_TUNNEL_L2TP;
12251                                         in_tunnel = true;
12252                                 }
12253
12254                                 break;
12255                         }
12256                 }
12257         }
12258
12259         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12260                                                 ptype_num, 0);
12261         if (ret)
12262                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12263
12264         rte_free(ptype_mapping);
12265         rte_free(ptype);
12266         return ret;
12267 }
12268
12269 void
12270 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12271                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12272 {
12273         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12274         uint32_t proto_num;
12275         struct rte_pmd_i40e_proto_info *proto;
12276         uint32_t buff_size;
12277         uint32_t i;
12278         int ret;
12279
12280         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12281             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12282                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12283                 return;
12284         }
12285
12286         /* get information about protocol number */
12287         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12288                                        (uint8_t *)&proto_num, sizeof(proto_num),
12289                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12290         if (ret) {
12291                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12292                 return;
12293         }
12294         if (!proto_num) {
12295                 PMD_DRV_LOG(INFO, "No new protocol added");
12296                 return;
12297         }
12298
12299         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12300         proto = rte_zmalloc("new_proto", buff_size, 0);
12301         if (!proto) {
12302                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12303                 return;
12304         }
12305
12306         /* get information about protocol list */
12307         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12308                                         (uint8_t *)proto, buff_size,
12309                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12310         if (ret) {
12311                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12312                 rte_free(proto);
12313                 return;
12314         }
12315
12316         /* Check if GTP is supported. */
12317         for (i = 0; i < proto_num; i++) {
12318                 if (!strncmp(proto[i].name, "GTP", 3)) {
12319                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12320                                 pf->gtp_support = true;
12321                         else
12322                                 pf->gtp_support = false;
12323                         break;
12324                 }
12325         }
12326
12327         /* Check if ESP is supported. */
12328         for (i = 0; i < proto_num; i++) {
12329                 if (!strncmp(proto[i].name, "ESP", 3)) {
12330                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12331                                 pf->esp_support = true;
12332                         else
12333                                 pf->esp_support = false;
12334                         break;
12335                 }
12336         }
12337
12338         /* Update customized pctype info */
12339         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12340                                             proto_num, proto, op);
12341         if (ret)
12342                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12343
12344         /* Update customized ptype info */
12345         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12346                                            proto_num, proto, op);
12347         if (ret)
12348                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12349
12350         rte_free(proto);
12351 }
12352
12353 /* Create a QinQ cloud filter
12354  *
12355  * The Fortville NIC has limited resources for tunnel filters,
12356  * so we can only reuse existing filters.
12357  *
12358  * In step 1 we define which Field Vector fields can be used for
12359  * filter types.
12360  * As we do not have the inner tag defined as a field,
12361  * we have to define it first, by reusing one of L1 entries.
12362  *
12363  * In step 2 we are replacing one of existing filter types with
12364  * a new one for QinQ.
12365  * As we reusing L1 and replacing L2, some of the default filter
12366  * types will disappear,which depends on L1 and L2 entries we reuse.
12367  *
12368  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12369  *
12370  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12371  *              later when we define the cloud filter.
12372  *      a.      Valid_flags.replace_cloud = 0
12373  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12374  *      c.      New_filter = 0x10
12375  *      d.      TR bit = 0xff (optional, not used here)
12376  *      e.      Buffer – 2 entries:
12377  *              i.      Byte 0 = 8 (outer vlan FV index).
12378  *                      Byte 1 = 0 (rsv)
12379  *                      Byte 2-3 = 0x0fff
12380  *              ii.     Byte 0 = 37 (inner vlan FV index).
12381  *                      Byte 1 =0 (rsv)
12382  *                      Byte 2-3 = 0x0fff
12383  *
12384  * Step 2:
12385  * 2.   Create cloud filter using two L1 filters entries: stag and
12386  *              new filter(outer vlan+ inner vlan)
12387  *      a.      Valid_flags.replace_cloud = 1
12388  *      b.      Old_filter = 1 (instead of outer IP)
12389  *      c.      New_filter = 0x10
12390  *      d.      Buffer – 2 entries:
12391  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12392  *                      Byte 1-3 = 0 (rsv)
12393  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12394  *                      Byte 9-11 = 0 (rsv)
12395  */
12396 static int
12397 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12398 {
12399         int ret = -ENOTSUP;
12400         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12401         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12402         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12403         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12404
12405         if (pf->support_multi_driver) {
12406                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12407                 return ret;
12408         }
12409
12410         /* Init */
12411         memset(&filter_replace, 0,
12412                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12413         memset(&filter_replace_buf, 0,
12414                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12415
12416         /* create L1 filter */
12417         filter_replace.old_filter_type =
12418                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12419         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12420         filter_replace.tr_bit = 0;
12421
12422         /* Prepare the buffer, 2 entries */
12423         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12424         filter_replace_buf.data[0] |=
12425                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12426         /* Field Vector 12b mask */
12427         filter_replace_buf.data[2] = 0xff;
12428         filter_replace_buf.data[3] = 0x0f;
12429         filter_replace_buf.data[4] =
12430                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12431         filter_replace_buf.data[4] |=
12432                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12433         /* Field Vector 12b mask */
12434         filter_replace_buf.data[6] = 0xff;
12435         filter_replace_buf.data[7] = 0x0f;
12436         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12437                         &filter_replace_buf);
12438         if (ret != I40E_SUCCESS)
12439                 return ret;
12440
12441         if (filter_replace.old_filter_type !=
12442             filter_replace.new_filter_type)
12443                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12444                             " original: 0x%x, new: 0x%x",
12445                             dev->device->name,
12446                             filter_replace.old_filter_type,
12447                             filter_replace.new_filter_type);
12448
12449         /* Apply the second L2 cloud filter */
12450         memset(&filter_replace, 0,
12451                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12452         memset(&filter_replace_buf, 0,
12453                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12454
12455         /* create L2 filter, input for L2 filter will be L1 filter  */
12456         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12457         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12458         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12459
12460         /* Prepare the buffer, 2 entries */
12461         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12462         filter_replace_buf.data[0] |=
12463                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12464         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12465         filter_replace_buf.data[4] |=
12466                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12467         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12468                         &filter_replace_buf);
12469         if (!ret && (filter_replace.old_filter_type !=
12470                      filter_replace.new_filter_type))
12471                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12472                             " original: 0x%x, new: 0x%x",
12473                             dev->device->name,
12474                             filter_replace.old_filter_type,
12475                             filter_replace.new_filter_type);
12476
12477         return ret;
12478 }
12479
12480 int
12481 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12482                    const struct rte_flow_action_rss *in)
12483 {
12484         if (in->key_len > RTE_DIM(out->key) ||
12485             in->queue_num > RTE_DIM(out->queue))
12486                 return -EINVAL;
12487         if (!in->key && in->key_len)
12488                 return -EINVAL;
12489         out->conf = (struct rte_flow_action_rss){
12490                 .func = in->func,
12491                 .level = in->level,
12492                 .types = in->types,
12493                 .key_len = in->key_len,
12494                 .queue_num = in->queue_num,
12495                 .queue = memcpy(out->queue, in->queue,
12496                                 sizeof(*in->queue) * in->queue_num),
12497         };
12498         if (in->key)
12499                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12500         return 0;
12501 }
12502
12503 /* Write HENA register to enable hash */
12504 static int
12505 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
12506 {
12507         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12508         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
12509         uint64_t hena;
12510         int ret;
12511
12512         ret = i40e_set_rss_key(pf->main_vsi, key,
12513                                rss_conf->conf.key_len);
12514         if (ret)
12515                 return ret;
12516
12517         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
12518         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
12519         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
12520         I40E_WRITE_FLUSH(hw);
12521
12522         return 0;
12523 }
12524
12525 /* Configure hash input set */
12526 static int
12527 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
12528 {
12529         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12530         struct rte_eth_input_set_conf conf;
12531         uint64_t mask0;
12532         int ret = 0;
12533         uint32_t j;
12534         int i;
12535         static const struct {
12536                 uint64_t type;
12537                 enum rte_eth_input_set_field field;
12538         } inset_match_table[] = {
12539                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
12540                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12541                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
12542                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12543                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
12544                         RTE_ETH_INPUT_SET_UNKNOWN},
12545                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
12546                         RTE_ETH_INPUT_SET_UNKNOWN},
12547
12548                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
12549                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12550                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
12551                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12552                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
12553                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
12554                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
12555                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
12556
12557                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
12558                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12559                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
12560                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12561                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
12562                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
12563                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
12564                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
12565
12566                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
12567                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12568                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
12569                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12570                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
12571                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
12572                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
12573                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
12574
12575                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
12576                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12577                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
12578                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12579                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
12580                         RTE_ETH_INPUT_SET_UNKNOWN},
12581                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
12582                         RTE_ETH_INPUT_SET_UNKNOWN},
12583
12584                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
12585                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
12586                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
12587                         RTE_ETH_INPUT_SET_L3_DST_IP6},
12588                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
12589                         RTE_ETH_INPUT_SET_UNKNOWN},
12590                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
12591                         RTE_ETH_INPUT_SET_UNKNOWN},
12592
12593                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
12594                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
12595                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
12596                         RTE_ETH_INPUT_SET_L3_DST_IP6},
12597                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
12598                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
12599                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
12600                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
12601
12602                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
12603                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
12604                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
12605                         RTE_ETH_INPUT_SET_L3_DST_IP6},
12606                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
12607                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
12608                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
12609                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
12610
12611                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
12612                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
12613                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
12614                         RTE_ETH_INPUT_SET_L3_DST_IP6},
12615                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
12616                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
12617                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
12618                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
12619
12620                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
12621                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
12622                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
12623                         RTE_ETH_INPUT_SET_L3_DST_IP6},
12624                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
12625                         RTE_ETH_INPUT_SET_UNKNOWN},
12626                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
12627                         RTE_ETH_INPUT_SET_UNKNOWN},
12628         };
12629
12630         mask0 = types & pf->adapter->flow_types_mask;
12631         conf.op = RTE_ETH_INPUT_SET_SELECT;
12632         conf.inset_size = 0;
12633         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
12634                 if (mask0 & (1ULL << i)) {
12635                         conf.flow_type = i;
12636                         break;
12637                 }
12638         }
12639
12640         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
12641                 if ((types & inset_match_table[j].type) ==
12642                     inset_match_table[j].type) {
12643                         if (inset_match_table[j].field ==
12644                             RTE_ETH_INPUT_SET_UNKNOWN)
12645                                 return -EINVAL;
12646
12647                         conf.field[conf.inset_size] =
12648                                 inset_match_table[j].field;
12649                         conf.inset_size++;
12650                 }
12651         }
12652
12653         if (conf.inset_size) {
12654                 ret = i40e_hash_filter_inset_select(hw, &conf);
12655                 if (ret)
12656                         return ret;
12657         }
12658
12659         return ret;
12660 }
12661
12662 /* Look up the conflicted rule then mark it as invalid */
12663 static void
12664 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
12665                 struct i40e_rte_flow_rss_conf *conf)
12666 {
12667         struct i40e_rss_filter *rss_item;
12668         uint64_t rss_inset;
12669
12670         /* Clear input set bits before comparing the pctype */
12671         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
12672                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
12673
12674         /* Look up the conflicted rule then mark it as invalid */
12675         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
12676                 if (!rss_item->rss_filter_info.valid)
12677                         continue;
12678
12679                 if (conf->conf.queue_num &&
12680                     rss_item->rss_filter_info.conf.queue_num)
12681                         rss_item->rss_filter_info.valid = false;
12682
12683                 if (conf->conf.types &&
12684                     (rss_item->rss_filter_info.conf.types &
12685                     rss_inset) ==
12686                     (conf->conf.types & rss_inset))
12687                         rss_item->rss_filter_info.valid = false;
12688
12689                 if (conf->conf.func ==
12690                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
12691                     rss_item->rss_filter_info.conf.func ==
12692                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
12693                         rss_item->rss_filter_info.valid = false;
12694         }
12695 }
12696
12697 /* Configure RSS hash function */
12698 static int
12699 i40e_rss_config_hash_function(struct i40e_pf *pf,
12700                 struct i40e_rte_flow_rss_conf *conf)
12701 {
12702         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12703         uint32_t reg, i;
12704         uint64_t mask0;
12705         uint16_t j;
12706
12707         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
12708                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
12709                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
12710                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
12711                         I40E_WRITE_FLUSH(hw);
12712                         i40e_rss_mark_invalid_rule(pf, conf);
12713
12714                         return 0;
12715                 }
12716                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
12717
12718                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
12719                 I40E_WRITE_FLUSH(hw);
12720                 i40e_rss_mark_invalid_rule(pf, conf);
12721         } else if (conf->conf.func ==
12722                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
12723                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
12724
12725                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
12726                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
12727                         if (mask0 & (1UL << i))
12728                                 break;
12729                 }
12730
12731                 if (i == UINT64_BIT)
12732                         return -EINVAL;
12733
12734                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
12735                      j < I40E_FILTER_PCTYPE_MAX; j++) {
12736                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
12737                                 i40e_write_global_rx_ctl(hw,
12738                                         I40E_GLQF_HSYM(j),
12739                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
12740                 }
12741         }
12742
12743         return 0;
12744 }
12745
12746 /* Enable RSS according to the configuration */
12747 static int
12748 i40e_rss_enable_hash(struct i40e_pf *pf,
12749                 struct i40e_rte_flow_rss_conf *conf)
12750 {
12751         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12752         struct i40e_rte_flow_rss_conf rss_conf;
12753
12754         if (!(conf->conf.types & pf->adapter->flow_types_mask))
12755                 return -ENOTSUP;
12756
12757         memset(&rss_conf, 0, sizeof(rss_conf));
12758         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
12759
12760         /* Configure hash input set */
12761         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
12762                 return -EINVAL;
12763
12764         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
12765             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12766                 /* Random default keys */
12767                 static uint32_t rss_key_default[] = {0x6b793944,
12768                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12769                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12770                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12771
12772                 rss_conf.conf.key = (uint8_t *)rss_key_default;
12773                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12774                                 sizeof(uint32_t);
12775                 PMD_DRV_LOG(INFO,
12776                         "No valid RSS key config for i40e, using default\n");
12777         }
12778
12779         rss_conf.conf.types |= rss_info->conf.types;
12780         i40e_rss_hash_set(pf, &rss_conf);
12781
12782         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
12783                 i40e_rss_config_hash_function(pf, conf);
12784
12785         i40e_rss_mark_invalid_rule(pf, conf);
12786
12787         return 0;
12788 }
12789
12790 /* Configure RSS queue region */
12791 static int
12792 i40e_rss_config_queue_region(struct i40e_pf *pf,
12793                 struct i40e_rte_flow_rss_conf *conf)
12794 {
12795         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12796         uint32_t lut = 0;
12797         uint16_t j, num;
12798         uint32_t i;
12799
12800         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12801          * It's necessary to calculate the actual PF queues that are configured.
12802          */
12803         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12804                 num = i40e_pf_calc_configured_queues_num(pf);
12805         else
12806                 num = pf->dev_data->nb_rx_queues;
12807
12808         num = RTE_MIN(num, conf->conf.queue_num);
12809         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12810                         num);
12811
12812         if (num == 0) {
12813                 PMD_DRV_LOG(ERR,
12814                         "No PF queues are configured to enable RSS for port %u",
12815                         pf->dev_data->port_id);
12816                 return -ENOTSUP;
12817         }
12818
12819         /* Fill in redirection table */
12820         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12821                 if (j == num)
12822                         j = 0;
12823                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12824                         hw->func_caps.rss_table_entry_width) - 1));
12825                 if ((i & 3) == 3)
12826                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12827         }
12828
12829         i40e_rss_mark_invalid_rule(pf, conf);
12830
12831         return 0;
12832 }
12833
12834 /* Configure RSS hash function to default */
12835 static int
12836 i40e_rss_clear_hash_function(struct i40e_pf *pf,
12837                 struct i40e_rte_flow_rss_conf *conf)
12838 {
12839         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12840         uint32_t i, reg;
12841         uint64_t mask0;
12842         uint16_t j;
12843
12844         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
12845                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
12846                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
12847                         PMD_DRV_LOG(DEBUG,
12848                                 "Hash function already set to Toeplitz");
12849                         I40E_WRITE_FLUSH(hw);
12850
12851                         return 0;
12852                 }
12853                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
12854
12855                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
12856                 I40E_WRITE_FLUSH(hw);
12857         } else if (conf->conf.func ==
12858                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
12859                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
12860
12861                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
12862                         if (mask0 & (1UL << i))
12863                                 break;
12864                 }
12865
12866                 if (i == UINT64_BIT)
12867                         return -EINVAL;
12868
12869                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
12870                      j < I40E_FILTER_PCTYPE_MAX; j++) {
12871                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
12872                                 i40e_write_global_rx_ctl(hw,
12873                                         I40E_GLQF_HSYM(j),
12874                                         0);
12875                 }
12876         }
12877
12878         return 0;
12879 }
12880
12881 /* Disable RSS hash and configure default input set */
12882 static int
12883 i40e_rss_disable_hash(struct i40e_pf *pf,
12884                 struct i40e_rte_flow_rss_conf *conf)
12885 {
12886         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12887         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12888         struct i40e_rte_flow_rss_conf rss_conf;
12889         uint32_t i;
12890
12891         memset(&rss_conf, 0, sizeof(rss_conf));
12892         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
12893
12894         /* Disable RSS hash */
12895         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
12896         i40e_rss_hash_set(pf, &rss_conf);
12897
12898         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
12899                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
12900                     !(conf->conf.types & (1ULL << i)))
12901                         continue;
12902
12903                 /* Configure default input set */
12904                 struct rte_eth_input_set_conf input_conf = {
12905                         .op = RTE_ETH_INPUT_SET_SELECT,
12906                         .flow_type = i,
12907                         .inset_size = 1,
12908                 };
12909                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
12910                 i40e_hash_filter_inset_select(hw, &input_conf);
12911         }
12912
12913         rss_info->conf.types = rss_conf.conf.types;
12914
12915         i40e_rss_clear_hash_function(pf, conf);
12916
12917         return 0;
12918 }
12919
12920 /* Configure RSS queue region to default */
12921 static int
12922 i40e_rss_clear_queue_region(struct i40e_pf *pf)
12923 {
12924         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12925         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12926         uint16_t queue[I40E_MAX_Q_PER_TC];
12927         uint32_t num_rxq, i;
12928         uint32_t lut = 0;
12929         uint16_t j, num;
12930
12931         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
12932
12933         for (j = 0; j < num_rxq; j++)
12934                 queue[j] = j;
12935
12936         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12937          * It's necessary to calculate the actual PF queues that are configured.
12938          */
12939         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12940                 num = i40e_pf_calc_configured_queues_num(pf);
12941         else
12942                 num = pf->dev_data->nb_rx_queues;
12943
12944         num = RTE_MIN(num, num_rxq);
12945         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12946                         num);
12947
12948         if (num == 0) {
12949                 PMD_DRV_LOG(ERR,
12950                         "No PF queues are configured to enable RSS for port %u",
12951                         pf->dev_data->port_id);
12952                 return -ENOTSUP;
12953         }
12954
12955         /* Fill in redirection table */
12956         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12957                 if (j == num)
12958                         j = 0;
12959                 lut = (lut << 8) | (queue[j] & ((0x1 <<
12960                         hw->func_caps.rss_table_entry_width) - 1));
12961                 if ((i & 3) == 3)
12962                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12963         }
12964
12965         rss_info->conf.queue_num = 0;
12966         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
12967
12968         return 0;
12969 }
12970
12971 int
12972 i40e_config_rss_filter(struct i40e_pf *pf,
12973                 struct i40e_rte_flow_rss_conf *conf, bool add)
12974 {
12975         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12976         struct rte_flow_action_rss update_conf = rss_info->conf;
12977         int ret = 0;
12978
12979         if (add) {
12980                 if (conf->conf.queue_num) {
12981                         /* Configure RSS queue region */
12982                         ret = i40e_rss_config_queue_region(pf, conf);
12983                         if (ret)
12984                                 return ret;
12985
12986                         update_conf.queue_num = conf->conf.queue_num;
12987                         update_conf.queue = conf->conf.queue;
12988                 } else if (conf->conf.func ==
12989                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
12990                         /* Configure hash function */
12991                         ret = i40e_rss_config_hash_function(pf, conf);
12992                         if (ret)
12993                                 return ret;
12994
12995                         update_conf.func = conf->conf.func;
12996                 } else {
12997                         /* Configure hash enable and input set */
12998                         ret = i40e_rss_enable_hash(pf, conf);
12999                         if (ret)
13000                                 return ret;
13001
13002                         update_conf.types |= conf->conf.types;
13003                         update_conf.key = conf->conf.key;
13004                         update_conf.key_len = conf->conf.key_len;
13005                 }
13006
13007                 /* Update RSS info in pf */
13008                 if (i40e_rss_conf_init(rss_info, &update_conf))
13009                         return -EINVAL;
13010         } else {
13011                 if (!conf->valid)
13012                         return 0;
13013
13014                 if (conf->conf.queue_num)
13015                         i40e_rss_clear_queue_region(pf);
13016                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13017                         i40e_rss_clear_hash_function(pf, conf);
13018                 else
13019                         i40e_rss_disable_hash(pf, conf);
13020         }
13021
13022         return 0;
13023 }
13024
13025 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13026 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13027 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13028 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13029 #endif
13030 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13031 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13032 #endif
13033 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13034 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13035 #endif
13036
13037 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13038                               ETH_I40E_FLOATING_VEB_ARG "=1"
13039                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13040                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13041                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13042                               ETH_I40E_USE_LATEST_VEC "=0|1");