drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 241                                 char *fw_version, size_t fw_size);
 242 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 243                              struct rte_eth_dev_info *dev_info);
 244 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 245                                 uint16_t vlan_id,
 246                                 int on);
 247 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 248                               enum rte_vlan_type vlan_type,
 249                               uint16_t tpid);
 250 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 251 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                                       uint16_t queue,
 253                                       int on);
 254 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 255 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 256 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 257 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 258                               struct rte_eth_fc_conf *fc_conf);
 259 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 262                                        struct rte_eth_pfc_conf *pfc_conf);
 263 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 264                             struct rte_ether_addr *mac_addr,
 265                             uint32_t index,
 266                             uint32_t pool);
 267 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 268 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 269                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 270                                     uint16_t reta_size);
 271 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 272                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 273                                    uint16_t reta_size);
 274
 275 static int i40e_get_cap(struct i40e_hw *hw);
 276 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 277 static int i40e_pf_setup(struct i40e_pf *pf);
 278 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 279 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 280 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 281 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 282                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 283 static void i40e_stat_update_48(struct i40e_hw *hw,
 284                                uint32_t hireg,
 285                                uint32_t loreg,
 286                                bool offset_loaded,
 287                                uint64_t *offset,
 288                                uint64_t *stat);
 289 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 290 static void i40e_dev_interrupt_handler(void *param);
 291 static void i40e_dev_alarm_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_get_module_info(struct rte_eth_dev *dev,
 373                                 struct rte_eth_dev_module_info *modinfo);
 374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 375                                   struct rte_dev_eeprom_info *info);
 376
 377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 378                                       struct rte_ether_addr *mac_addr);
 379
 380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 381
 382 static int i40e_ethertype_filter_convert(
 383         const struct rte_eth_ethertype_filter *input,
 384         struct i40e_ethertype_filter *filter);
 385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 386                                    struct i40e_ethertype_filter *filter);
 387
 388 static int i40e_tunnel_filter_convert(
 389         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 390         struct i40e_tunnel_filter *tunnel_filter);
 391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 392                                 struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 394
 395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 397 static void i40e_filter_restore(struct i40e_pf *pf);
 398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 399
 400 int i40e_logtype_init;
 401 int i40e_logtype_driver;
 402
 403 static const char *const valid_keys[] = {
 404         ETH_I40E_FLOATING_VEB_ARG,
 405         ETH_I40E_FLOATING_VEB_LIST_ARG,
 406         ETH_I40E_SUPPORT_MULTI_DRIVER,
 407         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 408         ETH_I40E_USE_LATEST_VEC,
 409         NULL};
 410
 411 static const struct rte_pci_id pci_id_i40e_map[] = {
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 435         { .vendor_id = 0, /* sentinel */ },
 436 };
 437
 438 static const struct eth_dev_ops i40e_eth_dev_ops = {
 439         .dev_configure                = i40e_dev_configure,
 440         .dev_start                    = i40e_dev_start,
 441         .dev_stop                     = i40e_dev_stop,
 442         .dev_close                    = i40e_dev_close,
 443         .dev_reset                    = i40e_dev_reset,
 444         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 445         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 446         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 447         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 448         .dev_set_link_up              = i40e_dev_set_link_up,
 449         .dev_set_link_down            = i40e_dev_set_link_down,
 450         .link_update                  = i40e_dev_link_update,
 451         .stats_get                    = i40e_dev_stats_get,
 452         .xstats_get                   = i40e_dev_xstats_get,
 453         .xstats_get_names             = i40e_dev_xstats_get_names,
 454         .stats_reset                  = i40e_dev_stats_reset,
 455         .xstats_reset                 = i40e_dev_stats_reset,
 456         .fw_version_get               = i40e_fw_version_get,
 457         .dev_infos_get                = i40e_dev_info_get,
 458         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 459         .vlan_filter_set              = i40e_vlan_filter_set,
 460         .vlan_tpid_set                = i40e_vlan_tpid_set,
 461         .vlan_offload_set             = i40e_vlan_offload_set,
 462         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 463         .vlan_pvid_set                = i40e_vlan_pvid_set,
 464         .rx_queue_start               = i40e_dev_rx_queue_start,
 465         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 466         .tx_queue_start               = i40e_dev_tx_queue_start,
 467         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 468         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 469         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 470         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 471         .rx_queue_release             = i40e_dev_rx_queue_release,
 472         .rx_queue_count               = i40e_dev_rx_queue_count,
 473         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 474         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 475         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 476         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 477         .tx_queue_release             = i40e_dev_tx_queue_release,
 478         .dev_led_on                   = i40e_dev_led_on,
 479         .dev_led_off                  = i40e_dev_led_off,
 480         .flow_ctrl_get                = i40e_flow_ctrl_get,
 481         .flow_ctrl_set                = i40e_flow_ctrl_set,
 482         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 483         .mac_addr_add                 = i40e_macaddr_add,
 484         .mac_addr_remove              = i40e_macaddr_remove,
 485         .reta_update                  = i40e_dev_rss_reta_update,
 486         .reta_query                   = i40e_dev_rss_reta_query,
 487         .rss_hash_update              = i40e_dev_rss_hash_update,
 488         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 489         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 490         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 491         .filter_ctrl                  = i40e_dev_filter_ctrl,
 492         .rxq_info_get                 = i40e_rxq_info_get,
 493         .txq_info_get                 = i40e_txq_info_get,
 494         .mirror_rule_set              = i40e_mirror_rule_set,
 495         .mirror_rule_reset            = i40e_mirror_rule_reset,
 496         .timesync_enable              = i40e_timesync_enable,
 497         .timesync_disable             = i40e_timesync_disable,
 498         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 499         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 500         .get_dcb_info                 = i40e_dev_get_dcb_info,
 501         .timesync_adjust_time         = i40e_timesync_adjust_time,
 502         .timesync_read_time           = i40e_timesync_read_time,
 503         .timesync_write_time          = i40e_timesync_write_time,
 504         .get_reg                      = i40e_get_regs,
 505         .get_eeprom_length            = i40e_get_eeprom_length,
 506         .get_eeprom                   = i40e_get_eeprom,
 507         .get_module_info              = i40e_get_module_info,
 508         .get_module_eeprom            = i40e_get_module_eeprom,
 509         .mac_addr_set                 = i40e_set_default_mac_addr,
 510         .mtu_set                      = i40e_dev_mtu_set,
 511         .tm_ops_get                   = i40e_tm_ops_get,
 512 };
 513
 514 /* store statistics names and its offset in stats structure */
 515 struct rte_i40e_xstats_name_off {
 516         char name[RTE_ETH_XSTATS_NAME_SIZE];
 517         unsigned offset;
 518 };
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 521         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 522         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 523         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 524         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 525         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 526                 rx_unknown_protocol)},
 527         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 528         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 529         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 530         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 531 };
 532
 533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 534                 sizeof(rte_i40e_stats_strings[0]))
 535
 536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 537         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 538                 tx_dropped_link_down)},
 539         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 540         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 541                 illegal_bytes)},
 542         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 543         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 544                 mac_local_faults)},
 545         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 546                 mac_remote_faults)},
 547         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 548                 rx_length_errors)},
 549         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 550         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 551         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 552         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 553         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 554         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 555                 rx_size_127)},
 556         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 557                 rx_size_255)},
 558         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_511)},
 560         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_1023)},
 562         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_1522)},
 564         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_big)},
 566         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 567                 rx_undersize)},
 568         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_oversize)},
 570         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 571                 mac_short_packet_dropped)},
 572         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_fragments)},
 574         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 575         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 576         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 577                 tx_size_127)},
 578         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 579                 tx_size_255)},
 580         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_511)},
 582         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_1023)},
 584         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_1522)},
 586         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_big)},
 588         {"rx_flow_director_atr_match_packets",
 589                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 590         {"rx_flow_director_sb_match_packets",
 591                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 592         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 593                 tx_lpi_status)},
 594         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 595                 rx_lpi_status)},
 596         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 597                 tx_lpi_count)},
 598         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 599                 rx_lpi_count)},
 600 };
 601
 602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 603                 sizeof(rte_i40e_hw_port_strings[0]))
 604
 605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 606         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 607                 priority_xon_rx)},
 608         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xoff_rx)},
 610 };
 611
 612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 613                 sizeof(rte_i40e_rxq_prio_strings[0]))
 614
 615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 616         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 617                 priority_xon_tx)},
 618         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xoff_tx)},
 620         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xon_2_xoff)},
 622 };
 623
 624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 625                 sizeof(rte_i40e_txq_prio_strings[0]))
 626
 627 static int
 628 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 629         struct rte_pci_device *pci_dev)
 630 {
 631         char name[RTE_ETH_NAME_MAX_LEN];
 632         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 633         int i, retval;
 634
 635         if (pci_dev->device.devargs) {
 636                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 637                                 &eth_da);
 638                 if (retval)
 639                         return retval;
 640         }
 641
 642         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 643                 sizeof(struct i40e_adapter),
 644                 eth_dev_pci_specific_init, pci_dev,
 645                 eth_i40e_dev_init, NULL);
 646
 647         if (retval || eth_da.nb_representor_ports < 1)
 648                 return retval;
 649
 650         /* probe VF representor ports */
 651         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 652                 pci_dev->device.name);
 653
 654         if (pf_ethdev == NULL)
 655                 return -ENODEV;
 656
 657         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 658                 struct i40e_vf_representor representor = {
 659                         .vf_id = eth_da.representor_ports[i],
 660                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 661                                 pf_ethdev->data->dev_private)->switch_domain_id,
 662                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 663                                 pf_ethdev->data->dev_private)
 664                 };
 665
 666                 /* representor port net_bdf_port */
 667                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 668                         pci_dev->device.name, eth_da.representor_ports[i]);
 669
 670                 retval = rte_eth_dev_create(&pci_dev->device, name,
 671                         sizeof(struct i40e_vf_representor), NULL, NULL,
 672                         i40e_vf_representor_init, &representor);
 673
 674                 if (retval)
 675                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 676                                 "representor %s.", name);
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 683 {
 684         struct rte_eth_dev *ethdev;
 685
 686         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 687         if (!ethdev)
 688                 return -ENODEV;
 689
 690
 691         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 692                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 693         else
 694                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 695 }
 696
 697 static struct rte_pci_driver rte_i40e_pmd = {
 698         .id_table = pci_id_i40e_map,
 699         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 700         .probe = eth_i40e_pci_probe,
 701         .remove = eth_i40e_pci_remove,
 702 };
 703
 704 static inline void
 705 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 706                          uint32_t reg_val)
 707 {
 708         uint32_t ori_reg_val;
 709         struct rte_eth_dev *dev;
 710
 711         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 712         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 713         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 714         if (ori_reg_val != reg_val)
 715                 PMD_DRV_LOG(WARNING,
 716                             "i40e device %s changed global register [0x%08x]."
 717                             " original: 0x%08x, new: 0x%08x",
 718                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 719 }
 720
 721 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 722 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 723 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 724
 725 #ifndef I40E_GLQF_ORT
 726 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 727 #endif
 728 #ifndef I40E_GLQF_PIT
 729 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 730 #endif
 731 #ifndef I40E_GLQF_L3_MAP
 732 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 733 #endif
 734
 735 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 736 {
 737         /*
 738          * Initialize registers for parsing packet type of QinQ
 739          * This should be removed from code once proper
 740          * configuration API is added to avoid configuration conflicts
 741          * between ports of the same device.
 742          */
 743         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 744         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 745 }
 746
 747 static inline void i40e_config_automask(struct i40e_pf *pf)
 748 {
 749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 750         uint32_t val;
 751
 752         /* INTENA flag is not auto-cleared for interrupt */
 753         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 754         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 755                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 756
 757         /* If support multi-driver, PF will use INT0. */
 758         if (!pf->support_multi_driver)
 759                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 760
 761         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 762 }
 763
 764 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 765
 766 /*
 767  * Add a ethertype filter to drop all flow control frames transmitted
 768  * from VSIs.
 769 */
 770 static void
 771 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 772 {
 773         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 774         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 775                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 776                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 777         int ret;
 778
 779         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 780                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 781                                 pf->main_vsi_seid, 0,
 782                                 TRUE, NULL, NULL);
 783         if (ret)
 784                 PMD_INIT_LOG(ERR,
 785                         "Failed to add filter to drop flow control frames from VSIs.");
 786 }
 787
 788 static int
 789 floating_veb_list_handler(__rte_unused const char *key,
 790                           const char *floating_veb_value,
 791                           void *opaque)
 792 {
 793         int idx = 0;
 794         unsigned int count = 0;
 795         char *end = NULL;
 796         int min, max;
 797         bool *vf_floating_veb = opaque;
 798
 799         while (isblank(*floating_veb_value))
 800                 floating_veb_value++;
 801
 802         /* Reset floating VEB configuration for VFs */
 803         for (idx = 0; idx < I40E_MAX_VF; idx++)
 804                 vf_floating_veb[idx] = false;
 805
 806         min = I40E_MAX_VF;
 807         do {
 808                 while (isblank(*floating_veb_value))
 809                         floating_veb_value++;
 810                 if (*floating_veb_value == '\0')
 811                         return -1;
 812                 errno = 0;
 813                 idx = strtoul(floating_veb_value, &end, 10);
 814                 if (errno || end == NULL)
 815                         return -1;
 816                 while (isblank(*end))
 817                         end++;
 818                 if (*end == '-') {
 819                         min = idx;
 820                 } else if ((*end == ';') || (*end == '\0')) {
 821                         max = idx;
 822                         if (min == I40E_MAX_VF)
 823                                 min = idx;
 824                         if (max >= I40E_MAX_VF)
 825                                 max = I40E_MAX_VF - 1;
 826                         for (idx = min; idx <= max; idx++) {
 827                                 vf_floating_veb[idx] = true;
 828                                 count++;
 829                         }
 830                         min = I40E_MAX_VF;
 831                 } else {
 832                         return -1;
 833                 }
 834                 floating_veb_value = end + 1;
 835         } while (*end != '\0');
 836
 837         if (count == 0)
 838                 return -1;
 839
 840         return 0;
 841 }
 842
 843 static void
 844 config_vf_floating_veb(struct rte_devargs *devargs,
 845                        uint16_t floating_veb,
 846                        bool *vf_floating_veb)
 847 {
 848         struct rte_kvargs *kvlist;
 849         int i;
 850         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 851
 852         if (!floating_veb)
 853                 return;
 854         /* All the VFs attach to the floating VEB by default
 855          * when the floating VEB is enabled.
 856          */
 857         for (i = 0; i < I40E_MAX_VF; i++)
 858                 vf_floating_veb[i] = true;
 859
 860         if (devargs == NULL)
 861                 return;
 862
 863         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 864         if (kvlist == NULL)
 865                 return;
 866
 867         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 868                 rte_kvargs_free(kvlist);
 869                 return;
 870         }
 871         /* When the floating_veb_list parameter exists, all the VFs
 872          * will attach to the legacy VEB firstly, then configure VFs
 873          * to the floating VEB according to the floating_veb_list.
 874          */
 875         if (rte_kvargs_process(kvlist, floating_veb_list,
 876                                floating_veb_list_handler,
 877                                vf_floating_veb) < 0) {
 878                 rte_kvargs_free(kvlist);
 879                 return;
 880         }
 881         rte_kvargs_free(kvlist);
 882 }
 883
 884 static int
 885 i40e_check_floating_handler(__rte_unused const char *key,
 886                             const char *value,
 887                             __rte_unused void *opaque)
 888 {
 889         if (strcmp(value, "1"))
 890                 return -1;
 891
 892         return 0;
 893 }
 894
 895 static int
 896 is_floating_veb_supported(struct rte_devargs *devargs)
 897 {
 898         struct rte_kvargs *kvlist;
 899         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 900
 901         if (devargs == NULL)
 902                 return 0;
 903
 904         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 905         if (kvlist == NULL)
 906                 return 0;
 907
 908         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 909                 rte_kvargs_free(kvlist);
 910                 return 0;
 911         }
 912         /* Floating VEB is enabled when there's key-value:
 913          * enable_floating_veb=1
 914          */
 915         if (rte_kvargs_process(kvlist, floating_veb_key,
 916                                i40e_check_floating_handler, NULL) < 0) {
 917                 rte_kvargs_free(kvlist);
 918                 return 0;
 919         }
 920         rte_kvargs_free(kvlist);
 921
 922         return 1;
 923 }
 924
 925 static void
 926 config_floating_veb(struct rte_eth_dev *dev)
 927 {
 928         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 931
 932         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 933
 934         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 935                 pf->floating_veb =
 936                         is_floating_veb_supported(pci_dev->device.devargs);
 937                 config_vf_floating_veb(pci_dev->device.devargs,
 938                                        pf->floating_veb,
 939                                        pf->floating_veb_list);
 940         } else {
 941                 pf->floating_veb = false;
 942         }
 943 }
 944
 945 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 946 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 947
 948 static int
 949 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 953         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters ethertype_hash_params = {
 957                 .name = ethertype_hash_name,
 958                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize ethertype filter rule list and hash */
 966         TAILQ_INIT(&ethertype_rule->ethertype_list);
 967         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 968                  "ethertype_%s", dev->device->name);
 969         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 970         if (!ethertype_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 972                 return -EINVAL;
 973         }
 974         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 975                                        sizeof(struct i40e_ethertype_filter *) *
 976                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 977                                        0);
 978         if (!ethertype_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for ethertype hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_ethertype_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_ethertype_hash_map_alloc:
 988         rte_hash_free(ethertype_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 998         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters tunnel_hash_params = {
1002                 .name = tunnel_hash_name,
1003                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1004                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize tunnel filter rule list and hash */
1011         TAILQ_INIT(&tunnel_rule->tunnel_list);
1012         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1013                  "tunnel_%s", dev->device->name);
1014         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1015         if (!tunnel_rule->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1017                 return -EINVAL;
1018         }
1019         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1020                                     sizeof(struct i40e_tunnel_filter *) *
1021                                     I40E_MAX_TUNNEL_FILTER_NUM,
1022                                     0);
1023         if (!tunnel_rule->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for tunnel hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_tunnel_hash_map_alloc;
1028         }
1029
1030         return 0;
1031
1032 err_tunnel_hash_map_alloc:
1033         rte_hash_free(tunnel_rule->hash_table);
1034
1035         return ret;
1036 }
1037
1038 static int
1039 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1040 {
1041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042         struct i40e_fdir_info *fdir_info = &pf->fdir;
1043         char fdir_hash_name[RTE_HASH_NAMESIZE];
1044         int ret;
1045
1046         struct rte_hash_parameters fdir_hash_params = {
1047                 .name = fdir_hash_name,
1048                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1049                 .key_len = sizeof(struct i40e_fdir_input),
1050                 .hash_func = rte_hash_crc,
1051                 .hash_func_init_val = 0,
1052                 .socket_id = rte_socket_id(),
1053         };
1054
1055         /* Initialize flow director filter rule list and hash */
1056         TAILQ_INIT(&fdir_info->fdir_list);
1057         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1058                  "fdir_%s", dev->device->name);
1059         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1060         if (!fdir_info->hash_table) {
1061                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1062                 return -EINVAL;
1063         }
1064         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1065                                           sizeof(struct i40e_fdir_filter *) *
1066                                           I40E_MAX_FDIR_FILTER_NUM,
1067                                           0);
1068         if (!fdir_info->hash_map) {
1069                 PMD_INIT_LOG(ERR,
1070                              "Failed to allocate memory for fdir hash map!");
1071                 ret = -ENOMEM;
1072                 goto err_fdir_hash_map_alloc;
1073         }
1074         return 0;
1075
1076 err_fdir_hash_map_alloc:
1077         rte_hash_free(fdir_info->hash_table);
1078
1079         return ret;
1080 }
1081
1082 static void
1083 i40e_init_customized_info(struct i40e_pf *pf)
1084 {
1085         int i;
1086
1087         /* Initialize customized pctype */
1088         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1089                 pf->customized_pctype[i].index = i;
1090                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1091                 pf->customized_pctype[i].valid = false;
1092         }
1093
1094         pf->gtp_support = false;
1095 }
1096
1097 void
1098 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1099 {
1100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1102         struct i40e_queue_regions *info = &pf->queue_region;
1103         uint16_t i;
1104
1105         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1106                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1107
1108         memset(info, 0, sizeof(struct i40e_queue_regions));
1109 }
1110
1111 static int
1112 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1113                                const char *value,
1114                                void *opaque)
1115 {
1116         struct i40e_pf *pf;
1117         unsigned long support_multi_driver;
1118         char *end;
1119
1120         pf = (struct i40e_pf *)opaque;
1121
1122         errno = 0;
1123         support_multi_driver = strtoul(value, &end, 10);
1124         if (errno != 0 || end == value || *end != 0) {
1125                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1126                 return -(EINVAL);
1127         }
1128
1129         if (support_multi_driver == 1 || support_multi_driver == 0)
1130                 pf->support_multi_driver = (bool)support_multi_driver;
1131         else
1132                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1133                             "enable global configuration by default."
1134                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1135         return 0;
1136 }
1137
1138 static int
1139 i40e_support_multi_driver(struct rte_eth_dev *dev)
1140 {
1141         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142         struct rte_kvargs *kvlist;
1143         int kvargs_count;
1144
1145         /* Enable global configuration by default */
1146         pf->support_multi_driver = false;
1147
1148         if (!dev->device->devargs)
1149                 return 0;
1150
1151         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1152         if (!kvlist)
1153                 return -EINVAL;
1154
1155         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1156         if (!kvargs_count) {
1157                 rte_kvargs_free(kvlist);
1158                 return 0;
1159         }
1160
1161         if (kvargs_count > 1)
1162                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1163                             "the first invalid or last valid one is used !",
1164                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1165
1166         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1167                                i40e_parse_multi_drv_handler, pf) < 0) {
1168                 rte_kvargs_free(kvlist);
1169                 return -EINVAL;
1170         }
1171
1172         rte_kvargs_free(kvlist);
1173         return 0;
1174 }
1175
1176 static int
1177 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1178                                     uint32_t reg_addr, uint64_t reg_val,
1179                                     struct i40e_asq_cmd_details *cmd_details)
1180 {
1181         uint64_t ori_reg_val;
1182         struct rte_eth_dev *dev;
1183         int ret;
1184
1185         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1186         if (ret != I40E_SUCCESS) {
1187                 PMD_DRV_LOG(ERR,
1188                             "Fail to debug read from 0x%08x",
1189                             reg_addr);
1190                 return -EIO;
1191         }
1192         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1193
1194         if (ori_reg_val != reg_val)
1195                 PMD_DRV_LOG(WARNING,
1196                             "i40e device %s changed global register [0x%08x]."
1197                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1198                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1199
1200         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1201 }
1202
1203 static int
1204 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1205                                 const char *value,
1206                                 void *opaque)
1207 {
1208         struct i40e_adapter *ad = opaque;
1209         int use_latest_vec;
1210
1211         use_latest_vec = atoi(value);
1212
1213         if (use_latest_vec != 0 && use_latest_vec != 1)
1214                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1215
1216         ad->use_latest_vec = (uint8_t)use_latest_vec;
1217
1218         return 0;
1219 }
1220
1221 static int
1222 i40e_use_latest_vec(struct rte_eth_dev *dev)
1223 {
1224         struct i40e_adapter *ad =
1225                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226         struct rte_kvargs *kvlist;
1227         int kvargs_count;
1228
1229         ad->use_latest_vec = false;
1230
1231         if (!dev->device->devargs)
1232                 return 0;
1233
1234         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1235         if (!kvlist)
1236                 return -EINVAL;
1237
1238         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1239         if (!kvargs_count) {
1240                 rte_kvargs_free(kvlist);
1241                 return 0;
1242         }
1243
1244         if (kvargs_count > 1)
1245                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1246                             "the first invalid or last valid one is used !",
1247                             ETH_I40E_USE_LATEST_VEC);
1248
1249         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1250                                 i40e_parse_latest_vec_handler, ad) < 0) {
1251                 rte_kvargs_free(kvlist);
1252                 return -EINVAL;
1253         }
1254
1255         rte_kvargs_free(kvlist);
1256         return 0;
1257 }
1258
1259 #define I40E_ALARM_INTERVAL 50000 /* us */
1260
1261 static int
1262 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1263 {
1264         struct rte_pci_device *pci_dev;
1265         struct rte_intr_handle *intr_handle;
1266         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1267         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268         struct i40e_vsi *vsi;
1269         int ret;
1270         uint32_t len, val;
1271         uint8_t aq_fail = 0;
1272
1273         PMD_INIT_FUNC_TRACE();
1274
1275         dev->dev_ops = &i40e_eth_dev_ops;
1276         dev->rx_pkt_burst = i40e_recv_pkts;
1277         dev->tx_pkt_burst = i40e_xmit_pkts;
1278         dev->tx_pkt_prepare = i40e_prep_pkts;
1279
1280         /* for secondary processes, we don't initialise any further as primary
1281          * has already done this work. Only check we don't need a different
1282          * RX function */
1283         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1284                 i40e_set_rx_function(dev);
1285                 i40e_set_tx_function(dev);
1286                 return 0;
1287         }
1288         i40e_set_default_ptype_table(dev);
1289         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1290         intr_handle = &pci_dev->intr_handle;
1291
1292         rte_eth_copy_pci_info(dev, pci_dev);
1293
1294         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1295         pf->adapter->eth_dev = dev;
1296         pf->dev_data = dev->data;
1297
1298         hw->back = I40E_PF_TO_ADAPTER(pf);
1299         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1300         if (!hw->hw_addr) {
1301                 PMD_INIT_LOG(ERR,
1302                         "Hardware is not available, as address is NULL");
1303                 return -ENODEV;
1304         }
1305
1306         hw->vendor_id = pci_dev->id.vendor_id;
1307         hw->device_id = pci_dev->id.device_id;
1308         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1309         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1310         hw->bus.device = pci_dev->addr.devid;
1311         hw->bus.func = pci_dev->addr.function;
1312         hw->adapter_stopped = 0;
1313         hw->adapter_closed = 0;
1314
1315         /*
1316          * Switch Tag value should not be identical to either the First Tag
1317          * or Second Tag values. So set something other than common Ethertype
1318          * for internal switching.
1319          */
1320         hw->switch_tag = 0xffff;
1321
1322         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1323         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1324                 PMD_INIT_LOG(ERR, "\nERROR: "
1325                         "Firmware recovery mode detected. Limiting functionality.\n"
1326                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1327                         "User Guide for details on firmware recovery mode.");
1328                 return -EIO;
1329         }
1330
1331         /* Check if need to support multi-driver */
1332         i40e_support_multi_driver(dev);
1333         /* Check if users want the latest supported vec path */
1334         i40e_use_latest_vec(dev);
1335
1336         /* Make sure all is clean before doing PF reset */
1337         i40e_clear_hw(hw);
1338
1339         /* Reset here to make sure all is clean for each PF */
1340         ret = i40e_pf_reset(hw);
1341         if (ret) {
1342                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1343                 return ret;
1344         }
1345
1346         /* Initialize the shared code (base driver) */
1347         ret = i40e_init_shared_code(hw);
1348         if (ret) {
1349                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1350                 return ret;
1351         }
1352
1353         /* Initialize the parameters for adminq */
1354         i40e_init_adminq_parameter(hw);
1355         ret = i40e_init_adminq(hw);
1356         if (ret != I40E_SUCCESS) {
1357                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1358                 return -EIO;
1359         }
1360         /* Firmware of SFP x722 does not support adminq option */
1361         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1362                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1363
1364         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1365                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1366                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1367                      ((hw->nvm.version >> 12) & 0xf),
1368                      ((hw->nvm.version >> 4) & 0xff),
1369                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1370
1371         /* Initialize the hardware */
1372         i40e_hw_init(dev);
1373
1374         i40e_config_automask(pf);
1375
1376         i40e_set_default_pctype_table(dev);
1377
1378         /*
1379          * To work around the NVM issue, initialize registers
1380          * for packet type of QinQ by software.
1381          * It should be removed once issues are fixed in NVM.
1382          */
1383         if (!pf->support_multi_driver)
1384                 i40e_GLQF_reg_init(hw);
1385
1386         /* Initialize the input set for filters (hash and fd) to default value */
1387         i40e_filter_input_set_init(pf);
1388
1389         /* initialise the L3_MAP register */
1390         if (!pf->support_multi_driver) {
1391                 ret = i40e_aq_debug_write_global_register(hw,
1392                                                    I40E_GLQF_L3_MAP(40),
1393                                                    0x00000028,  NULL);
1394                 if (ret)
1395                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1396                                      ret);
1397                 PMD_INIT_LOG(DEBUG,
1398                              "Global register 0x%08x is changed with 0x28",
1399                              I40E_GLQF_L3_MAP(40));
1400         }
1401
1402         /* Need the special FW version to support floating VEB */
1403         config_floating_veb(dev);
1404         /* Clear PXE mode */
1405         i40e_clear_pxe_mode(hw);
1406         i40e_dev_sync_phy_type(hw);
1407
1408         /*
1409          * On X710, performance number is far from the expectation on recent
1410          * firmware versions. The fix for this issue may not be integrated in
1411          * the following firmware version. So the workaround in software driver
1412          * is needed. It needs to modify the initial values of 3 internal only
1413          * registers. Note that the workaround can be removed when it is fixed
1414          * in firmware in the future.
1415          */
1416         i40e_configure_registers(hw);
1417
1418         /* Get hw capabilities */
1419         ret = i40e_get_cap(hw);
1420         if (ret != I40E_SUCCESS) {
1421                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1422                 goto err_get_capabilities;
1423         }
1424
1425         /* Initialize parameters for PF */
1426         ret = i40e_pf_parameter_init(dev);
1427         if (ret != 0) {
1428                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1429                 goto err_parameter_init;
1430         }
1431
1432         /* Initialize the queue management */
1433         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1434         if (ret < 0) {
1435                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1436                 goto err_qp_pool_init;
1437         }
1438         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1439                                 hw->func_caps.num_msix_vectors - 1);
1440         if (ret < 0) {
1441                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1442                 goto err_msix_pool_init;
1443         }
1444
1445         /* Initialize lan hmc */
1446         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1447                                 hw->func_caps.num_rx_qp, 0, 0);
1448         if (ret != I40E_SUCCESS) {
1449                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1450                 goto err_init_lan_hmc;
1451         }
1452
1453         /* Configure lan hmc */
1454         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1455         if (ret != I40E_SUCCESS) {
1456                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1457                 goto err_configure_lan_hmc;
1458         }
1459
1460         /* Get and check the mac address */
1461         i40e_get_mac_addr(hw, hw->mac.addr);
1462         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1463                 PMD_INIT_LOG(ERR, "mac address is not valid");
1464                 ret = -EIO;
1465                 goto err_get_mac_addr;
1466         }
1467         /* Copy the permanent MAC address */
1468         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1469                         (struct rte_ether_addr *)hw->mac.perm_addr);
1470
1471         /* Disable flow control */
1472         hw->fc.requested_mode = I40E_FC_NONE;
1473         i40e_set_fc(hw, &aq_fail, TRUE);
1474
1475         /* Set the global registers with default ether type value */
1476         if (!pf->support_multi_driver) {
1477                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1478                                          RTE_ETHER_TYPE_VLAN);
1479                 if (ret != I40E_SUCCESS) {
1480                         PMD_INIT_LOG(ERR,
1481                                      "Failed to set the default outer "
1482                                      "VLAN ether type");
1483                         goto err_setup_pf_switch;
1484                 }
1485         }
1486
1487         /* PF setup, which includes VSI setup */
1488         ret = i40e_pf_setup(pf);
1489         if (ret) {
1490                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1491                 goto err_setup_pf_switch;
1492         }
1493
1494         vsi = pf->main_vsi;
1495
1496         /* Disable double vlan by default */
1497         i40e_vsi_config_double_vlan(vsi, FALSE);
1498
1499         /* Disable S-TAG identification when floating_veb is disabled */
1500         if (!pf->floating_veb) {
1501                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1502                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1503                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1504                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1505                 }
1506         }
1507
1508         if (!vsi->max_macaddrs)
1509                 len = RTE_ETHER_ADDR_LEN;
1510         else
1511                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1512
1513         /* Should be after VSI initialized */
1514         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1515         if (!dev->data->mac_addrs) {
1516                 PMD_INIT_LOG(ERR,
1517                         "Failed to allocated memory for storing mac address");
1518                 goto err_mac_alloc;
1519         }
1520         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1521                                         &dev->data->mac_addrs[0]);
1522
1523         /* Init dcb to sw mode by default */
1524         ret = i40e_dcb_init_configure(dev, TRUE);
1525         if (ret != I40E_SUCCESS) {
1526                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1527                 pf->flags &= ~I40E_FLAG_DCB;
1528         }
1529         /* Update HW struct after DCB configuration */
1530         i40e_get_cap(hw);
1531
1532         /* initialize pf host driver to setup SRIOV resource if applicable */
1533         i40e_pf_host_init(dev);
1534
1535         /* register callback func to eal lib */
1536         rte_intr_callback_register(intr_handle,
1537                                    i40e_dev_interrupt_handler, dev);
1538
1539         /* configure and enable device interrupt */
1540         i40e_pf_config_irq0(hw, TRUE);
1541         i40e_pf_enable_irq0(hw);
1542
1543         /* enable uio intr after callback register */
1544         rte_intr_enable(intr_handle);
1545
1546         /* By default disable flexible payload in global configuration */
1547         if (!pf->support_multi_driver)
1548                 i40e_flex_payload_reg_set_default(hw);
1549
1550         /*
1551          * Add an ethertype filter to drop all flow control frames transmitted
1552          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1553          * frames to wire.
1554          */
1555         i40e_add_tx_flow_control_drop_filter(pf);
1556
1557         /* Set the max frame size to 0x2600 by default,
1558          * in case other drivers changed the default value.
1559          */
1560         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1561
1562         /* initialize mirror rule list */
1563         TAILQ_INIT(&pf->mirror_list);
1564
1565         /* initialize Traffic Manager configuration */
1566         i40e_tm_conf_init(dev);
1567
1568         /* Initialize customized information */
1569         i40e_init_customized_info(pf);
1570
1571         ret = i40e_init_ethtype_filter_list(dev);
1572         if (ret < 0)
1573                 goto err_init_ethtype_filter_list;
1574         ret = i40e_init_tunnel_filter_list(dev);
1575         if (ret < 0)
1576                 goto err_init_tunnel_filter_list;
1577         ret = i40e_init_fdir_filter_list(dev);
1578         if (ret < 0)
1579                 goto err_init_fdir_filter_list;
1580
1581         /* initialize queue region configuration */
1582         i40e_init_queue_region_conf(dev);
1583
1584         /* initialize rss configuration from rte_flow */
1585         memset(&pf->rss_info, 0,
1586                 sizeof(struct i40e_rte_flow_rss_conf));
1587
1588         /* reset all stats of the device, including pf and main vsi */
1589         i40e_dev_stats_reset(dev);
1590
1591         return 0;
1592
1593 err_init_fdir_filter_list:
1594         rte_free(pf->tunnel.hash_table);
1595         rte_free(pf->tunnel.hash_map);
1596 err_init_tunnel_filter_list:
1597         rte_free(pf->ethertype.hash_table);
1598         rte_free(pf->ethertype.hash_map);
1599 err_init_ethtype_filter_list:
1600         rte_free(dev->data->mac_addrs);
1601         dev->data->mac_addrs = NULL;
1602 err_mac_alloc:
1603         i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1605 err_get_mac_addr:
1606 err_configure_lan_hmc:
1607         (void)i40e_shutdown_lan_hmc(hw);
1608 err_init_lan_hmc:
1609         i40e_res_pool_destroy(&pf->msix_pool);
1610 err_msix_pool_init:
1611         i40e_res_pool_destroy(&pf->qp_pool);
1612 err_qp_pool_init:
1613 err_parameter_init:
1614 err_get_capabilities:
1615         (void)i40e_shutdown_adminq(hw);
1616
1617         return ret;
1618 }
1619
1620 static void
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1622 {
1623         struct i40e_ethertype_filter *p_ethertype;
1624         struct i40e_ethertype_rule *ethertype_rule;
1625
1626         ethertype_rule = &pf->ethertype;
1627         /* Remove all ethertype filter rules and hash */
1628         if (ethertype_rule->hash_map)
1629                 rte_free(ethertype_rule->hash_map);
1630         if (ethertype_rule->hash_table)
1631                 rte_hash_free(ethertype_rule->hash_table);
1632
1633         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1634                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1635                              p_ethertype, rules);
1636                 rte_free(p_ethertype);
1637         }
1638 }
1639
1640 static void
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1642 {
1643         struct i40e_tunnel_filter *p_tunnel;
1644         struct i40e_tunnel_rule *tunnel_rule;
1645
1646         tunnel_rule = &pf->tunnel;
1647         /* Remove all tunnel director rules and hash */
1648         if (tunnel_rule->hash_map)
1649                 rte_free(tunnel_rule->hash_map);
1650         if (tunnel_rule->hash_table)
1651                 rte_hash_free(tunnel_rule->hash_table);
1652
1653         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1655                 rte_free(p_tunnel);
1656         }
1657 }
1658
1659 static void
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1661 {
1662         struct i40e_fdir_filter *p_fdir;
1663         struct i40e_fdir_info *fdir_info;
1664
1665         fdir_info = &pf->fdir;
1666         /* Remove all flow director rules and hash */
1667         if (fdir_info->hash_map)
1668                 rte_free(fdir_info->hash_map);
1669         if (fdir_info->hash_table)
1670                 rte_hash_free(fdir_info->hash_table);
1671
1672         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1674                 rte_free(p_fdir);
1675         }
1676 }
1677
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1679 {
1680         /*
1681          * Disable by default flexible payload
1682          * for corresponding L2/L3/L4 layers.
1683          */
1684         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1687 }
1688
1689 static int
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1691 {
1692         struct i40e_pf *pf;
1693         struct rte_pci_device *pci_dev;
1694         struct rte_intr_handle *intr_handle;
1695         struct i40e_hw *hw;
1696         struct i40e_filter_control_settings settings;
1697         struct rte_flow *p_flow;
1698         int ret;
1699         uint8_t aq_fail = 0;
1700         int retries = 0;
1701
1702         PMD_INIT_FUNC_TRACE();
1703
1704         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1705                 return 0;
1706
1707         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710         intr_handle = &pci_dev->intr_handle;
1711
1712         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1713         if (ret)
1714                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1715
1716         if (hw->adapter_closed == 0)
1717                 i40e_dev_close(dev);
1718
1719         dev->dev_ops = NULL;
1720         dev->rx_pkt_burst = NULL;
1721         dev->tx_pkt_burst = NULL;
1722
1723         /* Clear PXE mode */
1724         i40e_clear_pxe_mode(hw);
1725
1726         /* Unconfigure filter control */
1727         memset(&settings, 0, sizeof(settings));
1728         ret = i40e_set_filter_control(hw, &settings);
1729         if (ret)
1730                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1731                                         ret);
1732
1733         /* Disable flow control */
1734         hw->fc.requested_mode = I40E_FC_NONE;
1735         i40e_set_fc(hw, &aq_fail, TRUE);
1736
1737         /* uninitialize pf host driver */
1738         i40e_pf_host_uninit(dev);
1739
1740         /* disable uio intr before callback unregister */
1741         rte_intr_disable(intr_handle);
1742
1743         /* unregister callback func to eal lib */
1744         do {
1745                 ret = rte_intr_callback_unregister(intr_handle,
1746                                 i40e_dev_interrupt_handler, dev);
1747                 if (ret >= 0) {
1748                         break;
1749                 } else if (ret != -EAGAIN) {
1750                         PMD_INIT_LOG(ERR,
1751                                  "intr callback unregister failed: %d",
1752                                  ret);
1753                         return ret;
1754                 }
1755                 i40e_msec_delay(500);
1756         } while (retries++ < 5);
1757
1758         i40e_rm_ethtype_filter_list(pf);
1759         i40e_rm_tunnel_filter_list(pf);
1760         i40e_rm_fdir_filter_list(pf);
1761
1762         /* Remove all flows */
1763         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1765                 rte_free(p_flow);
1766         }
1767
1768         /* Remove all Traffic Manager configuration */
1769         i40e_tm_conf_uninit(dev);
1770
1771         return 0;
1772 }
1773
1774 static int
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1776 {
1777         struct i40e_adapter *ad =
1778                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1782         int i, ret;
1783
1784         ret = i40e_dev_sync_phy_type(hw);
1785         if (ret)
1786                 return ret;
1787
1788         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789          * bulk allocation or vector Rx preconditions we will reset it.
1790          */
1791         ad->rx_bulk_alloc_allowed = true;
1792         ad->rx_vec_allowed = true;
1793         ad->tx_simple_allowed = true;
1794         ad->tx_vec_allowed = true;
1795
1796         /* Only legacy filter API needs the following fdir config. So when the
1797          * legacy filter API is deprecated, the following codes should also be
1798          * removed.
1799          */
1800         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801                 ret = i40e_fdir_setup(pf);
1802                 if (ret != I40E_SUCCESS) {
1803                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1804                         return -ENOTSUP;
1805                 }
1806                 ret = i40e_fdir_configure(dev);
1807                 if (ret < 0) {
1808                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1809                         goto err;
1810                 }
1811         } else
1812                 i40e_fdir_teardown(pf);
1813
1814         ret = i40e_dev_init_vlan(dev);
1815         if (ret < 0)
1816                 goto err;
1817
1818         /* VMDQ setup.
1819          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820          *  RSS setting have different requirements.
1821          *  General PMD driver call sequence are NIC init, configure,
1822          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1824          *  applicable. So, VMDQ setting has to be done before
1825          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1826          *  For RSS setting, it will try to calculate actual configured RX queue
1827          *  number, which will be available after rx_queue_setup(). dev_start()
1828          *  function is good to place RSS setup.
1829          */
1830         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831                 ret = i40e_vmdq_setup(dev);
1832                 if (ret)
1833                         goto err;
1834         }
1835
1836         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837                 ret = i40e_dcb_setup(dev);
1838                 if (ret) {
1839                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1840                         goto err_dcb;
1841                 }
1842         }
1843
1844         TAILQ_INIT(&pf->flow_list);
1845
1846         return 0;
1847
1848 err_dcb:
1849         /* need to release vmdq resource if exists */
1850         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851                 i40e_vsi_release(pf->vmdq[i].vsi);
1852                 pf->vmdq[i].vsi = NULL;
1853         }
1854         rte_free(pf->vmdq);
1855         pf->vmdq = NULL;
1856 err:
1857         /* Need to release fdir resource if exists.
1858          * Only legacy filter API needs the following fdir config. So when the
1859          * legacy filter API is deprecated, the following code should also be
1860          * removed.
1861          */
1862         i40e_fdir_teardown(pf);
1863         return ret;
1864 }
1865
1866 void
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1868 {
1869         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873         uint16_t msix_vect = vsi->msix_intr;
1874         uint16_t i;
1875
1876         for (i = 0; i < vsi->nb_qps; i++) {
1877                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1879                 rte_wmb();
1880         }
1881
1882         if (vsi->type != I40E_VSI_SRIOV) {
1883                 if (!rte_intr_allow_others(intr_handle)) {
1884                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1886                         I40E_WRITE_REG(hw,
1887                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1888                                        0);
1889                 } else {
1890                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1892                         I40E_WRITE_REG(hw,
1893                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1894                                                        msix_vect - 1), 0);
1895                 }
1896         } else {
1897                 uint32_t reg;
1898                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899                         vsi->user_param + (msix_vect - 1);
1900
1901                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1903         }
1904         I40E_WRITE_FLUSH(hw);
1905 }
1906
1907 static void
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909                        int base_queue, int nb_queue,
1910                        uint16_t itr_idx)
1911 {
1912         int i;
1913         uint32_t val;
1914         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1916
1917         /* Bind all RX queues to allocated MSIX interrupt */
1918         for (i = 0; i < nb_queue; i++) {
1919                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921                         ((base_queue + i + 1) <<
1922                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1925
1926                 if (i == nb_queue - 1)
1927                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1929         }
1930
1931         /* Write first RX queue to Link list register as the head element */
1932         if (vsi->type != I40E_VSI_SRIOV) {
1933                 uint16_t interval =
1934                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1935
1936                 if (msix_vect == I40E_MISC_VEC_ID) {
1937                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1938                                        (base_queue <<
1939                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1940                                        (0x0 <<
1941                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1942                         I40E_WRITE_REG(hw,
1943                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1944                                        interval);
1945                 } else {
1946                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1947                                        (base_queue <<
1948                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1949                                        (0x0 <<
1950                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1951                         I40E_WRITE_REG(hw,
1952                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1953                                                        msix_vect - 1),
1954                                        interval);
1955                 }
1956         } else {
1957                 uint32_t reg;
1958
1959                 if (msix_vect == I40E_MISC_VEC_ID) {
1960                         I40E_WRITE_REG(hw,
1961                                        I40E_VPINT_LNKLST0(vsi->user_param),
1962                                        (base_queue <<
1963                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1964                                        (0x0 <<
1965                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1966                 } else {
1967                         /* num_msix_vectors_vf needs to minus irq0 */
1968                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969                                 vsi->user_param + (msix_vect - 1);
1970
1971                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1972                                        (base_queue <<
1973                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1974                                        (0x0 <<
1975                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1976                 }
1977         }
1978
1979         I40E_WRITE_FLUSH(hw);
1980 }
1981
1982 void
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1984 {
1985         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989         uint16_t msix_vect = vsi->msix_intr;
1990         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991         uint16_t queue_idx = 0;
1992         int record = 0;
1993         int i;
1994
1995         for (i = 0; i < vsi->nb_qps; i++) {
1996                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1998         }
1999
2000         /* VF bind interrupt */
2001         if (vsi->type == I40E_VSI_SRIOV) {
2002                 __vsi_queues_bind_intr(vsi, msix_vect,
2003                                        vsi->base_queue, vsi->nb_qps,
2004                                        itr_idx);
2005                 return;
2006         }
2007
2008         /* PF & VMDq bind interrupt */
2009         if (rte_intr_dp_is_en(intr_handle)) {
2010                 if (vsi->type == I40E_VSI_MAIN) {
2011                         queue_idx = 0;
2012                         record = 1;
2013                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014                         struct i40e_vsi *main_vsi =
2015                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2017                         record = 1;
2018                 }
2019         }
2020
2021         for (i = 0; i < vsi->nb_used_qps; i++) {
2022                 if (nb_msix <= 1) {
2023                         if (!rte_intr_allow_others(intr_handle))
2024                                 /* allow to share MISC_VEC_ID */
2025                                 msix_vect = I40E_MISC_VEC_ID;
2026
2027                         /* no enough msix_vect, map all to one */
2028                         __vsi_queues_bind_intr(vsi, msix_vect,
2029                                                vsi->base_queue + i,
2030                                                vsi->nb_used_qps - i,
2031                                                itr_idx);
2032                         for (; !!record && i < vsi->nb_used_qps; i++)
2033                                 intr_handle->intr_vec[queue_idx + i] =
2034                                         msix_vect;
2035                         break;
2036                 }
2037                 /* 1:1 queue/msix_vect mapping */
2038                 __vsi_queues_bind_intr(vsi, msix_vect,
2039                                        vsi->base_queue + i, 1,
2040                                        itr_idx);
2041                 if (!!record)
2042                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2043
2044                 msix_vect++;
2045                 nb_msix--;
2046         }
2047 }
2048
2049 static void
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2051 {
2052         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057         uint16_t msix_intr, i;
2058
2059         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060                 for (i = 0; i < vsi->nb_msix; i++) {
2061                         msix_intr = vsi->msix_intr + i;
2062                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2066                 }
2067         else
2068                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2072
2073         I40E_WRITE_FLUSH(hw);
2074 }
2075
2076 static void
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2078 {
2079         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084         uint16_t msix_intr, i;
2085
2086         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087                 for (i = 0; i < vsi->nb_msix; i++) {
2088                         msix_intr = vsi->msix_intr + i;
2089                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2091                 }
2092         else
2093                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2095
2096         I40E_WRITE_FLUSH(hw);
2097 }
2098
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2101 {
2102         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2103
2104         if (link_speeds & ETH_LINK_SPEED_40G)
2105                 link_speed |= I40E_LINK_SPEED_40GB;
2106         if (link_speeds & ETH_LINK_SPEED_25G)
2107                 link_speed |= I40E_LINK_SPEED_25GB;
2108         if (link_speeds & ETH_LINK_SPEED_20G)
2109                 link_speed |= I40E_LINK_SPEED_20GB;
2110         if (link_speeds & ETH_LINK_SPEED_10G)
2111                 link_speed |= I40E_LINK_SPEED_10GB;
2112         if (link_speeds & ETH_LINK_SPEED_1G)
2113                 link_speed |= I40E_LINK_SPEED_1GB;
2114         if (link_speeds & ETH_LINK_SPEED_100M)
2115                 link_speed |= I40E_LINK_SPEED_100MB;
2116
2117         return link_speed;
2118 }
2119
2120 static int
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2122                    uint8_t abilities,
2123                    uint8_t force_speed,
2124                    bool is_up)
2125 {
2126         enum i40e_status_code status;
2127         struct i40e_aq_get_phy_abilities_resp phy_ab;
2128         struct i40e_aq_set_phy_config phy_conf;
2129         enum i40e_aq_phy_type cnt;
2130         uint8_t avail_speed;
2131         uint32_t phy_type_mask = 0;
2132
2133         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2135                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2136                         I40E_AQ_PHY_FLAG_LOW_POWER;
2137         int ret = -ENOTSUP;
2138
2139         /* To get phy capabilities of available speeds. */
2140         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2141                                               NULL);
2142         if (status) {
2143                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2144                                 status);
2145                 return ret;
2146         }
2147         avail_speed = phy_ab.link_speed;
2148
2149         /* To get the current phy config. */
2150         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2151                                               NULL);
2152         if (status) {
2153                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2154                                 status);
2155                 return ret;
2156         }
2157
2158         /* If link needs to go up and it is in autoneg mode the speed is OK,
2159          * no need to set up again.
2160          */
2161         if (is_up && phy_ab.phy_type != 0 &&
2162                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2163                      phy_ab.link_speed != 0)
2164                 return I40E_SUCCESS;
2165
2166         memset(&phy_conf, 0, sizeof(phy_conf));
2167
2168         /* bits 0-2 use the values from get_phy_abilities_resp */
2169         abilities &= ~mask;
2170         abilities |= phy_ab.abilities & mask;
2171
2172         phy_conf.abilities = abilities;
2173
2174         /* If link needs to go up, but the force speed is not supported,
2175          * Warn users and config the default available speeds.
2176          */
2177         if (is_up && !(force_speed & avail_speed)) {
2178                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179                 phy_conf.link_speed = avail_speed;
2180         } else {
2181                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2182         }
2183
2184         /* PHY type mask needs to include each type except PHY type extension */
2185         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186                 phy_type_mask |= 1 << cnt;
2187
2188         /* use get_phy_abilities_resp value for the rest */
2189         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194         phy_conf.eee_capability = phy_ab.eee_capability;
2195         phy_conf.eeer = phy_ab.eeer_val;
2196         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2197
2198         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199                     phy_ab.abilities, phy_ab.link_speed);
2200         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2201                     phy_conf.abilities, phy_conf.link_speed);
2202
2203         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2204         if (status)
2205                 return ret;
2206
2207         return I40E_SUCCESS;
2208 }
2209
2210 static int
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2212 {
2213         uint8_t speed;
2214         uint8_t abilities = 0;
2215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         struct rte_eth_conf *conf = &dev->data->dev_conf;
2217
2218         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219                 conf->link_speeds = ETH_LINK_SPEED_40G |
2220                                     ETH_LINK_SPEED_25G |
2221                                     ETH_LINK_SPEED_20G |
2222                                     ETH_LINK_SPEED_10G |
2223                                     ETH_LINK_SPEED_1G |
2224                                     ETH_LINK_SPEED_100M;
2225         }
2226         speed = i40e_parse_link_speeds(conf->link_speeds);
2227         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228                      I40E_AQ_PHY_AN_ENABLED |
2229                      I40E_AQ_PHY_LINK_ENABLED;
2230
2231         return i40e_phy_conf_link(hw, abilities, speed, true);
2232 }
2233
2234 static int
2235 i40e_dev_start(struct rte_eth_dev *dev)
2236 {
2237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         struct i40e_vsi *main_vsi = pf->main_vsi;
2240         int ret, i;
2241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243         uint32_t intr_vector = 0;
2244         struct i40e_vsi *vsi;
2245
2246         hw->adapter_stopped = 0;
2247
2248         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2249                 PMD_INIT_LOG(ERR,
2250                 "Invalid link_speeds for port %u, autonegotiation disabled",
2251                               dev->data->port_id);
2252                 return -EINVAL;
2253         }
2254
2255         rte_intr_disable(intr_handle);
2256
2257         if ((rte_intr_cap_multiple(intr_handle) ||
2258              !RTE_ETH_DEV_SRIOV(dev).active) &&
2259             dev->data->dev_conf.intr_conf.rxq != 0) {
2260                 intr_vector = dev->data->nb_rx_queues;
2261                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2262                 if (ret)
2263                         return ret;
2264         }
2265
2266         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267                 intr_handle->intr_vec =
2268                         rte_zmalloc("intr_vec",
2269                                     dev->data->nb_rx_queues * sizeof(int),
2270                                     0);
2271                 if (!intr_handle->intr_vec) {
2272                         PMD_INIT_LOG(ERR,
2273                                 "Failed to allocate %d rx_queues intr_vec",
2274                                 dev->data->nb_rx_queues);
2275                         return -ENOMEM;
2276                 }
2277         }
2278
2279         /* Initialize VSI */
2280         ret = i40e_dev_rxtx_init(pf);
2281         if (ret != I40E_SUCCESS) {
2282                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2283                 goto err_up;
2284         }
2285
2286         /* Map queues with MSIX interrupt */
2287         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290         i40e_vsi_enable_queues_intr(main_vsi);
2291
2292         /* Map VMDQ VSI queues with MSIX interrupt */
2293         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296                                           I40E_ITR_INDEX_DEFAULT);
2297                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2298         }
2299
2300         /* enable FDIR MSIX interrupt */
2301         if (pf->fdir.fdir_vsi) {
2302                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303                                           I40E_ITR_INDEX_NONE);
2304                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2305         }
2306
2307         /* Enable all queues which have been configured */
2308         ret = i40e_dev_switch_queues(pf, TRUE);
2309         if (ret != I40E_SUCCESS) {
2310                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2311                 goto err_up;
2312         }
2313
2314         /* Enable receiving broadcast packets */
2315         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316         if (ret != I40E_SUCCESS)
2317                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2318
2319         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2321                                                 true, NULL);
2322                 if (ret != I40E_SUCCESS)
2323                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2324         }
2325
2326         /* Enable the VLAN promiscuous mode. */
2327         if (pf->vfs) {
2328                 for (i = 0; i < pf->vf_num; i++) {
2329                         vsi = pf->vfs[i].vsi;
2330                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2331                                                      true, NULL);
2332                 }
2333         }
2334
2335         /* Enable mac loopback mode */
2336         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339                 if (ret != I40E_SUCCESS) {
2340                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2341                         goto err_up;
2342                 }
2343         }
2344
2345         /* Apply link configure */
2346         ret = i40e_apply_link_speed(dev);
2347         if (I40E_SUCCESS != ret) {
2348                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2349                 goto err_up;
2350         }
2351
2352         if (!rte_intr_allow_others(intr_handle)) {
2353                 rte_intr_callback_unregister(intr_handle,
2354                                              i40e_dev_interrupt_handler,
2355                                              (void *)dev);
2356                 /* configure and enable device interrupt */
2357                 i40e_pf_config_irq0(hw, FALSE);
2358                 i40e_pf_enable_irq0(hw);
2359
2360                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2361                         PMD_INIT_LOG(INFO,
2362                                 "lsc won't enable because of no intr multiplex");
2363         } else {
2364                 ret = i40e_aq_set_phy_int_mask(hw,
2365                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2368                 if (ret != I40E_SUCCESS)
2369                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2370
2371                 /* Call get_link_info aq commond to enable/disable LSE */
2372                 i40e_dev_link_update(dev, 0);
2373         }
2374
2375         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377                                   i40e_dev_alarm_handler, dev);
2378         } else {
2379                 /* enable uio intr after callback register */
2380                 rte_intr_enable(intr_handle);
2381         }
2382
2383         i40e_filter_restore(pf);
2384
2385         if (pf->tm_conf.root && !pf->tm_conf.committed)
2386                 PMD_DRV_LOG(WARNING,
2387                             "please call hierarchy_commit() "
2388                             "before starting the port");
2389
2390         return I40E_SUCCESS;
2391
2392 err_up:
2393         i40e_dev_switch_queues(pf, FALSE);
2394         i40e_dev_clear_queues(dev);
2395
2396         return ret;
2397 }
2398
2399 static void
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2401 {
2402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct i40e_vsi *main_vsi = pf->main_vsi;
2405         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2407         int i;
2408
2409         if (hw->adapter_stopped == 1)
2410                 return;
2411
2412         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414                 rte_intr_enable(intr_handle);
2415         }
2416
2417         /* Disable all queues */
2418         i40e_dev_switch_queues(pf, FALSE);
2419
2420         /* un-map queues with interrupt registers */
2421         i40e_vsi_disable_queues_intr(main_vsi);
2422         i40e_vsi_queues_unbind_intr(main_vsi);
2423
2424         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2427         }
2428
2429         if (pf->fdir.fdir_vsi) {
2430                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2432         }
2433         /* Clear all queues and release memory */
2434         i40e_dev_clear_queues(dev);
2435
2436         /* Set link down */
2437         i40e_dev_set_link_down(dev);
2438
2439         if (!rte_intr_allow_others(intr_handle))
2440                 /* resume to the default handler */
2441                 rte_intr_callback_register(intr_handle,
2442                                            i40e_dev_interrupt_handler,
2443                                            (void *)dev);
2444
2445         /* Clean datapath event and queue/vec mapping */
2446         rte_intr_efd_disable(intr_handle);
2447         if (intr_handle->intr_vec) {
2448                 rte_free(intr_handle->intr_vec);
2449                 intr_handle->intr_vec = NULL;
2450         }
2451
2452         /* reset hierarchy commit */
2453         pf->tm_conf.committed = false;
2454
2455         hw->adapter_stopped = 1;
2456
2457         pf->adapter->rss_reta_updated = 0;
2458 }
2459
2460 static void
2461 i40e_dev_close(struct rte_eth_dev *dev)
2462 {
2463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2467         struct i40e_mirror_rule *p_mirror;
2468         uint32_t reg;
2469         int i;
2470         int ret;
2471
2472         PMD_INIT_FUNC_TRACE();
2473
2474         i40e_dev_stop(dev);
2475
2476         /* Remove all mirror rules */
2477         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2478                 ret = i40e_aq_del_mirror_rule(hw,
2479                                               pf->main_vsi->veb->seid,
2480                                               p_mirror->rule_type,
2481                                               p_mirror->entries,
2482                                               p_mirror->num_entries,
2483                                               p_mirror->id);
2484                 if (ret < 0)
2485                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2486                                     "status = %d, aq_err = %d.", ret,
2487                                     hw->aq.asq_last_status);
2488
2489                 /* remove mirror software resource anyway */
2490                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2491                 rte_free(p_mirror);
2492                 pf->nb_mirror_rule--;
2493         }
2494
2495         i40e_dev_free_queues(dev);
2496
2497         /* Disable interrupt */
2498         i40e_pf_disable_irq0(hw);
2499         rte_intr_disable(intr_handle);
2500
2501         /*
2502          * Only legacy filter API needs the following fdir config. So when the
2503          * legacy filter API is deprecated, the following code should also be
2504          * removed.
2505          */
2506         i40e_fdir_teardown(pf);
2507
2508         /* shutdown and destroy the HMC */
2509         i40e_shutdown_lan_hmc(hw);
2510
2511         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2512                 i40e_vsi_release(pf->vmdq[i].vsi);
2513                 pf->vmdq[i].vsi = NULL;
2514         }
2515         rte_free(pf->vmdq);
2516         pf->vmdq = NULL;
2517
2518         /* release all the existing VSIs and VEBs */
2519         i40e_vsi_release(pf->main_vsi);
2520
2521         /* shutdown the adminq */
2522         i40e_aq_queue_shutdown(hw, true);
2523         i40e_shutdown_adminq(hw);
2524
2525         i40e_res_pool_destroy(&pf->qp_pool);
2526         i40e_res_pool_destroy(&pf->msix_pool);
2527
2528         /* Disable flexible payload in global configuration */
2529         if (!pf->support_multi_driver)
2530                 i40e_flex_payload_reg_set_default(hw);
2531
2532         /* force a PF reset to clean anything leftover */
2533         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2534         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2535                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2536         I40E_WRITE_FLUSH(hw);
2537
2538         hw->adapter_closed = 1;
2539 }
2540
2541 /*
2542  * Reset PF device only to re-initialize resources in PMD layer
2543  */
2544 static int
2545 i40e_dev_reset(struct rte_eth_dev *dev)
2546 {
2547         int ret;
2548
2549         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2550          * its VF to make them align with it. The detailed notification
2551          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2552          * To avoid unexpected behavior in VF, currently reset of PF with
2553          * SR-IOV activation is not supported. It might be supported later.
2554          */
2555         if (dev->data->sriov.active)
2556                 return -ENOTSUP;
2557
2558         ret = eth_i40e_dev_uninit(dev);
2559         if (ret)
2560                 return ret;
2561
2562         ret = eth_i40e_dev_init(dev, NULL);
2563
2564         return ret;
2565 }
2566
2567 static int
2568 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2569 {
2570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572         struct i40e_vsi *vsi = pf->main_vsi;
2573         int status;
2574
2575         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2576                                                      true, NULL, true);
2577         if (status != I40E_SUCCESS) {
2578                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2579                 return -EAGAIN;
2580         }
2581
2582         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2583                                                         TRUE, NULL);
2584         if (status != I40E_SUCCESS) {
2585                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2586                 /* Rollback unicast promiscuous mode */
2587                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2588                                                     false, NULL, true);
2589                 return -EAGAIN;
2590         }
2591
2592         return 0;
2593 }
2594
2595 static int
2596 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2597 {
2598         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2599         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2600         struct i40e_vsi *vsi = pf->main_vsi;
2601         int status;
2602
2603         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2604                                                      false, NULL, true);
2605         if (status != I40E_SUCCESS) {
2606                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2607                 return -EAGAIN;
2608         }
2609
2610         /* must remain in all_multicast mode */
2611         if (dev->data->all_multicast == 1)
2612                 return 0;
2613
2614         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2615                                                         false, NULL);
2616         if (status != I40E_SUCCESS) {
2617                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2618                 /* Rollback unicast promiscuous mode */
2619                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2620                                                     true, NULL, true);
2621                 return -EAGAIN;
2622         }
2623
2624         return 0;
2625 }
2626
2627 static void
2628 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2629 {
2630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         struct i40e_vsi *vsi = pf->main_vsi;
2633         int ret;
2634
2635         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2636         if (ret != I40E_SUCCESS)
2637                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2638 }
2639
2640 static void
2641 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2642 {
2643         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2644         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645         struct i40e_vsi *vsi = pf->main_vsi;
2646         int ret;
2647
2648         if (dev->data->promiscuous == 1)
2649                 return; /* must remain in all_multicast mode */
2650
2651         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2652                                 vsi->seid, FALSE, NULL);
2653         if (ret != I40E_SUCCESS)
2654                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2655 }
2656
2657 /*
2658  * Set device link up.
2659  */
2660 static int
2661 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2662 {
2663         /* re-apply link speed setting */
2664         return i40e_apply_link_speed(dev);
2665 }
2666
2667 /*
2668  * Set device link down.
2669  */
2670 static int
2671 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2672 {
2673         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2674         uint8_t abilities = 0;
2675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2676
2677         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2678         return i40e_phy_conf_link(hw, abilities, speed, false);
2679 }
2680
2681 static __rte_always_inline void
2682 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2683 {
2684 /* Link status registers and values*/
2685 #define I40E_PRTMAC_LINKSTA             0x001E2420
2686 #define I40E_REG_LINK_UP                0x40000080
2687 #define I40E_PRTMAC_MACC                0x001E24E0
2688 #define I40E_REG_MACC_25GB              0x00020000
2689 #define I40E_REG_SPEED_MASK             0x38000000
2690 #define I40E_REG_SPEED_0                0x00000000
2691 #define I40E_REG_SPEED_1                0x08000000
2692 #define I40E_REG_SPEED_2                0x10000000
2693 #define I40E_REG_SPEED_3                0x18000000
2694 #define I40E_REG_SPEED_4                0x20000000
2695         uint32_t link_speed;
2696         uint32_t reg_val;
2697
2698         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2699         link_speed = reg_val & I40E_REG_SPEED_MASK;
2700         reg_val &= I40E_REG_LINK_UP;
2701         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2702
2703         if (unlikely(link->link_status == 0))
2704                 return;
2705
2706         /* Parse the link status */
2707         switch (link_speed) {
2708         case I40E_REG_SPEED_0:
2709                 link->link_speed = ETH_SPEED_NUM_100M;
2710                 break;
2711         case I40E_REG_SPEED_1:
2712                 link->link_speed = ETH_SPEED_NUM_1G;
2713                 break;
2714         case I40E_REG_SPEED_2:
2715                 if (hw->mac.type == I40E_MAC_X722)
2716                         link->link_speed = ETH_SPEED_NUM_2_5G;
2717                 else
2718                         link->link_speed = ETH_SPEED_NUM_10G;
2719                 break;
2720         case I40E_REG_SPEED_3:
2721                 if (hw->mac.type == I40E_MAC_X722) {
2722                         link->link_speed = ETH_SPEED_NUM_5G;
2723                 } else {
2724                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2725
2726                         if (reg_val & I40E_REG_MACC_25GB)
2727                                 link->link_speed = ETH_SPEED_NUM_25G;
2728                         else
2729                                 link->link_speed = ETH_SPEED_NUM_40G;
2730                 }
2731                 break;
2732         case I40E_REG_SPEED_4:
2733                 if (hw->mac.type == I40E_MAC_X722)
2734                         link->link_speed = ETH_SPEED_NUM_10G;
2735                 else
2736                         link->link_speed = ETH_SPEED_NUM_20G;
2737                 break;
2738         default:
2739                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2740                 break;
2741         }
2742 }
2743
2744 static __rte_always_inline void
2745 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2746         bool enable_lse, int wait_to_complete)
2747 {
2748 #define CHECK_INTERVAL             100  /* 100ms */
2749 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2750         uint32_t rep_cnt = MAX_REPEAT_TIME;
2751         struct i40e_link_status link_status;
2752         int status;
2753
2754         memset(&link_status, 0, sizeof(link_status));
2755
2756         do {
2757                 memset(&link_status, 0, sizeof(link_status));
2758
2759                 /* Get link status information from hardware */
2760                 status = i40e_aq_get_link_info(hw, enable_lse,
2761                                                 &link_status, NULL);
2762                 if (unlikely(status != I40E_SUCCESS)) {
2763                         link->link_speed = ETH_SPEED_NUM_100M;
2764                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2765                         PMD_DRV_LOG(ERR, "Failed to get link info");
2766                         return;
2767                 }
2768
2769                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2770                 if (!wait_to_complete || link->link_status)
2771                         break;
2772
2773                 rte_delay_ms(CHECK_INTERVAL);
2774         } while (--rep_cnt);
2775
2776         /* Parse the link status */
2777         switch (link_status.link_speed) {
2778         case I40E_LINK_SPEED_100MB:
2779                 link->link_speed = ETH_SPEED_NUM_100M;
2780                 break;
2781         case I40E_LINK_SPEED_1GB:
2782                 link->link_speed = ETH_SPEED_NUM_1G;
2783                 break;
2784         case I40E_LINK_SPEED_10GB:
2785                 link->link_speed = ETH_SPEED_NUM_10G;
2786                 break;
2787         case I40E_LINK_SPEED_20GB:
2788                 link->link_speed = ETH_SPEED_NUM_20G;
2789                 break;
2790         case I40E_LINK_SPEED_25GB:
2791                 link->link_speed = ETH_SPEED_NUM_25G;
2792                 break;
2793         case I40E_LINK_SPEED_40GB:
2794                 link->link_speed = ETH_SPEED_NUM_40G;
2795                 break;
2796         default:
2797                 link->link_speed = ETH_SPEED_NUM_100M;
2798                 break;
2799         }
2800 }
2801
2802 int
2803 i40e_dev_link_update(struct rte_eth_dev *dev,
2804                      int wait_to_complete)
2805 {
2806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807         struct rte_eth_link link;
2808         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2809         int ret;
2810
2811         memset(&link, 0, sizeof(link));
2812
2813         /* i40e uses full duplex only */
2814         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2815         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2816                         ETH_LINK_SPEED_FIXED);
2817
2818         if (!wait_to_complete && !enable_lse)
2819                 update_link_reg(hw, &link);
2820         else
2821                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2822
2823         ret = rte_eth_linkstatus_set(dev, &link);
2824         i40e_notify_all_vfs_link_status(dev);
2825
2826         return ret;
2827 }
2828
2829 /* Get all the statistics of a VSI */
2830 void
2831 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2832 {
2833         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2834         struct i40e_eth_stats *nes = &vsi->eth_stats;
2835         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2836         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2837
2838         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2839                             vsi->offset_loaded, &oes->rx_bytes,
2840                             &nes->rx_bytes);
2841         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2842                             vsi->offset_loaded, &oes->rx_unicast,
2843                             &nes->rx_unicast);
2844         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2845                             vsi->offset_loaded, &oes->rx_multicast,
2846                             &nes->rx_multicast);
2847         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2848                             vsi->offset_loaded, &oes->rx_broadcast,
2849                             &nes->rx_broadcast);
2850         /* exclude CRC bytes */
2851         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2852                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2853
2854         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2855                             &oes->rx_discards, &nes->rx_discards);
2856         /* GLV_REPC not supported */
2857         /* GLV_RMPC not supported */
2858         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2859                             &oes->rx_unknown_protocol,
2860                             &nes->rx_unknown_protocol);
2861         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2862                             vsi->offset_loaded, &oes->tx_bytes,
2863                             &nes->tx_bytes);
2864         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2865                             vsi->offset_loaded, &oes->tx_unicast,
2866                             &nes->tx_unicast);
2867         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2868                             vsi->offset_loaded, &oes->tx_multicast,
2869                             &nes->tx_multicast);
2870         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2871                             vsi->offset_loaded,  &oes->tx_broadcast,
2872                             &nes->tx_broadcast);
2873         /* GLV_TDPC not supported */
2874         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2875                             &oes->tx_errors, &nes->tx_errors);
2876         vsi->offset_loaded = true;
2877
2878         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2879                     vsi->vsi_id);
2880         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2881         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2882         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2883         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2884         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2885         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2886                     nes->rx_unknown_protocol);
2887         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2888         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2889         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2890         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2891         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2892         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2893         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2894                     vsi->vsi_id);
2895 }
2896
2897 static void
2898 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2899 {
2900         unsigned int i;
2901         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2902         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2903
2904         /* Get rx/tx bytes of internal transfer packets */
2905         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2906                         I40E_GLV_GORCL(hw->port),
2907                         pf->offset_loaded,
2908                         &pf->internal_stats_offset.rx_bytes,
2909                         &pf->internal_stats.rx_bytes);
2910
2911         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2912                         I40E_GLV_GOTCL(hw->port),
2913                         pf->offset_loaded,
2914                         &pf->internal_stats_offset.tx_bytes,
2915                         &pf->internal_stats.tx_bytes);
2916         /* Get total internal rx packet count */
2917         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2918                             I40E_GLV_UPRCL(hw->port),
2919                             pf->offset_loaded,
2920                             &pf->internal_stats_offset.rx_unicast,
2921                             &pf->internal_stats.rx_unicast);
2922         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2923                             I40E_GLV_MPRCL(hw->port),
2924                             pf->offset_loaded,
2925                             &pf->internal_stats_offset.rx_multicast,
2926                             &pf->internal_stats.rx_multicast);
2927         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2928                             I40E_GLV_BPRCL(hw->port),
2929                             pf->offset_loaded,
2930                             &pf->internal_stats_offset.rx_broadcast,
2931                             &pf->internal_stats.rx_broadcast);
2932         /* Get total internal tx packet count */
2933         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2934                             I40E_GLV_UPTCL(hw->port),
2935                             pf->offset_loaded,
2936                             &pf->internal_stats_offset.tx_unicast,
2937                             &pf->internal_stats.tx_unicast);
2938         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2939                             I40E_GLV_MPTCL(hw->port),
2940                             pf->offset_loaded,
2941                             &pf->internal_stats_offset.tx_multicast,
2942                             &pf->internal_stats.tx_multicast);
2943         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2944                             I40E_GLV_BPTCL(hw->port),
2945                             pf->offset_loaded,
2946                             &pf->internal_stats_offset.tx_broadcast,
2947                             &pf->internal_stats.tx_broadcast);
2948
2949         /* exclude CRC size */
2950         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2951                 pf->internal_stats.rx_multicast +
2952                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2953
2954         /* Get statistics of struct i40e_eth_stats */
2955         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2956                             I40E_GLPRT_GORCL(hw->port),
2957                             pf->offset_loaded, &os->eth.rx_bytes,
2958                             &ns->eth.rx_bytes);
2959         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2960                             I40E_GLPRT_UPRCL(hw->port),
2961                             pf->offset_loaded, &os->eth.rx_unicast,
2962                             &ns->eth.rx_unicast);
2963         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2964                             I40E_GLPRT_MPRCL(hw->port),
2965                             pf->offset_loaded, &os->eth.rx_multicast,
2966                             &ns->eth.rx_multicast);
2967         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2968                             I40E_GLPRT_BPRCL(hw->port),
2969                             pf->offset_loaded, &os->eth.rx_broadcast,
2970                             &ns->eth.rx_broadcast);
2971         /* Workaround: CRC size should not be included in byte statistics,
2972          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2973          * packet.
2974          */
2975         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2976                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2977
2978         /* exclude internal rx bytes
2979          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2980          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2981          * value.
2982          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2983          */
2984         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2985                 ns->eth.rx_bytes = 0;
2986         else
2987                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2988
2989         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2990                 ns->eth.rx_unicast = 0;
2991         else
2992                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2993
2994         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2995                 ns->eth.rx_multicast = 0;
2996         else
2997                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2998
2999         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3000                 ns->eth.rx_broadcast = 0;
3001         else
3002                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3003
3004         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3005                             pf->offset_loaded, &os->eth.rx_discards,
3006                             &ns->eth.rx_discards);
3007         /* GLPRT_REPC not supported */
3008         /* GLPRT_RMPC not supported */
3009         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3010                             pf->offset_loaded,
3011                             &os->eth.rx_unknown_protocol,
3012                             &ns->eth.rx_unknown_protocol);
3013         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3014                             I40E_GLPRT_GOTCL(hw->port),
3015                             pf->offset_loaded, &os->eth.tx_bytes,
3016                             &ns->eth.tx_bytes);
3017         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3018                             I40E_GLPRT_UPTCL(hw->port),
3019                             pf->offset_loaded, &os->eth.tx_unicast,
3020                             &ns->eth.tx_unicast);
3021         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3022                             I40E_GLPRT_MPTCL(hw->port),
3023                             pf->offset_loaded, &os->eth.tx_multicast,
3024                             &ns->eth.tx_multicast);
3025         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3026                             I40E_GLPRT_BPTCL(hw->port),
3027                             pf->offset_loaded, &os->eth.tx_broadcast,
3028                             &ns->eth.tx_broadcast);
3029         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3030                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3031
3032         /* exclude internal tx bytes
3033          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3034          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3035          * value.
3036          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3037          */
3038         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3039                 ns->eth.tx_bytes = 0;
3040         else
3041                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3042
3043         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3044                 ns->eth.tx_unicast = 0;
3045         else
3046                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3047
3048         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3049                 ns->eth.tx_multicast = 0;
3050         else
3051                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3052
3053         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3054                 ns->eth.tx_broadcast = 0;
3055         else
3056                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3057
3058         /* GLPRT_TEPC not supported */
3059
3060         /* additional port specific stats */
3061         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3062                             pf->offset_loaded, &os->tx_dropped_link_down,
3063                             &ns->tx_dropped_link_down);
3064         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3065                             pf->offset_loaded, &os->crc_errors,
3066                             &ns->crc_errors);
3067         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3068                             pf->offset_loaded, &os->illegal_bytes,
3069                             &ns->illegal_bytes);
3070         /* GLPRT_ERRBC not supported */
3071         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3072                             pf->offset_loaded, &os->mac_local_faults,
3073                             &ns->mac_local_faults);
3074         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3075                             pf->offset_loaded, &os->mac_remote_faults,
3076                             &ns->mac_remote_faults);
3077         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3078                             pf->offset_loaded, &os->rx_length_errors,
3079                             &ns->rx_length_errors);
3080         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3081                             pf->offset_loaded, &os->link_xon_rx,
3082                             &ns->link_xon_rx);
3083         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3084                             pf->offset_loaded, &os->link_xoff_rx,
3085                             &ns->link_xoff_rx);
3086         for (i = 0; i < 8; i++) {
3087                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3088                                     pf->offset_loaded,
3089                                     &os->priority_xon_rx[i],
3090                                     &ns->priority_xon_rx[i]);
3091                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3092                                     pf->offset_loaded,
3093                                     &os->priority_xoff_rx[i],
3094                                     &ns->priority_xoff_rx[i]);
3095         }
3096         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3097                             pf->offset_loaded, &os->link_xon_tx,
3098                             &ns->link_xon_tx);
3099         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3100                             pf->offset_loaded, &os->link_xoff_tx,
3101                             &ns->link_xoff_tx);
3102         for (i = 0; i < 8; i++) {
3103                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3104                                     pf->offset_loaded,
3105                                     &os->priority_xon_tx[i],
3106                                     &ns->priority_xon_tx[i]);
3107                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3108                                     pf->offset_loaded,
3109                                     &os->priority_xoff_tx[i],
3110                                     &ns->priority_xoff_tx[i]);
3111                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3112                                     pf->offset_loaded,
3113                                     &os->priority_xon_2_xoff[i],
3114                                     &ns->priority_xon_2_xoff[i]);
3115         }
3116         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3117                             I40E_GLPRT_PRC64L(hw->port),
3118                             pf->offset_loaded, &os->rx_size_64,
3119                             &ns->rx_size_64);
3120         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3121                             I40E_GLPRT_PRC127L(hw->port),
3122                             pf->offset_loaded, &os->rx_size_127,
3123                             &ns->rx_size_127);
3124         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3125                             I40E_GLPRT_PRC255L(hw->port),
3126                             pf->offset_loaded, &os->rx_size_255,
3127                             &ns->rx_size_255);
3128         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3129                             I40E_GLPRT_PRC511L(hw->port),
3130                             pf->offset_loaded, &os->rx_size_511,
3131                             &ns->rx_size_511);
3132         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3133                             I40E_GLPRT_PRC1023L(hw->port),
3134                             pf->offset_loaded, &os->rx_size_1023,
3135                             &ns->rx_size_1023);
3136         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3137                             I40E_GLPRT_PRC1522L(hw->port),
3138                             pf->offset_loaded, &os->rx_size_1522,
3139                             &ns->rx_size_1522);
3140         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3141                             I40E_GLPRT_PRC9522L(hw->port),
3142                             pf->offset_loaded, &os->rx_size_big,
3143                             &ns->rx_size_big);
3144         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3145                             pf->offset_loaded, &os->rx_undersize,
3146                             &ns->rx_undersize);
3147         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3148                             pf->offset_loaded, &os->rx_fragments,
3149                             &ns->rx_fragments);
3150         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3151                             pf->offset_loaded, &os->rx_oversize,
3152                             &ns->rx_oversize);
3153         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3154                             pf->offset_loaded, &os->rx_jabber,
3155                             &ns->rx_jabber);
3156         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3157                             I40E_GLPRT_PTC64L(hw->port),
3158                             pf->offset_loaded, &os->tx_size_64,
3159                             &ns->tx_size_64);
3160         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3161                             I40E_GLPRT_PTC127L(hw->port),
3162                             pf->offset_loaded, &os->tx_size_127,
3163                             &ns->tx_size_127);
3164         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3165                             I40E_GLPRT_PTC255L(hw->port),
3166                             pf->offset_loaded, &os->tx_size_255,
3167                             &ns->tx_size_255);
3168         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3169                             I40E_GLPRT_PTC511L(hw->port),
3170                             pf->offset_loaded, &os->tx_size_511,
3171                             &ns->tx_size_511);
3172         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3173                             I40E_GLPRT_PTC1023L(hw->port),
3174                             pf->offset_loaded, &os->tx_size_1023,
3175                             &ns->tx_size_1023);
3176         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3177                             I40E_GLPRT_PTC1522L(hw->port),
3178                             pf->offset_loaded, &os->tx_size_1522,
3179                             &ns->tx_size_1522);
3180         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3181                             I40E_GLPRT_PTC9522L(hw->port),
3182                             pf->offset_loaded, &os->tx_size_big,
3183                             &ns->tx_size_big);
3184         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3185                            pf->offset_loaded,
3186                            &os->fd_sb_match, &ns->fd_sb_match);
3187         /* GLPRT_MSPDC not supported */
3188         /* GLPRT_XEC not supported */
3189
3190         pf->offset_loaded = true;
3191
3192         if (pf->main_vsi)
3193                 i40e_update_vsi_stats(pf->main_vsi);
3194 }
3195
3196 /* Get all statistics of a port */
3197 static int
3198 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3199 {
3200         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3203         struct i40e_vsi *vsi;
3204         unsigned i;
3205
3206         /* call read registers - updates values, now write them to struct */
3207         i40e_read_stats_registers(pf, hw);
3208
3209         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3210                         pf->main_vsi->eth_stats.rx_multicast +
3211                         pf->main_vsi->eth_stats.rx_broadcast -
3212                         pf->main_vsi->eth_stats.rx_discards;
3213         stats->opackets = ns->eth.tx_unicast +
3214                         ns->eth.tx_multicast +
3215                         ns->eth.tx_broadcast;
3216         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3217         stats->obytes   = ns->eth.tx_bytes;
3218         stats->oerrors  = ns->eth.tx_errors +
3219                         pf->main_vsi->eth_stats.tx_errors;
3220
3221         /* Rx Errors */
3222         stats->imissed  = ns->eth.rx_discards +
3223                         pf->main_vsi->eth_stats.rx_discards;
3224         stats->ierrors  = ns->crc_errors +
3225                         ns->rx_length_errors + ns->rx_undersize +
3226                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3227
3228         if (pf->vfs) {
3229                 for (i = 0; i < pf->vf_num; i++) {
3230                         vsi = pf->vfs[i].vsi;
3231                         i40e_update_vsi_stats(vsi);
3232
3233                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3234                                         vsi->eth_stats.rx_multicast +
3235                                         vsi->eth_stats.rx_broadcast -
3236                                         vsi->eth_stats.rx_discards);
3237                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3238                         stats->oerrors  += vsi->eth_stats.tx_errors;
3239                         stats->imissed  += vsi->eth_stats.rx_discards;
3240                 }
3241         }
3242
3243         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3244         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3245         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3246         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3247         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3248         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3249         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3250                     ns->eth.rx_unknown_protocol);
3251         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3252         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3253         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3254         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3255         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3256         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3257
3258         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3259                     ns->tx_dropped_link_down);
3260         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3261         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3262                     ns->illegal_bytes);
3263         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3264         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3265                     ns->mac_local_faults);
3266         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3267                     ns->mac_remote_faults);
3268         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3269                     ns->rx_length_errors);
3270         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3271         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3272         for (i = 0; i < 8; i++) {
3273                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3274                                 i, ns->priority_xon_rx[i]);
3275                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3276                                 i, ns->priority_xoff_rx[i]);
3277         }
3278         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3279         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3280         for (i = 0; i < 8; i++) {
3281                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3282                                 i, ns->priority_xon_tx[i]);
3283                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3284                                 i, ns->priority_xoff_tx[i]);
3285                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3286                                 i, ns->priority_xon_2_xoff[i]);
3287         }
3288         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3289         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3290         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3291         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3292         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3293         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3294         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3295         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3296         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3297         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3298         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3299         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3300         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3301         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3302         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3303         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3304         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3305         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3306         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3307                         ns->mac_short_packet_dropped);
3308         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3309                     ns->checksum_error);
3310         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3311         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3312         return 0;
3313 }
3314
3315 /* Reset the statistics */
3316 static void
3317 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3318 {
3319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3321
3322         /* Mark PF and VSI stats to update the offset, aka "reset" */
3323         pf->offset_loaded = false;
3324         if (pf->main_vsi)
3325                 pf->main_vsi->offset_loaded = false;
3326
3327         /* read the stats, reading current register values into offset */
3328         i40e_read_stats_registers(pf, hw);
3329 }
3330
3331 static uint32_t
3332 i40e_xstats_calc_num(void)
3333 {
3334         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3335                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3336                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3337 }
3338
3339 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3340                                      struct rte_eth_xstat_name *xstats_names,
3341                                      __rte_unused unsigned limit)
3342 {
3343         unsigned count = 0;
3344         unsigned i, prio;
3345
3346         if (xstats_names == NULL)
3347                 return i40e_xstats_calc_num();
3348
3349         /* Note: limit checked in rte_eth_xstats_names() */
3350
3351         /* Get stats from i40e_eth_stats struct */
3352         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3353                 strlcpy(xstats_names[count].name,
3354                         rte_i40e_stats_strings[i].name,
3355                         sizeof(xstats_names[count].name));
3356                 count++;
3357         }
3358
3359         /* Get individiual stats from i40e_hw_port struct */
3360         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3361                 strlcpy(xstats_names[count].name,
3362                         rte_i40e_hw_port_strings[i].name,
3363                         sizeof(xstats_names[count].name));
3364                 count++;
3365         }
3366
3367         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3368                 for (prio = 0; prio < 8; prio++) {
3369                         snprintf(xstats_names[count].name,
3370                                  sizeof(xstats_names[count].name),
3371                                  "rx_priority%u_%s", prio,
3372                                  rte_i40e_rxq_prio_strings[i].name);
3373                         count++;
3374                 }
3375         }
3376
3377         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3378                 for (prio = 0; prio < 8; prio++) {
3379                         snprintf(xstats_names[count].name,
3380                                  sizeof(xstats_names[count].name),
3381                                  "tx_priority%u_%s", prio,
3382                                  rte_i40e_txq_prio_strings[i].name);
3383                         count++;
3384                 }
3385         }
3386         return count;
3387 }
3388
3389 static int
3390 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3391                     unsigned n)
3392 {
3393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3395         unsigned i, count, prio;
3396         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3397
3398         count = i40e_xstats_calc_num();
3399         if (n < count)
3400                 return count;
3401
3402         i40e_read_stats_registers(pf, hw);
3403
3404         if (xstats == NULL)
3405                 return 0;
3406
3407         count = 0;
3408
3409         /* Get stats from i40e_eth_stats struct */
3410         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3411                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3412                         rte_i40e_stats_strings[i].offset);
3413                 xstats[count].id = count;
3414                 count++;
3415         }
3416
3417         /* Get individiual stats from i40e_hw_port struct */
3418         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3419                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3420                         rte_i40e_hw_port_strings[i].offset);
3421                 xstats[count].id = count;
3422                 count++;
3423         }
3424
3425         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3426                 for (prio = 0; prio < 8; prio++) {
3427                         xstats[count].value =
3428                                 *(uint64_t *)(((char *)hw_stats) +
3429                                 rte_i40e_rxq_prio_strings[i].offset +
3430                                 (sizeof(uint64_t) * prio));
3431                         xstats[count].id = count;
3432                         count++;
3433                 }
3434         }
3435
3436         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3437                 for (prio = 0; prio < 8; prio++) {
3438                         xstats[count].value =
3439                                 *(uint64_t *)(((char *)hw_stats) +
3440                                 rte_i40e_txq_prio_strings[i].offset +
3441                                 (sizeof(uint64_t) * prio));
3442                         xstats[count].id = count;
3443                         count++;
3444                 }
3445         }
3446
3447         return count;
3448 }
3449
3450 static int
3451 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3452 {
3453         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454         u32 full_ver;
3455         u8 ver, patch;
3456         u16 build;
3457         int ret;
3458
3459         full_ver = hw->nvm.oem_ver;
3460         ver = (u8)(full_ver >> 24);
3461         build = (u16)((full_ver >> 8) & 0xffff);
3462         patch = (u8)(full_ver & 0xff);
3463
3464         ret = snprintf(fw_version, fw_size,
3465                  "%d.%d%d 0x%08x %d.%d.%d",
3466                  ((hw->nvm.version >> 12) & 0xf),
3467                  ((hw->nvm.version >> 4) & 0xff),
3468                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3469                  ver, build, patch);
3470
3471         ret += 1; /* add the size of '\0' */
3472         if (fw_size < (u32)ret)
3473                 return ret;
3474         else
3475                 return 0;
3476 }
3477
3478 /*
3479  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3480  * the Rx data path does not hang if the FW LLDP is stopped.
3481  * return true if lldp need to stop
3482  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3483  */
3484 static bool
3485 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3486 {
3487         double nvm_ver;
3488         char ver_str[64] = {0};
3489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3490
3491         i40e_fw_version_get(dev, ver_str, 64);
3492         nvm_ver = atof(ver_str);
3493         if ((hw->mac.type == I40E_MAC_X722 ||
3494              hw->mac.type == I40E_MAC_X722_VF) &&
3495              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3496                 return true;
3497         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3498                 return true;
3499
3500         return false;
3501 }
3502
3503 static int
3504 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3505 {
3506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3507         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3508         struct i40e_vsi *vsi = pf->main_vsi;
3509         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3510
3511         dev_info->max_rx_queues = vsi->nb_qps;
3512         dev_info->max_tx_queues = vsi->nb_qps;
3513         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3514         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3515         dev_info->max_mac_addrs = vsi->max_macaddrs;
3516         dev_info->max_vfs = pci_dev->max_vfs;
3517         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3518         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3519         dev_info->rx_queue_offload_capa = 0;
3520         dev_info->rx_offload_capa =
3521                 DEV_RX_OFFLOAD_VLAN_STRIP |
3522                 DEV_RX_OFFLOAD_QINQ_STRIP |
3523                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3524                 DEV_RX_OFFLOAD_UDP_CKSUM |
3525                 DEV_RX_OFFLOAD_TCP_CKSUM |
3526                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3527                 DEV_RX_OFFLOAD_KEEP_CRC |
3528                 DEV_RX_OFFLOAD_SCATTER |
3529                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3530                 DEV_RX_OFFLOAD_VLAN_FILTER |
3531                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3532
3533         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3534         dev_info->tx_offload_capa =
3535                 DEV_TX_OFFLOAD_VLAN_INSERT |
3536                 DEV_TX_OFFLOAD_QINQ_INSERT |
3537                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3538                 DEV_TX_OFFLOAD_UDP_CKSUM |
3539                 DEV_TX_OFFLOAD_TCP_CKSUM |
3540                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3541                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3542                 DEV_TX_OFFLOAD_TCP_TSO |
3543                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3544                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3545                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3546                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3547                 DEV_TX_OFFLOAD_MULTI_SEGS |
3548                 dev_info->tx_queue_offload_capa;
3549         dev_info->dev_capa =
3550                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3551                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3552
3553         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3554                                                 sizeof(uint32_t);
3555         dev_info->reta_size = pf->hash_lut_size;
3556         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3557
3558         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3559                 .rx_thresh = {
3560                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3561                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3562                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3563                 },
3564                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3565                 .rx_drop_en = 0,
3566                 .offloads = 0,
3567         };
3568
3569         dev_info->default_txconf = (struct rte_eth_txconf) {
3570                 .tx_thresh = {
3571                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3572                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3573                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3574                 },
3575                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3576                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3577                 .offloads = 0,
3578         };
3579
3580         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3581                 .nb_max = I40E_MAX_RING_DESC,
3582                 .nb_min = I40E_MIN_RING_DESC,
3583                 .nb_align = I40E_ALIGN_RING_DESC,
3584         };
3585
3586         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3587                 .nb_max = I40E_MAX_RING_DESC,
3588                 .nb_min = I40E_MIN_RING_DESC,
3589                 .nb_align = I40E_ALIGN_RING_DESC,
3590                 .nb_seg_max = I40E_TX_MAX_SEG,
3591                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3592         };
3593
3594         if (pf->flags & I40E_FLAG_VMDQ) {
3595                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3596                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3597                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3598                                                 pf->max_nb_vmdq_vsi;
3599                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3600                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3601                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3602         }
3603
3604         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3605                 /* For XL710 */
3606                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3607                 dev_info->default_rxportconf.nb_queues = 2;
3608                 dev_info->default_txportconf.nb_queues = 2;
3609                 if (dev->data->nb_rx_queues == 1)
3610                         dev_info->default_rxportconf.ring_size = 2048;
3611                 else
3612                         dev_info->default_rxportconf.ring_size = 1024;
3613                 if (dev->data->nb_tx_queues == 1)
3614                         dev_info->default_txportconf.ring_size = 1024;
3615                 else
3616                         dev_info->default_txportconf.ring_size = 512;
3617
3618         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3619                 /* For XXV710 */
3620                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3621                 dev_info->default_rxportconf.nb_queues = 1;
3622                 dev_info->default_txportconf.nb_queues = 1;
3623                 dev_info->default_rxportconf.ring_size = 256;
3624                 dev_info->default_txportconf.ring_size = 256;
3625         } else {
3626                 /* For X710 */
3627                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3628                 dev_info->default_rxportconf.nb_queues = 1;
3629                 dev_info->default_txportconf.nb_queues = 1;
3630                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3631                         dev_info->default_rxportconf.ring_size = 512;
3632                         dev_info->default_txportconf.ring_size = 256;
3633                 } else {
3634                         dev_info->default_rxportconf.ring_size = 256;
3635                         dev_info->default_txportconf.ring_size = 256;
3636                 }
3637         }
3638         dev_info->default_rxportconf.burst_size = 32;
3639         dev_info->default_txportconf.burst_size = 32;
3640
3641         return 0;
3642 }
3643
3644 static int
3645 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3646 {
3647         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3648         struct i40e_vsi *vsi = pf->main_vsi;
3649         PMD_INIT_FUNC_TRACE();
3650
3651         if (on)
3652                 return i40e_vsi_add_vlan(vsi, vlan_id);
3653         else
3654                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3655 }
3656
3657 static int
3658 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3659                                 enum rte_vlan_type vlan_type,
3660                                 uint16_t tpid, int qinq)
3661 {
3662         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3663         uint64_t reg_r = 0;
3664         uint64_t reg_w = 0;
3665         uint16_t reg_id = 3;
3666         int ret;
3667
3668         if (qinq) {
3669                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3670                         reg_id = 2;
3671         }
3672
3673         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3674                                           &reg_r, NULL);
3675         if (ret != I40E_SUCCESS) {
3676                 PMD_DRV_LOG(ERR,
3677                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3678                            reg_id);
3679                 return -EIO;
3680         }
3681         PMD_DRV_LOG(DEBUG,
3682                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3683                     reg_id, reg_r);
3684
3685         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3686         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3687         if (reg_r == reg_w) {
3688                 PMD_DRV_LOG(DEBUG, "No need to write");
3689                 return 0;
3690         }
3691
3692         ret = i40e_aq_debug_write_global_register(hw,
3693                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3694                                            reg_w, NULL);
3695         if (ret != I40E_SUCCESS) {
3696                 PMD_DRV_LOG(ERR,
3697                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3698                             reg_id);
3699                 return -EIO;
3700         }
3701         PMD_DRV_LOG(DEBUG,
3702                     "Global register 0x%08x is changed with value 0x%08x",
3703                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3704
3705         return 0;
3706 }
3707
3708 static int
3709 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3710                    enum rte_vlan_type vlan_type,
3711                    uint16_t tpid)
3712 {
3713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3715         int qinq = dev->data->dev_conf.rxmode.offloads &
3716                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3717         int ret = 0;
3718
3719         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3720              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3721             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3722                 PMD_DRV_LOG(ERR,
3723                             "Unsupported vlan type.");
3724                 return -EINVAL;
3725         }
3726
3727         if (pf->support_multi_driver) {
3728                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3729                 return -ENOTSUP;
3730         }
3731
3732         /* 802.1ad frames ability is added in NVM API 1.7*/
3733         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3734                 if (qinq) {
3735                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3736                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3737                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3738                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3739                 } else {
3740                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3741                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3742                 }
3743                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3744                 if (ret != I40E_SUCCESS) {
3745                         PMD_DRV_LOG(ERR,
3746                                     "Set switch config failed aq_err: %d",
3747                                     hw->aq.asq_last_status);
3748                         ret = -EIO;
3749                 }
3750         } else
3751                 /* If NVM API < 1.7, keep the register setting */
3752                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3753                                                       tpid, qinq);
3754
3755         return ret;
3756 }
3757
3758 static int
3759 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3760 {
3761         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3762         struct i40e_vsi *vsi = pf->main_vsi;
3763         struct rte_eth_rxmode *rxmode;
3764
3765         rxmode = &dev->data->dev_conf.rxmode;
3766         if (mask & ETH_VLAN_FILTER_MASK) {
3767                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3768                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3769                 else
3770                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3771         }
3772
3773         if (mask & ETH_VLAN_STRIP_MASK) {
3774                 /* Enable or disable VLAN stripping */
3775                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3776                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3777                 else
3778                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3779         }
3780
3781         if (mask & ETH_VLAN_EXTEND_MASK) {
3782                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3783                         i40e_vsi_config_double_vlan(vsi, TRUE);
3784                         /* Set global registers with default ethertype. */
3785                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3786                                            RTE_ETHER_TYPE_VLAN);
3787                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3788                                            RTE_ETHER_TYPE_VLAN);
3789                 }
3790                 else
3791                         i40e_vsi_config_double_vlan(vsi, FALSE);
3792         }
3793
3794         return 0;
3795 }
3796
3797 static void
3798 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3799                           __rte_unused uint16_t queue,
3800                           __rte_unused int on)
3801 {
3802         PMD_INIT_FUNC_TRACE();
3803 }
3804
3805 static int
3806 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3807 {
3808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3809         struct i40e_vsi *vsi = pf->main_vsi;
3810         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3811         struct i40e_vsi_vlan_pvid_info info;
3812
3813         memset(&info, 0, sizeof(info));
3814         info.on = on;
3815         if (info.on)
3816                 info.config.pvid = pvid;
3817         else {
3818                 info.config.reject.tagged =
3819                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3820                 info.config.reject.untagged =
3821                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3822         }
3823
3824         return i40e_vsi_vlan_pvid_set(vsi, &info);
3825 }
3826
3827 static int
3828 i40e_dev_led_on(struct rte_eth_dev *dev)
3829 {
3830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3831         uint32_t mode = i40e_led_get(hw);
3832
3833         if (mode == 0)
3834                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3835
3836         return 0;
3837 }
3838
3839 static int
3840 i40e_dev_led_off(struct rte_eth_dev *dev)
3841 {
3842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3843         uint32_t mode = i40e_led_get(hw);
3844
3845         if (mode != 0)
3846                 i40e_led_set(hw, 0, false);
3847
3848         return 0;
3849 }
3850
3851 static int
3852 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3853 {
3854         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3856
3857         fc_conf->pause_time = pf->fc_conf.pause_time;
3858
3859         /* read out from register, in case they are modified by other port */
3860         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3861                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3862         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3863                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3864
3865         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3866         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3867
3868          /* Return current mode according to actual setting*/
3869         switch (hw->fc.current_mode) {
3870         case I40E_FC_FULL:
3871                 fc_conf->mode = RTE_FC_FULL;
3872                 break;
3873         case I40E_FC_TX_PAUSE:
3874                 fc_conf->mode = RTE_FC_TX_PAUSE;
3875                 break;
3876         case I40E_FC_RX_PAUSE:
3877                 fc_conf->mode = RTE_FC_RX_PAUSE;
3878                 break;
3879         case I40E_FC_NONE:
3880         default:
3881                 fc_conf->mode = RTE_FC_NONE;
3882         };
3883
3884         return 0;
3885 }
3886
3887 static int
3888 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3889 {
3890         uint32_t mflcn_reg, fctrl_reg, reg;
3891         uint32_t max_high_water;
3892         uint8_t i, aq_failure;
3893         int err;
3894         struct i40e_hw *hw;
3895         struct i40e_pf *pf;
3896         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3897                 [RTE_FC_NONE] = I40E_FC_NONE,
3898                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3899                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3900                 [RTE_FC_FULL] = I40E_FC_FULL
3901         };
3902
3903         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3904
3905         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3906         if ((fc_conf->high_water > max_high_water) ||
3907                         (fc_conf->high_water < fc_conf->low_water)) {
3908                 PMD_INIT_LOG(ERR,
3909                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3910                         max_high_water);
3911                 return -EINVAL;
3912         }
3913
3914         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3915         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3916         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3917
3918         pf->fc_conf.pause_time = fc_conf->pause_time;
3919         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3920         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3921
3922         PMD_INIT_FUNC_TRACE();
3923
3924         /* All the link flow control related enable/disable register
3925          * configuration is handle by the F/W
3926          */
3927         err = i40e_set_fc(hw, &aq_failure, true);
3928         if (err < 0)
3929                 return -ENOSYS;
3930
3931         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3932                 /* Configure flow control refresh threshold,
3933                  * the value for stat_tx_pause_refresh_timer[8]
3934                  * is used for global pause operation.
3935                  */
3936
3937                 I40E_WRITE_REG(hw,
3938                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3939                                pf->fc_conf.pause_time);
3940
3941                 /* configure the timer value included in transmitted pause
3942                  * frame,
3943                  * the value for stat_tx_pause_quanta[8] is used for global
3944                  * pause operation
3945                  */
3946                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3947                                pf->fc_conf.pause_time);
3948
3949                 fctrl_reg = I40E_READ_REG(hw,
3950                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3951
3952                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3953                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3954                 else
3955                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3956
3957                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3958                                fctrl_reg);
3959         } else {
3960                 /* Configure pause time (2 TCs per register) */
3961                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3962                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3963                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3964
3965                 /* Configure flow control refresh threshold value */
3966                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3967                                pf->fc_conf.pause_time / 2);
3968
3969                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3970
3971                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3972                  *depending on configuration
3973                  */
3974                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3975                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3976                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3977                 } else {
3978                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3979                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3980                 }
3981
3982                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3983         }
3984
3985         if (!pf->support_multi_driver) {
3986                 /* config water marker both based on the packets and bytes */
3987                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3988                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3989                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3990                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3991                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3992                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3993                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3994                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3995                                   << I40E_KILOSHIFT);
3996                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3997                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3998                                    << I40E_KILOSHIFT);
3999         } else {
4000                 PMD_DRV_LOG(ERR,
4001                             "Water marker configuration is not supported.");
4002         }
4003
4004         I40E_WRITE_FLUSH(hw);
4005
4006         return 0;
4007 }
4008
4009 static int
4010 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4011                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4012 {
4013         PMD_INIT_FUNC_TRACE();
4014
4015         return -ENOSYS;
4016 }
4017
4018 /* Add a MAC address, and update filters */
4019 static int
4020 i40e_macaddr_add(struct rte_eth_dev *dev,
4021                  struct rte_ether_addr *mac_addr,
4022                  __rte_unused uint32_t index,
4023                  uint32_t pool)
4024 {
4025         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4026         struct i40e_mac_filter_info mac_filter;
4027         struct i40e_vsi *vsi;
4028         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4029         int ret;
4030
4031         /* If VMDQ not enabled or configured, return */
4032         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4033                           !pf->nb_cfg_vmdq_vsi)) {
4034                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4035                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4036                         pool);
4037                 return -ENOTSUP;
4038         }
4039
4040         if (pool > pf->nb_cfg_vmdq_vsi) {
4041                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4042                                 pool, pf->nb_cfg_vmdq_vsi);
4043                 return -EINVAL;
4044         }
4045
4046         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4047         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4048                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4049         else
4050                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4051
4052         if (pool == 0)
4053                 vsi = pf->main_vsi;
4054         else
4055                 vsi = pf->vmdq[pool - 1].vsi;
4056
4057         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4058         if (ret != I40E_SUCCESS) {
4059                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4060                 return -ENODEV;
4061         }
4062         return 0;
4063 }
4064
4065 /* Remove a MAC address, and update filters */
4066 static void
4067 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4068 {
4069         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4070         struct i40e_vsi *vsi;
4071         struct rte_eth_dev_data *data = dev->data;
4072         struct rte_ether_addr *macaddr;
4073         int ret;
4074         uint32_t i;
4075         uint64_t pool_sel;
4076
4077         macaddr = &(data->mac_addrs[index]);
4078
4079         pool_sel = dev->data->mac_pool_sel[index];
4080
4081         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4082                 if (pool_sel & (1ULL << i)) {
4083                         if (i == 0)
4084                                 vsi = pf->main_vsi;
4085                         else {
4086                                 /* No VMDQ pool enabled or configured */
4087                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4088                                         (i > pf->nb_cfg_vmdq_vsi)) {
4089                                         PMD_DRV_LOG(ERR,
4090                                                 "No VMDQ pool enabled/configured");
4091                                         return;
4092                                 }
4093                                 vsi = pf->vmdq[i - 1].vsi;
4094                         }
4095                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4096
4097                         if (ret) {
4098                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4099                                 return;
4100                         }
4101                 }
4102         }
4103 }
4104
4105 /* Set perfect match or hash match of MAC and VLAN for a VF */
4106 static int
4107 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4108                  struct rte_eth_mac_filter *filter,
4109                  bool add)
4110 {
4111         struct i40e_hw *hw;
4112         struct i40e_mac_filter_info mac_filter;
4113         struct rte_ether_addr old_mac;
4114         struct rte_ether_addr *new_mac;
4115         struct i40e_pf_vf *vf = NULL;
4116         uint16_t vf_id;
4117         int ret;
4118
4119         if (pf == NULL) {
4120                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4121                 return -EINVAL;
4122         }
4123         hw = I40E_PF_TO_HW(pf);
4124
4125         if (filter == NULL) {
4126                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4127                 return -EINVAL;
4128         }
4129
4130         new_mac = &filter->mac_addr;
4131
4132         if (rte_is_zero_ether_addr(new_mac)) {
4133                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4134                 return -EINVAL;
4135         }
4136
4137         vf_id = filter->dst_id;
4138
4139         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4140                 PMD_DRV_LOG(ERR, "Invalid argument.");
4141                 return -EINVAL;
4142         }
4143         vf = &pf->vfs[vf_id];
4144
4145         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4146                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4147                 return -EINVAL;
4148         }
4149
4150         if (add) {
4151                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4152                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4153                                 RTE_ETHER_ADDR_LEN);
4154                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4155                                  RTE_ETHER_ADDR_LEN);
4156
4157                 mac_filter.filter_type = filter->filter_type;
4158                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4159                 if (ret != I40E_SUCCESS) {
4160                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4161                         return -1;
4162                 }
4163                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4164         } else {
4165                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4166                                 RTE_ETHER_ADDR_LEN);
4167                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4168                 if (ret != I40E_SUCCESS) {
4169                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4170                         return -1;
4171                 }
4172
4173                 /* Clear device address as it has been removed */
4174                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4175                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4176         }
4177
4178         return 0;
4179 }
4180
4181 /* MAC filter handle */
4182 static int
4183 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4184                 void *arg)
4185 {
4186         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4187         struct rte_eth_mac_filter *filter;
4188         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4189         int ret = I40E_NOT_SUPPORTED;
4190
4191         filter = (struct rte_eth_mac_filter *)(arg);
4192
4193         switch (filter_op) {
4194         case RTE_ETH_FILTER_NOP:
4195                 ret = I40E_SUCCESS;
4196                 break;
4197         case RTE_ETH_FILTER_ADD:
4198                 i40e_pf_disable_irq0(hw);
4199                 if (filter->is_vf)
4200                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4201                 i40e_pf_enable_irq0(hw);
4202                 break;
4203         case RTE_ETH_FILTER_DELETE:
4204                 i40e_pf_disable_irq0(hw);
4205                 if (filter->is_vf)
4206                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4207                 i40e_pf_enable_irq0(hw);
4208                 break;
4209         default:
4210                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4211                 ret = I40E_ERR_PARAM;
4212                 break;
4213         }
4214
4215         return ret;
4216 }
4217
4218 static int
4219 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4220 {
4221         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4222         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4223         uint32_t reg;
4224         int ret;
4225
4226         if (!lut)
4227                 return -EINVAL;
4228
4229         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4230                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4231                                           vsi->type != I40E_VSI_SRIOV,
4232                                           lut, lut_size);
4233                 if (ret) {
4234                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4235                         return ret;
4236                 }
4237         } else {
4238                 uint32_t *lut_dw = (uint32_t *)lut;
4239                 uint16_t i, lut_size_dw = lut_size / 4;
4240
4241                 if (vsi->type == I40E_VSI_SRIOV) {
4242                         for (i = 0; i <= lut_size_dw; i++) {
4243                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4244                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4245                         }
4246                 } else {
4247                         for (i = 0; i < lut_size_dw; i++)
4248                                 lut_dw[i] = I40E_READ_REG(hw,
4249                                                           I40E_PFQF_HLUT(i));
4250                 }
4251         }
4252
4253         return 0;
4254 }
4255
4256 int
4257 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4258 {
4259         struct i40e_pf *pf;
4260         struct i40e_hw *hw;
4261         int ret;
4262
4263         if (!vsi || !lut)
4264                 return -EINVAL;
4265
4266         pf = I40E_VSI_TO_PF(vsi);
4267         hw = I40E_VSI_TO_HW(vsi);
4268
4269         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4270                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4271                                           vsi->type != I40E_VSI_SRIOV,
4272                                           lut, lut_size);
4273                 if (ret) {
4274                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4275                         return ret;
4276                 }
4277         } else {
4278                 uint32_t *lut_dw = (uint32_t *)lut;
4279                 uint16_t i, lut_size_dw = lut_size / 4;
4280
4281                 if (vsi->type == I40E_VSI_SRIOV) {
4282                         for (i = 0; i < lut_size_dw; i++)
4283                                 I40E_WRITE_REG(
4284                                         hw,
4285                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4286                                         lut_dw[i]);
4287                 } else {
4288                         for (i = 0; i < lut_size_dw; i++)
4289                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4290                                                lut_dw[i]);
4291                 }
4292                 I40E_WRITE_FLUSH(hw);
4293         }
4294
4295         return 0;
4296 }
4297
4298 static int
4299 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4300                          struct rte_eth_rss_reta_entry64 *reta_conf,
4301                          uint16_t reta_size)
4302 {
4303         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4304         uint16_t i, lut_size = pf->hash_lut_size;
4305         uint16_t idx, shift;
4306         uint8_t *lut;
4307         int ret;
4308
4309         if (reta_size != lut_size ||
4310                 reta_size > ETH_RSS_RETA_SIZE_512) {
4311                 PMD_DRV_LOG(ERR,
4312                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4313                         reta_size, lut_size);
4314                 return -EINVAL;
4315         }
4316
4317         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4318         if (!lut) {
4319                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4320                 return -ENOMEM;
4321         }
4322         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4323         if (ret)
4324                 goto out;
4325         for (i = 0; i < reta_size; i++) {
4326                 idx = i / RTE_RETA_GROUP_SIZE;
4327                 shift = i % RTE_RETA_GROUP_SIZE;
4328                 if (reta_conf[idx].mask & (1ULL << shift))
4329                         lut[i] = reta_conf[idx].reta[shift];
4330         }
4331         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4332
4333         pf->adapter->rss_reta_updated = 1;
4334
4335 out:
4336         rte_free(lut);
4337
4338         return ret;
4339 }
4340
4341 static int
4342 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4343                         struct rte_eth_rss_reta_entry64 *reta_conf,
4344                         uint16_t reta_size)
4345 {
4346         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4347         uint16_t i, lut_size = pf->hash_lut_size;
4348         uint16_t idx, shift;
4349         uint8_t *lut;
4350         int ret;
4351
4352         if (reta_size != lut_size ||
4353                 reta_size > ETH_RSS_RETA_SIZE_512) {
4354                 PMD_DRV_LOG(ERR,
4355                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4356                         reta_size, lut_size);
4357                 return -EINVAL;
4358         }
4359
4360         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4361         if (!lut) {
4362                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4363                 return -ENOMEM;
4364         }
4365
4366         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4367         if (ret)
4368                 goto out;
4369         for (i = 0; i < reta_size; i++) {
4370                 idx = i / RTE_RETA_GROUP_SIZE;
4371                 shift = i % RTE_RETA_GROUP_SIZE;
4372                 if (reta_conf[idx].mask & (1ULL << shift))
4373                         reta_conf[idx].reta[shift] = lut[i];
4374         }
4375
4376 out:
4377         rte_free(lut);
4378
4379         return ret;
4380 }
4381
4382 /**
4383  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4384  * @hw:   pointer to the HW structure
4385  * @mem:  pointer to mem struct to fill out
4386  * @size: size of memory requested
4387  * @alignment: what to align the allocation to
4388  **/
4389 enum i40e_status_code
4390 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4391                         struct i40e_dma_mem *mem,
4392                         u64 size,
4393                         u32 alignment)
4394 {
4395         const struct rte_memzone *mz = NULL;
4396         char z_name[RTE_MEMZONE_NAMESIZE];
4397
4398         if (!mem)
4399                 return I40E_ERR_PARAM;
4400
4401         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4402         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4403                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4404         if (!mz)
4405                 return I40E_ERR_NO_MEMORY;
4406
4407         mem->size = size;
4408         mem->va = mz->addr;
4409         mem->pa = mz->iova;
4410         mem->zone = (const void *)mz;
4411         PMD_DRV_LOG(DEBUG,
4412                 "memzone %s allocated with physical address: %"PRIu64,
4413                 mz->name, mem->pa);
4414
4415         return I40E_SUCCESS;
4416 }
4417
4418 /**
4419  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4420  * @hw:   pointer to the HW structure
4421  * @mem:  ptr to mem struct to free
4422  **/
4423 enum i40e_status_code
4424 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4425                     struct i40e_dma_mem *mem)
4426 {
4427         if (!mem)
4428                 return I40E_ERR_PARAM;
4429
4430         PMD_DRV_LOG(DEBUG,
4431                 "memzone %s to be freed with physical address: %"PRIu64,
4432                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4433         rte_memzone_free((const struct rte_memzone *)mem->zone);
4434         mem->zone = NULL;
4435         mem->va = NULL;
4436         mem->pa = (u64)0;
4437
4438         return I40E_SUCCESS;
4439 }
4440
4441 /**
4442  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4443  * @hw:   pointer to the HW structure
4444  * @mem:  pointer to mem struct to fill out
4445  * @size: size of memory requested
4446  **/
4447 enum i40e_status_code
4448 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4449                          struct i40e_virt_mem *mem,
4450                          u32 size)
4451 {
4452         if (!mem)
4453                 return I40E_ERR_PARAM;
4454
4455         mem->size = size;
4456         mem->va = rte_zmalloc("i40e", size, 0);
4457
4458         if (mem->va)
4459                 return I40E_SUCCESS;
4460         else
4461                 return I40E_ERR_NO_MEMORY;
4462 }
4463
4464 /**
4465  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4466  * @hw:   pointer to the HW structure
4467  * @mem:  pointer to mem struct to free
4468  **/
4469 enum i40e_status_code
4470 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4471                      struct i40e_virt_mem *mem)
4472 {
4473         if (!mem)
4474                 return I40E_ERR_PARAM;
4475
4476         rte_free(mem->va);
4477         mem->va = NULL;
4478
4479         return I40E_SUCCESS;
4480 }
4481
4482 void
4483 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4484 {
4485         rte_spinlock_init(&sp->spinlock);
4486 }
4487
4488 void
4489 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4490 {
4491         rte_spinlock_lock(&sp->spinlock);
4492 }
4493
4494 void
4495 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4496 {
4497         rte_spinlock_unlock(&sp->spinlock);
4498 }
4499
4500 void
4501 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4502 {
4503         return;
4504 }
4505
4506 /**
4507  * Get the hardware capabilities, which will be parsed
4508  * and saved into struct i40e_hw.
4509  */
4510 static int
4511 i40e_get_cap(struct i40e_hw *hw)
4512 {
4513         struct i40e_aqc_list_capabilities_element_resp *buf;
4514         uint16_t len, size = 0;
4515         int ret;
4516
4517         /* Calculate a huge enough buff for saving response data temporarily */
4518         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4519                                                 I40E_MAX_CAP_ELE_NUM;
4520         buf = rte_zmalloc("i40e", len, 0);
4521         if (!buf) {
4522                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4523                 return I40E_ERR_NO_MEMORY;
4524         }
4525
4526         /* Get, parse the capabilities and save it to hw */
4527         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4528                         i40e_aqc_opc_list_func_capabilities, NULL);
4529         if (ret != I40E_SUCCESS)
4530                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4531
4532         /* Free the temporary buffer after being used */
4533         rte_free(buf);
4534
4535         return ret;
4536 }
4537
4538 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4539
4540 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4541                 const char *value,
4542                 void *opaque)
4543 {
4544         struct i40e_pf *pf;
4545         unsigned long num;
4546         char *end;
4547
4548         pf = (struct i40e_pf *)opaque;
4549         RTE_SET_USED(key);
4550
4551         errno = 0;
4552         num = strtoul(value, &end, 0);
4553         if (errno != 0 || end == value || *end != 0) {
4554                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4555                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4556                 return -(EINVAL);
4557         }
4558
4559         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4560                 pf->vf_nb_qp_max = (uint16_t)num;
4561         else
4562                 /* here return 0 to make next valid same argument work */
4563                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4564                             "power of 2 and equal or less than 16 !, Now it is "
4565                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4566
4567         return 0;
4568 }
4569
4570 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4571 {
4572         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4573         struct rte_kvargs *kvlist;
4574         int kvargs_count;
4575
4576         /* set default queue number per VF as 4 */
4577         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4578
4579         if (dev->device->devargs == NULL)
4580                 return 0;
4581
4582         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4583         if (kvlist == NULL)
4584                 return -(EINVAL);
4585
4586         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4587         if (!kvargs_count) {
4588                 rte_kvargs_free(kvlist);
4589                 return 0;
4590         }
4591
4592         if (kvargs_count > 1)
4593                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4594                             "the first invalid or last valid one is used !",
4595                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4596
4597         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4598                            i40e_pf_parse_vf_queue_number_handler, pf);
4599
4600         rte_kvargs_free(kvlist);
4601
4602         return 0;
4603 }
4604
4605 static int
4606 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4607 {
4608         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4610         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4611         uint16_t qp_count = 0, vsi_count = 0;
4612
4613         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4614                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4615                 return -EINVAL;
4616         }
4617
4618         i40e_pf_config_vf_rxq_number(dev);
4619
4620         /* Add the parameter init for LFC */
4621         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4622         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4623         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4624
4625         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4626         pf->max_num_vsi = hw->func_caps.num_vsis;
4627         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4628         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4629
4630         /* FDir queue/VSI allocation */
4631         pf->fdir_qp_offset = 0;
4632         if (hw->func_caps.fd) {
4633                 pf->flags |= I40E_FLAG_FDIR;
4634                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4635         } else {
4636                 pf->fdir_nb_qps = 0;
4637         }
4638         qp_count += pf->fdir_nb_qps;
4639         vsi_count += 1;
4640
4641         /* LAN queue/VSI allocation */
4642         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4643         if (!hw->func_caps.rss) {
4644                 pf->lan_nb_qps = 1;
4645         } else {
4646                 pf->flags |= I40E_FLAG_RSS;
4647                 if (hw->mac.type == I40E_MAC_X722)
4648                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4649                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4650         }
4651         qp_count += pf->lan_nb_qps;
4652         vsi_count += 1;
4653
4654         /* VF queue/VSI allocation */
4655         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4656         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4657                 pf->flags |= I40E_FLAG_SRIOV;
4658                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4659                 pf->vf_num = pci_dev->max_vfs;
4660                 PMD_DRV_LOG(DEBUG,
4661                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4662                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4663         } else {
4664                 pf->vf_nb_qps = 0;
4665                 pf->vf_num = 0;
4666         }
4667         qp_count += pf->vf_nb_qps * pf->vf_num;
4668         vsi_count += pf->vf_num;
4669
4670         /* VMDq queue/VSI allocation */
4671         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4672         pf->vmdq_nb_qps = 0;
4673         pf->max_nb_vmdq_vsi = 0;
4674         if (hw->func_caps.vmdq) {
4675                 if (qp_count < hw->func_caps.num_tx_qp &&
4676                         vsi_count < hw->func_caps.num_vsis) {
4677                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4678                                 qp_count) / pf->vmdq_nb_qp_max;
4679
4680                         /* Limit the maximum number of VMDq vsi to the maximum
4681                          * ethdev can support
4682                          */
4683                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4684                                 hw->func_caps.num_vsis - vsi_count);
4685                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4686                                 ETH_64_POOLS);
4687                         if (pf->max_nb_vmdq_vsi) {
4688                                 pf->flags |= I40E_FLAG_VMDQ;
4689                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4690                                 PMD_DRV_LOG(DEBUG,
4691                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4692                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4693                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4694                         } else {
4695                                 PMD_DRV_LOG(INFO,
4696                                         "No enough queues left for VMDq");
4697                         }
4698                 } else {
4699                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4700                 }
4701         }
4702         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4703         vsi_count += pf->max_nb_vmdq_vsi;
4704
4705         if (hw->func_caps.dcb)
4706                 pf->flags |= I40E_FLAG_DCB;
4707
4708         if (qp_count > hw->func_caps.num_tx_qp) {
4709                 PMD_DRV_LOG(ERR,
4710                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4711                         qp_count, hw->func_caps.num_tx_qp);
4712                 return -EINVAL;
4713         }
4714         if (vsi_count > hw->func_caps.num_vsis) {
4715                 PMD_DRV_LOG(ERR,
4716                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4717                         vsi_count, hw->func_caps.num_vsis);
4718                 return -EINVAL;
4719         }
4720
4721         return 0;
4722 }
4723
4724 static int
4725 i40e_pf_get_switch_config(struct i40e_pf *pf)
4726 {
4727         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4728         struct i40e_aqc_get_switch_config_resp *switch_config;
4729         struct i40e_aqc_switch_config_element_resp *element;
4730         uint16_t start_seid = 0, num_reported;
4731         int ret;
4732
4733         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4734                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4735         if (!switch_config) {
4736                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4737                 return -ENOMEM;
4738         }
4739
4740         /* Get the switch configurations */
4741         ret = i40e_aq_get_switch_config(hw, switch_config,
4742                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4743         if (ret != I40E_SUCCESS) {
4744                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4745                 goto fail;
4746         }
4747         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4748         if (num_reported != 1) { /* The number should be 1 */
4749                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4750                 goto fail;
4751         }
4752
4753         /* Parse the switch configuration elements */
4754         element = &(switch_config->element[0]);
4755         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4756                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4757                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4758         } else
4759                 PMD_DRV_LOG(INFO, "Unknown element type");
4760
4761 fail:
4762         rte_free(switch_config);
4763
4764         return ret;
4765 }
4766
4767 static int
4768 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4769                         uint32_t num)
4770 {
4771         struct pool_entry *entry;
4772
4773         if (pool == NULL || num == 0)
4774                 return -EINVAL;
4775
4776         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4777         if (entry == NULL) {
4778                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4779                 return -ENOMEM;
4780         }
4781
4782         /* queue heap initialize */
4783         pool->num_free = num;
4784         pool->num_alloc = 0;
4785         pool->base = base;
4786         LIST_INIT(&pool->alloc_list);
4787         LIST_INIT(&pool->free_list);
4788
4789         /* Initialize element  */
4790         entry->base = 0;
4791         entry->len = num;
4792
4793         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4794         return 0;
4795 }
4796
4797 static void
4798 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4799 {
4800         struct pool_entry *entry, *next_entry;
4801
4802         if (pool == NULL)
4803                 return;
4804
4805         for (entry = LIST_FIRST(&pool->alloc_list);
4806                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4807                         entry = next_entry) {
4808                 LIST_REMOVE(entry, next);
4809                 rte_free(entry);
4810         }
4811
4812         for (entry = LIST_FIRST(&pool->free_list);
4813                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4814                         entry = next_entry) {
4815                 LIST_REMOVE(entry, next);
4816                 rte_free(entry);
4817         }
4818
4819         pool->num_free = 0;
4820         pool->num_alloc = 0;
4821         pool->base = 0;
4822         LIST_INIT(&pool->alloc_list);
4823         LIST_INIT(&pool->free_list);
4824 }
4825
4826 static int
4827 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4828                        uint32_t base)
4829 {
4830         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4831         uint32_t pool_offset;
4832         int insert;
4833
4834         if (pool == NULL) {
4835                 PMD_DRV_LOG(ERR, "Invalid parameter");
4836                 return -EINVAL;
4837         }
4838
4839         pool_offset = base - pool->base;
4840         /* Lookup in alloc list */
4841         LIST_FOREACH(entry, &pool->alloc_list, next) {
4842                 if (entry->base == pool_offset) {
4843                         valid_entry = entry;
4844                         LIST_REMOVE(entry, next);
4845                         break;
4846                 }
4847         }
4848
4849         /* Not find, return */
4850         if (valid_entry == NULL) {
4851                 PMD_DRV_LOG(ERR, "Failed to find entry");
4852                 return -EINVAL;
4853         }
4854
4855         /**
4856          * Found it, move it to free list  and try to merge.
4857          * In order to make merge easier, always sort it by qbase.
4858          * Find adjacent prev and last entries.
4859          */
4860         prev = next = NULL;
4861         LIST_FOREACH(entry, &pool->free_list, next) {
4862                 if (entry->base > valid_entry->base) {
4863                         next = entry;
4864                         break;
4865                 }
4866                 prev = entry;
4867         }
4868
4869         insert = 0;
4870         /* Try to merge with next one*/
4871         if (next != NULL) {
4872                 /* Merge with next one */
4873                 if (valid_entry->base + valid_entry->len == next->base) {
4874                         next->base = valid_entry->base;
4875                         next->len += valid_entry->len;
4876                         rte_free(valid_entry);
4877                         valid_entry = next;
4878                         insert = 1;
4879                 }
4880         }
4881
4882         if (prev != NULL) {
4883                 /* Merge with previous one */
4884                 if (prev->base + prev->len == valid_entry->base) {
4885                         prev->len += valid_entry->len;
4886                         /* If it merge with next one, remove next node */
4887                         if (insert == 1) {
4888                                 LIST_REMOVE(valid_entry, next);
4889                                 rte_free(valid_entry);
4890                         } else {
4891                                 rte_free(valid_entry);
4892                                 insert = 1;
4893                         }
4894                 }
4895         }
4896
4897         /* Not find any entry to merge, insert */
4898         if (insert == 0) {
4899                 if (prev != NULL)
4900                         LIST_INSERT_AFTER(prev, valid_entry, next);
4901                 else if (next != NULL)
4902                         LIST_INSERT_BEFORE(next, valid_entry, next);
4903                 else /* It's empty list, insert to head */
4904                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4905         }
4906
4907         pool->num_free += valid_entry->len;
4908         pool->num_alloc -= valid_entry->len;
4909
4910         return 0;
4911 }
4912
4913 static int
4914 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4915                        uint16_t num)
4916 {
4917         struct pool_entry *entry, *valid_entry;
4918
4919         if (pool == NULL || num == 0) {
4920                 PMD_DRV_LOG(ERR, "Invalid parameter");
4921                 return -EINVAL;
4922         }
4923
4924         if (pool->num_free < num) {
4925                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4926                             num, pool->num_free);
4927                 return -ENOMEM;
4928         }
4929
4930         valid_entry = NULL;
4931         /* Lookup  in free list and find most fit one */
4932         LIST_FOREACH(entry, &pool->free_list, next) {
4933                 if (entry->len >= num) {
4934                         /* Find best one */
4935                         if (entry->len == num) {
4936                                 valid_entry = entry;
4937                                 break;
4938                         }
4939                         if (valid_entry == NULL || valid_entry->len > entry->len)
4940                                 valid_entry = entry;
4941                 }
4942         }
4943
4944         /* Not find one to satisfy the request, return */
4945         if (valid_entry == NULL) {
4946                 PMD_DRV_LOG(ERR, "No valid entry found");
4947                 return -ENOMEM;
4948         }
4949         /**
4950          * The entry have equal queue number as requested,
4951          * remove it from alloc_list.
4952          */
4953         if (valid_entry->len == num) {
4954                 LIST_REMOVE(valid_entry, next);
4955         } else {
4956                 /**
4957                  * The entry have more numbers than requested,
4958                  * create a new entry for alloc_list and minus its
4959                  * queue base and number in free_list.
4960                  */
4961                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4962                 if (entry == NULL) {
4963                         PMD_DRV_LOG(ERR,
4964                                 "Failed to allocate memory for resource pool");
4965                         return -ENOMEM;
4966                 }
4967                 entry->base = valid_entry->base;
4968                 entry->len = num;
4969                 valid_entry->base += num;
4970                 valid_entry->len -= num;
4971                 valid_entry = entry;
4972         }
4973
4974         /* Insert it into alloc list, not sorted */
4975         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4976
4977         pool->num_free -= valid_entry->len;
4978         pool->num_alloc += valid_entry->len;
4979
4980         return valid_entry->base + pool->base;
4981 }
4982
4983 /**
4984  * bitmap_is_subset - Check whether src2 is subset of src1
4985  **/
4986 static inline int
4987 bitmap_is_subset(uint8_t src1, uint8_t src2)
4988 {
4989         return !((src1 ^ src2) & src2);
4990 }
4991
4992 static enum i40e_status_code
4993 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4994 {
4995         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4996
4997         /* If DCB is not supported, only default TC is supported */
4998         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4999                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5000                 return I40E_NOT_SUPPORTED;
5001         }
5002
5003         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5004                 PMD_DRV_LOG(ERR,
5005                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5006                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5007                 return I40E_NOT_SUPPORTED;
5008         }
5009         return I40E_SUCCESS;
5010 }
5011
5012 int
5013 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5014                                 struct i40e_vsi_vlan_pvid_info *info)
5015 {
5016         struct i40e_hw *hw;
5017         struct i40e_vsi_context ctxt;
5018         uint8_t vlan_flags = 0;
5019         int ret;
5020
5021         if (vsi == NULL || info == NULL) {
5022                 PMD_DRV_LOG(ERR, "invalid parameters");
5023                 return I40E_ERR_PARAM;
5024         }
5025
5026         if (info->on) {
5027                 vsi->info.pvid = info->config.pvid;
5028                 /**
5029                  * If insert pvid is enabled, only tagged pkts are
5030                  * allowed to be sent out.
5031                  */
5032                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5033                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5034         } else {
5035                 vsi->info.pvid = 0;
5036                 if (info->config.reject.tagged == 0)
5037                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5038
5039                 if (info->config.reject.untagged == 0)
5040                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5041         }
5042         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5043                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5044         vsi->info.port_vlan_flags |= vlan_flags;
5045         vsi->info.valid_sections =
5046                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5047         memset(&ctxt, 0, sizeof(ctxt));
5048         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5049         ctxt.seid = vsi->seid;
5050
5051         hw = I40E_VSI_TO_HW(vsi);
5052         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5053         if (ret != I40E_SUCCESS)
5054                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5055
5056         return ret;
5057 }
5058
5059 static int
5060 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5061 {
5062         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5063         int i, ret;
5064         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5065
5066         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5067         if (ret != I40E_SUCCESS)
5068                 return ret;
5069
5070         if (!vsi->seid) {
5071                 PMD_DRV_LOG(ERR, "seid not valid");
5072                 return -EINVAL;
5073         }
5074
5075         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5076         tc_bw_data.tc_valid_bits = enabled_tcmap;
5077         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5078                 tc_bw_data.tc_bw_credits[i] =
5079                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5080
5081         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5082         if (ret != I40E_SUCCESS) {
5083                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5084                 return ret;
5085         }
5086
5087         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5088                                         sizeof(vsi->info.qs_handle));
5089         return I40E_SUCCESS;
5090 }
5091
5092 static enum i40e_status_code
5093 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5094                                  struct i40e_aqc_vsi_properties_data *info,
5095                                  uint8_t enabled_tcmap)
5096 {
5097         enum i40e_status_code ret;
5098         int i, total_tc = 0;
5099         uint16_t qpnum_per_tc, bsf, qp_idx;
5100
5101         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5102         if (ret != I40E_SUCCESS)
5103                 return ret;
5104
5105         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5106                 if (enabled_tcmap & (1 << i))
5107                         total_tc++;
5108         if (total_tc == 0)
5109                 total_tc = 1;
5110         vsi->enabled_tc = enabled_tcmap;
5111
5112         /* Number of queues per enabled TC */
5113         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5114         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5115         bsf = rte_bsf32(qpnum_per_tc);
5116
5117         /* Adjust the queue number to actual queues that can be applied */
5118         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5119                 vsi->nb_qps = qpnum_per_tc * total_tc;
5120
5121         /**
5122          * Configure TC and queue mapping parameters, for enabled TC,
5123          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5124          * default queue will serve it.
5125          */
5126         qp_idx = 0;
5127         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5128                 if (vsi->enabled_tc & (1 << i)) {
5129                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5130                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5131                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5132                         qp_idx += qpnum_per_tc;
5133                 } else
5134                         info->tc_mapping[i] = 0;
5135         }
5136
5137         /* Associate queue number with VSI */
5138         if (vsi->type == I40E_VSI_SRIOV) {
5139                 info->mapping_flags |=
5140                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5141                 for (i = 0; i < vsi->nb_qps; i++)
5142                         info->queue_mapping[i] =
5143                                 rte_cpu_to_le_16(vsi->base_queue + i);
5144         } else {
5145                 info->mapping_flags |=
5146                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5147                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5148         }
5149         info->valid_sections |=
5150                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5151
5152         return I40E_SUCCESS;
5153 }
5154
5155 static int
5156 i40e_veb_release(struct i40e_veb *veb)
5157 {
5158         struct i40e_vsi *vsi;
5159         struct i40e_hw *hw;
5160
5161         if (veb == NULL)
5162                 return -EINVAL;
5163
5164         if (!TAILQ_EMPTY(&veb->head)) {
5165                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5166                 return -EACCES;
5167         }
5168         /* associate_vsi field is NULL for floating VEB */
5169         if (veb->associate_vsi != NULL) {
5170                 vsi = veb->associate_vsi;
5171                 hw = I40E_VSI_TO_HW(vsi);
5172
5173                 vsi->uplink_seid = veb->uplink_seid;
5174                 vsi->veb = NULL;
5175         } else {
5176                 veb->associate_pf->main_vsi->floating_veb = NULL;
5177                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5178         }
5179
5180         i40e_aq_delete_element(hw, veb->seid, NULL);
5181         rte_free(veb);
5182         return I40E_SUCCESS;
5183 }
5184
5185 /* Setup a veb */
5186 static struct i40e_veb *
5187 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5188 {
5189         struct i40e_veb *veb;
5190         int ret;
5191         struct i40e_hw *hw;
5192
5193         if (pf == NULL) {
5194                 PMD_DRV_LOG(ERR,
5195                             "veb setup failed, associated PF shouldn't null");
5196                 return NULL;
5197         }
5198         hw = I40E_PF_TO_HW(pf);
5199
5200         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5201         if (!veb) {
5202                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5203                 goto fail;
5204         }
5205
5206         veb->associate_vsi = vsi;
5207         veb->associate_pf = pf;
5208         TAILQ_INIT(&veb->head);
5209         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5210
5211         /* create floating veb if vsi is NULL */
5212         if (vsi != NULL) {
5213                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5214                                       I40E_DEFAULT_TCMAP, false,
5215                                       &veb->seid, false, NULL);
5216         } else {
5217                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5218                                       true, &veb->seid, false, NULL);
5219         }
5220
5221         if (ret != I40E_SUCCESS) {
5222                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5223                             hw->aq.asq_last_status);
5224                 goto fail;
5225         }
5226         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5227
5228         /* get statistics index */
5229         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5230                                 &veb->stats_idx, NULL, NULL, NULL);
5231         if (ret != I40E_SUCCESS) {
5232                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5233                             hw->aq.asq_last_status);
5234                 goto fail;
5235         }
5236         /* Get VEB bandwidth, to be implemented */
5237         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5238         if (vsi)
5239                 vsi->uplink_seid = veb->seid;
5240
5241         return veb;
5242 fail:
5243         rte_free(veb);
5244         return NULL;
5245 }
5246
5247 int
5248 i40e_vsi_release(struct i40e_vsi *vsi)
5249 {
5250         struct i40e_pf *pf;
5251         struct i40e_hw *hw;
5252         struct i40e_vsi_list *vsi_list;
5253         void *temp;
5254         int ret;
5255         struct i40e_mac_filter *f;
5256         uint16_t user_param;
5257
5258         if (!vsi)
5259                 return I40E_SUCCESS;
5260
5261         if (!vsi->adapter)
5262                 return -EFAULT;
5263
5264         user_param = vsi->user_param;
5265
5266         pf = I40E_VSI_TO_PF(vsi);
5267         hw = I40E_VSI_TO_HW(vsi);
5268
5269         /* VSI has child to attach, release child first */
5270         if (vsi->veb) {
5271                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5272                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5273                                 return -1;
5274                 }
5275                 i40e_veb_release(vsi->veb);
5276         }
5277
5278         if (vsi->floating_veb) {
5279                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5280                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5281                                 return -1;
5282                 }
5283         }
5284
5285         /* Remove all macvlan filters of the VSI */
5286         i40e_vsi_remove_all_macvlan_filter(vsi);
5287         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5288                 rte_free(f);
5289
5290         if (vsi->type != I40E_VSI_MAIN &&
5291             ((vsi->type != I40E_VSI_SRIOV) ||
5292             !pf->floating_veb_list[user_param])) {
5293                 /* Remove vsi from parent's sibling list */
5294                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5295                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5296                         return I40E_ERR_PARAM;
5297                 }
5298                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5299                                 &vsi->sib_vsi_list, list);
5300
5301                 /* Remove all switch element of the VSI */
5302                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5303                 if (ret != I40E_SUCCESS)
5304                         PMD_DRV_LOG(ERR, "Failed to delete element");
5305         }
5306
5307         if ((vsi->type == I40E_VSI_SRIOV) &&
5308             pf->floating_veb_list[user_param]) {
5309                 /* Remove vsi from parent's sibling list */
5310                 if (vsi->parent_vsi == NULL ||
5311                     vsi->parent_vsi->floating_veb == NULL) {
5312                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5313                         return I40E_ERR_PARAM;
5314                 }
5315                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5316                              &vsi->sib_vsi_list, list);
5317
5318                 /* Remove all switch element of the VSI */
5319                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5320                 if (ret != I40E_SUCCESS)
5321                         PMD_DRV_LOG(ERR, "Failed to delete element");
5322         }
5323
5324         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5325
5326         if (vsi->type != I40E_VSI_SRIOV)
5327                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5328         rte_free(vsi);
5329
5330         return I40E_SUCCESS;
5331 }
5332
5333 static int
5334 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5335 {
5336         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5337         struct i40e_aqc_remove_macvlan_element_data def_filter;
5338         struct i40e_mac_filter_info filter;
5339         int ret;
5340
5341         if (vsi->type != I40E_VSI_MAIN)
5342                 return I40E_ERR_CONFIG;
5343         memset(&def_filter, 0, sizeof(def_filter));
5344         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5345                                         ETH_ADDR_LEN);
5346         def_filter.vlan_tag = 0;
5347         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5348                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5349         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5350         if (ret != I40E_SUCCESS) {
5351                 struct i40e_mac_filter *f;
5352                 struct rte_ether_addr *mac;
5353
5354                 PMD_DRV_LOG(DEBUG,
5355                             "Cannot remove the default macvlan filter");
5356                 /* It needs to add the permanent mac into mac list */
5357                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5358                 if (f == NULL) {
5359                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5360                         return I40E_ERR_NO_MEMORY;
5361                 }
5362                 mac = &f->mac_info.mac_addr;
5363                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5364                                 ETH_ADDR_LEN);
5365                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5366                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5367                 vsi->mac_num++;
5368
5369                 return ret;
5370         }
5371         rte_memcpy(&filter.mac_addr,
5372                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5373         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5374         return i40e_vsi_add_mac(vsi, &filter);
5375 }
5376
5377 /*
5378  * i40e_vsi_get_bw_config - Query VSI BW Information
5379  * @vsi: the VSI to be queried
5380  *
5381  * Returns 0 on success, negative value on failure
5382  */
5383 static enum i40e_status_code
5384 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5385 {
5386         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5387         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5388         struct i40e_hw *hw = &vsi->adapter->hw;
5389         i40e_status ret;
5390         int i;
5391         uint32_t bw_max;
5392
5393         memset(&bw_config, 0, sizeof(bw_config));
5394         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5395         if (ret != I40E_SUCCESS) {
5396                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5397                             hw->aq.asq_last_status);
5398                 return ret;
5399         }
5400
5401         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5402         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5403                                         &ets_sla_config, NULL);
5404         if (ret != I40E_SUCCESS) {
5405                 PMD_DRV_LOG(ERR,
5406                         "VSI failed to get TC bandwdith configuration %u",
5407                         hw->aq.asq_last_status);
5408                 return ret;
5409         }
5410
5411         /* store and print out BW info */
5412         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5413         vsi->bw_info.bw_max = bw_config.max_bw;
5414         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5415         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5416         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5417                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5418                      I40E_16_BIT_WIDTH);
5419         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5420                 vsi->bw_info.bw_ets_share_credits[i] =
5421                                 ets_sla_config.share_credits[i];
5422                 vsi->bw_info.bw_ets_credits[i] =
5423                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5424                 /* 4 bits per TC, 4th bit is reserved */
5425                 vsi->bw_info.bw_ets_max[i] =
5426                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5427                                   RTE_LEN2MASK(3, uint8_t));
5428                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5429                             vsi->bw_info.bw_ets_share_credits[i]);
5430                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5431                             vsi->bw_info.bw_ets_credits[i]);
5432                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5433                             vsi->bw_info.bw_ets_max[i]);
5434         }
5435
5436         return I40E_SUCCESS;
5437 }
5438
5439 /* i40e_enable_pf_lb
5440  * @pf: pointer to the pf structure
5441  *
5442  * allow loopback on pf
5443  */
5444 static inline void
5445 i40e_enable_pf_lb(struct i40e_pf *pf)
5446 {
5447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5448         struct i40e_vsi_context ctxt;
5449         int ret;
5450
5451         /* Use the FW API if FW >= v5.0 */
5452         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5453                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5454                 return;
5455         }
5456
5457         memset(&ctxt, 0, sizeof(ctxt));
5458         ctxt.seid = pf->main_vsi_seid;
5459         ctxt.pf_num = hw->pf_id;
5460         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5461         if (ret) {
5462                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5463                             ret, hw->aq.asq_last_status);
5464                 return;
5465         }
5466         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5467         ctxt.info.valid_sections =
5468                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5469         ctxt.info.switch_id |=
5470                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5471
5472         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5473         if (ret)
5474                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5475                             hw->aq.asq_last_status);
5476 }
5477
5478 /* Setup a VSI */
5479 struct i40e_vsi *
5480 i40e_vsi_setup(struct i40e_pf *pf,
5481                enum i40e_vsi_type type,
5482                struct i40e_vsi *uplink_vsi,
5483                uint16_t user_param)
5484 {
5485         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5486         struct i40e_vsi *vsi;
5487         struct i40e_mac_filter_info filter;
5488         int ret;
5489         struct i40e_vsi_context ctxt;
5490         struct rte_ether_addr broadcast =
5491                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5492
5493         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5494             uplink_vsi == NULL) {
5495                 PMD_DRV_LOG(ERR,
5496                         "VSI setup failed, VSI link shouldn't be NULL");
5497                 return NULL;
5498         }
5499
5500         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5501                 PMD_DRV_LOG(ERR,
5502                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5503                 return NULL;
5504         }
5505
5506         /* two situations
5507          * 1.type is not MAIN and uplink vsi is not NULL
5508          * If uplink vsi didn't setup VEB, create one first under veb field
5509          * 2.type is SRIOV and the uplink is NULL
5510          * If floating VEB is NULL, create one veb under floating veb field
5511          */
5512
5513         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5514             uplink_vsi->veb == NULL) {
5515                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5516
5517                 if (uplink_vsi->veb == NULL) {
5518                         PMD_DRV_LOG(ERR, "VEB setup failed");
5519                         return NULL;
5520                 }
5521                 /* set ALLOWLOOPBACk on pf, when veb is created */
5522                 i40e_enable_pf_lb(pf);
5523         }
5524
5525         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5526             pf->main_vsi->floating_veb == NULL) {
5527                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5528
5529                 if (pf->main_vsi->floating_veb == NULL) {
5530                         PMD_DRV_LOG(ERR, "VEB setup failed");
5531                         return NULL;
5532                 }
5533         }
5534
5535         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5536         if (!vsi) {
5537                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5538                 return NULL;
5539         }
5540         TAILQ_INIT(&vsi->mac_list);
5541         vsi->type = type;
5542         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5543         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5544         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5545         vsi->user_param = user_param;
5546         vsi->vlan_anti_spoof_on = 0;
5547         vsi->vlan_filter_on = 0;
5548         /* Allocate queues */
5549         switch (vsi->type) {
5550         case I40E_VSI_MAIN  :
5551                 vsi->nb_qps = pf->lan_nb_qps;
5552                 break;
5553         case I40E_VSI_SRIOV :
5554                 vsi->nb_qps = pf->vf_nb_qps;
5555                 break;
5556         case I40E_VSI_VMDQ2:
5557                 vsi->nb_qps = pf->vmdq_nb_qps;
5558                 break;
5559         case I40E_VSI_FDIR:
5560                 vsi->nb_qps = pf->fdir_nb_qps;
5561                 break;
5562         default:
5563                 goto fail_mem;
5564         }
5565         /*
5566          * The filter status descriptor is reported in rx queue 0,
5567          * while the tx queue for fdir filter programming has no
5568          * such constraints, can be non-zero queues.
5569          * To simplify it, choose FDIR vsi use queue 0 pair.
5570          * To make sure it will use queue 0 pair, queue allocation
5571          * need be done before this function is called
5572          */
5573         if (type != I40E_VSI_FDIR) {
5574                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5575                         if (ret < 0) {
5576                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5577                                                 vsi->seid, ret);
5578                                 goto fail_mem;
5579                         }
5580                         vsi->base_queue = ret;
5581         } else
5582                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5583
5584         /* VF has MSIX interrupt in VF range, don't allocate here */
5585         if (type == I40E_VSI_MAIN) {
5586                 if (pf->support_multi_driver) {
5587                         /* If support multi-driver, need to use INT0 instead of
5588                          * allocating from msix pool. The Msix pool is init from
5589                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5590                          * to 1 without calling i40e_res_pool_alloc.
5591                          */
5592                         vsi->msix_intr = 0;
5593                         vsi->nb_msix = 1;
5594                 } else {
5595                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5596                                                   RTE_MIN(vsi->nb_qps,
5597                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5598                         if (ret < 0) {
5599                                 PMD_DRV_LOG(ERR,
5600                                             "VSI MAIN %d get heap failed %d",
5601                                             vsi->seid, ret);
5602                                 goto fail_queue_alloc;
5603                         }
5604                         vsi->msix_intr = ret;
5605                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5606                                                RTE_MAX_RXTX_INTR_VEC_ID);
5607                 }
5608         } else if (type != I40E_VSI_SRIOV) {
5609                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5610                 if (ret < 0) {
5611                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5612                         goto fail_queue_alloc;
5613                 }
5614                 vsi->msix_intr = ret;
5615                 vsi->nb_msix = 1;
5616         } else {
5617                 vsi->msix_intr = 0;
5618                 vsi->nb_msix = 0;
5619         }
5620
5621         /* Add VSI */
5622         if (type == I40E_VSI_MAIN) {
5623                 /* For main VSI, no need to add since it's default one */
5624                 vsi->uplink_seid = pf->mac_seid;
5625                 vsi->seid = pf->main_vsi_seid;
5626                 /* Bind queues with specific MSIX interrupt */
5627                 /**
5628                  * Needs 2 interrupt at least, one for misc cause which will
5629                  * enabled from OS side, Another for queues binding the
5630                  * interrupt from device side only.
5631                  */
5632
5633                 /* Get default VSI parameters from hardware */
5634                 memset(&ctxt, 0, sizeof(ctxt));
5635                 ctxt.seid = vsi->seid;
5636                 ctxt.pf_num = hw->pf_id;
5637                 ctxt.uplink_seid = vsi->uplink_seid;
5638                 ctxt.vf_num = 0;
5639                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5640                 if (ret != I40E_SUCCESS) {
5641                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5642                         goto fail_msix_alloc;
5643                 }
5644                 rte_memcpy(&vsi->info, &ctxt.info,
5645                         sizeof(struct i40e_aqc_vsi_properties_data));
5646                 vsi->vsi_id = ctxt.vsi_number;
5647                 vsi->info.valid_sections = 0;
5648
5649                 /* Configure tc, enabled TC0 only */
5650                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5651                         I40E_SUCCESS) {
5652                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5653                         goto fail_msix_alloc;
5654                 }
5655
5656                 /* TC, queue mapping */
5657                 memset(&ctxt, 0, sizeof(ctxt));
5658                 vsi->info.valid_sections |=
5659                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5660                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5661                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5662                 rte_memcpy(&ctxt.info, &vsi->info,
5663                         sizeof(struct i40e_aqc_vsi_properties_data));
5664                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5665                                                 I40E_DEFAULT_TCMAP);
5666                 if (ret != I40E_SUCCESS) {
5667                         PMD_DRV_LOG(ERR,
5668                                 "Failed to configure TC queue mapping");
5669                         goto fail_msix_alloc;
5670                 }
5671                 ctxt.seid = vsi->seid;
5672                 ctxt.pf_num = hw->pf_id;
5673                 ctxt.uplink_seid = vsi->uplink_seid;
5674                 ctxt.vf_num = 0;
5675
5676                 /* Update VSI parameters */
5677                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5678                 if (ret != I40E_SUCCESS) {
5679                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5680                         goto fail_msix_alloc;
5681                 }
5682
5683                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5684                                                 sizeof(vsi->info.tc_mapping));
5685                 rte_memcpy(&vsi->info.queue_mapping,
5686                                 &ctxt.info.queue_mapping,
5687                         sizeof(vsi->info.queue_mapping));
5688                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5689                 vsi->info.valid_sections = 0;
5690
5691                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5692                                 ETH_ADDR_LEN);
5693
5694                 /**
5695                  * Updating default filter settings are necessary to prevent
5696                  * reception of tagged packets.
5697                  * Some old firmware configurations load a default macvlan
5698                  * filter which accepts both tagged and untagged packets.
5699                  * The updating is to use a normal filter instead if needed.
5700                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5701                  * The firmware with correct configurations load the default
5702                  * macvlan filter which is expected and cannot be removed.
5703                  */
5704                 i40e_update_default_filter_setting(vsi);
5705                 i40e_config_qinq(hw, vsi);
5706         } else if (type == I40E_VSI_SRIOV) {
5707                 memset(&ctxt, 0, sizeof(ctxt));
5708                 /**
5709                  * For other VSI, the uplink_seid equals to uplink VSI's
5710                  * uplink_seid since they share same VEB
5711                  */
5712                 if (uplink_vsi == NULL)
5713                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5714                 else
5715                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5716                 ctxt.pf_num = hw->pf_id;
5717                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5718                 ctxt.uplink_seid = vsi->uplink_seid;
5719                 ctxt.connection_type = 0x1;
5720                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5721
5722                 /* Use the VEB configuration if FW >= v5.0 */
5723                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5724                         /* Configure switch ID */
5725                         ctxt.info.valid_sections |=
5726                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5727                         ctxt.info.switch_id =
5728                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5729                 }
5730
5731                 /* Configure port/vlan */
5732                 ctxt.info.valid_sections |=
5733                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5734                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5735                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5736                                                 hw->func_caps.enabled_tcmap);
5737                 if (ret != I40E_SUCCESS) {
5738                         PMD_DRV_LOG(ERR,
5739                                 "Failed to configure TC queue mapping");
5740                         goto fail_msix_alloc;
5741                 }
5742
5743                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5744                 ctxt.info.valid_sections |=
5745                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5746                 /**
5747                  * Since VSI is not created yet, only configure parameter,
5748                  * will add vsi below.
5749                  */
5750
5751                 i40e_config_qinq(hw, vsi);
5752         } else if (type == I40E_VSI_VMDQ2) {
5753                 memset(&ctxt, 0, sizeof(ctxt));
5754                 /*
5755                  * For other VSI, the uplink_seid equals to uplink VSI's
5756                  * uplink_seid since they share same VEB
5757                  */
5758                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5759                 ctxt.pf_num = hw->pf_id;
5760                 ctxt.vf_num = 0;
5761                 ctxt.uplink_seid = vsi->uplink_seid;
5762                 ctxt.connection_type = 0x1;
5763                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5764
5765                 ctxt.info.valid_sections |=
5766                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5767                 /* user_param carries flag to enable loop back */
5768                 if (user_param) {
5769                         ctxt.info.switch_id =
5770                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5771                         ctxt.info.switch_id |=
5772                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5773                 }
5774
5775                 /* Configure port/vlan */
5776                 ctxt.info.valid_sections |=
5777                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5778                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5779                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5780                                                 I40E_DEFAULT_TCMAP);
5781                 if (ret != I40E_SUCCESS) {
5782                         PMD_DRV_LOG(ERR,
5783                                 "Failed to configure TC queue mapping");
5784                         goto fail_msix_alloc;
5785                 }
5786                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5787                 ctxt.info.valid_sections |=
5788                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5789         } else if (type == I40E_VSI_FDIR) {
5790                 memset(&ctxt, 0, sizeof(ctxt));
5791                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5792                 ctxt.pf_num = hw->pf_id;
5793                 ctxt.vf_num = 0;
5794                 ctxt.uplink_seid = vsi->uplink_seid;
5795                 ctxt.connection_type = 0x1;     /* regular data port */
5796                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5797                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5798                                                 I40E_DEFAULT_TCMAP);
5799                 if (ret != I40E_SUCCESS) {
5800                         PMD_DRV_LOG(ERR,
5801                                 "Failed to configure TC queue mapping.");
5802                         goto fail_msix_alloc;
5803                 }
5804                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5805                 ctxt.info.valid_sections |=
5806                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5807         } else {
5808                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5809                 goto fail_msix_alloc;
5810         }
5811
5812         if (vsi->type != I40E_VSI_MAIN) {
5813                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5814                 if (ret != I40E_SUCCESS) {
5815                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5816                                     hw->aq.asq_last_status);
5817                         goto fail_msix_alloc;
5818                 }
5819                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5820                 vsi->info.valid_sections = 0;
5821                 vsi->seid = ctxt.seid;
5822                 vsi->vsi_id = ctxt.vsi_number;
5823                 vsi->sib_vsi_list.vsi = vsi;
5824                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5825                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5826                                           &vsi->sib_vsi_list, list);
5827                 } else {
5828                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5829                                           &vsi->sib_vsi_list, list);
5830                 }
5831         }
5832
5833         /* MAC/VLAN configuration */
5834         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5835         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5836
5837         ret = i40e_vsi_add_mac(vsi, &filter);
5838         if (ret != I40E_SUCCESS) {
5839                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5840                 goto fail_msix_alloc;
5841         }
5842
5843         /* Get VSI BW information */
5844         i40e_vsi_get_bw_config(vsi);
5845         return vsi;
5846 fail_msix_alloc:
5847         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5848 fail_queue_alloc:
5849         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5850 fail_mem:
5851         rte_free(vsi);
5852         return NULL;
5853 }
5854
5855 /* Configure vlan filter on or off */
5856 int
5857 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5858 {
5859         int i, num;
5860         struct i40e_mac_filter *f;
5861         void *temp;
5862         struct i40e_mac_filter_info *mac_filter;
5863         enum rte_mac_filter_type desired_filter;
5864         int ret = I40E_SUCCESS;
5865
5866         if (on) {
5867                 /* Filter to match MAC and VLAN */
5868                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5869         } else {
5870                 /* Filter to match only MAC */
5871                 desired_filter = RTE_MAC_PERFECT_MATCH;
5872         }
5873
5874         num = vsi->mac_num;
5875
5876         mac_filter = rte_zmalloc("mac_filter_info_data",
5877                                  num * sizeof(*mac_filter), 0);
5878         if (mac_filter == NULL) {
5879                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5880                 return I40E_ERR_NO_MEMORY;
5881         }
5882
5883         i = 0;
5884
5885         /* Remove all existing mac */
5886         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5887                 mac_filter[i] = f->mac_info;
5888                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5889                 if (ret) {
5890                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5891                                     on ? "enable" : "disable");
5892                         goto DONE;
5893                 }
5894                 i++;
5895         }
5896
5897         /* Override with new filter */
5898         for (i = 0; i < num; i++) {
5899                 mac_filter[i].filter_type = desired_filter;
5900                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5901                 if (ret) {
5902                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5903                                     on ? "enable" : "disable");
5904                         goto DONE;
5905                 }
5906         }
5907
5908 DONE:
5909         rte_free(mac_filter);
5910         return ret;
5911 }
5912
5913 /* Configure vlan stripping on or off */
5914 int
5915 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5916 {
5917         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5918         struct i40e_vsi_context ctxt;
5919         uint8_t vlan_flags;
5920         int ret = I40E_SUCCESS;
5921
5922         /* Check if it has been already on or off */
5923         if (vsi->info.valid_sections &
5924                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5925                 if (on) {
5926                         if ((vsi->info.port_vlan_flags &
5927                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5928                                 return 0; /* already on */
5929                 } else {
5930                         if ((vsi->info.port_vlan_flags &
5931                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5932                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5933                                 return 0; /* already off */
5934                 }
5935         }
5936
5937         if (on)
5938                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5939         else
5940                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5941         vsi->info.valid_sections =
5942                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5943         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5944         vsi->info.port_vlan_flags |= vlan_flags;
5945         ctxt.seid = vsi->seid;
5946         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5947         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5948         if (ret)
5949                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5950                             on ? "enable" : "disable");
5951
5952         return ret;
5953 }
5954
5955 static int
5956 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5957 {
5958         struct rte_eth_dev_data *data = dev->data;
5959         int ret;
5960         int mask = 0;
5961
5962         /* Apply vlan offload setting */
5963         mask = ETH_VLAN_STRIP_MASK |
5964                ETH_VLAN_FILTER_MASK |
5965                ETH_VLAN_EXTEND_MASK;
5966         ret = i40e_vlan_offload_set(dev, mask);
5967         if (ret) {
5968                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5969                 return ret;
5970         }
5971
5972         /* Apply pvid setting */
5973         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5974                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5975         if (ret)
5976                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5977
5978         return ret;
5979 }
5980
5981 static int
5982 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5983 {
5984         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5985
5986         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5987 }
5988
5989 static int
5990 i40e_update_flow_control(struct i40e_hw *hw)
5991 {
5992 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5993         struct i40e_link_status link_status;
5994         uint32_t rxfc = 0, txfc = 0, reg;
5995         uint8_t an_info;
5996         int ret;
5997
5998         memset(&link_status, 0, sizeof(link_status));
5999         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6000         if (ret != I40E_SUCCESS) {
6001                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6002                 goto write_reg; /* Disable flow control */
6003         }
6004
6005         an_info = hw->phy.link_info.an_info;
6006         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6007                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6008                 ret = I40E_ERR_NOT_READY;
6009                 goto write_reg; /* Disable flow control */
6010         }
6011         /**
6012          * If link auto negotiation is enabled, flow control needs to
6013          * be configured according to it
6014          */
6015         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6016         case I40E_LINK_PAUSE_RXTX:
6017                 rxfc = 1;
6018                 txfc = 1;
6019                 hw->fc.current_mode = I40E_FC_FULL;
6020                 break;
6021         case I40E_AQ_LINK_PAUSE_RX:
6022                 rxfc = 1;
6023                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6024                 break;
6025         case I40E_AQ_LINK_PAUSE_TX:
6026                 txfc = 1;
6027                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6028                 break;
6029         default:
6030                 hw->fc.current_mode = I40E_FC_NONE;
6031                 break;
6032         }
6033
6034 write_reg:
6035         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6036                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6037         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6038         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6039         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6040         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6041
6042         return ret;
6043 }
6044
6045 /* PF setup */
6046 static int
6047 i40e_pf_setup(struct i40e_pf *pf)
6048 {
6049         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6050         struct i40e_filter_control_settings settings;
6051         struct i40e_vsi *vsi;
6052         int ret;
6053
6054         /* Clear all stats counters */
6055         pf->offset_loaded = FALSE;
6056         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6057         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6058         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6059         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6060
6061         ret = i40e_pf_get_switch_config(pf);
6062         if (ret != I40E_SUCCESS) {
6063                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6064                 return ret;
6065         }
6066
6067         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6068         if (ret)
6069                 PMD_INIT_LOG(WARNING,
6070                         "failed to allocate switch domain for device %d", ret);
6071
6072         if (pf->flags & I40E_FLAG_FDIR) {
6073                 /* make queue allocated first, let FDIR use queue pair 0*/
6074                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6075                 if (ret != I40E_FDIR_QUEUE_ID) {
6076                         PMD_DRV_LOG(ERR,
6077                                 "queue allocation fails for FDIR: ret =%d",
6078                                 ret);
6079                         pf->flags &= ~I40E_FLAG_FDIR;
6080                 }
6081         }
6082         /*  main VSI setup */
6083         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6084         if (!vsi) {
6085                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6086                 return I40E_ERR_NOT_READY;
6087         }
6088         pf->main_vsi = vsi;
6089
6090         /* Configure filter control */
6091         memset(&settings, 0, sizeof(settings));
6092         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6093                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6094         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6095                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6096         else {
6097                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6098                         hw->func_caps.rss_table_size);
6099                 return I40E_ERR_PARAM;
6100         }
6101         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6102                 hw->func_caps.rss_table_size);
6103         pf->hash_lut_size = hw->func_caps.rss_table_size;
6104
6105         /* Enable ethtype and macvlan filters */
6106         settings.enable_ethtype = TRUE;
6107         settings.enable_macvlan = TRUE;
6108         ret = i40e_set_filter_control(hw, &settings);
6109         if (ret)
6110                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6111                                                                 ret);
6112
6113         /* Update flow control according to the auto negotiation */
6114         i40e_update_flow_control(hw);
6115
6116         return I40E_SUCCESS;
6117 }
6118
6119 int
6120 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6121 {
6122         uint32_t reg;
6123         uint16_t j;
6124
6125         /**
6126          * Set or clear TX Queue Disable flags,
6127          * which is required by hardware.
6128          */
6129         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6130         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6131
6132         /* Wait until the request is finished */
6133         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6134                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6135                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6136                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6137                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6138                                                         & 0x1))) {
6139                         break;
6140                 }
6141         }
6142         if (on) {
6143                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6144                         return I40E_SUCCESS; /* already on, skip next steps */
6145
6146                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6147                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6148         } else {
6149                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6150                         return I40E_SUCCESS; /* already off, skip next steps */
6151                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6152         }
6153         /* Write the register */
6154         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6155         /* Check the result */
6156         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6157                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6158                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6159                 if (on) {
6160                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6161                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6162                                 break;
6163                 } else {
6164                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6165                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6166                                 break;
6167                 }
6168         }
6169         /* Check if it is timeout */
6170         if (j >= I40E_CHK_Q_ENA_COUNT) {
6171                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6172                             (on ? "enable" : "disable"), q_idx);
6173                 return I40E_ERR_TIMEOUT;
6174         }
6175
6176         return I40E_SUCCESS;
6177 }
6178
6179 /* Swith on or off the tx queues */
6180 static int
6181 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6182 {
6183         struct rte_eth_dev_data *dev_data = pf->dev_data;
6184         struct i40e_tx_queue *txq;
6185         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6186         uint16_t i;
6187         int ret;
6188
6189         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6190                 txq = dev_data->tx_queues[i];
6191                 /* Don't operate the queue if not configured or
6192                  * if starting only per queue */
6193                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6194                         continue;
6195                 if (on)
6196                         ret = i40e_dev_tx_queue_start(dev, i);
6197                 else
6198                         ret = i40e_dev_tx_queue_stop(dev, i);
6199                 if ( ret != I40E_SUCCESS)
6200                         return ret;
6201         }
6202
6203         return I40E_SUCCESS;
6204 }
6205
6206 int
6207 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6208 {
6209         uint32_t reg;
6210         uint16_t j;
6211
6212         /* Wait until the request is finished */
6213         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6214                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6215                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6216                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6217                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6218                         break;
6219         }
6220
6221         if (on) {
6222                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6223                         return I40E_SUCCESS; /* Already on, skip next steps */
6224                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6225         } else {
6226                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6227                         return I40E_SUCCESS; /* Already off, skip next steps */
6228                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6229         }
6230
6231         /* Write the register */
6232         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6233         /* Check the result */
6234         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6235                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6236                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6237                 if (on) {
6238                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6239                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6240                                 break;
6241                 } else {
6242                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6243                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6244                                 break;
6245                 }
6246         }
6247
6248         /* Check if it is timeout */
6249         if (j >= I40E_CHK_Q_ENA_COUNT) {
6250                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6251                             (on ? "enable" : "disable"), q_idx);
6252                 return I40E_ERR_TIMEOUT;
6253         }
6254
6255         return I40E_SUCCESS;
6256 }
6257 /* Switch on or off the rx queues */
6258 static int
6259 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6260 {
6261         struct rte_eth_dev_data *dev_data = pf->dev_data;
6262         struct i40e_rx_queue *rxq;
6263         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6264         uint16_t i;
6265         int ret;
6266
6267         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6268                 rxq = dev_data->rx_queues[i];
6269                 /* Don't operate the queue if not configured or
6270                  * if starting only per queue */
6271                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6272                         continue;
6273                 if (on)
6274                         ret = i40e_dev_rx_queue_start(dev, i);
6275                 else
6276                         ret = i40e_dev_rx_queue_stop(dev, i);
6277                 if (ret != I40E_SUCCESS)
6278                         return ret;
6279         }
6280
6281         return I40E_SUCCESS;
6282 }
6283
6284 /* Switch on or off all the rx/tx queues */
6285 int
6286 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6287 {
6288         int ret;
6289
6290         if (on) {
6291                 /* enable rx queues before enabling tx queues */
6292                 ret = i40e_dev_switch_rx_queues(pf, on);
6293                 if (ret) {
6294                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6295                         return ret;
6296                 }
6297                 ret = i40e_dev_switch_tx_queues(pf, on);
6298         } else {
6299                 /* Stop tx queues before stopping rx queues */
6300                 ret = i40e_dev_switch_tx_queues(pf, on);
6301                 if (ret) {
6302                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6303                         return ret;
6304                 }
6305                 ret = i40e_dev_switch_rx_queues(pf, on);
6306         }
6307
6308         return ret;
6309 }
6310
6311 /* Initialize VSI for TX */
6312 static int
6313 i40e_dev_tx_init(struct i40e_pf *pf)
6314 {
6315         struct rte_eth_dev_data *data = pf->dev_data;
6316         uint16_t i;
6317         uint32_t ret = I40E_SUCCESS;
6318         struct i40e_tx_queue *txq;
6319
6320         for (i = 0; i < data->nb_tx_queues; i++) {
6321                 txq = data->tx_queues[i];
6322                 if (!txq || !txq->q_set)
6323                         continue;
6324                 ret = i40e_tx_queue_init(txq);
6325                 if (ret != I40E_SUCCESS)
6326                         break;
6327         }
6328         if (ret == I40E_SUCCESS)
6329                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6330                                      ->eth_dev);
6331
6332         return ret;
6333 }
6334
6335 /* Initialize VSI for RX */
6336 static int
6337 i40e_dev_rx_init(struct i40e_pf *pf)
6338 {
6339         struct rte_eth_dev_data *data = pf->dev_data;
6340         int ret = I40E_SUCCESS;
6341         uint16_t i;
6342         struct i40e_rx_queue *rxq;
6343
6344         i40e_pf_config_mq_rx(pf);
6345         for (i = 0; i < data->nb_rx_queues; i++) {
6346                 rxq = data->rx_queues[i];
6347                 if (!rxq || !rxq->q_set)
6348                         continue;
6349
6350                 ret = i40e_rx_queue_init(rxq);
6351                 if (ret != I40E_SUCCESS) {
6352                         PMD_DRV_LOG(ERR,
6353                                 "Failed to do RX queue initialization");
6354                         break;
6355                 }
6356         }
6357         if (ret == I40E_SUCCESS)
6358                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6359                                      ->eth_dev);
6360
6361         return ret;
6362 }
6363
6364 static int
6365 i40e_dev_rxtx_init(struct i40e_pf *pf)
6366 {
6367         int err;
6368
6369         err = i40e_dev_tx_init(pf);
6370         if (err) {
6371                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6372                 return err;
6373         }
6374         err = i40e_dev_rx_init(pf);
6375         if (err) {
6376                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6377                 return err;
6378         }
6379
6380         return err;
6381 }
6382
6383 static int
6384 i40e_vmdq_setup(struct rte_eth_dev *dev)
6385 {
6386         struct rte_eth_conf *conf = &dev->data->dev_conf;
6387         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6388         int i, err, conf_vsis, j, loop;
6389         struct i40e_vsi *vsi;
6390         struct i40e_vmdq_info *vmdq_info;
6391         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6392         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6393
6394         /*
6395          * Disable interrupt to avoid message from VF. Furthermore, it will
6396          * avoid race condition in VSI creation/destroy.
6397          */
6398         i40e_pf_disable_irq0(hw);
6399
6400         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6401                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6402                 return -ENOTSUP;
6403         }
6404
6405         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6406         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6407                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6408                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6409                         pf->max_nb_vmdq_vsi);
6410                 return -ENOTSUP;
6411         }
6412
6413         if (pf->vmdq != NULL) {
6414                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6415                 return 0;
6416         }
6417
6418         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6419                                 sizeof(*vmdq_info) * conf_vsis, 0);
6420
6421         if (pf->vmdq == NULL) {
6422                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6423                 return -ENOMEM;
6424         }
6425
6426         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6427
6428         /* Create VMDQ VSI */
6429         for (i = 0; i < conf_vsis; i++) {
6430                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6431                                 vmdq_conf->enable_loop_back);
6432                 if (vsi == NULL) {
6433                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6434                         err = -1;
6435                         goto err_vsi_setup;
6436                 }
6437                 vmdq_info = &pf->vmdq[i];
6438                 vmdq_info->pf = pf;
6439                 vmdq_info->vsi = vsi;
6440         }
6441         pf->nb_cfg_vmdq_vsi = conf_vsis;
6442
6443         /* Configure Vlan */
6444         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6445         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6446                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6447                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6448                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6449                                         vmdq_conf->pool_map[i].vlan_id, j);
6450
6451                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6452                                                 vmdq_conf->pool_map[i].vlan_id);
6453                                 if (err) {
6454                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6455                                         err = -1;
6456                                         goto err_vsi_setup;
6457                                 }
6458                         }
6459                 }
6460         }
6461
6462         i40e_pf_enable_irq0(hw);
6463
6464         return 0;
6465
6466 err_vsi_setup:
6467         for (i = 0; i < conf_vsis; i++)
6468                 if (pf->vmdq[i].vsi == NULL)
6469                         break;
6470                 else
6471                         i40e_vsi_release(pf->vmdq[i].vsi);
6472
6473         rte_free(pf->vmdq);
6474         pf->vmdq = NULL;
6475         i40e_pf_enable_irq0(hw);
6476         return err;
6477 }
6478
6479 static void
6480 i40e_stat_update_32(struct i40e_hw *hw,
6481                    uint32_t reg,
6482                    bool offset_loaded,
6483                    uint64_t *offset,
6484                    uint64_t *stat)
6485 {
6486         uint64_t new_data;
6487
6488         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6489         if (!offset_loaded)
6490                 *offset = new_data;
6491
6492         if (new_data >= *offset)
6493                 *stat = (uint64_t)(new_data - *offset);
6494         else
6495                 *stat = (uint64_t)((new_data +
6496                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6497 }
6498
6499 static void
6500 i40e_stat_update_48(struct i40e_hw *hw,
6501                    uint32_t hireg,
6502                    uint32_t loreg,
6503                    bool offset_loaded,
6504                    uint64_t *offset,
6505                    uint64_t *stat)
6506 {
6507         uint64_t new_data;
6508
6509         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6510         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6511                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6512
6513         if (!offset_loaded)
6514                 *offset = new_data;
6515
6516         if (new_data >= *offset)
6517                 *stat = new_data - *offset;
6518         else
6519                 *stat = (uint64_t)((new_data +
6520                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6521
6522         *stat &= I40E_48_BIT_MASK;
6523 }
6524
6525 /* Disable IRQ0 */
6526 void
6527 i40e_pf_disable_irq0(struct i40e_hw *hw)
6528 {
6529         /* Disable all interrupt types */
6530         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6531                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6532         I40E_WRITE_FLUSH(hw);
6533 }
6534
6535 /* Enable IRQ0 */
6536 void
6537 i40e_pf_enable_irq0(struct i40e_hw *hw)
6538 {
6539         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6540                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6541                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6542                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6543         I40E_WRITE_FLUSH(hw);
6544 }
6545
6546 static void
6547 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6548 {
6549         /* read pending request and disable first */
6550         i40e_pf_disable_irq0(hw);
6551         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6552         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6553                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6554
6555         if (no_queue)
6556                 /* Link no queues with irq0 */
6557                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6558                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6559 }
6560
6561 static void
6562 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6563 {
6564         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6566         int i;
6567         uint16_t abs_vf_id;
6568         uint32_t index, offset, val;
6569
6570         if (!pf->vfs)
6571                 return;
6572         /**
6573          * Try to find which VF trigger a reset, use absolute VF id to access
6574          * since the reg is global register.
6575          */
6576         for (i = 0; i < pf->vf_num; i++) {
6577                 abs_vf_id = hw->func_caps.vf_base_id + i;
6578                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6579                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6580                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6581                 /* VFR event occurred */
6582                 if (val & (0x1 << offset)) {
6583                         int ret;
6584
6585                         /* Clear the event first */
6586                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6587                                                         (0x1 << offset));
6588                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6589                         /**
6590                          * Only notify a VF reset event occurred,
6591                          * don't trigger another SW reset
6592                          */
6593                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6594                         if (ret != I40E_SUCCESS)
6595                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6596                 }
6597         }
6598 }
6599
6600 static void
6601 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6602 {
6603         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6604         int i;
6605
6606         for (i = 0; i < pf->vf_num; i++)
6607                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6608 }
6609
6610 static void
6611 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6612 {
6613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6614         struct i40e_arq_event_info info;
6615         uint16_t pending, opcode;
6616         int ret;
6617
6618         info.buf_len = I40E_AQ_BUF_SZ;
6619         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6620         if (!info.msg_buf) {
6621                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6622                 return;
6623         }
6624
6625         pending = 1;
6626         while (pending) {
6627                 ret = i40e_clean_arq_element(hw, &info, &pending);
6628
6629                 if (ret != I40E_SUCCESS) {
6630                         PMD_DRV_LOG(INFO,
6631                                 "Failed to read msg from AdminQ, aq_err: %u",
6632                                 hw->aq.asq_last_status);
6633                         break;
6634                 }
6635                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6636
6637                 switch (opcode) {
6638                 case i40e_aqc_opc_send_msg_to_pf:
6639                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6640                         i40e_pf_host_handle_vf_msg(dev,
6641                                         rte_le_to_cpu_16(info.desc.retval),
6642                                         rte_le_to_cpu_32(info.desc.cookie_high),
6643                                         rte_le_to_cpu_32(info.desc.cookie_low),
6644                                         info.msg_buf,
6645                                         info.msg_len);
6646                         break;
6647                 case i40e_aqc_opc_get_link_status:
6648                         ret = i40e_dev_link_update(dev, 0);
6649                         if (!ret)
6650                                 _rte_eth_dev_callback_process(dev,
6651                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6652                         break;
6653                 default:
6654                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6655                                     opcode);
6656                         break;
6657                 }
6658         }
6659         rte_free(info.msg_buf);
6660 }
6661
6662 /**
6663  * Interrupt handler triggered by NIC  for handling
6664  * specific interrupt.
6665  *
6666  * @param handle
6667  *  Pointer to interrupt handle.
6668  * @param param
6669  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6670  *
6671  * @return
6672  *  void
6673  */
6674 static void
6675 i40e_dev_interrupt_handler(void *param)
6676 {
6677         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6679         uint32_t icr0;
6680
6681         /* Disable interrupt */
6682         i40e_pf_disable_irq0(hw);
6683
6684         /* read out interrupt causes */
6685         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6686
6687         /* No interrupt event indicated */
6688         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6689                 PMD_DRV_LOG(INFO, "No interrupt event");
6690                 goto done;
6691         }
6692         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6693                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6694         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6695                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6696         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6697                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6698         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6699                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6700         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6701                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6702         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6703                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6704         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6705                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6706
6707         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6708                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6709                 i40e_dev_handle_vfr_event(dev);
6710         }
6711         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6712                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6713                 i40e_dev_handle_aq_msg(dev);
6714         }
6715
6716 done:
6717         /* Enable interrupt */
6718         i40e_pf_enable_irq0(hw);
6719 }
6720
6721 static void
6722 i40e_dev_alarm_handler(void *param)
6723 {
6724         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726         uint32_t icr0;
6727
6728         /* Disable interrupt */
6729         i40e_pf_disable_irq0(hw);
6730
6731         /* read out interrupt causes */
6732         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6733
6734         /* No interrupt event indicated */
6735         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6736                 goto done;
6737         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6738                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6739         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6740                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6741         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6742                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6743         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6744                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6745         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6746                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6747         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6748                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6749         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6750                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6751
6752         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6753                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6754                 i40e_dev_handle_vfr_event(dev);
6755         }
6756         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6757                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6758                 i40e_dev_handle_aq_msg(dev);
6759         }
6760
6761 done:
6762         /* Enable interrupt */
6763         i40e_pf_enable_irq0(hw);
6764         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6765                           i40e_dev_alarm_handler, dev);
6766 }
6767
6768 int
6769 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6770                          struct i40e_macvlan_filter *filter,
6771                          int total)
6772 {
6773         int ele_num, ele_buff_size;
6774         int num, actual_num, i;
6775         uint16_t flags;
6776         int ret = I40E_SUCCESS;
6777         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6778         struct i40e_aqc_add_macvlan_element_data *req_list;
6779
6780         if (filter == NULL  || total == 0)
6781                 return I40E_ERR_PARAM;
6782         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6783         ele_buff_size = hw->aq.asq_buf_size;
6784
6785         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6786         if (req_list == NULL) {
6787                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6788                 return I40E_ERR_NO_MEMORY;
6789         }
6790
6791         num = 0;
6792         do {
6793                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6794                 memset(req_list, 0, ele_buff_size);
6795
6796                 for (i = 0; i < actual_num; i++) {
6797                         rte_memcpy(req_list[i].mac_addr,
6798                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6799                         req_list[i].vlan_tag =
6800                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6801
6802                         switch (filter[num + i].filter_type) {
6803                         case RTE_MAC_PERFECT_MATCH:
6804                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6805                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6806                                 break;
6807                         case RTE_MACVLAN_PERFECT_MATCH:
6808                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6809                                 break;
6810                         case RTE_MAC_HASH_MATCH:
6811                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6812                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6813                                 break;
6814                         case RTE_MACVLAN_HASH_MATCH:
6815                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6816                                 break;
6817                         default:
6818                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6819                                 ret = I40E_ERR_PARAM;
6820                                 goto DONE;
6821                         }
6822
6823                         req_list[i].queue_number = 0;
6824
6825                         req_list[i].flags = rte_cpu_to_le_16(flags);
6826                 }
6827
6828                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6829                                                 actual_num, NULL);
6830                 if (ret != I40E_SUCCESS) {
6831                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6832                         goto DONE;
6833                 }
6834                 num += actual_num;
6835         } while (num < total);
6836
6837 DONE:
6838         rte_free(req_list);
6839         return ret;
6840 }
6841
6842 int
6843 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6844                             struct i40e_macvlan_filter *filter,
6845                             int total)
6846 {
6847         int ele_num, ele_buff_size;
6848         int num, actual_num, i;
6849         uint16_t flags;
6850         int ret = I40E_SUCCESS;
6851         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6852         struct i40e_aqc_remove_macvlan_element_data *req_list;
6853
6854         if (filter == NULL  || total == 0)
6855                 return I40E_ERR_PARAM;
6856
6857         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6858         ele_buff_size = hw->aq.asq_buf_size;
6859
6860         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6861         if (req_list == NULL) {
6862                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6863                 return I40E_ERR_NO_MEMORY;
6864         }
6865
6866         num = 0;
6867         do {
6868                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6869                 memset(req_list, 0, ele_buff_size);
6870
6871                 for (i = 0; i < actual_num; i++) {
6872                         rte_memcpy(req_list[i].mac_addr,
6873                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6874                         req_list[i].vlan_tag =
6875                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6876
6877                         switch (filter[num + i].filter_type) {
6878                         case RTE_MAC_PERFECT_MATCH:
6879                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6880                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6881                                 break;
6882                         case RTE_MACVLAN_PERFECT_MATCH:
6883                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6884                                 break;
6885                         case RTE_MAC_HASH_MATCH:
6886                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6887                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6888                                 break;
6889                         case RTE_MACVLAN_HASH_MATCH:
6890                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6891                                 break;
6892                         default:
6893                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6894                                 ret = I40E_ERR_PARAM;
6895                                 goto DONE;
6896                         }
6897                         req_list[i].flags = rte_cpu_to_le_16(flags);
6898                 }
6899
6900                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6901                                                 actual_num, NULL);
6902                 if (ret != I40E_SUCCESS) {
6903                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6904                         goto DONE;
6905                 }
6906                 num += actual_num;
6907         } while (num < total);
6908
6909 DONE:
6910         rte_free(req_list);
6911         return ret;
6912 }
6913
6914 /* Find out specific MAC filter */
6915 static struct i40e_mac_filter *
6916 i40e_find_mac_filter(struct i40e_vsi *vsi,
6917                          struct rte_ether_addr *macaddr)
6918 {
6919         struct i40e_mac_filter *f;
6920
6921         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6922                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6923                         return f;
6924         }
6925
6926         return NULL;
6927 }
6928
6929 static bool
6930 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6931                          uint16_t vlan_id)
6932 {
6933         uint32_t vid_idx, vid_bit;
6934
6935         if (vlan_id > ETH_VLAN_ID_MAX)
6936                 return 0;
6937
6938         vid_idx = I40E_VFTA_IDX(vlan_id);
6939         vid_bit = I40E_VFTA_BIT(vlan_id);
6940
6941         if (vsi->vfta[vid_idx] & vid_bit)
6942                 return 1;
6943         else
6944                 return 0;
6945 }
6946
6947 static void
6948 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6949                        uint16_t vlan_id, bool on)
6950 {
6951         uint32_t vid_idx, vid_bit;
6952
6953         vid_idx = I40E_VFTA_IDX(vlan_id);
6954         vid_bit = I40E_VFTA_BIT(vlan_id);
6955
6956         if (on)
6957                 vsi->vfta[vid_idx] |= vid_bit;
6958         else
6959                 vsi->vfta[vid_idx] &= ~vid_bit;
6960 }
6961
6962 void
6963 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6964                      uint16_t vlan_id, bool on)
6965 {
6966         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6967         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6968         int ret;
6969
6970         if (vlan_id > ETH_VLAN_ID_MAX)
6971                 return;
6972
6973         i40e_store_vlan_filter(vsi, vlan_id, on);
6974
6975         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6976                 return;
6977
6978         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6979
6980         if (on) {
6981                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6982                                        &vlan_data, 1, NULL);
6983                 if (ret != I40E_SUCCESS)
6984                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6985         } else {
6986                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6987                                           &vlan_data, 1, NULL);
6988                 if (ret != I40E_SUCCESS)
6989                         PMD_DRV_LOG(ERR,
6990                                     "Failed to remove vlan filter");
6991         }
6992 }
6993
6994 /**
6995  * Find all vlan options for specific mac addr,
6996  * return with actual vlan found.
6997  */
6998 int
6999 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7000                            struct i40e_macvlan_filter *mv_f,
7001                            int num, struct rte_ether_addr *addr)
7002 {
7003         int i;
7004         uint32_t j, k;
7005
7006         /**
7007          * Not to use i40e_find_vlan_filter to decrease the loop time,
7008          * although the code looks complex.
7009           */
7010         if (num < vsi->vlan_num)
7011                 return I40E_ERR_PARAM;
7012
7013         i = 0;
7014         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7015                 if (vsi->vfta[j]) {
7016                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7017                                 if (vsi->vfta[j] & (1 << k)) {
7018                                         if (i > num - 1) {
7019                                                 PMD_DRV_LOG(ERR,
7020                                                         "vlan number doesn't match");
7021                                                 return I40E_ERR_PARAM;
7022                                         }
7023                                         rte_memcpy(&mv_f[i].macaddr,
7024                                                         addr, ETH_ADDR_LEN);
7025                                         mv_f[i].vlan_id =
7026                                                 j * I40E_UINT32_BIT_SIZE + k;
7027                                         i++;
7028                                 }
7029                         }
7030                 }
7031         }
7032         return I40E_SUCCESS;
7033 }
7034
7035 static inline int
7036 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7037                            struct i40e_macvlan_filter *mv_f,
7038                            int num,
7039                            uint16_t vlan)
7040 {
7041         int i = 0;
7042         struct i40e_mac_filter *f;
7043
7044         if (num < vsi->mac_num)
7045                 return I40E_ERR_PARAM;
7046
7047         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7048                 if (i > num - 1) {
7049                         PMD_DRV_LOG(ERR, "buffer number not match");
7050                         return I40E_ERR_PARAM;
7051                 }
7052                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7053                                 ETH_ADDR_LEN);
7054                 mv_f[i].vlan_id = vlan;
7055                 mv_f[i].filter_type = f->mac_info.filter_type;
7056                 i++;
7057         }
7058
7059         return I40E_SUCCESS;
7060 }
7061
7062 static int
7063 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7064 {
7065         int i, j, num;
7066         struct i40e_mac_filter *f;
7067         struct i40e_macvlan_filter *mv_f;
7068         int ret = I40E_SUCCESS;
7069
7070         if (vsi == NULL || vsi->mac_num == 0)
7071                 return I40E_ERR_PARAM;
7072
7073         /* Case that no vlan is set */
7074         if (vsi->vlan_num == 0)
7075                 num = vsi->mac_num;
7076         else
7077                 num = vsi->mac_num * vsi->vlan_num;
7078
7079         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7080         if (mv_f == NULL) {
7081                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7082                 return I40E_ERR_NO_MEMORY;
7083         }
7084
7085         i = 0;
7086         if (vsi->vlan_num == 0) {
7087                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7088                         rte_memcpy(&mv_f[i].macaddr,
7089                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7090                         mv_f[i].filter_type = f->mac_info.filter_type;
7091                         mv_f[i].vlan_id = 0;
7092                         i++;
7093                 }
7094         } else {
7095                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7096                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7097                                         vsi->vlan_num, &f->mac_info.mac_addr);
7098                         if (ret != I40E_SUCCESS)
7099                                 goto DONE;
7100                         for (j = i; j < i + vsi->vlan_num; j++)
7101                                 mv_f[j].filter_type = f->mac_info.filter_type;
7102                         i += vsi->vlan_num;
7103                 }
7104         }
7105
7106         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7107 DONE:
7108         rte_free(mv_f);
7109
7110         return ret;
7111 }
7112
7113 int
7114 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7115 {
7116         struct i40e_macvlan_filter *mv_f;
7117         int mac_num;
7118         int ret = I40E_SUCCESS;
7119
7120         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7121                 return I40E_ERR_PARAM;
7122
7123         /* If it's already set, just return */
7124         if (i40e_find_vlan_filter(vsi,vlan))
7125                 return I40E_SUCCESS;
7126
7127         mac_num = vsi->mac_num;
7128
7129         if (mac_num == 0) {
7130                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7131                 return I40E_ERR_PARAM;
7132         }
7133
7134         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7135
7136         if (mv_f == NULL) {
7137                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7138                 return I40E_ERR_NO_MEMORY;
7139         }
7140
7141         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7142
7143         if (ret != I40E_SUCCESS)
7144                 goto DONE;
7145
7146         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7147
7148         if (ret != I40E_SUCCESS)
7149                 goto DONE;
7150
7151         i40e_set_vlan_filter(vsi, vlan, 1);
7152
7153         vsi->vlan_num++;
7154         ret = I40E_SUCCESS;
7155 DONE:
7156         rte_free(mv_f);
7157         return ret;
7158 }
7159
7160 int
7161 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7162 {
7163         struct i40e_macvlan_filter *mv_f;
7164         int mac_num;
7165         int ret = I40E_SUCCESS;
7166
7167         /**
7168          * Vlan 0 is the generic filter for untagged packets
7169          * and can't be removed.
7170          */
7171         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7172                 return I40E_ERR_PARAM;
7173
7174         /* If can't find it, just return */
7175         if (!i40e_find_vlan_filter(vsi, vlan))
7176                 return I40E_ERR_PARAM;
7177
7178         mac_num = vsi->mac_num;
7179
7180         if (mac_num == 0) {
7181                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7182                 return I40E_ERR_PARAM;
7183         }
7184
7185         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7186
7187         if (mv_f == NULL) {
7188                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7189                 return I40E_ERR_NO_MEMORY;
7190         }
7191
7192         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7193
7194         if (ret != I40E_SUCCESS)
7195                 goto DONE;
7196
7197         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7198
7199         if (ret != I40E_SUCCESS)
7200                 goto DONE;
7201
7202         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7203         if (vsi->vlan_num == 1) {
7204                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7205                 if (ret != I40E_SUCCESS)
7206                         goto DONE;
7207
7208                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7209                 if (ret != I40E_SUCCESS)
7210                         goto DONE;
7211         }
7212
7213         i40e_set_vlan_filter(vsi, vlan, 0);
7214
7215         vsi->vlan_num--;
7216         ret = I40E_SUCCESS;
7217 DONE:
7218         rte_free(mv_f);
7219         return ret;
7220 }
7221
7222 int
7223 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7224 {
7225         struct i40e_mac_filter *f;
7226         struct i40e_macvlan_filter *mv_f;
7227         int i, vlan_num = 0;
7228         int ret = I40E_SUCCESS;
7229
7230         /* If it's add and we've config it, return */
7231         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7232         if (f != NULL)
7233                 return I40E_SUCCESS;
7234         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7235                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7236
7237                 /**
7238                  * If vlan_num is 0, that's the first time to add mac,
7239                  * set mask for vlan_id 0.
7240                  */
7241                 if (vsi->vlan_num == 0) {
7242                         i40e_set_vlan_filter(vsi, 0, 1);
7243                         vsi->vlan_num = 1;
7244                 }
7245                 vlan_num = vsi->vlan_num;
7246         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7247                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7248                 vlan_num = 1;
7249
7250         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7251         if (mv_f == NULL) {
7252                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7253                 return I40E_ERR_NO_MEMORY;
7254         }
7255
7256         for (i = 0; i < vlan_num; i++) {
7257                 mv_f[i].filter_type = mac_filter->filter_type;
7258                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7259                                 ETH_ADDR_LEN);
7260         }
7261
7262         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7263                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7264                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7265                                         &mac_filter->mac_addr);
7266                 if (ret != I40E_SUCCESS)
7267                         goto DONE;
7268         }
7269
7270         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7271         if (ret != I40E_SUCCESS)
7272                 goto DONE;
7273
7274         /* Add the mac addr into mac list */
7275         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7276         if (f == NULL) {
7277                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7278                 ret = I40E_ERR_NO_MEMORY;
7279                 goto DONE;
7280         }
7281         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7282                         ETH_ADDR_LEN);
7283         f->mac_info.filter_type = mac_filter->filter_type;
7284         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7285         vsi->mac_num++;
7286
7287         ret = I40E_SUCCESS;
7288 DONE:
7289         rte_free(mv_f);
7290
7291         return ret;
7292 }
7293
7294 int
7295 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7296 {
7297         struct i40e_mac_filter *f;
7298         struct i40e_macvlan_filter *mv_f;
7299         int i, vlan_num;
7300         enum rte_mac_filter_type filter_type;
7301         int ret = I40E_SUCCESS;
7302
7303         /* Can't find it, return an error */
7304         f = i40e_find_mac_filter(vsi, addr);
7305         if (f == NULL)
7306                 return I40E_ERR_PARAM;
7307
7308         vlan_num = vsi->vlan_num;
7309         filter_type = f->mac_info.filter_type;
7310         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7311                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7312                 if (vlan_num == 0) {
7313                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7314                         return I40E_ERR_PARAM;
7315                 }
7316         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7317                         filter_type == RTE_MAC_HASH_MATCH)
7318                 vlan_num = 1;
7319
7320         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7321         if (mv_f == NULL) {
7322                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7323                 return I40E_ERR_NO_MEMORY;
7324         }
7325
7326         for (i = 0; i < vlan_num; i++) {
7327                 mv_f[i].filter_type = filter_type;
7328                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7329                                 ETH_ADDR_LEN);
7330         }
7331         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7332                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7333                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7334                 if (ret != I40E_SUCCESS)
7335                         goto DONE;
7336         }
7337
7338         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7339         if (ret != I40E_SUCCESS)
7340                 goto DONE;
7341
7342         /* Remove the mac addr into mac list */
7343         TAILQ_REMOVE(&vsi->mac_list, f, next);
7344         rte_free(f);
7345         vsi->mac_num--;
7346
7347         ret = I40E_SUCCESS;
7348 DONE:
7349         rte_free(mv_f);
7350         return ret;
7351 }
7352
7353 /* Configure hash enable flags for RSS */
7354 uint64_t
7355 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7356 {
7357         uint64_t hena = 0;
7358         int i;
7359
7360         if (!flags)
7361                 return hena;
7362
7363         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7364                 if (flags & (1ULL << i))
7365                         hena |= adapter->pctypes_tbl[i];
7366         }
7367
7368         return hena;
7369 }
7370
7371 /* Parse the hash enable flags */
7372 uint64_t
7373 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7374 {
7375         uint64_t rss_hf = 0;
7376
7377         if (!flags)
7378                 return rss_hf;
7379         int i;
7380
7381         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7382                 if (flags & adapter->pctypes_tbl[i])
7383                         rss_hf |= (1ULL << i);
7384         }
7385         return rss_hf;
7386 }
7387
7388 /* Disable RSS */
7389 static void
7390 i40e_pf_disable_rss(struct i40e_pf *pf)
7391 {
7392         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7393
7394         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7395         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7396         I40E_WRITE_FLUSH(hw);
7397 }
7398
7399 int
7400 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7401 {
7402         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7403         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7404         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7405                            I40E_VFQF_HKEY_MAX_INDEX :
7406                            I40E_PFQF_HKEY_MAX_INDEX;
7407         int ret = 0;
7408
7409         if (!key || key_len == 0) {
7410                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7411                 return 0;
7412         } else if (key_len != (key_idx + 1) *
7413                 sizeof(uint32_t)) {
7414                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7415                 return -EINVAL;
7416         }
7417
7418         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7419                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7420                         (struct i40e_aqc_get_set_rss_key_data *)key;
7421
7422                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7423                 if (ret)
7424                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7425         } else {
7426                 uint32_t *hash_key = (uint32_t *)key;
7427                 uint16_t i;
7428
7429                 if (vsi->type == I40E_VSI_SRIOV) {
7430                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7431                                 I40E_WRITE_REG(
7432                                         hw,
7433                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7434                                         hash_key[i]);
7435
7436                 } else {
7437                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7438                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7439                                                hash_key[i]);
7440                 }
7441                 I40E_WRITE_FLUSH(hw);
7442         }
7443
7444         return ret;
7445 }
7446
7447 static int
7448 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7449 {
7450         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7451         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7452         uint32_t reg;
7453         int ret;
7454
7455         if (!key || !key_len)
7456                 return 0;
7457
7458         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7459                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7460                         (struct i40e_aqc_get_set_rss_key_data *)key);
7461                 if (ret) {
7462                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7463                         return ret;
7464                 }
7465         } else {
7466                 uint32_t *key_dw = (uint32_t *)key;
7467                 uint16_t i;
7468
7469                 if (vsi->type == I40E_VSI_SRIOV) {
7470                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7471                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7472                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7473                         }
7474                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7475                                    sizeof(uint32_t);
7476                 } else {
7477                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7478                                 reg = I40E_PFQF_HKEY(i);
7479                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7480                         }
7481                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7482                                    sizeof(uint32_t);
7483                 }
7484         }
7485         return 0;
7486 }
7487
7488 static int
7489 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7490 {
7491         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7492         uint64_t hena;
7493         int ret;
7494
7495         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7496                                rss_conf->rss_key_len);
7497         if (ret)
7498                 return ret;
7499
7500         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7501         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7502         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7503         I40E_WRITE_FLUSH(hw);
7504
7505         return 0;
7506 }
7507
7508 static int
7509 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7510                          struct rte_eth_rss_conf *rss_conf)
7511 {
7512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7514         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7515         uint64_t hena;
7516
7517         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7518         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7519
7520         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7521                 if (rss_hf != 0) /* Enable RSS */
7522                         return -EINVAL;
7523                 return 0; /* Nothing to do */
7524         }
7525         /* RSS enabled */
7526         if (rss_hf == 0) /* Disable RSS */
7527                 return -EINVAL;
7528
7529         return i40e_hw_rss_hash_set(pf, rss_conf);
7530 }
7531
7532 static int
7533 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7534                            struct rte_eth_rss_conf *rss_conf)
7535 {
7536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7538         uint64_t hena;
7539         int ret;
7540
7541         if (!rss_conf)
7542                 return -EINVAL;
7543
7544         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7545                          &rss_conf->rss_key_len);
7546         if (ret)
7547                 return ret;
7548
7549         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7550         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7551         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7552
7553         return 0;
7554 }
7555
7556 static int
7557 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7558 {
7559         switch (filter_type) {
7560         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7561                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7562                 break;
7563         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7564                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7565                 break;
7566         case RTE_TUNNEL_FILTER_IMAC_TENID:
7567                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7568                 break;
7569         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7570                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7571                 break;
7572         case ETH_TUNNEL_FILTER_IMAC:
7573                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7574                 break;
7575         case ETH_TUNNEL_FILTER_OIP:
7576                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7577                 break;
7578         case ETH_TUNNEL_FILTER_IIP:
7579                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7580                 break;
7581         default:
7582                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7583                 return -EINVAL;
7584         }
7585
7586         return 0;
7587 }
7588
7589 /* Convert tunnel filter structure */
7590 static int
7591 i40e_tunnel_filter_convert(
7592         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7593         struct i40e_tunnel_filter *tunnel_filter)
7594 {
7595         rte_ether_addr_copy((struct rte_ether_addr *)
7596                         &cld_filter->element.outer_mac,
7597                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7598         rte_ether_addr_copy((struct rte_ether_addr *)
7599                         &cld_filter->element.inner_mac,
7600                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7601         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7602         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7603              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7604             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7605                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7606         else
7607                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7608         tunnel_filter->input.flags = cld_filter->element.flags;
7609         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7610         tunnel_filter->queue = cld_filter->element.queue_number;
7611         rte_memcpy(tunnel_filter->input.general_fields,
7612                    cld_filter->general_fields,
7613                    sizeof(cld_filter->general_fields));
7614
7615         return 0;
7616 }
7617
7618 /* Check if there exists the tunnel filter */
7619 struct i40e_tunnel_filter *
7620 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7621                              const struct i40e_tunnel_filter_input *input)
7622 {
7623         int ret;
7624
7625         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7626         if (ret < 0)
7627                 return NULL;
7628
7629         return tunnel_rule->hash_map[ret];
7630 }
7631
7632 /* Add a tunnel filter into the SW list */
7633 static int
7634 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7635                              struct i40e_tunnel_filter *tunnel_filter)
7636 {
7637         struct i40e_tunnel_rule *rule = &pf->tunnel;
7638         int ret;
7639
7640         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7641         if (ret < 0) {
7642                 PMD_DRV_LOG(ERR,
7643                             "Failed to insert tunnel filter to hash table %d!",
7644                             ret);
7645                 return ret;
7646         }
7647         rule->hash_map[ret] = tunnel_filter;
7648
7649         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7650
7651         return 0;
7652 }
7653
7654 /* Delete a tunnel filter from the SW list */
7655 int
7656 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7657                           struct i40e_tunnel_filter_input *input)
7658 {
7659         struct i40e_tunnel_rule *rule = &pf->tunnel;
7660         struct i40e_tunnel_filter *tunnel_filter;
7661         int ret;
7662
7663         ret = rte_hash_del_key(rule->hash_table, input);
7664         if (ret < 0) {
7665                 PMD_DRV_LOG(ERR,
7666                             "Failed to delete tunnel filter to hash table %d!",
7667                             ret);
7668                 return ret;
7669         }
7670         tunnel_filter = rule->hash_map[ret];
7671         rule->hash_map[ret] = NULL;
7672
7673         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7674         rte_free(tunnel_filter);
7675
7676         return 0;
7677 }
7678
7679 int
7680 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7681                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7682                         uint8_t add)
7683 {
7684         uint16_t ip_type;
7685         uint32_t ipv4_addr, ipv4_addr_le;
7686         uint8_t i, tun_type = 0;
7687         /* internal varialbe to convert ipv6 byte order */
7688         uint32_t convert_ipv6[4];
7689         int val, ret = 0;
7690         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7691         struct i40e_vsi *vsi = pf->main_vsi;
7692         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7693         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7694         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7695         struct i40e_tunnel_filter *tunnel, *node;
7696         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7697
7698         cld_filter = rte_zmalloc("tunnel_filter",
7699                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7700         0);
7701
7702         if (NULL == cld_filter) {
7703                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7704                 return -ENOMEM;
7705         }
7706         pfilter = cld_filter;
7707
7708         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7709                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7710         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7711                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7712
7713         pfilter->element.inner_vlan =
7714                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7715         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7716                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7717                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7718                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7719                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7720                                 &ipv4_addr_le,
7721                                 sizeof(pfilter->element.ipaddr.v4.data));
7722         } else {
7723                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7724                 for (i = 0; i < 4; i++) {
7725                         convert_ipv6[i] =
7726                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7727                 }
7728                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7729                            &convert_ipv6,
7730                            sizeof(pfilter->element.ipaddr.v6.data));
7731         }
7732
7733         /* check tunneled type */
7734         switch (tunnel_filter->tunnel_type) {
7735         case RTE_TUNNEL_TYPE_VXLAN:
7736                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7737                 break;
7738         case RTE_TUNNEL_TYPE_NVGRE:
7739                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7740                 break;
7741         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7742                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7743                 break;
7744         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7745                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7746                 break;
7747         default:
7748                 /* Other tunnel types is not supported. */
7749                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7750                 rte_free(cld_filter);
7751                 return -EINVAL;
7752         }
7753
7754         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7755                                        &pfilter->element.flags);
7756         if (val < 0) {
7757                 rte_free(cld_filter);
7758                 return -EINVAL;
7759         }
7760
7761         pfilter->element.flags |= rte_cpu_to_le_16(
7762                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7763                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7764         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7765         pfilter->element.queue_number =
7766                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7767
7768         /* Check if there is the filter in SW list */
7769         memset(&check_filter, 0, sizeof(check_filter));
7770         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7771         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7772         if (add && node) {
7773                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7774                 rte_free(cld_filter);
7775                 return -EINVAL;
7776         }
7777
7778         if (!add && !node) {
7779                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7780                 rte_free(cld_filter);
7781                 return -EINVAL;
7782         }
7783
7784         if (add) {
7785                 ret = i40e_aq_add_cloud_filters(hw,
7786                                         vsi->seid, &cld_filter->element, 1);
7787                 if (ret < 0) {
7788                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7789                         rte_free(cld_filter);
7790                         return -ENOTSUP;
7791                 }
7792                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7793                 if (tunnel == NULL) {
7794                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7795                         rte_free(cld_filter);
7796                         return -ENOMEM;
7797                 }
7798
7799                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7800                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7801                 if (ret < 0)
7802                         rte_free(tunnel);
7803         } else {
7804                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7805                                                    &cld_filter->element, 1);
7806                 if (ret < 0) {
7807                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7808                         rte_free(cld_filter);
7809                         return -ENOTSUP;
7810                 }
7811                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7812         }
7813
7814         rte_free(cld_filter);
7815         return ret;
7816 }
7817
7818 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7819 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7820 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7821 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7822 #define I40E_TR_GRE_KEY_MASK                    0x400
7823 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7824 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7825
7826 static enum
7827 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7828 {
7829         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7830         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7831         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7832         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7833         enum i40e_status_code status = I40E_SUCCESS;
7834
7835         if (pf->support_multi_driver) {
7836                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7837                 return I40E_NOT_SUPPORTED;
7838         }
7839
7840         memset(&filter_replace, 0,
7841                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7842         memset(&filter_replace_buf, 0,
7843                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7844
7845         /* create L1 filter */
7846         filter_replace.old_filter_type =
7847                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7848         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7849         filter_replace.tr_bit = 0;
7850
7851         /* Prepare the buffer, 3 entries */
7852         filter_replace_buf.data[0] =
7853                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7854         filter_replace_buf.data[0] |=
7855                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7856         filter_replace_buf.data[2] = 0xFF;
7857         filter_replace_buf.data[3] = 0xFF;
7858         filter_replace_buf.data[4] =
7859                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7860         filter_replace_buf.data[4] |=
7861                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7862         filter_replace_buf.data[7] = 0xF0;
7863         filter_replace_buf.data[8]
7864                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7865         filter_replace_buf.data[8] |=
7866                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7867         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7868                 I40E_TR_GENEVE_KEY_MASK |
7869                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7870         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7871                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7872                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7873
7874         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7875                                                &filter_replace_buf);
7876         if (!status && (filter_replace.old_filter_type !=
7877                         filter_replace.new_filter_type))
7878                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7879                             " original: 0x%x, new: 0x%x",
7880                             dev->device->name,
7881                             filter_replace.old_filter_type,
7882                             filter_replace.new_filter_type);
7883
7884         return status;
7885 }
7886
7887 static enum
7888 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7889 {
7890         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7891         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7892         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7893         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7894         enum i40e_status_code status = I40E_SUCCESS;
7895
7896         if (pf->support_multi_driver) {
7897                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7898                 return I40E_NOT_SUPPORTED;
7899         }
7900
7901         /* For MPLSoUDP */
7902         memset(&filter_replace, 0,
7903                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7904         memset(&filter_replace_buf, 0,
7905                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7906         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7907                 I40E_AQC_MIRROR_CLOUD_FILTER;
7908         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7909         filter_replace.new_filter_type =
7910                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7911         /* Prepare the buffer, 2 entries */
7912         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7913         filter_replace_buf.data[0] |=
7914                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7915         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7916         filter_replace_buf.data[4] |=
7917                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7918         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7919                                                &filter_replace_buf);
7920         if (status < 0)
7921                 return status;
7922         if (filter_replace.old_filter_type !=
7923             filter_replace.new_filter_type)
7924                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7925                             " original: 0x%x, new: 0x%x",
7926                             dev->device->name,
7927                             filter_replace.old_filter_type,
7928                             filter_replace.new_filter_type);
7929
7930         /* For MPLSoGRE */
7931         memset(&filter_replace, 0,
7932                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7933         memset(&filter_replace_buf, 0,
7934                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7935
7936         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7937                 I40E_AQC_MIRROR_CLOUD_FILTER;
7938         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7939         filter_replace.new_filter_type =
7940                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7941         /* Prepare the buffer, 2 entries */
7942         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7943         filter_replace_buf.data[0] |=
7944                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7945         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7946         filter_replace_buf.data[4] |=
7947                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7948
7949         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7950                                                &filter_replace_buf);
7951         if (!status && (filter_replace.old_filter_type !=
7952                         filter_replace.new_filter_type))
7953                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7954                             " original: 0x%x, new: 0x%x",
7955                             dev->device->name,
7956                             filter_replace.old_filter_type,
7957                             filter_replace.new_filter_type);
7958
7959         return status;
7960 }
7961
7962 static enum i40e_status_code
7963 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7964 {
7965         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7966         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7967         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7968         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7969         enum i40e_status_code status = I40E_SUCCESS;
7970
7971         if (pf->support_multi_driver) {
7972                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7973                 return I40E_NOT_SUPPORTED;
7974         }
7975
7976         /* For GTP-C */
7977         memset(&filter_replace, 0,
7978                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7979         memset(&filter_replace_buf, 0,
7980                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7981         /* create L1 filter */
7982         filter_replace.old_filter_type =
7983                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7984         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7985         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7986                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7987         /* Prepare the buffer, 2 entries */
7988         filter_replace_buf.data[0] =
7989                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7990         filter_replace_buf.data[0] |=
7991                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7992         filter_replace_buf.data[2] = 0xFF;
7993         filter_replace_buf.data[3] = 0xFF;
7994         filter_replace_buf.data[4] =
7995                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7996         filter_replace_buf.data[4] |=
7997                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7998         filter_replace_buf.data[6] = 0xFF;
7999         filter_replace_buf.data[7] = 0xFF;
8000         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8001                                                &filter_replace_buf);
8002         if (status < 0)
8003                 return status;
8004         if (filter_replace.old_filter_type !=
8005             filter_replace.new_filter_type)
8006                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8007                             " original: 0x%x, new: 0x%x",
8008                             dev->device->name,
8009                             filter_replace.old_filter_type,
8010                             filter_replace.new_filter_type);
8011
8012         /* for GTP-U */
8013         memset(&filter_replace, 0,
8014                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8015         memset(&filter_replace_buf, 0,
8016                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8017         /* create L1 filter */
8018         filter_replace.old_filter_type =
8019                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8020         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8021         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8022                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8023         /* Prepare the buffer, 2 entries */
8024         filter_replace_buf.data[0] =
8025                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8026         filter_replace_buf.data[0] |=
8027                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8028         filter_replace_buf.data[2] = 0xFF;
8029         filter_replace_buf.data[3] = 0xFF;
8030         filter_replace_buf.data[4] =
8031                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8032         filter_replace_buf.data[4] |=
8033                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8034         filter_replace_buf.data[6] = 0xFF;
8035         filter_replace_buf.data[7] = 0xFF;
8036
8037         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8038                                                &filter_replace_buf);
8039         if (!status && (filter_replace.old_filter_type !=
8040                         filter_replace.new_filter_type))
8041                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8042                             " original: 0x%x, new: 0x%x",
8043                             dev->device->name,
8044                             filter_replace.old_filter_type,
8045                             filter_replace.new_filter_type);
8046
8047         return status;
8048 }
8049
8050 static enum
8051 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8052 {
8053         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8054         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8055         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8056         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8057         enum i40e_status_code status = I40E_SUCCESS;
8058
8059         if (pf->support_multi_driver) {
8060                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8061                 return I40E_NOT_SUPPORTED;
8062         }
8063
8064         /* for GTP-C */
8065         memset(&filter_replace, 0,
8066                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8067         memset(&filter_replace_buf, 0,
8068                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8069         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8070         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8071         filter_replace.new_filter_type =
8072                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8073         /* Prepare the buffer, 2 entries */
8074         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8075         filter_replace_buf.data[0] |=
8076                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8077         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8078         filter_replace_buf.data[4] |=
8079                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8080         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8081                                                &filter_replace_buf);
8082         if (status < 0)
8083                 return status;
8084         if (filter_replace.old_filter_type !=
8085             filter_replace.new_filter_type)
8086                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8087                             " original: 0x%x, new: 0x%x",
8088                             dev->device->name,
8089                             filter_replace.old_filter_type,
8090                             filter_replace.new_filter_type);
8091
8092         /* for GTP-U */
8093         memset(&filter_replace, 0,
8094                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8095         memset(&filter_replace_buf, 0,
8096                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8097         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8098         filter_replace.old_filter_type =
8099                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8100         filter_replace.new_filter_type =
8101                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8102         /* Prepare the buffer, 2 entries */
8103         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8104         filter_replace_buf.data[0] |=
8105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8106         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8107         filter_replace_buf.data[4] |=
8108                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8109
8110         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8111                                                &filter_replace_buf);
8112         if (!status && (filter_replace.old_filter_type !=
8113                         filter_replace.new_filter_type))
8114                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8115                             " original: 0x%x, new: 0x%x",
8116                             dev->device->name,
8117                             filter_replace.old_filter_type,
8118                             filter_replace.new_filter_type);
8119
8120         return status;
8121 }
8122
8123 int
8124 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8125                       struct i40e_tunnel_filter_conf *tunnel_filter,
8126                       uint8_t add)
8127 {
8128         uint16_t ip_type;
8129         uint32_t ipv4_addr, ipv4_addr_le;
8130         uint8_t i, tun_type = 0;
8131         /* internal variable to convert ipv6 byte order */
8132         uint32_t convert_ipv6[4];
8133         int val, ret = 0;
8134         struct i40e_pf_vf *vf = NULL;
8135         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8136         struct i40e_vsi *vsi;
8137         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8138         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8139         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8140         struct i40e_tunnel_filter *tunnel, *node;
8141         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8142         uint32_t teid_le;
8143         bool big_buffer = 0;
8144
8145         cld_filter = rte_zmalloc("tunnel_filter",
8146                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8147                          0);
8148
8149         if (cld_filter == NULL) {
8150                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8151                 return -ENOMEM;
8152         }
8153         pfilter = cld_filter;
8154
8155         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8156                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8157         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8158                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8159
8160         pfilter->element.inner_vlan =
8161                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8162         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8163                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8164                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8165                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8166                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8167                                 &ipv4_addr_le,
8168                                 sizeof(pfilter->element.ipaddr.v4.data));
8169         } else {
8170                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8171                 for (i = 0; i < 4; i++) {
8172                         convert_ipv6[i] =
8173                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8174                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8175                 }
8176                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8177                            &convert_ipv6,
8178                            sizeof(pfilter->element.ipaddr.v6.data));
8179         }
8180
8181         /* check tunneled type */
8182         switch (tunnel_filter->tunnel_type) {
8183         case I40E_TUNNEL_TYPE_VXLAN:
8184                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8185                 break;
8186         case I40E_TUNNEL_TYPE_NVGRE:
8187                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8188                 break;
8189         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8190                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8191                 break;
8192         case I40E_TUNNEL_TYPE_MPLSoUDP:
8193                 if (!pf->mpls_replace_flag) {
8194                         i40e_replace_mpls_l1_filter(pf);
8195                         i40e_replace_mpls_cloud_filter(pf);
8196                         pf->mpls_replace_flag = 1;
8197                 }
8198                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8199                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8200                         teid_le >> 4;
8201                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8202                         (teid_le & 0xF) << 12;
8203                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8204                         0x40;
8205                 big_buffer = 1;
8206                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8207                 break;
8208         case I40E_TUNNEL_TYPE_MPLSoGRE:
8209                 if (!pf->mpls_replace_flag) {
8210                         i40e_replace_mpls_l1_filter(pf);
8211                         i40e_replace_mpls_cloud_filter(pf);
8212                         pf->mpls_replace_flag = 1;
8213                 }
8214                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8215                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8216                         teid_le >> 4;
8217                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8218                         (teid_le & 0xF) << 12;
8219                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8220                         0x0;
8221                 big_buffer = 1;
8222                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8223                 break;
8224         case I40E_TUNNEL_TYPE_GTPC:
8225                 if (!pf->gtp_replace_flag) {
8226                         i40e_replace_gtp_l1_filter(pf);
8227                         i40e_replace_gtp_cloud_filter(pf);
8228                         pf->gtp_replace_flag = 1;
8229                 }
8230                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8231                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8232                         (teid_le >> 16) & 0xFFFF;
8233                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8234                         teid_le & 0xFFFF;
8235                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8236                         0x0;
8237                 big_buffer = 1;
8238                 break;
8239         case I40E_TUNNEL_TYPE_GTPU:
8240                 if (!pf->gtp_replace_flag) {
8241                         i40e_replace_gtp_l1_filter(pf);
8242                         i40e_replace_gtp_cloud_filter(pf);
8243                         pf->gtp_replace_flag = 1;
8244                 }
8245                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8246                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8247                         (teid_le >> 16) & 0xFFFF;
8248                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8249                         teid_le & 0xFFFF;
8250                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8251                         0x0;
8252                 big_buffer = 1;
8253                 break;
8254         case I40E_TUNNEL_TYPE_QINQ:
8255                 if (!pf->qinq_replace_flag) {
8256                         ret = i40e_cloud_filter_qinq_create(pf);
8257                         if (ret < 0)
8258                                 PMD_DRV_LOG(DEBUG,
8259                                             "QinQ tunnel filter already created.");
8260                         pf->qinq_replace_flag = 1;
8261                 }
8262                 /*      Add in the General fields the values of
8263                  *      the Outer and Inner VLAN
8264                  *      Big Buffer should be set, see changes in
8265                  *      i40e_aq_add_cloud_filters
8266                  */
8267                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8268                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8269                 big_buffer = 1;
8270                 break;
8271         default:
8272                 /* Other tunnel types is not supported. */
8273                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8274                 rte_free(cld_filter);
8275                 return -EINVAL;
8276         }
8277
8278         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8279                 pfilter->element.flags =
8280                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8281         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8282                 pfilter->element.flags =
8283                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8284         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8285                 pfilter->element.flags =
8286                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8287         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8288                 pfilter->element.flags =
8289                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8290         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8291                 pfilter->element.flags |=
8292                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8293         else {
8294                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8295                                                 &pfilter->element.flags);
8296                 if (val < 0) {
8297                         rte_free(cld_filter);
8298                         return -EINVAL;
8299                 }
8300         }
8301
8302         pfilter->element.flags |= rte_cpu_to_le_16(
8303                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8304                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8305         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8306         pfilter->element.queue_number =
8307                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8308
8309         if (!tunnel_filter->is_to_vf)
8310                 vsi = pf->main_vsi;
8311         else {
8312                 if (tunnel_filter->vf_id >= pf->vf_num) {
8313                         PMD_DRV_LOG(ERR, "Invalid argument.");
8314                         rte_free(cld_filter);
8315                         return -EINVAL;
8316                 }
8317                 vf = &pf->vfs[tunnel_filter->vf_id];
8318                 vsi = vf->vsi;
8319         }
8320
8321         /* Check if there is the filter in SW list */
8322         memset(&check_filter, 0, sizeof(check_filter));
8323         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8324         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8325         check_filter.vf_id = tunnel_filter->vf_id;
8326         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8327         if (add && node) {
8328                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8329                 rte_free(cld_filter);
8330                 return -EINVAL;
8331         }
8332
8333         if (!add && !node) {
8334                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8335                 rte_free(cld_filter);
8336                 return -EINVAL;
8337         }
8338
8339         if (add) {
8340                 if (big_buffer)
8341                         ret = i40e_aq_add_cloud_filters_bb(hw,
8342                                                    vsi->seid, cld_filter, 1);
8343                 else
8344                         ret = i40e_aq_add_cloud_filters(hw,
8345                                         vsi->seid, &cld_filter->element, 1);
8346                 if (ret < 0) {
8347                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8348                         rte_free(cld_filter);
8349                         return -ENOTSUP;
8350                 }
8351                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8352                 if (tunnel == NULL) {
8353                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8354                         rte_free(cld_filter);
8355                         return -ENOMEM;
8356                 }
8357
8358                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8359                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8360                 if (ret < 0)
8361                         rte_free(tunnel);
8362         } else {
8363                 if (big_buffer)
8364                         ret = i40e_aq_rem_cloud_filters_bb(
8365                                 hw, vsi->seid, cld_filter, 1);
8366                 else
8367                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8368                                                 &cld_filter->element, 1);
8369                 if (ret < 0) {
8370                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8371                         rte_free(cld_filter);
8372                         return -ENOTSUP;
8373                 }
8374                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8375         }
8376
8377         rte_free(cld_filter);
8378         return ret;
8379 }
8380
8381 static int
8382 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8383 {
8384         uint8_t i;
8385
8386         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8387                 if (pf->vxlan_ports[i] == port)
8388                         return i;
8389         }
8390
8391         return -1;
8392 }
8393
8394 static int
8395 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8396 {
8397         int  idx, ret;
8398         uint8_t filter_idx;
8399         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8400
8401         idx = i40e_get_vxlan_port_idx(pf, port);
8402
8403         /* Check if port already exists */
8404         if (idx >= 0) {
8405                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8406                 return -EINVAL;
8407         }
8408
8409         /* Now check if there is space to add the new port */
8410         idx = i40e_get_vxlan_port_idx(pf, 0);
8411         if (idx < 0) {
8412                 PMD_DRV_LOG(ERR,
8413                         "Maximum number of UDP ports reached, not adding port %d",
8414                         port);
8415                 return -ENOSPC;
8416         }
8417
8418         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8419                                         &filter_idx, NULL);
8420         if (ret < 0) {
8421                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8422                 return -1;
8423         }
8424
8425         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8426                          port,  filter_idx);
8427
8428         /* New port: add it and mark its index in the bitmap */
8429         pf->vxlan_ports[idx] = port;
8430         pf->vxlan_bitmap |= (1 << idx);
8431
8432         if (!(pf->flags & I40E_FLAG_VXLAN))
8433                 pf->flags |= I40E_FLAG_VXLAN;
8434
8435         return 0;
8436 }
8437
8438 static int
8439 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8440 {
8441         int idx;
8442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8443
8444         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8445                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8446                 return -EINVAL;
8447         }
8448
8449         idx = i40e_get_vxlan_port_idx(pf, port);
8450
8451         if (idx < 0) {
8452                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8453                 return -EINVAL;
8454         }
8455
8456         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8457                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8458                 return -1;
8459         }
8460
8461         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8462                         port, idx);
8463
8464         pf->vxlan_ports[idx] = 0;
8465         pf->vxlan_bitmap &= ~(1 << idx);
8466
8467         if (!pf->vxlan_bitmap)
8468                 pf->flags &= ~I40E_FLAG_VXLAN;
8469
8470         return 0;
8471 }
8472
8473 /* Add UDP tunneling port */
8474 static int
8475 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8476                              struct rte_eth_udp_tunnel *udp_tunnel)
8477 {
8478         int ret = 0;
8479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8480
8481         if (udp_tunnel == NULL)
8482                 return -EINVAL;
8483
8484         switch (udp_tunnel->prot_type) {
8485         case RTE_TUNNEL_TYPE_VXLAN:
8486                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8487                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8488                 break;
8489         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8490                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8491                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8492                 break;
8493         case RTE_TUNNEL_TYPE_GENEVE:
8494         case RTE_TUNNEL_TYPE_TEREDO:
8495                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8496                 ret = -1;
8497                 break;
8498
8499         default:
8500                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8501                 ret = -1;
8502                 break;
8503         }
8504
8505         return ret;
8506 }
8507
8508 /* Remove UDP tunneling port */
8509 static int
8510 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8511                              struct rte_eth_udp_tunnel *udp_tunnel)
8512 {
8513         int ret = 0;
8514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8515
8516         if (udp_tunnel == NULL)
8517                 return -EINVAL;
8518
8519         switch (udp_tunnel->prot_type) {
8520         case RTE_TUNNEL_TYPE_VXLAN:
8521         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8522                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8523                 break;
8524         case RTE_TUNNEL_TYPE_GENEVE:
8525         case RTE_TUNNEL_TYPE_TEREDO:
8526                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8527                 ret = -1;
8528                 break;
8529         default:
8530                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8531                 ret = -1;
8532                 break;
8533         }
8534
8535         return ret;
8536 }
8537
8538 /* Calculate the maximum number of contiguous PF queues that are configured */
8539 static int
8540 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8541 {
8542         struct rte_eth_dev_data *data = pf->dev_data;
8543         int i, num;
8544         struct i40e_rx_queue *rxq;
8545
8546         num = 0;
8547         for (i = 0; i < pf->lan_nb_qps; i++) {
8548                 rxq = data->rx_queues[i];
8549                 if (rxq && rxq->q_set)
8550                         num++;
8551                 else
8552                         break;
8553         }
8554
8555         return num;
8556 }
8557
8558 /* Configure RSS */
8559 static int
8560 i40e_pf_config_rss(struct i40e_pf *pf)
8561 {
8562         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8563         struct rte_eth_rss_conf rss_conf;
8564         uint32_t i, lut = 0;
8565         uint16_t j, num;
8566
8567         /*
8568          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8569          * It's necessary to calculate the actual PF queues that are configured.
8570          */
8571         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8572                 num = i40e_pf_calc_configured_queues_num(pf);
8573         else
8574                 num = pf->dev_data->nb_rx_queues;
8575
8576         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8577         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8578                         num);
8579
8580         if (num == 0) {
8581                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8582                 return -ENOTSUP;
8583         }
8584
8585         if (pf->adapter->rss_reta_updated == 0) {
8586                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8587                         if (j == num)
8588                                 j = 0;
8589                         lut = (lut << 8) | (j & ((0x1 <<
8590                                 hw->func_caps.rss_table_entry_width) - 1));
8591                         if ((i & 3) == 3)
8592                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8593                                                rte_bswap32(lut));
8594                 }
8595         }
8596
8597         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8598         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8599                 i40e_pf_disable_rss(pf);
8600                 return 0;
8601         }
8602         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8603                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8604                 /* Random default keys */
8605                 static uint32_t rss_key_default[] = {0x6b793944,
8606                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8607                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8608                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8609
8610                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8611                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8612                                                         sizeof(uint32_t);
8613         }
8614
8615         return i40e_hw_rss_hash_set(pf, &rss_conf);
8616 }
8617
8618 static int
8619 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8620                                struct rte_eth_tunnel_filter_conf *filter)
8621 {
8622         if (pf == NULL || filter == NULL) {
8623                 PMD_DRV_LOG(ERR, "Invalid parameter");
8624                 return -EINVAL;
8625         }
8626
8627         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8628                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8629                 return -EINVAL;
8630         }
8631
8632         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8633                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8634                 return -EINVAL;
8635         }
8636
8637         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8638                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8639                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8640                 return -EINVAL;
8641         }
8642
8643         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8644                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8645                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8646                 return -EINVAL;
8647         }
8648
8649         return 0;
8650 }
8651
8652 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8653 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8654 static int
8655 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8656 {
8657         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8658         uint32_t val, reg;
8659         int ret = -EINVAL;
8660
8661         if (pf->support_multi_driver) {
8662                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8663                 return -ENOTSUP;
8664         }
8665
8666         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8667         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8668
8669         if (len == 3) {
8670                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8671         } else if (len == 4) {
8672                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8673         } else {
8674                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8675                 return ret;
8676         }
8677
8678         if (reg != val) {
8679                 ret = i40e_aq_debug_write_global_register(hw,
8680                                                    I40E_GL_PRS_FVBM(2),
8681                                                    reg, NULL);
8682                 if (ret != 0)
8683                         return ret;
8684                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8685                             "with value 0x%08x",
8686                             I40E_GL_PRS_FVBM(2), reg);
8687         } else {
8688                 ret = 0;
8689         }
8690         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8691                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8692
8693         return ret;
8694 }
8695
8696 static int
8697 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8698 {
8699         int ret = -EINVAL;
8700
8701         if (!hw || !cfg)
8702                 return -EINVAL;
8703
8704         switch (cfg->cfg_type) {
8705         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8706                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8707                 break;
8708         default:
8709                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8710                 break;
8711         }
8712
8713         return ret;
8714 }
8715
8716 static int
8717 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8718                                enum rte_filter_op filter_op,
8719                                void *arg)
8720 {
8721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8722         int ret = I40E_ERR_PARAM;
8723
8724         switch (filter_op) {
8725         case RTE_ETH_FILTER_SET:
8726                 ret = i40e_dev_global_config_set(hw,
8727                         (struct rte_eth_global_cfg *)arg);
8728                 break;
8729         default:
8730                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8731                 break;
8732         }
8733
8734         return ret;
8735 }
8736
8737 static int
8738 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8739                           enum rte_filter_op filter_op,
8740                           void *arg)
8741 {
8742         struct rte_eth_tunnel_filter_conf *filter;
8743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8744         int ret = I40E_SUCCESS;
8745
8746         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8747
8748         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8749                 return I40E_ERR_PARAM;
8750
8751         switch (filter_op) {
8752         case RTE_ETH_FILTER_NOP:
8753                 if (!(pf->flags & I40E_FLAG_VXLAN))
8754                         ret = I40E_NOT_SUPPORTED;
8755                 break;
8756         case RTE_ETH_FILTER_ADD:
8757                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8758                 break;
8759         case RTE_ETH_FILTER_DELETE:
8760                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8761                 break;
8762         default:
8763                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8764                 ret = I40E_ERR_PARAM;
8765                 break;
8766         }
8767
8768         return ret;
8769 }
8770
8771 static int
8772 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8773 {
8774         int ret = 0;
8775         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8776
8777         /* RSS setup */
8778         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8779                 ret = i40e_pf_config_rss(pf);
8780         else
8781                 i40e_pf_disable_rss(pf);
8782
8783         return ret;
8784 }
8785
8786 /* Get the symmetric hash enable configurations per port */
8787 static void
8788 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8789 {
8790         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8791
8792         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8793 }
8794
8795 /* Set the symmetric hash enable configurations per port */
8796 static void
8797 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8798 {
8799         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8800
8801         if (enable > 0) {
8802                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8803                         PMD_DRV_LOG(INFO,
8804                                 "Symmetric hash has already been enabled");
8805                         return;
8806                 }
8807                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8808         } else {
8809                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8810                         PMD_DRV_LOG(INFO,
8811                                 "Symmetric hash has already been disabled");
8812                         return;
8813                 }
8814                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8815         }
8816         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8817         I40E_WRITE_FLUSH(hw);
8818 }
8819
8820 /*
8821  * Get global configurations of hash function type and symmetric hash enable
8822  * per flow type (pctype). Note that global configuration means it affects all
8823  * the ports on the same NIC.
8824  */
8825 static int
8826 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8827                                    struct rte_eth_hash_global_conf *g_cfg)
8828 {
8829         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8830         uint32_t reg;
8831         uint16_t i, j;
8832
8833         memset(g_cfg, 0, sizeof(*g_cfg));
8834         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8835         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8836                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8837         else
8838                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8839         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8840                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8841
8842         /*
8843          * As i40e supports less than 64 flow types, only first 64 bits need to
8844          * be checked.
8845          */
8846         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8847                 g_cfg->valid_bit_mask[i] = 0ULL;
8848                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8849         }
8850
8851         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8852
8853         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8854                 if (!adapter->pctypes_tbl[i])
8855                         continue;
8856                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8857                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8858                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8859                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8860                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8861                                         g_cfg->sym_hash_enable_mask[0] |=
8862                                                                 (1ULL << i);
8863                                 }
8864                         }
8865                 }
8866         }
8867
8868         return 0;
8869 }
8870
8871 static int
8872 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8873                               const struct rte_eth_hash_global_conf *g_cfg)
8874 {
8875         uint32_t i;
8876         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8877
8878         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8879                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8880                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8881                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8882                                                 g_cfg->hash_func);
8883                 return -EINVAL;
8884         }
8885
8886         /*
8887          * As i40e supports less than 64 flow types, only first 64 bits need to
8888          * be checked.
8889          */
8890         mask0 = g_cfg->valid_bit_mask[0];
8891         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8892                 if (i == 0) {
8893                         /* Check if any unsupported flow type configured */
8894                         if ((mask0 | i40e_mask) ^ i40e_mask)
8895                                 goto mask_err;
8896                 } else {
8897                         if (g_cfg->valid_bit_mask[i])
8898                                 goto mask_err;
8899                 }
8900         }
8901
8902         return 0;
8903
8904 mask_err:
8905         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8906
8907         return -EINVAL;
8908 }
8909
8910 /*
8911  * Set global configurations of hash function type and symmetric hash enable
8912  * per flow type (pctype). Note any modifying global configuration will affect
8913  * all the ports on the same NIC.
8914  */
8915 static int
8916 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8917                                    struct rte_eth_hash_global_conf *g_cfg)
8918 {
8919         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8920         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8921         int ret;
8922         uint16_t i, j;
8923         uint32_t reg;
8924         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8925
8926         if (pf->support_multi_driver) {
8927                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8928                 return -ENOTSUP;
8929         }
8930
8931         /* Check the input parameters */
8932         ret = i40e_hash_global_config_check(adapter, g_cfg);
8933         if (ret < 0)
8934                 return ret;
8935
8936         /*
8937          * As i40e supports less than 64 flow types, only first 64 bits need to
8938          * be configured.
8939          */
8940         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8941                 if (mask0 & (1UL << i)) {
8942                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8943                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8944
8945                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8946                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8947                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8948                                         i40e_write_global_rx_ctl(hw,
8949                                                           I40E_GLQF_HSYM(j),
8950                                                           reg);
8951                         }
8952                 }
8953         }
8954
8955         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8956         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8957                 /* Toeplitz */
8958                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8959                         PMD_DRV_LOG(DEBUG,
8960                                 "Hash function already set to Toeplitz");
8961                         goto out;
8962                 }
8963                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8964         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8965                 /* Simple XOR */
8966                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8967                         PMD_DRV_LOG(DEBUG,
8968                                 "Hash function already set to Simple XOR");
8969                         goto out;
8970                 }
8971                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8972         } else
8973                 /* Use the default, and keep it as it is */
8974                 goto out;
8975
8976         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8977
8978 out:
8979         I40E_WRITE_FLUSH(hw);
8980
8981         return 0;
8982 }
8983
8984 /**
8985  * Valid input sets for hash and flow director filters per PCTYPE
8986  */
8987 static uint64_t
8988 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8989                 enum rte_filter_type filter)
8990 {
8991         uint64_t valid;
8992
8993         static const uint64_t valid_hash_inset_table[] = {
8994                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8995                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8996                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8997                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8998                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8999                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9000                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9001                         I40E_INSET_FLEX_PAYLOAD,
9002                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9003                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9004                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9005                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9006                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9007                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9008                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9009                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9010                         I40E_INSET_FLEX_PAYLOAD,
9011                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9012                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9013                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9014                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9015                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9016                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9017                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9018                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9019                         I40E_INSET_FLEX_PAYLOAD,
9020                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9021                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9022                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9023                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9024                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9025                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9026                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9027                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9028                         I40E_INSET_FLEX_PAYLOAD,
9029                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9030                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9031                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9032                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9033                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9034                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9035                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9036                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9037                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9038                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9039                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9040                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9041                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9042                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9043                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9044                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9045                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9046                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9047                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9048                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9049                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9050                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9051                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9052                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9053                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9054                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9055                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9056                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9057                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9058                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9060                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9061                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9062                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9063                         I40E_INSET_FLEX_PAYLOAD,
9064                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9065                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9066                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9067                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9068                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9069                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9070                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9071                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9072                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9076                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9077                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9078                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9079                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9080                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9081                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9082                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9083                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9084                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9085                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9086                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9087                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9088                         I40E_INSET_FLEX_PAYLOAD,
9089                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9090                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9091                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9092                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9093                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9094                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9095                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9096                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9097                         I40E_INSET_FLEX_PAYLOAD,
9098                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9099                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9100                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9101                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9102                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9103                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9104                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9105                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9106                         I40E_INSET_FLEX_PAYLOAD,
9107                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9108                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9109                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9110                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9111                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9112                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9113                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9114                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9115                         I40E_INSET_FLEX_PAYLOAD,
9116                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9117                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9118                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9119                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9120                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9121                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9122                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9123                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9124                         I40E_INSET_FLEX_PAYLOAD,
9125                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9129                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9130                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9131                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9132                         I40E_INSET_FLEX_PAYLOAD,
9133                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9137                         I40E_INSET_FLEX_PAYLOAD,
9138         };
9139
9140         /**
9141          * Flow director supports only fields defined in
9142          * union rte_eth_fdir_flow.
9143          */
9144         static const uint64_t valid_fdir_inset_table[] = {
9145                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9146                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9148                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9149                 I40E_INSET_IPV4_TTL,
9150                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9151                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9153                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9154                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9155                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9156                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9158                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9159                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9160                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9161                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9162                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9163                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9164                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9165                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9166                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9168                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9169                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9170                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9173                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9174                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9175                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9176                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9177                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9178                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9179                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9180                 I40E_INSET_SCTP_VT,
9181                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9182                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9184                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9185                 I40E_INSET_IPV4_TTL,
9186                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9187                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9188                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9189                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9190                 I40E_INSET_IPV6_HOP_LIMIT,
9191                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9192                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9193                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9194                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9195                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9196                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9197                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9198                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9199                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9200                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9201                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9202                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9203                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9204                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9205                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9206                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9207                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9210                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9211                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9212                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9214                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9215                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9216                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9217                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9219                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9220                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9221                 I40E_INSET_SCTP_VT,
9222                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9223                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9224                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9225                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9226                 I40E_INSET_IPV6_HOP_LIMIT,
9227                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9228                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9229                 I40E_INSET_LAST_ETHER_TYPE,
9230         };
9231
9232         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9233                 return 0;
9234         if (filter == RTE_ETH_FILTER_HASH)
9235                 valid = valid_hash_inset_table[pctype];
9236         else
9237                 valid = valid_fdir_inset_table[pctype];
9238
9239         return valid;
9240 }
9241
9242 /**
9243  * Validate if the input set is allowed for a specific PCTYPE
9244  */
9245 int
9246 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9247                 enum rte_filter_type filter, uint64_t inset)
9248 {
9249         uint64_t valid;
9250
9251         valid = i40e_get_valid_input_set(pctype, filter);
9252         if (inset & (~valid))
9253                 return -EINVAL;
9254
9255         return 0;
9256 }
9257
9258 /* default input set fields combination per pctype */
9259 uint64_t
9260 i40e_get_default_input_set(uint16_t pctype)
9261 {
9262         static const uint64_t default_inset_table[] = {
9263                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9264                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9265                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9266                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9267                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9268                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9269                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9270                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9271                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9272                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9273                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9274                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9275                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9276                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9277                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9278                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9279                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9280                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9281                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9282                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9283                         I40E_INSET_SCTP_VT,
9284                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9285                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9286                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9287                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9288                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9289                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9290                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9291                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9292                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9293                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9294                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9295                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9296                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9297                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9298                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9299                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9300                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9301                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9302                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9303                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9304                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9305                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9306                         I40E_INSET_SCTP_VT,
9307                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9308                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9309                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9310                         I40E_INSET_LAST_ETHER_TYPE,
9311         };
9312
9313         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9314                 return 0;
9315
9316         return default_inset_table[pctype];
9317 }
9318
9319 /**
9320  * Parse the input set from index to logical bit masks
9321  */
9322 static int
9323 i40e_parse_input_set(uint64_t *inset,
9324                      enum i40e_filter_pctype pctype,
9325                      enum rte_eth_input_set_field *field,
9326                      uint16_t size)
9327 {
9328         uint16_t i, j;
9329         int ret = -EINVAL;
9330
9331         static const struct {
9332                 enum rte_eth_input_set_field field;
9333                 uint64_t inset;
9334         } inset_convert_table[] = {
9335                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9336                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9337                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9338                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9339                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9340                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9341                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9342                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9343                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9344                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9345                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9346                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9347                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9348                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9349                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9350                         I40E_INSET_IPV6_NEXT_HDR},
9351                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9352                         I40E_INSET_IPV6_HOP_LIMIT},
9353                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9354                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9355                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9356                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9357                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9358                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9359                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9360                         I40E_INSET_SCTP_VT},
9361                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9362                         I40E_INSET_TUNNEL_DMAC},
9363                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9364                         I40E_INSET_VLAN_TUNNEL},
9365                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9366                         I40E_INSET_TUNNEL_ID},
9367                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9368                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9369                         I40E_INSET_FLEX_PAYLOAD_W1},
9370                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9371                         I40E_INSET_FLEX_PAYLOAD_W2},
9372                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9373                         I40E_INSET_FLEX_PAYLOAD_W3},
9374                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9375                         I40E_INSET_FLEX_PAYLOAD_W4},
9376                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9377                         I40E_INSET_FLEX_PAYLOAD_W5},
9378                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9379                         I40E_INSET_FLEX_PAYLOAD_W6},
9380                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9381                         I40E_INSET_FLEX_PAYLOAD_W7},
9382                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9383                         I40E_INSET_FLEX_PAYLOAD_W8},
9384         };
9385
9386         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9387                 return ret;
9388
9389         /* Only one item allowed for default or all */
9390         if (size == 1) {
9391                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9392                         *inset = i40e_get_default_input_set(pctype);
9393                         return 0;
9394                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9395                         *inset = I40E_INSET_NONE;
9396                         return 0;
9397                 }
9398         }
9399
9400         for (i = 0, *inset = 0; i < size; i++) {
9401                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9402                         if (field[i] == inset_convert_table[j].field) {
9403                                 *inset |= inset_convert_table[j].inset;
9404                                 break;
9405                         }
9406                 }
9407
9408                 /* It contains unsupported input set, return immediately */
9409                 if (j == RTE_DIM(inset_convert_table))
9410                         return ret;
9411         }
9412
9413         return 0;
9414 }
9415
9416 /**
9417  * Translate the input set from bit masks to register aware bit masks
9418  * and vice versa
9419  */
9420 uint64_t
9421 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9422 {
9423         uint64_t val = 0;
9424         uint16_t i;
9425
9426         struct inset_map {
9427                 uint64_t inset;
9428                 uint64_t inset_reg;
9429         };
9430
9431         static const struct inset_map inset_map_common[] = {
9432                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9433                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9434                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9435                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9436                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9437                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9438                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9439                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9440                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9441                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9442                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9443                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9444                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9445                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9446                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9447                 {I40E_INSET_TUNNEL_DMAC,
9448                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9449                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9450                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9451                 {I40E_INSET_TUNNEL_SRC_PORT,
9452                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9453                 {I40E_INSET_TUNNEL_DST_PORT,
9454                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9455                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9456                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9457                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9458                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9459                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9460                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9461                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9462                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9463                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9464         };
9465
9466     /* some different registers map in x722*/
9467         static const struct inset_map inset_map_diff_x722[] = {
9468                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9469                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9470                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9471                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9472         };
9473
9474         static const struct inset_map inset_map_diff_not_x722[] = {
9475                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9476                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9477                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9478                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9479         };
9480
9481         if (input == 0)
9482                 return val;
9483
9484         /* Translate input set to register aware inset */
9485         if (type == I40E_MAC_X722) {
9486                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9487                         if (input & inset_map_diff_x722[i].inset)
9488                                 val |= inset_map_diff_x722[i].inset_reg;
9489                 }
9490         } else {
9491                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9492                         if (input & inset_map_diff_not_x722[i].inset)
9493                                 val |= inset_map_diff_not_x722[i].inset_reg;
9494                 }
9495         }
9496
9497         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9498                 if (input & inset_map_common[i].inset)
9499                         val |= inset_map_common[i].inset_reg;
9500         }
9501
9502         return val;
9503 }
9504
9505 int
9506 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9507 {
9508         uint8_t i, idx = 0;
9509         uint64_t inset_need_mask = inset;
9510
9511         static const struct {
9512                 uint64_t inset;
9513                 uint32_t mask;
9514         } inset_mask_map[] = {
9515                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9516                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9517                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9518                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9519                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9520                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9521                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9522                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9523         };
9524
9525         if (!inset || !mask || !nb_elem)
9526                 return 0;
9527
9528         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9529                 /* Clear the inset bit, if no MASK is required,
9530                  * for example proto + ttl
9531                  */
9532                 if ((inset & inset_mask_map[i].inset) ==
9533                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9534                         inset_need_mask &= ~inset_mask_map[i].inset;
9535                 if (!inset_need_mask)
9536                         return 0;
9537         }
9538         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9539                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9540                     inset_mask_map[i].inset) {
9541                         if (idx >= nb_elem) {
9542                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9543                                 return -EINVAL;
9544                         }
9545                         mask[idx] = inset_mask_map[i].mask;
9546                         idx++;
9547                 }
9548         }
9549
9550         return idx;
9551 }
9552
9553 void
9554 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9555 {
9556         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9557
9558         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9559         if (reg != val)
9560                 i40e_write_rx_ctl(hw, addr, val);
9561         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9562                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9563 }
9564
9565 void
9566 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9567 {
9568         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9569         struct rte_eth_dev *dev;
9570
9571         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9572         if (reg != val) {
9573                 i40e_write_rx_ctl(hw, addr, val);
9574                 PMD_DRV_LOG(WARNING,
9575                             "i40e device %s changed global register [0x%08x]."
9576                             " original: 0x%08x, new: 0x%08x",
9577                             dev->device->name, addr, reg,
9578                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9579         }
9580 }
9581
9582 static void
9583 i40e_filter_input_set_init(struct i40e_pf *pf)
9584 {
9585         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9586         enum i40e_filter_pctype pctype;
9587         uint64_t input_set, inset_reg;
9588         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9589         int num, i;
9590         uint16_t flow_type;
9591
9592         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9593              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9594                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9595
9596                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9597                         continue;
9598
9599                 input_set = i40e_get_default_input_set(pctype);
9600
9601                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9602                                                    I40E_INSET_MASK_NUM_REG);
9603                 if (num < 0)
9604                         return;
9605                 if (pf->support_multi_driver && num > 0) {
9606                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9607                         return;
9608                 }
9609                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9610                                         input_set);
9611
9612                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9613                                       (uint32_t)(inset_reg & UINT32_MAX));
9614                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9615                                      (uint32_t)((inset_reg >>
9616                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9617                 if (!pf->support_multi_driver) {
9618                         i40e_check_write_global_reg(hw,
9619                                             I40E_GLQF_HASH_INSET(0, pctype),
9620                                             (uint32_t)(inset_reg & UINT32_MAX));
9621                         i40e_check_write_global_reg(hw,
9622                                              I40E_GLQF_HASH_INSET(1, pctype),
9623                                              (uint32_t)((inset_reg >>
9624                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9625
9626                         for (i = 0; i < num; i++) {
9627                                 i40e_check_write_global_reg(hw,
9628                                                     I40E_GLQF_FD_MSK(i, pctype),
9629                                                     mask_reg[i]);
9630                                 i40e_check_write_global_reg(hw,
9631                                                   I40E_GLQF_HASH_MSK(i, pctype),
9632                                                   mask_reg[i]);
9633                         }
9634                         /*clear unused mask registers of the pctype */
9635                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9636                                 i40e_check_write_global_reg(hw,
9637                                                     I40E_GLQF_FD_MSK(i, pctype),
9638                                                     0);
9639                                 i40e_check_write_global_reg(hw,
9640                                                   I40E_GLQF_HASH_MSK(i, pctype),
9641                                                   0);
9642                         }
9643                 } else {
9644                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9645                 }
9646                 I40E_WRITE_FLUSH(hw);
9647
9648                 /* store the default input set */
9649                 if (!pf->support_multi_driver)
9650                         pf->hash_input_set[pctype] = input_set;
9651                 pf->fdir.input_set[pctype] = input_set;
9652         }
9653 }
9654
9655 int
9656 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9657                          struct rte_eth_input_set_conf *conf)
9658 {
9659         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9660         enum i40e_filter_pctype pctype;
9661         uint64_t input_set, inset_reg = 0;
9662         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9663         int ret, i, num;
9664
9665         if (!conf) {
9666                 PMD_DRV_LOG(ERR, "Invalid pointer");
9667                 return -EFAULT;
9668         }
9669         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9670             conf->op != RTE_ETH_INPUT_SET_ADD) {
9671                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9672                 return -EINVAL;
9673         }
9674
9675         if (pf->support_multi_driver) {
9676                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9677                 return -ENOTSUP;
9678         }
9679
9680         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9681         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9682                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9683                 return -EINVAL;
9684         }
9685
9686         if (hw->mac.type == I40E_MAC_X722) {
9687                 /* get translated pctype value in fd pctype register */
9688                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9689                         I40E_GLQF_FD_PCTYPES((int)pctype));
9690         }
9691
9692         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9693                                    conf->inset_size);
9694         if (ret) {
9695                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9696                 return -EINVAL;
9697         }
9698
9699         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9700                 /* get inset value in register */
9701                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9702                 inset_reg <<= I40E_32_BIT_WIDTH;
9703                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9704                 input_set |= pf->hash_input_set[pctype];
9705         }
9706         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9707                                            I40E_INSET_MASK_NUM_REG);
9708         if (num < 0)
9709                 return -EINVAL;
9710
9711         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9712
9713         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9714                                     (uint32_t)(inset_reg & UINT32_MAX));
9715         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9716                                     (uint32_t)((inset_reg >>
9717                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9718
9719         for (i = 0; i < num; i++)
9720                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9721                                             mask_reg[i]);
9722         /*clear unused mask registers of the pctype */
9723         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9724                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9725                                             0);
9726         I40E_WRITE_FLUSH(hw);
9727
9728         pf->hash_input_set[pctype] = input_set;
9729         return 0;
9730 }
9731
9732 int
9733 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9734                          struct rte_eth_input_set_conf *conf)
9735 {
9736         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9737         enum i40e_filter_pctype pctype;
9738         uint64_t input_set, inset_reg = 0;
9739         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9740         int ret, i, num;
9741
9742         if (!hw || !conf) {
9743                 PMD_DRV_LOG(ERR, "Invalid pointer");
9744                 return -EFAULT;
9745         }
9746         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9747             conf->op != RTE_ETH_INPUT_SET_ADD) {
9748                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9749                 return -EINVAL;
9750         }
9751
9752         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9753
9754         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9755                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9756                 return -EINVAL;
9757         }
9758
9759         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9760                                    conf->inset_size);
9761         if (ret) {
9762                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9763                 return -EINVAL;
9764         }
9765
9766         /* get inset value in register */
9767         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9768         inset_reg <<= I40E_32_BIT_WIDTH;
9769         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9770
9771         /* Can not change the inset reg for flex payload for fdir,
9772          * it is done by writing I40E_PRTQF_FD_FLXINSET
9773          * in i40e_set_flex_mask_on_pctype.
9774          */
9775         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9776                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9777         else
9778                 input_set |= pf->fdir.input_set[pctype];
9779         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9780                                            I40E_INSET_MASK_NUM_REG);
9781         if (num < 0)
9782                 return -EINVAL;
9783         if (pf->support_multi_driver && num > 0) {
9784                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9785                 return -ENOTSUP;
9786         }
9787
9788         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9789
9790         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9791                               (uint32_t)(inset_reg & UINT32_MAX));
9792         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9793                              (uint32_t)((inset_reg >>
9794                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9795
9796         if (!pf->support_multi_driver) {
9797                 for (i = 0; i < num; i++)
9798                         i40e_check_write_global_reg(hw,
9799                                                     I40E_GLQF_FD_MSK(i, pctype),
9800                                                     mask_reg[i]);
9801                 /*clear unused mask registers of the pctype */
9802                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9803                         i40e_check_write_global_reg(hw,
9804                                                     I40E_GLQF_FD_MSK(i, pctype),
9805                                                     0);
9806         } else {
9807                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9808         }
9809         I40E_WRITE_FLUSH(hw);
9810
9811         pf->fdir.input_set[pctype] = input_set;
9812         return 0;
9813 }
9814
9815 static int
9816 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9817 {
9818         int ret = 0;
9819
9820         if (!hw || !info) {
9821                 PMD_DRV_LOG(ERR, "Invalid pointer");
9822                 return -EFAULT;
9823         }
9824
9825         switch (info->info_type) {
9826         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9827                 i40e_get_symmetric_hash_enable_per_port(hw,
9828                                         &(info->info.enable));
9829                 break;
9830         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9831                 ret = i40e_get_hash_filter_global_config(hw,
9832                                 &(info->info.global_conf));
9833                 break;
9834         default:
9835                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9836                                                         info->info_type);
9837                 ret = -EINVAL;
9838                 break;
9839         }
9840
9841         return ret;
9842 }
9843
9844 static int
9845 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9846 {
9847         int ret = 0;
9848
9849         if (!hw || !info) {
9850                 PMD_DRV_LOG(ERR, "Invalid pointer");
9851                 return -EFAULT;
9852         }
9853
9854         switch (info->info_type) {
9855         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9856                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9857                 break;
9858         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9859                 ret = i40e_set_hash_filter_global_config(hw,
9860                                 &(info->info.global_conf));
9861                 break;
9862         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9863                 ret = i40e_hash_filter_inset_select(hw,
9864                                                &(info->info.input_set_conf));
9865                 break;
9866
9867         default:
9868                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9869                                                         info->info_type);
9870                 ret = -EINVAL;
9871                 break;
9872         }
9873
9874         return ret;
9875 }
9876
9877 /* Operations for hash function */
9878 static int
9879 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9880                       enum rte_filter_op filter_op,
9881                       void *arg)
9882 {
9883         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9884         int ret = 0;
9885
9886         switch (filter_op) {
9887         case RTE_ETH_FILTER_NOP:
9888                 break;
9889         case RTE_ETH_FILTER_GET:
9890                 ret = i40e_hash_filter_get(hw,
9891                         (struct rte_eth_hash_filter_info *)arg);
9892                 break;
9893         case RTE_ETH_FILTER_SET:
9894                 ret = i40e_hash_filter_set(hw,
9895                         (struct rte_eth_hash_filter_info *)arg);
9896                 break;
9897         default:
9898                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9899                                                                 filter_op);
9900                 ret = -ENOTSUP;
9901                 break;
9902         }
9903
9904         return ret;
9905 }
9906
9907 /* Convert ethertype filter structure */
9908 static int
9909 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9910                               struct i40e_ethertype_filter *filter)
9911 {
9912         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9913                 RTE_ETHER_ADDR_LEN);
9914         filter->input.ether_type = input->ether_type;
9915         filter->flags = input->flags;
9916         filter->queue = input->queue;
9917
9918         return 0;
9919 }
9920
9921 /* Check if there exists the ehtertype filter */
9922 struct i40e_ethertype_filter *
9923 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9924                                 const struct i40e_ethertype_filter_input *input)
9925 {
9926         int ret;
9927
9928         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9929         if (ret < 0)
9930                 return NULL;
9931
9932         return ethertype_rule->hash_map[ret];
9933 }
9934
9935 /* Add ethertype filter in SW list */
9936 static int
9937 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9938                                 struct i40e_ethertype_filter *filter)
9939 {
9940         struct i40e_ethertype_rule *rule = &pf->ethertype;
9941         int ret;
9942
9943         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9944         if (ret < 0) {
9945                 PMD_DRV_LOG(ERR,
9946                             "Failed to insert ethertype filter"
9947                             " to hash table %d!",
9948                             ret);
9949                 return ret;
9950         }
9951         rule->hash_map[ret] = filter;
9952
9953         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9954
9955         return 0;
9956 }
9957
9958 /* Delete ethertype filter in SW list */
9959 int
9960 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9961                              struct i40e_ethertype_filter_input *input)
9962 {
9963         struct i40e_ethertype_rule *rule = &pf->ethertype;
9964         struct i40e_ethertype_filter *filter;
9965         int ret;
9966
9967         ret = rte_hash_del_key(rule->hash_table, input);
9968         if (ret < 0) {
9969                 PMD_DRV_LOG(ERR,
9970                             "Failed to delete ethertype filter"
9971                             " to hash table %d!",
9972                             ret);
9973                 return ret;
9974         }
9975         filter = rule->hash_map[ret];
9976         rule->hash_map[ret] = NULL;
9977
9978         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9979         rte_free(filter);
9980
9981         return 0;
9982 }
9983
9984 /*
9985  * Configure ethertype filter, which can director packet by filtering
9986  * with mac address and ether_type or only ether_type
9987  */
9988 int
9989 i40e_ethertype_filter_set(struct i40e_pf *pf,
9990                         struct rte_eth_ethertype_filter *filter,
9991                         bool add)
9992 {
9993         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9994         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9995         struct i40e_ethertype_filter *ethertype_filter, *node;
9996         struct i40e_ethertype_filter check_filter;
9997         struct i40e_control_filter_stats stats;
9998         uint16_t flags = 0;
9999         int ret;
10000
10001         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10002                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10003                 return -EINVAL;
10004         }
10005         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10006                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10007                 PMD_DRV_LOG(ERR,
10008                         "unsupported ether_type(0x%04x) in control packet filter.",
10009                         filter->ether_type);
10010                 return -EINVAL;
10011         }
10012         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10013                 PMD_DRV_LOG(WARNING,
10014                         "filter vlan ether_type in first tag is not supported.");
10015
10016         /* Check if there is the filter in SW list */
10017         memset(&check_filter, 0, sizeof(check_filter));
10018         i40e_ethertype_filter_convert(filter, &check_filter);
10019         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10020                                                &check_filter.input);
10021         if (add && node) {
10022                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10023                 return -EINVAL;
10024         }
10025
10026         if (!add && !node) {
10027                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10028                 return -EINVAL;
10029         }
10030
10031         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10032                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10033         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10034                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10035         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10036
10037         memset(&stats, 0, sizeof(stats));
10038         ret = i40e_aq_add_rem_control_packet_filter(hw,
10039                         filter->mac_addr.addr_bytes,
10040                         filter->ether_type, flags,
10041                         pf->main_vsi->seid,
10042                         filter->queue, add, &stats, NULL);
10043
10044         PMD_DRV_LOG(INFO,
10045                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10046                 ret, stats.mac_etype_used, stats.etype_used,
10047                 stats.mac_etype_free, stats.etype_free);
10048         if (ret < 0)
10049                 return -ENOSYS;
10050
10051         /* Add or delete a filter in SW list */
10052         if (add) {
10053                 ethertype_filter = rte_zmalloc("ethertype_filter",
10054                                        sizeof(*ethertype_filter), 0);
10055                 if (ethertype_filter == NULL) {
10056                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10057                         return -ENOMEM;
10058                 }
10059
10060                 rte_memcpy(ethertype_filter, &check_filter,
10061                            sizeof(check_filter));
10062                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10063                 if (ret < 0)
10064                         rte_free(ethertype_filter);
10065         } else {
10066                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10067         }
10068
10069         return ret;
10070 }
10071
10072 /*
10073  * Handle operations for ethertype filter.
10074  */
10075 static int
10076 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10077                                 enum rte_filter_op filter_op,
10078                                 void *arg)
10079 {
10080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10081         int ret = 0;
10082
10083         if (filter_op == RTE_ETH_FILTER_NOP)
10084                 return ret;
10085
10086         if (arg == NULL) {
10087                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10088                             filter_op);
10089                 return -EINVAL;
10090         }
10091
10092         switch (filter_op) {
10093         case RTE_ETH_FILTER_ADD:
10094                 ret = i40e_ethertype_filter_set(pf,
10095                         (struct rte_eth_ethertype_filter *)arg,
10096                         TRUE);
10097                 break;
10098         case RTE_ETH_FILTER_DELETE:
10099                 ret = i40e_ethertype_filter_set(pf,
10100                         (struct rte_eth_ethertype_filter *)arg,
10101                         FALSE);
10102                 break;
10103         default:
10104                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10105                 ret = -ENOSYS;
10106                 break;
10107         }
10108         return ret;
10109 }
10110
10111 static int
10112 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10113                      enum rte_filter_type filter_type,
10114                      enum rte_filter_op filter_op,
10115                      void *arg)
10116 {
10117         int ret = 0;
10118
10119         if (dev == NULL)
10120                 return -EINVAL;
10121
10122         switch (filter_type) {
10123         case RTE_ETH_FILTER_NONE:
10124                 /* For global configuration */
10125                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10126                 break;
10127         case RTE_ETH_FILTER_HASH:
10128                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10129                 break;
10130         case RTE_ETH_FILTER_MACVLAN:
10131                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10132                 break;
10133         case RTE_ETH_FILTER_ETHERTYPE:
10134                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10135                 break;
10136         case RTE_ETH_FILTER_TUNNEL:
10137                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10138                 break;
10139         case RTE_ETH_FILTER_FDIR:
10140                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10141                 break;
10142         case RTE_ETH_FILTER_GENERIC:
10143                 if (filter_op != RTE_ETH_FILTER_GET)
10144                         return -EINVAL;
10145                 *(const void **)arg = &i40e_flow_ops;
10146                 break;
10147         default:
10148                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10149                                                         filter_type);
10150                 ret = -EINVAL;
10151                 break;
10152         }
10153
10154         return ret;
10155 }
10156
10157 /*
10158  * Check and enable Extended Tag.
10159  * Enabling Extended Tag is important for 40G performance.
10160  */
10161 static void
10162 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10163 {
10164         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10165         uint32_t buf = 0;
10166         int ret;
10167
10168         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10169                                       PCI_DEV_CAP_REG);
10170         if (ret < 0) {
10171                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10172                             PCI_DEV_CAP_REG);
10173                 return;
10174         }
10175         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10176                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10177                 return;
10178         }
10179
10180         buf = 0;
10181         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10182                                       PCI_DEV_CTRL_REG);
10183         if (ret < 0) {
10184                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10185                             PCI_DEV_CTRL_REG);
10186                 return;
10187         }
10188         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10189                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10190                 return;
10191         }
10192         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10193         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10194                                        PCI_DEV_CTRL_REG);
10195         if (ret < 0) {
10196                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10197                             PCI_DEV_CTRL_REG);
10198                 return;
10199         }
10200 }
10201
10202 /*
10203  * As some registers wouldn't be reset unless a global hardware reset,
10204  * hardware initialization is needed to put those registers into an
10205  * expected initial state.
10206  */
10207 static void
10208 i40e_hw_init(struct rte_eth_dev *dev)
10209 {
10210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10211
10212         i40e_enable_extended_tag(dev);
10213
10214         /* clear the PF Queue Filter control register */
10215         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10216
10217         /* Disable symmetric hash per port */
10218         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10219 }
10220
10221 /*
10222  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10223  * however this function will return only one highest pctype index,
10224  * which is not quite correct. This is known problem of i40e driver
10225  * and needs to be fixed later.
10226  */
10227 enum i40e_filter_pctype
10228 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10229 {
10230         int i;
10231         uint64_t pctype_mask;
10232
10233         if (flow_type < I40E_FLOW_TYPE_MAX) {
10234                 pctype_mask = adapter->pctypes_tbl[flow_type];
10235                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10236                         if (pctype_mask & (1ULL << i))
10237                                 return (enum i40e_filter_pctype)i;
10238                 }
10239         }
10240         return I40E_FILTER_PCTYPE_INVALID;
10241 }
10242
10243 uint16_t
10244 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10245                         enum i40e_filter_pctype pctype)
10246 {
10247         uint16_t flowtype;
10248         uint64_t pctype_mask = 1ULL << pctype;
10249
10250         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10251              flowtype++) {
10252                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10253                         return flowtype;
10254         }
10255
10256         return RTE_ETH_FLOW_UNKNOWN;
10257 }
10258
10259 /*
10260  * On X710, performance number is far from the expectation on recent firmware
10261  * versions; on XL710, performance number is also far from the expectation on
10262  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10263  * mode is enabled and port MAC address is equal to the packet destination MAC
10264  * address. The fix for this issue may not be integrated in the following
10265  * firmware version. So the workaround in software driver is needed. It needs
10266  * to modify the initial values of 3 internal only registers for both X710 and
10267  * XL710. Note that the values for X710 or XL710 could be different, and the
10268  * workaround can be removed when it is fixed in firmware in the future.
10269  */
10270
10271 /* For both X710 and XL710 */
10272 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10273 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10274 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10275
10276 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10277 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10278
10279 /* For X722 */
10280 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10281 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10282
10283 /* For X710 */
10284 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10285 /* For XL710 */
10286 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10287 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10288
10289 /*
10290  * GL_SWR_PM_UP_THR:
10291  * The value is not impacted from the link speed, its value is set according
10292  * to the total number of ports for a better pipe-monitor configuration.
10293  */
10294 static bool
10295 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10296 {
10297 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10298                 .device_id = (dev),   \
10299                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10300
10301 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10302                 .device_id = (dev),   \
10303                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10304
10305         static const struct {
10306                 uint16_t device_id;
10307                 uint32_t val;
10308         } swr_pm_table[] = {
10309                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10310                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10311                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10312                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10313
10314                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10315                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10316                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10317                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10318                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10319                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10320                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10321         };
10322         uint32_t i;
10323
10324         if (value == NULL) {
10325                 PMD_DRV_LOG(ERR, "value is NULL");
10326                 return false;
10327         }
10328
10329         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10330                 if (hw->device_id == swr_pm_table[i].device_id) {
10331                         *value = swr_pm_table[i].val;
10332
10333                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10334                                     "value - 0x%08x",
10335                                     hw->device_id, *value);
10336                         return true;
10337                 }
10338         }
10339
10340         return false;
10341 }
10342
10343 static int
10344 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10345 {
10346         enum i40e_status_code status;
10347         struct i40e_aq_get_phy_abilities_resp phy_ab;
10348         int ret = -ENOTSUP;
10349         int retries = 0;
10350
10351         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10352                                               NULL);
10353
10354         while (status) {
10355                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10356                         status);
10357                 retries++;
10358                 rte_delay_us(100000);
10359                 if  (retries < 5)
10360                         status = i40e_aq_get_phy_capabilities(hw, false,
10361                                         true, &phy_ab, NULL);
10362                 else
10363                         return ret;
10364         }
10365         return 0;
10366 }
10367
10368 static void
10369 i40e_configure_registers(struct i40e_hw *hw)
10370 {
10371         static struct {
10372                 uint32_t addr;
10373                 uint64_t val;
10374         } reg_table[] = {
10375                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10376                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10377                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10378         };
10379         uint64_t reg;
10380         uint32_t i;
10381         int ret;
10382
10383         for (i = 0; i < RTE_DIM(reg_table); i++) {
10384                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10385                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10386                                 reg_table[i].val =
10387                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10388                         else /* For X710/XL710/XXV710 */
10389                                 if (hw->aq.fw_maj_ver < 6)
10390                                         reg_table[i].val =
10391                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10392                                 else
10393                                         reg_table[i].val =
10394                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10395                 }
10396
10397                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10398                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10399                                 reg_table[i].val =
10400                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10401                         else /* For X710/XL710/XXV710 */
10402                                 reg_table[i].val =
10403                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10404                 }
10405
10406                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10407                         uint32_t cfg_val;
10408
10409                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10410                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10411                                             "GL_SWR_PM_UP_THR value fixup",
10412                                             hw->device_id);
10413                                 continue;
10414                         }
10415
10416                         reg_table[i].val = cfg_val;
10417                 }
10418
10419                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10420                                                         &reg, NULL);
10421                 if (ret < 0) {
10422                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10423                                                         reg_table[i].addr);
10424                         break;
10425                 }
10426                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10427                                                 reg_table[i].addr, reg);
10428                 if (reg == reg_table[i].val)
10429                         continue;
10430
10431                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10432                                                 reg_table[i].val, NULL);
10433                 if (ret < 0) {
10434                         PMD_DRV_LOG(ERR,
10435                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10436                                 reg_table[i].val, reg_table[i].addr);
10437                         break;
10438                 }
10439                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10440                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10441         }
10442 }
10443
10444 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10445 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10446 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10447 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10448 static int
10449 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10450 {
10451         uint32_t reg;
10452         int ret;
10453
10454         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10455                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10456                 return -EINVAL;
10457         }
10458
10459         /* Configure for double VLAN RX stripping */
10460         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10461         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10462                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10463                 ret = i40e_aq_debug_write_register(hw,
10464                                                    I40E_VSI_TSR(vsi->vsi_id),
10465                                                    reg, NULL);
10466                 if (ret < 0) {
10467                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10468                                     vsi->vsi_id);
10469                         return I40E_ERR_CONFIG;
10470                 }
10471         }
10472
10473         /* Configure for double VLAN TX insertion */
10474         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10475         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10476                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10477                 ret = i40e_aq_debug_write_register(hw,
10478                                                    I40E_VSI_L2TAGSTXVALID(
10479                                                    vsi->vsi_id), reg, NULL);
10480                 if (ret < 0) {
10481                         PMD_DRV_LOG(ERR,
10482                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10483                                 vsi->vsi_id);
10484                         return I40E_ERR_CONFIG;
10485                 }
10486         }
10487
10488         return 0;
10489 }
10490
10491 /**
10492  * i40e_aq_add_mirror_rule
10493  * @hw: pointer to the hardware structure
10494  * @seid: VEB seid to add mirror rule to
10495  * @dst_id: destination vsi seid
10496  * @entries: Buffer which contains the entities to be mirrored
10497  * @count: number of entities contained in the buffer
10498  * @rule_id:the rule_id of the rule to be added
10499  *
10500  * Add a mirror rule for a given veb.
10501  *
10502  **/
10503 static enum i40e_status_code
10504 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10505                         uint16_t seid, uint16_t dst_id,
10506                         uint16_t rule_type, uint16_t *entries,
10507                         uint16_t count, uint16_t *rule_id)
10508 {
10509         struct i40e_aq_desc desc;
10510         struct i40e_aqc_add_delete_mirror_rule cmd;
10511         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10512                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10513                 &desc.params.raw;
10514         uint16_t buff_len;
10515         enum i40e_status_code status;
10516
10517         i40e_fill_default_direct_cmd_desc(&desc,
10518                                           i40e_aqc_opc_add_mirror_rule);
10519         memset(&cmd, 0, sizeof(cmd));
10520
10521         buff_len = sizeof(uint16_t) * count;
10522         desc.datalen = rte_cpu_to_le_16(buff_len);
10523         if (buff_len > 0)
10524                 desc.flags |= rte_cpu_to_le_16(
10525                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10526         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10527                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10528         cmd.num_entries = rte_cpu_to_le_16(count);
10529         cmd.seid = rte_cpu_to_le_16(seid);
10530         cmd.destination = rte_cpu_to_le_16(dst_id);
10531
10532         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10533         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10534         PMD_DRV_LOG(INFO,
10535                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10536                 hw->aq.asq_last_status, resp->rule_id,
10537                 resp->mirror_rules_used, resp->mirror_rules_free);
10538         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10539
10540         return status;
10541 }
10542
10543 /**
10544  * i40e_aq_del_mirror_rule
10545  * @hw: pointer to the hardware structure
10546  * @seid: VEB seid to add mirror rule to
10547  * @entries: Buffer which contains the entities to be mirrored
10548  * @count: number of entities contained in the buffer
10549  * @rule_id:the rule_id of the rule to be delete
10550  *
10551  * Delete a mirror rule for a given veb.
10552  *
10553  **/
10554 static enum i40e_status_code
10555 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10556                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10557                 uint16_t count, uint16_t rule_id)
10558 {
10559         struct i40e_aq_desc desc;
10560         struct i40e_aqc_add_delete_mirror_rule cmd;
10561         uint16_t buff_len = 0;
10562         enum i40e_status_code status;
10563         void *buff = NULL;
10564
10565         i40e_fill_default_direct_cmd_desc(&desc,
10566                                           i40e_aqc_opc_delete_mirror_rule);
10567         memset(&cmd, 0, sizeof(cmd));
10568         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10569                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10570                                                           I40E_AQ_FLAG_RD));
10571                 cmd.num_entries = count;
10572                 buff_len = sizeof(uint16_t) * count;
10573                 desc.datalen = rte_cpu_to_le_16(buff_len);
10574                 buff = (void *)entries;
10575         } else
10576                 /* rule id is filled in destination field for deleting mirror rule */
10577                 cmd.destination = rte_cpu_to_le_16(rule_id);
10578
10579         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10580                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10581         cmd.seid = rte_cpu_to_le_16(seid);
10582
10583         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10584         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10585
10586         return status;
10587 }
10588
10589 /**
10590  * i40e_mirror_rule_set
10591  * @dev: pointer to the hardware structure
10592  * @mirror_conf: mirror rule info
10593  * @sw_id: mirror rule's sw_id
10594  * @on: enable/disable
10595  *
10596  * set a mirror rule.
10597  *
10598  **/
10599 static int
10600 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10601                         struct rte_eth_mirror_conf *mirror_conf,
10602                         uint8_t sw_id, uint8_t on)
10603 {
10604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10605         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10606         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10607         struct i40e_mirror_rule *parent = NULL;
10608         uint16_t seid, dst_seid, rule_id;
10609         uint16_t i, j = 0;
10610         int ret;
10611
10612         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10613
10614         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10615                 PMD_DRV_LOG(ERR,
10616                         "mirror rule can not be configured without veb or vfs.");
10617                 return -ENOSYS;
10618         }
10619         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10620                 PMD_DRV_LOG(ERR, "mirror table is full.");
10621                 return -ENOSPC;
10622         }
10623         if (mirror_conf->dst_pool > pf->vf_num) {
10624                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10625                                  mirror_conf->dst_pool);
10626                 return -EINVAL;
10627         }
10628
10629         seid = pf->main_vsi->veb->seid;
10630
10631         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10632                 if (sw_id <= it->index) {
10633                         mirr_rule = it;
10634                         break;
10635                 }
10636                 parent = it;
10637         }
10638         if (mirr_rule && sw_id == mirr_rule->index) {
10639                 if (on) {
10640                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10641                         return -EEXIST;
10642                 } else {
10643                         ret = i40e_aq_del_mirror_rule(hw, seid,
10644                                         mirr_rule->rule_type,
10645                                         mirr_rule->entries,
10646                                         mirr_rule->num_entries, mirr_rule->id);
10647                         if (ret < 0) {
10648                                 PMD_DRV_LOG(ERR,
10649                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10650                                         ret, hw->aq.asq_last_status);
10651                                 return -ENOSYS;
10652                         }
10653                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10654                         rte_free(mirr_rule);
10655                         pf->nb_mirror_rule--;
10656                         return 0;
10657                 }
10658         } else if (!on) {
10659                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10660                 return -ENOENT;
10661         }
10662
10663         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10664                                 sizeof(struct i40e_mirror_rule) , 0);
10665         if (!mirr_rule) {
10666                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10667                 return I40E_ERR_NO_MEMORY;
10668         }
10669         switch (mirror_conf->rule_type) {
10670         case ETH_MIRROR_VLAN:
10671                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10672                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10673                                 mirr_rule->entries[j] =
10674                                         mirror_conf->vlan.vlan_id[i];
10675                                 j++;
10676                         }
10677                 }
10678                 if (j == 0) {
10679                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10680                         rte_free(mirr_rule);
10681                         return -EINVAL;
10682                 }
10683                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10684                 break;
10685         case ETH_MIRROR_VIRTUAL_POOL_UP:
10686         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10687                 /* check if the specified pool bit is out of range */
10688                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10689                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10690                         rte_free(mirr_rule);
10691                         return -EINVAL;
10692                 }
10693                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10694                         if (mirror_conf->pool_mask & (1ULL << i)) {
10695                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10696                                 j++;
10697                         }
10698                 }
10699                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10700                         /* add pf vsi to entries */
10701                         mirr_rule->entries[j] = pf->main_vsi_seid;
10702                         j++;
10703                 }
10704                 if (j == 0) {
10705                         PMD_DRV_LOG(ERR, "pool is not specified.");
10706                         rte_free(mirr_rule);
10707                         return -EINVAL;
10708                 }
10709                 /* egress and ingress in aq commands means from switch but not port */
10710                 mirr_rule->rule_type =
10711                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10712                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10713                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10714                 break;
10715         case ETH_MIRROR_UPLINK_PORT:
10716                 /* egress and ingress in aq commands means from switch but not port*/
10717                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10718                 break;
10719         case ETH_MIRROR_DOWNLINK_PORT:
10720                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10721                 break;
10722         default:
10723                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10724                         mirror_conf->rule_type);
10725                 rte_free(mirr_rule);
10726                 return -EINVAL;
10727         }
10728
10729         /* If the dst_pool is equal to vf_num, consider it as PF */
10730         if (mirror_conf->dst_pool == pf->vf_num)
10731                 dst_seid = pf->main_vsi_seid;
10732         else
10733                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10734
10735         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10736                                       mirr_rule->rule_type, mirr_rule->entries,
10737                                       j, &rule_id);
10738         if (ret < 0) {
10739                 PMD_DRV_LOG(ERR,
10740                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10741                         ret, hw->aq.asq_last_status);
10742                 rte_free(mirr_rule);
10743                 return -ENOSYS;
10744         }
10745
10746         mirr_rule->index = sw_id;
10747         mirr_rule->num_entries = j;
10748         mirr_rule->id = rule_id;
10749         mirr_rule->dst_vsi_seid = dst_seid;
10750
10751         if (parent)
10752                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10753         else
10754                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10755
10756         pf->nb_mirror_rule++;
10757         return 0;
10758 }
10759
10760 /**
10761  * i40e_mirror_rule_reset
10762  * @dev: pointer to the device
10763  * @sw_id: mirror rule's sw_id
10764  *
10765  * reset a mirror rule.
10766  *
10767  **/
10768 static int
10769 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10770 {
10771         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10773         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10774         uint16_t seid;
10775         int ret;
10776
10777         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10778
10779         seid = pf->main_vsi->veb->seid;
10780
10781         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10782                 if (sw_id == it->index) {
10783                         mirr_rule = it;
10784                         break;
10785                 }
10786         }
10787         if (mirr_rule) {
10788                 ret = i40e_aq_del_mirror_rule(hw, seid,
10789                                 mirr_rule->rule_type,
10790                                 mirr_rule->entries,
10791                                 mirr_rule->num_entries, mirr_rule->id);
10792                 if (ret < 0) {
10793                         PMD_DRV_LOG(ERR,
10794                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10795                                 ret, hw->aq.asq_last_status);
10796                         return -ENOSYS;
10797                 }
10798                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10799                 rte_free(mirr_rule);
10800                 pf->nb_mirror_rule--;
10801         } else {
10802                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10803                 return -ENOENT;
10804         }
10805         return 0;
10806 }
10807
10808 static uint64_t
10809 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10810 {
10811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10812         uint64_t systim_cycles;
10813
10814         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10815         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10816                         << 32;
10817
10818         return systim_cycles;
10819 }
10820
10821 static uint64_t
10822 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10823 {
10824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10825         uint64_t rx_tstamp;
10826
10827         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10828         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10829                         << 32;
10830
10831         return rx_tstamp;
10832 }
10833
10834 static uint64_t
10835 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10836 {
10837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10838         uint64_t tx_tstamp;
10839
10840         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10841         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10842                         << 32;
10843
10844         return tx_tstamp;
10845 }
10846
10847 static void
10848 i40e_start_timecounters(struct rte_eth_dev *dev)
10849 {
10850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10851         struct i40e_adapter *adapter = dev->data->dev_private;
10852         struct rte_eth_link link;
10853         uint32_t tsync_inc_l;
10854         uint32_t tsync_inc_h;
10855
10856         /* Get current link speed. */
10857         i40e_dev_link_update(dev, 1);
10858         rte_eth_linkstatus_get(dev, &link);
10859
10860         switch (link.link_speed) {
10861         case ETH_SPEED_NUM_40G:
10862         case ETH_SPEED_NUM_25G:
10863                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10864                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10865                 break;
10866         case ETH_SPEED_NUM_10G:
10867                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10868                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10869                 break;
10870         case ETH_SPEED_NUM_1G:
10871                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10872                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10873                 break;
10874         default:
10875                 tsync_inc_l = 0x0;
10876                 tsync_inc_h = 0x0;
10877         }
10878
10879         /* Set the timesync increment value. */
10880         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10881         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10882
10883         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10884         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10885         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10886
10887         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10888         adapter->systime_tc.cc_shift = 0;
10889         adapter->systime_tc.nsec_mask = 0;
10890
10891         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10892         adapter->rx_tstamp_tc.cc_shift = 0;
10893         adapter->rx_tstamp_tc.nsec_mask = 0;
10894
10895         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10896         adapter->tx_tstamp_tc.cc_shift = 0;
10897         adapter->tx_tstamp_tc.nsec_mask = 0;
10898 }
10899
10900 static int
10901 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10902 {
10903         struct i40e_adapter *adapter = dev->data->dev_private;
10904
10905         adapter->systime_tc.nsec += delta;
10906         adapter->rx_tstamp_tc.nsec += delta;
10907         adapter->tx_tstamp_tc.nsec += delta;
10908
10909         return 0;
10910 }
10911
10912 static int
10913 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10914 {
10915         uint64_t ns;
10916         struct i40e_adapter *adapter = dev->data->dev_private;
10917
10918         ns = rte_timespec_to_ns(ts);
10919
10920         /* Set the timecounters to a new value. */
10921         adapter->systime_tc.nsec = ns;
10922         adapter->rx_tstamp_tc.nsec = ns;
10923         adapter->tx_tstamp_tc.nsec = ns;
10924
10925         return 0;
10926 }
10927
10928 static int
10929 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10930 {
10931         uint64_t ns, systime_cycles;
10932         struct i40e_adapter *adapter = dev->data->dev_private;
10933
10934         systime_cycles = i40e_read_systime_cyclecounter(dev);
10935         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10936         *ts = rte_ns_to_timespec(ns);
10937
10938         return 0;
10939 }
10940
10941 static int
10942 i40e_timesync_enable(struct rte_eth_dev *dev)
10943 {
10944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10945         uint32_t tsync_ctl_l;
10946         uint32_t tsync_ctl_h;
10947
10948         /* Stop the timesync system time. */
10949         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10950         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10951         /* Reset the timesync system time value. */
10952         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10953         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10954
10955         i40e_start_timecounters(dev);
10956
10957         /* Clear timesync registers. */
10958         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10959         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10960         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10961         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10962         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10963         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10964
10965         /* Enable timestamping of PTP packets. */
10966         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10967         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10968
10969         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10970         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10971         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10972
10973         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10974         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10975
10976         return 0;
10977 }
10978
10979 static int
10980 i40e_timesync_disable(struct rte_eth_dev *dev)
10981 {
10982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10983         uint32_t tsync_ctl_l;
10984         uint32_t tsync_ctl_h;
10985
10986         /* Disable timestamping of transmitted PTP packets. */
10987         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10988         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10989
10990         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10991         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10992
10993         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10994         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10995
10996         /* Reset the timesync increment value. */
10997         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10998         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10999
11000         return 0;
11001 }
11002
11003 static int
11004 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11005                                 struct timespec *timestamp, uint32_t flags)
11006 {
11007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11008         struct i40e_adapter *adapter = dev->data->dev_private;
11009         uint32_t sync_status;
11010         uint32_t index = flags & 0x03;
11011         uint64_t rx_tstamp_cycles;
11012         uint64_t ns;
11013
11014         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11015         if ((sync_status & (1 << index)) == 0)
11016                 return -EINVAL;
11017
11018         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11019         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11020         *timestamp = rte_ns_to_timespec(ns);
11021
11022         return 0;
11023 }
11024
11025 static int
11026 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11027                                 struct timespec *timestamp)
11028 {
11029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11030         struct i40e_adapter *adapter = dev->data->dev_private;
11031         uint32_t sync_status;
11032         uint64_t tx_tstamp_cycles;
11033         uint64_t ns;
11034
11035         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11036         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11037                 return -EINVAL;
11038
11039         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11040         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11041         *timestamp = rte_ns_to_timespec(ns);
11042
11043         return 0;
11044 }
11045
11046 /*
11047  * i40e_parse_dcb_configure - parse dcb configure from user
11048  * @dev: the device being configured
11049  * @dcb_cfg: pointer of the result of parse
11050  * @*tc_map: bit map of enabled traffic classes
11051  *
11052  * Returns 0 on success, negative value on failure
11053  */
11054 static int
11055 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11056                          struct i40e_dcbx_config *dcb_cfg,
11057                          uint8_t *tc_map)
11058 {
11059         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11060         uint8_t i, tc_bw, bw_lf;
11061
11062         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11063
11064         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11065         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11066                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11067                 return -EINVAL;
11068         }
11069
11070         /* assume each tc has the same bw */
11071         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11072         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11073                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11074         /* to ensure the sum of tcbw is equal to 100 */
11075         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11076         for (i = 0; i < bw_lf; i++)
11077                 dcb_cfg->etscfg.tcbwtable[i]++;
11078
11079         /* assume each tc has the same Transmission Selection Algorithm */
11080         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11081                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11082
11083         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11084                 dcb_cfg->etscfg.prioritytable[i] =
11085                                 dcb_rx_conf->dcb_tc[i];
11086
11087         /* FW needs one App to configure HW */
11088         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11089         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11090         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11091         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11092
11093         if (dcb_rx_conf->nb_tcs == 0)
11094                 *tc_map = 1; /* tc0 only */
11095         else
11096                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11097
11098         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11099                 dcb_cfg->pfc.willing = 0;
11100                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11101                 dcb_cfg->pfc.pfcenable = *tc_map;
11102         }
11103         return 0;
11104 }
11105
11106
11107 static enum i40e_status_code
11108 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11109                               struct i40e_aqc_vsi_properties_data *info,
11110                               uint8_t enabled_tcmap)
11111 {
11112         enum i40e_status_code ret;
11113         int i, total_tc = 0;
11114         uint16_t qpnum_per_tc, bsf, qp_idx;
11115         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11116         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11117         uint16_t used_queues;
11118
11119         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11120         if (ret != I40E_SUCCESS)
11121                 return ret;
11122
11123         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11124                 if (enabled_tcmap & (1 << i))
11125                         total_tc++;
11126         }
11127         if (total_tc == 0)
11128                 total_tc = 1;
11129         vsi->enabled_tc = enabled_tcmap;
11130
11131         /* different VSI has different queues assigned */
11132         if (vsi->type == I40E_VSI_MAIN)
11133                 used_queues = dev_data->nb_rx_queues -
11134                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11135         else if (vsi->type == I40E_VSI_VMDQ2)
11136                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11137         else {
11138                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11139                 return I40E_ERR_NO_AVAILABLE_VSI;
11140         }
11141
11142         qpnum_per_tc = used_queues / total_tc;
11143         /* Number of queues per enabled TC */
11144         if (qpnum_per_tc == 0) {
11145                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11146                 return I40E_ERR_INVALID_QP_ID;
11147         }
11148         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11149                                 I40E_MAX_Q_PER_TC);
11150         bsf = rte_bsf32(qpnum_per_tc);
11151
11152         /**
11153          * Configure TC and queue mapping parameters, for enabled TC,
11154          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11155          * default queue will serve it.
11156          */
11157         qp_idx = 0;
11158         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11159                 if (vsi->enabled_tc & (1 << i)) {
11160                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11161                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11162                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11163                         qp_idx += qpnum_per_tc;
11164                 } else
11165                         info->tc_mapping[i] = 0;
11166         }
11167
11168         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11169         if (vsi->type == I40E_VSI_SRIOV) {
11170                 info->mapping_flags |=
11171                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11172                 for (i = 0; i < vsi->nb_qps; i++)
11173                         info->queue_mapping[i] =
11174                                 rte_cpu_to_le_16(vsi->base_queue + i);
11175         } else {
11176                 info->mapping_flags |=
11177                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11178                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11179         }
11180         info->valid_sections |=
11181                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11182
11183         return I40E_SUCCESS;
11184 }
11185
11186 /*
11187  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11188  * @veb: VEB to be configured
11189  * @tc_map: enabled TC bitmap
11190  *
11191  * Returns 0 on success, negative value on failure
11192  */
11193 static enum i40e_status_code
11194 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11195 {
11196         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11197         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11198         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11199         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11200         enum i40e_status_code ret = I40E_SUCCESS;
11201         int i;
11202         uint32_t bw_max;
11203
11204         /* Check if enabled_tc is same as existing or new TCs */
11205         if (veb->enabled_tc == tc_map)
11206                 return ret;
11207
11208         /* configure tc bandwidth */
11209         memset(&veb_bw, 0, sizeof(veb_bw));
11210         veb_bw.tc_valid_bits = tc_map;
11211         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11212         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11213                 if (tc_map & BIT_ULL(i))
11214                         veb_bw.tc_bw_share_credits[i] = 1;
11215         }
11216         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11217                                                    &veb_bw, NULL);
11218         if (ret) {
11219                 PMD_INIT_LOG(ERR,
11220                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11221                         hw->aq.asq_last_status);
11222                 return ret;
11223         }
11224
11225         memset(&ets_query, 0, sizeof(ets_query));
11226         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11227                                                    &ets_query, NULL);
11228         if (ret != I40E_SUCCESS) {
11229                 PMD_DRV_LOG(ERR,
11230                         "Failed to get switch_comp ETS configuration %u",
11231                         hw->aq.asq_last_status);
11232                 return ret;
11233         }
11234         memset(&bw_query, 0, sizeof(bw_query));
11235         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11236                                                   &bw_query, NULL);
11237         if (ret != I40E_SUCCESS) {
11238                 PMD_DRV_LOG(ERR,
11239                         "Failed to get switch_comp bandwidth configuration %u",
11240                         hw->aq.asq_last_status);
11241                 return ret;
11242         }
11243
11244         /* store and print out BW info */
11245         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11246         veb->bw_info.bw_max = ets_query.tc_bw_max;
11247         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11248         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11249         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11250                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11251                      I40E_16_BIT_WIDTH);
11252         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11253                 veb->bw_info.bw_ets_share_credits[i] =
11254                                 bw_query.tc_bw_share_credits[i];
11255                 veb->bw_info.bw_ets_credits[i] =
11256                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11257                 /* 4 bits per TC, 4th bit is reserved */
11258                 veb->bw_info.bw_ets_max[i] =
11259                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11260                                   RTE_LEN2MASK(3, uint8_t));
11261                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11262                             veb->bw_info.bw_ets_share_credits[i]);
11263                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11264                             veb->bw_info.bw_ets_credits[i]);
11265                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11266                             veb->bw_info.bw_ets_max[i]);
11267         }
11268
11269         veb->enabled_tc = tc_map;
11270
11271         return ret;
11272 }
11273
11274
11275 /*
11276  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11277  * @vsi: VSI to be configured
11278  * @tc_map: enabled TC bitmap
11279  *
11280  * Returns 0 on success, negative value on failure
11281  */
11282 static enum i40e_status_code
11283 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11284 {
11285         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11286         struct i40e_vsi_context ctxt;
11287         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11288         enum i40e_status_code ret = I40E_SUCCESS;
11289         int i;
11290
11291         /* Check if enabled_tc is same as existing or new TCs */
11292         if (vsi->enabled_tc == tc_map)
11293                 return ret;
11294
11295         /* configure tc bandwidth */
11296         memset(&bw_data, 0, sizeof(bw_data));
11297         bw_data.tc_valid_bits = tc_map;
11298         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11299         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11300                 if (tc_map & BIT_ULL(i))
11301                         bw_data.tc_bw_credits[i] = 1;
11302         }
11303         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11304         if (ret) {
11305                 PMD_INIT_LOG(ERR,
11306                         "AQ command Config VSI BW allocation per TC failed = %d",
11307                         hw->aq.asq_last_status);
11308                 goto out;
11309         }
11310         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11311                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11312
11313         /* Update Queue Pairs Mapping for currently enabled UPs */
11314         ctxt.seid = vsi->seid;
11315         ctxt.pf_num = hw->pf_id;
11316         ctxt.vf_num = 0;
11317         ctxt.uplink_seid = vsi->uplink_seid;
11318         ctxt.info = vsi->info;
11319         i40e_get_cap(hw);
11320         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11321         if (ret)
11322                 goto out;
11323
11324         /* Update the VSI after updating the VSI queue-mapping information */
11325         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11326         if (ret) {
11327                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11328                         hw->aq.asq_last_status);
11329                 goto out;
11330         }
11331         /* update the local VSI info with updated queue map */
11332         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11333                                         sizeof(vsi->info.tc_mapping));
11334         rte_memcpy(&vsi->info.queue_mapping,
11335                         &ctxt.info.queue_mapping,
11336                 sizeof(vsi->info.queue_mapping));
11337         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11338         vsi->info.valid_sections = 0;
11339
11340         /* query and update current VSI BW information */
11341         ret = i40e_vsi_get_bw_config(vsi);
11342         if (ret) {
11343                 PMD_INIT_LOG(ERR,
11344                          "Failed updating vsi bw info, err %s aq_err %s",
11345                          i40e_stat_str(hw, ret),
11346                          i40e_aq_str(hw, hw->aq.asq_last_status));
11347                 goto out;
11348         }
11349
11350         vsi->enabled_tc = tc_map;
11351
11352 out:
11353         return ret;
11354 }
11355
11356 /*
11357  * i40e_dcb_hw_configure - program the dcb setting to hw
11358  * @pf: pf the configuration is taken on
11359  * @new_cfg: new configuration
11360  * @tc_map: enabled TC bitmap
11361  *
11362  * Returns 0 on success, negative value on failure
11363  */
11364 static enum i40e_status_code
11365 i40e_dcb_hw_configure(struct i40e_pf *pf,
11366                       struct i40e_dcbx_config *new_cfg,
11367                       uint8_t tc_map)
11368 {
11369         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11370         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11371         struct i40e_vsi *main_vsi = pf->main_vsi;
11372         struct i40e_vsi_list *vsi_list;
11373         enum i40e_status_code ret;
11374         int i;
11375         uint32_t val;
11376
11377         /* Use the FW API if FW > v4.4*/
11378         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11379               (hw->aq.fw_maj_ver >= 5))) {
11380                 PMD_INIT_LOG(ERR,
11381                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11382                 return I40E_ERR_FIRMWARE_API_VERSION;
11383         }
11384
11385         /* Check if need reconfiguration */
11386         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11387                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11388                 return I40E_SUCCESS;
11389         }
11390
11391         /* Copy the new config to the current config */
11392         *old_cfg = *new_cfg;
11393         old_cfg->etsrec = old_cfg->etscfg;
11394         ret = i40e_set_dcb_config(hw);
11395         if (ret) {
11396                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11397                          i40e_stat_str(hw, ret),
11398                          i40e_aq_str(hw, hw->aq.asq_last_status));
11399                 return ret;
11400         }
11401         /* set receive Arbiter to RR mode and ETS scheme by default */
11402         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11403                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11404                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11405                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11406                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11407                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11408                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11409                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11410                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11411                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11412                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11413                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11414                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11415         }
11416         /* get local mib to check whether it is configured correctly */
11417         /* IEEE mode */
11418         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11419         /* Get Local DCB Config */
11420         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11421                                      &hw->local_dcbx_config);
11422
11423         /* if Veb is created, need to update TC of it at first */
11424         if (main_vsi->veb) {
11425                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11426                 if (ret)
11427                         PMD_INIT_LOG(WARNING,
11428                                  "Failed configuring TC for VEB seid=%d",
11429                                  main_vsi->veb->seid);
11430         }
11431         /* Update each VSI */
11432         i40e_vsi_config_tc(main_vsi, tc_map);
11433         if (main_vsi->veb) {
11434                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11435                         /* Beside main VSI and VMDQ VSIs, only enable default
11436                          * TC for other VSIs
11437                          */
11438                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11439                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11440                                                          tc_map);
11441                         else
11442                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11443                                                          I40E_DEFAULT_TCMAP);
11444                         if (ret)
11445                                 PMD_INIT_LOG(WARNING,
11446                                         "Failed configuring TC for VSI seid=%d",
11447                                         vsi_list->vsi->seid);
11448                         /* continue */
11449                 }
11450         }
11451         return I40E_SUCCESS;
11452 }
11453
11454 /*
11455  * i40e_dcb_init_configure - initial dcb config
11456  * @dev: device being configured
11457  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11458  *
11459  * Returns 0 on success, negative value on failure
11460  */
11461 int
11462 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11463 {
11464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11466         int i, ret = 0;
11467
11468         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11469                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11470                 return -ENOTSUP;
11471         }
11472
11473         /* DCB initialization:
11474          * Update DCB configuration from the Firmware and configure
11475          * LLDP MIB change event.
11476          */
11477         if (sw_dcb == TRUE) {
11478                 if (i40e_need_stop_lldp(dev)) {
11479                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11480                         if (ret != I40E_SUCCESS)
11481                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11482                 }
11483
11484                 ret = i40e_init_dcb(hw);
11485                 /* If lldp agent is stopped, the return value from
11486                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11487                  * adminq status. Otherwise, it should return success.
11488                  */
11489                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11490                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11491                         memset(&hw->local_dcbx_config, 0,
11492                                 sizeof(struct i40e_dcbx_config));
11493                         /* set dcb default configuration */
11494                         hw->local_dcbx_config.etscfg.willing = 0;
11495                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11496                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11497                         hw->local_dcbx_config.etscfg.tsatable[0] =
11498                                                 I40E_IEEE_TSA_ETS;
11499                         /* all UPs mapping to TC0 */
11500                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11501                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11502                         hw->local_dcbx_config.etsrec =
11503                                 hw->local_dcbx_config.etscfg;
11504                         hw->local_dcbx_config.pfc.willing = 0;
11505                         hw->local_dcbx_config.pfc.pfccap =
11506                                                 I40E_MAX_TRAFFIC_CLASS;
11507                         /* FW needs one App to configure HW */
11508                         hw->local_dcbx_config.numapps = 1;
11509                         hw->local_dcbx_config.app[0].selector =
11510                                                 I40E_APP_SEL_ETHTYPE;
11511                         hw->local_dcbx_config.app[0].priority = 3;
11512                         hw->local_dcbx_config.app[0].protocolid =
11513                                                 I40E_APP_PROTOID_FCOE;
11514                         ret = i40e_set_dcb_config(hw);
11515                         if (ret) {
11516                                 PMD_INIT_LOG(ERR,
11517                                         "default dcb config fails. err = %d, aq_err = %d.",
11518                                         ret, hw->aq.asq_last_status);
11519                                 return -ENOSYS;
11520                         }
11521                 } else {
11522                         PMD_INIT_LOG(ERR,
11523                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11524                                 ret, hw->aq.asq_last_status);
11525                         return -ENOTSUP;
11526                 }
11527         } else {
11528                 ret = i40e_aq_start_lldp(hw, NULL);
11529                 if (ret != I40E_SUCCESS)
11530                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11531
11532                 ret = i40e_init_dcb(hw);
11533                 if (!ret) {
11534                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11535                                 PMD_INIT_LOG(ERR,
11536                                         "HW doesn't support DCBX offload.");
11537                                 return -ENOTSUP;
11538                         }
11539                 } else {
11540                         PMD_INIT_LOG(ERR,
11541                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11542                                 ret, hw->aq.asq_last_status);
11543                         return -ENOTSUP;
11544                 }
11545         }
11546         return 0;
11547 }
11548
11549 /*
11550  * i40e_dcb_setup - setup dcb related config
11551  * @dev: device being configured
11552  *
11553  * Returns 0 on success, negative value on failure
11554  */
11555 static int
11556 i40e_dcb_setup(struct rte_eth_dev *dev)
11557 {
11558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11559         struct i40e_dcbx_config dcb_cfg;
11560         uint8_t tc_map = 0;
11561         int ret = 0;
11562
11563         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11564                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11565                 return -ENOTSUP;
11566         }
11567
11568         if (pf->vf_num != 0)
11569                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11570
11571         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11572         if (ret) {
11573                 PMD_INIT_LOG(ERR, "invalid dcb config");
11574                 return -EINVAL;
11575         }
11576         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11577         if (ret) {
11578                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11579                 return -ENOSYS;
11580         }
11581
11582         return 0;
11583 }
11584
11585 static int
11586 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11587                       struct rte_eth_dcb_info *dcb_info)
11588 {
11589         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11590         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11591         struct i40e_vsi *vsi = pf->main_vsi;
11592         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11593         uint16_t bsf, tc_mapping;
11594         int i, j = 0;
11595
11596         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11597                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11598         else
11599                 dcb_info->nb_tcs = 1;
11600         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11601                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11602         for (i = 0; i < dcb_info->nb_tcs; i++)
11603                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11604
11605         /* get queue mapping if vmdq is disabled */
11606         if (!pf->nb_cfg_vmdq_vsi) {
11607                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11608                         if (!(vsi->enabled_tc & (1 << i)))
11609                                 continue;
11610                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11611                         dcb_info->tc_queue.tc_rxq[j][i].base =
11612                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11613                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11614                         dcb_info->tc_queue.tc_txq[j][i].base =
11615                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11616                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11617                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11618                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11619                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11620                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11621                 }
11622                 return 0;
11623         }
11624
11625         /* get queue mapping if vmdq is enabled */
11626         do {
11627                 vsi = pf->vmdq[j].vsi;
11628                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11629                         if (!(vsi->enabled_tc & (1 << i)))
11630                                 continue;
11631                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11632                         dcb_info->tc_queue.tc_rxq[j][i].base =
11633                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11634                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11635                         dcb_info->tc_queue.tc_txq[j][i].base =
11636                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11637                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11638                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11639                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11640                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11641                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11642                 }
11643                 j++;
11644         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11645         return 0;
11646 }
11647
11648 static int
11649 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11650 {
11651         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11652         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11654         uint16_t msix_intr;
11655
11656         msix_intr = intr_handle->intr_vec[queue_id];
11657         if (msix_intr == I40E_MISC_VEC_ID)
11658                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11659                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11660                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11661                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11662         else
11663                 I40E_WRITE_REG(hw,
11664                                I40E_PFINT_DYN_CTLN(msix_intr -
11665                                                    I40E_RX_VEC_START),
11666                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11667                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11668                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11669
11670         I40E_WRITE_FLUSH(hw);
11671         rte_intr_ack(&pci_dev->intr_handle);
11672
11673         return 0;
11674 }
11675
11676 static int
11677 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11678 {
11679         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11680         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11682         uint16_t msix_intr;
11683
11684         msix_intr = intr_handle->intr_vec[queue_id];
11685         if (msix_intr == I40E_MISC_VEC_ID)
11686                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11687                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11688         else
11689                 I40E_WRITE_REG(hw,
11690                                I40E_PFINT_DYN_CTLN(msix_intr -
11691                                                    I40E_RX_VEC_START),
11692                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11693         I40E_WRITE_FLUSH(hw);
11694
11695         return 0;
11696 }
11697
11698 /**
11699  * This function is used to check if the register is valid.
11700  * Below is the valid registers list for X722 only:
11701  * 0x2b800--0x2bb00
11702  * 0x38700--0x38a00
11703  * 0x3d800--0x3db00
11704  * 0x208e00--0x209000
11705  * 0x20be00--0x20c000
11706  * 0x263c00--0x264000
11707  * 0x265c00--0x266000
11708  */
11709 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11710 {
11711         if ((type != I40E_MAC_X722) &&
11712             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11713              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11714              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11715              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11716              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11717              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11718              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11719                 return 0;
11720         else
11721                 return 1;
11722 }
11723
11724 static int i40e_get_regs(struct rte_eth_dev *dev,
11725                          struct rte_dev_reg_info *regs)
11726 {
11727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11728         uint32_t *ptr_data = regs->data;
11729         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11730         const struct i40e_reg_info *reg_info;
11731
11732         if (ptr_data == NULL) {
11733                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11734                 regs->width = sizeof(uint32_t);
11735                 return 0;
11736         }
11737
11738         /* The first few registers have to be read using AQ operations */
11739         reg_idx = 0;
11740         while (i40e_regs_adminq[reg_idx].name) {
11741                 reg_info = &i40e_regs_adminq[reg_idx++];
11742                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11743                         for (arr_idx2 = 0;
11744                                         arr_idx2 <= reg_info->count2;
11745                                         arr_idx2++) {
11746                                 reg_offset = arr_idx * reg_info->stride1 +
11747                                         arr_idx2 * reg_info->stride2;
11748                                 reg_offset += reg_info->base_addr;
11749                                 ptr_data[reg_offset >> 2] =
11750                                         i40e_read_rx_ctl(hw, reg_offset);
11751                         }
11752         }
11753
11754         /* The remaining registers can be read using primitives */
11755         reg_idx = 0;
11756         while (i40e_regs_others[reg_idx].name) {
11757                 reg_info = &i40e_regs_others[reg_idx++];
11758                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11759                         for (arr_idx2 = 0;
11760                                         arr_idx2 <= reg_info->count2;
11761                                         arr_idx2++) {
11762                                 reg_offset = arr_idx * reg_info->stride1 +
11763                                         arr_idx2 * reg_info->stride2;
11764                                 reg_offset += reg_info->base_addr;
11765                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11766                                         ptr_data[reg_offset >> 2] = 0;
11767                                 else
11768                                         ptr_data[reg_offset >> 2] =
11769                                                 I40E_READ_REG(hw, reg_offset);
11770                         }
11771         }
11772
11773         return 0;
11774 }
11775
11776 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11777 {
11778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11779
11780         /* Convert word count to byte count */
11781         return hw->nvm.sr_size << 1;
11782 }
11783
11784 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11785                            struct rte_dev_eeprom_info *eeprom)
11786 {
11787         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11788         uint16_t *data = eeprom->data;
11789         uint16_t offset, length, cnt_words;
11790         int ret_code;
11791
11792         offset = eeprom->offset >> 1;
11793         length = eeprom->length >> 1;
11794         cnt_words = length;
11795
11796         if (offset > hw->nvm.sr_size ||
11797                 offset + length > hw->nvm.sr_size) {
11798                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11799                 return -EINVAL;
11800         }
11801
11802         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11803
11804         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11805         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11806                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11807                 return -EIO;
11808         }
11809
11810         return 0;
11811 }
11812
11813 static int i40e_get_module_info(struct rte_eth_dev *dev,
11814                                 struct rte_eth_dev_module_info *modinfo)
11815 {
11816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11817         uint32_t sff8472_comp = 0;
11818         uint32_t sff8472_swap = 0;
11819         uint32_t sff8636_rev = 0;
11820         i40e_status status;
11821         uint32_t type = 0;
11822
11823         /* Check if firmware supports reading module EEPROM. */
11824         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11825                 PMD_DRV_LOG(ERR,
11826                             "Module EEPROM memory read not supported. "
11827                             "Please update the NVM image.\n");
11828                 return -EINVAL;
11829         }
11830
11831         status = i40e_update_link_info(hw);
11832         if (status)
11833                 return -EIO;
11834
11835         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11836                 PMD_DRV_LOG(ERR,
11837                             "Cannot read module EEPROM memory. "
11838                             "No module connected.\n");
11839                 return -EINVAL;
11840         }
11841
11842         type = hw->phy.link_info.module_type[0];
11843
11844         switch (type) {
11845         case I40E_MODULE_TYPE_SFP:
11846                 status = i40e_aq_get_phy_register(hw,
11847                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11848                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11849                                 I40E_MODULE_SFF_8472_COMP,
11850                                 &sff8472_comp, NULL);
11851                 if (status)
11852                         return -EIO;
11853
11854                 status = i40e_aq_get_phy_register(hw,
11855                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11856                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11857                                 I40E_MODULE_SFF_8472_SWAP,
11858                                 &sff8472_swap, NULL);
11859                 if (status)
11860                         return -EIO;
11861
11862                 /* Check if the module requires address swap to access
11863                  * the other EEPROM memory page.
11864                  */
11865                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11866                         PMD_DRV_LOG(WARNING,
11867                                     "Module address swap to access "
11868                                     "page 0xA2 is not supported.\n");
11869                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11870                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11871                 } else if (sff8472_comp == 0x00) {
11872                         /* Module is not SFF-8472 compliant */
11873                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11874                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11875                 } else {
11876                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11877                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11878                 }
11879                 break;
11880         case I40E_MODULE_TYPE_QSFP_PLUS:
11881                 /* Read from memory page 0. */
11882                 status = i40e_aq_get_phy_register(hw,
11883                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11884                                 0, 1,
11885                                 I40E_MODULE_REVISION_ADDR,
11886                                 &sff8636_rev, NULL);
11887                 if (status)
11888                         return -EIO;
11889                 /* Determine revision compliance byte */
11890                 if (sff8636_rev > 0x02) {
11891                         /* Module is SFF-8636 compliant */
11892                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11893                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11894                 } else {
11895                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11896                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11897                 }
11898                 break;
11899         case I40E_MODULE_TYPE_QSFP28:
11900                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11901                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11902                 break;
11903         default:
11904                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11905                 return -EINVAL;
11906         }
11907         return 0;
11908 }
11909
11910 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11911                                   struct rte_dev_eeprom_info *info)
11912 {
11913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11914         bool is_sfp = false;
11915         i40e_status status;
11916         uint8_t *data;
11917         uint32_t value = 0;
11918         uint32_t i;
11919
11920         if (!info || !info->length || !info->data)
11921                 return -EINVAL;
11922
11923         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11924                 is_sfp = true;
11925
11926         data = info->data;
11927         for (i = 0; i < info->length; i++) {
11928                 u32 offset = i + info->offset;
11929                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11930
11931                 /* Check if we need to access the other memory page */
11932                 if (is_sfp) {
11933                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11934                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11935                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11936                         }
11937                 } else {
11938                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11939                                 /* Compute memory page number and offset. */
11940                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11941                                 addr++;
11942                         }
11943                 }
11944                 status = i40e_aq_get_phy_register(hw,
11945                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11946                                 addr, offset, 1, &value, NULL);
11947                 if (status)
11948                         return -EIO;
11949                 data[i] = (uint8_t)value;
11950         }
11951         return 0;
11952 }
11953
11954 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11955                                      struct rte_ether_addr *mac_addr)
11956 {
11957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11959         struct i40e_vsi *vsi = pf->main_vsi;
11960         struct i40e_mac_filter_info mac_filter;
11961         struct i40e_mac_filter *f;
11962         int ret;
11963
11964         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11965                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11966                 return -EINVAL;
11967         }
11968
11969         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11970                 if (rte_is_same_ether_addr(&pf->dev_addr,
11971                                                 &f->mac_info.mac_addr))
11972                         break;
11973         }
11974
11975         if (f == NULL) {
11976                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11977                 return -EIO;
11978         }
11979
11980         mac_filter = f->mac_info;
11981         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11982         if (ret != I40E_SUCCESS) {
11983                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11984                 return -EIO;
11985         }
11986         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11987         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11988         if (ret != I40E_SUCCESS) {
11989                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11990                 return -EIO;
11991         }
11992         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11993
11994         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11995                                         mac_addr->addr_bytes, NULL);
11996         if (ret != I40E_SUCCESS) {
11997                 PMD_DRV_LOG(ERR, "Failed to change mac");
11998                 return -EIO;
11999         }
12000
12001         return 0;
12002 }
12003
12004 static int
12005 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12006 {
12007         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12008         struct rte_eth_dev_data *dev_data = pf->dev_data;
12009         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12010         int ret = 0;
12011
12012         /* check if mtu is within the allowed range */
12013         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12014                 return -EINVAL;
12015
12016         /* mtu setting is forbidden if port is start */
12017         if (dev_data->dev_started) {
12018                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12019                             dev_data->port_id);
12020                 return -EBUSY;
12021         }
12022
12023         if (frame_size > RTE_ETHER_MAX_LEN)
12024                 dev_data->dev_conf.rxmode.offloads |=
12025                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12026         else
12027                 dev_data->dev_conf.rxmode.offloads &=
12028                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12029
12030         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12031
12032         return ret;
12033 }
12034
12035 /* Restore ethertype filter */
12036 static void
12037 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12038 {
12039         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12040         struct i40e_ethertype_filter_list
12041                 *ethertype_list = &pf->ethertype.ethertype_list;
12042         struct i40e_ethertype_filter *f;
12043         struct i40e_control_filter_stats stats;
12044         uint16_t flags;
12045
12046         TAILQ_FOREACH(f, ethertype_list, rules) {
12047                 flags = 0;
12048                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12049                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12050                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12051                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12052                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12053
12054                 memset(&stats, 0, sizeof(stats));
12055                 i40e_aq_add_rem_control_packet_filter(hw,
12056                                             f->input.mac_addr.addr_bytes,
12057                                             f->input.ether_type,
12058                                             flags, pf->main_vsi->seid,
12059                                             f->queue, 1, &stats, NULL);
12060         }
12061         PMD_DRV_LOG(INFO, "Ethertype filter:"
12062                     " mac_etype_used = %u, etype_used = %u,"
12063                     " mac_etype_free = %u, etype_free = %u",
12064                     stats.mac_etype_used, stats.etype_used,
12065                     stats.mac_etype_free, stats.etype_free);
12066 }
12067
12068 /* Restore tunnel filter */
12069 static void
12070 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12071 {
12072         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12073         struct i40e_vsi *vsi;
12074         struct i40e_pf_vf *vf;
12075         struct i40e_tunnel_filter_list
12076                 *tunnel_list = &pf->tunnel.tunnel_list;
12077         struct i40e_tunnel_filter *f;
12078         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12079         bool big_buffer = 0;
12080
12081         TAILQ_FOREACH(f, tunnel_list, rules) {
12082                 if (!f->is_to_vf)
12083                         vsi = pf->main_vsi;
12084                 else {
12085                         vf = &pf->vfs[f->vf_id];
12086                         vsi = vf->vsi;
12087                 }
12088                 memset(&cld_filter, 0, sizeof(cld_filter));
12089                 rte_ether_addr_copy((struct rte_ether_addr *)
12090                                 &f->input.outer_mac,
12091                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12092                 rte_ether_addr_copy((struct rte_ether_addr *)
12093                                 &f->input.inner_mac,
12094                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12095                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12096                 cld_filter.element.flags = f->input.flags;
12097                 cld_filter.element.tenant_id = f->input.tenant_id;
12098                 cld_filter.element.queue_number = f->queue;
12099                 rte_memcpy(cld_filter.general_fields,
12100                            f->input.general_fields,
12101                            sizeof(f->input.general_fields));
12102
12103                 if (((f->input.flags &
12104                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12105                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12106                     ((f->input.flags &
12107                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12108                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12109                     ((f->input.flags &
12110                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12111                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12112                         big_buffer = 1;
12113
12114                 if (big_buffer)
12115                         i40e_aq_add_cloud_filters_bb(hw,
12116                                         vsi->seid, &cld_filter, 1);
12117                 else
12118                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12119                                                   &cld_filter.element, 1);
12120         }
12121 }
12122
12123 /* Restore rss filter */
12124 static inline void
12125 i40e_rss_filter_restore(struct i40e_pf *pf)
12126 {
12127         struct i40e_rte_flow_rss_conf *conf =
12128                                         &pf->rss_info;
12129         if (conf->conf.queue_num)
12130                 i40e_config_rss_filter(pf, conf, TRUE);
12131 }
12132
12133 static void
12134 i40e_filter_restore(struct i40e_pf *pf)
12135 {
12136         i40e_ethertype_filter_restore(pf);
12137         i40e_tunnel_filter_restore(pf);
12138         i40e_fdir_filter_restore(pf);
12139         i40e_rss_filter_restore(pf);
12140 }
12141
12142 bool
12143 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12144 {
12145         if (strcmp(dev->device->driver->name, drv->driver.name))
12146                 return false;
12147
12148         return true;
12149 }
12150
12151 bool
12152 is_i40e_supported(struct rte_eth_dev *dev)
12153 {
12154         return is_device_supported(dev, &rte_i40e_pmd);
12155 }
12156
12157 struct i40e_customized_pctype*
12158 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12159 {
12160         int i;
12161
12162         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12163                 if (pf->customized_pctype[i].index == index)
12164                         return &pf->customized_pctype[i];
12165         }
12166         return NULL;
12167 }
12168
12169 static int
12170 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12171                               uint32_t pkg_size, uint32_t proto_num,
12172                               struct rte_pmd_i40e_proto_info *proto,
12173                               enum rte_pmd_i40e_package_op op)
12174 {
12175         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12176         uint32_t pctype_num;
12177         struct rte_pmd_i40e_ptype_info *pctype;
12178         uint32_t buff_size;
12179         struct i40e_customized_pctype *new_pctype = NULL;
12180         uint8_t proto_id;
12181         uint8_t pctype_value;
12182         char name[64];
12183         uint32_t i, j, n;
12184         int ret;
12185
12186         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12187             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12188                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12189                 return -1;
12190         }
12191
12192         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12193                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12194                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12195         if (ret) {
12196                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12197                 return -1;
12198         }
12199         if (!pctype_num) {
12200                 PMD_DRV_LOG(INFO, "No new pctype added");
12201                 return -1;
12202         }
12203
12204         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12205         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12206         if (!pctype) {
12207                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12208                 return -1;
12209         }
12210         /* get information about new pctype list */
12211         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12212                                         (uint8_t *)pctype, buff_size,
12213                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12214         if (ret) {
12215                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12216                 rte_free(pctype);
12217                 return -1;
12218         }
12219
12220         /* Update customized pctype. */
12221         for (i = 0; i < pctype_num; i++) {
12222                 pctype_value = pctype[i].ptype_id;
12223                 memset(name, 0, sizeof(name));
12224                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12225                         proto_id = pctype[i].protocols[j];
12226                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12227                                 continue;
12228                         for (n = 0; n < proto_num; n++) {
12229                                 if (proto[n].proto_id != proto_id)
12230                                         continue;
12231                                 strlcat(name, proto[n].name, sizeof(name));
12232                                 strlcat(name, "_", sizeof(name));
12233                                 break;
12234                         }
12235                 }
12236                 name[strlen(name) - 1] = '\0';
12237                 if (!strcmp(name, "GTPC"))
12238                         new_pctype =
12239                                 i40e_find_customized_pctype(pf,
12240                                                       I40E_CUSTOMIZED_GTPC);
12241                 else if (!strcmp(name, "GTPU_IPV4"))
12242                         new_pctype =
12243                                 i40e_find_customized_pctype(pf,
12244                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12245                 else if (!strcmp(name, "GTPU_IPV6"))
12246                         new_pctype =
12247                                 i40e_find_customized_pctype(pf,
12248                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12249                 else if (!strcmp(name, "GTPU"))
12250                         new_pctype =
12251                                 i40e_find_customized_pctype(pf,
12252                                                       I40E_CUSTOMIZED_GTPU);
12253                 if (new_pctype) {
12254                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12255                                 new_pctype->pctype = pctype_value;
12256                                 new_pctype->valid = true;
12257                         } else {
12258                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12259                                 new_pctype->valid = false;
12260                         }
12261                 }
12262         }
12263
12264         rte_free(pctype);
12265         return 0;
12266 }
12267
12268 static int
12269 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12270                              uint32_t pkg_size, uint32_t proto_num,
12271                              struct rte_pmd_i40e_proto_info *proto,
12272                              enum rte_pmd_i40e_package_op op)
12273 {
12274         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12275         uint16_t port_id = dev->data->port_id;
12276         uint32_t ptype_num;
12277         struct rte_pmd_i40e_ptype_info *ptype;
12278         uint32_t buff_size;
12279         uint8_t proto_id;
12280         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12281         uint32_t i, j, n;
12282         bool in_tunnel;
12283         int ret;
12284
12285         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12286             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12287                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12288                 return -1;
12289         }
12290
12291         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12292                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12293                 return 0;
12294         }
12295
12296         /* get information about new ptype num */
12297         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12298                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12299                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12300         if (ret) {
12301                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12302                 return ret;
12303         }
12304         if (!ptype_num) {
12305                 PMD_DRV_LOG(INFO, "No new ptype added");
12306                 return -1;
12307         }
12308
12309         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12310         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12311         if (!ptype) {
12312                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12313                 return -1;
12314         }
12315
12316         /* get information about new ptype list */
12317         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12318                                         (uint8_t *)ptype, buff_size,
12319                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12320         if (ret) {
12321                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12322                 rte_free(ptype);
12323                 return ret;
12324         }
12325
12326         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12327         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12328         if (!ptype_mapping) {
12329                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12330                 rte_free(ptype);
12331                 return -1;
12332         }
12333
12334         /* Update ptype mapping table. */
12335         for (i = 0; i < ptype_num; i++) {
12336                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12337                 ptype_mapping[i].sw_ptype = 0;
12338                 in_tunnel = false;
12339                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12340                         proto_id = ptype[i].protocols[j];
12341                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12342                                 continue;
12343                         for (n = 0; n < proto_num; n++) {
12344                                 if (proto[n].proto_id != proto_id)
12345                                         continue;
12346                                 memset(name, 0, sizeof(name));
12347                                 strcpy(name, proto[n].name);
12348                                 if (!strncasecmp(name, "PPPOE", 5))
12349                                         ptype_mapping[i].sw_ptype |=
12350                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12351                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12352                                          !in_tunnel) {
12353                                         ptype_mapping[i].sw_ptype |=
12354                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12355                                         ptype_mapping[i].sw_ptype |=
12356                                                 RTE_PTYPE_L4_FRAG;
12357                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12358                                            in_tunnel) {
12359                                         ptype_mapping[i].sw_ptype |=
12360                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12361                                         ptype_mapping[i].sw_ptype |=
12362                                                 RTE_PTYPE_INNER_L4_FRAG;
12363                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12364                                         ptype_mapping[i].sw_ptype |=
12365                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12366                                         in_tunnel = true;
12367                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12368                                            !in_tunnel)
12369                                         ptype_mapping[i].sw_ptype |=
12370                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12371                                 else if (!strncasecmp(name, "IPV4", 4) &&
12372                                          in_tunnel)
12373                                         ptype_mapping[i].sw_ptype |=
12374                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12375                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12376                                          !in_tunnel) {
12377                                         ptype_mapping[i].sw_ptype |=
12378                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12379                                         ptype_mapping[i].sw_ptype |=
12380                                                 RTE_PTYPE_L4_FRAG;
12381                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12382                                            in_tunnel) {
12383                                         ptype_mapping[i].sw_ptype |=
12384                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12385                                         ptype_mapping[i].sw_ptype |=
12386                                                 RTE_PTYPE_INNER_L4_FRAG;
12387                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12388                                         ptype_mapping[i].sw_ptype |=
12389                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12390                                         in_tunnel = true;
12391                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12392                                            !in_tunnel)
12393                                         ptype_mapping[i].sw_ptype |=
12394                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12395                                 else if (!strncasecmp(name, "IPV6", 4) &&
12396                                          in_tunnel)
12397                                         ptype_mapping[i].sw_ptype |=
12398                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12399                                 else if (!strncasecmp(name, "UDP", 3) &&
12400                                          !in_tunnel)
12401                                         ptype_mapping[i].sw_ptype |=
12402                                                 RTE_PTYPE_L4_UDP;
12403                                 else if (!strncasecmp(name, "UDP", 3) &&
12404                                          in_tunnel)
12405                                         ptype_mapping[i].sw_ptype |=
12406                                                 RTE_PTYPE_INNER_L4_UDP;
12407                                 else if (!strncasecmp(name, "TCP", 3) &&
12408                                          !in_tunnel)
12409                                         ptype_mapping[i].sw_ptype |=
12410                                                 RTE_PTYPE_L4_TCP;
12411                                 else if (!strncasecmp(name, "TCP", 3) &&
12412                                          in_tunnel)
12413                                         ptype_mapping[i].sw_ptype |=
12414                                                 RTE_PTYPE_INNER_L4_TCP;
12415                                 else if (!strncasecmp(name, "SCTP", 4) &&
12416                                          !in_tunnel)
12417                                         ptype_mapping[i].sw_ptype |=
12418                                                 RTE_PTYPE_L4_SCTP;
12419                                 else if (!strncasecmp(name, "SCTP", 4) &&
12420                                          in_tunnel)
12421                                         ptype_mapping[i].sw_ptype |=
12422                                                 RTE_PTYPE_INNER_L4_SCTP;
12423                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12424                                           !strncasecmp(name, "ICMPV6", 6)) &&
12425                                          !in_tunnel)
12426                                         ptype_mapping[i].sw_ptype |=
12427                                                 RTE_PTYPE_L4_ICMP;
12428                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12429                                           !strncasecmp(name, "ICMPV6", 6)) &&
12430                                          in_tunnel)
12431                                         ptype_mapping[i].sw_ptype |=
12432                                                 RTE_PTYPE_INNER_L4_ICMP;
12433                                 else if (!strncasecmp(name, "GTPC", 4)) {
12434                                         ptype_mapping[i].sw_ptype |=
12435                                                 RTE_PTYPE_TUNNEL_GTPC;
12436                                         in_tunnel = true;
12437                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12438                                         ptype_mapping[i].sw_ptype |=
12439                                                 RTE_PTYPE_TUNNEL_GTPU;
12440                                         in_tunnel = true;
12441                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12442                                         ptype_mapping[i].sw_ptype |=
12443                                                 RTE_PTYPE_TUNNEL_GRENAT;
12444                                         in_tunnel = true;
12445                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12446                                            !strncasecmp(name, "L2TPV2", 6)) {
12447                                         ptype_mapping[i].sw_ptype |=
12448                                                 RTE_PTYPE_TUNNEL_L2TP;
12449                                         in_tunnel = true;
12450                                 }
12451
12452                                 break;
12453                         }
12454                 }
12455         }
12456
12457         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12458                                                 ptype_num, 0);
12459         if (ret)
12460                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12461
12462         rte_free(ptype_mapping);
12463         rte_free(ptype);
12464         return ret;
12465 }
12466
12467 void
12468 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12469                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12470 {
12471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12472         uint32_t proto_num;
12473         struct rte_pmd_i40e_proto_info *proto;
12474         uint32_t buff_size;
12475         uint32_t i;
12476         int ret;
12477
12478         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12479             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12480                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12481                 return;
12482         }
12483
12484         /* get information about protocol number */
12485         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12486                                        (uint8_t *)&proto_num, sizeof(proto_num),
12487                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12488         if (ret) {
12489                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12490                 return;
12491         }
12492         if (!proto_num) {
12493                 PMD_DRV_LOG(INFO, "No new protocol added");
12494                 return;
12495         }
12496
12497         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12498         proto = rte_zmalloc("new_proto", buff_size, 0);
12499         if (!proto) {
12500                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12501                 return;
12502         }
12503
12504         /* get information about protocol list */
12505         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12506                                         (uint8_t *)proto, buff_size,
12507                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12508         if (ret) {
12509                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12510                 rte_free(proto);
12511                 return;
12512         }
12513
12514         /* Check if GTP is supported. */
12515         for (i = 0; i < proto_num; i++) {
12516                 if (!strncmp(proto[i].name, "GTP", 3)) {
12517                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12518                                 pf->gtp_support = true;
12519                         else
12520                                 pf->gtp_support = false;
12521                         break;
12522                 }
12523         }
12524
12525         /* Update customized pctype info */
12526         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12527                                             proto_num, proto, op);
12528         if (ret)
12529                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12530
12531         /* Update customized ptype info */
12532         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12533                                            proto_num, proto, op);
12534         if (ret)
12535                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12536
12537         rte_free(proto);
12538 }
12539
12540 /* Create a QinQ cloud filter
12541  *
12542  * The Fortville NIC has limited resources for tunnel filters,
12543  * so we can only reuse existing filters.
12544  *
12545  * In step 1 we define which Field Vector fields can be used for
12546  * filter types.
12547  * As we do not have the inner tag defined as a field,
12548  * we have to define it first, by reusing one of L1 entries.
12549  *
12550  * In step 2 we are replacing one of existing filter types with
12551  * a new one for QinQ.
12552  * As we reusing L1 and replacing L2, some of the default filter
12553  * types will disappear,which depends on L1 and L2 entries we reuse.
12554  *
12555  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12556  *
12557  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12558  *              later when we define the cloud filter.
12559  *      a.      Valid_flags.replace_cloud = 0
12560  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12561  *      c.      New_filter = 0x10
12562  *      d.      TR bit = 0xff (optional, not used here)
12563  *      e.      Buffer – 2 entries:
12564  *              i.      Byte 0 = 8 (outer vlan FV index).
12565  *                      Byte 1 = 0 (rsv)
12566  *                      Byte 2-3 = 0x0fff
12567  *              ii.     Byte 0 = 37 (inner vlan FV index).
12568  *                      Byte 1 =0 (rsv)
12569  *                      Byte 2-3 = 0x0fff
12570  *
12571  * Step 2:
12572  * 2.   Create cloud filter using two L1 filters entries: stag and
12573  *              new filter(outer vlan+ inner vlan)
12574  *      a.      Valid_flags.replace_cloud = 1
12575  *      b.      Old_filter = 1 (instead of outer IP)
12576  *      c.      New_filter = 0x10
12577  *      d.      Buffer – 2 entries:
12578  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12579  *                      Byte 1-3 = 0 (rsv)
12580  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12581  *                      Byte 9-11 = 0 (rsv)
12582  */
12583 static int
12584 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12585 {
12586         int ret = -ENOTSUP;
12587         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12588         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12589         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12590         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12591
12592         if (pf->support_multi_driver) {
12593                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12594                 return ret;
12595         }
12596
12597         /* Init */
12598         memset(&filter_replace, 0,
12599                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12600         memset(&filter_replace_buf, 0,
12601                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12602
12603         /* create L1 filter */
12604         filter_replace.old_filter_type =
12605                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12606         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12607         filter_replace.tr_bit = 0;
12608
12609         /* Prepare the buffer, 2 entries */
12610         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12611         filter_replace_buf.data[0] |=
12612                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12613         /* Field Vector 12b mask */
12614         filter_replace_buf.data[2] = 0xff;
12615         filter_replace_buf.data[3] = 0x0f;
12616         filter_replace_buf.data[4] =
12617                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12618         filter_replace_buf.data[4] |=
12619                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12620         /* Field Vector 12b mask */
12621         filter_replace_buf.data[6] = 0xff;
12622         filter_replace_buf.data[7] = 0x0f;
12623         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12624                         &filter_replace_buf);
12625         if (ret != I40E_SUCCESS)
12626                 return ret;
12627
12628         if (filter_replace.old_filter_type !=
12629             filter_replace.new_filter_type)
12630                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12631                             " original: 0x%x, new: 0x%x",
12632                             dev->device->name,
12633                             filter_replace.old_filter_type,
12634                             filter_replace.new_filter_type);
12635
12636         /* Apply the second L2 cloud filter */
12637         memset(&filter_replace, 0,
12638                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12639         memset(&filter_replace_buf, 0,
12640                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12641
12642         /* create L2 filter, input for L2 filter will be L1 filter  */
12643         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12644         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12645         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12646
12647         /* Prepare the buffer, 2 entries */
12648         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12649         filter_replace_buf.data[0] |=
12650                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12651         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12652         filter_replace_buf.data[4] |=
12653                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12654         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12655                         &filter_replace_buf);
12656         if (!ret && (filter_replace.old_filter_type !=
12657                      filter_replace.new_filter_type))
12658                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12659                             " original: 0x%x, new: 0x%x",
12660                             dev->device->name,
12661                             filter_replace.old_filter_type,
12662                             filter_replace.new_filter_type);
12663
12664         return ret;
12665 }
12666
12667 int
12668 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12669                    const struct rte_flow_action_rss *in)
12670 {
12671         if (in->key_len > RTE_DIM(out->key) ||
12672             in->queue_num > RTE_DIM(out->queue))
12673                 return -EINVAL;
12674         if (!in->key && in->key_len)
12675                 return -EINVAL;
12676         out->conf = (struct rte_flow_action_rss){
12677                 .func = in->func,
12678                 .level = in->level,
12679                 .types = in->types,
12680                 .key_len = in->key_len,
12681                 .queue_num = in->queue_num,
12682                 .queue = memcpy(out->queue, in->queue,
12683                                 sizeof(*in->queue) * in->queue_num),
12684         };
12685         if (in->key)
12686                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12687         return 0;
12688 }
12689
12690 int
12691 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12692                      const struct rte_flow_action_rss *with)
12693 {
12694         return (comp->func == with->func &&
12695                 comp->level == with->level &&
12696                 comp->types == with->types &&
12697                 comp->key_len == with->key_len &&
12698                 comp->queue_num == with->queue_num &&
12699                 !memcmp(comp->key, with->key, with->key_len) &&
12700                 !memcmp(comp->queue, with->queue,
12701                         sizeof(*with->queue) * with->queue_num));
12702 }
12703
12704 int
12705 i40e_config_rss_filter(struct i40e_pf *pf,
12706                 struct i40e_rte_flow_rss_conf *conf, bool add)
12707 {
12708         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12709         uint32_t i, lut = 0;
12710         uint16_t j, num;
12711         struct rte_eth_rss_conf rss_conf = {
12712                 .rss_key = conf->conf.key_len ?
12713                         (void *)(uintptr_t)conf->conf.key : NULL,
12714                 .rss_key_len = conf->conf.key_len,
12715                 .rss_hf = conf->conf.types,
12716         };
12717         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12718
12719         if (!add) {
12720                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12721                         i40e_pf_disable_rss(pf);
12722                         memset(rss_info, 0,
12723                                 sizeof(struct i40e_rte_flow_rss_conf));
12724                         return 0;
12725                 }
12726                 return -EINVAL;
12727         }
12728
12729         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12730          * It's necessary to calculate the actual PF queues that are configured.
12731          */
12732         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12733                 num = i40e_pf_calc_configured_queues_num(pf);
12734         else
12735                 num = pf->dev_data->nb_rx_queues;
12736
12737         num = RTE_MIN(num, conf->conf.queue_num);
12738         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12739                         num);
12740
12741         if (num == 0) {
12742                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12743                 return -ENOTSUP;
12744         }
12745
12746         /* Fill in redirection table */
12747         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12748                 if (j == num)
12749                         j = 0;
12750                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12751                         hw->func_caps.rss_table_entry_width) - 1));
12752                 if ((i & 3) == 3)
12753                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12754         }
12755
12756         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12757                 i40e_pf_disable_rss(pf);
12758                 return 0;
12759         }
12760         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12761                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12762                 /* Random default keys */
12763                 static uint32_t rss_key_default[] = {0x6b793944,
12764                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12765                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12766                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12767
12768                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12769                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12770                                                         sizeof(uint32_t);
12771                 PMD_DRV_LOG(INFO,
12772                         "No valid RSS key config for i40e, using default\n");
12773         }
12774
12775         i40e_hw_rss_hash_set(pf, &rss_conf);
12776
12777         if (i40e_rss_conf_init(rss_info, &conf->conf))
12778                 return -EINVAL;
12779
12780         return 0;
12781 }
12782
12783 RTE_INIT(i40e_init_log)
12784 {
12785         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12786         if (i40e_logtype_init >= 0)
12787                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12788         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12789         if (i40e_logtype_driver >= 0)
12790                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12791 }
12792
12793 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12794                               ETH_I40E_FLOATING_VEB_ARG "=1"
12795                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12796                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12797                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12798                               ETH_I40E_USE_LATEST_VEC "=0|1");