drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 241                                             uint16_t queue_id,
 242                                             uint8_t stat_idx,
 243                                             uint8_t is_rx);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 247                               struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 310                                              struct i40e_macvlan_filter *mv_f,
 311                                              int num,
 312                                              uint16_t vlan);
 313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 315                                     struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 317                                       struct rte_eth_rss_conf *rss_conf);
 318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 321                                         struct rte_eth_udp_tunnel *udp_tunnel);
 322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                                 enum rte_filter_type filter_type,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 331                                   struct rte_eth_dcb_info *dcb_info);
 332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 333 static void i40e_configure_registers(struct i40e_hw *hw);
 334 static void i40e_hw_init(struct rte_eth_dev *dev);
 335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 337                                                      uint16_t seid,
 338                                                      uint16_t rule_type,
 339                                                      uint16_t *entries,
 340                                                      uint16_t count,
 341                                                      uint16_t rule_id);
 342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 343                         struct rte_eth_mirror_conf *mirror_conf,
 344                         uint8_t sw_id, uint8_t on);
 345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 346
 347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp,
 351                                            uint32_t flags);
 352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 353                                            struct timespec *timestamp);
 354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 355
 356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 357
 358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 361                                     const struct timespec *timestamp);
 362
 363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 364                                          uint16_t queue_id);
 365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 366                                           uint16_t queue_id);
 367
 368 static int i40e_get_regs(struct rte_eth_dev *dev,
 369                          struct rte_dev_reg_info *regs);
 370
 371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 372
 373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 374                            struct rte_dev_eeprom_info *eeprom);
 375
 376 static int i40e_get_module_info(struct rte_eth_dev *dev,
 377                                 struct rte_eth_dev_module_info *modinfo);
 378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 379                                   struct rte_dev_eeprom_info *info);
 380
 381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 382                                       struct rte_ether_addr *mac_addr);
 383
 384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 385
 386 static int i40e_ethertype_filter_convert(
 387         const struct rte_eth_ethertype_filter *input,
 388         struct i40e_ethertype_filter *filter);
 389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 390                                    struct i40e_ethertype_filter *filter);
 391
 392 static int i40e_tunnel_filter_convert(
 393         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 394         struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 396                                 struct i40e_tunnel_filter *tunnel_filter);
 397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 398
 399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 401 static void i40e_filter_restore(struct i40e_pf *pf);
 402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 403
 404 int i40e_logtype_init;
 405 int i40e_logtype_driver;
 406
 407 static const char *const valid_keys[] = {
 408         ETH_I40E_FLOATING_VEB_ARG,
 409         ETH_I40E_FLOATING_VEB_LIST_ARG,
 410         ETH_I40E_SUPPORT_MULTI_DRIVER,
 411         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 412         ETH_I40E_USE_LATEST_VEC,
 413         NULL};
 414
 415 static const struct rte_pci_id pci_id_i40e_map[] = {
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 439         { .vendor_id = 0, /* sentinel */ },
 440 };
 441
 442 static const struct eth_dev_ops i40e_eth_dev_ops = {
 443         .dev_configure                = i40e_dev_configure,
 444         .dev_start                    = i40e_dev_start,
 445         .dev_stop                     = i40e_dev_stop,
 446         .dev_close                    = i40e_dev_close,
 447         .dev_reset                    = i40e_dev_reset,
 448         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 449         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 450         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 451         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 452         .dev_set_link_up              = i40e_dev_set_link_up,
 453         .dev_set_link_down            = i40e_dev_set_link_down,
 454         .link_update                  = i40e_dev_link_update,
 455         .stats_get                    = i40e_dev_stats_get,
 456         .xstats_get                   = i40e_dev_xstats_get,
 457         .xstats_get_names             = i40e_dev_xstats_get_names,
 458         .stats_reset                  = i40e_dev_stats_reset,
 459         .xstats_reset                 = i40e_dev_stats_reset,
 460         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 461         .fw_version_get               = i40e_fw_version_get,
 462         .dev_infos_get                = i40e_dev_info_get,
 463         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 464         .vlan_filter_set              = i40e_vlan_filter_set,
 465         .vlan_tpid_set                = i40e_vlan_tpid_set,
 466         .vlan_offload_set             = i40e_vlan_offload_set,
 467         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 468         .vlan_pvid_set                = i40e_vlan_pvid_set,
 469         .rx_queue_start               = i40e_dev_rx_queue_start,
 470         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 471         .tx_queue_start               = i40e_dev_tx_queue_start,
 472         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 473         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 474         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 475         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 476         .rx_queue_release             = i40e_dev_rx_queue_release,
 477         .rx_queue_count               = i40e_dev_rx_queue_count,
 478         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 479         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 480         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .filter_ctrl                  = i40e_dev_filter_ctrl,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static int
 633 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 634         struct rte_pci_device *pci_dev)
 635 {
 636         char name[RTE_ETH_NAME_MAX_LEN];
 637         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 638         int i, retval;
 639
 640         if (pci_dev->device.devargs) {
 641                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 642                                 &eth_da);
 643                 if (retval)
 644                         return retval;
 645         }
 646
 647         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 648                 sizeof(struct i40e_adapter),
 649                 eth_dev_pci_specific_init, pci_dev,
 650                 eth_i40e_dev_init, NULL);
 651
 652         if (retval || eth_da.nb_representor_ports < 1)
 653                 return retval;
 654
 655         /* probe VF representor ports */
 656         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 657                 pci_dev->device.name);
 658
 659         if (pf_ethdev == NULL)
 660                 return -ENODEV;
 661
 662         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 663                 struct i40e_vf_representor representor = {
 664                         .vf_id = eth_da.representor_ports[i],
 665                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 666                                 pf_ethdev->data->dev_private)->switch_domain_id,
 667                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 668                                 pf_ethdev->data->dev_private)
 669                 };
 670
 671                 /* representor port net_bdf_port */
 672                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 673                         pci_dev->device.name, eth_da.representor_ports[i]);
 674
 675                 retval = rte_eth_dev_create(&pci_dev->device, name,
 676                         sizeof(struct i40e_vf_representor), NULL, NULL,
 677                         i40e_vf_representor_init, &representor);
 678
 679                 if (retval)
 680                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 681                                 "representor %s.", name);
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 688 {
 689         struct rte_eth_dev *ethdev;
 690
 691         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 692         if (!ethdev)
 693                 return -ENODEV;
 694
 695
 696         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 697                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 698         else
 699                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 700 }
 701
 702 static struct rte_pci_driver rte_i40e_pmd = {
 703         .id_table = pci_id_i40e_map,
 704         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 705                      RTE_PCI_DRV_IOVA_AS_VA,
 706         .probe = eth_i40e_pci_probe,
 707         .remove = eth_i40e_pci_remove,
 708 };
 709
 710 static inline void
 711 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 712                          uint32_t reg_val)
 713 {
 714         uint32_t ori_reg_val;
 715         struct rte_eth_dev *dev;
 716
 717         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 718         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 719         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 720         if (ori_reg_val != reg_val)
 721                 PMD_DRV_LOG(WARNING,
 722                             "i40e device %s changed global register [0x%08x]."
 723                             " original: 0x%08x, new: 0x%08x",
 724                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 725 }
 726
 727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737 #ifndef I40E_GLQF_L3_MAP
 738 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 739 #endif
 740
 741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 742 {
 743         /*
 744          * Initialize registers for parsing packet type of QinQ
 745          * This should be removed from code once proper
 746          * configuration API is added to avoid configuration conflicts
 747          * between ports of the same device.
 748          */
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 750         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 751 }
 752
 753 static inline void i40e_config_automask(struct i40e_pf *pf)
 754 {
 755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 756         uint32_t val;
 757
 758         /* INTENA flag is not auto-cleared for interrupt */
 759         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 760         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 761                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 762
 763         /* If support multi-driver, PF will use INT0. */
 764         if (!pf->support_multi_driver)
 765                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 766
 767         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 768 }
 769
 770 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 771
 772 /*
 773  * Add a ethertype filter to drop all flow control frames transmitted
 774  * from VSIs.
 775 */
 776 static void
 777 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 778 {
 779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 780         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 781                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 782                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 783         int ret;
 784
 785         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 786                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 787                                 pf->main_vsi_seid, 0,
 788                                 TRUE, NULL, NULL);
 789         if (ret)
 790                 PMD_INIT_LOG(ERR,
 791                         "Failed to add filter to drop flow control frames from VSIs.");
 792 }
 793
 794 static int
 795 floating_veb_list_handler(__rte_unused const char *key,
 796                           const char *floating_veb_value,
 797                           void *opaque)
 798 {
 799         int idx = 0;
 800         unsigned int count = 0;
 801         char *end = NULL;
 802         int min, max;
 803         bool *vf_floating_veb = opaque;
 804
 805         while (isblank(*floating_veb_value))
 806                 floating_veb_value++;
 807
 808         /* Reset floating VEB configuration for VFs */
 809         for (idx = 0; idx < I40E_MAX_VF; idx++)
 810                 vf_floating_veb[idx] = false;
 811
 812         min = I40E_MAX_VF;
 813         do {
 814                 while (isblank(*floating_veb_value))
 815                         floating_veb_value++;
 816                 if (*floating_veb_value == '\0')
 817                         return -1;
 818                 errno = 0;
 819                 idx = strtoul(floating_veb_value, &end, 10);
 820                 if (errno || end == NULL)
 821                         return -1;
 822                 while (isblank(*end))
 823                         end++;
 824                 if (*end == '-') {
 825                         min = idx;
 826                 } else if ((*end == ';') || (*end == '\0')) {
 827                         max = idx;
 828                         if (min == I40E_MAX_VF)
 829                                 min = idx;
 830                         if (max >= I40E_MAX_VF)
 831                                 max = I40E_MAX_VF - 1;
 832                         for (idx = min; idx <= max; idx++) {
 833                                 vf_floating_veb[idx] = true;
 834                                 count++;
 835                         }
 836                         min = I40E_MAX_VF;
 837                 } else {
 838                         return -1;
 839                 }
 840                 floating_veb_value = end + 1;
 841         } while (*end != '\0');
 842
 843         if (count == 0)
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 static void
 850 config_vf_floating_veb(struct rte_devargs *devargs,
 851                        uint16_t floating_veb,
 852                        bool *vf_floating_veb)
 853 {
 854         struct rte_kvargs *kvlist;
 855         int i;
 856         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 857
 858         if (!floating_veb)
 859                 return;
 860         /* All the VFs attach to the floating VEB by default
 861          * when the floating VEB is enabled.
 862          */
 863         for (i = 0; i < I40E_MAX_VF; i++)
 864                 vf_floating_veb[i] = true;
 865
 866         if (devargs == NULL)
 867                 return;
 868
 869         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 870         if (kvlist == NULL)
 871                 return;
 872
 873         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 874                 rte_kvargs_free(kvlist);
 875                 return;
 876         }
 877         /* When the floating_veb_list parameter exists, all the VFs
 878          * will attach to the legacy VEB firstly, then configure VFs
 879          * to the floating VEB according to the floating_veb_list.
 880          */
 881         if (rte_kvargs_process(kvlist, floating_veb_list,
 882                                floating_veb_list_handler,
 883                                vf_floating_veb) < 0) {
 884                 rte_kvargs_free(kvlist);
 885                 return;
 886         }
 887         rte_kvargs_free(kvlist);
 888 }
 889
 890 static int
 891 i40e_check_floating_handler(__rte_unused const char *key,
 892                             const char *value,
 893                             __rte_unused void *opaque)
 894 {
 895         if (strcmp(value, "1"))
 896                 return -1;
 897
 898         return 0;
 899 }
 900
 901 static int
 902 is_floating_veb_supported(struct rte_devargs *devargs)
 903 {
 904         struct rte_kvargs *kvlist;
 905         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 906
 907         if (devargs == NULL)
 908                 return 0;
 909
 910         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 911         if (kvlist == NULL)
 912                 return 0;
 913
 914         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 915                 rte_kvargs_free(kvlist);
 916                 return 0;
 917         }
 918         /* Floating VEB is enabled when there's key-value:
 919          * enable_floating_veb=1
 920          */
 921         if (rte_kvargs_process(kvlist, floating_veb_key,
 922                                i40e_check_floating_handler, NULL) < 0) {
 923                 rte_kvargs_free(kvlist);
 924                 return 0;
 925         }
 926         rte_kvargs_free(kvlist);
 927
 928         return 1;
 929 }
 930
 931 static void
 932 config_floating_veb(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937
 938         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 939
 940         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 941                 pf->floating_veb =
 942                         is_floating_veb_supported(pci_dev->device.devargs);
 943                 config_vf_floating_veb(pci_dev->device.devargs,
 944                                        pf->floating_veb,
 945                                        pf->floating_veb_list);
 946         } else {
 947                 pf->floating_veb = false;
 948         }
 949 }
 950
 951 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 952 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 953
 954 static int
 955 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 956 {
 957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 958         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 959         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 960         int ret;
 961
 962         struct rte_hash_parameters ethertype_hash_params = {
 963                 .name = ethertype_hash_name,
 964                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 965                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 966                 .hash_func = rte_hash_crc,
 967                 .hash_func_init_val = 0,
 968                 .socket_id = rte_socket_id(),
 969         };
 970
 971         /* Initialize ethertype filter rule list and hash */
 972         TAILQ_INIT(&ethertype_rule->ethertype_list);
 973         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 974                  "ethertype_%s", dev->device->name);
 975         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 976         if (!ethertype_rule->hash_table) {
 977                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 978                 return -EINVAL;
 979         }
 980         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 981                                        sizeof(struct i40e_ethertype_filter *) *
 982                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 983                                        0);
 984         if (!ethertype_rule->hash_map) {
 985                 PMD_INIT_LOG(ERR,
 986                              "Failed to allocate memory for ethertype hash map!");
 987                 ret = -ENOMEM;
 988                 goto err_ethertype_hash_map_alloc;
 989         }
 990
 991         return 0;
 992
 993 err_ethertype_hash_map_alloc:
 994         rte_hash_free(ethertype_rule->hash_table);
 995
 996         return ret;
 997 }
 998
 999 static int
1000 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1001 {
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1004         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005         int ret;
1006
1007         struct rte_hash_parameters tunnel_hash_params = {
1008                 .name = tunnel_hash_name,
1009                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1010                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1011                 .hash_func = rte_hash_crc,
1012                 .hash_func_init_val = 0,
1013                 .socket_id = rte_socket_id(),
1014         };
1015
1016         /* Initialize tunnel filter rule list and hash */
1017         TAILQ_INIT(&tunnel_rule->tunnel_list);
1018         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1019                  "tunnel_%s", dev->device->name);
1020         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1021         if (!tunnel_rule->hash_table) {
1022                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023                 return -EINVAL;
1024         }
1025         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1026                                     sizeof(struct i40e_tunnel_filter *) *
1027                                     I40E_MAX_TUNNEL_FILTER_NUM,
1028                                     0);
1029         if (!tunnel_rule->hash_map) {
1030                 PMD_INIT_LOG(ERR,
1031                              "Failed to allocate memory for tunnel hash map!");
1032                 ret = -ENOMEM;
1033                 goto err_tunnel_hash_map_alloc;
1034         }
1035
1036         return 0;
1037
1038 err_tunnel_hash_map_alloc:
1039         rte_hash_free(tunnel_rule->hash_table);
1040
1041         return ret;
1042 }
1043
1044 static int
1045 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_fdir_info *fdir_info = &pf->fdir;
1049         char fdir_hash_name[RTE_HASH_NAMESIZE];
1050         int ret;
1051
1052         struct rte_hash_parameters fdir_hash_params = {
1053                 .name = fdir_hash_name,
1054                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1055                 .key_len = sizeof(struct i40e_fdir_input),
1056                 .hash_func = rte_hash_crc,
1057                 .hash_func_init_val = 0,
1058                 .socket_id = rte_socket_id(),
1059         };
1060
1061         /* Initialize flow director filter rule list and hash */
1062         TAILQ_INIT(&fdir_info->fdir_list);
1063         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1064                  "fdir_%s", dev->device->name);
1065         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1066         if (!fdir_info->hash_table) {
1067                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068                 return -EINVAL;
1069         }
1070         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1071                                           sizeof(struct i40e_fdir_filter *) *
1072                                           I40E_MAX_FDIR_FILTER_NUM,
1073                                           0);
1074         if (!fdir_info->hash_map) {
1075                 PMD_INIT_LOG(ERR,
1076                              "Failed to allocate memory for fdir hash map!");
1077                 ret = -ENOMEM;
1078                 goto err_fdir_hash_map_alloc;
1079         }
1080         return 0;
1081
1082 err_fdir_hash_map_alloc:
1083         rte_hash_free(fdir_info->hash_table);
1084
1085         return ret;
1086 }
1087
1088 static void
1089 i40e_init_customized_info(struct i40e_pf *pf)
1090 {
1091         int i;
1092
1093         /* Initialize customized pctype */
1094         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1095                 pf->customized_pctype[i].index = i;
1096                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1097                 pf->customized_pctype[i].valid = false;
1098         }
1099
1100         pf->gtp_support = false;
1101 }
1102
1103 void
1104 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1105 {
1106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1108         struct i40e_queue_regions *info = &pf->queue_region;
1109         uint16_t i;
1110
1111         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1112                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1113
1114         memset(info, 0, sizeof(struct i40e_queue_regions));
1115 }
1116
1117 static int
1118 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1119                                const char *value,
1120                                void *opaque)
1121 {
1122         struct i40e_pf *pf;
1123         unsigned long support_multi_driver;
1124         char *end;
1125
1126         pf = (struct i40e_pf *)opaque;
1127
1128         errno = 0;
1129         support_multi_driver = strtoul(value, &end, 10);
1130         if (errno != 0 || end == value || *end != 0) {
1131                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1132                 return -(EINVAL);
1133         }
1134
1135         if (support_multi_driver == 1 || support_multi_driver == 0)
1136                 pf->support_multi_driver = (bool)support_multi_driver;
1137         else
1138                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1139                             "enable global configuration by default."
1140                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1141         return 0;
1142 }
1143
1144 static int
1145 i40e_support_multi_driver(struct rte_eth_dev *dev)
1146 {
1147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1148         struct rte_kvargs *kvlist;
1149         int kvargs_count;
1150
1151         /* Enable global configuration by default */
1152         pf->support_multi_driver = false;
1153
1154         if (!dev->device->devargs)
1155                 return 0;
1156
1157         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1158         if (!kvlist)
1159                 return -EINVAL;
1160
1161         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1162         if (!kvargs_count) {
1163                 rte_kvargs_free(kvlist);
1164                 return 0;
1165         }
1166
1167         if (kvargs_count > 1)
1168                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1169                             "the first invalid or last valid one is used !",
1170                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1171
1172         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1173                                i40e_parse_multi_drv_handler, pf) < 0) {
1174                 rte_kvargs_free(kvlist);
1175                 return -EINVAL;
1176         }
1177
1178         rte_kvargs_free(kvlist);
1179         return 0;
1180 }
1181
1182 static int
1183 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1184                                     uint32_t reg_addr, uint64_t reg_val,
1185                                     struct i40e_asq_cmd_details *cmd_details)
1186 {
1187         uint64_t ori_reg_val;
1188         struct rte_eth_dev *dev;
1189         int ret;
1190
1191         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1192         if (ret != I40E_SUCCESS) {
1193                 PMD_DRV_LOG(ERR,
1194                             "Fail to debug read from 0x%08x",
1195                             reg_addr);
1196                 return -EIO;
1197         }
1198         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1199
1200         if (ori_reg_val != reg_val)
1201                 PMD_DRV_LOG(WARNING,
1202                             "i40e device %s changed global register [0x%08x]."
1203                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1204                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1205
1206         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1207 }
1208
1209 static int
1210 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1211                                 const char *value,
1212                                 void *opaque)
1213 {
1214         struct i40e_adapter *ad;
1215         int use_latest_vec;
1216
1217         ad = (struct i40e_adapter *)opaque;
1218
1219         use_latest_vec = atoi(value);
1220
1221         if (use_latest_vec != 0 && use_latest_vec != 1)
1222                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1223
1224         ad->use_latest_vec = (uint8_t)use_latest_vec;
1225
1226         return 0;
1227 }
1228
1229 static int
1230 i40e_use_latest_vec(struct rte_eth_dev *dev)
1231 {
1232         struct i40e_adapter *ad =
1233                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1234         struct rte_kvargs *kvlist;
1235         int kvargs_count;
1236
1237         ad->use_latest_vec = false;
1238
1239         if (!dev->device->devargs)
1240                 return 0;
1241
1242         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1243         if (!kvlist)
1244                 return -EINVAL;
1245
1246         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1247         if (!kvargs_count) {
1248                 rte_kvargs_free(kvlist);
1249                 return 0;
1250         }
1251
1252         if (kvargs_count > 1)
1253                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1254                             "the first invalid or last valid one is used !",
1255                             ETH_I40E_USE_LATEST_VEC);
1256
1257         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1258                                 i40e_parse_latest_vec_handler, ad) < 0) {
1259                 rte_kvargs_free(kvlist);
1260                 return -EINVAL;
1261         }
1262
1263         rte_kvargs_free(kvlist);
1264         return 0;
1265 }
1266
1267 #define I40E_ALARM_INTERVAL 50000 /* us */
1268
1269 static int
1270 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1271 {
1272         struct rte_pci_device *pci_dev;
1273         struct rte_intr_handle *intr_handle;
1274         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1276         struct i40e_vsi *vsi;
1277         int ret;
1278         uint32_t len, val;
1279         uint8_t aq_fail = 0;
1280
1281         PMD_INIT_FUNC_TRACE();
1282
1283         dev->dev_ops = &i40e_eth_dev_ops;
1284         dev->rx_pkt_burst = i40e_recv_pkts;
1285         dev->tx_pkt_burst = i40e_xmit_pkts;
1286         dev->tx_pkt_prepare = i40e_prep_pkts;
1287
1288         /* for secondary processes, we don't initialise any further as primary
1289          * has already done this work. Only check we don't need a different
1290          * RX function */
1291         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1292                 i40e_set_rx_function(dev);
1293                 i40e_set_tx_function(dev);
1294                 return 0;
1295         }
1296         i40e_set_default_ptype_table(dev);
1297         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1298         intr_handle = &pci_dev->intr_handle;
1299
1300         rte_eth_copy_pci_info(dev, pci_dev);
1301
1302         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1303         pf->adapter->eth_dev = dev;
1304         pf->dev_data = dev->data;
1305
1306         hw->back = I40E_PF_TO_ADAPTER(pf);
1307         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308         if (!hw->hw_addr) {
1309                 PMD_INIT_LOG(ERR,
1310                         "Hardware is not available, as address is NULL");
1311                 return -ENODEV;
1312         }
1313
1314         hw->vendor_id = pci_dev->id.vendor_id;
1315         hw->device_id = pci_dev->id.device_id;
1316         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1317         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1318         hw->bus.device = pci_dev->addr.devid;
1319         hw->bus.func = pci_dev->addr.function;
1320         hw->adapter_stopped = 0;
1321         hw->adapter_closed = 0;
1322
1323         /*
1324          * Switch Tag value should not be identical to either the First Tag
1325          * or Second Tag values. So set something other than common Ethertype
1326          * for internal switching.
1327          */
1328         hw->switch_tag = 0xffff;
1329
1330         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1331         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1332                 PMD_INIT_LOG(ERR, "\nERROR: "
1333                         "Firmware recovery mode detected. Limiting functionality.\n"
1334                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1335                         "User Guide for details on firmware recovery mode.");
1336                 return -EIO;
1337         }
1338
1339         /* Check if need to support multi-driver */
1340         i40e_support_multi_driver(dev);
1341         /* Check if users want the latest supported vec path */
1342         i40e_use_latest_vec(dev);
1343
1344         /* Make sure all is clean before doing PF reset */
1345         i40e_clear_hw(hw);
1346
1347         /* Reset here to make sure all is clean for each PF */
1348         ret = i40e_pf_reset(hw);
1349         if (ret) {
1350                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1351                 return ret;
1352         }
1353
1354         /* Initialize the shared code (base driver) */
1355         ret = i40e_init_shared_code(hw);
1356         if (ret) {
1357                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1358                 return ret;
1359         }
1360
1361         /* Initialize the parameters for adminq */
1362         i40e_init_adminq_parameter(hw);
1363         ret = i40e_init_adminq(hw);
1364         if (ret != I40E_SUCCESS) {
1365                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1366                 return -EIO;
1367         }
1368         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1369                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1370                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1371                      ((hw->nvm.version >> 12) & 0xf),
1372                      ((hw->nvm.version >> 4) & 0xff),
1373                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1374
1375         /* Initialize the hardware */
1376         i40e_hw_init(dev);
1377
1378         i40e_config_automask(pf);
1379
1380         i40e_set_default_pctype_table(dev);
1381
1382         /*
1383          * To work around the NVM issue, initialize registers
1384          * for packet type of QinQ by software.
1385          * It should be removed once issues are fixed in NVM.
1386          */
1387         if (!pf->support_multi_driver)
1388                 i40e_GLQF_reg_init(hw);
1389
1390         /* Initialize the input set for filters (hash and fd) to default value */
1391         i40e_filter_input_set_init(pf);
1392
1393         /* initialise the L3_MAP register */
1394         if (!pf->support_multi_driver) {
1395                 ret = i40e_aq_debug_write_global_register(hw,
1396                                                    I40E_GLQF_L3_MAP(40),
1397                                                    0x00000028,  NULL);
1398                 if (ret)
1399                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1400                                      ret);
1401                 PMD_INIT_LOG(DEBUG,
1402                              "Global register 0x%08x is changed with 0x28",
1403                              I40E_GLQF_L3_MAP(40));
1404         }
1405
1406         /* Need the special FW version to support floating VEB */
1407         config_floating_veb(dev);
1408         /* Clear PXE mode */
1409         i40e_clear_pxe_mode(hw);
1410         i40e_dev_sync_phy_type(hw);
1411
1412         /*
1413          * On X710, performance number is far from the expectation on recent
1414          * firmware versions. The fix for this issue may not be integrated in
1415          * the following firmware version. So the workaround in software driver
1416          * is needed. It needs to modify the initial values of 3 internal only
1417          * registers. Note that the workaround can be removed when it is fixed
1418          * in firmware in the future.
1419          */
1420         i40e_configure_registers(hw);
1421
1422         /* Get hw capabilities */
1423         ret = i40e_get_cap(hw);
1424         if (ret != I40E_SUCCESS) {
1425                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1426                 goto err_get_capabilities;
1427         }
1428
1429         /* Initialize parameters for PF */
1430         ret = i40e_pf_parameter_init(dev);
1431         if (ret != 0) {
1432                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1433                 goto err_parameter_init;
1434         }
1435
1436         /* Initialize the queue management */
1437         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1438         if (ret < 0) {
1439                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1440                 goto err_qp_pool_init;
1441         }
1442         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1443                                 hw->func_caps.num_msix_vectors - 1);
1444         if (ret < 0) {
1445                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1446                 goto err_msix_pool_init;
1447         }
1448
1449         /* Initialize lan hmc */
1450         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1451                                 hw->func_caps.num_rx_qp, 0, 0);
1452         if (ret != I40E_SUCCESS) {
1453                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1454                 goto err_init_lan_hmc;
1455         }
1456
1457         /* Configure lan hmc */
1458         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1459         if (ret != I40E_SUCCESS) {
1460                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1461                 goto err_configure_lan_hmc;
1462         }
1463
1464         /* Get and check the mac address */
1465         i40e_get_mac_addr(hw, hw->mac.addr);
1466         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1467                 PMD_INIT_LOG(ERR, "mac address is not valid");
1468                 ret = -EIO;
1469                 goto err_get_mac_addr;
1470         }
1471         /* Copy the permanent MAC address */
1472         ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1473                         (struct rte_ether_addr *)hw->mac.perm_addr);
1474
1475         /* Disable flow control */
1476         hw->fc.requested_mode = I40E_FC_NONE;
1477         i40e_set_fc(hw, &aq_fail, TRUE);
1478
1479         /* Set the global registers with default ether type value */
1480         if (!pf->support_multi_driver) {
1481                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1482                                          ETHER_TYPE_VLAN);
1483                 if (ret != I40E_SUCCESS) {
1484                         PMD_INIT_LOG(ERR,
1485                                      "Failed to set the default outer "
1486                                      "VLAN ether type");
1487                         goto err_setup_pf_switch;
1488                 }
1489         }
1490
1491         /* PF setup, which includes VSI setup */
1492         ret = i40e_pf_setup(pf);
1493         if (ret) {
1494                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1495                 goto err_setup_pf_switch;
1496         }
1497
1498         vsi = pf->main_vsi;
1499
1500         /* Disable double vlan by default */
1501         i40e_vsi_config_double_vlan(vsi, FALSE);
1502
1503         /* Disable S-TAG identification when floating_veb is disabled */
1504         if (!pf->floating_veb) {
1505                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1506                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1507                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1508                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1509                 }
1510         }
1511
1512         if (!vsi->max_macaddrs)
1513                 len = ETHER_ADDR_LEN;
1514         else
1515                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1516
1517         /* Should be after VSI initialized */
1518         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1519         if (!dev->data->mac_addrs) {
1520                 PMD_INIT_LOG(ERR,
1521                         "Failed to allocated memory for storing mac address");
1522                 goto err_mac_alloc;
1523         }
1524         ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1525                                         &dev->data->mac_addrs[0]);
1526
1527         /* Init dcb to sw mode by default */
1528         ret = i40e_dcb_init_configure(dev, TRUE);
1529         if (ret != I40E_SUCCESS) {
1530                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1531                 pf->flags &= ~I40E_FLAG_DCB;
1532         }
1533         /* Update HW struct after DCB configuration */
1534         i40e_get_cap(hw);
1535
1536         /* initialize pf host driver to setup SRIOV resource if applicable */
1537         i40e_pf_host_init(dev);
1538
1539         /* register callback func to eal lib */
1540         rte_intr_callback_register(intr_handle,
1541                                    i40e_dev_interrupt_handler, dev);
1542
1543         /* configure and enable device interrupt */
1544         i40e_pf_config_irq0(hw, TRUE);
1545         i40e_pf_enable_irq0(hw);
1546
1547         /* enable uio intr after callback register */
1548         rte_intr_enable(intr_handle);
1549
1550         /* By default disable flexible payload in global configuration */
1551         if (!pf->support_multi_driver)
1552                 i40e_flex_payload_reg_set_default(hw);
1553
1554         /*
1555          * Add an ethertype filter to drop all flow control frames transmitted
1556          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1557          * frames to wire.
1558          */
1559         i40e_add_tx_flow_control_drop_filter(pf);
1560
1561         /* Set the max frame size to 0x2600 by default,
1562          * in case other drivers changed the default value.
1563          */
1564         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1565
1566         /* initialize mirror rule list */
1567         TAILQ_INIT(&pf->mirror_list);
1568
1569         /* initialize Traffic Manager configuration */
1570         i40e_tm_conf_init(dev);
1571
1572         /* Initialize customized information */
1573         i40e_init_customized_info(pf);
1574
1575         ret = i40e_init_ethtype_filter_list(dev);
1576         if (ret < 0)
1577                 goto err_init_ethtype_filter_list;
1578         ret = i40e_init_tunnel_filter_list(dev);
1579         if (ret < 0)
1580                 goto err_init_tunnel_filter_list;
1581         ret = i40e_init_fdir_filter_list(dev);
1582         if (ret < 0)
1583                 goto err_init_fdir_filter_list;
1584
1585         /* initialize queue region configuration */
1586         i40e_init_queue_region_conf(dev);
1587
1588         /* initialize rss configuration from rte_flow */
1589         memset(&pf->rss_info, 0,
1590                 sizeof(struct i40e_rte_flow_rss_conf));
1591
1592         /* reset all stats of the device, including pf and main vsi */
1593         i40e_dev_stats_reset(dev);
1594
1595         return 0;
1596
1597 err_init_fdir_filter_list:
1598         rte_free(pf->tunnel.hash_table);
1599         rte_free(pf->tunnel.hash_map);
1600 err_init_tunnel_filter_list:
1601         rte_free(pf->ethertype.hash_table);
1602         rte_free(pf->ethertype.hash_map);
1603 err_init_ethtype_filter_list:
1604         rte_free(dev->data->mac_addrs);
1605 err_mac_alloc:
1606         i40e_vsi_release(pf->main_vsi);
1607 err_setup_pf_switch:
1608 err_get_mac_addr:
1609 err_configure_lan_hmc:
1610         (void)i40e_shutdown_lan_hmc(hw);
1611 err_init_lan_hmc:
1612         i40e_res_pool_destroy(&pf->msix_pool);
1613 err_msix_pool_init:
1614         i40e_res_pool_destroy(&pf->qp_pool);
1615 err_qp_pool_init:
1616 err_parameter_init:
1617 err_get_capabilities:
1618         (void)i40e_shutdown_adminq(hw);
1619
1620         return ret;
1621 }
1622
1623 static void
1624 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1625 {
1626         struct i40e_ethertype_filter *p_ethertype;
1627         struct i40e_ethertype_rule *ethertype_rule;
1628
1629         ethertype_rule = &pf->ethertype;
1630         /* Remove all ethertype filter rules and hash */
1631         if (ethertype_rule->hash_map)
1632                 rte_free(ethertype_rule->hash_map);
1633         if (ethertype_rule->hash_table)
1634                 rte_hash_free(ethertype_rule->hash_table);
1635
1636         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1637                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1638                              p_ethertype, rules);
1639                 rte_free(p_ethertype);
1640         }
1641 }
1642
1643 static void
1644 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1645 {
1646         struct i40e_tunnel_filter *p_tunnel;
1647         struct i40e_tunnel_rule *tunnel_rule;
1648
1649         tunnel_rule = &pf->tunnel;
1650         /* Remove all tunnel director rules and hash */
1651         if (tunnel_rule->hash_map)
1652                 rte_free(tunnel_rule->hash_map);
1653         if (tunnel_rule->hash_table)
1654                 rte_hash_free(tunnel_rule->hash_table);
1655
1656         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1657                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1658                 rte_free(p_tunnel);
1659         }
1660 }
1661
1662 static void
1663 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1664 {
1665         struct i40e_fdir_filter *p_fdir;
1666         struct i40e_fdir_info *fdir_info;
1667
1668         fdir_info = &pf->fdir;
1669         /* Remove all flow director rules and hash */
1670         if (fdir_info->hash_map)
1671                 rte_free(fdir_info->hash_map);
1672         if (fdir_info->hash_table)
1673                 rte_hash_free(fdir_info->hash_table);
1674
1675         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1676                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1677                 rte_free(p_fdir);
1678         }
1679 }
1680
1681 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1682 {
1683         /*
1684          * Disable by default flexible payload
1685          * for corresponding L2/L3/L4 layers.
1686          */
1687         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1688         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1689         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 }
1691
1692 static int
1693 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1694 {
1695         struct i40e_pf *pf;
1696         struct rte_pci_device *pci_dev;
1697         struct rte_intr_handle *intr_handle;
1698         struct i40e_hw *hw;
1699         struct i40e_filter_control_settings settings;
1700         struct rte_flow *p_flow;
1701         int ret;
1702         uint8_t aq_fail = 0;
1703         int retries = 0;
1704
1705         PMD_INIT_FUNC_TRACE();
1706
1707         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1708                 return 0;
1709
1710         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1713         intr_handle = &pci_dev->intr_handle;
1714
1715         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1716         if (ret)
1717                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1718
1719         if (hw->adapter_closed == 0)
1720                 i40e_dev_close(dev);
1721
1722         dev->dev_ops = NULL;
1723         dev->rx_pkt_burst = NULL;
1724         dev->tx_pkt_burst = NULL;
1725
1726         /* Clear PXE mode */
1727         i40e_clear_pxe_mode(hw);
1728
1729         /* Unconfigure filter control */
1730         memset(&settings, 0, sizeof(settings));
1731         ret = i40e_set_filter_control(hw, &settings);
1732         if (ret)
1733                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1734                                         ret);
1735
1736         /* Disable flow control */
1737         hw->fc.requested_mode = I40E_FC_NONE;
1738         i40e_set_fc(hw, &aq_fail, TRUE);
1739
1740         /* uninitialize pf host driver */
1741         i40e_pf_host_uninit(dev);
1742
1743         /* disable uio intr before callback unregister */
1744         rte_intr_disable(intr_handle);
1745
1746         /* unregister callback func to eal lib */
1747         do {
1748                 ret = rte_intr_callback_unregister(intr_handle,
1749                                 i40e_dev_interrupt_handler, dev);
1750                 if (ret >= 0) {
1751                         break;
1752                 } else if (ret != -EAGAIN) {
1753                         PMD_INIT_LOG(ERR,
1754                                  "intr callback unregister failed: %d",
1755                                  ret);
1756                         return ret;
1757                 }
1758                 i40e_msec_delay(500);
1759         } while (retries++ < 5);
1760
1761         i40e_rm_ethtype_filter_list(pf);
1762         i40e_rm_tunnel_filter_list(pf);
1763         i40e_rm_fdir_filter_list(pf);
1764
1765         /* Remove all flows */
1766         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1767                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768                 rte_free(p_flow);
1769         }
1770
1771         /* Remove all Traffic Manager configuration */
1772         i40e_tm_conf_uninit(dev);
1773
1774         return 0;
1775 }
1776
1777 static int
1778 i40e_dev_configure(struct rte_eth_dev *dev)
1779 {
1780         struct i40e_adapter *ad =
1781                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1785         int i, ret;
1786
1787         ret = i40e_dev_sync_phy_type(hw);
1788         if (ret)
1789                 return ret;
1790
1791         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1792          * bulk allocation or vector Rx preconditions we will reset it.
1793          */
1794         ad->rx_bulk_alloc_allowed = true;
1795         ad->rx_vec_allowed = true;
1796         ad->tx_simple_allowed = true;
1797         ad->tx_vec_allowed = true;
1798
1799         /* Only legacy filter API needs the following fdir config. So when the
1800          * legacy filter API is deprecated, the following codes should also be
1801          * removed.
1802          */
1803         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1804                 ret = i40e_fdir_setup(pf);
1805                 if (ret != I40E_SUCCESS) {
1806                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1807                         return -ENOTSUP;
1808                 }
1809                 ret = i40e_fdir_configure(dev);
1810                 if (ret < 0) {
1811                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812                         goto err;
1813                 }
1814         } else
1815                 i40e_fdir_teardown(pf);
1816
1817         ret = i40e_dev_init_vlan(dev);
1818         if (ret < 0)
1819                 goto err;
1820
1821         /* VMDQ setup.
1822          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1823          *  RSS setting have different requirements.
1824          *  General PMD driver call sequence are NIC init, configure,
1825          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1826          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1827          *  applicable. So, VMDQ setting has to be done before
1828          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1829          *  For RSS setting, it will try to calculate actual configured RX queue
1830          *  number, which will be available after rx_queue_setup(). dev_start()
1831          *  function is good to place RSS setup.
1832          */
1833         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1834                 ret = i40e_vmdq_setup(dev);
1835                 if (ret)
1836                         goto err;
1837         }
1838
1839         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1840                 ret = i40e_dcb_setup(dev);
1841                 if (ret) {
1842                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1843                         goto err_dcb;
1844                 }
1845         }
1846
1847         TAILQ_INIT(&pf->flow_list);
1848
1849         return 0;
1850
1851 err_dcb:
1852         /* need to release vmdq resource if exists */
1853         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1854                 i40e_vsi_release(pf->vmdq[i].vsi);
1855                 pf->vmdq[i].vsi = NULL;
1856         }
1857         rte_free(pf->vmdq);
1858         pf->vmdq = NULL;
1859 err:
1860         /* Need to release fdir resource if exists.
1861          * Only legacy filter API needs the following fdir config. So when the
1862          * legacy filter API is deprecated, the following code should also be
1863          * removed.
1864          */
1865         i40e_fdir_teardown(pf);
1866         return ret;
1867 }
1868
1869 void
1870 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1871 {
1872         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1873         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1874         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1875         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1876         uint16_t msix_vect = vsi->msix_intr;
1877         uint16_t i;
1878
1879         for (i = 0; i < vsi->nb_qps; i++) {
1880                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1881                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882                 rte_wmb();
1883         }
1884
1885         if (vsi->type != I40E_VSI_SRIOV) {
1886                 if (!rte_intr_allow_others(intr_handle)) {
1887                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1888                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1889                         I40E_WRITE_REG(hw,
1890                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1891                                        0);
1892                 } else {
1893                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1894                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1895                         I40E_WRITE_REG(hw,
1896                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1897                                                        msix_vect - 1), 0);
1898                 }
1899         } else {
1900                 uint32_t reg;
1901                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1902                         vsi->user_param + (msix_vect - 1);
1903
1904                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1905                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1906         }
1907         I40E_WRITE_FLUSH(hw);
1908 }
1909
1910 static void
1911 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1912                        int base_queue, int nb_queue,
1913                        uint16_t itr_idx)
1914 {
1915         int i;
1916         uint32_t val;
1917         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1918         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1919
1920         /* Bind all RX queues to allocated MSIX interrupt */
1921         for (i = 0; i < nb_queue; i++) {
1922                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1923                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1924                         ((base_queue + i + 1) <<
1925                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1926                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1927                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1928
1929                 if (i == nb_queue - 1)
1930                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1931                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1932         }
1933
1934         /* Write first RX queue to Link list register as the head element */
1935         if (vsi->type != I40E_VSI_SRIOV) {
1936                 uint16_t interval =
1937                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1938
1939                 if (msix_vect == I40E_MISC_VEC_ID) {
1940                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1941                                        (base_queue <<
1942                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1943                                        (0x0 <<
1944                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1945                         I40E_WRITE_REG(hw,
1946                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1947                                        interval);
1948                 } else {
1949                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1950                                        (base_queue <<
1951                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1952                                        (0x0 <<
1953                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1954                         I40E_WRITE_REG(hw,
1955                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1956                                                        msix_vect - 1),
1957                                        interval);
1958                 }
1959         } else {
1960                 uint32_t reg;
1961
1962                 if (msix_vect == I40E_MISC_VEC_ID) {
1963                         I40E_WRITE_REG(hw,
1964                                        I40E_VPINT_LNKLST0(vsi->user_param),
1965                                        (base_queue <<
1966                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1967                                        (0x0 <<
1968                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1969                 } else {
1970                         /* num_msix_vectors_vf needs to minus irq0 */
1971                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1972                                 vsi->user_param + (msix_vect - 1);
1973
1974                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1975                                        (base_queue <<
1976                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1977                                        (0x0 <<
1978                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979                 }
1980         }
1981
1982         I40E_WRITE_FLUSH(hw);
1983 }
1984
1985 void
1986 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1987 {
1988         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1989         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1990         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1992         uint16_t msix_vect = vsi->msix_intr;
1993         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1994         uint16_t queue_idx = 0;
1995         int record = 0;
1996         int i;
1997
1998         for (i = 0; i < vsi->nb_qps; i++) {
1999                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2000                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2001         }
2002
2003         /* VF bind interrupt */
2004         if (vsi->type == I40E_VSI_SRIOV) {
2005                 __vsi_queues_bind_intr(vsi, msix_vect,
2006                                        vsi->base_queue, vsi->nb_qps,
2007                                        itr_idx);
2008                 return;
2009         }
2010
2011         /* PF & VMDq bind interrupt */
2012         if (rte_intr_dp_is_en(intr_handle)) {
2013                 if (vsi->type == I40E_VSI_MAIN) {
2014                         queue_idx = 0;
2015                         record = 1;
2016                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2017                         struct i40e_vsi *main_vsi =
2018                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2019                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2020                         record = 1;
2021                 }
2022         }
2023
2024         for (i = 0; i < vsi->nb_used_qps; i++) {
2025                 if (nb_msix <= 1) {
2026                         if (!rte_intr_allow_others(intr_handle))
2027                                 /* allow to share MISC_VEC_ID */
2028                                 msix_vect = I40E_MISC_VEC_ID;
2029
2030                         /* no enough msix_vect, map all to one */
2031                         __vsi_queues_bind_intr(vsi, msix_vect,
2032                                                vsi->base_queue + i,
2033                                                vsi->nb_used_qps - i,
2034                                                itr_idx);
2035                         for (; !!record && i < vsi->nb_used_qps; i++)
2036                                 intr_handle->intr_vec[queue_idx + i] =
2037                                         msix_vect;
2038                         break;
2039                 }
2040                 /* 1:1 queue/msix_vect mapping */
2041                 __vsi_queues_bind_intr(vsi, msix_vect,
2042                                        vsi->base_queue + i, 1,
2043                                        itr_idx);
2044                 if (!!record)
2045                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2046
2047                 msix_vect++;
2048                 nb_msix--;
2049         }
2050 }
2051
2052 static void
2053 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2054 {
2055         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2059         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2060         uint16_t msix_intr, i;
2061
2062         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2063                 for (i = 0; i < vsi->nb_msix; i++) {
2064                         msix_intr = vsi->msix_intr + i;
2065                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2066                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2067                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2068                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2069                 }
2070         else
2071                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2072                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2073                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2074                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2075
2076         I40E_WRITE_FLUSH(hw);
2077 }
2078
2079 static void
2080 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2081 {
2082         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2083         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2084         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2086         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2087         uint16_t msix_intr, i;
2088
2089         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2090                 for (i = 0; i < vsi->nb_msix; i++) {
2091                         msix_intr = vsi->msix_intr + i;
2092                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2093                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2094                 }
2095         else
2096                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2097                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2098
2099         I40E_WRITE_FLUSH(hw);
2100 }
2101
2102 static inline uint8_t
2103 i40e_parse_link_speeds(uint16_t link_speeds)
2104 {
2105         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2106
2107         if (link_speeds & ETH_LINK_SPEED_40G)
2108                 link_speed |= I40E_LINK_SPEED_40GB;
2109         if (link_speeds & ETH_LINK_SPEED_25G)
2110                 link_speed |= I40E_LINK_SPEED_25GB;
2111         if (link_speeds & ETH_LINK_SPEED_20G)
2112                 link_speed |= I40E_LINK_SPEED_20GB;
2113         if (link_speeds & ETH_LINK_SPEED_10G)
2114                 link_speed |= I40E_LINK_SPEED_10GB;
2115         if (link_speeds & ETH_LINK_SPEED_1G)
2116                 link_speed |= I40E_LINK_SPEED_1GB;
2117         if (link_speeds & ETH_LINK_SPEED_100M)
2118                 link_speed |= I40E_LINK_SPEED_100MB;
2119
2120         return link_speed;
2121 }
2122
2123 static int
2124 i40e_phy_conf_link(struct i40e_hw *hw,
2125                    uint8_t abilities,
2126                    uint8_t force_speed,
2127                    bool is_up)
2128 {
2129         enum i40e_status_code status;
2130         struct i40e_aq_get_phy_abilities_resp phy_ab;
2131         struct i40e_aq_set_phy_config phy_conf;
2132         enum i40e_aq_phy_type cnt;
2133         uint8_t avail_speed;
2134         uint32_t phy_type_mask = 0;
2135
2136         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2137                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2138                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2139                         I40E_AQ_PHY_FLAG_LOW_POWER;
2140         int ret = -ENOTSUP;
2141
2142         /* To get phy capabilities of available speeds. */
2143         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2144                                               NULL);
2145         if (status) {
2146                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147                                 status);
2148                 return ret;
2149         }
2150         avail_speed = phy_ab.link_speed;
2151
2152         /* To get the current phy config. */
2153         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2154                                               NULL);
2155         if (status) {
2156                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2157                                 status);
2158                 return ret;
2159         }
2160
2161         /* If link needs to go up and it is in autoneg mode the speed is OK,
2162          * no need to set up again.
2163          */
2164         if (is_up && phy_ab.phy_type != 0 &&
2165                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2166                      phy_ab.link_speed != 0)
2167                 return I40E_SUCCESS;
2168
2169         memset(&phy_conf, 0, sizeof(phy_conf));
2170
2171         /* bits 0-2 use the values from get_phy_abilities_resp */
2172         abilities &= ~mask;
2173         abilities |= phy_ab.abilities & mask;
2174
2175         phy_conf.abilities = abilities;
2176
2177         /* If link needs to go up, but the force speed is not supported,
2178          * Warn users and config the default available speeds.
2179          */
2180         if (is_up && !(force_speed & avail_speed)) {
2181                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2182                 phy_conf.link_speed = avail_speed;
2183         } else {
2184                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2185         }
2186
2187         /* PHY type mask needs to include each type except PHY type extension */
2188         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2189                 phy_type_mask |= 1 << cnt;
2190
2191         /* use get_phy_abilities_resp value for the rest */
2192         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2193         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2194                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2195                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2196         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2197         phy_conf.eee_capability = phy_ab.eee_capability;
2198         phy_conf.eeer = phy_ab.eeer_val;
2199         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2200
2201         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2202                     phy_ab.abilities, phy_ab.link_speed);
2203         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2204                     phy_conf.abilities, phy_conf.link_speed);
2205
2206         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207         if (status)
2208                 return ret;
2209
2210         return I40E_SUCCESS;
2211 }
2212
2213 static int
2214 i40e_apply_link_speed(struct rte_eth_dev *dev)
2215 {
2216         uint8_t speed;
2217         uint8_t abilities = 0;
2218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2219         struct rte_eth_conf *conf = &dev->data->dev_conf;
2220
2221         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2222                 conf->link_speeds = ETH_LINK_SPEED_40G |
2223                                     ETH_LINK_SPEED_25G |
2224                                     ETH_LINK_SPEED_20G |
2225                                     ETH_LINK_SPEED_10G |
2226                                     ETH_LINK_SPEED_1G |
2227                                     ETH_LINK_SPEED_100M;
2228         }
2229         speed = i40e_parse_link_speeds(conf->link_speeds);
2230         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2231                      I40E_AQ_PHY_AN_ENABLED |
2232                      I40E_AQ_PHY_LINK_ENABLED;
2233
2234         return i40e_phy_conf_link(hw, abilities, speed, true);
2235 }
2236
2237 static int
2238 i40e_dev_start(struct rte_eth_dev *dev)
2239 {
2240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         struct i40e_vsi *main_vsi = pf->main_vsi;
2243         int ret, i;
2244         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2245         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2246         uint32_t intr_vector = 0;
2247         struct i40e_vsi *vsi;
2248
2249         hw->adapter_stopped = 0;
2250
2251         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2252                 PMD_INIT_LOG(ERR,
2253                 "Invalid link_speeds for port %u, autonegotiation disabled",
2254                               dev->data->port_id);
2255                 return -EINVAL;
2256         }
2257
2258         rte_intr_disable(intr_handle);
2259
2260         if ((rte_intr_cap_multiple(intr_handle) ||
2261              !RTE_ETH_DEV_SRIOV(dev).active) &&
2262             dev->data->dev_conf.intr_conf.rxq != 0) {
2263                 intr_vector = dev->data->nb_rx_queues;
2264                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2265                 if (ret)
2266                         return ret;
2267         }
2268
2269         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2270                 intr_handle->intr_vec =
2271                         rte_zmalloc("intr_vec",
2272                                     dev->data->nb_rx_queues * sizeof(int),
2273                                     0);
2274                 if (!intr_handle->intr_vec) {
2275                         PMD_INIT_LOG(ERR,
2276                                 "Failed to allocate %d rx_queues intr_vec",
2277                                 dev->data->nb_rx_queues);
2278                         return -ENOMEM;
2279                 }
2280         }
2281
2282         /* Initialize VSI */
2283         ret = i40e_dev_rxtx_init(pf);
2284         if (ret != I40E_SUCCESS) {
2285                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286                 goto err_up;
2287         }
2288
2289         /* Map queues with MSIX interrupt */
2290         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2291                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2292         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2293         i40e_vsi_enable_queues_intr(main_vsi);
2294
2295         /* Map VMDQ VSI queues with MSIX interrupt */
2296         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2297                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2298                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2299                                           I40E_ITR_INDEX_DEFAULT);
2300                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2301         }
2302
2303         /* enable FDIR MSIX interrupt */
2304         if (pf->fdir.fdir_vsi) {
2305                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2306                                           I40E_ITR_INDEX_NONE);
2307                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2308         }
2309
2310         /* Enable all queues which have been configured */
2311         ret = i40e_dev_switch_queues(pf, TRUE);
2312         if (ret != I40E_SUCCESS) {
2313                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314                 goto err_up;
2315         }
2316
2317         /* Enable receiving broadcast packets */
2318         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2319         if (ret != I40E_SUCCESS)
2320                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2321
2322         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2323                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2324                                                 true, NULL);
2325                 if (ret != I40E_SUCCESS)
2326                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2327         }
2328
2329         /* Enable the VLAN promiscuous mode. */
2330         if (pf->vfs) {
2331                 for (i = 0; i < pf->vf_num; i++) {
2332                         vsi = pf->vfs[i].vsi;
2333                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2334                                                      true, NULL);
2335                 }
2336         }
2337
2338         /* Enable mac loopback mode */
2339         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2340             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2341                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2342                 if (ret != I40E_SUCCESS) {
2343                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2344                         goto err_up;
2345                 }
2346         }
2347
2348         /* Apply link configure */
2349         ret = i40e_apply_link_speed(dev);
2350         if (I40E_SUCCESS != ret) {
2351                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352                 goto err_up;
2353         }
2354
2355         if (!rte_intr_allow_others(intr_handle)) {
2356                 rte_intr_callback_unregister(intr_handle,
2357                                              i40e_dev_interrupt_handler,
2358                                              (void *)dev);
2359                 /* configure and enable device interrupt */
2360                 i40e_pf_config_irq0(hw, FALSE);
2361                 i40e_pf_enable_irq0(hw);
2362
2363                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2364                         PMD_INIT_LOG(INFO,
2365                                 "lsc won't enable because of no intr multiplex");
2366         } else {
2367                 ret = i40e_aq_set_phy_int_mask(hw,
2368                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2369                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2370                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2371                 if (ret != I40E_SUCCESS)
2372                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2373
2374                 /* Call get_link_info aq commond to enable/disable LSE */
2375                 i40e_dev_link_update(dev, 0);
2376         }
2377
2378         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2379                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2380                                   i40e_dev_alarm_handler, dev);
2381         } else {
2382                 /* enable uio intr after callback register */
2383                 rte_intr_enable(intr_handle);
2384         }
2385
2386         i40e_filter_restore(pf);
2387
2388         if (pf->tm_conf.root && !pf->tm_conf.committed)
2389                 PMD_DRV_LOG(WARNING,
2390                             "please call hierarchy_commit() "
2391                             "before starting the port");
2392
2393         return I40E_SUCCESS;
2394
2395 err_up:
2396         i40e_dev_switch_queues(pf, FALSE);
2397         i40e_dev_clear_queues(dev);
2398
2399         return ret;
2400 }
2401
2402 static void
2403 i40e_dev_stop(struct rte_eth_dev *dev)
2404 {
2405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2407         struct i40e_vsi *main_vsi = pf->main_vsi;
2408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2409         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2410         int i;
2411
2412         if (hw->adapter_stopped == 1)
2413                 return;
2414
2415         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2416                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2417                 rte_intr_enable(intr_handle);
2418         }
2419
2420         /* Disable all queues */
2421         i40e_dev_switch_queues(pf, FALSE);
2422
2423         /* un-map queues with interrupt registers */
2424         i40e_vsi_disable_queues_intr(main_vsi);
2425         i40e_vsi_queues_unbind_intr(main_vsi);
2426
2427         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2428                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2429                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2430         }
2431
2432         if (pf->fdir.fdir_vsi) {
2433                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2434                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2435         }
2436         /* Clear all queues and release memory */
2437         i40e_dev_clear_queues(dev);
2438
2439         /* Set link down */
2440         i40e_dev_set_link_down(dev);
2441
2442         if (!rte_intr_allow_others(intr_handle))
2443                 /* resume to the default handler */
2444                 rte_intr_callback_register(intr_handle,
2445                                            i40e_dev_interrupt_handler,
2446                                            (void *)dev);
2447
2448         /* Clean datapath event and queue/vec mapping */
2449         rte_intr_efd_disable(intr_handle);
2450         if (intr_handle->intr_vec) {
2451                 rte_free(intr_handle->intr_vec);
2452                 intr_handle->intr_vec = NULL;
2453         }
2454
2455         /* reset hierarchy commit */
2456         pf->tm_conf.committed = false;
2457
2458         hw->adapter_stopped = 1;
2459
2460         pf->adapter->rss_reta_updated = 0;
2461 }
2462
2463 static void
2464 i40e_dev_close(struct rte_eth_dev *dev)
2465 {
2466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2468         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2469         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2470         struct i40e_mirror_rule *p_mirror;
2471         uint32_t reg;
2472         int i;
2473         int ret;
2474
2475         PMD_INIT_FUNC_TRACE();
2476
2477         i40e_dev_stop(dev);
2478
2479         /* Remove all mirror rules */
2480         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2481                 ret = i40e_aq_del_mirror_rule(hw,
2482                                               pf->main_vsi->veb->seid,
2483                                               p_mirror->rule_type,
2484                                               p_mirror->entries,
2485                                               p_mirror->num_entries,
2486                                               p_mirror->id);
2487                 if (ret < 0)
2488                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2489                                     "status = %d, aq_err = %d.", ret,
2490                                     hw->aq.asq_last_status);
2491
2492                 /* remove mirror software resource anyway */
2493                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2494                 rte_free(p_mirror);
2495                 pf->nb_mirror_rule--;
2496         }
2497
2498         i40e_dev_free_queues(dev);
2499
2500         /* Disable interrupt */
2501         i40e_pf_disable_irq0(hw);
2502         rte_intr_disable(intr_handle);
2503
2504         /*
2505          * Only legacy filter API needs the following fdir config. So when the
2506          * legacy filter API is deprecated, the following code should also be
2507          * removed.
2508          */
2509         i40e_fdir_teardown(pf);
2510
2511         /* shutdown and destroy the HMC */
2512         i40e_shutdown_lan_hmc(hw);
2513
2514         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2515                 i40e_vsi_release(pf->vmdq[i].vsi);
2516                 pf->vmdq[i].vsi = NULL;
2517         }
2518         rte_free(pf->vmdq);
2519         pf->vmdq = NULL;
2520
2521         /* release all the existing VSIs and VEBs */
2522         i40e_vsi_release(pf->main_vsi);
2523
2524         /* shutdown the adminq */
2525         i40e_aq_queue_shutdown(hw, true);
2526         i40e_shutdown_adminq(hw);
2527
2528         i40e_res_pool_destroy(&pf->qp_pool);
2529         i40e_res_pool_destroy(&pf->msix_pool);
2530
2531         /* Disable flexible payload in global configuration */
2532         if (!pf->support_multi_driver)
2533                 i40e_flex_payload_reg_set_default(hw);
2534
2535         /* force a PF reset to clean anything leftover */
2536         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2537         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2538                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2539         I40E_WRITE_FLUSH(hw);
2540
2541         hw->adapter_closed = 1;
2542 }
2543
2544 /*
2545  * Reset PF device only to re-initialize resources in PMD layer
2546  */
2547 static int
2548 i40e_dev_reset(struct rte_eth_dev *dev)
2549 {
2550         int ret;
2551
2552         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2553          * its VF to make them align with it. The detailed notification
2554          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2555          * To avoid unexpected behavior in VF, currently reset of PF with
2556          * SR-IOV activation is not supported. It might be supported later.
2557          */
2558         if (dev->data->sriov.active)
2559                 return -ENOTSUP;
2560
2561         ret = eth_i40e_dev_uninit(dev);
2562         if (ret)
2563                 return ret;
2564
2565         ret = eth_i40e_dev_init(dev, NULL);
2566
2567         return ret;
2568 }
2569
2570 static void
2571 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2572 {
2573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         struct i40e_vsi *vsi = pf->main_vsi;
2576         int status;
2577
2578         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2579                                                      true, NULL, true);
2580         if (status != I40E_SUCCESS)
2581                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2582
2583         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2584                                                         TRUE, NULL);
2585         if (status != I40E_SUCCESS)
2586                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2587
2588 }
2589
2590 static void
2591 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2592 {
2593         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2595         struct i40e_vsi *vsi = pf->main_vsi;
2596         int status;
2597
2598         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2599                                                      false, NULL, true);
2600         if (status != I40E_SUCCESS)
2601                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2602
2603         /* must remain in all_multicast mode */
2604         if (dev->data->all_multicast == 1)
2605                 return;
2606
2607         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2608                                                         false, NULL);
2609         if (status != I40E_SUCCESS)
2610                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2611 }
2612
2613 static void
2614 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2615 {
2616         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2618         struct i40e_vsi *vsi = pf->main_vsi;
2619         int ret;
2620
2621         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2622         if (ret != I40E_SUCCESS)
2623                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2624 }
2625
2626 static void
2627 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2628 {
2629         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         struct i40e_vsi *vsi = pf->main_vsi;
2632         int ret;
2633
2634         if (dev->data->promiscuous == 1)
2635                 return; /* must remain in all_multicast mode */
2636
2637         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2638                                 vsi->seid, FALSE, NULL);
2639         if (ret != I40E_SUCCESS)
2640                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2641 }
2642
2643 /*
2644  * Set device link up.
2645  */
2646 static int
2647 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2648 {
2649         /* re-apply link speed setting */
2650         return i40e_apply_link_speed(dev);
2651 }
2652
2653 /*
2654  * Set device link down.
2655  */
2656 static int
2657 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2658 {
2659         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2660         uint8_t abilities = 0;
2661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2662
2663         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2664         return i40e_phy_conf_link(hw, abilities, speed, false);
2665 }
2666
2667 static __rte_always_inline void
2668 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2669 {
2670 /* Link status registers and values*/
2671 #define I40E_PRTMAC_LINKSTA             0x001E2420
2672 #define I40E_REG_LINK_UP                0x40000080
2673 #define I40E_PRTMAC_MACC                0x001E24E0
2674 #define I40E_REG_MACC_25GB              0x00020000
2675 #define I40E_REG_SPEED_MASK             0x38000000
2676 #define I40E_REG_SPEED_0                0x00000000
2677 #define I40E_REG_SPEED_1                0x08000000
2678 #define I40E_REG_SPEED_2                0x10000000
2679 #define I40E_REG_SPEED_3                0x18000000
2680 #define I40E_REG_SPEED_4                0x20000000
2681         uint32_t link_speed;
2682         uint32_t reg_val;
2683
2684         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2685         link_speed = reg_val & I40E_REG_SPEED_MASK;
2686         reg_val &= I40E_REG_LINK_UP;
2687         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2688
2689         if (unlikely(link->link_status == 0))
2690                 return;
2691
2692         /* Parse the link status */
2693         switch (link_speed) {
2694         case I40E_REG_SPEED_0:
2695                 link->link_speed = ETH_SPEED_NUM_100M;
2696                 break;
2697         case I40E_REG_SPEED_1:
2698                 link->link_speed = ETH_SPEED_NUM_1G;
2699                 break;
2700         case I40E_REG_SPEED_2:
2701                 if (hw->mac.type == I40E_MAC_X722)
2702                         link->link_speed = ETH_SPEED_NUM_2_5G;
2703                 else
2704                         link->link_speed = ETH_SPEED_NUM_10G;
2705                 break;
2706         case I40E_REG_SPEED_3:
2707                 if (hw->mac.type == I40E_MAC_X722) {
2708                         link->link_speed = ETH_SPEED_NUM_5G;
2709                 } else {
2710                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2711
2712                         if (reg_val & I40E_REG_MACC_25GB)
2713                                 link->link_speed = ETH_SPEED_NUM_25G;
2714                         else
2715                                 link->link_speed = ETH_SPEED_NUM_40G;
2716                 }
2717                 break;
2718         case I40E_REG_SPEED_4:
2719                 if (hw->mac.type == I40E_MAC_X722)
2720                         link->link_speed = ETH_SPEED_NUM_10G;
2721                 else
2722                         link->link_speed = ETH_SPEED_NUM_20G;
2723                 break;
2724         default:
2725                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2726                 break;
2727         }
2728 }
2729
2730 static __rte_always_inline void
2731 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2732         bool enable_lse, int wait_to_complete)
2733 {
2734 #define CHECK_INTERVAL             100  /* 100ms */
2735 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2736         uint32_t rep_cnt = MAX_REPEAT_TIME;
2737         struct i40e_link_status link_status;
2738         int status;
2739
2740         memset(&link_status, 0, sizeof(link_status));
2741
2742         do {
2743                 memset(&link_status, 0, sizeof(link_status));
2744
2745                 /* Get link status information from hardware */
2746                 status = i40e_aq_get_link_info(hw, enable_lse,
2747                                                 &link_status, NULL);
2748                 if (unlikely(status != I40E_SUCCESS)) {
2749                         link->link_speed = ETH_SPEED_NUM_100M;
2750                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2751                         PMD_DRV_LOG(ERR, "Failed to get link info");
2752                         return;
2753                 }
2754
2755                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2756                 if (!wait_to_complete || link->link_status)
2757                         break;
2758
2759                 rte_delay_ms(CHECK_INTERVAL);
2760         } while (--rep_cnt);
2761
2762         /* Parse the link status */
2763         switch (link_status.link_speed) {
2764         case I40E_LINK_SPEED_100MB:
2765                 link->link_speed = ETH_SPEED_NUM_100M;
2766                 break;
2767         case I40E_LINK_SPEED_1GB:
2768                 link->link_speed = ETH_SPEED_NUM_1G;
2769                 break;
2770         case I40E_LINK_SPEED_10GB:
2771                 link->link_speed = ETH_SPEED_NUM_10G;
2772                 break;
2773         case I40E_LINK_SPEED_20GB:
2774                 link->link_speed = ETH_SPEED_NUM_20G;
2775                 break;
2776         case I40E_LINK_SPEED_25GB:
2777                 link->link_speed = ETH_SPEED_NUM_25G;
2778                 break;
2779         case I40E_LINK_SPEED_40GB:
2780                 link->link_speed = ETH_SPEED_NUM_40G;
2781                 break;
2782         default:
2783                 link->link_speed = ETH_SPEED_NUM_100M;
2784                 break;
2785         }
2786 }
2787
2788 int
2789 i40e_dev_link_update(struct rte_eth_dev *dev,
2790                      int wait_to_complete)
2791 {
2792         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2793         struct rte_eth_link link;
2794         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2795         int ret;
2796
2797         memset(&link, 0, sizeof(link));
2798
2799         /* i40e uses full duplex only */
2800         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2801         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2802                         ETH_LINK_SPEED_FIXED);
2803
2804         if (!wait_to_complete && !enable_lse)
2805                 update_link_reg(hw, &link);
2806         else
2807                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2808
2809         ret = rte_eth_linkstatus_set(dev, &link);
2810         i40e_notify_all_vfs_link_status(dev);
2811
2812         return ret;
2813 }
2814
2815 /* Get all the statistics of a VSI */
2816 void
2817 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2818 {
2819         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2820         struct i40e_eth_stats *nes = &vsi->eth_stats;
2821         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2822         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2823
2824         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2825                             vsi->offset_loaded, &oes->rx_bytes,
2826                             &nes->rx_bytes);
2827         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2828                             vsi->offset_loaded, &oes->rx_unicast,
2829                             &nes->rx_unicast);
2830         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2831                             vsi->offset_loaded, &oes->rx_multicast,
2832                             &nes->rx_multicast);
2833         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2834                             vsi->offset_loaded, &oes->rx_broadcast,
2835                             &nes->rx_broadcast);
2836         /* exclude CRC bytes */
2837         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2838                 nes->rx_broadcast) * ETHER_CRC_LEN;
2839
2840         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2841                             &oes->rx_discards, &nes->rx_discards);
2842         /* GLV_REPC not supported */
2843         /* GLV_RMPC not supported */
2844         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2845                             &oes->rx_unknown_protocol,
2846                             &nes->rx_unknown_protocol);
2847         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2848                             vsi->offset_loaded, &oes->tx_bytes,
2849                             &nes->tx_bytes);
2850         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2851                             vsi->offset_loaded, &oes->tx_unicast,
2852                             &nes->tx_unicast);
2853         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2854                             vsi->offset_loaded, &oes->tx_multicast,
2855                             &nes->tx_multicast);
2856         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2857                             vsi->offset_loaded,  &oes->tx_broadcast,
2858                             &nes->tx_broadcast);
2859         /* GLV_TDPC not supported */
2860         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2861                             &oes->tx_errors, &nes->tx_errors);
2862         vsi->offset_loaded = true;
2863
2864         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2865                     vsi->vsi_id);
2866         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2867         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2868         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2869         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2870         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2871         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2872                     nes->rx_unknown_protocol);
2873         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2874         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2875         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2876         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2877         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2878         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2879         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2880                     vsi->vsi_id);
2881 }
2882
2883 static void
2884 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2885 {
2886         unsigned int i;
2887         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2888         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2889
2890         /* Get rx/tx bytes of internal transfer packets */
2891         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2892                         I40E_GLV_GORCL(hw->port),
2893                         pf->offset_loaded,
2894                         &pf->internal_stats_offset.rx_bytes,
2895                         &pf->internal_stats.rx_bytes);
2896
2897         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2898                         I40E_GLV_GOTCL(hw->port),
2899                         pf->offset_loaded,
2900                         &pf->internal_stats_offset.tx_bytes,
2901                         &pf->internal_stats.tx_bytes);
2902         /* Get total internal rx packet count */
2903         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2904                             I40E_GLV_UPRCL(hw->port),
2905                             pf->offset_loaded,
2906                             &pf->internal_stats_offset.rx_unicast,
2907                             &pf->internal_stats.rx_unicast);
2908         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2909                             I40E_GLV_MPRCL(hw->port),
2910                             pf->offset_loaded,
2911                             &pf->internal_stats_offset.rx_multicast,
2912                             &pf->internal_stats.rx_multicast);
2913         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2914                             I40E_GLV_BPRCL(hw->port),
2915                             pf->offset_loaded,
2916                             &pf->internal_stats_offset.rx_broadcast,
2917                             &pf->internal_stats.rx_broadcast);
2918         /* Get total internal tx packet count */
2919         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2920                             I40E_GLV_UPTCL(hw->port),
2921                             pf->offset_loaded,
2922                             &pf->internal_stats_offset.tx_unicast,
2923                             &pf->internal_stats.tx_unicast);
2924         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2925                             I40E_GLV_MPTCL(hw->port),
2926                             pf->offset_loaded,
2927                             &pf->internal_stats_offset.tx_multicast,
2928                             &pf->internal_stats.tx_multicast);
2929         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2930                             I40E_GLV_BPTCL(hw->port),
2931                             pf->offset_loaded,
2932                             &pf->internal_stats_offset.tx_broadcast,
2933                             &pf->internal_stats.tx_broadcast);
2934
2935         /* exclude CRC size */
2936         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2937                 pf->internal_stats.rx_multicast +
2938                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2939
2940         /* Get statistics of struct i40e_eth_stats */
2941         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2942                             I40E_GLPRT_GORCL(hw->port),
2943                             pf->offset_loaded, &os->eth.rx_bytes,
2944                             &ns->eth.rx_bytes);
2945         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2946                             I40E_GLPRT_UPRCL(hw->port),
2947                             pf->offset_loaded, &os->eth.rx_unicast,
2948                             &ns->eth.rx_unicast);
2949         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2950                             I40E_GLPRT_MPRCL(hw->port),
2951                             pf->offset_loaded, &os->eth.rx_multicast,
2952                             &ns->eth.rx_multicast);
2953         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2954                             I40E_GLPRT_BPRCL(hw->port),
2955                             pf->offset_loaded, &os->eth.rx_broadcast,
2956                             &ns->eth.rx_broadcast);
2957         /* Workaround: CRC size should not be included in byte statistics,
2958          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2959          */
2960         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2961                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2962
2963         /* exclude internal rx bytes
2964          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2965          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2966          * value.
2967          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2968          */
2969         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2970                 ns->eth.rx_bytes = 0;
2971         else
2972                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2973
2974         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2975                 ns->eth.rx_unicast = 0;
2976         else
2977                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2978
2979         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2980                 ns->eth.rx_multicast = 0;
2981         else
2982                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2983
2984         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2985                 ns->eth.rx_broadcast = 0;
2986         else
2987                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2988
2989         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2990                             pf->offset_loaded, &os->eth.rx_discards,
2991                             &ns->eth.rx_discards);
2992         /* GLPRT_REPC not supported */
2993         /* GLPRT_RMPC not supported */
2994         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2995                             pf->offset_loaded,
2996                             &os->eth.rx_unknown_protocol,
2997                             &ns->eth.rx_unknown_protocol);
2998         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2999                             I40E_GLPRT_GOTCL(hw->port),
3000                             pf->offset_loaded, &os->eth.tx_bytes,
3001                             &ns->eth.tx_bytes);
3002         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3003                             I40E_GLPRT_UPTCL(hw->port),
3004                             pf->offset_loaded, &os->eth.tx_unicast,
3005                             &ns->eth.tx_unicast);
3006         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3007                             I40E_GLPRT_MPTCL(hw->port),
3008                             pf->offset_loaded, &os->eth.tx_multicast,
3009                             &ns->eth.tx_multicast);
3010         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3011                             I40E_GLPRT_BPTCL(hw->port),
3012                             pf->offset_loaded, &os->eth.tx_broadcast,
3013                             &ns->eth.tx_broadcast);
3014         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3015                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3016
3017         /* exclude internal tx bytes
3018          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3019          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3020          * value.
3021          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3022          */
3023         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3024                 ns->eth.tx_bytes = 0;
3025         else
3026                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3027
3028         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3029                 ns->eth.tx_unicast = 0;
3030         else
3031                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3032
3033         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3034                 ns->eth.tx_multicast = 0;
3035         else
3036                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3037
3038         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3039                 ns->eth.tx_broadcast = 0;
3040         else
3041                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3042
3043         /* GLPRT_TEPC not supported */
3044
3045         /* additional port specific stats */
3046         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3047                             pf->offset_loaded, &os->tx_dropped_link_down,
3048                             &ns->tx_dropped_link_down);
3049         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3050                             pf->offset_loaded, &os->crc_errors,
3051                             &ns->crc_errors);
3052         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3053                             pf->offset_loaded, &os->illegal_bytes,
3054                             &ns->illegal_bytes);
3055         /* GLPRT_ERRBC not supported */
3056         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3057                             pf->offset_loaded, &os->mac_local_faults,
3058                             &ns->mac_local_faults);
3059         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3060                             pf->offset_loaded, &os->mac_remote_faults,
3061                             &ns->mac_remote_faults);
3062         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3063                             pf->offset_loaded, &os->rx_length_errors,
3064                             &ns->rx_length_errors);
3065         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3066                             pf->offset_loaded, &os->link_xon_rx,
3067                             &ns->link_xon_rx);
3068         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3069                             pf->offset_loaded, &os->link_xoff_rx,
3070                             &ns->link_xoff_rx);
3071         for (i = 0; i < 8; i++) {
3072                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3073                                     pf->offset_loaded,
3074                                     &os->priority_xon_rx[i],
3075                                     &ns->priority_xon_rx[i]);
3076                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3077                                     pf->offset_loaded,
3078                                     &os->priority_xoff_rx[i],
3079                                     &ns->priority_xoff_rx[i]);
3080         }
3081         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3082                             pf->offset_loaded, &os->link_xon_tx,
3083                             &ns->link_xon_tx);
3084         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3085                             pf->offset_loaded, &os->link_xoff_tx,
3086                             &ns->link_xoff_tx);
3087         for (i = 0; i < 8; i++) {
3088                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3089                                     pf->offset_loaded,
3090                                     &os->priority_xon_tx[i],
3091                                     &ns->priority_xon_tx[i]);
3092                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3093                                     pf->offset_loaded,
3094                                     &os->priority_xoff_tx[i],
3095                                     &ns->priority_xoff_tx[i]);
3096                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3097                                     pf->offset_loaded,
3098                                     &os->priority_xon_2_xoff[i],
3099                                     &ns->priority_xon_2_xoff[i]);
3100         }
3101         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3102                             I40E_GLPRT_PRC64L(hw->port),
3103                             pf->offset_loaded, &os->rx_size_64,
3104                             &ns->rx_size_64);
3105         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3106                             I40E_GLPRT_PRC127L(hw->port),
3107                             pf->offset_loaded, &os->rx_size_127,
3108                             &ns->rx_size_127);
3109         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3110                             I40E_GLPRT_PRC255L(hw->port),
3111                             pf->offset_loaded, &os->rx_size_255,
3112                             &ns->rx_size_255);
3113         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3114                             I40E_GLPRT_PRC511L(hw->port),
3115                             pf->offset_loaded, &os->rx_size_511,
3116                             &ns->rx_size_511);
3117         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3118                             I40E_GLPRT_PRC1023L(hw->port),
3119                             pf->offset_loaded, &os->rx_size_1023,
3120                             &ns->rx_size_1023);
3121         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3122                             I40E_GLPRT_PRC1522L(hw->port),
3123                             pf->offset_loaded, &os->rx_size_1522,
3124                             &ns->rx_size_1522);
3125         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3126                             I40E_GLPRT_PRC9522L(hw->port),
3127                             pf->offset_loaded, &os->rx_size_big,
3128                             &ns->rx_size_big);
3129         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3130                             pf->offset_loaded, &os->rx_undersize,
3131                             &ns->rx_undersize);
3132         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3133                             pf->offset_loaded, &os->rx_fragments,
3134                             &ns->rx_fragments);
3135         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3136                             pf->offset_loaded, &os->rx_oversize,
3137                             &ns->rx_oversize);
3138         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3139                             pf->offset_loaded, &os->rx_jabber,
3140                             &ns->rx_jabber);
3141         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3142                             I40E_GLPRT_PTC64L(hw->port),
3143                             pf->offset_loaded, &os->tx_size_64,
3144                             &ns->tx_size_64);
3145         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3146                             I40E_GLPRT_PTC127L(hw->port),
3147                             pf->offset_loaded, &os->tx_size_127,
3148                             &ns->tx_size_127);
3149         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3150                             I40E_GLPRT_PTC255L(hw->port),
3151                             pf->offset_loaded, &os->tx_size_255,
3152                             &ns->tx_size_255);
3153         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3154                             I40E_GLPRT_PTC511L(hw->port),
3155                             pf->offset_loaded, &os->tx_size_511,
3156                             &ns->tx_size_511);
3157         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3158                             I40E_GLPRT_PTC1023L(hw->port),
3159                             pf->offset_loaded, &os->tx_size_1023,
3160                             &ns->tx_size_1023);
3161         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3162                             I40E_GLPRT_PTC1522L(hw->port),
3163                             pf->offset_loaded, &os->tx_size_1522,
3164                             &ns->tx_size_1522);
3165         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3166                             I40E_GLPRT_PTC9522L(hw->port),
3167                             pf->offset_loaded, &os->tx_size_big,
3168                             &ns->tx_size_big);
3169         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3170                            pf->offset_loaded,
3171                            &os->fd_sb_match, &ns->fd_sb_match);
3172         /* GLPRT_MSPDC not supported */
3173         /* GLPRT_XEC not supported */
3174
3175         pf->offset_loaded = true;
3176
3177         if (pf->main_vsi)
3178                 i40e_update_vsi_stats(pf->main_vsi);
3179 }
3180
3181 /* Get all statistics of a port */
3182 static int
3183 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3184 {
3185         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3187         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3188         struct i40e_vsi *vsi;
3189         unsigned i;
3190
3191         /* call read registers - updates values, now write them to struct */
3192         i40e_read_stats_registers(pf, hw);
3193
3194         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3195                         pf->main_vsi->eth_stats.rx_multicast +
3196                         pf->main_vsi->eth_stats.rx_broadcast -
3197                         pf->main_vsi->eth_stats.rx_discards;
3198         stats->opackets = ns->eth.tx_unicast +
3199                         ns->eth.tx_multicast +
3200                         ns->eth.tx_broadcast;
3201         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3202         stats->obytes   = ns->eth.tx_bytes;
3203         stats->oerrors  = ns->eth.tx_errors +
3204                         pf->main_vsi->eth_stats.tx_errors;
3205
3206         /* Rx Errors */
3207         stats->imissed  = ns->eth.rx_discards +
3208                         pf->main_vsi->eth_stats.rx_discards;
3209         stats->ierrors  = ns->crc_errors +
3210                         ns->rx_length_errors + ns->rx_undersize +
3211                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3212
3213         if (pf->vfs) {
3214                 for (i = 0; i < pf->vf_num; i++) {
3215                         vsi = pf->vfs[i].vsi;
3216                         i40e_update_vsi_stats(vsi);
3217
3218                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3219                                         vsi->eth_stats.rx_multicast +
3220                                         vsi->eth_stats.rx_broadcast -
3221                                         vsi->eth_stats.rx_discards);
3222                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3223                         stats->oerrors  += vsi->eth_stats.tx_errors;
3224                         stats->imissed  += vsi->eth_stats.rx_discards;
3225                 }
3226         }
3227
3228         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3229         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3230         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3231         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3232         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3233         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3234         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3235                     ns->eth.rx_unknown_protocol);
3236         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3237         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3238         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3239         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3240         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3241         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3242
3243         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3244                     ns->tx_dropped_link_down);
3245         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3246         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3247                     ns->illegal_bytes);
3248         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3249         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3250                     ns->mac_local_faults);
3251         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3252                     ns->mac_remote_faults);
3253         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3254                     ns->rx_length_errors);
3255         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3256         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3257         for (i = 0; i < 8; i++) {
3258                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3259                                 i, ns->priority_xon_rx[i]);
3260                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3261                                 i, ns->priority_xoff_rx[i]);
3262         }
3263         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3264         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3265         for (i = 0; i < 8; i++) {
3266                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3267                                 i, ns->priority_xon_tx[i]);
3268                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3269                                 i, ns->priority_xoff_tx[i]);
3270                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3271                                 i, ns->priority_xon_2_xoff[i]);
3272         }
3273         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3274         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3275         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3276         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3277         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3278         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3279         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3280         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3281         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3282         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3283         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3284         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3285         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3286         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3287         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3288         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3289         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3290         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3291         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3292                         ns->mac_short_packet_dropped);
3293         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3294                     ns->checksum_error);
3295         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3296         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3297         return 0;
3298 }
3299
3300 /* Reset the statistics */
3301 static void
3302 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3303 {
3304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306
3307         /* Mark PF and VSI stats to update the offset, aka "reset" */
3308         pf->offset_loaded = false;
3309         if (pf->main_vsi)
3310                 pf->main_vsi->offset_loaded = false;
3311
3312         /* read the stats, reading current register values into offset */
3313         i40e_read_stats_registers(pf, hw);
3314 }
3315
3316 static uint32_t
3317 i40e_xstats_calc_num(void)
3318 {
3319         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3320                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3321                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3322 }
3323
3324 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3325                                      struct rte_eth_xstat_name *xstats_names,
3326                                      __rte_unused unsigned limit)
3327 {
3328         unsigned count = 0;
3329         unsigned i, prio;
3330
3331         if (xstats_names == NULL)
3332                 return i40e_xstats_calc_num();
3333
3334         /* Note: limit checked in rte_eth_xstats_names() */
3335
3336         /* Get stats from i40e_eth_stats struct */
3337         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3338                 strlcpy(xstats_names[count].name,
3339                         rte_i40e_stats_strings[i].name,
3340                         sizeof(xstats_names[count].name));
3341                 count++;
3342         }
3343
3344         /* Get individiual stats from i40e_hw_port struct */
3345         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3346                 strlcpy(xstats_names[count].name,
3347                         rte_i40e_hw_port_strings[i].name,
3348                         sizeof(xstats_names[count].name));
3349                 count++;
3350         }
3351
3352         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3353                 for (prio = 0; prio < 8; prio++) {
3354                         snprintf(xstats_names[count].name,
3355                                  sizeof(xstats_names[count].name),
3356                                  "rx_priority%u_%s", prio,
3357                                  rte_i40e_rxq_prio_strings[i].name);
3358                         count++;
3359                 }
3360         }
3361
3362         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3363                 for (prio = 0; prio < 8; prio++) {
3364                         snprintf(xstats_names[count].name,
3365                                  sizeof(xstats_names[count].name),
3366                                  "tx_priority%u_%s", prio,
3367                                  rte_i40e_txq_prio_strings[i].name);
3368                         count++;
3369                 }
3370         }
3371         return count;
3372 }
3373
3374 static int
3375 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3376                     unsigned n)
3377 {
3378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3380         unsigned i, count, prio;
3381         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3382
3383         count = i40e_xstats_calc_num();
3384         if (n < count)
3385                 return count;
3386
3387         i40e_read_stats_registers(pf, hw);
3388
3389         if (xstats == NULL)
3390                 return 0;
3391
3392         count = 0;
3393
3394         /* Get stats from i40e_eth_stats struct */
3395         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3396                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3397                         rte_i40e_stats_strings[i].offset);
3398                 xstats[count].id = count;
3399                 count++;
3400         }
3401
3402         /* Get individiual stats from i40e_hw_port struct */
3403         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3404                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3405                         rte_i40e_hw_port_strings[i].offset);
3406                 xstats[count].id = count;
3407                 count++;
3408         }
3409
3410         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3411                 for (prio = 0; prio < 8; prio++) {
3412                         xstats[count].value =
3413                                 *(uint64_t *)(((char *)hw_stats) +
3414                                 rte_i40e_rxq_prio_strings[i].offset +
3415                                 (sizeof(uint64_t) * prio));
3416                         xstats[count].id = count;
3417                         count++;
3418                 }
3419         }
3420
3421         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3422                 for (prio = 0; prio < 8; prio++) {
3423                         xstats[count].value =
3424                                 *(uint64_t *)(((char *)hw_stats) +
3425                                 rte_i40e_txq_prio_strings[i].offset +
3426                                 (sizeof(uint64_t) * prio));
3427                         xstats[count].id = count;
3428                         count++;
3429                 }
3430         }
3431
3432         return count;
3433 }
3434
3435 static int
3436 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3437                                  __rte_unused uint16_t queue_id,
3438                                  __rte_unused uint8_t stat_idx,
3439                                  __rte_unused uint8_t is_rx)
3440 {
3441         PMD_INIT_FUNC_TRACE();
3442
3443         return -ENOSYS;
3444 }
3445
3446 static int
3447 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3448 {
3449         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450         u32 full_ver;
3451         u8 ver, patch;
3452         u16 build;
3453         int ret;
3454
3455         full_ver = hw->nvm.oem_ver;
3456         ver = (u8)(full_ver >> 24);
3457         build = (u16)((full_ver >> 8) & 0xffff);
3458         patch = (u8)(full_ver & 0xff);
3459
3460         ret = snprintf(fw_version, fw_size,
3461                  "%d.%d%d 0x%08x %d.%d.%d",
3462                  ((hw->nvm.version >> 12) & 0xf),
3463                  ((hw->nvm.version >> 4) & 0xff),
3464                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3465                  ver, build, patch);
3466
3467         ret += 1; /* add the size of '\0' */
3468         if (fw_size < (u32)ret)
3469                 return ret;
3470         else
3471                 return 0;
3472 }
3473
3474 /*
3475  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3476  * the Rx data path does not hang if the FW LLDP is stopped.
3477  * return true if lldp need to stop
3478  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3479  */
3480 static bool
3481 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3482 {
3483         double nvm_ver;
3484         char ver_str[64] = {0};
3485         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486
3487         i40e_fw_version_get(dev, ver_str, 64);
3488         nvm_ver = atof(ver_str);
3489         if ((hw->mac.type == I40E_MAC_X722 ||
3490              hw->mac.type == I40E_MAC_X722_VF) &&
3491              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3492                 return true;
3493         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3494                 return true;
3495
3496         return false;
3497 }
3498
3499 static void
3500 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3501 {
3502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3504         struct i40e_vsi *vsi = pf->main_vsi;
3505         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3506
3507         dev_info->max_rx_queues = vsi->nb_qps;
3508         dev_info->max_tx_queues = vsi->nb_qps;
3509         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3510         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3511         dev_info->max_mac_addrs = vsi->max_macaddrs;
3512         dev_info->max_vfs = pci_dev->max_vfs;
3513         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3514         dev_info->min_mtu = ETHER_MIN_MTU;
3515         dev_info->rx_queue_offload_capa = 0;
3516         dev_info->rx_offload_capa =
3517                 DEV_RX_OFFLOAD_VLAN_STRIP |
3518                 DEV_RX_OFFLOAD_QINQ_STRIP |
3519                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3520                 DEV_RX_OFFLOAD_UDP_CKSUM |
3521                 DEV_RX_OFFLOAD_TCP_CKSUM |
3522                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3523                 DEV_RX_OFFLOAD_KEEP_CRC |
3524                 DEV_RX_OFFLOAD_SCATTER |
3525                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3526                 DEV_RX_OFFLOAD_VLAN_FILTER |
3527                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3528
3529         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3530         dev_info->tx_offload_capa =
3531                 DEV_TX_OFFLOAD_VLAN_INSERT |
3532                 DEV_TX_OFFLOAD_QINQ_INSERT |
3533                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3534                 DEV_TX_OFFLOAD_UDP_CKSUM |
3535                 DEV_TX_OFFLOAD_TCP_CKSUM |
3536                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3537                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3538                 DEV_TX_OFFLOAD_TCP_TSO |
3539                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3540                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3541                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3542                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3543                 DEV_TX_OFFLOAD_MULTI_SEGS |
3544                 dev_info->tx_queue_offload_capa;
3545         dev_info->dev_capa =
3546                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3547                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3548
3549         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3550                                                 sizeof(uint32_t);
3551         dev_info->reta_size = pf->hash_lut_size;
3552         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3553
3554         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3555                 .rx_thresh = {
3556                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3557                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3558                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3559                 },
3560                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3561                 .rx_drop_en = 0,
3562                 .offloads = 0,
3563         };
3564
3565         dev_info->default_txconf = (struct rte_eth_txconf) {
3566                 .tx_thresh = {
3567                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3568                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3569                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3570                 },
3571                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3572                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3573                 .offloads = 0,
3574         };
3575
3576         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3577                 .nb_max = I40E_MAX_RING_DESC,
3578                 .nb_min = I40E_MIN_RING_DESC,
3579                 .nb_align = I40E_ALIGN_RING_DESC,
3580         };
3581
3582         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3583                 .nb_max = I40E_MAX_RING_DESC,
3584                 .nb_min = I40E_MIN_RING_DESC,
3585                 .nb_align = I40E_ALIGN_RING_DESC,
3586                 .nb_seg_max = I40E_TX_MAX_SEG,
3587                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3588         };
3589
3590         if (pf->flags & I40E_FLAG_VMDQ) {
3591                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3592                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3593                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3594                                                 pf->max_nb_vmdq_vsi;
3595                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3596                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3597                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3598         }
3599
3600         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3601                 /* For XL710 */
3602                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3603                 dev_info->default_rxportconf.nb_queues = 2;
3604                 dev_info->default_txportconf.nb_queues = 2;
3605                 if (dev->data->nb_rx_queues == 1)
3606                         dev_info->default_rxportconf.ring_size = 2048;
3607                 else
3608                         dev_info->default_rxportconf.ring_size = 1024;
3609                 if (dev->data->nb_tx_queues == 1)
3610                         dev_info->default_txportconf.ring_size = 1024;
3611                 else
3612                         dev_info->default_txportconf.ring_size = 512;
3613
3614         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3615                 /* For XXV710 */
3616                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3617                 dev_info->default_rxportconf.nb_queues = 1;
3618                 dev_info->default_txportconf.nb_queues = 1;
3619                 dev_info->default_rxportconf.ring_size = 256;
3620                 dev_info->default_txportconf.ring_size = 256;
3621         } else {
3622                 /* For X710 */
3623                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3624                 dev_info->default_rxportconf.nb_queues = 1;
3625                 dev_info->default_txportconf.nb_queues = 1;
3626                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3627                         dev_info->default_rxportconf.ring_size = 512;
3628                         dev_info->default_txportconf.ring_size = 256;
3629                 } else {
3630                         dev_info->default_rxportconf.ring_size = 256;
3631                         dev_info->default_txportconf.ring_size = 256;
3632                 }
3633         }
3634         dev_info->default_rxportconf.burst_size = 32;
3635         dev_info->default_txportconf.burst_size = 32;
3636 }
3637
3638 static int
3639 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3640 {
3641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3642         struct i40e_vsi *vsi = pf->main_vsi;
3643         PMD_INIT_FUNC_TRACE();
3644
3645         if (on)
3646                 return i40e_vsi_add_vlan(vsi, vlan_id);
3647         else
3648                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3649 }
3650
3651 static int
3652 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3653                                 enum rte_vlan_type vlan_type,
3654                                 uint16_t tpid, int qinq)
3655 {
3656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657         uint64_t reg_r = 0;
3658         uint64_t reg_w = 0;
3659         uint16_t reg_id = 3;
3660         int ret;
3661
3662         if (qinq) {
3663                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3664                         reg_id = 2;
3665         }
3666
3667         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3668                                           &reg_r, NULL);
3669         if (ret != I40E_SUCCESS) {
3670                 PMD_DRV_LOG(ERR,
3671                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3672                            reg_id);
3673                 return -EIO;
3674         }
3675         PMD_DRV_LOG(DEBUG,
3676                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3677                     reg_id, reg_r);
3678
3679         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3680         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3681         if (reg_r == reg_w) {
3682                 PMD_DRV_LOG(DEBUG, "No need to write");
3683                 return 0;
3684         }
3685
3686         ret = i40e_aq_debug_write_global_register(hw,
3687                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3688                                            reg_w, NULL);
3689         if (ret != I40E_SUCCESS) {
3690                 PMD_DRV_LOG(ERR,
3691                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3692                             reg_id);
3693                 return -EIO;
3694         }
3695         PMD_DRV_LOG(DEBUG,
3696                     "Global register 0x%08x is changed with value 0x%08x",
3697                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3698
3699         return 0;
3700 }
3701
3702 static int
3703 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3704                    enum rte_vlan_type vlan_type,
3705                    uint16_t tpid)
3706 {
3707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3709         int qinq = dev->data->dev_conf.rxmode.offloads &
3710                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3711         int ret = 0;
3712
3713         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3714              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3715             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3716                 PMD_DRV_LOG(ERR,
3717                             "Unsupported vlan type.");
3718                 return -EINVAL;
3719         }
3720
3721         if (pf->support_multi_driver) {
3722                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3723                 return -ENOTSUP;
3724         }
3725
3726         /* 802.1ad frames ability is added in NVM API 1.7*/
3727         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3728                 if (qinq) {
3729                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3730                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3731                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3732                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3733                 } else {
3734                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3735                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3736                 }
3737                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3738                 if (ret != I40E_SUCCESS) {
3739                         PMD_DRV_LOG(ERR,
3740                                     "Set switch config failed aq_err: %d",
3741                                     hw->aq.asq_last_status);
3742                         ret = -EIO;
3743                 }
3744         } else
3745                 /* If NVM API < 1.7, keep the register setting */
3746                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3747                                                       tpid, qinq);
3748
3749         return ret;
3750 }
3751
3752 static int
3753 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3754 {
3755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3756         struct i40e_vsi *vsi = pf->main_vsi;
3757         struct rte_eth_rxmode *rxmode;
3758
3759         rxmode = &dev->data->dev_conf.rxmode;
3760         if (mask & ETH_VLAN_FILTER_MASK) {
3761                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3762                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3763                 else
3764                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3765         }
3766
3767         if (mask & ETH_VLAN_STRIP_MASK) {
3768                 /* Enable or disable VLAN stripping */
3769                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3770                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3771                 else
3772                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3773         }
3774
3775         if (mask & ETH_VLAN_EXTEND_MASK) {
3776                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3777                         i40e_vsi_config_double_vlan(vsi, TRUE);
3778                         /* Set global registers with default ethertype. */
3779                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3780                                            ETHER_TYPE_VLAN);
3781                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3782                                            ETHER_TYPE_VLAN);
3783                 }
3784                 else
3785                         i40e_vsi_config_double_vlan(vsi, FALSE);
3786         }
3787
3788         return 0;
3789 }
3790
3791 static void
3792 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3793                           __rte_unused uint16_t queue,
3794                           __rte_unused int on)
3795 {
3796         PMD_INIT_FUNC_TRACE();
3797 }
3798
3799 static int
3800 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3801 {
3802         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3803         struct i40e_vsi *vsi = pf->main_vsi;
3804         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3805         struct i40e_vsi_vlan_pvid_info info;
3806
3807         memset(&info, 0, sizeof(info));
3808         info.on = on;
3809         if (info.on)
3810                 info.config.pvid = pvid;
3811         else {
3812                 info.config.reject.tagged =
3813                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3814                 info.config.reject.untagged =
3815                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3816         }
3817
3818         return i40e_vsi_vlan_pvid_set(vsi, &info);
3819 }
3820
3821 static int
3822 i40e_dev_led_on(struct rte_eth_dev *dev)
3823 {
3824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3825         uint32_t mode = i40e_led_get(hw);
3826
3827         if (mode == 0)
3828                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3829
3830         return 0;
3831 }
3832
3833 static int
3834 i40e_dev_led_off(struct rte_eth_dev *dev)
3835 {
3836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3837         uint32_t mode = i40e_led_get(hw);
3838
3839         if (mode != 0)
3840                 i40e_led_set(hw, 0, false);
3841
3842         return 0;
3843 }
3844
3845 static int
3846 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3847 {
3848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3850
3851         fc_conf->pause_time = pf->fc_conf.pause_time;
3852
3853         /* read out from register, in case they are modified by other port */
3854         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3855                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3856         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3857                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3858
3859         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3860         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3861
3862          /* Return current mode according to actual setting*/
3863         switch (hw->fc.current_mode) {
3864         case I40E_FC_FULL:
3865                 fc_conf->mode = RTE_FC_FULL;
3866                 break;
3867         case I40E_FC_TX_PAUSE:
3868                 fc_conf->mode = RTE_FC_TX_PAUSE;
3869                 break;
3870         case I40E_FC_RX_PAUSE:
3871                 fc_conf->mode = RTE_FC_RX_PAUSE;
3872                 break;
3873         case I40E_FC_NONE:
3874         default:
3875                 fc_conf->mode = RTE_FC_NONE;
3876         };
3877
3878         return 0;
3879 }
3880
3881 static int
3882 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3883 {
3884         uint32_t mflcn_reg, fctrl_reg, reg;
3885         uint32_t max_high_water;
3886         uint8_t i, aq_failure;
3887         int err;
3888         struct i40e_hw *hw;
3889         struct i40e_pf *pf;
3890         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3891                 [RTE_FC_NONE] = I40E_FC_NONE,
3892                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3893                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3894                 [RTE_FC_FULL] = I40E_FC_FULL
3895         };
3896
3897         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3898
3899         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3900         if ((fc_conf->high_water > max_high_water) ||
3901                         (fc_conf->high_water < fc_conf->low_water)) {
3902                 PMD_INIT_LOG(ERR,
3903                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3904                         max_high_water);
3905                 return -EINVAL;
3906         }
3907
3908         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3909         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3910         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3911
3912         pf->fc_conf.pause_time = fc_conf->pause_time;
3913         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3914         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3915
3916         PMD_INIT_FUNC_TRACE();
3917
3918         /* All the link flow control related enable/disable register
3919          * configuration is handle by the F/W
3920          */
3921         err = i40e_set_fc(hw, &aq_failure, true);
3922         if (err < 0)
3923                 return -ENOSYS;
3924
3925         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3926                 /* Configure flow control refresh threshold,
3927                  * the value for stat_tx_pause_refresh_timer[8]
3928                  * is used for global pause operation.
3929                  */
3930
3931                 I40E_WRITE_REG(hw,
3932                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3933                                pf->fc_conf.pause_time);
3934
3935                 /* configure the timer value included in transmitted pause
3936                  * frame,
3937                  * the value for stat_tx_pause_quanta[8] is used for global
3938                  * pause operation
3939                  */
3940                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3941                                pf->fc_conf.pause_time);
3942
3943                 fctrl_reg = I40E_READ_REG(hw,
3944                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3945
3946                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3947                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3948                 else
3949                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3950
3951                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3952                                fctrl_reg);
3953         } else {
3954                 /* Configure pause time (2 TCs per register) */
3955                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3956                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3957                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3958
3959                 /* Configure flow control refresh threshold value */
3960                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3961                                pf->fc_conf.pause_time / 2);
3962
3963                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3964
3965                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3966                  *depending on configuration
3967                  */
3968                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3969                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3970                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3971                 } else {
3972                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3973                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3974                 }
3975
3976                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3977         }
3978
3979         if (!pf->support_multi_driver) {
3980                 /* config water marker both based on the packets and bytes */
3981                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3982                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3983                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3984                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3985                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3986                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3987                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3988                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3989                                   << I40E_KILOSHIFT);
3990                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3991                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3992                                    << I40E_KILOSHIFT);
3993         } else {
3994                 PMD_DRV_LOG(ERR,
3995                             "Water marker configuration is not supported.");
3996         }
3997
3998         I40E_WRITE_FLUSH(hw);
3999
4000         return 0;
4001 }
4002
4003 static int
4004 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4005                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4006 {
4007         PMD_INIT_FUNC_TRACE();
4008
4009         return -ENOSYS;
4010 }
4011
4012 /* Add a MAC address, and update filters */
4013 static int
4014 i40e_macaddr_add(struct rte_eth_dev *dev,
4015                  struct rte_ether_addr *mac_addr,
4016                  __rte_unused uint32_t index,
4017                  uint32_t pool)
4018 {
4019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4020         struct i40e_mac_filter_info mac_filter;
4021         struct i40e_vsi *vsi;
4022         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4023         int ret;
4024
4025         /* If VMDQ not enabled or configured, return */
4026         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4027                           !pf->nb_cfg_vmdq_vsi)) {
4028                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4029                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4030                         pool);
4031                 return -ENOTSUP;
4032         }
4033
4034         if (pool > pf->nb_cfg_vmdq_vsi) {
4035                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4036                                 pool, pf->nb_cfg_vmdq_vsi);
4037                 return -EINVAL;
4038         }
4039
4040         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
4041         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4042                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4043         else
4044                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4045
4046         if (pool == 0)
4047                 vsi = pf->main_vsi;
4048         else
4049                 vsi = pf->vmdq[pool - 1].vsi;
4050
4051         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4052         if (ret != I40E_SUCCESS) {
4053                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4054                 return -ENODEV;
4055         }
4056         return 0;
4057 }
4058
4059 /* Remove a MAC address, and update filters */
4060 static void
4061 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4062 {
4063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4064         struct i40e_vsi *vsi;
4065         struct rte_eth_dev_data *data = dev->data;
4066         struct rte_ether_addr *macaddr;
4067         int ret;
4068         uint32_t i;
4069         uint64_t pool_sel;
4070
4071         macaddr = &(data->mac_addrs[index]);
4072
4073         pool_sel = dev->data->mac_pool_sel[index];
4074
4075         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4076                 if (pool_sel & (1ULL << i)) {
4077                         if (i == 0)
4078                                 vsi = pf->main_vsi;
4079                         else {
4080                                 /* No VMDQ pool enabled or configured */
4081                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4082                                         (i > pf->nb_cfg_vmdq_vsi)) {
4083                                         PMD_DRV_LOG(ERR,
4084                                                 "No VMDQ pool enabled/configured");
4085                                         return;
4086                                 }
4087                                 vsi = pf->vmdq[i - 1].vsi;
4088                         }
4089                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4090
4091                         if (ret) {
4092                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4093                                 return;
4094                         }
4095                 }
4096         }
4097 }
4098
4099 /* Set perfect match or hash match of MAC and VLAN for a VF */
4100 static int
4101 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4102                  struct rte_eth_mac_filter *filter,
4103                  bool add)
4104 {
4105         struct i40e_hw *hw;
4106         struct i40e_mac_filter_info mac_filter;
4107         struct rte_ether_addr old_mac;
4108         struct rte_ether_addr *new_mac;
4109         struct i40e_pf_vf *vf = NULL;
4110         uint16_t vf_id;
4111         int ret;
4112
4113         if (pf == NULL) {
4114                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4115                 return -EINVAL;
4116         }
4117         hw = I40E_PF_TO_HW(pf);
4118
4119         if (filter == NULL) {
4120                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4121                 return -EINVAL;
4122         }
4123
4124         new_mac = &filter->mac_addr;
4125
4126         if (is_zero_ether_addr(new_mac)) {
4127                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4128                 return -EINVAL;
4129         }
4130
4131         vf_id = filter->dst_id;
4132
4133         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4134                 PMD_DRV_LOG(ERR, "Invalid argument.");
4135                 return -EINVAL;
4136         }
4137         vf = &pf->vfs[vf_id];
4138
4139         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4140                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4141                 return -EINVAL;
4142         }
4143
4144         if (add) {
4145                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4146                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4147                                 ETHER_ADDR_LEN);
4148                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4149                                  ETHER_ADDR_LEN);
4150
4151                 mac_filter.filter_type = filter->filter_type;
4152                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4153                 if (ret != I40E_SUCCESS) {
4154                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4155                         return -1;
4156                 }
4157                 ether_addr_copy(new_mac, &pf->dev_addr);
4158         } else {
4159                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4160                                 ETHER_ADDR_LEN);
4161                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4162                 if (ret != I40E_SUCCESS) {
4163                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4164                         return -1;
4165                 }
4166
4167                 /* Clear device address as it has been removed */
4168                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4169                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4170         }
4171
4172         return 0;
4173 }
4174
4175 /* MAC filter handle */
4176 static int
4177 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4178                 void *arg)
4179 {
4180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4181         struct rte_eth_mac_filter *filter;
4182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4183         int ret = I40E_NOT_SUPPORTED;
4184
4185         filter = (struct rte_eth_mac_filter *)(arg);
4186
4187         switch (filter_op) {
4188         case RTE_ETH_FILTER_NOP:
4189                 ret = I40E_SUCCESS;
4190                 break;
4191         case RTE_ETH_FILTER_ADD:
4192                 i40e_pf_disable_irq0(hw);
4193                 if (filter->is_vf)
4194                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4195                 i40e_pf_enable_irq0(hw);
4196                 break;
4197         case RTE_ETH_FILTER_DELETE:
4198                 i40e_pf_disable_irq0(hw);
4199                 if (filter->is_vf)
4200                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4201                 i40e_pf_enable_irq0(hw);
4202                 break;
4203         default:
4204                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4205                 ret = I40E_ERR_PARAM;
4206                 break;
4207         }
4208
4209         return ret;
4210 }
4211
4212 static int
4213 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4214 {
4215         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4216         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4217         uint32_t reg;
4218         int ret;
4219
4220         if (!lut)
4221                 return -EINVAL;
4222
4223         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4224                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4225                                           vsi->type != I40E_VSI_SRIOV,
4226                                           lut, lut_size);
4227                 if (ret) {
4228                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4229                         return ret;
4230                 }
4231         } else {
4232                 uint32_t *lut_dw = (uint32_t *)lut;
4233                 uint16_t i, lut_size_dw = lut_size / 4;
4234
4235                 if (vsi->type == I40E_VSI_SRIOV) {
4236                         for (i = 0; i <= lut_size_dw; i++) {
4237                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4238                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4239                         }
4240                 } else {
4241                         for (i = 0; i < lut_size_dw; i++)
4242                                 lut_dw[i] = I40E_READ_REG(hw,
4243                                                           I40E_PFQF_HLUT(i));
4244                 }
4245         }
4246
4247         return 0;
4248 }
4249
4250 int
4251 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4252 {
4253         struct i40e_pf *pf;
4254         struct i40e_hw *hw;
4255         int ret;
4256
4257         if (!vsi || !lut)
4258                 return -EINVAL;
4259
4260         pf = I40E_VSI_TO_PF(vsi);
4261         hw = I40E_VSI_TO_HW(vsi);
4262
4263         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4264                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4265                                           vsi->type != I40E_VSI_SRIOV,
4266                                           lut, lut_size);
4267                 if (ret) {
4268                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4269                         return ret;
4270                 }
4271         } else {
4272                 uint32_t *lut_dw = (uint32_t *)lut;
4273                 uint16_t i, lut_size_dw = lut_size / 4;
4274
4275                 if (vsi->type == I40E_VSI_SRIOV) {
4276                         for (i = 0; i < lut_size_dw; i++)
4277                                 I40E_WRITE_REG(
4278                                         hw,
4279                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4280                                         lut_dw[i]);
4281                 } else {
4282                         for (i = 0; i < lut_size_dw; i++)
4283                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4284                                                lut_dw[i]);
4285                 }
4286                 I40E_WRITE_FLUSH(hw);
4287         }
4288
4289         return 0;
4290 }
4291
4292 static int
4293 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4294                          struct rte_eth_rss_reta_entry64 *reta_conf,
4295                          uint16_t reta_size)
4296 {
4297         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4298         uint16_t i, lut_size = pf->hash_lut_size;
4299         uint16_t idx, shift;
4300         uint8_t *lut;
4301         int ret;
4302
4303         if (reta_size != lut_size ||
4304                 reta_size > ETH_RSS_RETA_SIZE_512) {
4305                 PMD_DRV_LOG(ERR,
4306                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4307                         reta_size, lut_size);
4308                 return -EINVAL;
4309         }
4310
4311         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4312         if (!lut) {
4313                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4314                 return -ENOMEM;
4315         }
4316         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4317         if (ret)
4318                 goto out;
4319         for (i = 0; i < reta_size; i++) {
4320                 idx = i / RTE_RETA_GROUP_SIZE;
4321                 shift = i % RTE_RETA_GROUP_SIZE;
4322                 if (reta_conf[idx].mask & (1ULL << shift))
4323                         lut[i] = reta_conf[idx].reta[shift];
4324         }
4325         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4326
4327         pf->adapter->rss_reta_updated = 1;
4328
4329 out:
4330         rte_free(lut);
4331
4332         return ret;
4333 }
4334
4335 static int
4336 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4337                         struct rte_eth_rss_reta_entry64 *reta_conf,
4338                         uint16_t reta_size)
4339 {
4340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4341         uint16_t i, lut_size = pf->hash_lut_size;
4342         uint16_t idx, shift;
4343         uint8_t *lut;
4344         int ret;
4345
4346         if (reta_size != lut_size ||
4347                 reta_size > ETH_RSS_RETA_SIZE_512) {
4348                 PMD_DRV_LOG(ERR,
4349                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4350                         reta_size, lut_size);
4351                 return -EINVAL;
4352         }
4353
4354         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4355         if (!lut) {
4356                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4357                 return -ENOMEM;
4358         }
4359
4360         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4361         if (ret)
4362                 goto out;
4363         for (i = 0; i < reta_size; i++) {
4364                 idx = i / RTE_RETA_GROUP_SIZE;
4365                 shift = i % RTE_RETA_GROUP_SIZE;
4366                 if (reta_conf[idx].mask & (1ULL << shift))
4367                         reta_conf[idx].reta[shift] = lut[i];
4368         }
4369
4370 out:
4371         rte_free(lut);
4372
4373         return ret;
4374 }
4375
4376 /**
4377  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4378  * @hw:   pointer to the HW structure
4379  * @mem:  pointer to mem struct to fill out
4380  * @size: size of memory requested
4381  * @alignment: what to align the allocation to
4382  **/
4383 enum i40e_status_code
4384 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4385                         struct i40e_dma_mem *mem,
4386                         u64 size,
4387                         u32 alignment)
4388 {
4389         const struct rte_memzone *mz = NULL;
4390         char z_name[RTE_MEMZONE_NAMESIZE];
4391
4392         if (!mem)
4393                 return I40E_ERR_PARAM;
4394
4395         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4396         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4397                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4398         if (!mz)
4399                 return I40E_ERR_NO_MEMORY;
4400
4401         mem->size = size;
4402         mem->va = mz->addr;
4403         mem->pa = mz->iova;
4404         mem->zone = (const void *)mz;
4405         PMD_DRV_LOG(DEBUG,
4406                 "memzone %s allocated with physical address: %"PRIu64,
4407                 mz->name, mem->pa);
4408
4409         return I40E_SUCCESS;
4410 }
4411
4412 /**
4413  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4414  * @hw:   pointer to the HW structure
4415  * @mem:  ptr to mem struct to free
4416  **/
4417 enum i40e_status_code
4418 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4419                     struct i40e_dma_mem *mem)
4420 {
4421         if (!mem)
4422                 return I40E_ERR_PARAM;
4423
4424         PMD_DRV_LOG(DEBUG,
4425                 "memzone %s to be freed with physical address: %"PRIu64,
4426                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4427         rte_memzone_free((const struct rte_memzone *)mem->zone);
4428         mem->zone = NULL;
4429         mem->va = NULL;
4430         mem->pa = (u64)0;
4431
4432         return I40E_SUCCESS;
4433 }
4434
4435 /**
4436  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4437  * @hw:   pointer to the HW structure
4438  * @mem:  pointer to mem struct to fill out
4439  * @size: size of memory requested
4440  **/
4441 enum i40e_status_code
4442 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4443                          struct i40e_virt_mem *mem,
4444                          u32 size)
4445 {
4446         if (!mem)
4447                 return I40E_ERR_PARAM;
4448
4449         mem->size = size;
4450         mem->va = rte_zmalloc("i40e", size, 0);
4451
4452         if (mem->va)
4453                 return I40E_SUCCESS;
4454         else
4455                 return I40E_ERR_NO_MEMORY;
4456 }
4457
4458 /**
4459  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4460  * @hw:   pointer to the HW structure
4461  * @mem:  pointer to mem struct to free
4462  **/
4463 enum i40e_status_code
4464 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4465                      struct i40e_virt_mem *mem)
4466 {
4467         if (!mem)
4468                 return I40E_ERR_PARAM;
4469
4470         rte_free(mem->va);
4471         mem->va = NULL;
4472
4473         return I40E_SUCCESS;
4474 }
4475
4476 void
4477 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4478 {
4479         rte_spinlock_init(&sp->spinlock);
4480 }
4481
4482 void
4483 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4484 {
4485         rte_spinlock_lock(&sp->spinlock);
4486 }
4487
4488 void
4489 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4490 {
4491         rte_spinlock_unlock(&sp->spinlock);
4492 }
4493
4494 void
4495 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4496 {
4497         return;
4498 }
4499
4500 /**
4501  * Get the hardware capabilities, which will be parsed
4502  * and saved into struct i40e_hw.
4503  */
4504 static int
4505 i40e_get_cap(struct i40e_hw *hw)
4506 {
4507         struct i40e_aqc_list_capabilities_element_resp *buf;
4508         uint16_t len, size = 0;
4509         int ret;
4510
4511         /* Calculate a huge enough buff for saving response data temporarily */
4512         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4513                                                 I40E_MAX_CAP_ELE_NUM;
4514         buf = rte_zmalloc("i40e", len, 0);
4515         if (!buf) {
4516                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4517                 return I40E_ERR_NO_MEMORY;
4518         }
4519
4520         /* Get, parse the capabilities and save it to hw */
4521         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4522                         i40e_aqc_opc_list_func_capabilities, NULL);
4523         if (ret != I40E_SUCCESS)
4524                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4525
4526         /* Free the temporary buffer after being used */
4527         rte_free(buf);
4528
4529         return ret;
4530 }
4531
4532 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4533
4534 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4535                 const char *value,
4536                 void *opaque)
4537 {
4538         struct i40e_pf *pf;
4539         unsigned long num;
4540         char *end;
4541
4542         pf = (struct i40e_pf *)opaque;
4543         RTE_SET_USED(key);
4544
4545         errno = 0;
4546         num = strtoul(value, &end, 0);
4547         if (errno != 0 || end == value || *end != 0) {
4548                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4549                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4550                 return -(EINVAL);
4551         }
4552
4553         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4554                 pf->vf_nb_qp_max = (uint16_t)num;
4555         else
4556                 /* here return 0 to make next valid same argument work */
4557                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4558                             "power of 2 and equal or less than 16 !, Now it is "
4559                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4560
4561         return 0;
4562 }
4563
4564 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4565 {
4566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4567         struct rte_kvargs *kvlist;
4568         int kvargs_count;
4569
4570         /* set default queue number per VF as 4 */
4571         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4572
4573         if (dev->device->devargs == NULL)
4574                 return 0;
4575
4576         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4577         if (kvlist == NULL)
4578                 return -(EINVAL);
4579
4580         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4581         if (!kvargs_count) {
4582                 rte_kvargs_free(kvlist);
4583                 return 0;
4584         }
4585
4586         if (kvargs_count > 1)
4587                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4588                             "the first invalid or last valid one is used !",
4589                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4590
4591         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4592                            i40e_pf_parse_vf_queue_number_handler, pf);
4593
4594         rte_kvargs_free(kvlist);
4595
4596         return 0;
4597 }
4598
4599 static int
4600 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4601 {
4602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4604         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4605         uint16_t qp_count = 0, vsi_count = 0;
4606
4607         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4608                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4609                 return -EINVAL;
4610         }
4611
4612         i40e_pf_config_vf_rxq_number(dev);
4613
4614         /* Add the parameter init for LFC */
4615         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4616         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4617         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4618
4619         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4620         pf->max_num_vsi = hw->func_caps.num_vsis;
4621         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4622         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4623
4624         /* FDir queue/VSI allocation */
4625         pf->fdir_qp_offset = 0;
4626         if (hw->func_caps.fd) {
4627                 pf->flags |= I40E_FLAG_FDIR;
4628                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4629         } else {
4630                 pf->fdir_nb_qps = 0;
4631         }
4632         qp_count += pf->fdir_nb_qps;
4633         vsi_count += 1;
4634
4635         /* LAN queue/VSI allocation */
4636         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4637         if (!hw->func_caps.rss) {
4638                 pf->lan_nb_qps = 1;
4639         } else {
4640                 pf->flags |= I40E_FLAG_RSS;
4641                 if (hw->mac.type == I40E_MAC_X722)
4642                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4643                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4644         }
4645         qp_count += pf->lan_nb_qps;
4646         vsi_count += 1;
4647
4648         /* VF queue/VSI allocation */
4649         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4650         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4651                 pf->flags |= I40E_FLAG_SRIOV;
4652                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4653                 pf->vf_num = pci_dev->max_vfs;
4654                 PMD_DRV_LOG(DEBUG,
4655                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4656                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4657         } else {
4658                 pf->vf_nb_qps = 0;
4659                 pf->vf_num = 0;
4660         }
4661         qp_count += pf->vf_nb_qps * pf->vf_num;
4662         vsi_count += pf->vf_num;
4663
4664         /* VMDq queue/VSI allocation */
4665         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4666         pf->vmdq_nb_qps = 0;
4667         pf->max_nb_vmdq_vsi = 0;
4668         if (hw->func_caps.vmdq) {
4669                 if (qp_count < hw->func_caps.num_tx_qp &&
4670                         vsi_count < hw->func_caps.num_vsis) {
4671                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4672                                 qp_count) / pf->vmdq_nb_qp_max;
4673
4674                         /* Limit the maximum number of VMDq vsi to the maximum
4675                          * ethdev can support
4676                          */
4677                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4678                                 hw->func_caps.num_vsis - vsi_count);
4679                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4680                                 ETH_64_POOLS);
4681                         if (pf->max_nb_vmdq_vsi) {
4682                                 pf->flags |= I40E_FLAG_VMDQ;
4683                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4684                                 PMD_DRV_LOG(DEBUG,
4685                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4686                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4687                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4688                         } else {
4689                                 PMD_DRV_LOG(INFO,
4690                                         "No enough queues left for VMDq");
4691                         }
4692                 } else {
4693                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4694                 }
4695         }
4696         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4697         vsi_count += pf->max_nb_vmdq_vsi;
4698
4699         if (hw->func_caps.dcb)
4700                 pf->flags |= I40E_FLAG_DCB;
4701
4702         if (qp_count > hw->func_caps.num_tx_qp) {
4703                 PMD_DRV_LOG(ERR,
4704                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4705                         qp_count, hw->func_caps.num_tx_qp);
4706                 return -EINVAL;
4707         }
4708         if (vsi_count > hw->func_caps.num_vsis) {
4709                 PMD_DRV_LOG(ERR,
4710                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4711                         vsi_count, hw->func_caps.num_vsis);
4712                 return -EINVAL;
4713         }
4714
4715         return 0;
4716 }
4717
4718 static int
4719 i40e_pf_get_switch_config(struct i40e_pf *pf)
4720 {
4721         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4722         struct i40e_aqc_get_switch_config_resp *switch_config;
4723         struct i40e_aqc_switch_config_element_resp *element;
4724         uint16_t start_seid = 0, num_reported;
4725         int ret;
4726
4727         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4728                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4729         if (!switch_config) {
4730                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4731                 return -ENOMEM;
4732         }
4733
4734         /* Get the switch configurations */
4735         ret = i40e_aq_get_switch_config(hw, switch_config,
4736                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4737         if (ret != I40E_SUCCESS) {
4738                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4739                 goto fail;
4740         }
4741         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4742         if (num_reported != 1) { /* The number should be 1 */
4743                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4744                 goto fail;
4745         }
4746
4747         /* Parse the switch configuration elements */
4748         element = &(switch_config->element[0]);
4749         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4750                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4751                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4752         } else
4753                 PMD_DRV_LOG(INFO, "Unknown element type");
4754
4755 fail:
4756         rte_free(switch_config);
4757
4758         return ret;
4759 }
4760
4761 static int
4762 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4763                         uint32_t num)
4764 {
4765         struct pool_entry *entry;
4766
4767         if (pool == NULL || num == 0)
4768                 return -EINVAL;
4769
4770         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4771         if (entry == NULL) {
4772                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4773                 return -ENOMEM;
4774         }
4775
4776         /* queue heap initialize */
4777         pool->num_free = num;
4778         pool->num_alloc = 0;
4779         pool->base = base;
4780         LIST_INIT(&pool->alloc_list);
4781         LIST_INIT(&pool->free_list);
4782
4783         /* Initialize element  */
4784         entry->base = 0;
4785         entry->len = num;
4786
4787         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4788         return 0;
4789 }
4790
4791 static void
4792 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4793 {
4794         struct pool_entry *entry, *next_entry;
4795
4796         if (pool == NULL)
4797                 return;
4798
4799         for (entry = LIST_FIRST(&pool->alloc_list);
4800                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4801                         entry = next_entry) {
4802                 LIST_REMOVE(entry, next);
4803                 rte_free(entry);
4804         }
4805
4806         for (entry = LIST_FIRST(&pool->free_list);
4807                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4808                         entry = next_entry) {
4809                 LIST_REMOVE(entry, next);
4810                 rte_free(entry);
4811         }
4812
4813         pool->num_free = 0;
4814         pool->num_alloc = 0;
4815         pool->base = 0;
4816         LIST_INIT(&pool->alloc_list);
4817         LIST_INIT(&pool->free_list);
4818 }
4819
4820 static int
4821 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4822                        uint32_t base)
4823 {
4824         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4825         uint32_t pool_offset;
4826         int insert;
4827
4828         if (pool == NULL) {
4829                 PMD_DRV_LOG(ERR, "Invalid parameter");
4830                 return -EINVAL;
4831         }
4832
4833         pool_offset = base - pool->base;
4834         /* Lookup in alloc list */
4835         LIST_FOREACH(entry, &pool->alloc_list, next) {
4836                 if (entry->base == pool_offset) {
4837                         valid_entry = entry;
4838                         LIST_REMOVE(entry, next);
4839                         break;
4840                 }
4841         }
4842
4843         /* Not find, return */
4844         if (valid_entry == NULL) {
4845                 PMD_DRV_LOG(ERR, "Failed to find entry");
4846                 return -EINVAL;
4847         }
4848
4849         /**
4850          * Found it, move it to free list  and try to merge.
4851          * In order to make merge easier, always sort it by qbase.
4852          * Find adjacent prev and last entries.
4853          */
4854         prev = next = NULL;
4855         LIST_FOREACH(entry, &pool->free_list, next) {
4856                 if (entry->base > valid_entry->base) {
4857                         next = entry;
4858                         break;
4859                 }
4860                 prev = entry;
4861         }
4862
4863         insert = 0;
4864         /* Try to merge with next one*/
4865         if (next != NULL) {
4866                 /* Merge with next one */
4867                 if (valid_entry->base + valid_entry->len == next->base) {
4868                         next->base = valid_entry->base;
4869                         next->len += valid_entry->len;
4870                         rte_free(valid_entry);
4871                         valid_entry = next;
4872                         insert = 1;
4873                 }
4874         }
4875
4876         if (prev != NULL) {
4877                 /* Merge with previous one */
4878                 if (prev->base + prev->len == valid_entry->base) {
4879                         prev->len += valid_entry->len;
4880                         /* If it merge with next one, remove next node */
4881                         if (insert == 1) {
4882                                 LIST_REMOVE(valid_entry, next);
4883                                 rte_free(valid_entry);
4884                         } else {
4885                                 rte_free(valid_entry);
4886                                 insert = 1;
4887                         }
4888                 }
4889         }
4890
4891         /* Not find any entry to merge, insert */
4892         if (insert == 0) {
4893                 if (prev != NULL)
4894                         LIST_INSERT_AFTER(prev, valid_entry, next);
4895                 else if (next != NULL)
4896                         LIST_INSERT_BEFORE(next, valid_entry, next);
4897                 else /* It's empty list, insert to head */
4898                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4899         }
4900
4901         pool->num_free += valid_entry->len;
4902         pool->num_alloc -= valid_entry->len;
4903
4904         return 0;
4905 }
4906
4907 static int
4908 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4909                        uint16_t num)
4910 {
4911         struct pool_entry *entry, *valid_entry;
4912
4913         if (pool == NULL || num == 0) {
4914                 PMD_DRV_LOG(ERR, "Invalid parameter");
4915                 return -EINVAL;
4916         }
4917
4918         if (pool->num_free < num) {
4919                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4920                             num, pool->num_free);
4921                 return -ENOMEM;
4922         }
4923
4924         valid_entry = NULL;
4925         /* Lookup  in free list and find most fit one */
4926         LIST_FOREACH(entry, &pool->free_list, next) {
4927                 if (entry->len >= num) {
4928                         /* Find best one */
4929                         if (entry->len == num) {
4930                                 valid_entry = entry;
4931                                 break;
4932                         }
4933                         if (valid_entry == NULL || valid_entry->len > entry->len)
4934                                 valid_entry = entry;
4935                 }
4936         }
4937
4938         /* Not find one to satisfy the request, return */
4939         if (valid_entry == NULL) {
4940                 PMD_DRV_LOG(ERR, "No valid entry found");
4941                 return -ENOMEM;
4942         }
4943         /**
4944          * The entry have equal queue number as requested,
4945          * remove it from alloc_list.
4946          */
4947         if (valid_entry->len == num) {
4948                 LIST_REMOVE(valid_entry, next);
4949         } else {
4950                 /**
4951                  * The entry have more numbers than requested,
4952                  * create a new entry for alloc_list and minus its
4953                  * queue base and number in free_list.
4954                  */
4955                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4956                 if (entry == NULL) {
4957                         PMD_DRV_LOG(ERR,
4958                                 "Failed to allocate memory for resource pool");
4959                         return -ENOMEM;
4960                 }
4961                 entry->base = valid_entry->base;
4962                 entry->len = num;
4963                 valid_entry->base += num;
4964                 valid_entry->len -= num;
4965                 valid_entry = entry;
4966         }
4967
4968         /* Insert it into alloc list, not sorted */
4969         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4970
4971         pool->num_free -= valid_entry->len;
4972         pool->num_alloc += valid_entry->len;
4973
4974         return valid_entry->base + pool->base;
4975 }
4976
4977 /**
4978  * bitmap_is_subset - Check whether src2 is subset of src1
4979  **/
4980 static inline int
4981 bitmap_is_subset(uint8_t src1, uint8_t src2)
4982 {
4983         return !((src1 ^ src2) & src2);
4984 }
4985
4986 static enum i40e_status_code
4987 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4988 {
4989         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4990
4991         /* If DCB is not supported, only default TC is supported */
4992         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4993                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4994                 return I40E_NOT_SUPPORTED;
4995         }
4996
4997         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4998                 PMD_DRV_LOG(ERR,
4999                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5000                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5001                 return I40E_NOT_SUPPORTED;
5002         }
5003         return I40E_SUCCESS;
5004 }
5005
5006 int
5007 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5008                                 struct i40e_vsi_vlan_pvid_info *info)
5009 {
5010         struct i40e_hw *hw;
5011         struct i40e_vsi_context ctxt;
5012         uint8_t vlan_flags = 0;
5013         int ret;
5014
5015         if (vsi == NULL || info == NULL) {
5016                 PMD_DRV_LOG(ERR, "invalid parameters");
5017                 return I40E_ERR_PARAM;
5018         }
5019
5020         if (info->on) {
5021                 vsi->info.pvid = info->config.pvid;
5022                 /**
5023                  * If insert pvid is enabled, only tagged pkts are
5024                  * allowed to be sent out.
5025                  */
5026                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5027                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5028         } else {
5029                 vsi->info.pvid = 0;
5030                 if (info->config.reject.tagged == 0)
5031                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5032
5033                 if (info->config.reject.untagged == 0)
5034                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5035         }
5036         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5037                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5038         vsi->info.port_vlan_flags |= vlan_flags;
5039         vsi->info.valid_sections =
5040                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5041         memset(&ctxt, 0, sizeof(ctxt));
5042         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5043         ctxt.seid = vsi->seid;
5044
5045         hw = I40E_VSI_TO_HW(vsi);
5046         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5047         if (ret != I40E_SUCCESS)
5048                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5049
5050         return ret;
5051 }
5052
5053 static int
5054 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5055 {
5056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5057         int i, ret;
5058         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5059
5060         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5061         if (ret != I40E_SUCCESS)
5062                 return ret;
5063
5064         if (!vsi->seid) {
5065                 PMD_DRV_LOG(ERR, "seid not valid");
5066                 return -EINVAL;
5067         }
5068
5069         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5070         tc_bw_data.tc_valid_bits = enabled_tcmap;
5071         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5072                 tc_bw_data.tc_bw_credits[i] =
5073                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5074
5075         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5076         if (ret != I40E_SUCCESS) {
5077                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5078                 return ret;
5079         }
5080
5081         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5082                                         sizeof(vsi->info.qs_handle));
5083         return I40E_SUCCESS;
5084 }
5085
5086 static enum i40e_status_code
5087 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5088                                  struct i40e_aqc_vsi_properties_data *info,
5089                                  uint8_t enabled_tcmap)
5090 {
5091         enum i40e_status_code ret;
5092         int i, total_tc = 0;
5093         uint16_t qpnum_per_tc, bsf, qp_idx;
5094
5095         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5096         if (ret != I40E_SUCCESS)
5097                 return ret;
5098
5099         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5100                 if (enabled_tcmap & (1 << i))
5101                         total_tc++;
5102         if (total_tc == 0)
5103                 total_tc = 1;
5104         vsi->enabled_tc = enabled_tcmap;
5105
5106         /* Number of queues per enabled TC */
5107         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5108         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5109         bsf = rte_bsf32(qpnum_per_tc);
5110
5111         /* Adjust the queue number to actual queues that can be applied */
5112         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5113                 vsi->nb_qps = qpnum_per_tc * total_tc;
5114
5115         /**
5116          * Configure TC and queue mapping parameters, for enabled TC,
5117          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5118          * default queue will serve it.
5119          */
5120         qp_idx = 0;
5121         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5122                 if (vsi->enabled_tc & (1 << i)) {
5123                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5124                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5125                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5126                         qp_idx += qpnum_per_tc;
5127                 } else
5128                         info->tc_mapping[i] = 0;
5129         }
5130
5131         /* Associate queue number with VSI */
5132         if (vsi->type == I40E_VSI_SRIOV) {
5133                 info->mapping_flags |=
5134                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5135                 for (i = 0; i < vsi->nb_qps; i++)
5136                         info->queue_mapping[i] =
5137                                 rte_cpu_to_le_16(vsi->base_queue + i);
5138         } else {
5139                 info->mapping_flags |=
5140                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5141                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5142         }
5143         info->valid_sections |=
5144                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5145
5146         return I40E_SUCCESS;
5147 }
5148
5149 static int
5150 i40e_veb_release(struct i40e_veb *veb)
5151 {
5152         struct i40e_vsi *vsi;
5153         struct i40e_hw *hw;
5154
5155         if (veb == NULL)
5156                 return -EINVAL;
5157
5158         if (!TAILQ_EMPTY(&veb->head)) {
5159                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5160                 return -EACCES;
5161         }
5162         /* associate_vsi field is NULL for floating VEB */
5163         if (veb->associate_vsi != NULL) {
5164                 vsi = veb->associate_vsi;
5165                 hw = I40E_VSI_TO_HW(vsi);
5166
5167                 vsi->uplink_seid = veb->uplink_seid;
5168                 vsi->veb = NULL;
5169         } else {
5170                 veb->associate_pf->main_vsi->floating_veb = NULL;
5171                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5172         }
5173
5174         i40e_aq_delete_element(hw, veb->seid, NULL);
5175         rte_free(veb);
5176         return I40E_SUCCESS;
5177 }
5178
5179 /* Setup a veb */
5180 static struct i40e_veb *
5181 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5182 {
5183         struct i40e_veb *veb;
5184         int ret;
5185         struct i40e_hw *hw;
5186
5187         if (pf == NULL) {
5188                 PMD_DRV_LOG(ERR,
5189                             "veb setup failed, associated PF shouldn't null");
5190                 return NULL;
5191         }
5192         hw = I40E_PF_TO_HW(pf);
5193
5194         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5195         if (!veb) {
5196                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5197                 goto fail;
5198         }
5199
5200         veb->associate_vsi = vsi;
5201         veb->associate_pf = pf;
5202         TAILQ_INIT(&veb->head);
5203         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5204
5205         /* create floating veb if vsi is NULL */
5206         if (vsi != NULL) {
5207                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5208                                       I40E_DEFAULT_TCMAP, false,
5209                                       &veb->seid, false, NULL);
5210         } else {
5211                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5212                                       true, &veb->seid, false, NULL);
5213         }
5214
5215         if (ret != I40E_SUCCESS) {
5216                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5217                             hw->aq.asq_last_status);
5218                 goto fail;
5219         }
5220         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5221
5222         /* get statistics index */
5223         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5224                                 &veb->stats_idx, NULL, NULL, NULL);
5225         if (ret != I40E_SUCCESS) {
5226                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5227                             hw->aq.asq_last_status);
5228                 goto fail;
5229         }
5230         /* Get VEB bandwidth, to be implemented */
5231         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5232         if (vsi)
5233                 vsi->uplink_seid = veb->seid;
5234
5235         return veb;
5236 fail:
5237         rte_free(veb);
5238         return NULL;
5239 }
5240
5241 int
5242 i40e_vsi_release(struct i40e_vsi *vsi)
5243 {
5244         struct i40e_pf *pf;
5245         struct i40e_hw *hw;
5246         struct i40e_vsi_list *vsi_list;
5247         void *temp;
5248         int ret;
5249         struct i40e_mac_filter *f;
5250         uint16_t user_param;
5251
5252         if (!vsi)
5253                 return I40E_SUCCESS;
5254
5255         if (!vsi->adapter)
5256                 return -EFAULT;
5257
5258         user_param = vsi->user_param;
5259
5260         pf = I40E_VSI_TO_PF(vsi);
5261         hw = I40E_VSI_TO_HW(vsi);
5262
5263         /* VSI has child to attach, release child first */
5264         if (vsi->veb) {
5265                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5266                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5267                                 return -1;
5268                 }
5269                 i40e_veb_release(vsi->veb);
5270         }
5271
5272         if (vsi->floating_veb) {
5273                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5274                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5275                                 return -1;
5276                 }
5277         }
5278
5279         /* Remove all macvlan filters of the VSI */
5280         i40e_vsi_remove_all_macvlan_filter(vsi);
5281         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5282                 rte_free(f);
5283
5284         if (vsi->type != I40E_VSI_MAIN &&
5285             ((vsi->type != I40E_VSI_SRIOV) ||
5286             !pf->floating_veb_list[user_param])) {
5287                 /* Remove vsi from parent's sibling list */
5288                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5289                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5290                         return I40E_ERR_PARAM;
5291                 }
5292                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5293                                 &vsi->sib_vsi_list, list);
5294
5295                 /* Remove all switch element of the VSI */
5296                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5297                 if (ret != I40E_SUCCESS)
5298                         PMD_DRV_LOG(ERR, "Failed to delete element");
5299         }
5300
5301         if ((vsi->type == I40E_VSI_SRIOV) &&
5302             pf->floating_veb_list[user_param]) {
5303                 /* Remove vsi from parent's sibling list */
5304                 if (vsi->parent_vsi == NULL ||
5305                     vsi->parent_vsi->floating_veb == NULL) {
5306                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5307                         return I40E_ERR_PARAM;
5308                 }
5309                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5310                              &vsi->sib_vsi_list, list);
5311
5312                 /* Remove all switch element of the VSI */
5313                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5314                 if (ret != I40E_SUCCESS)
5315                         PMD_DRV_LOG(ERR, "Failed to delete element");
5316         }
5317
5318         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5319
5320         if (vsi->type != I40E_VSI_SRIOV)
5321                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5322         rte_free(vsi);
5323
5324         return I40E_SUCCESS;
5325 }
5326
5327 static int
5328 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5329 {
5330         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5331         struct i40e_aqc_remove_macvlan_element_data def_filter;
5332         struct i40e_mac_filter_info filter;
5333         int ret;
5334
5335         if (vsi->type != I40E_VSI_MAIN)
5336                 return I40E_ERR_CONFIG;
5337         memset(&def_filter, 0, sizeof(def_filter));
5338         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5339                                         ETH_ADDR_LEN);
5340         def_filter.vlan_tag = 0;
5341         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5342                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5343         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5344         if (ret != I40E_SUCCESS) {
5345                 struct i40e_mac_filter *f;
5346                 struct rte_ether_addr *mac;
5347
5348                 PMD_DRV_LOG(DEBUG,
5349                             "Cannot remove the default macvlan filter");
5350                 /* It needs to add the permanent mac into mac list */
5351                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5352                 if (f == NULL) {
5353                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5354                         return I40E_ERR_NO_MEMORY;
5355                 }
5356                 mac = &f->mac_info.mac_addr;
5357                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5358                                 ETH_ADDR_LEN);
5359                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5360                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5361                 vsi->mac_num++;
5362
5363                 return ret;
5364         }
5365         rte_memcpy(&filter.mac_addr,
5366                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5367         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5368         return i40e_vsi_add_mac(vsi, &filter);
5369 }
5370
5371 /*
5372  * i40e_vsi_get_bw_config - Query VSI BW Information
5373  * @vsi: the VSI to be queried
5374  *
5375  * Returns 0 on success, negative value on failure
5376  */
5377 static enum i40e_status_code
5378 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5379 {
5380         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5381         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5382         struct i40e_hw *hw = &vsi->adapter->hw;
5383         i40e_status ret;
5384         int i;
5385         uint32_t bw_max;
5386
5387         memset(&bw_config, 0, sizeof(bw_config));
5388         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5389         if (ret != I40E_SUCCESS) {
5390                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5391                             hw->aq.asq_last_status);
5392                 return ret;
5393         }
5394
5395         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5396         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5397                                         &ets_sla_config, NULL);
5398         if (ret != I40E_SUCCESS) {
5399                 PMD_DRV_LOG(ERR,
5400                         "VSI failed to get TC bandwdith configuration %u",
5401                         hw->aq.asq_last_status);
5402                 return ret;
5403         }
5404
5405         /* store and print out BW info */
5406         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5407         vsi->bw_info.bw_max = bw_config.max_bw;
5408         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5409         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5410         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5411                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5412                      I40E_16_BIT_WIDTH);
5413         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5414                 vsi->bw_info.bw_ets_share_credits[i] =
5415                                 ets_sla_config.share_credits[i];
5416                 vsi->bw_info.bw_ets_credits[i] =
5417                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5418                 /* 4 bits per TC, 4th bit is reserved */
5419                 vsi->bw_info.bw_ets_max[i] =
5420                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5421                                   RTE_LEN2MASK(3, uint8_t));
5422                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5423                             vsi->bw_info.bw_ets_share_credits[i]);
5424                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5425                             vsi->bw_info.bw_ets_credits[i]);
5426                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5427                             vsi->bw_info.bw_ets_max[i]);
5428         }
5429
5430         return I40E_SUCCESS;
5431 }
5432
5433 /* i40e_enable_pf_lb
5434  * @pf: pointer to the pf structure
5435  *
5436  * allow loopback on pf
5437  */
5438 static inline void
5439 i40e_enable_pf_lb(struct i40e_pf *pf)
5440 {
5441         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5442         struct i40e_vsi_context ctxt;
5443         int ret;
5444
5445         /* Use the FW API if FW >= v5.0 */
5446         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5447                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5448                 return;
5449         }
5450
5451         memset(&ctxt, 0, sizeof(ctxt));
5452         ctxt.seid = pf->main_vsi_seid;
5453         ctxt.pf_num = hw->pf_id;
5454         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5455         if (ret) {
5456                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5457                             ret, hw->aq.asq_last_status);
5458                 return;
5459         }
5460         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5461         ctxt.info.valid_sections =
5462                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5463         ctxt.info.switch_id |=
5464                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5465
5466         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5467         if (ret)
5468                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5469                             hw->aq.asq_last_status);
5470 }
5471
5472 /* Setup a VSI */
5473 struct i40e_vsi *
5474 i40e_vsi_setup(struct i40e_pf *pf,
5475                enum i40e_vsi_type type,
5476                struct i40e_vsi *uplink_vsi,
5477                uint16_t user_param)
5478 {
5479         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5480         struct i40e_vsi *vsi;
5481         struct i40e_mac_filter_info filter;
5482         int ret;
5483         struct i40e_vsi_context ctxt;
5484         struct rte_ether_addr broadcast =
5485                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5486
5487         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5488             uplink_vsi == NULL) {
5489                 PMD_DRV_LOG(ERR,
5490                         "VSI setup failed, VSI link shouldn't be NULL");
5491                 return NULL;
5492         }
5493
5494         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5495                 PMD_DRV_LOG(ERR,
5496                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5497                 return NULL;
5498         }
5499
5500         /* two situations
5501          * 1.type is not MAIN and uplink vsi is not NULL
5502          * If uplink vsi didn't setup VEB, create one first under veb field
5503          * 2.type is SRIOV and the uplink is NULL
5504          * If floating VEB is NULL, create one veb under floating veb field
5505          */
5506
5507         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5508             uplink_vsi->veb == NULL) {
5509                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5510
5511                 if (uplink_vsi->veb == NULL) {
5512                         PMD_DRV_LOG(ERR, "VEB setup failed");
5513                         return NULL;
5514                 }
5515                 /* set ALLOWLOOPBACk on pf, when veb is created */
5516                 i40e_enable_pf_lb(pf);
5517         }
5518
5519         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5520             pf->main_vsi->floating_veb == NULL) {
5521                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5522
5523                 if (pf->main_vsi->floating_veb == NULL) {
5524                         PMD_DRV_LOG(ERR, "VEB setup failed");
5525                         return NULL;
5526                 }
5527         }
5528
5529         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5530         if (!vsi) {
5531                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5532                 return NULL;
5533         }
5534         TAILQ_INIT(&vsi->mac_list);
5535         vsi->type = type;
5536         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5537         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5538         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5539         vsi->user_param = user_param;
5540         vsi->vlan_anti_spoof_on = 0;
5541         vsi->vlan_filter_on = 0;
5542         /* Allocate queues */
5543         switch (vsi->type) {
5544         case I40E_VSI_MAIN  :
5545                 vsi->nb_qps = pf->lan_nb_qps;
5546                 break;
5547         case I40E_VSI_SRIOV :
5548                 vsi->nb_qps = pf->vf_nb_qps;
5549                 break;
5550         case I40E_VSI_VMDQ2:
5551                 vsi->nb_qps = pf->vmdq_nb_qps;
5552                 break;
5553         case I40E_VSI_FDIR:
5554                 vsi->nb_qps = pf->fdir_nb_qps;
5555                 break;
5556         default:
5557                 goto fail_mem;
5558         }
5559         /*
5560          * The filter status descriptor is reported in rx queue 0,
5561          * while the tx queue for fdir filter programming has no
5562          * such constraints, can be non-zero queues.
5563          * To simplify it, choose FDIR vsi use queue 0 pair.
5564          * To make sure it will use queue 0 pair, queue allocation
5565          * need be done before this function is called
5566          */
5567         if (type != I40E_VSI_FDIR) {
5568                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5569                         if (ret < 0) {
5570                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5571                                                 vsi->seid, ret);
5572                                 goto fail_mem;
5573                         }
5574                         vsi->base_queue = ret;
5575         } else
5576                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5577
5578         /* VF has MSIX interrupt in VF range, don't allocate here */
5579         if (type == I40E_VSI_MAIN) {
5580                 if (pf->support_multi_driver) {
5581                         /* If support multi-driver, need to use INT0 instead of
5582                          * allocating from msix pool. The Msix pool is init from
5583                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5584                          * to 1 without calling i40e_res_pool_alloc.
5585                          */
5586                         vsi->msix_intr = 0;
5587                         vsi->nb_msix = 1;
5588                 } else {
5589                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5590                                                   RTE_MIN(vsi->nb_qps,
5591                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5592                         if (ret < 0) {
5593                                 PMD_DRV_LOG(ERR,
5594                                             "VSI MAIN %d get heap failed %d",
5595                                             vsi->seid, ret);
5596                                 goto fail_queue_alloc;
5597                         }
5598                         vsi->msix_intr = ret;
5599                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5600                                                RTE_MAX_RXTX_INTR_VEC_ID);
5601                 }
5602         } else if (type != I40E_VSI_SRIOV) {
5603                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5604                 if (ret < 0) {
5605                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5606                         goto fail_queue_alloc;
5607                 }
5608                 vsi->msix_intr = ret;
5609                 vsi->nb_msix = 1;
5610         } else {
5611                 vsi->msix_intr = 0;
5612                 vsi->nb_msix = 0;
5613         }
5614
5615         /* Add VSI */
5616         if (type == I40E_VSI_MAIN) {
5617                 /* For main VSI, no need to add since it's default one */
5618                 vsi->uplink_seid = pf->mac_seid;
5619                 vsi->seid = pf->main_vsi_seid;
5620                 /* Bind queues with specific MSIX interrupt */
5621                 /**
5622                  * Needs 2 interrupt at least, one for misc cause which will
5623                  * enabled from OS side, Another for queues binding the
5624                  * interrupt from device side only.
5625                  */
5626
5627                 /* Get default VSI parameters from hardware */
5628                 memset(&ctxt, 0, sizeof(ctxt));
5629                 ctxt.seid = vsi->seid;
5630                 ctxt.pf_num = hw->pf_id;
5631                 ctxt.uplink_seid = vsi->uplink_seid;
5632                 ctxt.vf_num = 0;
5633                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5634                 if (ret != I40E_SUCCESS) {
5635                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5636                         goto fail_msix_alloc;
5637                 }
5638                 rte_memcpy(&vsi->info, &ctxt.info,
5639                         sizeof(struct i40e_aqc_vsi_properties_data));
5640                 vsi->vsi_id = ctxt.vsi_number;
5641                 vsi->info.valid_sections = 0;
5642
5643                 /* Configure tc, enabled TC0 only */
5644                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5645                         I40E_SUCCESS) {
5646                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5647                         goto fail_msix_alloc;
5648                 }
5649
5650                 /* TC, queue mapping */
5651                 memset(&ctxt, 0, sizeof(ctxt));
5652                 vsi->info.valid_sections |=
5653                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5654                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5655                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5656                 rte_memcpy(&ctxt.info, &vsi->info,
5657                         sizeof(struct i40e_aqc_vsi_properties_data));
5658                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5659                                                 I40E_DEFAULT_TCMAP);
5660                 if (ret != I40E_SUCCESS) {
5661                         PMD_DRV_LOG(ERR,
5662                                 "Failed to configure TC queue mapping");
5663                         goto fail_msix_alloc;
5664                 }
5665                 ctxt.seid = vsi->seid;
5666                 ctxt.pf_num = hw->pf_id;
5667                 ctxt.uplink_seid = vsi->uplink_seid;
5668                 ctxt.vf_num = 0;
5669
5670                 /* Update VSI parameters */
5671                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5672                 if (ret != I40E_SUCCESS) {
5673                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5674                         goto fail_msix_alloc;
5675                 }
5676
5677                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5678                                                 sizeof(vsi->info.tc_mapping));
5679                 rte_memcpy(&vsi->info.queue_mapping,
5680                                 &ctxt.info.queue_mapping,
5681                         sizeof(vsi->info.queue_mapping));
5682                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5683                 vsi->info.valid_sections = 0;
5684
5685                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5686                                 ETH_ADDR_LEN);
5687
5688                 /**
5689                  * Updating default filter settings are necessary to prevent
5690                  * reception of tagged packets.
5691                  * Some old firmware configurations load a default macvlan
5692                  * filter which accepts both tagged and untagged packets.
5693                  * The updating is to use a normal filter instead if needed.
5694                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5695                  * The firmware with correct configurations load the default
5696                  * macvlan filter which is expected and cannot be removed.
5697                  */
5698                 i40e_update_default_filter_setting(vsi);
5699                 i40e_config_qinq(hw, vsi);
5700         } else if (type == I40E_VSI_SRIOV) {
5701                 memset(&ctxt, 0, sizeof(ctxt));
5702                 /**
5703                  * For other VSI, the uplink_seid equals to uplink VSI's
5704                  * uplink_seid since they share same VEB
5705                  */
5706                 if (uplink_vsi == NULL)
5707                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5708                 else
5709                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5710                 ctxt.pf_num = hw->pf_id;
5711                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5712                 ctxt.uplink_seid = vsi->uplink_seid;
5713                 ctxt.connection_type = 0x1;
5714                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5715
5716                 /* Use the VEB configuration if FW >= v5.0 */
5717                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5718                         /* Configure switch ID */
5719                         ctxt.info.valid_sections |=
5720                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5721                         ctxt.info.switch_id =
5722                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5723                 }
5724
5725                 /* Configure port/vlan */
5726                 ctxt.info.valid_sections |=
5727                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5728                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5729                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5730                                                 hw->func_caps.enabled_tcmap);
5731                 if (ret != I40E_SUCCESS) {
5732                         PMD_DRV_LOG(ERR,
5733                                 "Failed to configure TC queue mapping");
5734                         goto fail_msix_alloc;
5735                 }
5736
5737                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5738                 ctxt.info.valid_sections |=
5739                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5740                 /**
5741                  * Since VSI is not created yet, only configure parameter,
5742                  * will add vsi below.
5743                  */
5744
5745                 i40e_config_qinq(hw, vsi);
5746         } else if (type == I40E_VSI_VMDQ2) {
5747                 memset(&ctxt, 0, sizeof(ctxt));
5748                 /*
5749                  * For other VSI, the uplink_seid equals to uplink VSI's
5750                  * uplink_seid since they share same VEB
5751                  */
5752                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5753                 ctxt.pf_num = hw->pf_id;
5754                 ctxt.vf_num = 0;
5755                 ctxt.uplink_seid = vsi->uplink_seid;
5756                 ctxt.connection_type = 0x1;
5757                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5758
5759                 ctxt.info.valid_sections |=
5760                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5761                 /* user_param carries flag to enable loop back */
5762                 if (user_param) {
5763                         ctxt.info.switch_id =
5764                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5765                         ctxt.info.switch_id |=
5766                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5767                 }
5768
5769                 /* Configure port/vlan */
5770                 ctxt.info.valid_sections |=
5771                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5772                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5773                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5774                                                 I40E_DEFAULT_TCMAP);
5775                 if (ret != I40E_SUCCESS) {
5776                         PMD_DRV_LOG(ERR,
5777                                 "Failed to configure TC queue mapping");
5778                         goto fail_msix_alloc;
5779                 }
5780                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5781                 ctxt.info.valid_sections |=
5782                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5783         } else if (type == I40E_VSI_FDIR) {
5784                 memset(&ctxt, 0, sizeof(ctxt));
5785                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5786                 ctxt.pf_num = hw->pf_id;
5787                 ctxt.vf_num = 0;
5788                 ctxt.uplink_seid = vsi->uplink_seid;
5789                 ctxt.connection_type = 0x1;     /* regular data port */
5790                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5791                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5792                                                 I40E_DEFAULT_TCMAP);
5793                 if (ret != I40E_SUCCESS) {
5794                         PMD_DRV_LOG(ERR,
5795                                 "Failed to configure TC queue mapping.");
5796                         goto fail_msix_alloc;
5797                 }
5798                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5799                 ctxt.info.valid_sections |=
5800                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5801         } else {
5802                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5803                 goto fail_msix_alloc;
5804         }
5805
5806         if (vsi->type != I40E_VSI_MAIN) {
5807                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5808                 if (ret != I40E_SUCCESS) {
5809                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5810                                     hw->aq.asq_last_status);
5811                         goto fail_msix_alloc;
5812                 }
5813                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5814                 vsi->info.valid_sections = 0;
5815                 vsi->seid = ctxt.seid;
5816                 vsi->vsi_id = ctxt.vsi_number;
5817                 vsi->sib_vsi_list.vsi = vsi;
5818                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5819                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5820                                           &vsi->sib_vsi_list, list);
5821                 } else {
5822                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5823                                           &vsi->sib_vsi_list, list);
5824                 }
5825         }
5826
5827         /* MAC/VLAN configuration */
5828         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5829         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5830
5831         ret = i40e_vsi_add_mac(vsi, &filter);
5832         if (ret != I40E_SUCCESS) {
5833                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5834                 goto fail_msix_alloc;
5835         }
5836
5837         /* Get VSI BW information */
5838         i40e_vsi_get_bw_config(vsi);
5839         return vsi;
5840 fail_msix_alloc:
5841         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5842 fail_queue_alloc:
5843         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5844 fail_mem:
5845         rte_free(vsi);
5846         return NULL;
5847 }
5848
5849 /* Configure vlan filter on or off */
5850 int
5851 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5852 {
5853         int i, num;
5854         struct i40e_mac_filter *f;
5855         void *temp;
5856         struct i40e_mac_filter_info *mac_filter;
5857         enum rte_mac_filter_type desired_filter;
5858         int ret = I40E_SUCCESS;
5859
5860         if (on) {
5861                 /* Filter to match MAC and VLAN */
5862                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5863         } else {
5864                 /* Filter to match only MAC */
5865                 desired_filter = RTE_MAC_PERFECT_MATCH;
5866         }
5867
5868         num = vsi->mac_num;
5869
5870         mac_filter = rte_zmalloc("mac_filter_info_data",
5871                                  num * sizeof(*mac_filter), 0);
5872         if (mac_filter == NULL) {
5873                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5874                 return I40E_ERR_NO_MEMORY;
5875         }
5876
5877         i = 0;
5878
5879         /* Remove all existing mac */
5880         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5881                 mac_filter[i] = f->mac_info;
5882                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5883                 if (ret) {
5884                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5885                                     on ? "enable" : "disable");
5886                         goto DONE;
5887                 }
5888                 i++;
5889         }
5890
5891         /* Override with new filter */
5892         for (i = 0; i < num; i++) {
5893                 mac_filter[i].filter_type = desired_filter;
5894                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5895                 if (ret) {
5896                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5897                                     on ? "enable" : "disable");
5898                         goto DONE;
5899                 }
5900         }
5901
5902 DONE:
5903         rte_free(mac_filter);
5904         return ret;
5905 }
5906
5907 /* Configure vlan stripping on or off */
5908 int
5909 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5910 {
5911         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5912         struct i40e_vsi_context ctxt;
5913         uint8_t vlan_flags;
5914         int ret = I40E_SUCCESS;
5915
5916         /* Check if it has been already on or off */
5917         if (vsi->info.valid_sections &
5918                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5919                 if (on) {
5920                         if ((vsi->info.port_vlan_flags &
5921                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5922                                 return 0; /* already on */
5923                 } else {
5924                         if ((vsi->info.port_vlan_flags &
5925                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5926                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5927                                 return 0; /* already off */
5928                 }
5929         }
5930
5931         if (on)
5932                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5933         else
5934                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5935         vsi->info.valid_sections =
5936                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5937         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5938         vsi->info.port_vlan_flags |= vlan_flags;
5939         ctxt.seid = vsi->seid;
5940         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5941         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5942         if (ret)
5943                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5944                             on ? "enable" : "disable");
5945
5946         return ret;
5947 }
5948
5949 static int
5950 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5951 {
5952         struct rte_eth_dev_data *data = dev->data;
5953         int ret;
5954         int mask = 0;
5955
5956         /* Apply vlan offload setting */
5957         mask = ETH_VLAN_STRIP_MASK |
5958                ETH_VLAN_FILTER_MASK |
5959                ETH_VLAN_EXTEND_MASK;
5960         ret = i40e_vlan_offload_set(dev, mask);
5961         if (ret) {
5962                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5963                 return ret;
5964         }
5965
5966         /* Apply pvid setting */
5967         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5968                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5969         if (ret)
5970                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5971
5972         return ret;
5973 }
5974
5975 static int
5976 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5977 {
5978         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5979
5980         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5981 }
5982
5983 static int
5984 i40e_update_flow_control(struct i40e_hw *hw)
5985 {
5986 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5987         struct i40e_link_status link_status;
5988         uint32_t rxfc = 0, txfc = 0, reg;
5989         uint8_t an_info;
5990         int ret;
5991
5992         memset(&link_status, 0, sizeof(link_status));
5993         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5994         if (ret != I40E_SUCCESS) {
5995                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5996                 goto write_reg; /* Disable flow control */
5997         }
5998
5999         an_info = hw->phy.link_info.an_info;
6000         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6001                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6002                 ret = I40E_ERR_NOT_READY;
6003                 goto write_reg; /* Disable flow control */
6004         }
6005         /**
6006          * If link auto negotiation is enabled, flow control needs to
6007          * be configured according to it
6008          */
6009         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6010         case I40E_LINK_PAUSE_RXTX:
6011                 rxfc = 1;
6012                 txfc = 1;
6013                 hw->fc.current_mode = I40E_FC_FULL;
6014                 break;
6015         case I40E_AQ_LINK_PAUSE_RX:
6016                 rxfc = 1;
6017                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6018                 break;
6019         case I40E_AQ_LINK_PAUSE_TX:
6020                 txfc = 1;
6021                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6022                 break;
6023         default:
6024                 hw->fc.current_mode = I40E_FC_NONE;
6025                 break;
6026         }
6027
6028 write_reg:
6029         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6030                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6031         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6032         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6033         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6034         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6035
6036         return ret;
6037 }
6038
6039 /* PF setup */
6040 static int
6041 i40e_pf_setup(struct i40e_pf *pf)
6042 {
6043         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6044         struct i40e_filter_control_settings settings;
6045         struct i40e_vsi *vsi;
6046         int ret;
6047
6048         /* Clear all stats counters */
6049         pf->offset_loaded = FALSE;
6050         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6051         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6052         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6053         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6054
6055         ret = i40e_pf_get_switch_config(pf);
6056         if (ret != I40E_SUCCESS) {
6057                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6058                 return ret;
6059         }
6060
6061         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6062         if (ret)
6063                 PMD_INIT_LOG(WARNING,
6064                         "failed to allocate switch domain for device %d", ret);
6065
6066         if (pf->flags & I40E_FLAG_FDIR) {
6067                 /* make queue allocated first, let FDIR use queue pair 0*/
6068                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6069                 if (ret != I40E_FDIR_QUEUE_ID) {
6070                         PMD_DRV_LOG(ERR,
6071                                 "queue allocation fails for FDIR: ret =%d",
6072                                 ret);
6073                         pf->flags &= ~I40E_FLAG_FDIR;
6074                 }
6075         }
6076         /*  main VSI setup */
6077         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6078         if (!vsi) {
6079                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6080                 return I40E_ERR_NOT_READY;
6081         }
6082         pf->main_vsi = vsi;
6083
6084         /* Configure filter control */
6085         memset(&settings, 0, sizeof(settings));
6086         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6087                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6088         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6089                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6090         else {
6091                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6092                         hw->func_caps.rss_table_size);
6093                 return I40E_ERR_PARAM;
6094         }
6095         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6096                 hw->func_caps.rss_table_size);
6097         pf->hash_lut_size = hw->func_caps.rss_table_size;
6098
6099         /* Enable ethtype and macvlan filters */
6100         settings.enable_ethtype = TRUE;
6101         settings.enable_macvlan = TRUE;
6102         ret = i40e_set_filter_control(hw, &settings);
6103         if (ret)
6104                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6105                                                                 ret);
6106
6107         /* Update flow control according to the auto negotiation */
6108         i40e_update_flow_control(hw);
6109
6110         return I40E_SUCCESS;
6111 }
6112
6113 int
6114 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6115 {
6116         uint32_t reg;
6117         uint16_t j;
6118
6119         /**
6120          * Set or clear TX Queue Disable flags,
6121          * which is required by hardware.
6122          */
6123         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6124         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6125
6126         /* Wait until the request is finished */
6127         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6128                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6129                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6130                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6131                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6132                                                         & 0x1))) {
6133                         break;
6134                 }
6135         }
6136         if (on) {
6137                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6138                         return I40E_SUCCESS; /* already on, skip next steps */
6139
6140                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6141                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6142         } else {
6143                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6144                         return I40E_SUCCESS; /* already off, skip next steps */
6145                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6146         }
6147         /* Write the register */
6148         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6149         /* Check the result */
6150         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6151                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6152                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6153                 if (on) {
6154                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6155                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6156                                 break;
6157                 } else {
6158                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6159                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6160                                 break;
6161                 }
6162         }
6163         /* Check if it is timeout */
6164         if (j >= I40E_CHK_Q_ENA_COUNT) {
6165                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6166                             (on ? "enable" : "disable"), q_idx);
6167                 return I40E_ERR_TIMEOUT;
6168         }
6169
6170         return I40E_SUCCESS;
6171 }
6172
6173 /* Swith on or off the tx queues */
6174 static int
6175 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6176 {
6177         struct rte_eth_dev_data *dev_data = pf->dev_data;
6178         struct i40e_tx_queue *txq;
6179         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6180         uint16_t i;
6181         int ret;
6182
6183         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6184                 txq = dev_data->tx_queues[i];
6185                 /* Don't operate the queue if not configured or
6186                  * if starting only per queue */
6187                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6188                         continue;
6189                 if (on)
6190                         ret = i40e_dev_tx_queue_start(dev, i);
6191                 else
6192                         ret = i40e_dev_tx_queue_stop(dev, i);
6193                 if ( ret != I40E_SUCCESS)
6194                         return ret;
6195         }
6196
6197         return I40E_SUCCESS;
6198 }
6199
6200 int
6201 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6202 {
6203         uint32_t reg;
6204         uint16_t j;
6205
6206         /* Wait until the request is finished */
6207         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6208                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6209                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6210                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6211                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6212                         break;
6213         }
6214
6215         if (on) {
6216                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6217                         return I40E_SUCCESS; /* Already on, skip next steps */
6218                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6219         } else {
6220                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6221                         return I40E_SUCCESS; /* Already off, skip next steps */
6222                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6223         }
6224
6225         /* Write the register */
6226         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6227         /* Check the result */
6228         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6229                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6230                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6231                 if (on) {
6232                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6233                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6234                                 break;
6235                 } else {
6236                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6237                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6238                                 break;
6239                 }
6240         }
6241
6242         /* Check if it is timeout */
6243         if (j >= I40E_CHK_Q_ENA_COUNT) {
6244                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6245                             (on ? "enable" : "disable"), q_idx);
6246                 return I40E_ERR_TIMEOUT;
6247         }
6248
6249         return I40E_SUCCESS;
6250 }
6251 /* Switch on or off the rx queues */
6252 static int
6253 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6254 {
6255         struct rte_eth_dev_data *dev_data = pf->dev_data;
6256         struct i40e_rx_queue *rxq;
6257         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6258         uint16_t i;
6259         int ret;
6260
6261         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6262                 rxq = dev_data->rx_queues[i];
6263                 /* Don't operate the queue if not configured or
6264                  * if starting only per queue */
6265                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6266                         continue;
6267                 if (on)
6268                         ret = i40e_dev_rx_queue_start(dev, i);
6269                 else
6270                         ret = i40e_dev_rx_queue_stop(dev, i);
6271                 if (ret != I40E_SUCCESS)
6272                         return ret;
6273         }
6274
6275         return I40E_SUCCESS;
6276 }
6277
6278 /* Switch on or off all the rx/tx queues */
6279 int
6280 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6281 {
6282         int ret;
6283
6284         if (on) {
6285                 /* enable rx queues before enabling tx queues */
6286                 ret = i40e_dev_switch_rx_queues(pf, on);
6287                 if (ret) {
6288                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6289                         return ret;
6290                 }
6291                 ret = i40e_dev_switch_tx_queues(pf, on);
6292         } else {
6293                 /* Stop tx queues before stopping rx queues */
6294                 ret = i40e_dev_switch_tx_queues(pf, on);
6295                 if (ret) {
6296                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6297                         return ret;
6298                 }
6299                 ret = i40e_dev_switch_rx_queues(pf, on);
6300         }
6301
6302         return ret;
6303 }
6304
6305 /* Initialize VSI for TX */
6306 static int
6307 i40e_dev_tx_init(struct i40e_pf *pf)
6308 {
6309         struct rte_eth_dev_data *data = pf->dev_data;
6310         uint16_t i;
6311         uint32_t ret = I40E_SUCCESS;
6312         struct i40e_tx_queue *txq;
6313
6314         for (i = 0; i < data->nb_tx_queues; i++) {
6315                 txq = data->tx_queues[i];
6316                 if (!txq || !txq->q_set)
6317                         continue;
6318                 ret = i40e_tx_queue_init(txq);
6319                 if (ret != I40E_SUCCESS)
6320                         break;
6321         }
6322         if (ret == I40E_SUCCESS)
6323                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6324                                      ->eth_dev);
6325
6326         return ret;
6327 }
6328
6329 /* Initialize VSI for RX */
6330 static int
6331 i40e_dev_rx_init(struct i40e_pf *pf)
6332 {
6333         struct rte_eth_dev_data *data = pf->dev_data;
6334         int ret = I40E_SUCCESS;
6335         uint16_t i;
6336         struct i40e_rx_queue *rxq;
6337
6338         i40e_pf_config_mq_rx(pf);
6339         for (i = 0; i < data->nb_rx_queues; i++) {
6340                 rxq = data->rx_queues[i];
6341                 if (!rxq || !rxq->q_set)
6342                         continue;
6343
6344                 ret = i40e_rx_queue_init(rxq);
6345                 if (ret != I40E_SUCCESS) {
6346                         PMD_DRV_LOG(ERR,
6347                                 "Failed to do RX queue initialization");
6348                         break;
6349                 }
6350         }
6351         if (ret == I40E_SUCCESS)
6352                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6353                                      ->eth_dev);
6354
6355         return ret;
6356 }
6357
6358 static int
6359 i40e_dev_rxtx_init(struct i40e_pf *pf)
6360 {
6361         int err;
6362
6363         err = i40e_dev_tx_init(pf);
6364         if (err) {
6365                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6366                 return err;
6367         }
6368         err = i40e_dev_rx_init(pf);
6369         if (err) {
6370                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6371                 return err;
6372         }
6373
6374         return err;
6375 }
6376
6377 static int
6378 i40e_vmdq_setup(struct rte_eth_dev *dev)
6379 {
6380         struct rte_eth_conf *conf = &dev->data->dev_conf;
6381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6382         int i, err, conf_vsis, j, loop;
6383         struct i40e_vsi *vsi;
6384         struct i40e_vmdq_info *vmdq_info;
6385         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6386         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6387
6388         /*
6389          * Disable interrupt to avoid message from VF. Furthermore, it will
6390          * avoid race condition in VSI creation/destroy.
6391          */
6392         i40e_pf_disable_irq0(hw);
6393
6394         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6395                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6396                 return -ENOTSUP;
6397         }
6398
6399         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6400         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6401                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6402                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6403                         pf->max_nb_vmdq_vsi);
6404                 return -ENOTSUP;
6405         }
6406
6407         if (pf->vmdq != NULL) {
6408                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6409                 return 0;
6410         }
6411
6412         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6413                                 sizeof(*vmdq_info) * conf_vsis, 0);
6414
6415         if (pf->vmdq == NULL) {
6416                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6417                 return -ENOMEM;
6418         }
6419
6420         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6421
6422         /* Create VMDQ VSI */
6423         for (i = 0; i < conf_vsis; i++) {
6424                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6425                                 vmdq_conf->enable_loop_back);
6426                 if (vsi == NULL) {
6427                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6428                         err = -1;
6429                         goto err_vsi_setup;
6430                 }
6431                 vmdq_info = &pf->vmdq[i];
6432                 vmdq_info->pf = pf;
6433                 vmdq_info->vsi = vsi;
6434         }
6435         pf->nb_cfg_vmdq_vsi = conf_vsis;
6436
6437         /* Configure Vlan */
6438         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6439         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6440                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6441                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6442                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6443                                         vmdq_conf->pool_map[i].vlan_id, j);
6444
6445                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6446                                                 vmdq_conf->pool_map[i].vlan_id);
6447                                 if (err) {
6448                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6449                                         err = -1;
6450                                         goto err_vsi_setup;
6451                                 }
6452                         }
6453                 }
6454         }
6455
6456         i40e_pf_enable_irq0(hw);
6457
6458         return 0;
6459
6460 err_vsi_setup:
6461         for (i = 0; i < conf_vsis; i++)
6462                 if (pf->vmdq[i].vsi == NULL)
6463                         break;
6464                 else
6465                         i40e_vsi_release(pf->vmdq[i].vsi);
6466
6467         rte_free(pf->vmdq);
6468         pf->vmdq = NULL;
6469         i40e_pf_enable_irq0(hw);
6470         return err;
6471 }
6472
6473 static void
6474 i40e_stat_update_32(struct i40e_hw *hw,
6475                    uint32_t reg,
6476                    bool offset_loaded,
6477                    uint64_t *offset,
6478                    uint64_t *stat)
6479 {
6480         uint64_t new_data;
6481
6482         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6483         if (!offset_loaded)
6484                 *offset = new_data;
6485
6486         if (new_data >= *offset)
6487                 *stat = (uint64_t)(new_data - *offset);
6488         else
6489                 *stat = (uint64_t)((new_data +
6490                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6491 }
6492
6493 static void
6494 i40e_stat_update_48(struct i40e_hw *hw,
6495                    uint32_t hireg,
6496                    uint32_t loreg,
6497                    bool offset_loaded,
6498                    uint64_t *offset,
6499                    uint64_t *stat)
6500 {
6501         uint64_t new_data;
6502
6503         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6504         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6505                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6506
6507         if (!offset_loaded)
6508                 *offset = new_data;
6509
6510         if (new_data >= *offset)
6511                 *stat = new_data - *offset;
6512         else
6513                 *stat = (uint64_t)((new_data +
6514                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6515
6516         *stat &= I40E_48_BIT_MASK;
6517 }
6518
6519 /* Disable IRQ0 */
6520 void
6521 i40e_pf_disable_irq0(struct i40e_hw *hw)
6522 {
6523         /* Disable all interrupt types */
6524         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6525                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6526         I40E_WRITE_FLUSH(hw);
6527 }
6528
6529 /* Enable IRQ0 */
6530 void
6531 i40e_pf_enable_irq0(struct i40e_hw *hw)
6532 {
6533         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6534                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6535                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6536                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6537         I40E_WRITE_FLUSH(hw);
6538 }
6539
6540 static void
6541 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6542 {
6543         /* read pending request and disable first */
6544         i40e_pf_disable_irq0(hw);
6545         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6546         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6547                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6548
6549         if (no_queue)
6550                 /* Link no queues with irq0 */
6551                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6552                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6553 }
6554
6555 static void
6556 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6557 {
6558         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6560         int i;
6561         uint16_t abs_vf_id;
6562         uint32_t index, offset, val;
6563
6564         if (!pf->vfs)
6565                 return;
6566         /**
6567          * Try to find which VF trigger a reset, use absolute VF id to access
6568          * since the reg is global register.
6569          */
6570         for (i = 0; i < pf->vf_num; i++) {
6571                 abs_vf_id = hw->func_caps.vf_base_id + i;
6572                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6573                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6574                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6575                 /* VFR event occurred */
6576                 if (val & (0x1 << offset)) {
6577                         int ret;
6578
6579                         /* Clear the event first */
6580                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6581                                                         (0x1 << offset));
6582                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6583                         /**
6584                          * Only notify a VF reset event occurred,
6585                          * don't trigger another SW reset
6586                          */
6587                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6588                         if (ret != I40E_SUCCESS)
6589                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6590                 }
6591         }
6592 }
6593
6594 static void
6595 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6596 {
6597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6598         int i;
6599
6600         for (i = 0; i < pf->vf_num; i++)
6601                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6602 }
6603
6604 static void
6605 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6606 {
6607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6608         struct i40e_arq_event_info info;
6609         uint16_t pending, opcode;
6610         int ret;
6611
6612         info.buf_len = I40E_AQ_BUF_SZ;
6613         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6614         if (!info.msg_buf) {
6615                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6616                 return;
6617         }
6618
6619         pending = 1;
6620         while (pending) {
6621                 ret = i40e_clean_arq_element(hw, &info, &pending);
6622
6623                 if (ret != I40E_SUCCESS) {
6624                         PMD_DRV_LOG(INFO,
6625                                 "Failed to read msg from AdminQ, aq_err: %u",
6626                                 hw->aq.asq_last_status);
6627                         break;
6628                 }
6629                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6630
6631                 switch (opcode) {
6632                 case i40e_aqc_opc_send_msg_to_pf:
6633                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6634                         i40e_pf_host_handle_vf_msg(dev,
6635                                         rte_le_to_cpu_16(info.desc.retval),
6636                                         rte_le_to_cpu_32(info.desc.cookie_high),
6637                                         rte_le_to_cpu_32(info.desc.cookie_low),
6638                                         info.msg_buf,
6639                                         info.msg_len);
6640                         break;
6641                 case i40e_aqc_opc_get_link_status:
6642                         ret = i40e_dev_link_update(dev, 0);
6643                         if (!ret)
6644                                 _rte_eth_dev_callback_process(dev,
6645                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6646                         break;
6647                 default:
6648                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6649                                     opcode);
6650                         break;
6651                 }
6652         }
6653         rte_free(info.msg_buf);
6654 }
6655
6656 /**
6657  * Interrupt handler triggered by NIC  for handling
6658  * specific interrupt.
6659  *
6660  * @param handle
6661  *  Pointer to interrupt handle.
6662  * @param param
6663  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6664  *
6665  * @return
6666  *  void
6667  */
6668 static void
6669 i40e_dev_interrupt_handler(void *param)
6670 {
6671         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6672         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6673         uint32_t icr0;
6674
6675         /* Disable interrupt */
6676         i40e_pf_disable_irq0(hw);
6677
6678         /* read out interrupt causes */
6679         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6680
6681         /* No interrupt event indicated */
6682         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6683                 PMD_DRV_LOG(INFO, "No interrupt event");
6684                 goto done;
6685         }
6686         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6687                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6688         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6689                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6690         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6691                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6692         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6693                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6694         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6695                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6696         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6697                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6698         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6699                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6700
6701         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6702                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6703                 i40e_dev_handle_vfr_event(dev);
6704         }
6705         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6706                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6707                 i40e_dev_handle_aq_msg(dev);
6708         }
6709
6710 done:
6711         /* Enable interrupt */
6712         i40e_pf_enable_irq0(hw);
6713 }
6714
6715 static void
6716 i40e_dev_alarm_handler(void *param)
6717 {
6718         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6720         uint32_t icr0;
6721
6722         /* Disable interrupt */
6723         i40e_pf_disable_irq0(hw);
6724
6725         /* read out interrupt causes */
6726         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6727
6728         /* No interrupt event indicated */
6729         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6730                 goto done;
6731         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6732                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6733         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6734                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6735         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6736                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6737         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6738                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6739         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6740                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6741         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6742                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6743         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6744                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6745
6746         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6747                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6748                 i40e_dev_handle_vfr_event(dev);
6749         }
6750         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6751                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6752                 i40e_dev_handle_aq_msg(dev);
6753         }
6754
6755 done:
6756         /* Enable interrupt */
6757         i40e_pf_enable_irq0(hw);
6758         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6759                           i40e_dev_alarm_handler, dev);
6760 }
6761
6762 int
6763 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6764                          struct i40e_macvlan_filter *filter,
6765                          int total)
6766 {
6767         int ele_num, ele_buff_size;
6768         int num, actual_num, i;
6769         uint16_t flags;
6770         int ret = I40E_SUCCESS;
6771         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6772         struct i40e_aqc_add_macvlan_element_data *req_list;
6773
6774         if (filter == NULL  || total == 0)
6775                 return I40E_ERR_PARAM;
6776         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6777         ele_buff_size = hw->aq.asq_buf_size;
6778
6779         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6780         if (req_list == NULL) {
6781                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6782                 return I40E_ERR_NO_MEMORY;
6783         }
6784
6785         num = 0;
6786         do {
6787                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6788                 memset(req_list, 0, ele_buff_size);
6789
6790                 for (i = 0; i < actual_num; i++) {
6791                         rte_memcpy(req_list[i].mac_addr,
6792                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6793                         req_list[i].vlan_tag =
6794                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6795
6796                         switch (filter[num + i].filter_type) {
6797                         case RTE_MAC_PERFECT_MATCH:
6798                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6799                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6800                                 break;
6801                         case RTE_MACVLAN_PERFECT_MATCH:
6802                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6803                                 break;
6804                         case RTE_MAC_HASH_MATCH:
6805                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6806                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6807                                 break;
6808                         case RTE_MACVLAN_HASH_MATCH:
6809                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6810                                 break;
6811                         default:
6812                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6813                                 ret = I40E_ERR_PARAM;
6814                                 goto DONE;
6815                         }
6816
6817                         req_list[i].queue_number = 0;
6818
6819                         req_list[i].flags = rte_cpu_to_le_16(flags);
6820                 }
6821
6822                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6823                                                 actual_num, NULL);
6824                 if (ret != I40E_SUCCESS) {
6825                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6826                         goto DONE;
6827                 }
6828                 num += actual_num;
6829         } while (num < total);
6830
6831 DONE:
6832         rte_free(req_list);
6833         return ret;
6834 }
6835
6836 int
6837 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6838                             struct i40e_macvlan_filter *filter,
6839                             int total)
6840 {
6841         int ele_num, ele_buff_size;
6842         int num, actual_num, i;
6843         uint16_t flags;
6844         int ret = I40E_SUCCESS;
6845         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6846         struct i40e_aqc_remove_macvlan_element_data *req_list;
6847
6848         if (filter == NULL  || total == 0)
6849                 return I40E_ERR_PARAM;
6850
6851         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6852         ele_buff_size = hw->aq.asq_buf_size;
6853
6854         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6855         if (req_list == NULL) {
6856                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6857                 return I40E_ERR_NO_MEMORY;
6858         }
6859
6860         num = 0;
6861         do {
6862                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6863                 memset(req_list, 0, ele_buff_size);
6864
6865                 for (i = 0; i < actual_num; i++) {
6866                         rte_memcpy(req_list[i].mac_addr,
6867                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6868                         req_list[i].vlan_tag =
6869                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6870
6871                         switch (filter[num + i].filter_type) {
6872                         case RTE_MAC_PERFECT_MATCH:
6873                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6874                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6875                                 break;
6876                         case RTE_MACVLAN_PERFECT_MATCH:
6877                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6878                                 break;
6879                         case RTE_MAC_HASH_MATCH:
6880                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6881                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6882                                 break;
6883                         case RTE_MACVLAN_HASH_MATCH:
6884                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6885                                 break;
6886                         default:
6887                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6888                                 ret = I40E_ERR_PARAM;
6889                                 goto DONE;
6890                         }
6891                         req_list[i].flags = rte_cpu_to_le_16(flags);
6892                 }
6893
6894                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6895                                                 actual_num, NULL);
6896                 if (ret != I40E_SUCCESS) {
6897                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6898                         goto DONE;
6899                 }
6900                 num += actual_num;
6901         } while (num < total);
6902
6903 DONE:
6904         rte_free(req_list);
6905         return ret;
6906 }
6907
6908 /* Find out specific MAC filter */
6909 static struct i40e_mac_filter *
6910 i40e_find_mac_filter(struct i40e_vsi *vsi,
6911                          struct rte_ether_addr *macaddr)
6912 {
6913         struct i40e_mac_filter *f;
6914
6915         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6916                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6917                         return f;
6918         }
6919
6920         return NULL;
6921 }
6922
6923 static bool
6924 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6925                          uint16_t vlan_id)
6926 {
6927         uint32_t vid_idx, vid_bit;
6928
6929         if (vlan_id > ETH_VLAN_ID_MAX)
6930                 return 0;
6931
6932         vid_idx = I40E_VFTA_IDX(vlan_id);
6933         vid_bit = I40E_VFTA_BIT(vlan_id);
6934
6935         if (vsi->vfta[vid_idx] & vid_bit)
6936                 return 1;
6937         else
6938                 return 0;
6939 }
6940
6941 static void
6942 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6943                        uint16_t vlan_id, bool on)
6944 {
6945         uint32_t vid_idx, vid_bit;
6946
6947         vid_idx = I40E_VFTA_IDX(vlan_id);
6948         vid_bit = I40E_VFTA_BIT(vlan_id);
6949
6950         if (on)
6951                 vsi->vfta[vid_idx] |= vid_bit;
6952         else
6953                 vsi->vfta[vid_idx] &= ~vid_bit;
6954 }
6955
6956 void
6957 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6958                      uint16_t vlan_id, bool on)
6959 {
6960         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6961         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6962         int ret;
6963
6964         if (vlan_id > ETH_VLAN_ID_MAX)
6965                 return;
6966
6967         i40e_store_vlan_filter(vsi, vlan_id, on);
6968
6969         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6970                 return;
6971
6972         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6973
6974         if (on) {
6975                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6976                                        &vlan_data, 1, NULL);
6977                 if (ret != I40E_SUCCESS)
6978                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6979         } else {
6980                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6981                                           &vlan_data, 1, NULL);
6982                 if (ret != I40E_SUCCESS)
6983                         PMD_DRV_LOG(ERR,
6984                                     "Failed to remove vlan filter");
6985         }
6986 }
6987
6988 /**
6989  * Find all vlan options for specific mac addr,
6990  * return with actual vlan found.
6991  */
6992 int
6993 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6994                            struct i40e_macvlan_filter *mv_f,
6995                            int num, struct rte_ether_addr *addr)
6996 {
6997         int i;
6998         uint32_t j, k;
6999
7000         /**
7001          * Not to use i40e_find_vlan_filter to decrease the loop time,
7002          * although the code looks complex.
7003           */
7004         if (num < vsi->vlan_num)
7005                 return I40E_ERR_PARAM;
7006
7007         i = 0;
7008         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7009                 if (vsi->vfta[j]) {
7010                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7011                                 if (vsi->vfta[j] & (1 << k)) {
7012                                         if (i > num - 1) {
7013                                                 PMD_DRV_LOG(ERR,
7014                                                         "vlan number doesn't match");
7015                                                 return I40E_ERR_PARAM;
7016                                         }
7017                                         rte_memcpy(&mv_f[i].macaddr,
7018                                                         addr, ETH_ADDR_LEN);
7019                                         mv_f[i].vlan_id =
7020                                                 j * I40E_UINT32_BIT_SIZE + k;
7021                                         i++;
7022                                 }
7023                         }
7024                 }
7025         }
7026         return I40E_SUCCESS;
7027 }
7028
7029 static inline int
7030 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7031                            struct i40e_macvlan_filter *mv_f,
7032                            int num,
7033                            uint16_t vlan)
7034 {
7035         int i = 0;
7036         struct i40e_mac_filter *f;
7037
7038         if (num < vsi->mac_num)
7039                 return I40E_ERR_PARAM;
7040
7041         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7042                 if (i > num - 1) {
7043                         PMD_DRV_LOG(ERR, "buffer number not match");
7044                         return I40E_ERR_PARAM;
7045                 }
7046                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7047                                 ETH_ADDR_LEN);
7048                 mv_f[i].vlan_id = vlan;
7049                 mv_f[i].filter_type = f->mac_info.filter_type;
7050                 i++;
7051         }
7052
7053         return I40E_SUCCESS;
7054 }
7055
7056 static int
7057 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7058 {
7059         int i, j, num;
7060         struct i40e_mac_filter *f;
7061         struct i40e_macvlan_filter *mv_f;
7062         int ret = I40E_SUCCESS;
7063
7064         if (vsi == NULL || vsi->mac_num == 0)
7065                 return I40E_ERR_PARAM;
7066
7067         /* Case that no vlan is set */
7068         if (vsi->vlan_num == 0)
7069                 num = vsi->mac_num;
7070         else
7071                 num = vsi->mac_num * vsi->vlan_num;
7072
7073         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7074         if (mv_f == NULL) {
7075                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7076                 return I40E_ERR_NO_MEMORY;
7077         }
7078
7079         i = 0;
7080         if (vsi->vlan_num == 0) {
7081                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7082                         rte_memcpy(&mv_f[i].macaddr,
7083                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7084                         mv_f[i].filter_type = f->mac_info.filter_type;
7085                         mv_f[i].vlan_id = 0;
7086                         i++;
7087                 }
7088         } else {
7089                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7090                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7091                                         vsi->vlan_num, &f->mac_info.mac_addr);
7092                         if (ret != I40E_SUCCESS)
7093                                 goto DONE;
7094                         for (j = i; j < i + vsi->vlan_num; j++)
7095                                 mv_f[j].filter_type = f->mac_info.filter_type;
7096                         i += vsi->vlan_num;
7097                 }
7098         }
7099
7100         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7101 DONE:
7102         rte_free(mv_f);
7103
7104         return ret;
7105 }
7106
7107 int
7108 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7109 {
7110         struct i40e_macvlan_filter *mv_f;
7111         int mac_num;
7112         int ret = I40E_SUCCESS;
7113
7114         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7115                 return I40E_ERR_PARAM;
7116
7117         /* If it's already set, just return */
7118         if (i40e_find_vlan_filter(vsi,vlan))
7119                 return I40E_SUCCESS;
7120
7121         mac_num = vsi->mac_num;
7122
7123         if (mac_num == 0) {
7124                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7125                 return I40E_ERR_PARAM;
7126         }
7127
7128         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7129
7130         if (mv_f == NULL) {
7131                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7132                 return I40E_ERR_NO_MEMORY;
7133         }
7134
7135         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7136
7137         if (ret != I40E_SUCCESS)
7138                 goto DONE;
7139
7140         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7141
7142         if (ret != I40E_SUCCESS)
7143                 goto DONE;
7144
7145         i40e_set_vlan_filter(vsi, vlan, 1);
7146
7147         vsi->vlan_num++;
7148         ret = I40E_SUCCESS;
7149 DONE:
7150         rte_free(mv_f);
7151         return ret;
7152 }
7153
7154 int
7155 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7156 {
7157         struct i40e_macvlan_filter *mv_f;
7158         int mac_num;
7159         int ret = I40E_SUCCESS;
7160
7161         /**
7162          * Vlan 0 is the generic filter for untagged packets
7163          * and can't be removed.
7164          */
7165         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7166                 return I40E_ERR_PARAM;
7167
7168         /* If can't find it, just return */
7169         if (!i40e_find_vlan_filter(vsi, vlan))
7170                 return I40E_ERR_PARAM;
7171
7172         mac_num = vsi->mac_num;
7173
7174         if (mac_num == 0) {
7175                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7176                 return I40E_ERR_PARAM;
7177         }
7178
7179         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7180
7181         if (mv_f == NULL) {
7182                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7183                 return I40E_ERR_NO_MEMORY;
7184         }
7185
7186         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7187
7188         if (ret != I40E_SUCCESS)
7189                 goto DONE;
7190
7191         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7192
7193         if (ret != I40E_SUCCESS)
7194                 goto DONE;
7195
7196         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7197         if (vsi->vlan_num == 1) {
7198                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7199                 if (ret != I40E_SUCCESS)
7200                         goto DONE;
7201
7202                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7203                 if (ret != I40E_SUCCESS)
7204                         goto DONE;
7205         }
7206
7207         i40e_set_vlan_filter(vsi, vlan, 0);
7208
7209         vsi->vlan_num--;
7210         ret = I40E_SUCCESS;
7211 DONE:
7212         rte_free(mv_f);
7213         return ret;
7214 }
7215
7216 int
7217 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7218 {
7219         struct i40e_mac_filter *f;
7220         struct i40e_macvlan_filter *mv_f;
7221         int i, vlan_num = 0;
7222         int ret = I40E_SUCCESS;
7223
7224         /* If it's add and we've config it, return */
7225         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7226         if (f != NULL)
7227                 return I40E_SUCCESS;
7228         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7229                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7230
7231                 /**
7232                  * If vlan_num is 0, that's the first time to add mac,
7233                  * set mask for vlan_id 0.
7234                  */
7235                 if (vsi->vlan_num == 0) {
7236                         i40e_set_vlan_filter(vsi, 0, 1);
7237                         vsi->vlan_num = 1;
7238                 }
7239                 vlan_num = vsi->vlan_num;
7240         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7241                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7242                 vlan_num = 1;
7243
7244         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7245         if (mv_f == NULL) {
7246                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7247                 return I40E_ERR_NO_MEMORY;
7248         }
7249
7250         for (i = 0; i < vlan_num; i++) {
7251                 mv_f[i].filter_type = mac_filter->filter_type;
7252                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7253                                 ETH_ADDR_LEN);
7254         }
7255
7256         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7257                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7258                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7259                                         &mac_filter->mac_addr);
7260                 if (ret != I40E_SUCCESS)
7261                         goto DONE;
7262         }
7263
7264         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7265         if (ret != I40E_SUCCESS)
7266                 goto DONE;
7267
7268         /* Add the mac addr into mac list */
7269         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7270         if (f == NULL) {
7271                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7272                 ret = I40E_ERR_NO_MEMORY;
7273                 goto DONE;
7274         }
7275         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7276                         ETH_ADDR_LEN);
7277         f->mac_info.filter_type = mac_filter->filter_type;
7278         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7279         vsi->mac_num++;
7280
7281         ret = I40E_SUCCESS;
7282 DONE:
7283         rte_free(mv_f);
7284
7285         return ret;
7286 }
7287
7288 int
7289 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7290 {
7291         struct i40e_mac_filter *f;
7292         struct i40e_macvlan_filter *mv_f;
7293         int i, vlan_num;
7294         enum rte_mac_filter_type filter_type;
7295         int ret = I40E_SUCCESS;
7296
7297         /* Can't find it, return an error */
7298         f = i40e_find_mac_filter(vsi, addr);
7299         if (f == NULL)
7300                 return I40E_ERR_PARAM;
7301
7302         vlan_num = vsi->vlan_num;
7303         filter_type = f->mac_info.filter_type;
7304         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7305                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7306                 if (vlan_num == 0) {
7307                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7308                         return I40E_ERR_PARAM;
7309                 }
7310         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7311                         filter_type == RTE_MAC_HASH_MATCH)
7312                 vlan_num = 1;
7313
7314         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7315         if (mv_f == NULL) {
7316                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7317                 return I40E_ERR_NO_MEMORY;
7318         }
7319
7320         for (i = 0; i < vlan_num; i++) {
7321                 mv_f[i].filter_type = filter_type;
7322                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7323                                 ETH_ADDR_LEN);
7324         }
7325         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7326                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7327                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7328                 if (ret != I40E_SUCCESS)
7329                         goto DONE;
7330         }
7331
7332         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7333         if (ret != I40E_SUCCESS)
7334                 goto DONE;
7335
7336         /* Remove the mac addr into mac list */
7337         TAILQ_REMOVE(&vsi->mac_list, f, next);
7338         rte_free(f);
7339         vsi->mac_num--;
7340
7341         ret = I40E_SUCCESS;
7342 DONE:
7343         rte_free(mv_f);
7344         return ret;
7345 }
7346
7347 /* Configure hash enable flags for RSS */
7348 uint64_t
7349 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7350 {
7351         uint64_t hena = 0;
7352         int i;
7353
7354         if (!flags)
7355                 return hena;
7356
7357         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7358                 if (flags & (1ULL << i))
7359                         hena |= adapter->pctypes_tbl[i];
7360         }
7361
7362         return hena;
7363 }
7364
7365 /* Parse the hash enable flags */
7366 uint64_t
7367 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7368 {
7369         uint64_t rss_hf = 0;
7370
7371         if (!flags)
7372                 return rss_hf;
7373         int i;
7374
7375         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7376                 if (flags & adapter->pctypes_tbl[i])
7377                         rss_hf |= (1ULL << i);
7378         }
7379         return rss_hf;
7380 }
7381
7382 /* Disable RSS */
7383 static void
7384 i40e_pf_disable_rss(struct i40e_pf *pf)
7385 {
7386         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7387
7388         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7389         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7390         I40E_WRITE_FLUSH(hw);
7391 }
7392
7393 int
7394 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7395 {
7396         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7397         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7398         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7399                            I40E_VFQF_HKEY_MAX_INDEX :
7400                            I40E_PFQF_HKEY_MAX_INDEX;
7401         int ret = 0;
7402
7403         if (!key || key_len == 0) {
7404                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7405                 return 0;
7406         } else if (key_len != (key_idx + 1) *
7407                 sizeof(uint32_t)) {
7408                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7409                 return -EINVAL;
7410         }
7411
7412         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7413                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7414                         (struct i40e_aqc_get_set_rss_key_data *)key;
7415
7416                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7417                 if (ret)
7418                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7419         } else {
7420                 uint32_t *hash_key = (uint32_t *)key;
7421                 uint16_t i;
7422
7423                 if (vsi->type == I40E_VSI_SRIOV) {
7424                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7425                                 I40E_WRITE_REG(
7426                                         hw,
7427                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7428                                         hash_key[i]);
7429
7430                 } else {
7431                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7432                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7433                                                hash_key[i]);
7434                 }
7435                 I40E_WRITE_FLUSH(hw);
7436         }
7437
7438         return ret;
7439 }
7440
7441 static int
7442 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7443 {
7444         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7445         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7446         uint32_t reg;
7447         int ret;
7448
7449         if (!key || !key_len)
7450                 return 0;
7451
7452         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7453                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7454                         (struct i40e_aqc_get_set_rss_key_data *)key);
7455                 if (ret) {
7456                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7457                         return ret;
7458                 }
7459         } else {
7460                 uint32_t *key_dw = (uint32_t *)key;
7461                 uint16_t i;
7462
7463                 if (vsi->type == I40E_VSI_SRIOV) {
7464                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7465                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7466                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7467                         }
7468                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7469                                    sizeof(uint32_t);
7470                 } else {
7471                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7472                                 reg = I40E_PFQF_HKEY(i);
7473                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7474                         }
7475                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7476                                    sizeof(uint32_t);
7477                 }
7478         }
7479         return 0;
7480 }
7481
7482 static int
7483 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7484 {
7485         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7486         uint64_t hena;
7487         int ret;
7488
7489         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7490                                rss_conf->rss_key_len);
7491         if (ret)
7492                 return ret;
7493
7494         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7495         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7496         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7497         I40E_WRITE_FLUSH(hw);
7498
7499         return 0;
7500 }
7501
7502 static int
7503 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7504                          struct rte_eth_rss_conf *rss_conf)
7505 {
7506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7507         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7508         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7509         uint64_t hena;
7510
7511         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7512         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7513
7514         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7515                 if (rss_hf != 0) /* Enable RSS */
7516                         return -EINVAL;
7517                 return 0; /* Nothing to do */
7518         }
7519         /* RSS enabled */
7520         if (rss_hf == 0) /* Disable RSS */
7521                 return -EINVAL;
7522
7523         return i40e_hw_rss_hash_set(pf, rss_conf);
7524 }
7525
7526 static int
7527 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7528                            struct rte_eth_rss_conf *rss_conf)
7529 {
7530         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7531         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7532         uint64_t hena;
7533         int ret;
7534
7535         if (!rss_conf)
7536                 return -EINVAL;
7537
7538         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7539                          &rss_conf->rss_key_len);
7540         if (ret)
7541                 return ret;
7542
7543         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7544         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7545         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7546
7547         return 0;
7548 }
7549
7550 static int
7551 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7552 {
7553         switch (filter_type) {
7554         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7555                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7556                 break;
7557         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7558                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7559                 break;
7560         case RTE_TUNNEL_FILTER_IMAC_TENID:
7561                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7562                 break;
7563         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7564                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7565                 break;
7566         case ETH_TUNNEL_FILTER_IMAC:
7567                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7568                 break;
7569         case ETH_TUNNEL_FILTER_OIP:
7570                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7571                 break;
7572         case ETH_TUNNEL_FILTER_IIP:
7573                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7574                 break;
7575         default:
7576                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7577                 return -EINVAL;
7578         }
7579
7580         return 0;
7581 }
7582
7583 /* Convert tunnel filter structure */
7584 static int
7585 i40e_tunnel_filter_convert(
7586         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7587         struct i40e_tunnel_filter *tunnel_filter)
7588 {
7589         ether_addr_copy((struct rte_ether_addr *)&cld_filter->element.outer_mac,
7590                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7591         ether_addr_copy((struct rte_ether_addr *)&cld_filter->element.inner_mac,
7592                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7593         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7594         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7595              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7596             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7597                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7598         else
7599                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7600         tunnel_filter->input.flags = cld_filter->element.flags;
7601         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7602         tunnel_filter->queue = cld_filter->element.queue_number;
7603         rte_memcpy(tunnel_filter->input.general_fields,
7604                    cld_filter->general_fields,
7605                    sizeof(cld_filter->general_fields));
7606
7607         return 0;
7608 }
7609
7610 /* Check if there exists the tunnel filter */
7611 struct i40e_tunnel_filter *
7612 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7613                              const struct i40e_tunnel_filter_input *input)
7614 {
7615         int ret;
7616
7617         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7618         if (ret < 0)
7619                 return NULL;
7620
7621         return tunnel_rule->hash_map[ret];
7622 }
7623
7624 /* Add a tunnel filter into the SW list */
7625 static int
7626 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7627                              struct i40e_tunnel_filter *tunnel_filter)
7628 {
7629         struct i40e_tunnel_rule *rule = &pf->tunnel;
7630         int ret;
7631
7632         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7633         if (ret < 0) {
7634                 PMD_DRV_LOG(ERR,
7635                             "Failed to insert tunnel filter to hash table %d!",
7636                             ret);
7637                 return ret;
7638         }
7639         rule->hash_map[ret] = tunnel_filter;
7640
7641         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7642
7643         return 0;
7644 }
7645
7646 /* Delete a tunnel filter from the SW list */
7647 int
7648 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7649                           struct i40e_tunnel_filter_input *input)
7650 {
7651         struct i40e_tunnel_rule *rule = &pf->tunnel;
7652         struct i40e_tunnel_filter *tunnel_filter;
7653         int ret;
7654
7655         ret = rte_hash_del_key(rule->hash_table, input);
7656         if (ret < 0) {
7657                 PMD_DRV_LOG(ERR,
7658                             "Failed to delete tunnel filter to hash table %d!",
7659                             ret);
7660                 return ret;
7661         }
7662         tunnel_filter = rule->hash_map[ret];
7663         rule->hash_map[ret] = NULL;
7664
7665         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7666         rte_free(tunnel_filter);
7667
7668         return 0;
7669 }
7670
7671 int
7672 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7673                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7674                         uint8_t add)
7675 {
7676         uint16_t ip_type;
7677         uint32_t ipv4_addr, ipv4_addr_le;
7678         uint8_t i, tun_type = 0;
7679         /* internal varialbe to convert ipv6 byte order */
7680         uint32_t convert_ipv6[4];
7681         int val, ret = 0;
7682         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7683         struct i40e_vsi *vsi = pf->main_vsi;
7684         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7685         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7686         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7687         struct i40e_tunnel_filter *tunnel, *node;
7688         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7689
7690         cld_filter = rte_zmalloc("tunnel_filter",
7691                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7692         0);
7693
7694         if (NULL == cld_filter) {
7695                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7696                 return -ENOMEM;
7697         }
7698         pfilter = cld_filter;
7699
7700         ether_addr_copy(&tunnel_filter->outer_mac,
7701                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7702         ether_addr_copy(&tunnel_filter->inner_mac,
7703                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7704
7705         pfilter->element.inner_vlan =
7706                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7707         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7708                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7709                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7710                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7711                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7712                                 &ipv4_addr_le,
7713                                 sizeof(pfilter->element.ipaddr.v4.data));
7714         } else {
7715                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7716                 for (i = 0; i < 4; i++) {
7717                         convert_ipv6[i] =
7718                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7719                 }
7720                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7721                            &convert_ipv6,
7722                            sizeof(pfilter->element.ipaddr.v6.data));
7723         }
7724
7725         /* check tunneled type */
7726         switch (tunnel_filter->tunnel_type) {
7727         case RTE_TUNNEL_TYPE_VXLAN:
7728                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7729                 break;
7730         case RTE_TUNNEL_TYPE_NVGRE:
7731                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7732                 break;
7733         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7734                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7735                 break;
7736         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7737                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7738                 break;
7739         default:
7740                 /* Other tunnel types is not supported. */
7741                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7742                 rte_free(cld_filter);
7743                 return -EINVAL;
7744         }
7745
7746         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7747                                        &pfilter->element.flags);
7748         if (val < 0) {
7749                 rte_free(cld_filter);
7750                 return -EINVAL;
7751         }
7752
7753         pfilter->element.flags |= rte_cpu_to_le_16(
7754                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7755                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7756         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7757         pfilter->element.queue_number =
7758                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7759
7760         /* Check if there is the filter in SW list */
7761         memset(&check_filter, 0, sizeof(check_filter));
7762         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7763         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7764         if (add && node) {
7765                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7766                 rte_free(cld_filter);
7767                 return -EINVAL;
7768         }
7769
7770         if (!add && !node) {
7771                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7772                 rte_free(cld_filter);
7773                 return -EINVAL;
7774         }
7775
7776         if (add) {
7777                 ret = i40e_aq_add_cloud_filters(hw,
7778                                         vsi->seid, &cld_filter->element, 1);
7779                 if (ret < 0) {
7780                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7781                         rte_free(cld_filter);
7782                         return -ENOTSUP;
7783                 }
7784                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7785                 if (tunnel == NULL) {
7786                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7787                         rte_free(cld_filter);
7788                         return -ENOMEM;
7789                 }
7790
7791                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7792                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7793                 if (ret < 0)
7794                         rte_free(tunnel);
7795         } else {
7796                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7797                                                    &cld_filter->element, 1);
7798                 if (ret < 0) {
7799                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7800                         rte_free(cld_filter);
7801                         return -ENOTSUP;
7802                 }
7803                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7804         }
7805
7806         rte_free(cld_filter);
7807         return ret;
7808 }
7809
7810 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7811 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7812 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7813 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7814 #define I40E_TR_GRE_KEY_MASK                    0x400
7815 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7816 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7817
7818 static enum
7819 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7820 {
7821         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7822         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7823         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7824         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7825         enum i40e_status_code status = I40E_SUCCESS;
7826
7827         if (pf->support_multi_driver) {
7828                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7829                 return I40E_NOT_SUPPORTED;
7830         }
7831
7832         memset(&filter_replace, 0,
7833                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7834         memset(&filter_replace_buf, 0,
7835                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7836
7837         /* create L1 filter */
7838         filter_replace.old_filter_type =
7839                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7840         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7841         filter_replace.tr_bit = 0;
7842
7843         /* Prepare the buffer, 3 entries */
7844         filter_replace_buf.data[0] =
7845                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7846         filter_replace_buf.data[0] |=
7847                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7848         filter_replace_buf.data[2] = 0xFF;
7849         filter_replace_buf.data[3] = 0xFF;
7850         filter_replace_buf.data[4] =
7851                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7852         filter_replace_buf.data[4] |=
7853                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7854         filter_replace_buf.data[7] = 0xF0;
7855         filter_replace_buf.data[8]
7856                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7857         filter_replace_buf.data[8] |=
7858                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7859         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7860                 I40E_TR_GENEVE_KEY_MASK |
7861                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7862         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7863                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7864                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7865
7866         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7867                                                &filter_replace_buf);
7868         if (!status && (filter_replace.old_filter_type !=
7869                         filter_replace.new_filter_type))
7870                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7871                             " original: 0x%x, new: 0x%x",
7872                             dev->device->name,
7873                             filter_replace.old_filter_type,
7874                             filter_replace.new_filter_type);
7875
7876         return status;
7877 }
7878
7879 static enum
7880 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7881 {
7882         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7883         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7884         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7885         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7886         enum i40e_status_code status = I40E_SUCCESS;
7887
7888         if (pf->support_multi_driver) {
7889                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7890                 return I40E_NOT_SUPPORTED;
7891         }
7892
7893         /* For MPLSoUDP */
7894         memset(&filter_replace, 0,
7895                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7896         memset(&filter_replace_buf, 0,
7897                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7898         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7899                 I40E_AQC_MIRROR_CLOUD_FILTER;
7900         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7901         filter_replace.new_filter_type =
7902                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7903         /* Prepare the buffer, 2 entries */
7904         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7905         filter_replace_buf.data[0] |=
7906                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7907         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7908         filter_replace_buf.data[4] |=
7909                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7910         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7911                                                &filter_replace_buf);
7912         if (status < 0)
7913                 return status;
7914         if (filter_replace.old_filter_type !=
7915             filter_replace.new_filter_type)
7916                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7917                             " original: 0x%x, new: 0x%x",
7918                             dev->device->name,
7919                             filter_replace.old_filter_type,
7920                             filter_replace.new_filter_type);
7921
7922         /* For MPLSoGRE */
7923         memset(&filter_replace, 0,
7924                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7925         memset(&filter_replace_buf, 0,
7926                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7927
7928         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7929                 I40E_AQC_MIRROR_CLOUD_FILTER;
7930         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7931         filter_replace.new_filter_type =
7932                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7933         /* Prepare the buffer, 2 entries */
7934         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7935         filter_replace_buf.data[0] |=
7936                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7937         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7938         filter_replace_buf.data[4] |=
7939                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7940
7941         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7942                                                &filter_replace_buf);
7943         if (!status && (filter_replace.old_filter_type !=
7944                         filter_replace.new_filter_type))
7945                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7946                             " original: 0x%x, new: 0x%x",
7947                             dev->device->name,
7948                             filter_replace.old_filter_type,
7949                             filter_replace.new_filter_type);
7950
7951         return status;
7952 }
7953
7954 static enum i40e_status_code
7955 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7956 {
7957         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7958         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7959         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7960         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7961         enum i40e_status_code status = I40E_SUCCESS;
7962
7963         if (pf->support_multi_driver) {
7964                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7965                 return I40E_NOT_SUPPORTED;
7966         }
7967
7968         /* For GTP-C */
7969         memset(&filter_replace, 0,
7970                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7971         memset(&filter_replace_buf, 0,
7972                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7973         /* create L1 filter */
7974         filter_replace.old_filter_type =
7975                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7976         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7977         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7978                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7979         /* Prepare the buffer, 2 entries */
7980         filter_replace_buf.data[0] =
7981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7982         filter_replace_buf.data[0] |=
7983                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7984         filter_replace_buf.data[2] = 0xFF;
7985         filter_replace_buf.data[3] = 0xFF;
7986         filter_replace_buf.data[4] =
7987                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7988         filter_replace_buf.data[4] |=
7989                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7990         filter_replace_buf.data[6] = 0xFF;
7991         filter_replace_buf.data[7] = 0xFF;
7992         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7993                                                &filter_replace_buf);
7994         if (status < 0)
7995                 return status;
7996         if (filter_replace.old_filter_type !=
7997             filter_replace.new_filter_type)
7998                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7999                             " original: 0x%x, new: 0x%x",
8000                             dev->device->name,
8001                             filter_replace.old_filter_type,
8002                             filter_replace.new_filter_type);
8003
8004         /* for GTP-U */
8005         memset(&filter_replace, 0,
8006                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8007         memset(&filter_replace_buf, 0,
8008                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8009         /* create L1 filter */
8010         filter_replace.old_filter_type =
8011                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8012         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8013         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8014                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8015         /* Prepare the buffer, 2 entries */
8016         filter_replace_buf.data[0] =
8017                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8018         filter_replace_buf.data[0] |=
8019                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8020         filter_replace_buf.data[2] = 0xFF;
8021         filter_replace_buf.data[3] = 0xFF;
8022         filter_replace_buf.data[4] =
8023                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8024         filter_replace_buf.data[4] |=
8025                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8026         filter_replace_buf.data[6] = 0xFF;
8027         filter_replace_buf.data[7] = 0xFF;
8028
8029         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8030                                                &filter_replace_buf);
8031         if (!status && (filter_replace.old_filter_type !=
8032                         filter_replace.new_filter_type))
8033                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8034                             " original: 0x%x, new: 0x%x",
8035                             dev->device->name,
8036                             filter_replace.old_filter_type,
8037                             filter_replace.new_filter_type);
8038
8039         return status;
8040 }
8041
8042 static enum
8043 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8044 {
8045         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8046         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8048         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8049         enum i40e_status_code status = I40E_SUCCESS;
8050
8051         if (pf->support_multi_driver) {
8052                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8053                 return I40E_NOT_SUPPORTED;
8054         }
8055
8056         /* for GTP-C */
8057         memset(&filter_replace, 0,
8058                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8059         memset(&filter_replace_buf, 0,
8060                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8061         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8062         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8063         filter_replace.new_filter_type =
8064                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8065         /* Prepare the buffer, 2 entries */
8066         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8067         filter_replace_buf.data[0] |=
8068                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8069         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8070         filter_replace_buf.data[4] |=
8071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8073                                                &filter_replace_buf);
8074         if (status < 0)
8075                 return status;
8076         if (filter_replace.old_filter_type !=
8077             filter_replace.new_filter_type)
8078                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8079                             " original: 0x%x, new: 0x%x",
8080                             dev->device->name,
8081                             filter_replace.old_filter_type,
8082                             filter_replace.new_filter_type);
8083
8084         /* for GTP-U */
8085         memset(&filter_replace, 0,
8086                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8087         memset(&filter_replace_buf, 0,
8088                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8089         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8090         filter_replace.old_filter_type =
8091                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8092         filter_replace.new_filter_type =
8093                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8094         /* Prepare the buffer, 2 entries */
8095         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8096         filter_replace_buf.data[0] |=
8097                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8098         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8099         filter_replace_buf.data[4] |=
8100                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8101
8102         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8103                                                &filter_replace_buf);
8104         if (!status && (filter_replace.old_filter_type !=
8105                         filter_replace.new_filter_type))
8106                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8107                             " original: 0x%x, new: 0x%x",
8108                             dev->device->name,
8109                             filter_replace.old_filter_type,
8110                             filter_replace.new_filter_type);
8111
8112         return status;
8113 }
8114
8115 int
8116 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8117                       struct i40e_tunnel_filter_conf *tunnel_filter,
8118                       uint8_t add)
8119 {
8120         uint16_t ip_type;
8121         uint32_t ipv4_addr, ipv4_addr_le;
8122         uint8_t i, tun_type = 0;
8123         /* internal variable to convert ipv6 byte order */
8124         uint32_t convert_ipv6[4];
8125         int val, ret = 0;
8126         struct i40e_pf_vf *vf = NULL;
8127         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8128         struct i40e_vsi *vsi;
8129         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8130         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8131         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8132         struct i40e_tunnel_filter *tunnel, *node;
8133         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8134         uint32_t teid_le;
8135         bool big_buffer = 0;
8136
8137         cld_filter = rte_zmalloc("tunnel_filter",
8138                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8139                          0);
8140
8141         if (cld_filter == NULL) {
8142                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8143                 return -ENOMEM;
8144         }
8145         pfilter = cld_filter;
8146
8147         ether_addr_copy(&tunnel_filter->outer_mac,
8148                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8149         ether_addr_copy(&tunnel_filter->inner_mac,
8150                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8151
8152         pfilter->element.inner_vlan =
8153                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8154         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8155                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8156                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8157                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8158                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8159                                 &ipv4_addr_le,
8160                                 sizeof(pfilter->element.ipaddr.v4.data));
8161         } else {
8162                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8163                 for (i = 0; i < 4; i++) {
8164                         convert_ipv6[i] =
8165                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8166                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8167                 }
8168                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8169                            &convert_ipv6,
8170                            sizeof(pfilter->element.ipaddr.v6.data));
8171         }
8172
8173         /* check tunneled type */
8174         switch (tunnel_filter->tunnel_type) {
8175         case I40E_TUNNEL_TYPE_VXLAN:
8176                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8177                 break;
8178         case I40E_TUNNEL_TYPE_NVGRE:
8179                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8180                 break;
8181         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8182                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8183                 break;
8184         case I40E_TUNNEL_TYPE_MPLSoUDP:
8185                 if (!pf->mpls_replace_flag) {
8186                         i40e_replace_mpls_l1_filter(pf);
8187                         i40e_replace_mpls_cloud_filter(pf);
8188                         pf->mpls_replace_flag = 1;
8189                 }
8190                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8191                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8192                         teid_le >> 4;
8193                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8194                         (teid_le & 0xF) << 12;
8195                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8196                         0x40;
8197                 big_buffer = 1;
8198                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8199                 break;
8200         case I40E_TUNNEL_TYPE_MPLSoGRE:
8201                 if (!pf->mpls_replace_flag) {
8202                         i40e_replace_mpls_l1_filter(pf);
8203                         i40e_replace_mpls_cloud_filter(pf);
8204                         pf->mpls_replace_flag = 1;
8205                 }
8206                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8207                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8208                         teid_le >> 4;
8209                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8210                         (teid_le & 0xF) << 12;
8211                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8212                         0x0;
8213                 big_buffer = 1;
8214                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8215                 break;
8216         case I40E_TUNNEL_TYPE_GTPC:
8217                 if (!pf->gtp_replace_flag) {
8218                         i40e_replace_gtp_l1_filter(pf);
8219                         i40e_replace_gtp_cloud_filter(pf);
8220                         pf->gtp_replace_flag = 1;
8221                 }
8222                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8223                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8224                         (teid_le >> 16) & 0xFFFF;
8225                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8226                         teid_le & 0xFFFF;
8227                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8228                         0x0;
8229                 big_buffer = 1;
8230                 break;
8231         case I40E_TUNNEL_TYPE_GTPU:
8232                 if (!pf->gtp_replace_flag) {
8233                         i40e_replace_gtp_l1_filter(pf);
8234                         i40e_replace_gtp_cloud_filter(pf);
8235                         pf->gtp_replace_flag = 1;
8236                 }
8237                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8238                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8239                         (teid_le >> 16) & 0xFFFF;
8240                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8241                         teid_le & 0xFFFF;
8242                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8243                         0x0;
8244                 big_buffer = 1;
8245                 break;
8246         case I40E_TUNNEL_TYPE_QINQ:
8247                 if (!pf->qinq_replace_flag) {
8248                         ret = i40e_cloud_filter_qinq_create(pf);
8249                         if (ret < 0)
8250                                 PMD_DRV_LOG(DEBUG,
8251                                             "QinQ tunnel filter already created.");
8252                         pf->qinq_replace_flag = 1;
8253                 }
8254                 /*      Add in the General fields the values of
8255                  *      the Outer and Inner VLAN
8256                  *      Big Buffer should be set, see changes in
8257                  *      i40e_aq_add_cloud_filters
8258                  */
8259                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8260                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8261                 big_buffer = 1;
8262                 break;
8263         default:
8264                 /* Other tunnel types is not supported. */
8265                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8266                 rte_free(cld_filter);
8267                 return -EINVAL;
8268         }
8269
8270         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8271                 pfilter->element.flags =
8272                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8273         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8274                 pfilter->element.flags =
8275                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8276         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8277                 pfilter->element.flags =
8278                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8279         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8280                 pfilter->element.flags =
8281                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8282         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8283                 pfilter->element.flags |=
8284                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8285         else {
8286                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8287                                                 &pfilter->element.flags);
8288                 if (val < 0) {
8289                         rte_free(cld_filter);
8290                         return -EINVAL;
8291                 }
8292         }
8293
8294         pfilter->element.flags |= rte_cpu_to_le_16(
8295                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8296                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8297         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8298         pfilter->element.queue_number =
8299                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8300
8301         if (!tunnel_filter->is_to_vf)
8302                 vsi = pf->main_vsi;
8303         else {
8304                 if (tunnel_filter->vf_id >= pf->vf_num) {
8305                         PMD_DRV_LOG(ERR, "Invalid argument.");
8306                         rte_free(cld_filter);
8307                         return -EINVAL;
8308                 }
8309                 vf = &pf->vfs[tunnel_filter->vf_id];
8310                 vsi = vf->vsi;
8311         }
8312
8313         /* Check if there is the filter in SW list */
8314         memset(&check_filter, 0, sizeof(check_filter));
8315         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8316         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8317         check_filter.vf_id = tunnel_filter->vf_id;
8318         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8319         if (add && node) {
8320                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8321                 rte_free(cld_filter);
8322                 return -EINVAL;
8323         }
8324
8325         if (!add && !node) {
8326                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8327                 rte_free(cld_filter);
8328                 return -EINVAL;
8329         }
8330
8331         if (add) {
8332                 if (big_buffer)
8333                         ret = i40e_aq_add_cloud_filters_bb(hw,
8334                                                    vsi->seid, cld_filter, 1);
8335                 else
8336                         ret = i40e_aq_add_cloud_filters(hw,
8337                                         vsi->seid, &cld_filter->element, 1);
8338                 if (ret < 0) {
8339                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8340                         rte_free(cld_filter);
8341                         return -ENOTSUP;
8342                 }
8343                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8344                 if (tunnel == NULL) {
8345                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8346                         rte_free(cld_filter);
8347                         return -ENOMEM;
8348                 }
8349
8350                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8351                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8352                 if (ret < 0)
8353                         rte_free(tunnel);
8354         } else {
8355                 if (big_buffer)
8356                         ret = i40e_aq_rem_cloud_filters_bb(
8357                                 hw, vsi->seid, cld_filter, 1);
8358                 else
8359                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8360                                                 &cld_filter->element, 1);
8361                 if (ret < 0) {
8362                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8363                         rte_free(cld_filter);
8364                         return -ENOTSUP;
8365                 }
8366                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8367         }
8368
8369         rte_free(cld_filter);
8370         return ret;
8371 }
8372
8373 static int
8374 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8375 {
8376         uint8_t i;
8377
8378         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8379                 if (pf->vxlan_ports[i] == port)
8380                         return i;
8381         }
8382
8383         return -1;
8384 }
8385
8386 static int
8387 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8388 {
8389         int  idx, ret;
8390         uint8_t filter_idx;
8391         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8392
8393         idx = i40e_get_vxlan_port_idx(pf, port);
8394
8395         /* Check if port already exists */
8396         if (idx >= 0) {
8397                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8398                 return -EINVAL;
8399         }
8400
8401         /* Now check if there is space to add the new port */
8402         idx = i40e_get_vxlan_port_idx(pf, 0);
8403         if (idx < 0) {
8404                 PMD_DRV_LOG(ERR,
8405                         "Maximum number of UDP ports reached, not adding port %d",
8406                         port);
8407                 return -ENOSPC;
8408         }
8409
8410         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8411                                         &filter_idx, NULL);
8412         if (ret < 0) {
8413                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8414                 return -1;
8415         }
8416
8417         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8418                          port,  filter_idx);
8419
8420         /* New port: add it and mark its index in the bitmap */
8421         pf->vxlan_ports[idx] = port;
8422         pf->vxlan_bitmap |= (1 << idx);
8423
8424         if (!(pf->flags & I40E_FLAG_VXLAN))
8425                 pf->flags |= I40E_FLAG_VXLAN;
8426
8427         return 0;
8428 }
8429
8430 static int
8431 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8432 {
8433         int idx;
8434         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8435
8436         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8437                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8438                 return -EINVAL;
8439         }
8440
8441         idx = i40e_get_vxlan_port_idx(pf, port);
8442
8443         if (idx < 0) {
8444                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8445                 return -EINVAL;
8446         }
8447
8448         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8449                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8450                 return -1;
8451         }
8452
8453         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8454                         port, idx);
8455
8456         pf->vxlan_ports[idx] = 0;
8457         pf->vxlan_bitmap &= ~(1 << idx);
8458
8459         if (!pf->vxlan_bitmap)
8460                 pf->flags &= ~I40E_FLAG_VXLAN;
8461
8462         return 0;
8463 }
8464
8465 /* Add UDP tunneling port */
8466 static int
8467 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8468                              struct rte_eth_udp_tunnel *udp_tunnel)
8469 {
8470         int ret = 0;
8471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8472
8473         if (udp_tunnel == NULL)
8474                 return -EINVAL;
8475
8476         switch (udp_tunnel->prot_type) {
8477         case RTE_TUNNEL_TYPE_VXLAN:
8478                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8479                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8480                 break;
8481         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8482                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8483                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8484                 break;
8485         case RTE_TUNNEL_TYPE_GENEVE:
8486         case RTE_TUNNEL_TYPE_TEREDO:
8487                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8488                 ret = -1;
8489                 break;
8490
8491         default:
8492                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8493                 ret = -1;
8494                 break;
8495         }
8496
8497         return ret;
8498 }
8499
8500 /* Remove UDP tunneling port */
8501 static int
8502 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8503                              struct rte_eth_udp_tunnel *udp_tunnel)
8504 {
8505         int ret = 0;
8506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8507
8508         if (udp_tunnel == NULL)
8509                 return -EINVAL;
8510
8511         switch (udp_tunnel->prot_type) {
8512         case RTE_TUNNEL_TYPE_VXLAN:
8513         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8514                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8515                 break;
8516         case RTE_TUNNEL_TYPE_GENEVE:
8517         case RTE_TUNNEL_TYPE_TEREDO:
8518                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8519                 ret = -1;
8520                 break;
8521         default:
8522                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8523                 ret = -1;
8524                 break;
8525         }
8526
8527         return ret;
8528 }
8529
8530 /* Calculate the maximum number of contiguous PF queues that are configured */
8531 static int
8532 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8533 {
8534         struct rte_eth_dev_data *data = pf->dev_data;
8535         int i, num;
8536         struct i40e_rx_queue *rxq;
8537
8538         num = 0;
8539         for (i = 0; i < pf->lan_nb_qps; i++) {
8540                 rxq = data->rx_queues[i];
8541                 if (rxq && rxq->q_set)
8542                         num++;
8543                 else
8544                         break;
8545         }
8546
8547         return num;
8548 }
8549
8550 /* Configure RSS */
8551 static int
8552 i40e_pf_config_rss(struct i40e_pf *pf)
8553 {
8554         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8555         struct rte_eth_rss_conf rss_conf;
8556         uint32_t i, lut = 0;
8557         uint16_t j, num;
8558
8559         /*
8560          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8561          * It's necessary to calculate the actual PF queues that are configured.
8562          */
8563         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8564                 num = i40e_pf_calc_configured_queues_num(pf);
8565         else
8566                 num = pf->dev_data->nb_rx_queues;
8567
8568         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8569         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8570                         num);
8571
8572         if (num == 0) {
8573                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8574                 return -ENOTSUP;
8575         }
8576
8577         if (pf->adapter->rss_reta_updated == 0) {
8578                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8579                         if (j == num)
8580                                 j = 0;
8581                         lut = (lut << 8) | (j & ((0x1 <<
8582                                 hw->func_caps.rss_table_entry_width) - 1));
8583                         if ((i & 3) == 3)
8584                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8585                                                rte_bswap32(lut));
8586                 }
8587         }
8588
8589         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8590         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8591                 i40e_pf_disable_rss(pf);
8592                 return 0;
8593         }
8594         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8595                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8596                 /* Random default keys */
8597                 static uint32_t rss_key_default[] = {0x6b793944,
8598                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8599                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8600                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8601
8602                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8603                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8604                                                         sizeof(uint32_t);
8605         }
8606
8607         return i40e_hw_rss_hash_set(pf, &rss_conf);
8608 }
8609
8610 static int
8611 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8612                                struct rte_eth_tunnel_filter_conf *filter)
8613 {
8614         if (pf == NULL || filter == NULL) {
8615                 PMD_DRV_LOG(ERR, "Invalid parameter");
8616                 return -EINVAL;
8617         }
8618
8619         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8620                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8621                 return -EINVAL;
8622         }
8623
8624         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8625                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8626                 return -EINVAL;
8627         }
8628
8629         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8630                 (is_zero_ether_addr(&filter->outer_mac))) {
8631                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8632                 return -EINVAL;
8633         }
8634
8635         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8636                 (is_zero_ether_addr(&filter->inner_mac))) {
8637                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8638                 return -EINVAL;
8639         }
8640
8641         return 0;
8642 }
8643
8644 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8645 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8646 static int
8647 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8648 {
8649         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8650         uint32_t val, reg;
8651         int ret = -EINVAL;
8652
8653         if (pf->support_multi_driver) {
8654                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8655                 return -ENOTSUP;
8656         }
8657
8658         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8659         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8660
8661         if (len == 3) {
8662                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8663         } else if (len == 4) {
8664                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8665         } else {
8666                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8667                 return ret;
8668         }
8669
8670         if (reg != val) {
8671                 ret = i40e_aq_debug_write_global_register(hw,
8672                                                    I40E_GL_PRS_FVBM(2),
8673                                                    reg, NULL);
8674                 if (ret != 0)
8675                         return ret;
8676                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8677                             "with value 0x%08x",
8678                             I40E_GL_PRS_FVBM(2), reg);
8679         } else {
8680                 ret = 0;
8681         }
8682         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8683                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8684
8685         return ret;
8686 }
8687
8688 static int
8689 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8690 {
8691         int ret = -EINVAL;
8692
8693         if (!hw || !cfg)
8694                 return -EINVAL;
8695
8696         switch (cfg->cfg_type) {
8697         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8698                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8699                 break;
8700         default:
8701                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8702                 break;
8703         }
8704
8705         return ret;
8706 }
8707
8708 static int
8709 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8710                                enum rte_filter_op filter_op,
8711                                void *arg)
8712 {
8713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8714         int ret = I40E_ERR_PARAM;
8715
8716         switch (filter_op) {
8717         case RTE_ETH_FILTER_SET:
8718                 ret = i40e_dev_global_config_set(hw,
8719                         (struct rte_eth_global_cfg *)arg);
8720                 break;
8721         default:
8722                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8723                 break;
8724         }
8725
8726         return ret;
8727 }
8728
8729 static int
8730 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8731                           enum rte_filter_op filter_op,
8732                           void *arg)
8733 {
8734         struct rte_eth_tunnel_filter_conf *filter;
8735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8736         int ret = I40E_SUCCESS;
8737
8738         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8739
8740         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8741                 return I40E_ERR_PARAM;
8742
8743         switch (filter_op) {
8744         case RTE_ETH_FILTER_NOP:
8745                 if (!(pf->flags & I40E_FLAG_VXLAN))
8746                         ret = I40E_NOT_SUPPORTED;
8747                 break;
8748         case RTE_ETH_FILTER_ADD:
8749                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8750                 break;
8751         case RTE_ETH_FILTER_DELETE:
8752                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8753                 break;
8754         default:
8755                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8756                 ret = I40E_ERR_PARAM;
8757                 break;
8758         }
8759
8760         return ret;
8761 }
8762
8763 static int
8764 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8765 {
8766         int ret = 0;
8767         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8768
8769         /* RSS setup */
8770         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8771                 ret = i40e_pf_config_rss(pf);
8772         else
8773                 i40e_pf_disable_rss(pf);
8774
8775         return ret;
8776 }
8777
8778 /* Get the symmetric hash enable configurations per port */
8779 static void
8780 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8781 {
8782         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8783
8784         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8785 }
8786
8787 /* Set the symmetric hash enable configurations per port */
8788 static void
8789 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8790 {
8791         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8792
8793         if (enable > 0) {
8794                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8795                         PMD_DRV_LOG(INFO,
8796                                 "Symmetric hash has already been enabled");
8797                         return;
8798                 }
8799                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8800         } else {
8801                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8802                         PMD_DRV_LOG(INFO,
8803                                 "Symmetric hash has already been disabled");
8804                         return;
8805                 }
8806                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8807         }
8808         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8809         I40E_WRITE_FLUSH(hw);
8810 }
8811
8812 /*
8813  * Get global configurations of hash function type and symmetric hash enable
8814  * per flow type (pctype). Note that global configuration means it affects all
8815  * the ports on the same NIC.
8816  */
8817 static int
8818 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8819                                    struct rte_eth_hash_global_conf *g_cfg)
8820 {
8821         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8822         uint32_t reg;
8823         uint16_t i, j;
8824
8825         memset(g_cfg, 0, sizeof(*g_cfg));
8826         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8827         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8828                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8829         else
8830                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8831         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8832                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8833
8834         /*
8835          * As i40e supports less than 64 flow types, only first 64 bits need to
8836          * be checked.
8837          */
8838         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8839                 g_cfg->valid_bit_mask[i] = 0ULL;
8840                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8841         }
8842
8843         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8844
8845         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8846                 if (!adapter->pctypes_tbl[i])
8847                         continue;
8848                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8849                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8850                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8851                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8852                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8853                                         g_cfg->sym_hash_enable_mask[0] |=
8854                                                                 (1ULL << i);
8855                                 }
8856                         }
8857                 }
8858         }
8859
8860         return 0;
8861 }
8862
8863 static int
8864 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8865                               const struct rte_eth_hash_global_conf *g_cfg)
8866 {
8867         uint32_t i;
8868         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8869
8870         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8871                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8872                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8873                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8874                                                 g_cfg->hash_func);
8875                 return -EINVAL;
8876         }
8877
8878         /*
8879          * As i40e supports less than 64 flow types, only first 64 bits need to
8880          * be checked.
8881          */
8882         mask0 = g_cfg->valid_bit_mask[0];
8883         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8884                 if (i == 0) {
8885                         /* Check if any unsupported flow type configured */
8886                         if ((mask0 | i40e_mask) ^ i40e_mask)
8887                                 goto mask_err;
8888                 } else {
8889                         if (g_cfg->valid_bit_mask[i])
8890                                 goto mask_err;
8891                 }
8892         }
8893
8894         return 0;
8895
8896 mask_err:
8897         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8898
8899         return -EINVAL;
8900 }
8901
8902 /*
8903  * Set global configurations of hash function type and symmetric hash enable
8904  * per flow type (pctype). Note any modifying global configuration will affect
8905  * all the ports on the same NIC.
8906  */
8907 static int
8908 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8909                                    struct rte_eth_hash_global_conf *g_cfg)
8910 {
8911         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8912         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8913         int ret;
8914         uint16_t i, j;
8915         uint32_t reg;
8916         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8917
8918         if (pf->support_multi_driver) {
8919                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8920                 return -ENOTSUP;
8921         }
8922
8923         /* Check the input parameters */
8924         ret = i40e_hash_global_config_check(adapter, g_cfg);
8925         if (ret < 0)
8926                 return ret;
8927
8928         /*
8929          * As i40e supports less than 64 flow types, only first 64 bits need to
8930          * be configured.
8931          */
8932         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8933                 if (mask0 & (1UL << i)) {
8934                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8935                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8936
8937                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8938                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8939                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8940                                         i40e_write_global_rx_ctl(hw,
8941                                                           I40E_GLQF_HSYM(j),
8942                                                           reg);
8943                         }
8944                 }
8945         }
8946
8947         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8948         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8949                 /* Toeplitz */
8950                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8951                         PMD_DRV_LOG(DEBUG,
8952                                 "Hash function already set to Toeplitz");
8953                         goto out;
8954                 }
8955                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8956         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8957                 /* Simple XOR */
8958                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8959                         PMD_DRV_LOG(DEBUG,
8960                                 "Hash function already set to Simple XOR");
8961                         goto out;
8962                 }
8963                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8964         } else
8965                 /* Use the default, and keep it as it is */
8966                 goto out;
8967
8968         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8969
8970 out:
8971         I40E_WRITE_FLUSH(hw);
8972
8973         return 0;
8974 }
8975
8976 /**
8977  * Valid input sets for hash and flow director filters per PCTYPE
8978  */
8979 static uint64_t
8980 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8981                 enum rte_filter_type filter)
8982 {
8983         uint64_t valid;
8984
8985         static const uint64_t valid_hash_inset_table[] = {
8986                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8987                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8988                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8989                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8990                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8991                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8992                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8993                         I40E_INSET_FLEX_PAYLOAD,
8994                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8995                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8996                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8997                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8998                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8999                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9000                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9001                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9002                         I40E_INSET_FLEX_PAYLOAD,
9003                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9004                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9005                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9006                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9007                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9008                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9009                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9010                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9011                         I40E_INSET_FLEX_PAYLOAD,
9012                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9013                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9014                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9015                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9016                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9017                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9018                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9019                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9020                         I40E_INSET_FLEX_PAYLOAD,
9021                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9022                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9023                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9025                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9026                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9027                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9028                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9029                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9030                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9031                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9032                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9033                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9034                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9035                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9036                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9037                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9038                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9039                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9040                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9041                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9042                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9043                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9044                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9045                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9046                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9047                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9048                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9049                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9050                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9051                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9052                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9053                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9054                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9055                         I40E_INSET_FLEX_PAYLOAD,
9056                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9057                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9058                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9060                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9061                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9062                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9063                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9064                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9065                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9066                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9067                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9068                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9069                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9070                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9071                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9072                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9076                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9077                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9078                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9079                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9080                         I40E_INSET_FLEX_PAYLOAD,
9081                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9082                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9083                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9084                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9085                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9086                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9087                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9088                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9089                         I40E_INSET_FLEX_PAYLOAD,
9090                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9091                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9092                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9094                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9095                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9096                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9097                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9098                         I40E_INSET_FLEX_PAYLOAD,
9099                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9100                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9101                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9102                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9103                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9104                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9105                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9106                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9107                         I40E_INSET_FLEX_PAYLOAD,
9108                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9109                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9110                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9111                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9112                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9113                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9114                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9115                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9116                         I40E_INSET_FLEX_PAYLOAD,
9117                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9118                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9119                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9120                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9121                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9122                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9123                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9124                         I40E_INSET_FLEX_PAYLOAD,
9125                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9129                         I40E_INSET_FLEX_PAYLOAD,
9130         };
9131
9132         /**
9133          * Flow director supports only fields defined in
9134          * union rte_eth_fdir_flow.
9135          */
9136         static const uint64_t valid_fdir_inset_table[] = {
9137                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9138                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9139                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9140                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9141                 I40E_INSET_IPV4_TTL,
9142                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9143                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9145                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9146                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9147                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9148                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9150                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9151                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9152                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9153                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9155                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9156                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9157                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9158                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9159                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9160                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9161                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9162                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9163                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9164                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9165                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9166                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9167                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9169                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9170                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9171                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9172                 I40E_INSET_SCTP_VT,
9173                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9174                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9175                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9176                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9177                 I40E_INSET_IPV4_TTL,
9178                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9179                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9180                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9181                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9182                 I40E_INSET_IPV6_HOP_LIMIT,
9183                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9184                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9185                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9186                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9187                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9188                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9189                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9190                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9191                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9192                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9193                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9194                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9196                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9197                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9198                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9199                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9200                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9201                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9202                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9204                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9205                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9206                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9207                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9208                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9209                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9210                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9211                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9212                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9213                 I40E_INSET_SCTP_VT,
9214                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9215                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9216                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9217                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9218                 I40E_INSET_IPV6_HOP_LIMIT,
9219                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9220                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9221                 I40E_INSET_LAST_ETHER_TYPE,
9222         };
9223
9224         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9225                 return 0;
9226         if (filter == RTE_ETH_FILTER_HASH)
9227                 valid = valid_hash_inset_table[pctype];
9228         else
9229                 valid = valid_fdir_inset_table[pctype];
9230
9231         return valid;
9232 }
9233
9234 /**
9235  * Validate if the input set is allowed for a specific PCTYPE
9236  */
9237 int
9238 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9239                 enum rte_filter_type filter, uint64_t inset)
9240 {
9241         uint64_t valid;
9242
9243         valid = i40e_get_valid_input_set(pctype, filter);
9244         if (inset & (~valid))
9245                 return -EINVAL;
9246
9247         return 0;
9248 }
9249
9250 /* default input set fields combination per pctype */
9251 uint64_t
9252 i40e_get_default_input_set(uint16_t pctype)
9253 {
9254         static const uint64_t default_inset_table[] = {
9255                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9256                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9257                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9258                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9259                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9261                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9264                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9265                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9266                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9267                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9269                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9270                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9271                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9272                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9273                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9274                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9275                         I40E_INSET_SCTP_VT,
9276                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9277                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9278                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9279                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9280                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9281                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9282                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9283                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9284                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9285                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9287                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9289                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9290                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9291                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9292                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9293                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9295                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9296                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9297                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9298                         I40E_INSET_SCTP_VT,
9299                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9300                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9301                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9302                         I40E_INSET_LAST_ETHER_TYPE,
9303         };
9304
9305         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9306                 return 0;
9307
9308         return default_inset_table[pctype];
9309 }
9310
9311 /**
9312  * Parse the input set from index to logical bit masks
9313  */
9314 static int
9315 i40e_parse_input_set(uint64_t *inset,
9316                      enum i40e_filter_pctype pctype,
9317                      enum rte_eth_input_set_field *field,
9318                      uint16_t size)
9319 {
9320         uint16_t i, j;
9321         int ret = -EINVAL;
9322
9323         static const struct {
9324                 enum rte_eth_input_set_field field;
9325                 uint64_t inset;
9326         } inset_convert_table[] = {
9327                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9328                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9329                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9330                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9331                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9332                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9333                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9334                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9335                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9336                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9337                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9338                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9339                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9340                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9341                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9342                         I40E_INSET_IPV6_NEXT_HDR},
9343                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9344                         I40E_INSET_IPV6_HOP_LIMIT},
9345                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9346                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9347                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9348                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9349                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9350                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9351                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9352                         I40E_INSET_SCTP_VT},
9353                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9354                         I40E_INSET_TUNNEL_DMAC},
9355                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9356                         I40E_INSET_VLAN_TUNNEL},
9357                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9358                         I40E_INSET_TUNNEL_ID},
9359                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9360                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9361                         I40E_INSET_FLEX_PAYLOAD_W1},
9362                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9363                         I40E_INSET_FLEX_PAYLOAD_W2},
9364                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9365                         I40E_INSET_FLEX_PAYLOAD_W3},
9366                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9367                         I40E_INSET_FLEX_PAYLOAD_W4},
9368                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9369                         I40E_INSET_FLEX_PAYLOAD_W5},
9370                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9371                         I40E_INSET_FLEX_PAYLOAD_W6},
9372                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9373                         I40E_INSET_FLEX_PAYLOAD_W7},
9374                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9375                         I40E_INSET_FLEX_PAYLOAD_W8},
9376         };
9377
9378         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9379                 return ret;
9380
9381         /* Only one item allowed for default or all */
9382         if (size == 1) {
9383                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9384                         *inset = i40e_get_default_input_set(pctype);
9385                         return 0;
9386                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9387                         *inset = I40E_INSET_NONE;
9388                         return 0;
9389                 }
9390         }
9391
9392         for (i = 0, *inset = 0; i < size; i++) {
9393                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9394                         if (field[i] == inset_convert_table[j].field) {
9395                                 *inset |= inset_convert_table[j].inset;
9396                                 break;
9397                         }
9398                 }
9399
9400                 /* It contains unsupported input set, return immediately */
9401                 if (j == RTE_DIM(inset_convert_table))
9402                         return ret;
9403         }
9404
9405         return 0;
9406 }
9407
9408 /**
9409  * Translate the input set from bit masks to register aware bit masks
9410  * and vice versa
9411  */
9412 uint64_t
9413 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9414 {
9415         uint64_t val = 0;
9416         uint16_t i;
9417
9418         struct inset_map {
9419                 uint64_t inset;
9420                 uint64_t inset_reg;
9421         };
9422
9423         static const struct inset_map inset_map_common[] = {
9424                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9425                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9426                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9427                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9428                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9429                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9430                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9431                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9432                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9433                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9434                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9435                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9436                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9437                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9438                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9439                 {I40E_INSET_TUNNEL_DMAC,
9440                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9441                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9442                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9443                 {I40E_INSET_TUNNEL_SRC_PORT,
9444                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9445                 {I40E_INSET_TUNNEL_DST_PORT,
9446                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9447                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9448                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9449                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9450                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9451                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9452                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9453                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9454                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9455                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9456         };
9457
9458     /* some different registers map in x722*/
9459         static const struct inset_map inset_map_diff_x722[] = {
9460                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9461                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9462                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9463                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9464         };
9465
9466         static const struct inset_map inset_map_diff_not_x722[] = {
9467                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9468                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9469                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9470                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9471         };
9472
9473         if (input == 0)
9474                 return val;
9475
9476         /* Translate input set to register aware inset */
9477         if (type == I40E_MAC_X722) {
9478                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9479                         if (input & inset_map_diff_x722[i].inset)
9480                                 val |= inset_map_diff_x722[i].inset_reg;
9481                 }
9482         } else {
9483                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9484                         if (input & inset_map_diff_not_x722[i].inset)
9485                                 val |= inset_map_diff_not_x722[i].inset_reg;
9486                 }
9487         }
9488
9489         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9490                 if (input & inset_map_common[i].inset)
9491                         val |= inset_map_common[i].inset_reg;
9492         }
9493
9494         return val;
9495 }
9496
9497 int
9498 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9499 {
9500         uint8_t i, idx = 0;
9501         uint64_t inset_need_mask = inset;
9502
9503         static const struct {
9504                 uint64_t inset;
9505                 uint32_t mask;
9506         } inset_mask_map[] = {
9507                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9508                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9509                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9510                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9511                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9512                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9513                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9514                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9515         };
9516
9517         if (!inset || !mask || !nb_elem)
9518                 return 0;
9519
9520         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9521                 /* Clear the inset bit, if no MASK is required,
9522                  * for example proto + ttl
9523                  */
9524                 if ((inset & inset_mask_map[i].inset) ==
9525                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9526                         inset_need_mask &= ~inset_mask_map[i].inset;
9527                 if (!inset_need_mask)
9528                         return 0;
9529         }
9530         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9531                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9532                     inset_mask_map[i].inset) {
9533                         if (idx >= nb_elem) {
9534                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9535                                 return -EINVAL;
9536                         }
9537                         mask[idx] = inset_mask_map[i].mask;
9538                         idx++;
9539                 }
9540         }
9541
9542         return idx;
9543 }
9544
9545 void
9546 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9547 {
9548         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9549
9550         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9551         if (reg != val)
9552                 i40e_write_rx_ctl(hw, addr, val);
9553         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9554                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9555 }
9556
9557 void
9558 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9559 {
9560         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9561         struct rte_eth_dev *dev;
9562
9563         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9564         if (reg != val) {
9565                 i40e_write_rx_ctl(hw, addr, val);
9566                 PMD_DRV_LOG(WARNING,
9567                             "i40e device %s changed global register [0x%08x]."
9568                             " original: 0x%08x, new: 0x%08x",
9569                             dev->device->name, addr, reg,
9570                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9571         }
9572 }
9573
9574 static void
9575 i40e_filter_input_set_init(struct i40e_pf *pf)
9576 {
9577         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9578         enum i40e_filter_pctype pctype;
9579         uint64_t input_set, inset_reg;
9580         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9581         int num, i;
9582         uint16_t flow_type;
9583
9584         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9585              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9586                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9587
9588                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9589                         continue;
9590
9591                 input_set = i40e_get_default_input_set(pctype);
9592
9593                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9594                                                    I40E_INSET_MASK_NUM_REG);
9595                 if (num < 0)
9596                         return;
9597                 if (pf->support_multi_driver && num > 0) {
9598                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9599                         return;
9600                 }
9601                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9602                                         input_set);
9603
9604                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9605                                       (uint32_t)(inset_reg & UINT32_MAX));
9606                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9607                                      (uint32_t)((inset_reg >>
9608                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9609                 if (!pf->support_multi_driver) {
9610                         i40e_check_write_global_reg(hw,
9611                                             I40E_GLQF_HASH_INSET(0, pctype),
9612                                             (uint32_t)(inset_reg & UINT32_MAX));
9613                         i40e_check_write_global_reg(hw,
9614                                              I40E_GLQF_HASH_INSET(1, pctype),
9615                                              (uint32_t)((inset_reg >>
9616                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9617
9618                         for (i = 0; i < num; i++) {
9619                                 i40e_check_write_global_reg(hw,
9620                                                     I40E_GLQF_FD_MSK(i, pctype),
9621                                                     mask_reg[i]);
9622                                 i40e_check_write_global_reg(hw,
9623                                                   I40E_GLQF_HASH_MSK(i, pctype),
9624                                                   mask_reg[i]);
9625                         }
9626                         /*clear unused mask registers of the pctype */
9627                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9628                                 i40e_check_write_global_reg(hw,
9629                                                     I40E_GLQF_FD_MSK(i, pctype),
9630                                                     0);
9631                                 i40e_check_write_global_reg(hw,
9632                                                   I40E_GLQF_HASH_MSK(i, pctype),
9633                                                   0);
9634                         }
9635                 } else {
9636                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9637                 }
9638                 I40E_WRITE_FLUSH(hw);
9639
9640                 /* store the default input set */
9641                 if (!pf->support_multi_driver)
9642                         pf->hash_input_set[pctype] = input_set;
9643                 pf->fdir.input_set[pctype] = input_set;
9644         }
9645 }
9646
9647 int
9648 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9649                          struct rte_eth_input_set_conf *conf)
9650 {
9651         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9652         enum i40e_filter_pctype pctype;
9653         uint64_t input_set, inset_reg = 0;
9654         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9655         int ret, i, num;
9656
9657         if (!conf) {
9658                 PMD_DRV_LOG(ERR, "Invalid pointer");
9659                 return -EFAULT;
9660         }
9661         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9662             conf->op != RTE_ETH_INPUT_SET_ADD) {
9663                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9664                 return -EINVAL;
9665         }
9666
9667         if (pf->support_multi_driver) {
9668                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9669                 return -ENOTSUP;
9670         }
9671
9672         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9673         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9674                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9675                 return -EINVAL;
9676         }
9677
9678         if (hw->mac.type == I40E_MAC_X722) {
9679                 /* get translated pctype value in fd pctype register */
9680                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9681                         I40E_GLQF_FD_PCTYPES((int)pctype));
9682         }
9683
9684         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9685                                    conf->inset_size);
9686         if (ret) {
9687                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9688                 return -EINVAL;
9689         }
9690
9691         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9692                 /* get inset value in register */
9693                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9694                 inset_reg <<= I40E_32_BIT_WIDTH;
9695                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9696                 input_set |= pf->hash_input_set[pctype];
9697         }
9698         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9699                                            I40E_INSET_MASK_NUM_REG);
9700         if (num < 0)
9701                 return -EINVAL;
9702
9703         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9704
9705         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9706                                     (uint32_t)(inset_reg & UINT32_MAX));
9707         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9708                                     (uint32_t)((inset_reg >>
9709                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9710
9711         for (i = 0; i < num; i++)
9712                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9713                                             mask_reg[i]);
9714         /*clear unused mask registers of the pctype */
9715         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9716                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9717                                             0);
9718         I40E_WRITE_FLUSH(hw);
9719
9720         pf->hash_input_set[pctype] = input_set;
9721         return 0;
9722 }
9723
9724 int
9725 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9726                          struct rte_eth_input_set_conf *conf)
9727 {
9728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9729         enum i40e_filter_pctype pctype;
9730         uint64_t input_set, inset_reg = 0;
9731         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9732         int ret, i, num;
9733
9734         if (!hw || !conf) {
9735                 PMD_DRV_LOG(ERR, "Invalid pointer");
9736                 return -EFAULT;
9737         }
9738         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9739             conf->op != RTE_ETH_INPUT_SET_ADD) {
9740                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9741                 return -EINVAL;
9742         }
9743
9744         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9745
9746         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9747                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9748                 return -EINVAL;
9749         }
9750
9751         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9752                                    conf->inset_size);
9753         if (ret) {
9754                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9755                 return -EINVAL;
9756         }
9757
9758         /* get inset value in register */
9759         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9760         inset_reg <<= I40E_32_BIT_WIDTH;
9761         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9762
9763         /* Can not change the inset reg for flex payload for fdir,
9764          * it is done by writing I40E_PRTQF_FD_FLXINSET
9765          * in i40e_set_flex_mask_on_pctype.
9766          */
9767         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9768                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9769         else
9770                 input_set |= pf->fdir.input_set[pctype];
9771         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9772                                            I40E_INSET_MASK_NUM_REG);
9773         if (num < 0)
9774                 return -EINVAL;
9775         if (pf->support_multi_driver && num > 0) {
9776                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9777                 return -ENOTSUP;
9778         }
9779
9780         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9781
9782         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9783                               (uint32_t)(inset_reg & UINT32_MAX));
9784         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9785                              (uint32_t)((inset_reg >>
9786                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9787
9788         if (!pf->support_multi_driver) {
9789                 for (i = 0; i < num; i++)
9790                         i40e_check_write_global_reg(hw,
9791                                                     I40E_GLQF_FD_MSK(i, pctype),
9792                                                     mask_reg[i]);
9793                 /*clear unused mask registers of the pctype */
9794                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9795                         i40e_check_write_global_reg(hw,
9796                                                     I40E_GLQF_FD_MSK(i, pctype),
9797                                                     0);
9798         } else {
9799                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9800         }
9801         I40E_WRITE_FLUSH(hw);
9802
9803         pf->fdir.input_set[pctype] = input_set;
9804         return 0;
9805 }
9806
9807 static int
9808 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9809 {
9810         int ret = 0;
9811
9812         if (!hw || !info) {
9813                 PMD_DRV_LOG(ERR, "Invalid pointer");
9814                 return -EFAULT;
9815         }
9816
9817         switch (info->info_type) {
9818         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9819                 i40e_get_symmetric_hash_enable_per_port(hw,
9820                                         &(info->info.enable));
9821                 break;
9822         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9823                 ret = i40e_get_hash_filter_global_config(hw,
9824                                 &(info->info.global_conf));
9825                 break;
9826         default:
9827                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9828                                                         info->info_type);
9829                 ret = -EINVAL;
9830                 break;
9831         }
9832
9833         return ret;
9834 }
9835
9836 static int
9837 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9838 {
9839         int ret = 0;
9840
9841         if (!hw || !info) {
9842                 PMD_DRV_LOG(ERR, "Invalid pointer");
9843                 return -EFAULT;
9844         }
9845
9846         switch (info->info_type) {
9847         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9848                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9849                 break;
9850         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9851                 ret = i40e_set_hash_filter_global_config(hw,
9852                                 &(info->info.global_conf));
9853                 break;
9854         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9855                 ret = i40e_hash_filter_inset_select(hw,
9856                                                &(info->info.input_set_conf));
9857                 break;
9858
9859         default:
9860                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9861                                                         info->info_type);
9862                 ret = -EINVAL;
9863                 break;
9864         }
9865
9866         return ret;
9867 }
9868
9869 /* Operations for hash function */
9870 static int
9871 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9872                       enum rte_filter_op filter_op,
9873                       void *arg)
9874 {
9875         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9876         int ret = 0;
9877
9878         switch (filter_op) {
9879         case RTE_ETH_FILTER_NOP:
9880                 break;
9881         case RTE_ETH_FILTER_GET:
9882                 ret = i40e_hash_filter_get(hw,
9883                         (struct rte_eth_hash_filter_info *)arg);
9884                 break;
9885         case RTE_ETH_FILTER_SET:
9886                 ret = i40e_hash_filter_set(hw,
9887                         (struct rte_eth_hash_filter_info *)arg);
9888                 break;
9889         default:
9890                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9891                                                                 filter_op);
9892                 ret = -ENOTSUP;
9893                 break;
9894         }
9895
9896         return ret;
9897 }
9898
9899 /* Convert ethertype filter structure */
9900 static int
9901 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9902                               struct i40e_ethertype_filter *filter)
9903 {
9904         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9905         filter->input.ether_type = input->ether_type;
9906         filter->flags = input->flags;
9907         filter->queue = input->queue;
9908
9909         return 0;
9910 }
9911
9912 /* Check if there exists the ehtertype filter */
9913 struct i40e_ethertype_filter *
9914 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9915                                 const struct i40e_ethertype_filter_input *input)
9916 {
9917         int ret;
9918
9919         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9920         if (ret < 0)
9921                 return NULL;
9922
9923         return ethertype_rule->hash_map[ret];
9924 }
9925
9926 /* Add ethertype filter in SW list */
9927 static int
9928 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9929                                 struct i40e_ethertype_filter *filter)
9930 {
9931         struct i40e_ethertype_rule *rule = &pf->ethertype;
9932         int ret;
9933
9934         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9935         if (ret < 0) {
9936                 PMD_DRV_LOG(ERR,
9937                             "Failed to insert ethertype filter"
9938                             " to hash table %d!",
9939                             ret);
9940                 return ret;
9941         }
9942         rule->hash_map[ret] = filter;
9943
9944         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9945
9946         return 0;
9947 }
9948
9949 /* Delete ethertype filter in SW list */
9950 int
9951 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9952                              struct i40e_ethertype_filter_input *input)
9953 {
9954         struct i40e_ethertype_rule *rule = &pf->ethertype;
9955         struct i40e_ethertype_filter *filter;
9956         int ret;
9957
9958         ret = rte_hash_del_key(rule->hash_table, input);
9959         if (ret < 0) {
9960                 PMD_DRV_LOG(ERR,
9961                             "Failed to delete ethertype filter"
9962                             " to hash table %d!",
9963                             ret);
9964                 return ret;
9965         }
9966         filter = rule->hash_map[ret];
9967         rule->hash_map[ret] = NULL;
9968
9969         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9970         rte_free(filter);
9971
9972         return 0;
9973 }
9974
9975 /*
9976  * Configure ethertype filter, which can director packet by filtering
9977  * with mac address and ether_type or only ether_type
9978  */
9979 int
9980 i40e_ethertype_filter_set(struct i40e_pf *pf,
9981                         struct rte_eth_ethertype_filter *filter,
9982                         bool add)
9983 {
9984         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9985         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9986         struct i40e_ethertype_filter *ethertype_filter, *node;
9987         struct i40e_ethertype_filter check_filter;
9988         struct i40e_control_filter_stats stats;
9989         uint16_t flags = 0;
9990         int ret;
9991
9992         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9993                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9994                 return -EINVAL;
9995         }
9996         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9997                 filter->ether_type == ETHER_TYPE_IPv6) {
9998                 PMD_DRV_LOG(ERR,
9999                         "unsupported ether_type(0x%04x) in control packet filter.",
10000                         filter->ether_type);
10001                 return -EINVAL;
10002         }
10003         if (filter->ether_type == ETHER_TYPE_VLAN)
10004                 PMD_DRV_LOG(WARNING,
10005                         "filter vlan ether_type in first tag is not supported.");
10006
10007         /* Check if there is the filter in SW list */
10008         memset(&check_filter, 0, sizeof(check_filter));
10009         i40e_ethertype_filter_convert(filter, &check_filter);
10010         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10011                                                &check_filter.input);
10012         if (add && node) {
10013                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10014                 return -EINVAL;
10015         }
10016
10017         if (!add && !node) {
10018                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10019                 return -EINVAL;
10020         }
10021
10022         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10023                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10024         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10025                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10026         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10027
10028         memset(&stats, 0, sizeof(stats));
10029         ret = i40e_aq_add_rem_control_packet_filter(hw,
10030                         filter->mac_addr.addr_bytes,
10031                         filter->ether_type, flags,
10032                         pf->main_vsi->seid,
10033                         filter->queue, add, &stats, NULL);
10034
10035         PMD_DRV_LOG(INFO,
10036                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10037                 ret, stats.mac_etype_used, stats.etype_used,
10038                 stats.mac_etype_free, stats.etype_free);
10039         if (ret < 0)
10040                 return -ENOSYS;
10041
10042         /* Add or delete a filter in SW list */
10043         if (add) {
10044                 ethertype_filter = rte_zmalloc("ethertype_filter",
10045                                        sizeof(*ethertype_filter), 0);
10046                 if (ethertype_filter == NULL) {
10047                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10048                         return -ENOMEM;
10049                 }
10050
10051                 rte_memcpy(ethertype_filter, &check_filter,
10052                            sizeof(check_filter));
10053                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10054                 if (ret < 0)
10055                         rte_free(ethertype_filter);
10056         } else {
10057                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10058         }
10059
10060         return ret;
10061 }
10062
10063 /*
10064  * Handle operations for ethertype filter.
10065  */
10066 static int
10067 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10068                                 enum rte_filter_op filter_op,
10069                                 void *arg)
10070 {
10071         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10072         int ret = 0;
10073
10074         if (filter_op == RTE_ETH_FILTER_NOP)
10075                 return ret;
10076
10077         if (arg == NULL) {
10078                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10079                             filter_op);
10080                 return -EINVAL;
10081         }
10082
10083         switch (filter_op) {
10084         case RTE_ETH_FILTER_ADD:
10085                 ret = i40e_ethertype_filter_set(pf,
10086                         (struct rte_eth_ethertype_filter *)arg,
10087                         TRUE);
10088                 break;
10089         case RTE_ETH_FILTER_DELETE:
10090                 ret = i40e_ethertype_filter_set(pf,
10091                         (struct rte_eth_ethertype_filter *)arg,
10092                         FALSE);
10093                 break;
10094         default:
10095                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10096                 ret = -ENOSYS;
10097                 break;
10098         }
10099         return ret;
10100 }
10101
10102 static int
10103 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10104                      enum rte_filter_type filter_type,
10105                      enum rte_filter_op filter_op,
10106                      void *arg)
10107 {
10108         int ret = 0;
10109
10110         if (dev == NULL)
10111                 return -EINVAL;
10112
10113         switch (filter_type) {
10114         case RTE_ETH_FILTER_NONE:
10115                 /* For global configuration */
10116                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10117                 break;
10118         case RTE_ETH_FILTER_HASH:
10119                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10120                 break;
10121         case RTE_ETH_FILTER_MACVLAN:
10122                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10123                 break;
10124         case RTE_ETH_FILTER_ETHERTYPE:
10125                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10126                 break;
10127         case RTE_ETH_FILTER_TUNNEL:
10128                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10129                 break;
10130         case RTE_ETH_FILTER_FDIR:
10131                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10132                 break;
10133         case RTE_ETH_FILTER_GENERIC:
10134                 if (filter_op != RTE_ETH_FILTER_GET)
10135                         return -EINVAL;
10136                 *(const void **)arg = &i40e_flow_ops;
10137                 break;
10138         default:
10139                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10140                                                         filter_type);
10141                 ret = -EINVAL;
10142                 break;
10143         }
10144
10145         return ret;
10146 }
10147
10148 /*
10149  * Check and enable Extended Tag.
10150  * Enabling Extended Tag is important for 40G performance.
10151  */
10152 static void
10153 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10154 {
10155         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10156         uint32_t buf = 0;
10157         int ret;
10158
10159         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10160                                       PCI_DEV_CAP_REG);
10161         if (ret < 0) {
10162                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10163                             PCI_DEV_CAP_REG);
10164                 return;
10165         }
10166         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10167                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10168                 return;
10169         }
10170
10171         buf = 0;
10172         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10173                                       PCI_DEV_CTRL_REG);
10174         if (ret < 0) {
10175                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10176                             PCI_DEV_CTRL_REG);
10177                 return;
10178         }
10179         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10180                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10181                 return;
10182         }
10183         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10184         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10185                                        PCI_DEV_CTRL_REG);
10186         if (ret < 0) {
10187                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10188                             PCI_DEV_CTRL_REG);
10189                 return;
10190         }
10191 }
10192
10193 /*
10194  * As some registers wouldn't be reset unless a global hardware reset,
10195  * hardware initialization is needed to put those registers into an
10196  * expected initial state.
10197  */
10198 static void
10199 i40e_hw_init(struct rte_eth_dev *dev)
10200 {
10201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10202
10203         i40e_enable_extended_tag(dev);
10204
10205         /* clear the PF Queue Filter control register */
10206         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10207
10208         /* Disable symmetric hash per port */
10209         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10210 }
10211
10212 /*
10213  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10214  * however this function will return only one highest pctype index,
10215  * which is not quite correct. This is known problem of i40e driver
10216  * and needs to be fixed later.
10217  */
10218 enum i40e_filter_pctype
10219 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10220 {
10221         int i;
10222         uint64_t pctype_mask;
10223
10224         if (flow_type < I40E_FLOW_TYPE_MAX) {
10225                 pctype_mask = adapter->pctypes_tbl[flow_type];
10226                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10227                         if (pctype_mask & (1ULL << i))
10228                                 return (enum i40e_filter_pctype)i;
10229                 }
10230         }
10231         return I40E_FILTER_PCTYPE_INVALID;
10232 }
10233
10234 uint16_t
10235 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10236                         enum i40e_filter_pctype pctype)
10237 {
10238         uint16_t flowtype;
10239         uint64_t pctype_mask = 1ULL << pctype;
10240
10241         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10242              flowtype++) {
10243                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10244                         return flowtype;
10245         }
10246
10247         return RTE_ETH_FLOW_UNKNOWN;
10248 }
10249
10250 /*
10251  * On X710, performance number is far from the expectation on recent firmware
10252  * versions; on XL710, performance number is also far from the expectation on
10253  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10254  * mode is enabled and port MAC address is equal to the packet destination MAC
10255  * address. The fix for this issue may not be integrated in the following
10256  * firmware version. So the workaround in software driver is needed. It needs
10257  * to modify the initial values of 3 internal only registers for both X710 and
10258  * XL710. Note that the values for X710 or XL710 could be different, and the
10259  * workaround can be removed when it is fixed in firmware in the future.
10260  */
10261
10262 /* For both X710 and XL710 */
10263 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10264 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10265 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10266
10267 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10268 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10269
10270 /* For X722 */
10271 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10272 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10273
10274 /* For X710 */
10275 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10276 /* For XL710 */
10277 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10278 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10279
10280 /*
10281  * GL_SWR_PM_UP_THR:
10282  * The value is not impacted from the link speed, its value is set according
10283  * to the total number of ports for a better pipe-monitor configuration.
10284  */
10285 static bool
10286 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10287 {
10288 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10289                 .device_id = (dev),   \
10290                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10291
10292 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10293                 .device_id = (dev),   \
10294                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10295
10296         static const struct {
10297                 uint16_t device_id;
10298                 uint32_t val;
10299         } swr_pm_table[] = {
10300                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10301                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10302                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10303                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10304
10305                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10306                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10307                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10308                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10309                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10310                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10311                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10312         };
10313         uint32_t i;
10314
10315         if (value == NULL) {
10316                 PMD_DRV_LOG(ERR, "value is NULL");
10317                 return false;
10318         }
10319
10320         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10321                 if (hw->device_id == swr_pm_table[i].device_id) {
10322                         *value = swr_pm_table[i].val;
10323
10324                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10325                                     "value - 0x%08x",
10326                                     hw->device_id, *value);
10327                         return true;
10328                 }
10329         }
10330
10331         return false;
10332 }
10333
10334 static int
10335 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10336 {
10337         enum i40e_status_code status;
10338         struct i40e_aq_get_phy_abilities_resp phy_ab;
10339         int ret = -ENOTSUP;
10340         int retries = 0;
10341
10342         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10343                                               NULL);
10344
10345         while (status) {
10346                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10347                         status);
10348                 retries++;
10349                 rte_delay_us(100000);
10350                 if  (retries < 5)
10351                         status = i40e_aq_get_phy_capabilities(hw, false,
10352                                         true, &phy_ab, NULL);
10353                 else
10354                         return ret;
10355         }
10356         return 0;
10357 }
10358
10359 static void
10360 i40e_configure_registers(struct i40e_hw *hw)
10361 {
10362         static struct {
10363                 uint32_t addr;
10364                 uint64_t val;
10365         } reg_table[] = {
10366                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10367                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10368                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10369         };
10370         uint64_t reg;
10371         uint32_t i;
10372         int ret;
10373
10374         for (i = 0; i < RTE_DIM(reg_table); i++) {
10375                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10376                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10377                                 reg_table[i].val =
10378                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10379                         else /* For X710/XL710/XXV710 */
10380                                 if (hw->aq.fw_maj_ver < 6)
10381                                         reg_table[i].val =
10382                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10383                                 else
10384                                         reg_table[i].val =
10385                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10386                 }
10387
10388                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10389                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10390                                 reg_table[i].val =
10391                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10392                         else /* For X710/XL710/XXV710 */
10393                                 reg_table[i].val =
10394                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10395                 }
10396
10397                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10398                         uint32_t cfg_val;
10399
10400                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10401                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10402                                             "GL_SWR_PM_UP_THR value fixup",
10403                                             hw->device_id);
10404                                 continue;
10405                         }
10406
10407                         reg_table[i].val = cfg_val;
10408                 }
10409
10410                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10411                                                         &reg, NULL);
10412                 if (ret < 0) {
10413                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10414                                                         reg_table[i].addr);
10415                         break;
10416                 }
10417                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10418                                                 reg_table[i].addr, reg);
10419                 if (reg == reg_table[i].val)
10420                         continue;
10421
10422                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10423                                                 reg_table[i].val, NULL);
10424                 if (ret < 0) {
10425                         PMD_DRV_LOG(ERR,
10426                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10427                                 reg_table[i].val, reg_table[i].addr);
10428                         break;
10429                 }
10430                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10431                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10432         }
10433 }
10434
10435 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10436 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10437 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10438 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10439 static int
10440 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10441 {
10442         uint32_t reg;
10443         int ret;
10444
10445         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10446                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10447                 return -EINVAL;
10448         }
10449
10450         /* Configure for double VLAN RX stripping */
10451         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10452         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10453                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10454                 ret = i40e_aq_debug_write_register(hw,
10455                                                    I40E_VSI_TSR(vsi->vsi_id),
10456                                                    reg, NULL);
10457                 if (ret < 0) {
10458                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10459                                     vsi->vsi_id);
10460                         return I40E_ERR_CONFIG;
10461                 }
10462         }
10463
10464         /* Configure for double VLAN TX insertion */
10465         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10466         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10467                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10468                 ret = i40e_aq_debug_write_register(hw,
10469                                                    I40E_VSI_L2TAGSTXVALID(
10470                                                    vsi->vsi_id), reg, NULL);
10471                 if (ret < 0) {
10472                         PMD_DRV_LOG(ERR,
10473                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10474                                 vsi->vsi_id);
10475                         return I40E_ERR_CONFIG;
10476                 }
10477         }
10478
10479         return 0;
10480 }
10481
10482 /**
10483  * i40e_aq_add_mirror_rule
10484  * @hw: pointer to the hardware structure
10485  * @seid: VEB seid to add mirror rule to
10486  * @dst_id: destination vsi seid
10487  * @entries: Buffer which contains the entities to be mirrored
10488  * @count: number of entities contained in the buffer
10489  * @rule_id:the rule_id of the rule to be added
10490  *
10491  * Add a mirror rule for a given veb.
10492  *
10493  **/
10494 static enum i40e_status_code
10495 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10496                         uint16_t seid, uint16_t dst_id,
10497                         uint16_t rule_type, uint16_t *entries,
10498                         uint16_t count, uint16_t *rule_id)
10499 {
10500         struct i40e_aq_desc desc;
10501         struct i40e_aqc_add_delete_mirror_rule cmd;
10502         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10503                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10504                 &desc.params.raw;
10505         uint16_t buff_len;
10506         enum i40e_status_code status;
10507
10508         i40e_fill_default_direct_cmd_desc(&desc,
10509                                           i40e_aqc_opc_add_mirror_rule);
10510         memset(&cmd, 0, sizeof(cmd));
10511
10512         buff_len = sizeof(uint16_t) * count;
10513         desc.datalen = rte_cpu_to_le_16(buff_len);
10514         if (buff_len > 0)
10515                 desc.flags |= rte_cpu_to_le_16(
10516                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10517         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10518                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10519         cmd.num_entries = rte_cpu_to_le_16(count);
10520         cmd.seid = rte_cpu_to_le_16(seid);
10521         cmd.destination = rte_cpu_to_le_16(dst_id);
10522
10523         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10524         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10525         PMD_DRV_LOG(INFO,
10526                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10527                 hw->aq.asq_last_status, resp->rule_id,
10528                 resp->mirror_rules_used, resp->mirror_rules_free);
10529         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10530
10531         return status;
10532 }
10533
10534 /**
10535  * i40e_aq_del_mirror_rule
10536  * @hw: pointer to the hardware structure
10537  * @seid: VEB seid to add mirror rule to
10538  * @entries: Buffer which contains the entities to be mirrored
10539  * @count: number of entities contained in the buffer
10540  * @rule_id:the rule_id of the rule to be delete
10541  *
10542  * Delete a mirror rule for a given veb.
10543  *
10544  **/
10545 static enum i40e_status_code
10546 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10547                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10548                 uint16_t count, uint16_t rule_id)
10549 {
10550         struct i40e_aq_desc desc;
10551         struct i40e_aqc_add_delete_mirror_rule cmd;
10552         uint16_t buff_len = 0;
10553         enum i40e_status_code status;
10554         void *buff = NULL;
10555
10556         i40e_fill_default_direct_cmd_desc(&desc,
10557                                           i40e_aqc_opc_delete_mirror_rule);
10558         memset(&cmd, 0, sizeof(cmd));
10559         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10560                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10561                                                           I40E_AQ_FLAG_RD));
10562                 cmd.num_entries = count;
10563                 buff_len = sizeof(uint16_t) * count;
10564                 desc.datalen = rte_cpu_to_le_16(buff_len);
10565                 buff = (void *)entries;
10566         } else
10567                 /* rule id is filled in destination field for deleting mirror rule */
10568                 cmd.destination = rte_cpu_to_le_16(rule_id);
10569
10570         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10571                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10572         cmd.seid = rte_cpu_to_le_16(seid);
10573
10574         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10575         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10576
10577         return status;
10578 }
10579
10580 /**
10581  * i40e_mirror_rule_set
10582  * @dev: pointer to the hardware structure
10583  * @mirror_conf: mirror rule info
10584  * @sw_id: mirror rule's sw_id
10585  * @on: enable/disable
10586  *
10587  * set a mirror rule.
10588  *
10589  **/
10590 static int
10591 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10592                         struct rte_eth_mirror_conf *mirror_conf,
10593                         uint8_t sw_id, uint8_t on)
10594 {
10595         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10597         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10598         struct i40e_mirror_rule *parent = NULL;
10599         uint16_t seid, dst_seid, rule_id;
10600         uint16_t i, j = 0;
10601         int ret;
10602
10603         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10604
10605         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10606                 PMD_DRV_LOG(ERR,
10607                         "mirror rule can not be configured without veb or vfs.");
10608                 return -ENOSYS;
10609         }
10610         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10611                 PMD_DRV_LOG(ERR, "mirror table is full.");
10612                 return -ENOSPC;
10613         }
10614         if (mirror_conf->dst_pool > pf->vf_num) {
10615                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10616                                  mirror_conf->dst_pool);
10617                 return -EINVAL;
10618         }
10619
10620         seid = pf->main_vsi->veb->seid;
10621
10622         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10623                 if (sw_id <= it->index) {
10624                         mirr_rule = it;
10625                         break;
10626                 }
10627                 parent = it;
10628         }
10629         if (mirr_rule && sw_id == mirr_rule->index) {
10630                 if (on) {
10631                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10632                         return -EEXIST;
10633                 } else {
10634                         ret = i40e_aq_del_mirror_rule(hw, seid,
10635                                         mirr_rule->rule_type,
10636                                         mirr_rule->entries,
10637                                         mirr_rule->num_entries, mirr_rule->id);
10638                         if (ret < 0) {
10639                                 PMD_DRV_LOG(ERR,
10640                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10641                                         ret, hw->aq.asq_last_status);
10642                                 return -ENOSYS;
10643                         }
10644                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10645                         rte_free(mirr_rule);
10646                         pf->nb_mirror_rule--;
10647                         return 0;
10648                 }
10649         } else if (!on) {
10650                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10651                 return -ENOENT;
10652         }
10653
10654         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10655                                 sizeof(struct i40e_mirror_rule) , 0);
10656         if (!mirr_rule) {
10657                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10658                 return I40E_ERR_NO_MEMORY;
10659         }
10660         switch (mirror_conf->rule_type) {
10661         case ETH_MIRROR_VLAN:
10662                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10663                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10664                                 mirr_rule->entries[j] =
10665                                         mirror_conf->vlan.vlan_id[i];
10666                                 j++;
10667                         }
10668                 }
10669                 if (j == 0) {
10670                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10671                         rte_free(mirr_rule);
10672                         return -EINVAL;
10673                 }
10674                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10675                 break;
10676         case ETH_MIRROR_VIRTUAL_POOL_UP:
10677         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10678                 /* check if the specified pool bit is out of range */
10679                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10680                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10681                         rte_free(mirr_rule);
10682                         return -EINVAL;
10683                 }
10684                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10685                         if (mirror_conf->pool_mask & (1ULL << i)) {
10686                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10687                                 j++;
10688                         }
10689                 }
10690                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10691                         /* add pf vsi to entries */
10692                         mirr_rule->entries[j] = pf->main_vsi_seid;
10693                         j++;
10694                 }
10695                 if (j == 0) {
10696                         PMD_DRV_LOG(ERR, "pool is not specified.");
10697                         rte_free(mirr_rule);
10698                         return -EINVAL;
10699                 }
10700                 /* egress and ingress in aq commands means from switch but not port */
10701                 mirr_rule->rule_type =
10702                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10703                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10704                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10705                 break;
10706         case ETH_MIRROR_UPLINK_PORT:
10707                 /* egress and ingress in aq commands means from switch but not port*/
10708                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10709                 break;
10710         case ETH_MIRROR_DOWNLINK_PORT:
10711                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10712                 break;
10713         default:
10714                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10715                         mirror_conf->rule_type);
10716                 rte_free(mirr_rule);
10717                 return -EINVAL;
10718         }
10719
10720         /* If the dst_pool is equal to vf_num, consider it as PF */
10721         if (mirror_conf->dst_pool == pf->vf_num)
10722                 dst_seid = pf->main_vsi_seid;
10723         else
10724                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10725
10726         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10727                                       mirr_rule->rule_type, mirr_rule->entries,
10728                                       j, &rule_id);
10729         if (ret < 0) {
10730                 PMD_DRV_LOG(ERR,
10731                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10732                         ret, hw->aq.asq_last_status);
10733                 rte_free(mirr_rule);
10734                 return -ENOSYS;
10735         }
10736
10737         mirr_rule->index = sw_id;
10738         mirr_rule->num_entries = j;
10739         mirr_rule->id = rule_id;
10740         mirr_rule->dst_vsi_seid = dst_seid;
10741
10742         if (parent)
10743                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10744         else
10745                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10746
10747         pf->nb_mirror_rule++;
10748         return 0;
10749 }
10750
10751 /**
10752  * i40e_mirror_rule_reset
10753  * @dev: pointer to the device
10754  * @sw_id: mirror rule's sw_id
10755  *
10756  * reset a mirror rule.
10757  *
10758  **/
10759 static int
10760 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10761 {
10762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10764         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10765         uint16_t seid;
10766         int ret;
10767
10768         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10769
10770         seid = pf->main_vsi->veb->seid;
10771
10772         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10773                 if (sw_id == it->index) {
10774                         mirr_rule = it;
10775                         break;
10776                 }
10777         }
10778         if (mirr_rule) {
10779                 ret = i40e_aq_del_mirror_rule(hw, seid,
10780                                 mirr_rule->rule_type,
10781                                 mirr_rule->entries,
10782                                 mirr_rule->num_entries, mirr_rule->id);
10783                 if (ret < 0) {
10784                         PMD_DRV_LOG(ERR,
10785                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10786                                 ret, hw->aq.asq_last_status);
10787                         return -ENOSYS;
10788                 }
10789                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10790                 rte_free(mirr_rule);
10791                 pf->nb_mirror_rule--;
10792         } else {
10793                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10794                 return -ENOENT;
10795         }
10796         return 0;
10797 }
10798
10799 static uint64_t
10800 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10801 {
10802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10803         uint64_t systim_cycles;
10804
10805         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10806         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10807                         << 32;
10808
10809         return systim_cycles;
10810 }
10811
10812 static uint64_t
10813 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10814 {
10815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10816         uint64_t rx_tstamp;
10817
10818         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10819         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10820                         << 32;
10821
10822         return rx_tstamp;
10823 }
10824
10825 static uint64_t
10826 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10827 {
10828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10829         uint64_t tx_tstamp;
10830
10831         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10832         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10833                         << 32;
10834
10835         return tx_tstamp;
10836 }
10837
10838 static void
10839 i40e_start_timecounters(struct rte_eth_dev *dev)
10840 {
10841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10842         struct i40e_adapter *adapter =
10843                         (struct i40e_adapter *)dev->data->dev_private;
10844         struct rte_eth_link link;
10845         uint32_t tsync_inc_l;
10846         uint32_t tsync_inc_h;
10847
10848         /* Get current link speed. */
10849         i40e_dev_link_update(dev, 1);
10850         rte_eth_linkstatus_get(dev, &link);
10851
10852         switch (link.link_speed) {
10853         case ETH_SPEED_NUM_40G:
10854         case ETH_SPEED_NUM_25G:
10855                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10856                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10857                 break;
10858         case ETH_SPEED_NUM_10G:
10859                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10860                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10861                 break;
10862         case ETH_SPEED_NUM_1G:
10863                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10864                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10865                 break;
10866         default:
10867                 tsync_inc_l = 0x0;
10868                 tsync_inc_h = 0x0;
10869         }
10870
10871         /* Set the timesync increment value. */
10872         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10873         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10874
10875         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10876         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10877         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10878
10879         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10880         adapter->systime_tc.cc_shift = 0;
10881         adapter->systime_tc.nsec_mask = 0;
10882
10883         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10884         adapter->rx_tstamp_tc.cc_shift = 0;
10885         adapter->rx_tstamp_tc.nsec_mask = 0;
10886
10887         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10888         adapter->tx_tstamp_tc.cc_shift = 0;
10889         adapter->tx_tstamp_tc.nsec_mask = 0;
10890 }
10891
10892 static int
10893 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10894 {
10895         struct i40e_adapter *adapter =
10896                         (struct i40e_adapter *)dev->data->dev_private;
10897
10898         adapter->systime_tc.nsec += delta;
10899         adapter->rx_tstamp_tc.nsec += delta;
10900         adapter->tx_tstamp_tc.nsec += delta;
10901
10902         return 0;
10903 }
10904
10905 static int
10906 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10907 {
10908         uint64_t ns;
10909         struct i40e_adapter *adapter =
10910                         (struct i40e_adapter *)dev->data->dev_private;
10911
10912         ns = rte_timespec_to_ns(ts);
10913
10914         /* Set the timecounters to a new value. */
10915         adapter->systime_tc.nsec = ns;
10916         adapter->rx_tstamp_tc.nsec = ns;
10917         adapter->tx_tstamp_tc.nsec = ns;
10918
10919         return 0;
10920 }
10921
10922 static int
10923 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10924 {
10925         uint64_t ns, systime_cycles;
10926         struct i40e_adapter *adapter =
10927                         (struct i40e_adapter *)dev->data->dev_private;
10928
10929         systime_cycles = i40e_read_systime_cyclecounter(dev);
10930         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10931         *ts = rte_ns_to_timespec(ns);
10932
10933         return 0;
10934 }
10935
10936 static int
10937 i40e_timesync_enable(struct rte_eth_dev *dev)
10938 {
10939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10940         uint32_t tsync_ctl_l;
10941         uint32_t tsync_ctl_h;
10942
10943         /* Stop the timesync system time. */
10944         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10945         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10946         /* Reset the timesync system time value. */
10947         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10948         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10949
10950         i40e_start_timecounters(dev);
10951
10952         /* Clear timesync registers. */
10953         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10954         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10955         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10956         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10957         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10958         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10959
10960         /* Enable timestamping of PTP packets. */
10961         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10962         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10963
10964         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10965         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10966         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10967
10968         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10969         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10970
10971         return 0;
10972 }
10973
10974 static int
10975 i40e_timesync_disable(struct rte_eth_dev *dev)
10976 {
10977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10978         uint32_t tsync_ctl_l;
10979         uint32_t tsync_ctl_h;
10980
10981         /* Disable timestamping of transmitted PTP packets. */
10982         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10983         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10984
10985         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10986         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10987
10988         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10989         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10990
10991         /* Reset the timesync increment value. */
10992         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10993         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10994
10995         return 0;
10996 }
10997
10998 static int
10999 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11000                                 struct timespec *timestamp, uint32_t flags)
11001 {
11002         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11003         struct i40e_adapter *adapter =
11004                 (struct i40e_adapter *)dev->data->dev_private;
11005
11006         uint32_t sync_status;
11007         uint32_t index = flags & 0x03;
11008         uint64_t rx_tstamp_cycles;
11009         uint64_t ns;
11010
11011         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11012         if ((sync_status & (1 << index)) == 0)
11013                 return -EINVAL;
11014
11015         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11016         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11017         *timestamp = rte_ns_to_timespec(ns);
11018
11019         return 0;
11020 }
11021
11022 static int
11023 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11024                                 struct timespec *timestamp)
11025 {
11026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11027         struct i40e_adapter *adapter =
11028                 (struct i40e_adapter *)dev->data->dev_private;
11029
11030         uint32_t sync_status;
11031         uint64_t tx_tstamp_cycles;
11032         uint64_t ns;
11033
11034         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11035         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11036                 return -EINVAL;
11037
11038         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11039         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11040         *timestamp = rte_ns_to_timespec(ns);
11041
11042         return 0;
11043 }
11044
11045 /*
11046  * i40e_parse_dcb_configure - parse dcb configure from user
11047  * @dev: the device being configured
11048  * @dcb_cfg: pointer of the result of parse
11049  * @*tc_map: bit map of enabled traffic classes
11050  *
11051  * Returns 0 on success, negative value on failure
11052  */
11053 static int
11054 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11055                          struct i40e_dcbx_config *dcb_cfg,
11056                          uint8_t *tc_map)
11057 {
11058         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11059         uint8_t i, tc_bw, bw_lf;
11060
11061         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11062
11063         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11064         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11065                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11066                 return -EINVAL;
11067         }
11068
11069         /* assume each tc has the same bw */
11070         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11071         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11072                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11073         /* to ensure the sum of tcbw is equal to 100 */
11074         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11075         for (i = 0; i < bw_lf; i++)
11076                 dcb_cfg->etscfg.tcbwtable[i]++;
11077
11078         /* assume each tc has the same Transmission Selection Algorithm */
11079         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11080                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11081
11082         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11083                 dcb_cfg->etscfg.prioritytable[i] =
11084                                 dcb_rx_conf->dcb_tc[i];
11085
11086         /* FW needs one App to configure HW */
11087         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11088         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11089         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11090         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11091
11092         if (dcb_rx_conf->nb_tcs == 0)
11093                 *tc_map = 1; /* tc0 only */
11094         else
11095                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11096
11097         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11098                 dcb_cfg->pfc.willing = 0;
11099                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11100                 dcb_cfg->pfc.pfcenable = *tc_map;
11101         }
11102         return 0;
11103 }
11104
11105
11106 static enum i40e_status_code
11107 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11108                               struct i40e_aqc_vsi_properties_data *info,
11109                               uint8_t enabled_tcmap)
11110 {
11111         enum i40e_status_code ret;
11112         int i, total_tc = 0;
11113         uint16_t qpnum_per_tc, bsf, qp_idx;
11114         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11115         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11116         uint16_t used_queues;
11117
11118         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11119         if (ret != I40E_SUCCESS)
11120                 return ret;
11121
11122         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11123                 if (enabled_tcmap & (1 << i))
11124                         total_tc++;
11125         }
11126         if (total_tc == 0)
11127                 total_tc = 1;
11128         vsi->enabled_tc = enabled_tcmap;
11129
11130         /* different VSI has different queues assigned */
11131         if (vsi->type == I40E_VSI_MAIN)
11132                 used_queues = dev_data->nb_rx_queues -
11133                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11134         else if (vsi->type == I40E_VSI_VMDQ2)
11135                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11136         else {
11137                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11138                 return I40E_ERR_NO_AVAILABLE_VSI;
11139         }
11140
11141         qpnum_per_tc = used_queues / total_tc;
11142         /* Number of queues per enabled TC */
11143         if (qpnum_per_tc == 0) {
11144                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11145                 return I40E_ERR_INVALID_QP_ID;
11146         }
11147         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11148                                 I40E_MAX_Q_PER_TC);
11149         bsf = rte_bsf32(qpnum_per_tc);
11150
11151         /**
11152          * Configure TC and queue mapping parameters, for enabled TC,
11153          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11154          * default queue will serve it.
11155          */
11156         qp_idx = 0;
11157         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11158                 if (vsi->enabled_tc & (1 << i)) {
11159                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11160                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11161                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11162                         qp_idx += qpnum_per_tc;
11163                 } else
11164                         info->tc_mapping[i] = 0;
11165         }
11166
11167         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11168         if (vsi->type == I40E_VSI_SRIOV) {
11169                 info->mapping_flags |=
11170                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11171                 for (i = 0; i < vsi->nb_qps; i++)
11172                         info->queue_mapping[i] =
11173                                 rte_cpu_to_le_16(vsi->base_queue + i);
11174         } else {
11175                 info->mapping_flags |=
11176                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11177                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11178         }
11179         info->valid_sections |=
11180                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11181
11182         return I40E_SUCCESS;
11183 }
11184
11185 /*
11186  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11187  * @veb: VEB to be configured
11188  * @tc_map: enabled TC bitmap
11189  *
11190  * Returns 0 on success, negative value on failure
11191  */
11192 static enum i40e_status_code
11193 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11194 {
11195         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11196         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11197         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11198         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11199         enum i40e_status_code ret = I40E_SUCCESS;
11200         int i;
11201         uint32_t bw_max;
11202
11203         /* Check if enabled_tc is same as existing or new TCs */
11204         if (veb->enabled_tc == tc_map)
11205                 return ret;
11206
11207         /* configure tc bandwidth */
11208         memset(&veb_bw, 0, sizeof(veb_bw));
11209         veb_bw.tc_valid_bits = tc_map;
11210         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11211         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11212                 if (tc_map & BIT_ULL(i))
11213                         veb_bw.tc_bw_share_credits[i] = 1;
11214         }
11215         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11216                                                    &veb_bw, NULL);
11217         if (ret) {
11218                 PMD_INIT_LOG(ERR,
11219                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11220                         hw->aq.asq_last_status);
11221                 return ret;
11222         }
11223
11224         memset(&ets_query, 0, sizeof(ets_query));
11225         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11226                                                    &ets_query, NULL);
11227         if (ret != I40E_SUCCESS) {
11228                 PMD_DRV_LOG(ERR,
11229                         "Failed to get switch_comp ETS configuration %u",
11230                         hw->aq.asq_last_status);
11231                 return ret;
11232         }
11233         memset(&bw_query, 0, sizeof(bw_query));
11234         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11235                                                   &bw_query, NULL);
11236         if (ret != I40E_SUCCESS) {
11237                 PMD_DRV_LOG(ERR,
11238                         "Failed to get switch_comp bandwidth configuration %u",
11239                         hw->aq.asq_last_status);
11240                 return ret;
11241         }
11242
11243         /* store and print out BW info */
11244         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11245         veb->bw_info.bw_max = ets_query.tc_bw_max;
11246         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11247         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11248         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11249                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11250                      I40E_16_BIT_WIDTH);
11251         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11252                 veb->bw_info.bw_ets_share_credits[i] =
11253                                 bw_query.tc_bw_share_credits[i];
11254                 veb->bw_info.bw_ets_credits[i] =
11255                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11256                 /* 4 bits per TC, 4th bit is reserved */
11257                 veb->bw_info.bw_ets_max[i] =
11258                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11259                                   RTE_LEN2MASK(3, uint8_t));
11260                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11261                             veb->bw_info.bw_ets_share_credits[i]);
11262                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11263                             veb->bw_info.bw_ets_credits[i]);
11264                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11265                             veb->bw_info.bw_ets_max[i]);
11266         }
11267
11268         veb->enabled_tc = tc_map;
11269
11270         return ret;
11271 }
11272
11273
11274 /*
11275  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11276  * @vsi: VSI to be configured
11277  * @tc_map: enabled TC bitmap
11278  *
11279  * Returns 0 on success, negative value on failure
11280  */
11281 static enum i40e_status_code
11282 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11283 {
11284         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11285         struct i40e_vsi_context ctxt;
11286         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11287         enum i40e_status_code ret = I40E_SUCCESS;
11288         int i;
11289
11290         /* Check if enabled_tc is same as existing or new TCs */
11291         if (vsi->enabled_tc == tc_map)
11292                 return ret;
11293
11294         /* configure tc bandwidth */
11295         memset(&bw_data, 0, sizeof(bw_data));
11296         bw_data.tc_valid_bits = tc_map;
11297         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11298         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11299                 if (tc_map & BIT_ULL(i))
11300                         bw_data.tc_bw_credits[i] = 1;
11301         }
11302         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11303         if (ret) {
11304                 PMD_INIT_LOG(ERR,
11305                         "AQ command Config VSI BW allocation per TC failed = %d",
11306                         hw->aq.asq_last_status);
11307                 goto out;
11308         }
11309         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11310                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11311
11312         /* Update Queue Pairs Mapping for currently enabled UPs */
11313         ctxt.seid = vsi->seid;
11314         ctxt.pf_num = hw->pf_id;
11315         ctxt.vf_num = 0;
11316         ctxt.uplink_seid = vsi->uplink_seid;
11317         ctxt.info = vsi->info;
11318         i40e_get_cap(hw);
11319         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11320         if (ret)
11321                 goto out;
11322
11323         /* Update the VSI after updating the VSI queue-mapping information */
11324         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11325         if (ret) {
11326                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11327                         hw->aq.asq_last_status);
11328                 goto out;
11329         }
11330         /* update the local VSI info with updated queue map */
11331         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11332                                         sizeof(vsi->info.tc_mapping));
11333         rte_memcpy(&vsi->info.queue_mapping,
11334                         &ctxt.info.queue_mapping,
11335                 sizeof(vsi->info.queue_mapping));
11336         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11337         vsi->info.valid_sections = 0;
11338
11339         /* query and update current VSI BW information */
11340         ret = i40e_vsi_get_bw_config(vsi);
11341         if (ret) {
11342                 PMD_INIT_LOG(ERR,
11343                          "Failed updating vsi bw info, err %s aq_err %s",
11344                          i40e_stat_str(hw, ret),
11345                          i40e_aq_str(hw, hw->aq.asq_last_status));
11346                 goto out;
11347         }
11348
11349         vsi->enabled_tc = tc_map;
11350
11351 out:
11352         return ret;
11353 }
11354
11355 /*
11356  * i40e_dcb_hw_configure - program the dcb setting to hw
11357  * @pf: pf the configuration is taken on
11358  * @new_cfg: new configuration
11359  * @tc_map: enabled TC bitmap
11360  *
11361  * Returns 0 on success, negative value on failure
11362  */
11363 static enum i40e_status_code
11364 i40e_dcb_hw_configure(struct i40e_pf *pf,
11365                       struct i40e_dcbx_config *new_cfg,
11366                       uint8_t tc_map)
11367 {
11368         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11369         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11370         struct i40e_vsi *main_vsi = pf->main_vsi;
11371         struct i40e_vsi_list *vsi_list;
11372         enum i40e_status_code ret;
11373         int i;
11374         uint32_t val;
11375
11376         /* Use the FW API if FW > v4.4*/
11377         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11378               (hw->aq.fw_maj_ver >= 5))) {
11379                 PMD_INIT_LOG(ERR,
11380                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11381                 return I40E_ERR_FIRMWARE_API_VERSION;
11382         }
11383
11384         /* Check if need reconfiguration */
11385         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11386                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11387                 return I40E_SUCCESS;
11388         }
11389
11390         /* Copy the new config to the current config */
11391         *old_cfg = *new_cfg;
11392         old_cfg->etsrec = old_cfg->etscfg;
11393         ret = i40e_set_dcb_config(hw);
11394         if (ret) {
11395                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11396                          i40e_stat_str(hw, ret),
11397                          i40e_aq_str(hw, hw->aq.asq_last_status));
11398                 return ret;
11399         }
11400         /* set receive Arbiter to RR mode and ETS scheme by default */
11401         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11402                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11403                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11404                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11405                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11406                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11407                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11408                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11409                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11410                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11411                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11412                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11413                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11414         }
11415         /* get local mib to check whether it is configured correctly */
11416         /* IEEE mode */
11417         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11418         /* Get Local DCB Config */
11419         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11420                                      &hw->local_dcbx_config);
11421
11422         /* if Veb is created, need to update TC of it at first */
11423         if (main_vsi->veb) {
11424                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11425                 if (ret)
11426                         PMD_INIT_LOG(WARNING,
11427                                  "Failed configuring TC for VEB seid=%d",
11428                                  main_vsi->veb->seid);
11429         }
11430         /* Update each VSI */
11431         i40e_vsi_config_tc(main_vsi, tc_map);
11432         if (main_vsi->veb) {
11433                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11434                         /* Beside main VSI and VMDQ VSIs, only enable default
11435                          * TC for other VSIs
11436                          */
11437                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11438                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11439                                                          tc_map);
11440                         else
11441                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11442                                                          I40E_DEFAULT_TCMAP);
11443                         if (ret)
11444                                 PMD_INIT_LOG(WARNING,
11445                                         "Failed configuring TC for VSI seid=%d",
11446                                         vsi_list->vsi->seid);
11447                         /* continue */
11448                 }
11449         }
11450         return I40E_SUCCESS;
11451 }
11452
11453 /*
11454  * i40e_dcb_init_configure - initial dcb config
11455  * @dev: device being configured
11456  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11457  *
11458  * Returns 0 on success, negative value on failure
11459  */
11460 int
11461 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11462 {
11463         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11464         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11465         int i, ret = 0;
11466
11467         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11468                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11469                 return -ENOTSUP;
11470         }
11471
11472         /* DCB initialization:
11473          * Update DCB configuration from the Firmware and configure
11474          * LLDP MIB change event.
11475          */
11476         if (sw_dcb == TRUE) {
11477                 if (i40e_need_stop_lldp(dev)) {
11478                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11479                         if (ret != I40E_SUCCESS)
11480                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11481                 }
11482
11483                 ret = i40e_init_dcb(hw);
11484                 /* If lldp agent is stopped, the return value from
11485                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11486                  * adminq status. Otherwise, it should return success.
11487                  */
11488                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11489                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11490                         memset(&hw->local_dcbx_config, 0,
11491                                 sizeof(struct i40e_dcbx_config));
11492                         /* set dcb default configuration */
11493                         hw->local_dcbx_config.etscfg.willing = 0;
11494                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11495                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11496                         hw->local_dcbx_config.etscfg.tsatable[0] =
11497                                                 I40E_IEEE_TSA_ETS;
11498                         /* all UPs mapping to TC0 */
11499                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11500                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11501                         hw->local_dcbx_config.etsrec =
11502                                 hw->local_dcbx_config.etscfg;
11503                         hw->local_dcbx_config.pfc.willing = 0;
11504                         hw->local_dcbx_config.pfc.pfccap =
11505                                                 I40E_MAX_TRAFFIC_CLASS;
11506                         /* FW needs one App to configure HW */
11507                         hw->local_dcbx_config.numapps = 1;
11508                         hw->local_dcbx_config.app[0].selector =
11509                                                 I40E_APP_SEL_ETHTYPE;
11510                         hw->local_dcbx_config.app[0].priority = 3;
11511                         hw->local_dcbx_config.app[0].protocolid =
11512                                                 I40E_APP_PROTOID_FCOE;
11513                         ret = i40e_set_dcb_config(hw);
11514                         if (ret) {
11515                                 PMD_INIT_LOG(ERR,
11516                                         "default dcb config fails. err = %d, aq_err = %d.",
11517                                         ret, hw->aq.asq_last_status);
11518                                 return -ENOSYS;
11519                         }
11520                 } else {
11521                         PMD_INIT_LOG(ERR,
11522                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11523                                 ret, hw->aq.asq_last_status);
11524                         return -ENOTSUP;
11525                 }
11526         } else {
11527                 ret = i40e_aq_start_lldp(hw, NULL);
11528                 if (ret != I40E_SUCCESS)
11529                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11530
11531                 ret = i40e_init_dcb(hw);
11532                 if (!ret) {
11533                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11534                                 PMD_INIT_LOG(ERR,
11535                                         "HW doesn't support DCBX offload.");
11536                                 return -ENOTSUP;
11537                         }
11538                 } else {
11539                         PMD_INIT_LOG(ERR,
11540                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11541                                 ret, hw->aq.asq_last_status);
11542                         return -ENOTSUP;
11543                 }
11544         }
11545         return 0;
11546 }
11547
11548 /*
11549  * i40e_dcb_setup - setup dcb related config
11550  * @dev: device being configured
11551  *
11552  * Returns 0 on success, negative value on failure
11553  */
11554 static int
11555 i40e_dcb_setup(struct rte_eth_dev *dev)
11556 {
11557         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11558         struct i40e_dcbx_config dcb_cfg;
11559         uint8_t tc_map = 0;
11560         int ret = 0;
11561
11562         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11563                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11564                 return -ENOTSUP;
11565         }
11566
11567         if (pf->vf_num != 0)
11568                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11569
11570         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11571         if (ret) {
11572                 PMD_INIT_LOG(ERR, "invalid dcb config");
11573                 return -EINVAL;
11574         }
11575         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11576         if (ret) {
11577                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11578                 return -ENOSYS;
11579         }
11580
11581         return 0;
11582 }
11583
11584 static int
11585 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11586                       struct rte_eth_dcb_info *dcb_info)
11587 {
11588         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11590         struct i40e_vsi *vsi = pf->main_vsi;
11591         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11592         uint16_t bsf, tc_mapping;
11593         int i, j = 0;
11594
11595         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11596                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11597         else
11598                 dcb_info->nb_tcs = 1;
11599         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11600                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11601         for (i = 0; i < dcb_info->nb_tcs; i++)
11602                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11603
11604         /* get queue mapping if vmdq is disabled */
11605         if (!pf->nb_cfg_vmdq_vsi) {
11606                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11607                         if (!(vsi->enabled_tc & (1 << i)))
11608                                 continue;
11609                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11610                         dcb_info->tc_queue.tc_rxq[j][i].base =
11611                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11612                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11613                         dcb_info->tc_queue.tc_txq[j][i].base =
11614                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11615                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11616                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11617                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11618                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11619                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11620                 }
11621                 return 0;
11622         }
11623
11624         /* get queue mapping if vmdq is enabled */
11625         do {
11626                 vsi = pf->vmdq[j].vsi;
11627                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11628                         if (!(vsi->enabled_tc & (1 << i)))
11629                                 continue;
11630                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11631                         dcb_info->tc_queue.tc_rxq[j][i].base =
11632                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11633                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11634                         dcb_info->tc_queue.tc_txq[j][i].base =
11635                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11636                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11637                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11638                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11639                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11640                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11641                 }
11642                 j++;
11643         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11644         return 0;
11645 }
11646
11647 static int
11648 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11649 {
11650         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11651         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11652         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11653         uint16_t msix_intr;
11654
11655         msix_intr = intr_handle->intr_vec[queue_id];
11656         if (msix_intr == I40E_MISC_VEC_ID)
11657                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11658                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11659                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11660                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11661         else
11662                 I40E_WRITE_REG(hw,
11663                                I40E_PFINT_DYN_CTLN(msix_intr -
11664                                                    I40E_RX_VEC_START),
11665                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11666                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11667                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11668
11669         I40E_WRITE_FLUSH(hw);
11670         rte_intr_enable(&pci_dev->intr_handle);
11671
11672         return 0;
11673 }
11674
11675 static int
11676 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11677 {
11678         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11681         uint16_t msix_intr;
11682
11683         msix_intr = intr_handle->intr_vec[queue_id];
11684         if (msix_intr == I40E_MISC_VEC_ID)
11685                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11686                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11687         else
11688                 I40E_WRITE_REG(hw,
11689                                I40E_PFINT_DYN_CTLN(msix_intr -
11690                                                    I40E_RX_VEC_START),
11691                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11692         I40E_WRITE_FLUSH(hw);
11693
11694         return 0;
11695 }
11696
11697 /**
11698  * This function is used to check if the register is valid.
11699  * Below is the valid registers list for X722 only:
11700  * 0x2b800--0x2bb00
11701  * 0x38700--0x38a00
11702  * 0x3d800--0x3db00
11703  * 0x208e00--0x209000
11704  * 0x20be00--0x20c000
11705  * 0x263c00--0x264000
11706  * 0x265c00--0x266000
11707  */
11708 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11709 {
11710         if ((type != I40E_MAC_X722) &&
11711             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11712              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11713              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11714              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11715              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11716              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11717              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11718                 return 0;
11719         else
11720                 return 1;
11721 }
11722
11723 static int i40e_get_regs(struct rte_eth_dev *dev,
11724                          struct rte_dev_reg_info *regs)
11725 {
11726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11727         uint32_t *ptr_data = regs->data;
11728         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11729         const struct i40e_reg_info *reg_info;
11730
11731         if (ptr_data == NULL) {
11732                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11733                 regs->width = sizeof(uint32_t);
11734                 return 0;
11735         }
11736
11737         /* The first few registers have to be read using AQ operations */
11738         reg_idx = 0;
11739         while (i40e_regs_adminq[reg_idx].name) {
11740                 reg_info = &i40e_regs_adminq[reg_idx++];
11741                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11742                         for (arr_idx2 = 0;
11743                                         arr_idx2 <= reg_info->count2;
11744                                         arr_idx2++) {
11745                                 reg_offset = arr_idx * reg_info->stride1 +
11746                                         arr_idx2 * reg_info->stride2;
11747                                 reg_offset += reg_info->base_addr;
11748                                 ptr_data[reg_offset >> 2] =
11749                                         i40e_read_rx_ctl(hw, reg_offset);
11750                         }
11751         }
11752
11753         /* The remaining registers can be read using primitives */
11754         reg_idx = 0;
11755         while (i40e_regs_others[reg_idx].name) {
11756                 reg_info = &i40e_regs_others[reg_idx++];
11757                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11758                         for (arr_idx2 = 0;
11759                                         arr_idx2 <= reg_info->count2;
11760                                         arr_idx2++) {
11761                                 reg_offset = arr_idx * reg_info->stride1 +
11762                                         arr_idx2 * reg_info->stride2;
11763                                 reg_offset += reg_info->base_addr;
11764                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11765                                         ptr_data[reg_offset >> 2] = 0;
11766                                 else
11767                                         ptr_data[reg_offset >> 2] =
11768                                                 I40E_READ_REG(hw, reg_offset);
11769                         }
11770         }
11771
11772         return 0;
11773 }
11774
11775 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11776 {
11777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11778
11779         /* Convert word count to byte count */
11780         return hw->nvm.sr_size << 1;
11781 }
11782
11783 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11784                            struct rte_dev_eeprom_info *eeprom)
11785 {
11786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11787         uint16_t *data = eeprom->data;
11788         uint16_t offset, length, cnt_words;
11789         int ret_code;
11790
11791         offset = eeprom->offset >> 1;
11792         length = eeprom->length >> 1;
11793         cnt_words = length;
11794
11795         if (offset > hw->nvm.sr_size ||
11796                 offset + length > hw->nvm.sr_size) {
11797                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11798                 return -EINVAL;
11799         }
11800
11801         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11802
11803         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11804         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11805                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11806                 return -EIO;
11807         }
11808
11809         return 0;
11810 }
11811
11812 static int i40e_get_module_info(struct rte_eth_dev *dev,
11813                                 struct rte_eth_dev_module_info *modinfo)
11814 {
11815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11816         uint32_t sff8472_comp = 0;
11817         uint32_t sff8472_swap = 0;
11818         uint32_t sff8636_rev = 0;
11819         i40e_status status;
11820         uint32_t type = 0;
11821
11822         /* Check if firmware supports reading module EEPROM. */
11823         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11824                 PMD_DRV_LOG(ERR,
11825                             "Module EEPROM memory read not supported. "
11826                             "Please update the NVM image.\n");
11827                 return -EINVAL;
11828         }
11829
11830         status = i40e_update_link_info(hw);
11831         if (status)
11832                 return -EIO;
11833
11834         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11835                 PMD_DRV_LOG(ERR,
11836                             "Cannot read module EEPROM memory. "
11837                             "No module connected.\n");
11838                 return -EINVAL;
11839         }
11840
11841         type = hw->phy.link_info.module_type[0];
11842
11843         switch (type) {
11844         case I40E_MODULE_TYPE_SFP:
11845                 status = i40e_aq_get_phy_register(hw,
11846                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11847                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11848                                 I40E_MODULE_SFF_8472_COMP,
11849                                 &sff8472_comp, NULL);
11850                 if (status)
11851                         return -EIO;
11852
11853                 status = i40e_aq_get_phy_register(hw,
11854                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11855                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11856                                 I40E_MODULE_SFF_8472_SWAP,
11857                                 &sff8472_swap, NULL);
11858                 if (status)
11859                         return -EIO;
11860
11861                 /* Check if the module requires address swap to access
11862                  * the other EEPROM memory page.
11863                  */
11864                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11865                         PMD_DRV_LOG(WARNING,
11866                                     "Module address swap to access "
11867                                     "page 0xA2 is not supported.\n");
11868                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11869                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11870                 } else if (sff8472_comp == 0x00) {
11871                         /* Module is not SFF-8472 compliant */
11872                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11873                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11874                 } else {
11875                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11876                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11877                 }
11878                 break;
11879         case I40E_MODULE_TYPE_QSFP_PLUS:
11880                 /* Read from memory page 0. */
11881                 status = i40e_aq_get_phy_register(hw,
11882                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11883                                 0, 1,
11884                                 I40E_MODULE_REVISION_ADDR,
11885                                 &sff8636_rev, NULL);
11886                 if (status)
11887                         return -EIO;
11888                 /* Determine revision compliance byte */
11889                 if (sff8636_rev > 0x02) {
11890                         /* Module is SFF-8636 compliant */
11891                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11892                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11893                 } else {
11894                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11895                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11896                 }
11897                 break;
11898         case I40E_MODULE_TYPE_QSFP28:
11899                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11900                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11901                 break;
11902         default:
11903                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11904                 return -EINVAL;
11905         }
11906         return 0;
11907 }
11908
11909 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11910                                   struct rte_dev_eeprom_info *info)
11911 {
11912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11913         bool is_sfp = false;
11914         i40e_status status;
11915         uint8_t *data;
11916         uint32_t value = 0;
11917         uint32_t i;
11918
11919         if (!info || !info->length || !info->data)
11920                 return -EINVAL;
11921
11922         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11923                 is_sfp = true;
11924
11925         data = info->data;
11926         for (i = 0; i < info->length; i++) {
11927                 u32 offset = i + info->offset;
11928                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11929
11930                 /* Check if we need to access the other memory page */
11931                 if (is_sfp) {
11932                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11933                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11934                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11935                         }
11936                 } else {
11937                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11938                                 /* Compute memory page number and offset. */
11939                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11940                                 addr++;
11941                         }
11942                 }
11943                 status = i40e_aq_get_phy_register(hw,
11944                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11945                                 addr, offset, 1, &value, NULL);
11946                 if (status)
11947                         return -EIO;
11948                 data[i] = (uint8_t)value;
11949         }
11950         return 0;
11951 }
11952
11953 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11954                                      struct rte_ether_addr *mac_addr)
11955 {
11956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11958         struct i40e_vsi *vsi = pf->main_vsi;
11959         struct i40e_mac_filter_info mac_filter;
11960         struct i40e_mac_filter *f;
11961         int ret;
11962
11963         if (!is_valid_assigned_ether_addr(mac_addr)) {
11964                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11965                 return -EINVAL;
11966         }
11967
11968         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11969                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11970                         break;
11971         }
11972
11973         if (f == NULL) {
11974                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11975                 return -EIO;
11976         }
11977
11978         mac_filter = f->mac_info;
11979         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11980         if (ret != I40E_SUCCESS) {
11981                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11982                 return -EIO;
11983         }
11984         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11985         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11986         if (ret != I40E_SUCCESS) {
11987                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11988                 return -EIO;
11989         }
11990         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11991
11992         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11993                                         mac_addr->addr_bytes, NULL);
11994         if (ret != I40E_SUCCESS) {
11995                 PMD_DRV_LOG(ERR, "Failed to change mac");
11996                 return -EIO;
11997         }
11998
11999         return 0;
12000 }
12001
12002 static int
12003 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12004 {
12005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12006         struct rte_eth_dev_data *dev_data = pf->dev_data;
12007         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12008         int ret = 0;
12009
12010         /* check if mtu is within the allowed range */
12011         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
12012                 return -EINVAL;
12013
12014         /* mtu setting is forbidden if port is start */
12015         if (dev_data->dev_started) {
12016                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12017                             dev_data->port_id);
12018                 return -EBUSY;
12019         }
12020
12021         if (frame_size > ETHER_MAX_LEN)
12022                 dev_data->dev_conf.rxmode.offloads |=
12023                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12024         else
12025                 dev_data->dev_conf.rxmode.offloads &=
12026                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12027
12028         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12029
12030         return ret;
12031 }
12032
12033 /* Restore ethertype filter */
12034 static void
12035 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12036 {
12037         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12038         struct i40e_ethertype_filter_list
12039                 *ethertype_list = &pf->ethertype.ethertype_list;
12040         struct i40e_ethertype_filter *f;
12041         struct i40e_control_filter_stats stats;
12042         uint16_t flags;
12043
12044         TAILQ_FOREACH(f, ethertype_list, rules) {
12045                 flags = 0;
12046                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12047                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12048                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12049                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12050                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12051
12052                 memset(&stats, 0, sizeof(stats));
12053                 i40e_aq_add_rem_control_packet_filter(hw,
12054                                             f->input.mac_addr.addr_bytes,
12055                                             f->input.ether_type,
12056                                             flags, pf->main_vsi->seid,
12057                                             f->queue, 1, &stats, NULL);
12058         }
12059         PMD_DRV_LOG(INFO, "Ethertype filter:"
12060                     " mac_etype_used = %u, etype_used = %u,"
12061                     " mac_etype_free = %u, etype_free = %u",
12062                     stats.mac_etype_used, stats.etype_used,
12063                     stats.mac_etype_free, stats.etype_free);
12064 }
12065
12066 /* Restore tunnel filter */
12067 static void
12068 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12069 {
12070         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12071         struct i40e_vsi *vsi;
12072         struct i40e_pf_vf *vf;
12073         struct i40e_tunnel_filter_list
12074                 *tunnel_list = &pf->tunnel.tunnel_list;
12075         struct i40e_tunnel_filter *f;
12076         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12077         bool big_buffer = 0;
12078
12079         TAILQ_FOREACH(f, tunnel_list, rules) {
12080                 if (!f->is_to_vf)
12081                         vsi = pf->main_vsi;
12082                 else {
12083                         vf = &pf->vfs[f->vf_id];
12084                         vsi = vf->vsi;
12085                 }
12086                 memset(&cld_filter, 0, sizeof(cld_filter));
12087                 ether_addr_copy((struct rte_ether_addr *)&f->input.outer_mac,
12088                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12089                 ether_addr_copy((struct rte_ether_addr *)&f->input.inner_mac,
12090                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12091                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12092                 cld_filter.element.flags = f->input.flags;
12093                 cld_filter.element.tenant_id = f->input.tenant_id;
12094                 cld_filter.element.queue_number = f->queue;
12095                 rte_memcpy(cld_filter.general_fields,
12096                            f->input.general_fields,
12097                            sizeof(f->input.general_fields));
12098
12099                 if (((f->input.flags &
12100                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12101                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12102                     ((f->input.flags &
12103                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12104                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12105                     ((f->input.flags &
12106                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12107                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12108                         big_buffer = 1;
12109
12110                 if (big_buffer)
12111                         i40e_aq_add_cloud_filters_bb(hw,
12112                                         vsi->seid, &cld_filter, 1);
12113                 else
12114                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12115                                                   &cld_filter.element, 1);
12116         }
12117 }
12118
12119 /* Restore rss filter */
12120 static inline void
12121 i40e_rss_filter_restore(struct i40e_pf *pf)
12122 {
12123         struct i40e_rte_flow_rss_conf *conf =
12124                                         &pf->rss_info;
12125         if (conf->conf.queue_num)
12126                 i40e_config_rss_filter(pf, conf, TRUE);
12127 }
12128
12129 static void
12130 i40e_filter_restore(struct i40e_pf *pf)
12131 {
12132         i40e_ethertype_filter_restore(pf);
12133         i40e_tunnel_filter_restore(pf);
12134         i40e_fdir_filter_restore(pf);
12135         i40e_rss_filter_restore(pf);
12136 }
12137
12138 static bool
12139 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12140 {
12141         if (strcmp(dev->device->driver->name, drv->driver.name))
12142                 return false;
12143
12144         return true;
12145 }
12146
12147 bool
12148 is_i40e_supported(struct rte_eth_dev *dev)
12149 {
12150         return is_device_supported(dev, &rte_i40e_pmd);
12151 }
12152
12153 struct i40e_customized_pctype*
12154 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12155 {
12156         int i;
12157
12158         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12159                 if (pf->customized_pctype[i].index == index)
12160                         return &pf->customized_pctype[i];
12161         }
12162         return NULL;
12163 }
12164
12165 static int
12166 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12167                               uint32_t pkg_size, uint32_t proto_num,
12168                               struct rte_pmd_i40e_proto_info *proto,
12169                               enum rte_pmd_i40e_package_op op)
12170 {
12171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12172         uint32_t pctype_num;
12173         struct rte_pmd_i40e_ptype_info *pctype;
12174         uint32_t buff_size;
12175         struct i40e_customized_pctype *new_pctype = NULL;
12176         uint8_t proto_id;
12177         uint8_t pctype_value;
12178         char name[64];
12179         uint32_t i, j, n;
12180         int ret;
12181
12182         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12183             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12184                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12185                 return -1;
12186         }
12187
12188         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12189                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12190                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12191         if (ret) {
12192                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12193                 return -1;
12194         }
12195         if (!pctype_num) {
12196                 PMD_DRV_LOG(INFO, "No new pctype added");
12197                 return -1;
12198         }
12199
12200         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12201         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12202         if (!pctype) {
12203                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12204                 return -1;
12205         }
12206         /* get information about new pctype list */
12207         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12208                                         (uint8_t *)pctype, buff_size,
12209                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12210         if (ret) {
12211                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12212                 rte_free(pctype);
12213                 return -1;
12214         }
12215
12216         /* Update customized pctype. */
12217         for (i = 0; i < pctype_num; i++) {
12218                 pctype_value = pctype[i].ptype_id;
12219                 memset(name, 0, sizeof(name));
12220                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12221                         proto_id = pctype[i].protocols[j];
12222                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12223                                 continue;
12224                         for (n = 0; n < proto_num; n++) {
12225                                 if (proto[n].proto_id != proto_id)
12226                                         continue;
12227                                 strlcat(name, proto[n].name, sizeof(name));
12228                                 strlcat(name, "_", sizeof(name));
12229                                 break;
12230                         }
12231                 }
12232                 name[strlen(name) - 1] = '\0';
12233                 if (!strcmp(name, "GTPC"))
12234                         new_pctype =
12235                                 i40e_find_customized_pctype(pf,
12236                                                       I40E_CUSTOMIZED_GTPC);
12237                 else if (!strcmp(name, "GTPU_IPV4"))
12238                         new_pctype =
12239                                 i40e_find_customized_pctype(pf,
12240                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12241                 else if (!strcmp(name, "GTPU_IPV6"))
12242                         new_pctype =
12243                                 i40e_find_customized_pctype(pf,
12244                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12245                 else if (!strcmp(name, "GTPU"))
12246                         new_pctype =
12247                                 i40e_find_customized_pctype(pf,
12248                                                       I40E_CUSTOMIZED_GTPU);
12249                 if (new_pctype) {
12250                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12251                                 new_pctype->pctype = pctype_value;
12252                                 new_pctype->valid = true;
12253                         } else {
12254                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12255                                 new_pctype->valid = false;
12256                         }
12257                 }
12258         }
12259
12260         rte_free(pctype);
12261         return 0;
12262 }
12263
12264 static int
12265 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12266                              uint32_t pkg_size, uint32_t proto_num,
12267                              struct rte_pmd_i40e_proto_info *proto,
12268                              enum rte_pmd_i40e_package_op op)
12269 {
12270         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12271         uint16_t port_id = dev->data->port_id;
12272         uint32_t ptype_num;
12273         struct rte_pmd_i40e_ptype_info *ptype;
12274         uint32_t buff_size;
12275         uint8_t proto_id;
12276         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12277         uint32_t i, j, n;
12278         bool in_tunnel;
12279         int ret;
12280
12281         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12282             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12283                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12284                 return -1;
12285         }
12286
12287         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12288                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12289                 return 0;
12290         }
12291
12292         /* get information about new ptype num */
12293         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12294                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12295                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12296         if (ret) {
12297                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12298                 return ret;
12299         }
12300         if (!ptype_num) {
12301                 PMD_DRV_LOG(INFO, "No new ptype added");
12302                 return -1;
12303         }
12304
12305         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12306         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12307         if (!ptype) {
12308                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12309                 return -1;
12310         }
12311
12312         /* get information about new ptype list */
12313         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12314                                         (uint8_t *)ptype, buff_size,
12315                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12316         if (ret) {
12317                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12318                 rte_free(ptype);
12319                 return ret;
12320         }
12321
12322         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12323         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12324         if (!ptype_mapping) {
12325                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12326                 rte_free(ptype);
12327                 return -1;
12328         }
12329
12330         /* Update ptype mapping table. */
12331         for (i = 0; i < ptype_num; i++) {
12332                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12333                 ptype_mapping[i].sw_ptype = 0;
12334                 in_tunnel = false;
12335                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12336                         proto_id = ptype[i].protocols[j];
12337                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12338                                 continue;
12339                         for (n = 0; n < proto_num; n++) {
12340                                 if (proto[n].proto_id != proto_id)
12341                                         continue;
12342                                 memset(name, 0, sizeof(name));
12343                                 strcpy(name, proto[n].name);
12344                                 if (!strncasecmp(name, "PPPOE", 5))
12345                                         ptype_mapping[i].sw_ptype |=
12346                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12347                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12348                                          !in_tunnel) {
12349                                         ptype_mapping[i].sw_ptype |=
12350                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12351                                         ptype_mapping[i].sw_ptype |=
12352                                                 RTE_PTYPE_L4_FRAG;
12353                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12354                                            in_tunnel) {
12355                                         ptype_mapping[i].sw_ptype |=
12356                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12357                                         ptype_mapping[i].sw_ptype |=
12358                                                 RTE_PTYPE_INNER_L4_FRAG;
12359                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12360                                         ptype_mapping[i].sw_ptype |=
12361                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12362                                         in_tunnel = true;
12363                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12364                                            !in_tunnel)
12365                                         ptype_mapping[i].sw_ptype |=
12366                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12367                                 else if (!strncasecmp(name, "IPV4", 4) &&
12368                                          in_tunnel)
12369                                         ptype_mapping[i].sw_ptype |=
12370                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12371                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12372                                          !in_tunnel) {
12373                                         ptype_mapping[i].sw_ptype |=
12374                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12375                                         ptype_mapping[i].sw_ptype |=
12376                                                 RTE_PTYPE_L4_FRAG;
12377                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12378                                            in_tunnel) {
12379                                         ptype_mapping[i].sw_ptype |=
12380                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12381                                         ptype_mapping[i].sw_ptype |=
12382                                                 RTE_PTYPE_INNER_L4_FRAG;
12383                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12384                                         ptype_mapping[i].sw_ptype |=
12385                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12386                                         in_tunnel = true;
12387                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12388                                            !in_tunnel)
12389                                         ptype_mapping[i].sw_ptype |=
12390                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12391                                 else if (!strncasecmp(name, "IPV6", 4) &&
12392                                          in_tunnel)
12393                                         ptype_mapping[i].sw_ptype |=
12394                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12395                                 else if (!strncasecmp(name, "UDP", 3) &&
12396                                          !in_tunnel)
12397                                         ptype_mapping[i].sw_ptype |=
12398                                                 RTE_PTYPE_L4_UDP;
12399                                 else if (!strncasecmp(name, "UDP", 3) &&
12400                                          in_tunnel)
12401                                         ptype_mapping[i].sw_ptype |=
12402                                                 RTE_PTYPE_INNER_L4_UDP;
12403                                 else if (!strncasecmp(name, "TCP", 3) &&
12404                                          !in_tunnel)
12405                                         ptype_mapping[i].sw_ptype |=
12406                                                 RTE_PTYPE_L4_TCP;
12407                                 else if (!strncasecmp(name, "TCP", 3) &&
12408                                          in_tunnel)
12409                                         ptype_mapping[i].sw_ptype |=
12410                                                 RTE_PTYPE_INNER_L4_TCP;
12411                                 else if (!strncasecmp(name, "SCTP", 4) &&
12412                                          !in_tunnel)
12413                                         ptype_mapping[i].sw_ptype |=
12414                                                 RTE_PTYPE_L4_SCTP;
12415                                 else if (!strncasecmp(name, "SCTP", 4) &&
12416                                          in_tunnel)
12417                                         ptype_mapping[i].sw_ptype |=
12418                                                 RTE_PTYPE_INNER_L4_SCTP;
12419                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12420                                           !strncasecmp(name, "ICMPV6", 6)) &&
12421                                          !in_tunnel)
12422                                         ptype_mapping[i].sw_ptype |=
12423                                                 RTE_PTYPE_L4_ICMP;
12424                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12425                                           !strncasecmp(name, "ICMPV6", 6)) &&
12426                                          in_tunnel)
12427                                         ptype_mapping[i].sw_ptype |=
12428                                                 RTE_PTYPE_INNER_L4_ICMP;
12429                                 else if (!strncasecmp(name, "GTPC", 4)) {
12430                                         ptype_mapping[i].sw_ptype |=
12431                                                 RTE_PTYPE_TUNNEL_GTPC;
12432                                         in_tunnel = true;
12433                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12434                                         ptype_mapping[i].sw_ptype |=
12435                                                 RTE_PTYPE_TUNNEL_GTPU;
12436                                         in_tunnel = true;
12437                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12438                                         ptype_mapping[i].sw_ptype |=
12439                                                 RTE_PTYPE_TUNNEL_GRENAT;
12440                                         in_tunnel = true;
12441                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12442                                            !strncasecmp(name, "L2TPV2", 6)) {
12443                                         ptype_mapping[i].sw_ptype |=
12444                                                 RTE_PTYPE_TUNNEL_L2TP;
12445                                         in_tunnel = true;
12446                                 }
12447
12448                                 break;
12449                         }
12450                 }
12451         }
12452
12453         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12454                                                 ptype_num, 0);
12455         if (ret)
12456                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12457
12458         rte_free(ptype_mapping);
12459         rte_free(ptype);
12460         return ret;
12461 }
12462
12463 void
12464 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12465                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12466 {
12467         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12468         uint32_t proto_num;
12469         struct rte_pmd_i40e_proto_info *proto;
12470         uint32_t buff_size;
12471         uint32_t i;
12472         int ret;
12473
12474         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12475             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12476                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12477                 return;
12478         }
12479
12480         /* get information about protocol number */
12481         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12482                                        (uint8_t *)&proto_num, sizeof(proto_num),
12483                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12484         if (ret) {
12485                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12486                 return;
12487         }
12488         if (!proto_num) {
12489                 PMD_DRV_LOG(INFO, "No new protocol added");
12490                 return;
12491         }
12492
12493         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12494         proto = rte_zmalloc("new_proto", buff_size, 0);
12495         if (!proto) {
12496                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12497                 return;
12498         }
12499
12500         /* get information about protocol list */
12501         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12502                                         (uint8_t *)proto, buff_size,
12503                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12504         if (ret) {
12505                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12506                 rte_free(proto);
12507                 return;
12508         }
12509
12510         /* Check if GTP is supported. */
12511         for (i = 0; i < proto_num; i++) {
12512                 if (!strncmp(proto[i].name, "GTP", 3)) {
12513                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12514                                 pf->gtp_support = true;
12515                         else
12516                                 pf->gtp_support = false;
12517                         break;
12518                 }
12519         }
12520
12521         /* Update customized pctype info */
12522         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12523                                             proto_num, proto, op);
12524         if (ret)
12525                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12526
12527         /* Update customized ptype info */
12528         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12529                                            proto_num, proto, op);
12530         if (ret)
12531                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12532
12533         rte_free(proto);
12534 }
12535
12536 /* Create a QinQ cloud filter
12537  *
12538  * The Fortville NIC has limited resources for tunnel filters,
12539  * so we can only reuse existing filters.
12540  *
12541  * In step 1 we define which Field Vector fields can be used for
12542  * filter types.
12543  * As we do not have the inner tag defined as a field,
12544  * we have to define it first, by reusing one of L1 entries.
12545  *
12546  * In step 2 we are replacing one of existing filter types with
12547  * a new one for QinQ.
12548  * As we reusing L1 and replacing L2, some of the default filter
12549  * types will disappear,which depends on L1 and L2 entries we reuse.
12550  *
12551  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12552  *
12553  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12554  *              later when we define the cloud filter.
12555  *      a.      Valid_flags.replace_cloud = 0
12556  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12557  *      c.      New_filter = 0x10
12558  *      d.      TR bit = 0xff (optional, not used here)
12559  *      e.      Buffer – 2 entries:
12560  *              i.      Byte 0 = 8 (outer vlan FV index).
12561  *                      Byte 1 = 0 (rsv)
12562  *                      Byte 2-3 = 0x0fff
12563  *              ii.     Byte 0 = 37 (inner vlan FV index).
12564  *                      Byte 1 =0 (rsv)
12565  *                      Byte 2-3 = 0x0fff
12566  *
12567  * Step 2:
12568  * 2.   Create cloud filter using two L1 filters entries: stag and
12569  *              new filter(outer vlan+ inner vlan)
12570  *      a.      Valid_flags.replace_cloud = 1
12571  *      b.      Old_filter = 1 (instead of outer IP)
12572  *      c.      New_filter = 0x10
12573  *      d.      Buffer – 2 entries:
12574  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12575  *                      Byte 1-3 = 0 (rsv)
12576  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12577  *                      Byte 9-11 = 0 (rsv)
12578  */
12579 static int
12580 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12581 {
12582         int ret = -ENOTSUP;
12583         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12584         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12585         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12586         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12587
12588         if (pf->support_multi_driver) {
12589                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12590                 return ret;
12591         }
12592
12593         /* Init */
12594         memset(&filter_replace, 0,
12595                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12596         memset(&filter_replace_buf, 0,
12597                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12598
12599         /* create L1 filter */
12600         filter_replace.old_filter_type =
12601                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12602         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12603         filter_replace.tr_bit = 0;
12604
12605         /* Prepare the buffer, 2 entries */
12606         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12607         filter_replace_buf.data[0] |=
12608                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12609         /* Field Vector 12b mask */
12610         filter_replace_buf.data[2] = 0xff;
12611         filter_replace_buf.data[3] = 0x0f;
12612         filter_replace_buf.data[4] =
12613                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12614         filter_replace_buf.data[4] |=
12615                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12616         /* Field Vector 12b mask */
12617         filter_replace_buf.data[6] = 0xff;
12618         filter_replace_buf.data[7] = 0x0f;
12619         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12620                         &filter_replace_buf);
12621         if (ret != I40E_SUCCESS)
12622                 return ret;
12623
12624         if (filter_replace.old_filter_type !=
12625             filter_replace.new_filter_type)
12626                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12627                             " original: 0x%x, new: 0x%x",
12628                             dev->device->name,
12629                             filter_replace.old_filter_type,
12630                             filter_replace.new_filter_type);
12631
12632         /* Apply the second L2 cloud filter */
12633         memset(&filter_replace, 0,
12634                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12635         memset(&filter_replace_buf, 0,
12636                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12637
12638         /* create L2 filter, input for L2 filter will be L1 filter  */
12639         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12640         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12641         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12642
12643         /* Prepare the buffer, 2 entries */
12644         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12645         filter_replace_buf.data[0] |=
12646                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12647         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12648         filter_replace_buf.data[4] |=
12649                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12650         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12651                         &filter_replace_buf);
12652         if (!ret && (filter_replace.old_filter_type !=
12653                      filter_replace.new_filter_type))
12654                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12655                             " original: 0x%x, new: 0x%x",
12656                             dev->device->name,
12657                             filter_replace.old_filter_type,
12658                             filter_replace.new_filter_type);
12659
12660         return ret;
12661 }
12662
12663 int
12664 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12665                    const struct rte_flow_action_rss *in)
12666 {
12667         if (in->key_len > RTE_DIM(out->key) ||
12668             in->queue_num > RTE_DIM(out->queue))
12669                 return -EINVAL;
12670         if (!in->key && in->key_len)
12671                 return -EINVAL;
12672         out->conf = (struct rte_flow_action_rss){
12673                 .func = in->func,
12674                 .level = in->level,
12675                 .types = in->types,
12676                 .key_len = in->key_len,
12677                 .queue_num = in->queue_num,
12678                 .queue = memcpy(out->queue, in->queue,
12679                                 sizeof(*in->queue) * in->queue_num),
12680         };
12681         if (in->key)
12682                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12683         return 0;
12684 }
12685
12686 int
12687 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12688                      const struct rte_flow_action_rss *with)
12689 {
12690         return (comp->func == with->func &&
12691                 comp->level == with->level &&
12692                 comp->types == with->types &&
12693                 comp->key_len == with->key_len &&
12694                 comp->queue_num == with->queue_num &&
12695                 !memcmp(comp->key, with->key, with->key_len) &&
12696                 !memcmp(comp->queue, with->queue,
12697                         sizeof(*with->queue) * with->queue_num));
12698 }
12699
12700 int
12701 i40e_config_rss_filter(struct i40e_pf *pf,
12702                 struct i40e_rte_flow_rss_conf *conf, bool add)
12703 {
12704         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12705         uint32_t i, lut = 0;
12706         uint16_t j, num;
12707         struct rte_eth_rss_conf rss_conf = {
12708                 .rss_key = conf->conf.key_len ?
12709                         (void *)(uintptr_t)conf->conf.key : NULL,
12710                 .rss_key_len = conf->conf.key_len,
12711                 .rss_hf = conf->conf.types,
12712         };
12713         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12714
12715         if (!add) {
12716                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12717                         i40e_pf_disable_rss(pf);
12718                         memset(rss_info, 0,
12719                                 sizeof(struct i40e_rte_flow_rss_conf));
12720                         return 0;
12721                 }
12722                 return -EINVAL;
12723         }
12724
12725         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12726          * It's necessary to calculate the actual PF queues that are configured.
12727          */
12728         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12729                 num = i40e_pf_calc_configured_queues_num(pf);
12730         else
12731                 num = pf->dev_data->nb_rx_queues;
12732
12733         num = RTE_MIN(num, conf->conf.queue_num);
12734         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12735                         num);
12736
12737         if (num == 0) {
12738                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12739                 return -ENOTSUP;
12740         }
12741
12742         /* Fill in redirection table */
12743         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12744                 if (j == num)
12745                         j = 0;
12746                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12747                         hw->func_caps.rss_table_entry_width) - 1));
12748                 if ((i & 3) == 3)
12749                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12750         }
12751
12752         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12753                 i40e_pf_disable_rss(pf);
12754                 return 0;
12755         }
12756         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12757                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12758                 /* Random default keys */
12759                 static uint32_t rss_key_default[] = {0x6b793944,
12760                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12761                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12762                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12763
12764                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12765                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12766                                                         sizeof(uint32_t);
12767                 PMD_DRV_LOG(INFO,
12768                         "No valid RSS key config for i40e, using default\n");
12769         }
12770
12771         i40e_hw_rss_hash_set(pf, &rss_conf);
12772
12773         if (i40e_rss_conf_init(rss_info, &conf->conf))
12774                 return -EINVAL;
12775
12776         return 0;
12777 }
12778
12779 RTE_INIT(i40e_init_log)
12780 {
12781         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12782         if (i40e_logtype_init >= 0)
12783                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12784         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12785         if (i40e_logtype_driver >= 0)
12786                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12787 }
12788
12789 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12790                               ETH_I40E_FLOATING_VEB_ARG "=1"
12791                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12792                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12793                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12794                               ETH_I40E_USE_LATEST_VEC "=0|1");