drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518         .tm_ops_get                   = i40e_tm_ops_get,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         unsigned offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 535         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 536         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 537         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 538 };
 539
 540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 541                 sizeof(rte_i40e_stats_strings[0]))
 542
 543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 544         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 545                 tx_dropped_link_down)},
 546         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 547         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 548                 illegal_bytes)},
 549         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 550         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_local_faults)},
 552         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_remote_faults)},
 554         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_length_errors)},
 556         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 557         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 558         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 559         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 560         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 561         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_127)},
 563         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_255)},
 565         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_511)},
 567         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1023)},
 569         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1522)},
 571         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_big)},
 573         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_undersize)},
 575         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_oversize)},
 577         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 578                 mac_short_packet_dropped)},
 579         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_fragments)},
 581         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 582         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 583         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_127)},
 585         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_255)},
 587         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_511)},
 589         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1023)},
 591         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1522)},
 593         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_big)},
 595         {"rx_flow_director_atr_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 597         {"rx_flow_director_sb_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 599         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_status)},
 601         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_status)},
 603         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_count)},
 605         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_count)},
 607 };
 608
 609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 610                 sizeof(rte_i40e_hw_port_strings[0]))
 611
 612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 613         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xon_rx)},
 615         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xoff_rx)},
 617 };
 618
 619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 620                 sizeof(rte_i40e_rxq_prio_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_tx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_tx)},
 627         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_2_xoff)},
 629 };
 630
 631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 632                 sizeof(rte_i40e_txq_prio_strings[0]))
 633
 634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         return rte_eth_dev_pci_generic_probe(pci_dev,
 638                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 639 }
 640
 641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 642 {
 643         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 644 }
 645
 646 static struct rte_pci_driver rte_i40e_pmd = {
 647         .id_table = pci_id_i40e_map,
 648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 649         .probe = eth_i40e_pci_probe,
 650         .remove = eth_i40e_pci_remove,
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691 #ifndef I40E_GLQF_L3_MAP
 692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 693 #endif
 694
 695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 696 {
 697         /*
 698          * Initialize registers for flexible payload, which should be set by NVM.
 699          * This should be removed from code once it is fixed in NVM.
 700          */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 712         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 713
 714         /* Initialize registers for parsing packet type of QinQ */
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 717 }
 718
 719 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 720
 721 /*
 722  * Add a ethertype filter to drop all flow control frames transmitted
 723  * from VSIs.
 724 */
 725 static void
 726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 727 {
 728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 729         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 731                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 732         int ret;
 733
 734         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 735                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 736                                 pf->main_vsi_seid, 0,
 737                                 TRUE, NULL, NULL);
 738         if (ret)
 739                 PMD_INIT_LOG(ERR,
 740                         "Failed to add filter to drop flow control frames from VSIs.");
 741 }
 742
 743 static int
 744 floating_veb_list_handler(__rte_unused const char *key,
 745                           const char *floating_veb_value,
 746                           void *opaque)
 747 {
 748         int idx = 0;
 749         unsigned int count = 0;
 750         char *end = NULL;
 751         int min, max;
 752         bool *vf_floating_veb = opaque;
 753
 754         while (isblank(*floating_veb_value))
 755                 floating_veb_value++;
 756
 757         /* Reset floating VEB configuration for VFs */
 758         for (idx = 0; idx < I40E_MAX_VF; idx++)
 759                 vf_floating_veb[idx] = false;
 760
 761         min = I40E_MAX_VF;
 762         do {
 763                 while (isblank(*floating_veb_value))
 764                         floating_veb_value++;
 765                 if (*floating_veb_value == '\0')
 766                         return -1;
 767                 errno = 0;
 768                 idx = strtoul(floating_veb_value, &end, 10);
 769                 if (errno || end == NULL)
 770                         return -1;
 771                 while (isblank(*end))
 772                         end++;
 773                 if (*end == '-') {
 774                         min = idx;
 775                 } else if ((*end == ';') || (*end == '\0')) {
 776                         max = idx;
 777                         if (min == I40E_MAX_VF)
 778                                 min = idx;
 779                         if (max >= I40E_MAX_VF)
 780                                 max = I40E_MAX_VF - 1;
 781                         for (idx = min; idx <= max; idx++) {
 782                                 vf_floating_veb[idx] = true;
 783                                 count++;
 784                         }
 785                         min = I40E_MAX_VF;
 786                 } else {
 787                         return -1;
 788                 }
 789                 floating_veb_value = end + 1;
 790         } while (*end != '\0');
 791
 792         if (count == 0)
 793                 return -1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 config_vf_floating_veb(struct rte_devargs *devargs,
 800                        uint16_t floating_veb,
 801                        bool *vf_floating_veb)
 802 {
 803         struct rte_kvargs *kvlist;
 804         int i;
 805         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 806
 807         if (!floating_veb)
 808                 return;
 809         /* All the VFs attach to the floating VEB by default
 810          * when the floating VEB is enabled.
 811          */
 812         for (i = 0; i < I40E_MAX_VF; i++)
 813                 vf_floating_veb[i] = true;
 814
 815         if (devargs == NULL)
 816                 return;
 817
 818         kvlist = rte_kvargs_parse(devargs->args, NULL);
 819         if (kvlist == NULL)
 820                 return;
 821
 822         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 823                 rte_kvargs_free(kvlist);
 824                 return;
 825         }
 826         /* When the floating_veb_list parameter exists, all the VFs
 827          * will attach to the legacy VEB firstly, then configure VFs
 828          * to the floating VEB according to the floating_veb_list.
 829          */
 830         if (rte_kvargs_process(kvlist, floating_veb_list,
 831                                floating_veb_list_handler,
 832                                vf_floating_veb) < 0) {
 833                 rte_kvargs_free(kvlist);
 834                 return;
 835         }
 836         rte_kvargs_free(kvlist);
 837 }
 838
 839 static int
 840 i40e_check_floating_handler(__rte_unused const char *key,
 841                             const char *value,
 842                             __rte_unused void *opaque)
 843 {
 844         if (strcmp(value, "1"))
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static int
 851 is_floating_veb_supported(struct rte_devargs *devargs)
 852 {
 853         struct rte_kvargs *kvlist;
 854         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 855
 856         if (devargs == NULL)
 857                 return 0;
 858
 859         kvlist = rte_kvargs_parse(devargs->args, NULL);
 860         if (kvlist == NULL)
 861                 return 0;
 862
 863         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         /* Floating VEB is enabled when there's key-value:
 868          * enable_floating_veb=1
 869          */
 870         if (rte_kvargs_process(kvlist, floating_veb_key,
 871                                i40e_check_floating_handler, NULL) < 0) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         rte_kvargs_free(kvlist);
 876
 877         return 1;
 878 }
 879
 880 static void
 881 config_floating_veb(struct rte_eth_dev *dev)
 882 {
 883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886
 887         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 888
 889         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 890                 pf->floating_veb =
 891                         is_floating_veb_supported(pci_dev->device.devargs);
 892                 config_vf_floating_veb(pci_dev->device.devargs,
 893                                        pf->floating_veb,
 894                                        pf->floating_veb_list);
 895         } else {
 896                 pf->floating_veb = false;
 897         }
 898 }
 899
 900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 902
 903 static int
 904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 908         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 909         int ret;
 910
 911         struct rte_hash_parameters ethertype_hash_params = {
 912                 .name = ethertype_hash_name,
 913                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 914                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 915                 .hash_func = rte_hash_crc,
 916                 .hash_func_init_val = 0,
 917                 .socket_id = rte_socket_id(),
 918         };
 919
 920         /* Initialize ethertype filter rule list and hash */
 921         TAILQ_INIT(&ethertype_rule->ethertype_list);
 922         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 923                  "ethertype_%s", dev->device->name);
 924         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 925         if (!ethertype_rule->hash_table) {
 926                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 927                 return -EINVAL;
 928         }
 929         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 930                                        sizeof(struct i40e_ethertype_filter *) *
 931                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 932                                        0);
 933         if (!ethertype_rule->hash_map) {
 934                 PMD_INIT_LOG(ERR,
 935                              "Failed to allocate memory for ethertype hash map!");
 936                 ret = -ENOMEM;
 937                 goto err_ethertype_hash_map_alloc;
 938         }
 939
 940         return 0;
 941
 942 err_ethertype_hash_map_alloc:
 943         rte_hash_free(ethertype_rule->hash_table);
 944
 945         return ret;
 946 }
 947
 948 static int
 949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 953         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters tunnel_hash_params = {
 957                 .name = tunnel_hash_name,
 958                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize tunnel filter rule list and hash */
 966         TAILQ_INIT(&tunnel_rule->tunnel_list);
 967         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 968                  "tunnel_%s", dev->device->name);
 969         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 970         if (!tunnel_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 972                 return -EINVAL;
 973         }
 974         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 975                                     sizeof(struct i40e_tunnel_filter *) *
 976                                     I40E_MAX_TUNNEL_FILTER_NUM,
 977                                     0);
 978         if (!tunnel_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for tunnel hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_tunnel_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_tunnel_hash_map_alloc:
 988         rte_hash_free(tunnel_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_fdir_info *fdir_info = &pf->fdir;
 998         char fdir_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters fdir_hash_params = {
1002                 .name = fdir_hash_name,
1003                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004                 .key_len = sizeof(struct rte_eth_fdir_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize flow director filter rule list and hash */
1011         TAILQ_INIT(&fdir_info->fdir_list);
1012         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013                  "fdir_%s", dev->device->name);
1014         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015         if (!fdir_info->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1017                 return -EINVAL;
1018         }
1019         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020                                           sizeof(struct i40e_fdir_filter *) *
1021                                           I40E_MAX_FDIR_FILTER_NUM,
1022                                           0);
1023         if (!fdir_info->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for fdir hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_fdir_hash_map_alloc;
1028         }
1029         return 0;
1030
1031 err_fdir_hash_map_alloc:
1032         rte_hash_free(fdir_info->hash_table);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 {
1040         struct rte_pci_device *pci_dev;
1041         struct rte_intr_handle *intr_handle;
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         struct i40e_vsi *vsi;
1045         int ret;
1046         uint32_t len;
1047         uint8_t aq_fail = 0;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         dev->dev_ops = &i40e_eth_dev_ops;
1052         dev->rx_pkt_burst = i40e_recv_pkts;
1053         dev->tx_pkt_burst = i40e_xmit_pkts;
1054         dev->tx_pkt_prepare = i40e_prep_pkts;
1055
1056         /* for secondary processes, we don't initialise any further as primary
1057          * has already done this work. Only check we don't need a different
1058          * RX function */
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060                 i40e_set_rx_function(dev);
1061                 i40e_set_tx_function(dev);
1062                 return 0;
1063         }
1064         i40e_set_default_ptype_table(dev);
1065         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         intr_handle = &pci_dev->intr_handle;
1067
1068         rte_eth_copy_pci_info(dev, pci_dev);
1069         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070
1071         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         pf->adapter->eth_dev = dev;
1073         pf->dev_data = dev->data;
1074
1075         hw->back = I40E_PF_TO_ADAPTER(pf);
1076         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1077         if (!hw->hw_addr) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Hardware is not available, as address is NULL");
1080                 return -ENODEV;
1081         }
1082
1083         hw->vendor_id = pci_dev->id.vendor_id;
1084         hw->device_id = pci_dev->id.device_id;
1085         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087         hw->bus.device = pci_dev->addr.devid;
1088         hw->bus.func = pci_dev->addr.function;
1089         hw->adapter_stopped = 0;
1090
1091         /* Make sure all is clean before doing PF reset */
1092         i40e_clear_hw(hw);
1093
1094         /* Initialize the hardware */
1095         i40e_hw_init(dev);
1096
1097         /* Reset here to make sure all is clean for each PF */
1098         ret = i40e_pf_reset(hw);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1101                 return ret;
1102         }
1103
1104         /* Initialize the shared code (base driver) */
1105         ret = i40e_init_shared_code(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108                 return ret;
1109         }
1110
1111         /*
1112          * To work around the NVM issue, initialize registers
1113          * for flexible payload and packet type of QinQ by
1114          * software. It should be removed once issues are fixed
1115          * in NVM.
1116          */
1117         i40e_GLQF_reg_init(hw);
1118
1119         /* Initialize the input set for filters (hash and fd) to default value */
1120         i40e_filter_input_set_init(pf);
1121
1122         /* Initialize the parameters for adminq */
1123         i40e_init_adminq_parameter(hw);
1124         ret = i40e_init_adminq(hw);
1125         if (ret != I40E_SUCCESS) {
1126                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1127                 return -EIO;
1128         }
1129         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132                      ((hw->nvm.version >> 12) & 0xf),
1133                      ((hw->nvm.version >> 4) & 0xff),
1134                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135
1136         /* initialise the L3_MAP register */
1137         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1138                                    0x00000028,  NULL);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141
1142         /* Need the special FW version to support floating VEB */
1143         config_floating_veb(dev);
1144         /* Clear PXE mode */
1145         i40e_clear_pxe_mode(hw);
1146         i40e_dev_sync_phy_type(hw);
1147
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         /* initialize Traffic Manager configuration */
1300         i40e_tm_conf_init(dev);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         return 0;
1313
1314 err_init_fdir_filter_list:
1315         rte_free(pf->tunnel.hash_table);
1316         rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318         rte_free(pf->ethertype.hash_table);
1319         rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321         rte_free(dev->data->mac_addrs);
1322 err_mac_alloc:
1323         i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1325 err_get_mac_addr:
1326 err_configure_lan_hmc:
1327         (void)i40e_shutdown_lan_hmc(hw);
1328 err_init_lan_hmc:
1329         i40e_res_pool_destroy(&pf->msix_pool);
1330 err_msix_pool_init:
1331         i40e_res_pool_destroy(&pf->qp_pool);
1332 err_qp_pool_init:
1333 err_parameter_init:
1334 err_get_capabilities:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         /* Remove all Traffic Manager configuration */
1465         i40e_tm_conf_uninit(dev);
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1472 {
1473         struct i40e_adapter *ad =
1474                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1478         int i, ret;
1479
1480         ret = i40e_dev_sync_phy_type(hw);
1481         if (ret)
1482                 return ret;
1483
1484         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485          * bulk allocation or vector Rx preconditions we will reset it.
1486          */
1487         ad->rx_bulk_alloc_allowed = true;
1488         ad->rx_vec_allowed = true;
1489         ad->tx_simple_allowed = true;
1490         ad->tx_vec_allowed = true;
1491
1492         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493                 ret = i40e_fdir_setup(pf);
1494                 if (ret != I40E_SUCCESS) {
1495                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1496                         return -ENOTSUP;
1497                 }
1498                 ret = i40e_fdir_configure(dev);
1499                 if (ret < 0) {
1500                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501                         goto err;
1502                 }
1503         } else
1504                 i40e_fdir_teardown(pf);
1505
1506         ret = i40e_dev_init_vlan(dev);
1507         if (ret < 0)
1508                 goto err;
1509
1510         /* VMDQ setup.
1511          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512          *  RSS setting have different requirements.
1513          *  General PMD driver call sequence are NIC init, configure,
1514          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1516          *  applicable. So, VMDQ setting has to be done before
1517          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1518          *  For RSS setting, it will try to calculate actual configured RX queue
1519          *  number, which will be available after rx_queue_setup(). dev_start()
1520          *  function is good to place RSS setup.
1521          */
1522         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523                 ret = i40e_vmdq_setup(dev);
1524                 if (ret)
1525                         goto err;
1526         }
1527
1528         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529                 ret = i40e_dcb_setup(dev);
1530                 if (ret) {
1531                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532                         goto err_dcb;
1533                 }
1534         }
1535
1536         TAILQ_INIT(&pf->flow_list);
1537
1538         return 0;
1539
1540 err_dcb:
1541         /* need to release vmdq resource if exists */
1542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543                 i40e_vsi_release(pf->vmdq[i].vsi);
1544                 pf->vmdq[i].vsi = NULL;
1545         }
1546         rte_free(pf->vmdq);
1547         pf->vmdq = NULL;
1548 err:
1549         /* need to release fdir resource if exists */
1550         i40e_fdir_teardown(pf);
1551         return ret;
1552 }
1553
1554 void
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1556 {
1557         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_vect = vsi->msix_intr;
1562         uint16_t i;
1563
1564         for (i = 0; i < vsi->nb_qps; i++) {
1565                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567                 rte_wmb();
1568         }
1569
1570         if (vsi->type != I40E_VSI_SRIOV) {
1571                 if (!rte_intr_allow_others(intr_handle)) {
1572                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1574                         I40E_WRITE_REG(hw,
1575                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1576                                        0);
1577                 } else {
1578                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1580                         I40E_WRITE_REG(hw,
1581                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582                                                        msix_vect - 1), 0);
1583                 }
1584         } else {
1585                 uint32_t reg;
1586                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587                         vsi->user_param + (msix_vect - 1);
1588
1589                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591         }
1592         I40E_WRITE_FLUSH(hw);
1593 }
1594
1595 static void
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597                        int base_queue, int nb_queue)
1598 {
1599         int i;
1600         uint32_t val;
1601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1602
1603         /* Bind all RX queues to allocated MSIX interrupt */
1604         for (i = 0; i < nb_queue; i++) {
1605                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1607                         ((base_queue + i + 1) <<
1608                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1611
1612                 if (i == nb_queue - 1)
1613                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1615         }
1616
1617         /* Write first RX queue to Link list register as the head element */
1618         if (vsi->type != I40E_VSI_SRIOV) {
1619                 uint16_t interval =
1620                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1621
1622                 if (msix_vect == I40E_MISC_VEC_ID) {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1630                                        interval);
1631                 } else {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1639                                                        msix_vect - 1),
1640                                        interval);
1641                 }
1642         } else {
1643                 uint32_t reg;
1644
1645                 if (msix_vect == I40E_MISC_VEC_ID) {
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_VPINT_LNKLST0(vsi->user_param),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1652                 } else {
1653                         /* num_msix_vectors_vf needs to minus irq0 */
1654                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655                                 vsi->user_param + (msix_vect - 1);
1656
1657                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1658                                        (base_queue <<
1659                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660                                        (0x0 <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662                 }
1663         }
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 void
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1670 {
1671         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675         uint16_t msix_vect = vsi->msix_intr;
1676         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677         uint16_t queue_idx = 0;
1678         int record = 0;
1679         uint32_t val;
1680         int i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685         }
1686
1687         /* INTENA flag is not auto-cleared for interrupt */
1688         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1693
1694         /* VF bind interrupt */
1695         if (vsi->type == I40E_VSI_SRIOV) {
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue, vsi->nb_qps);
1698                 return;
1699         }
1700
1701         /* PF & VMDq bind interrupt */
1702         if (rte_intr_dp_is_en(intr_handle)) {
1703                 if (vsi->type == I40E_VSI_MAIN) {
1704                         queue_idx = 0;
1705                         record = 1;
1706                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707                         struct i40e_vsi *main_vsi =
1708                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710                         record = 1;
1711                 }
1712         }
1713
1714         for (i = 0; i < vsi->nb_used_qps; i++) {
1715                 if (nb_msix <= 1) {
1716                         if (!rte_intr_allow_others(intr_handle))
1717                                 /* allow to share MISC_VEC_ID */
1718                                 msix_vect = I40E_MISC_VEC_ID;
1719
1720                         /* no enough msix_vect, map all to one */
1721                         __vsi_queues_bind_intr(vsi, msix_vect,
1722                                                vsi->base_queue + i,
1723                                                vsi->nb_used_qps - i);
1724                         for (; !!record && i < vsi->nb_used_qps; i++)
1725                                 intr_handle->intr_vec[queue_idx + i] =
1726                                         msix_vect;
1727                         break;
1728                 }
1729                 /* 1:1 queue/msix_vect mapping */
1730                 __vsi_queues_bind_intr(vsi, msix_vect,
1731                                        vsi->base_queue + i, 1);
1732                 if (!!record)
1733                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734
1735                 msix_vect++;
1736                 nb_msix--;
1737         }
1738 }
1739
1740 static void
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1742 {
1743         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747         uint16_t interval = i40e_calc_itr_interval(\
1748                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749         uint16_t msix_intr, i;
1750
1751         if (rte_intr_allow_others(intr_handle))
1752                 for (i = 0; i < vsi->nb_msix; i++) {
1753                         msix_intr = vsi->msix_intr + i;
1754                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1758                                 (interval <<
1759                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1766                                (interval <<
1767                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static void
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t msix_intr, i;
1780
1781         if (rte_intr_allow_others(intr_handle))
1782                 for (i = 0; i < vsi->nb_msix; i++) {
1783                         msix_intr = vsi->msix_intr + i;
1784                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785                                        0);
1786                 }
1787         else
1788                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1789
1790         I40E_WRITE_FLUSH(hw);
1791 }
1792
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1795 {
1796         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1797
1798         if (link_speeds & ETH_LINK_SPEED_40G)
1799                 link_speed |= I40E_LINK_SPEED_40GB;
1800         if (link_speeds & ETH_LINK_SPEED_25G)
1801                 link_speed |= I40E_LINK_SPEED_25GB;
1802         if (link_speeds & ETH_LINK_SPEED_20G)
1803                 link_speed |= I40E_LINK_SPEED_20GB;
1804         if (link_speeds & ETH_LINK_SPEED_10G)
1805                 link_speed |= I40E_LINK_SPEED_10GB;
1806         if (link_speeds & ETH_LINK_SPEED_1G)
1807                 link_speed |= I40E_LINK_SPEED_1GB;
1808         if (link_speeds & ETH_LINK_SPEED_100M)
1809                 link_speed |= I40E_LINK_SPEED_100MB;
1810
1811         return link_speed;
1812 }
1813
1814 static int
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1816                    uint8_t abilities,
1817                    uint8_t force_speed)
1818 {
1819         enum i40e_status_code status;
1820         struct i40e_aq_get_phy_abilities_resp phy_ab;
1821         struct i40e_aq_set_phy_config phy_conf;
1822         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1823                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1824                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1825                         I40E_AQ_PHY_FLAG_LOW_POWER;
1826         const uint8_t advt = I40E_LINK_SPEED_40GB |
1827                         I40E_LINK_SPEED_25GB |
1828                         I40E_LINK_SPEED_10GB |
1829                         I40E_LINK_SPEED_1GB |
1830                         I40E_LINK_SPEED_100MB;
1831         int ret = -ENOTSUP;
1832
1833
1834         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1835                                               NULL);
1836         if (status)
1837                 return ret;
1838
1839         memset(&phy_conf, 0, sizeof(phy_conf));
1840
1841         /* bits 0-2 use the values from get_phy_abilities_resp */
1842         abilities &= ~mask;
1843         abilities |= phy_ab.abilities & mask;
1844
1845         /* update ablities and speed */
1846         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847                 phy_conf.link_speed = advt;
1848         else
1849                 phy_conf.link_speed = force_speed;
1850
1851         phy_conf.abilities = abilities;
1852
1853         /* use get_phy_abilities_resp value for the rest */
1854         phy_conf.phy_type = phy_ab.phy_type;
1855         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1856         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1857         phy_conf.eee_capability = phy_ab.eee_capability;
1858         phy_conf.eeer = phy_ab.eeer_val;
1859         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1860
1861         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1862                     phy_ab.abilities, phy_ab.link_speed);
1863         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1864                     phy_conf.abilities, phy_conf.link_speed);
1865
1866         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1867         if (status)
1868                 return ret;
1869
1870         return I40E_SUCCESS;
1871 }
1872
1873 static int
1874 i40e_apply_link_speed(struct rte_eth_dev *dev)
1875 {
1876         uint8_t speed;
1877         uint8_t abilities = 0;
1878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct rte_eth_conf *conf = &dev->data->dev_conf;
1880
1881         speed = i40e_parse_link_speeds(conf->link_speeds);
1882         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1883         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1884                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1886
1887         /* Skip changing speed on 40G interfaces, FW does not support */
1888         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1889                 speed =  I40E_LINK_SPEED_UNKNOWN;
1890                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1891         }
1892
1893         return i40e_phy_conf_link(hw, abilities, speed);
1894 }
1895
1896 static int
1897 i40e_dev_start(struct rte_eth_dev *dev)
1898 {
1899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct i40e_vsi *main_vsi = pf->main_vsi;
1902         int ret, i;
1903         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1904         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1905         uint32_t intr_vector = 0;
1906         struct i40e_vsi *vsi;
1907
1908         hw->adapter_stopped = 0;
1909
1910         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1911                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1912                              dev->data->port_id);
1913                 return -EINVAL;
1914         }
1915
1916         rte_intr_disable(intr_handle);
1917
1918         if ((rte_intr_cap_multiple(intr_handle) ||
1919              !RTE_ETH_DEV_SRIOV(dev).active) &&
1920             dev->data->dev_conf.intr_conf.rxq != 0) {
1921                 intr_vector = dev->data->nb_rx_queues;
1922                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1923                 if (ret)
1924                         return ret;
1925         }
1926
1927         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1928                 intr_handle->intr_vec =
1929                         rte_zmalloc("intr_vec",
1930                                     dev->data->nb_rx_queues * sizeof(int),
1931                                     0);
1932                 if (!intr_handle->intr_vec) {
1933                         PMD_INIT_LOG(ERR,
1934                                 "Failed to allocate %d rx_queues intr_vec",
1935                                 dev->data->nb_rx_queues);
1936                         return -ENOMEM;
1937                 }
1938         }
1939
1940         /* Initialize VSI */
1941         ret = i40e_dev_rxtx_init(pf);
1942         if (ret != I40E_SUCCESS) {
1943                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1944                 goto err_up;
1945         }
1946
1947         /* Map queues with MSIX interrupt */
1948         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1949                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1950         i40e_vsi_queues_bind_intr(main_vsi);
1951         i40e_vsi_enable_queues_intr(main_vsi);
1952
1953         /* Map VMDQ VSI queues with MSIX interrupt */
1954         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1956                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1957                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1958         }
1959
1960         /* enable FDIR MSIX interrupt */
1961         if (pf->fdir.fdir_vsi) {
1962                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1963                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1964         }
1965
1966         /* Enable all queues which have been configured */
1967         ret = i40e_dev_switch_queues(pf, TRUE);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1970                 goto err_up;
1971         }
1972
1973         /* Enable receiving broadcast packets */
1974         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1975         if (ret != I40E_SUCCESS)
1976                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977
1978         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1979                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1980                                                 true, NULL);
1981                 if (ret != I40E_SUCCESS)
1982                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1983         }
1984
1985         /* Enable the VLAN promiscuous mode. */
1986         if (pf->vfs) {
1987                 for (i = 0; i < pf->vf_num; i++) {
1988                         vsi = pf->vfs[i].vsi;
1989                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1990                                                      true, NULL);
1991                 }
1992         }
1993
1994         /* Apply link configure */
1995         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998                                 ETH_LINK_SPEED_40G)) {
1999                 PMD_DRV_LOG(ERR, "Invalid link setting");
2000                 goto err_up;
2001         }
2002         ret = i40e_apply_link_speed(dev);
2003         if (I40E_SUCCESS != ret) {
2004                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2005                 goto err_up;
2006         }
2007
2008         if (!rte_intr_allow_others(intr_handle)) {
2009                 rte_intr_callback_unregister(intr_handle,
2010                                              i40e_dev_interrupt_handler,
2011                                              (void *)dev);
2012                 /* configure and enable device interrupt */
2013                 i40e_pf_config_irq0(hw, FALSE);
2014                 i40e_pf_enable_irq0(hw);
2015
2016                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2017                         PMD_INIT_LOG(INFO,
2018                                 "lsc won't enable because of no intr multiplex");
2019         } else {
2020                 ret = i40e_aq_set_phy_int_mask(hw,
2021                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2024                 if (ret != I40E_SUCCESS)
2025                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2026
2027                 /* Call get_link_info aq commond to enable/disable LSE */
2028                 i40e_dev_link_update(dev, 0);
2029         }
2030
2031         /* enable uio intr after callback register */
2032         rte_intr_enable(intr_handle);
2033
2034         i40e_filter_restore(pf);
2035
2036         if (!pf->tm_conf.committed)
2037                 PMD_DRV_LOG(WARNING,
2038                             "please call hierarchy_commit() "
2039                             "before starting the port");
2040
2041         return I40E_SUCCESS;
2042
2043 err_up:
2044         i40e_dev_switch_queues(pf, FALSE);
2045         i40e_dev_clear_queues(dev);
2046
2047         return ret;
2048 }
2049
2050 static void
2051 i40e_dev_stop(struct rte_eth_dev *dev)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         struct i40e_vsi *main_vsi = pf->main_vsi;
2056         struct i40e_mirror_rule *p_mirror;
2057         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2059         int i;
2060
2061         if (hw->adapter_stopped == 1)
2062                 return;
2063         /* Disable all queues */
2064         i40e_dev_switch_queues(pf, FALSE);
2065
2066         /* un-map queues with interrupt registers */
2067         i40e_vsi_disable_queues_intr(main_vsi);
2068         i40e_vsi_queues_unbind_intr(main_vsi);
2069
2070         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2071                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2072                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2073         }
2074
2075         if (pf->fdir.fdir_vsi) {
2076                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2077                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2078         }
2079         /* Clear all queues and release memory */
2080         i40e_dev_clear_queues(dev);
2081
2082         /* Set link down */
2083         i40e_dev_set_link_down(dev);
2084
2085         /* Remove all mirror rules */
2086         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2087                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2088                 rte_free(p_mirror);
2089         }
2090         pf->nb_mirror_rule = 0;
2091
2092         if (!rte_intr_allow_others(intr_handle))
2093                 /* resume to the default handler */
2094                 rte_intr_callback_register(intr_handle,
2095                                            i40e_dev_interrupt_handler,
2096                                            (void *)dev);
2097
2098         /* Clean datapath event and queue/vec mapping */
2099         rte_intr_efd_disable(intr_handle);
2100         if (intr_handle->intr_vec) {
2101                 rte_free(intr_handle->intr_vec);
2102                 intr_handle->intr_vec = NULL;
2103         }
2104
2105         /* reset hierarchy commit */
2106         pf->tm_conf.committed = false;
2107
2108         hw->adapter_stopped = 1;
2109 }
2110
2111 static void
2112 i40e_dev_close(struct rte_eth_dev *dev)
2113 {
2114         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2115         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2116         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2117         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2118         uint32_t reg;
2119         int i;
2120
2121         PMD_INIT_FUNC_TRACE();
2122
2123         i40e_dev_stop(dev);
2124         i40e_dev_free_queues(dev);
2125
2126         /* Disable interrupt */
2127         i40e_pf_disable_irq0(hw);
2128         rte_intr_disable(intr_handle);
2129
2130         /* shutdown and destroy the HMC */
2131         i40e_shutdown_lan_hmc(hw);
2132
2133         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2134                 i40e_vsi_release(pf->vmdq[i].vsi);
2135                 pf->vmdq[i].vsi = NULL;
2136         }
2137         rte_free(pf->vmdq);
2138         pf->vmdq = NULL;
2139
2140         /* release all the existing VSIs and VEBs */
2141         i40e_fdir_teardown(pf);
2142         i40e_vsi_release(pf->main_vsi);
2143
2144         /* shutdown the adminq */
2145         i40e_aq_queue_shutdown(hw, true);
2146         i40e_shutdown_adminq(hw);
2147
2148         i40e_res_pool_destroy(&pf->qp_pool);
2149         i40e_res_pool_destroy(&pf->msix_pool);
2150
2151         /* force a PF reset to clean anything leftover */
2152         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2153         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2154                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2155         I40E_WRITE_FLUSH(hw);
2156 }
2157
2158 static void
2159 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2160 {
2161         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct i40e_vsi *vsi = pf->main_vsi;
2164         int status;
2165
2166         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2167                                                      true, NULL, true);
2168         if (status != I40E_SUCCESS)
2169                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2170
2171         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2172                                                         TRUE, NULL);
2173         if (status != I40E_SUCCESS)
2174                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2175
2176 }
2177
2178 static void
2179 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2180 {
2181         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183         struct i40e_vsi *vsi = pf->main_vsi;
2184         int status;
2185
2186         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2187                                                      false, NULL, true);
2188         if (status != I40E_SUCCESS)
2189                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2190
2191         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2192                                                         false, NULL);
2193         if (status != I40E_SUCCESS)
2194                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2195 }
2196
2197 static void
2198 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2199 {
2200         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         struct i40e_vsi *vsi = pf->main_vsi;
2203         int ret;
2204
2205         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2206         if (ret != I40E_SUCCESS)
2207                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2208 }
2209
2210 static void
2211 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2212 {
2213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2214         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215         struct i40e_vsi *vsi = pf->main_vsi;
2216         int ret;
2217
2218         if (dev->data->promiscuous == 1)
2219                 return; /* must remain in all_multicast mode */
2220
2221         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2222                                 vsi->seid, FALSE, NULL);
2223         if (ret != I40E_SUCCESS)
2224                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2225 }
2226
2227 /*
2228  * Set device link up.
2229  */
2230 static int
2231 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2232 {
2233         /* re-apply link speed setting */
2234         return i40e_apply_link_speed(dev);
2235 }
2236
2237 /*
2238  * Set device link down.
2239  */
2240 static int
2241 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2242 {
2243         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2244         uint8_t abilities = 0;
2245         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246
2247         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2248         return i40e_phy_conf_link(hw, abilities, speed);
2249 }
2250
2251 int
2252 i40e_dev_link_update(struct rte_eth_dev *dev,
2253                      int wait_to_complete)
2254 {
2255 #define CHECK_INTERVAL 100  /* 100ms */
2256 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258         struct i40e_link_status link_status;
2259         struct rte_eth_link link, old;
2260         int status;
2261         unsigned rep_cnt = MAX_REPEAT_TIME;
2262         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2263
2264         memset(&link, 0, sizeof(link));
2265         memset(&old, 0, sizeof(old));
2266         memset(&link_status, 0, sizeof(link_status));
2267         rte_i40e_dev_atomic_read_link_status(dev, &old);
2268
2269         do {
2270                 /* Get link status information from hardware */
2271                 status = i40e_aq_get_link_info(hw, enable_lse,
2272                                                 &link_status, NULL);
2273                 if (status != I40E_SUCCESS) {
2274                         link.link_speed = ETH_SPEED_NUM_100M;
2275                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2276                         PMD_DRV_LOG(ERR, "Failed to get link info");
2277                         goto out;
2278                 }
2279
2280                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2281                 if (!wait_to_complete || link.link_status)
2282                         break;
2283
2284                 rte_delay_ms(CHECK_INTERVAL);
2285         } while (--rep_cnt);
2286
2287         if (!link.link_status)
2288                 goto out;
2289
2290         /* i40e uses full duplex only */
2291         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2292
2293         /* Parse the link status */
2294         switch (link_status.link_speed) {
2295         case I40E_LINK_SPEED_100MB:
2296                 link.link_speed = ETH_SPEED_NUM_100M;
2297                 break;
2298         case I40E_LINK_SPEED_1GB:
2299                 link.link_speed = ETH_SPEED_NUM_1G;
2300                 break;
2301         case I40E_LINK_SPEED_10GB:
2302                 link.link_speed = ETH_SPEED_NUM_10G;
2303                 break;
2304         case I40E_LINK_SPEED_20GB:
2305                 link.link_speed = ETH_SPEED_NUM_20G;
2306                 break;
2307         case I40E_LINK_SPEED_25GB:
2308                 link.link_speed = ETH_SPEED_NUM_25G;
2309                 break;
2310         case I40E_LINK_SPEED_40GB:
2311                 link.link_speed = ETH_SPEED_NUM_40G;
2312                 break;
2313         default:
2314                 link.link_speed = ETH_SPEED_NUM_100M;
2315                 break;
2316         }
2317
2318         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2319                         ETH_LINK_SPEED_FIXED);
2320
2321 out:
2322         rte_i40e_dev_atomic_write_link_status(dev, &link);
2323         if (link.link_status == old.link_status)
2324                 return -1;
2325
2326         i40e_notify_all_vfs_link_status(dev);
2327
2328         return 0;
2329 }
2330
2331 /* Get all the statistics of a VSI */
2332 void
2333 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2334 {
2335         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2336         struct i40e_eth_stats *nes = &vsi->eth_stats;
2337         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2338         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2339
2340         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2341                             vsi->offset_loaded, &oes->rx_bytes,
2342                             &nes->rx_bytes);
2343         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2344                             vsi->offset_loaded, &oes->rx_unicast,
2345                             &nes->rx_unicast);
2346         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2347                             vsi->offset_loaded, &oes->rx_multicast,
2348                             &nes->rx_multicast);
2349         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2350                             vsi->offset_loaded, &oes->rx_broadcast,
2351                             &nes->rx_broadcast);
2352         /* exclude CRC bytes */
2353         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2354                 nes->rx_broadcast) * ETHER_CRC_LEN;
2355
2356         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2357                             &oes->rx_discards, &nes->rx_discards);
2358         /* GLV_REPC not supported */
2359         /* GLV_RMPC not supported */
2360         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2361                             &oes->rx_unknown_protocol,
2362                             &nes->rx_unknown_protocol);
2363         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2364                             vsi->offset_loaded, &oes->tx_bytes,
2365                             &nes->tx_bytes);
2366         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2367                             vsi->offset_loaded, &oes->tx_unicast,
2368                             &nes->tx_unicast);
2369         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2370                             vsi->offset_loaded, &oes->tx_multicast,
2371                             &nes->tx_multicast);
2372         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2373                             vsi->offset_loaded,  &oes->tx_broadcast,
2374                             &nes->tx_broadcast);
2375         /* GLV_TDPC not supported */
2376         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2377                             &oes->tx_errors, &nes->tx_errors);
2378         vsi->offset_loaded = true;
2379
2380         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2381                     vsi->vsi_id);
2382         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2383         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2384         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2385         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2386         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2387         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2388                     nes->rx_unknown_protocol);
2389         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2390         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2391         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2392         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2393         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2394         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2395         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2396                     vsi->vsi_id);
2397 }
2398
2399 static void
2400 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2401 {
2402         unsigned int i;
2403         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2404         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2405
2406         /* Get rx/tx bytes of internal transfer packets */
2407         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2408                         I40E_GLV_GORCL(hw->port),
2409                         pf->offset_loaded,
2410                         &pf->internal_stats_offset.rx_bytes,
2411                         &pf->internal_stats.rx_bytes);
2412
2413         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2414                         I40E_GLV_GOTCL(hw->port),
2415                         pf->offset_loaded,
2416                         &pf->internal_stats_offset.tx_bytes,
2417                         &pf->internal_stats.tx_bytes);
2418         /* Get total internal rx packet count */
2419         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2420                             I40E_GLV_UPRCL(hw->port),
2421                             pf->offset_loaded,
2422                             &pf->internal_stats_offset.rx_unicast,
2423                             &pf->internal_stats.rx_unicast);
2424         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2425                             I40E_GLV_MPRCL(hw->port),
2426                             pf->offset_loaded,
2427                             &pf->internal_stats_offset.rx_multicast,
2428                             &pf->internal_stats.rx_multicast);
2429         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2430                             I40E_GLV_BPRCL(hw->port),
2431                             pf->offset_loaded,
2432                             &pf->internal_stats_offset.rx_broadcast,
2433                             &pf->internal_stats.rx_broadcast);
2434
2435         /* exclude CRC size */
2436         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2437                 pf->internal_stats.rx_multicast +
2438                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2439
2440         /* Get statistics of struct i40e_eth_stats */
2441         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2442                             I40E_GLPRT_GORCL(hw->port),
2443                             pf->offset_loaded, &os->eth.rx_bytes,
2444                             &ns->eth.rx_bytes);
2445         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2446                             I40E_GLPRT_UPRCL(hw->port),
2447                             pf->offset_loaded, &os->eth.rx_unicast,
2448                             &ns->eth.rx_unicast);
2449         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2450                             I40E_GLPRT_MPRCL(hw->port),
2451                             pf->offset_loaded, &os->eth.rx_multicast,
2452                             &ns->eth.rx_multicast);
2453         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2454                             I40E_GLPRT_BPRCL(hw->port),
2455                             pf->offset_loaded, &os->eth.rx_broadcast,
2456                             &ns->eth.rx_broadcast);
2457         /* Workaround: CRC size should not be included in byte statistics,
2458          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2459          */
2460         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2461                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2462
2463         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2464          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2465          * value.
2466          */
2467         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2468                 ns->eth.rx_bytes = 0;
2469         /* exlude internal rx bytes */
2470         else
2471                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2472
2473         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2474                             pf->offset_loaded, &os->eth.rx_discards,
2475                             &ns->eth.rx_discards);
2476         /* GLPRT_REPC not supported */
2477         /* GLPRT_RMPC not supported */
2478         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2479                             pf->offset_loaded,
2480                             &os->eth.rx_unknown_protocol,
2481                             &ns->eth.rx_unknown_protocol);
2482         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2483                             I40E_GLPRT_GOTCL(hw->port),
2484                             pf->offset_loaded, &os->eth.tx_bytes,
2485                             &ns->eth.tx_bytes);
2486         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2487                             I40E_GLPRT_UPTCL(hw->port),
2488                             pf->offset_loaded, &os->eth.tx_unicast,
2489                             &ns->eth.tx_unicast);
2490         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2491                             I40E_GLPRT_MPTCL(hw->port),
2492                             pf->offset_loaded, &os->eth.tx_multicast,
2493                             &ns->eth.tx_multicast);
2494         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2495                             I40E_GLPRT_BPTCL(hw->port),
2496                             pf->offset_loaded, &os->eth.tx_broadcast,
2497                             &ns->eth.tx_broadcast);
2498         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2499                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2500
2501         /* exclude internal tx bytes */
2502         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2503                 ns->eth.tx_bytes = 0;
2504         else
2505                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2506
2507         /* GLPRT_TEPC not supported */
2508
2509         /* additional port specific stats */
2510         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2511                             pf->offset_loaded, &os->tx_dropped_link_down,
2512                             &ns->tx_dropped_link_down);
2513         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2514                             pf->offset_loaded, &os->crc_errors,
2515                             &ns->crc_errors);
2516         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2517                             pf->offset_loaded, &os->illegal_bytes,
2518                             &ns->illegal_bytes);
2519         /* GLPRT_ERRBC not supported */
2520         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2521                             pf->offset_loaded, &os->mac_local_faults,
2522                             &ns->mac_local_faults);
2523         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2524                             pf->offset_loaded, &os->mac_remote_faults,
2525                             &ns->mac_remote_faults);
2526         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2527                             pf->offset_loaded, &os->rx_length_errors,
2528                             &ns->rx_length_errors);
2529         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2530                             pf->offset_loaded, &os->link_xon_rx,
2531                             &ns->link_xon_rx);
2532         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2533                             pf->offset_loaded, &os->link_xoff_rx,
2534                             &ns->link_xoff_rx);
2535         for (i = 0; i < 8; i++) {
2536                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2537                                     pf->offset_loaded,
2538                                     &os->priority_xon_rx[i],
2539                                     &ns->priority_xon_rx[i]);
2540                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2541                                     pf->offset_loaded,
2542                                     &os->priority_xoff_rx[i],
2543                                     &ns->priority_xoff_rx[i]);
2544         }
2545         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2546                             pf->offset_loaded, &os->link_xon_tx,
2547                             &ns->link_xon_tx);
2548         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2549                             pf->offset_loaded, &os->link_xoff_tx,
2550                             &ns->link_xoff_tx);
2551         for (i = 0; i < 8; i++) {
2552                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2553                                     pf->offset_loaded,
2554                                     &os->priority_xon_tx[i],
2555                                     &ns->priority_xon_tx[i]);
2556                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2557                                     pf->offset_loaded,
2558                                     &os->priority_xoff_tx[i],
2559                                     &ns->priority_xoff_tx[i]);
2560                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2561                                     pf->offset_loaded,
2562                                     &os->priority_xon_2_xoff[i],
2563                                     &ns->priority_xon_2_xoff[i]);
2564         }
2565         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2566                             I40E_GLPRT_PRC64L(hw->port),
2567                             pf->offset_loaded, &os->rx_size_64,
2568                             &ns->rx_size_64);
2569         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2570                             I40E_GLPRT_PRC127L(hw->port),
2571                             pf->offset_loaded, &os->rx_size_127,
2572                             &ns->rx_size_127);
2573         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2574                             I40E_GLPRT_PRC255L(hw->port),
2575                             pf->offset_loaded, &os->rx_size_255,
2576                             &ns->rx_size_255);
2577         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2578                             I40E_GLPRT_PRC511L(hw->port),
2579                             pf->offset_loaded, &os->rx_size_511,
2580                             &ns->rx_size_511);
2581         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2582                             I40E_GLPRT_PRC1023L(hw->port),
2583                             pf->offset_loaded, &os->rx_size_1023,
2584                             &ns->rx_size_1023);
2585         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2586                             I40E_GLPRT_PRC1522L(hw->port),
2587                             pf->offset_loaded, &os->rx_size_1522,
2588                             &ns->rx_size_1522);
2589         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2590                             I40E_GLPRT_PRC9522L(hw->port),
2591                             pf->offset_loaded, &os->rx_size_big,
2592                             &ns->rx_size_big);
2593         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2594                             pf->offset_loaded, &os->rx_undersize,
2595                             &ns->rx_undersize);
2596         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2597                             pf->offset_loaded, &os->rx_fragments,
2598                             &ns->rx_fragments);
2599         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2600                             pf->offset_loaded, &os->rx_oversize,
2601                             &ns->rx_oversize);
2602         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2603                             pf->offset_loaded, &os->rx_jabber,
2604                             &ns->rx_jabber);
2605         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2606                             I40E_GLPRT_PTC64L(hw->port),
2607                             pf->offset_loaded, &os->tx_size_64,
2608                             &ns->tx_size_64);
2609         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2610                             I40E_GLPRT_PTC127L(hw->port),
2611                             pf->offset_loaded, &os->tx_size_127,
2612                             &ns->tx_size_127);
2613         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2614                             I40E_GLPRT_PTC255L(hw->port),
2615                             pf->offset_loaded, &os->tx_size_255,
2616                             &ns->tx_size_255);
2617         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2618                             I40E_GLPRT_PTC511L(hw->port),
2619                             pf->offset_loaded, &os->tx_size_511,
2620                             &ns->tx_size_511);
2621         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2622                             I40E_GLPRT_PTC1023L(hw->port),
2623                             pf->offset_loaded, &os->tx_size_1023,
2624                             &ns->tx_size_1023);
2625         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2626                             I40E_GLPRT_PTC1522L(hw->port),
2627                             pf->offset_loaded, &os->tx_size_1522,
2628                             &ns->tx_size_1522);
2629         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2630                             I40E_GLPRT_PTC9522L(hw->port),
2631                             pf->offset_loaded, &os->tx_size_big,
2632                             &ns->tx_size_big);
2633         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2634                            pf->offset_loaded,
2635                            &os->fd_sb_match, &ns->fd_sb_match);
2636         /* GLPRT_MSPDC not supported */
2637         /* GLPRT_XEC not supported */
2638
2639         pf->offset_loaded = true;
2640
2641         if (pf->main_vsi)
2642                 i40e_update_vsi_stats(pf->main_vsi);
2643 }
2644
2645 /* Get all statistics of a port */
2646 static void
2647 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2648 {
2649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2651         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2652         unsigned i;
2653
2654         /* call read registers - updates values, now write them to struct */
2655         i40e_read_stats_registers(pf, hw);
2656
2657         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2658                         pf->main_vsi->eth_stats.rx_multicast +
2659                         pf->main_vsi->eth_stats.rx_broadcast -
2660                         pf->main_vsi->eth_stats.rx_discards;
2661         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2662                         pf->main_vsi->eth_stats.tx_multicast +
2663                         pf->main_vsi->eth_stats.tx_broadcast;
2664         stats->ibytes   = ns->eth.rx_bytes;
2665         stats->obytes   = ns->eth.tx_bytes;
2666         stats->oerrors  = ns->eth.tx_errors +
2667                         pf->main_vsi->eth_stats.tx_errors;
2668
2669         /* Rx Errors */
2670         stats->imissed  = ns->eth.rx_discards +
2671                         pf->main_vsi->eth_stats.rx_discards;
2672         stats->ierrors  = ns->crc_errors +
2673                         ns->rx_length_errors + ns->rx_undersize +
2674                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2675
2676         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2677         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2678         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2679         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2680         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2681         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2682         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2683                     ns->eth.rx_unknown_protocol);
2684         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2685         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2686         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2687         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2688         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2689         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2690
2691         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2692                     ns->tx_dropped_link_down);
2693         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2694         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2695                     ns->illegal_bytes);
2696         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2697         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2698                     ns->mac_local_faults);
2699         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2700                     ns->mac_remote_faults);
2701         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2702                     ns->rx_length_errors);
2703         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2704         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2705         for (i = 0; i < 8; i++) {
2706                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2707                                 i, ns->priority_xon_rx[i]);
2708                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2709                                 i, ns->priority_xoff_rx[i]);
2710         }
2711         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2712         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2713         for (i = 0; i < 8; i++) {
2714                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2715                                 i, ns->priority_xon_tx[i]);
2716                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2717                                 i, ns->priority_xoff_tx[i]);
2718                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2719                                 i, ns->priority_xon_2_xoff[i]);
2720         }
2721         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2722         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2723         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2724         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2725         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2726         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2727         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2728         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2729         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2730         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2731         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2732         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2733         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2734         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2735         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2736         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2737         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2738         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2739         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2740                         ns->mac_short_packet_dropped);
2741         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2742                     ns->checksum_error);
2743         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2744         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2745 }
2746
2747 /* Reset the statistics */
2748 static void
2749 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2750 {
2751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2753
2754         /* Mark PF and VSI stats to update the offset, aka "reset" */
2755         pf->offset_loaded = false;
2756         if (pf->main_vsi)
2757                 pf->main_vsi->offset_loaded = false;
2758
2759         /* read the stats, reading current register values into offset */
2760         i40e_read_stats_registers(pf, hw);
2761 }
2762
2763 static uint32_t
2764 i40e_xstats_calc_num(void)
2765 {
2766         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2767                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2768                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2769 }
2770
2771 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2772                                      struct rte_eth_xstat_name *xstats_names,
2773                                      __rte_unused unsigned limit)
2774 {
2775         unsigned count = 0;
2776         unsigned i, prio;
2777
2778         if (xstats_names == NULL)
2779                 return i40e_xstats_calc_num();
2780
2781         /* Note: limit checked in rte_eth_xstats_names() */
2782
2783         /* Get stats from i40e_eth_stats struct */
2784         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2785                 snprintf(xstats_names[count].name,
2786                          sizeof(xstats_names[count].name),
2787                          "%s", rte_i40e_stats_strings[i].name);
2788                 count++;
2789         }
2790
2791         /* Get individiual stats from i40e_hw_port struct */
2792         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2793                 snprintf(xstats_names[count].name,
2794                         sizeof(xstats_names[count].name),
2795                          "%s", rte_i40e_hw_port_strings[i].name);
2796                 count++;
2797         }
2798
2799         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2800                 for (prio = 0; prio < 8; prio++) {
2801                         snprintf(xstats_names[count].name,
2802                                  sizeof(xstats_names[count].name),
2803                                  "rx_priority%u_%s", prio,
2804                                  rte_i40e_rxq_prio_strings[i].name);
2805                         count++;
2806                 }
2807         }
2808
2809         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2810                 for (prio = 0; prio < 8; prio++) {
2811                         snprintf(xstats_names[count].name,
2812                                  sizeof(xstats_names[count].name),
2813                                  "tx_priority%u_%s", prio,
2814                                  rte_i40e_txq_prio_strings[i].name);
2815                         count++;
2816                 }
2817         }
2818         return count;
2819 }
2820
2821 static int
2822 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2823                     unsigned n)
2824 {
2825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827         unsigned i, count, prio;
2828         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2829
2830         count = i40e_xstats_calc_num();
2831         if (n < count)
2832                 return count;
2833
2834         i40e_read_stats_registers(pf, hw);
2835
2836         if (xstats == NULL)
2837                 return 0;
2838
2839         count = 0;
2840
2841         /* Get stats from i40e_eth_stats struct */
2842         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2843                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2844                         rte_i40e_stats_strings[i].offset);
2845                 xstats[count].id = count;
2846                 count++;
2847         }
2848
2849         /* Get individiual stats from i40e_hw_port struct */
2850         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2851                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2852                         rte_i40e_hw_port_strings[i].offset);
2853                 xstats[count].id = count;
2854                 count++;
2855         }
2856
2857         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2858                 for (prio = 0; prio < 8; prio++) {
2859                         xstats[count].value =
2860                                 *(uint64_t *)(((char *)hw_stats) +
2861                                 rte_i40e_rxq_prio_strings[i].offset +
2862                                 (sizeof(uint64_t) * prio));
2863                         xstats[count].id = count;
2864                         count++;
2865                 }
2866         }
2867
2868         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2869                 for (prio = 0; prio < 8; prio++) {
2870                         xstats[count].value =
2871                                 *(uint64_t *)(((char *)hw_stats) +
2872                                 rte_i40e_txq_prio_strings[i].offset +
2873                                 (sizeof(uint64_t) * prio));
2874                         xstats[count].id = count;
2875                         count++;
2876                 }
2877         }
2878
2879         return count;
2880 }
2881
2882 static int
2883 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2884                                  __rte_unused uint16_t queue_id,
2885                                  __rte_unused uint8_t stat_idx,
2886                                  __rte_unused uint8_t is_rx)
2887 {
2888         PMD_INIT_FUNC_TRACE();
2889
2890         return -ENOSYS;
2891 }
2892
2893 static int
2894 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2895 {
2896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2897         u32 full_ver;
2898         u8 ver, patch;
2899         u16 build;
2900         int ret;
2901
2902         full_ver = hw->nvm.oem_ver;
2903         ver = (u8)(full_ver >> 24);
2904         build = (u16)((full_ver >> 8) & 0xffff);
2905         patch = (u8)(full_ver & 0xff);
2906
2907         ret = snprintf(fw_version, fw_size,
2908                  "%d.%d%d 0x%08x %d.%d.%d",
2909                  ((hw->nvm.version >> 12) & 0xf),
2910                  ((hw->nvm.version >> 4) & 0xff),
2911                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2912                  ver, build, patch);
2913
2914         ret += 1; /* add the size of '\0' */
2915         if (fw_size < (u32)ret)
2916                 return ret;
2917         else
2918                 return 0;
2919 }
2920
2921 static void
2922 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2923 {
2924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2926         struct i40e_vsi *vsi = pf->main_vsi;
2927         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2928
2929         dev_info->pci_dev = pci_dev;
2930         dev_info->max_rx_queues = vsi->nb_qps;
2931         dev_info->max_tx_queues = vsi->nb_qps;
2932         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2933         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2934         dev_info->max_mac_addrs = vsi->max_macaddrs;
2935         dev_info->max_vfs = pci_dev->max_vfs;
2936         dev_info->rx_offload_capa =
2937                 DEV_RX_OFFLOAD_VLAN_STRIP |
2938                 DEV_RX_OFFLOAD_QINQ_STRIP |
2939                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2940                 DEV_RX_OFFLOAD_UDP_CKSUM |
2941                 DEV_RX_OFFLOAD_TCP_CKSUM;
2942         dev_info->tx_offload_capa =
2943                 DEV_TX_OFFLOAD_VLAN_INSERT |
2944                 DEV_TX_OFFLOAD_QINQ_INSERT |
2945                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2946                 DEV_TX_OFFLOAD_UDP_CKSUM |
2947                 DEV_TX_OFFLOAD_TCP_CKSUM |
2948                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2949                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2950                 DEV_TX_OFFLOAD_TCP_TSO |
2951                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2952                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2953                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2954                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2955         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2956                                                 sizeof(uint32_t);
2957         dev_info->reta_size = pf->hash_lut_size;
2958         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2959
2960         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2961                 .rx_thresh = {
2962                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2963                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2964                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2965                 },
2966                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2967                 .rx_drop_en = 0,
2968         };
2969
2970         dev_info->default_txconf = (struct rte_eth_txconf) {
2971                 .tx_thresh = {
2972                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2973                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2974                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2975                 },
2976                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2977                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2978                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2979                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2980         };
2981
2982         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2983                 .nb_max = I40E_MAX_RING_DESC,
2984                 .nb_min = I40E_MIN_RING_DESC,
2985                 .nb_align = I40E_ALIGN_RING_DESC,
2986         };
2987
2988         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2989                 .nb_max = I40E_MAX_RING_DESC,
2990                 .nb_min = I40E_MIN_RING_DESC,
2991                 .nb_align = I40E_ALIGN_RING_DESC,
2992                 .nb_seg_max = I40E_TX_MAX_SEG,
2993                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2994         };
2995
2996         if (pf->flags & I40E_FLAG_VMDQ) {
2997                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2998                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2999                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3000                                                 pf->max_nb_vmdq_vsi;
3001                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3002                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3003                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3004         }
3005
3006         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3007                 /* For XL710 */
3008                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3009         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3010                 /* For XXV710 */
3011                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3012         else
3013                 /* For X710 */
3014                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3015 }
3016
3017 static int
3018 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3019 {
3020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3021         struct i40e_vsi *vsi = pf->main_vsi;
3022         PMD_INIT_FUNC_TRACE();
3023
3024         if (on)
3025                 return i40e_vsi_add_vlan(vsi, vlan_id);
3026         else
3027                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3028 }
3029
3030 static int
3031 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3032                                 enum rte_vlan_type vlan_type,
3033                                 uint16_t tpid, int qinq)
3034 {
3035         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3036         uint64_t reg_r = 0;
3037         uint64_t reg_w = 0;
3038         uint16_t reg_id = 3;
3039         int ret;
3040
3041         if (qinq) {
3042                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3043                         reg_id = 2;
3044         }
3045
3046         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3047                                           &reg_r, NULL);
3048         if (ret != I40E_SUCCESS) {
3049                 PMD_DRV_LOG(ERR,
3050                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3051                            reg_id);
3052                 return -EIO;
3053         }
3054         PMD_DRV_LOG(DEBUG,
3055                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3056                     reg_id, reg_r);
3057
3058         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3059         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3060         if (reg_r == reg_w) {
3061                 PMD_DRV_LOG(DEBUG, "No need to write");
3062                 return 0;
3063         }
3064
3065         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3066                                            reg_w, NULL);
3067         if (ret != I40E_SUCCESS) {
3068                 PMD_DRV_LOG(ERR,
3069                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3070                             reg_id);
3071                 return -EIO;
3072         }
3073         PMD_DRV_LOG(DEBUG,
3074                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3075                     reg_w, reg_id);
3076
3077         return 0;
3078 }
3079
3080 static int
3081 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3082                    enum rte_vlan_type vlan_type,
3083                    uint16_t tpid)
3084 {
3085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3086         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3087         int ret = 0;
3088
3089         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3090              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3091             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3092                 PMD_DRV_LOG(ERR,
3093                             "Unsupported vlan type.");
3094                 return -EINVAL;
3095         }
3096         /* 802.1ad frames ability is added in NVM API 1.7*/
3097         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3098                 if (qinq) {
3099                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3100                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3101                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3102                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3103                 } else {
3104                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3105                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3106                 }
3107                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3108                 if (ret != I40E_SUCCESS) {
3109                         PMD_DRV_LOG(ERR,
3110                                     "Set switch config failed aq_err: %d",
3111                                     hw->aq.asq_last_status);
3112                         ret = -EIO;
3113                 }
3114         } else
3115                 /* If NVM API < 1.7, keep the register setting */
3116                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3117                                                       tpid, qinq);
3118
3119         return ret;
3120 }
3121
3122 static void
3123 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3124 {
3125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126         struct i40e_vsi *vsi = pf->main_vsi;
3127
3128         if (mask & ETH_VLAN_FILTER_MASK) {
3129                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3130                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3131                 else
3132                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3133         }
3134
3135         if (mask & ETH_VLAN_STRIP_MASK) {
3136                 /* Enable or disable VLAN stripping */
3137                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3138                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3139                 else
3140                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3141         }
3142
3143         if (mask & ETH_VLAN_EXTEND_MASK) {
3144                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3145                         i40e_vsi_config_double_vlan(vsi, TRUE);
3146                         /* Set global registers with default ethertype. */
3147                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3148                                            ETHER_TYPE_VLAN);
3149                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3150                                            ETHER_TYPE_VLAN);
3151                 }
3152                 else
3153                         i40e_vsi_config_double_vlan(vsi, FALSE);
3154         }
3155 }
3156
3157 static void
3158 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3159                           __rte_unused uint16_t queue,
3160                           __rte_unused int on)
3161 {
3162         PMD_INIT_FUNC_TRACE();
3163 }
3164
3165 static int
3166 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3167 {
3168         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3169         struct i40e_vsi *vsi = pf->main_vsi;
3170         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3171         struct i40e_vsi_vlan_pvid_info info;
3172
3173         memset(&info, 0, sizeof(info));
3174         info.on = on;
3175         if (info.on)
3176                 info.config.pvid = pvid;
3177         else {
3178                 info.config.reject.tagged =
3179                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3180                 info.config.reject.untagged =
3181                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3182         }
3183
3184         return i40e_vsi_vlan_pvid_set(vsi, &info);
3185 }
3186
3187 static int
3188 i40e_dev_led_on(struct rte_eth_dev *dev)
3189 {
3190         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3191         uint32_t mode = i40e_led_get(hw);
3192
3193         if (mode == 0)
3194                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3195
3196         return 0;
3197 }
3198
3199 static int
3200 i40e_dev_led_off(struct rte_eth_dev *dev)
3201 {
3202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3203         uint32_t mode = i40e_led_get(hw);
3204
3205         if (mode != 0)
3206                 i40e_led_set(hw, 0, false);
3207
3208         return 0;
3209 }
3210
3211 static int
3212 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3213 {
3214         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3215         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3216
3217         fc_conf->pause_time = pf->fc_conf.pause_time;
3218         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3219         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3220
3221          /* Return current mode according to actual setting*/
3222         switch (hw->fc.current_mode) {
3223         case I40E_FC_FULL:
3224                 fc_conf->mode = RTE_FC_FULL;
3225                 break;
3226         case I40E_FC_TX_PAUSE:
3227                 fc_conf->mode = RTE_FC_TX_PAUSE;
3228                 break;
3229         case I40E_FC_RX_PAUSE:
3230                 fc_conf->mode = RTE_FC_RX_PAUSE;
3231                 break;
3232         case I40E_FC_NONE:
3233         default:
3234                 fc_conf->mode = RTE_FC_NONE;
3235         };
3236
3237         return 0;
3238 }
3239
3240 static int
3241 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3242 {
3243         uint32_t mflcn_reg, fctrl_reg, reg;
3244         uint32_t max_high_water;
3245         uint8_t i, aq_failure;
3246         int err;
3247         struct i40e_hw *hw;
3248         struct i40e_pf *pf;
3249         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3250                 [RTE_FC_NONE] = I40E_FC_NONE,
3251                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3252                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3253                 [RTE_FC_FULL] = I40E_FC_FULL
3254         };
3255
3256         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3257
3258         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3259         if ((fc_conf->high_water > max_high_water) ||
3260                         (fc_conf->high_water < fc_conf->low_water)) {
3261                 PMD_INIT_LOG(ERR,
3262                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3263                         max_high_water);
3264                 return -EINVAL;
3265         }
3266
3267         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3268         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3269         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3270
3271         pf->fc_conf.pause_time = fc_conf->pause_time;
3272         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3273         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3274
3275         PMD_INIT_FUNC_TRACE();
3276
3277         /* All the link flow control related enable/disable register
3278          * configuration is handle by the F/W
3279          */
3280         err = i40e_set_fc(hw, &aq_failure, true);
3281         if (err < 0)
3282                 return -ENOSYS;
3283
3284         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3285                 /* Configure flow control refresh threshold,
3286                  * the value for stat_tx_pause_refresh_timer[8]
3287                  * is used for global pause operation.
3288                  */
3289
3290                 I40E_WRITE_REG(hw,
3291                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3292                                pf->fc_conf.pause_time);
3293
3294                 /* configure the timer value included in transmitted pause
3295                  * frame,
3296                  * the value for stat_tx_pause_quanta[8] is used for global
3297                  * pause operation
3298                  */
3299                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3300                                pf->fc_conf.pause_time);
3301
3302                 fctrl_reg = I40E_READ_REG(hw,
3303                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3304
3305                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3306                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3307                 else
3308                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3309
3310                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3311                                fctrl_reg);
3312         } else {
3313                 /* Configure pause time (2 TCs per register) */
3314                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3315                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3316                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3317
3318                 /* Configure flow control refresh threshold value */
3319                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3320                                pf->fc_conf.pause_time / 2);
3321
3322                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3323
3324                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3325                  *depending on configuration
3326                  */
3327                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3328                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3329                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3330                 } else {
3331                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3332                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3333                 }
3334
3335                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3336         }
3337
3338         /* config the water marker both based on the packets and bytes */
3339         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3340                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3341                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3342         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3343                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3344                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3345         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3346                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3347                        << I40E_KILOSHIFT);
3348         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3349                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3350                        << I40E_KILOSHIFT);
3351
3352         I40E_WRITE_FLUSH(hw);
3353
3354         return 0;
3355 }
3356
3357 static int
3358 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3359                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3360 {
3361         PMD_INIT_FUNC_TRACE();
3362
3363         return -ENOSYS;
3364 }
3365
3366 /* Add a MAC address, and update filters */
3367 static int
3368 i40e_macaddr_add(struct rte_eth_dev *dev,
3369                  struct ether_addr *mac_addr,
3370                  __rte_unused uint32_t index,
3371                  uint32_t pool)
3372 {
3373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3374         struct i40e_mac_filter_info mac_filter;
3375         struct i40e_vsi *vsi;
3376         int ret;
3377
3378         /* If VMDQ not enabled or configured, return */
3379         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3380                           !pf->nb_cfg_vmdq_vsi)) {
3381                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3382                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3383                         pool);
3384                 return -ENOTSUP;
3385         }
3386
3387         if (pool > pf->nb_cfg_vmdq_vsi) {
3388                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3389                                 pool, pf->nb_cfg_vmdq_vsi);
3390                 return -EINVAL;
3391         }
3392
3393         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3394         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3395                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3396         else
3397                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3398
3399         if (pool == 0)
3400                 vsi = pf->main_vsi;
3401         else
3402                 vsi = pf->vmdq[pool - 1].vsi;
3403
3404         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3405         if (ret != I40E_SUCCESS) {
3406                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3407                 return -ENODEV;
3408         }
3409         return 0;
3410 }
3411
3412 /* Remove a MAC address, and update filters */
3413 static void
3414 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3415 {
3416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3417         struct i40e_vsi *vsi;
3418         struct rte_eth_dev_data *data = dev->data;
3419         struct ether_addr *macaddr;
3420         int ret;
3421         uint32_t i;
3422         uint64_t pool_sel;
3423
3424         macaddr = &(data->mac_addrs[index]);
3425
3426         pool_sel = dev->data->mac_pool_sel[index];
3427
3428         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3429                 if (pool_sel & (1ULL << i)) {
3430                         if (i == 0)
3431                                 vsi = pf->main_vsi;
3432                         else {
3433                                 /* No VMDQ pool enabled or configured */
3434                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3435                                         (i > pf->nb_cfg_vmdq_vsi)) {
3436                                         PMD_DRV_LOG(ERR,
3437                                                 "No VMDQ pool enabled/configured");
3438                                         return;
3439                                 }
3440                                 vsi = pf->vmdq[i - 1].vsi;
3441                         }
3442                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3443
3444                         if (ret) {
3445                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3446                                 return;
3447                         }
3448                 }
3449         }
3450 }
3451
3452 /* Set perfect match or hash match of MAC and VLAN for a VF */
3453 static int
3454 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3455                  struct rte_eth_mac_filter *filter,
3456                  bool add)
3457 {
3458         struct i40e_hw *hw;
3459         struct i40e_mac_filter_info mac_filter;
3460         struct ether_addr old_mac;
3461         struct ether_addr *new_mac;
3462         struct i40e_pf_vf *vf = NULL;
3463         uint16_t vf_id;
3464         int ret;
3465
3466         if (pf == NULL) {
3467                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3468                 return -EINVAL;
3469         }
3470         hw = I40E_PF_TO_HW(pf);
3471
3472         if (filter == NULL) {
3473                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3474                 return -EINVAL;
3475         }
3476
3477         new_mac = &filter->mac_addr;
3478
3479         if (is_zero_ether_addr(new_mac)) {
3480                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3481                 return -EINVAL;
3482         }
3483
3484         vf_id = filter->dst_id;
3485
3486         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3487                 PMD_DRV_LOG(ERR, "Invalid argument.");
3488                 return -EINVAL;
3489         }
3490         vf = &pf->vfs[vf_id];
3491
3492         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3493                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3494                 return -EINVAL;
3495         }
3496
3497         if (add) {
3498                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3499                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3500                                 ETHER_ADDR_LEN);
3501                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3502                                  ETHER_ADDR_LEN);
3503
3504                 mac_filter.filter_type = filter->filter_type;
3505                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3506                 if (ret != I40E_SUCCESS) {
3507                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3508                         return -1;
3509                 }
3510                 ether_addr_copy(new_mac, &pf->dev_addr);
3511         } else {
3512                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3513                                 ETHER_ADDR_LEN);
3514                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3515                 if (ret != I40E_SUCCESS) {
3516                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3517                         return -1;
3518                 }
3519
3520                 /* Clear device address as it has been removed */
3521                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3522                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3523         }
3524
3525         return 0;
3526 }
3527
3528 /* MAC filter handle */
3529 static int
3530 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3531                 void *arg)
3532 {
3533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534         struct rte_eth_mac_filter *filter;
3535         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3536         int ret = I40E_NOT_SUPPORTED;
3537
3538         filter = (struct rte_eth_mac_filter *)(arg);
3539
3540         switch (filter_op) {
3541         case RTE_ETH_FILTER_NOP:
3542                 ret = I40E_SUCCESS;
3543                 break;
3544         case RTE_ETH_FILTER_ADD:
3545                 i40e_pf_disable_irq0(hw);
3546                 if (filter->is_vf)
3547                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3548                 i40e_pf_enable_irq0(hw);
3549                 break;
3550         case RTE_ETH_FILTER_DELETE:
3551                 i40e_pf_disable_irq0(hw);
3552                 if (filter->is_vf)
3553                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3554                 i40e_pf_enable_irq0(hw);
3555                 break;
3556         default:
3557                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3558                 ret = I40E_ERR_PARAM;
3559                 break;
3560         }
3561
3562         return ret;
3563 }
3564
3565 static int
3566 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3567 {
3568         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3570         int ret;
3571
3572         if (!lut)
3573                 return -EINVAL;
3574
3575         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3576                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3577                                           lut, lut_size);
3578                 if (ret) {
3579                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3580                         return ret;
3581                 }
3582         } else {
3583                 uint32_t *lut_dw = (uint32_t *)lut;
3584                 uint16_t i, lut_size_dw = lut_size / 4;
3585
3586                 for (i = 0; i < lut_size_dw; i++)
3587                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3588         }
3589
3590         return 0;
3591 }
3592
3593 static int
3594 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3595 {
3596         struct i40e_pf *pf;
3597         struct i40e_hw *hw;
3598         int ret;
3599
3600         if (!vsi || !lut)
3601                 return -EINVAL;
3602
3603         pf = I40E_VSI_TO_PF(vsi);
3604         hw = I40E_VSI_TO_HW(vsi);
3605
3606         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3607                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3608                                           lut, lut_size);
3609                 if (ret) {
3610                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3611                         return ret;
3612                 }
3613         } else {
3614                 uint32_t *lut_dw = (uint32_t *)lut;
3615                 uint16_t i, lut_size_dw = lut_size / 4;
3616
3617                 for (i = 0; i < lut_size_dw; i++)
3618                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3619                 I40E_WRITE_FLUSH(hw);
3620         }
3621
3622         return 0;
3623 }
3624
3625 static int
3626 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3627                          struct rte_eth_rss_reta_entry64 *reta_conf,
3628                          uint16_t reta_size)
3629 {
3630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3631         uint16_t i, lut_size = pf->hash_lut_size;
3632         uint16_t idx, shift;
3633         uint8_t *lut;
3634         int ret;
3635
3636         if (reta_size != lut_size ||
3637                 reta_size > ETH_RSS_RETA_SIZE_512) {
3638                 PMD_DRV_LOG(ERR,
3639                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3640                         reta_size, lut_size);
3641                 return -EINVAL;
3642         }
3643
3644         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3645         if (!lut) {
3646                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3647                 return -ENOMEM;
3648         }
3649         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3650         if (ret)
3651                 goto out;
3652         for (i = 0; i < reta_size; i++) {
3653                 idx = i / RTE_RETA_GROUP_SIZE;
3654                 shift = i % RTE_RETA_GROUP_SIZE;
3655                 if (reta_conf[idx].mask & (1ULL << shift))
3656                         lut[i] = reta_conf[idx].reta[shift];
3657         }
3658         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3659
3660 out:
3661         rte_free(lut);
3662
3663         return ret;
3664 }
3665
3666 static int
3667 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3668                         struct rte_eth_rss_reta_entry64 *reta_conf,
3669                         uint16_t reta_size)
3670 {
3671         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3672         uint16_t i, lut_size = pf->hash_lut_size;
3673         uint16_t idx, shift;
3674         uint8_t *lut;
3675         int ret;
3676
3677         if (reta_size != lut_size ||
3678                 reta_size > ETH_RSS_RETA_SIZE_512) {
3679                 PMD_DRV_LOG(ERR,
3680                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3681                         reta_size, lut_size);
3682                 return -EINVAL;
3683         }
3684
3685         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3686         if (!lut) {
3687                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3688                 return -ENOMEM;
3689         }
3690
3691         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3692         if (ret)
3693                 goto out;
3694         for (i = 0; i < reta_size; i++) {
3695                 idx = i / RTE_RETA_GROUP_SIZE;
3696                 shift = i % RTE_RETA_GROUP_SIZE;
3697                 if (reta_conf[idx].mask & (1ULL << shift))
3698                         reta_conf[idx].reta[shift] = lut[i];
3699         }
3700
3701 out:
3702         rte_free(lut);
3703
3704         return ret;
3705 }
3706
3707 /**
3708  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3709  * @hw:   pointer to the HW structure
3710  * @mem:  pointer to mem struct to fill out
3711  * @size: size of memory requested
3712  * @alignment: what to align the allocation to
3713  **/
3714 enum i40e_status_code
3715 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3716                         struct i40e_dma_mem *mem,
3717                         u64 size,
3718                         u32 alignment)
3719 {
3720         const struct rte_memzone *mz = NULL;
3721         char z_name[RTE_MEMZONE_NAMESIZE];
3722
3723         if (!mem)
3724                 return I40E_ERR_PARAM;
3725
3726         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3727         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3728                                          alignment, RTE_PGSIZE_2M);
3729         if (!mz)
3730                 return I40E_ERR_NO_MEMORY;
3731
3732         mem->size = size;
3733         mem->va = mz->addr;
3734         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3735         mem->zone = (const void *)mz;
3736         PMD_DRV_LOG(DEBUG,
3737                 "memzone %s allocated with physical address: %"PRIu64,
3738                 mz->name, mem->pa);
3739
3740         return I40E_SUCCESS;
3741 }
3742
3743 /**
3744  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3745  * @hw:   pointer to the HW structure
3746  * @mem:  ptr to mem struct to free
3747  **/
3748 enum i40e_status_code
3749 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3750                     struct i40e_dma_mem *mem)
3751 {
3752         if (!mem)
3753                 return I40E_ERR_PARAM;
3754
3755         PMD_DRV_LOG(DEBUG,
3756                 "memzone %s to be freed with physical address: %"PRIu64,
3757                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3758         rte_memzone_free((const struct rte_memzone *)mem->zone);
3759         mem->zone = NULL;
3760         mem->va = NULL;
3761         mem->pa = (u64)0;
3762
3763         return I40E_SUCCESS;
3764 }
3765
3766 /**
3767  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3768  * @hw:   pointer to the HW structure
3769  * @mem:  pointer to mem struct to fill out
3770  * @size: size of memory requested
3771  **/
3772 enum i40e_status_code
3773 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3774                          struct i40e_virt_mem *mem,
3775                          u32 size)
3776 {
3777         if (!mem)
3778                 return I40E_ERR_PARAM;
3779
3780         mem->size = size;
3781         mem->va = rte_zmalloc("i40e", size, 0);
3782
3783         if (mem->va)
3784                 return I40E_SUCCESS;
3785         else
3786                 return I40E_ERR_NO_MEMORY;
3787 }
3788
3789 /**
3790  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3791  * @hw:   pointer to the HW structure
3792  * @mem:  pointer to mem struct to free
3793  **/
3794 enum i40e_status_code
3795 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3796                      struct i40e_virt_mem *mem)
3797 {
3798         if (!mem)
3799                 return I40E_ERR_PARAM;
3800
3801         rte_free(mem->va);
3802         mem->va = NULL;
3803
3804         return I40E_SUCCESS;
3805 }
3806
3807 void
3808 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3809 {
3810         rte_spinlock_init(&sp->spinlock);
3811 }
3812
3813 void
3814 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3815 {
3816         rte_spinlock_lock(&sp->spinlock);
3817 }
3818
3819 void
3820 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3821 {
3822         rte_spinlock_unlock(&sp->spinlock);
3823 }
3824
3825 void
3826 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3827 {
3828         return;
3829 }
3830
3831 /**
3832  * Get the hardware capabilities, which will be parsed
3833  * and saved into struct i40e_hw.
3834  */
3835 static int
3836 i40e_get_cap(struct i40e_hw *hw)
3837 {
3838         struct i40e_aqc_list_capabilities_element_resp *buf;
3839         uint16_t len, size = 0;
3840         int ret;
3841
3842         /* Calculate a huge enough buff for saving response data temporarily */
3843         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3844                                                 I40E_MAX_CAP_ELE_NUM;
3845         buf = rte_zmalloc("i40e", len, 0);
3846         if (!buf) {
3847                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3848                 return I40E_ERR_NO_MEMORY;
3849         }
3850
3851         /* Get, parse the capabilities and save it to hw */
3852         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3853                         i40e_aqc_opc_list_func_capabilities, NULL);
3854         if (ret != I40E_SUCCESS)
3855                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3856
3857         /* Free the temporary buffer after being used */
3858         rte_free(buf);
3859
3860         return ret;
3861 }
3862
3863 static int
3864 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3865 {
3866         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3867         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3868         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3869         uint16_t qp_count = 0, vsi_count = 0;
3870
3871         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3872                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3873                 return -EINVAL;
3874         }
3875         /* Add the parameter init for LFC */
3876         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3877         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3878         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3879
3880         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3881         pf->max_num_vsi = hw->func_caps.num_vsis;
3882         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3883         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3884         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3885
3886         /* FDir queue/VSI allocation */
3887         pf->fdir_qp_offset = 0;
3888         if (hw->func_caps.fd) {
3889                 pf->flags |= I40E_FLAG_FDIR;
3890                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3891         } else {
3892                 pf->fdir_nb_qps = 0;
3893         }
3894         qp_count += pf->fdir_nb_qps;
3895         vsi_count += 1;
3896
3897         /* LAN queue/VSI allocation */
3898         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3899         if (!hw->func_caps.rss) {
3900                 pf->lan_nb_qps = 1;
3901         } else {
3902                 pf->flags |= I40E_FLAG_RSS;
3903                 if (hw->mac.type == I40E_MAC_X722)
3904                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3905                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3906         }
3907         qp_count += pf->lan_nb_qps;
3908         vsi_count += 1;
3909
3910         /* VF queue/VSI allocation */
3911         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3912         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3913                 pf->flags |= I40E_FLAG_SRIOV;
3914                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3915                 pf->vf_num = pci_dev->max_vfs;
3916                 PMD_DRV_LOG(DEBUG,
3917                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3918                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3919         } else {
3920                 pf->vf_nb_qps = 0;
3921                 pf->vf_num = 0;
3922         }
3923         qp_count += pf->vf_nb_qps * pf->vf_num;
3924         vsi_count += pf->vf_num;
3925
3926         /* VMDq queue/VSI allocation */
3927         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3928         pf->vmdq_nb_qps = 0;
3929         pf->max_nb_vmdq_vsi = 0;
3930         if (hw->func_caps.vmdq) {
3931                 if (qp_count < hw->func_caps.num_tx_qp &&
3932                         vsi_count < hw->func_caps.num_vsis) {
3933                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3934                                 qp_count) / pf->vmdq_nb_qp_max;
3935
3936                         /* Limit the maximum number of VMDq vsi to the maximum
3937                          * ethdev can support
3938                          */
3939                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3940                                 hw->func_caps.num_vsis - vsi_count);
3941                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3942                                 ETH_64_POOLS);
3943                         if (pf->max_nb_vmdq_vsi) {
3944                                 pf->flags |= I40E_FLAG_VMDQ;
3945                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3946                                 PMD_DRV_LOG(DEBUG,
3947                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3948                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3949                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3950                         } else {
3951                                 PMD_DRV_LOG(INFO,
3952                                         "No enough queues left for VMDq");
3953                         }
3954                 } else {
3955                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3956                 }
3957         }
3958         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3959         vsi_count += pf->max_nb_vmdq_vsi;
3960
3961         if (hw->func_caps.dcb)
3962                 pf->flags |= I40E_FLAG_DCB;
3963
3964         if (qp_count > hw->func_caps.num_tx_qp) {
3965                 PMD_DRV_LOG(ERR,
3966                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3967                         qp_count, hw->func_caps.num_tx_qp);
3968                 return -EINVAL;
3969         }
3970         if (vsi_count > hw->func_caps.num_vsis) {
3971                 PMD_DRV_LOG(ERR,
3972                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3973                         vsi_count, hw->func_caps.num_vsis);
3974                 return -EINVAL;
3975         }
3976
3977         return 0;
3978 }
3979
3980 static int
3981 i40e_pf_get_switch_config(struct i40e_pf *pf)
3982 {
3983         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3984         struct i40e_aqc_get_switch_config_resp *switch_config;
3985         struct i40e_aqc_switch_config_element_resp *element;
3986         uint16_t start_seid = 0, num_reported;
3987         int ret;
3988
3989         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3990                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3991         if (!switch_config) {
3992                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3993                 return -ENOMEM;
3994         }
3995
3996         /* Get the switch configurations */
3997         ret = i40e_aq_get_switch_config(hw, switch_config,
3998                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3999         if (ret != I40E_SUCCESS) {
4000                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4001                 goto fail;
4002         }
4003         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4004         if (num_reported != 1) { /* The number should be 1 */
4005                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4006                 goto fail;
4007         }
4008
4009         /* Parse the switch configuration elements */
4010         element = &(switch_config->element[0]);
4011         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4012                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4013                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4014         } else
4015                 PMD_DRV_LOG(INFO, "Unknown element type");
4016
4017 fail:
4018         rte_free(switch_config);
4019
4020         return ret;
4021 }
4022
4023 static int
4024 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4025                         uint32_t num)
4026 {
4027         struct pool_entry *entry;
4028
4029         if (pool == NULL || num == 0)
4030                 return -EINVAL;
4031
4032         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4033         if (entry == NULL) {
4034                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4035                 return -ENOMEM;
4036         }
4037
4038         /* queue heap initialize */
4039         pool->num_free = num;
4040         pool->num_alloc = 0;
4041         pool->base = base;
4042         LIST_INIT(&pool->alloc_list);
4043         LIST_INIT(&pool->free_list);
4044
4045         /* Initialize element  */
4046         entry->base = 0;
4047         entry->len = num;
4048
4049         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4050         return 0;
4051 }
4052
4053 static void
4054 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4055 {
4056         struct pool_entry *entry, *next_entry;
4057
4058         if (pool == NULL)
4059                 return;
4060
4061         for (entry = LIST_FIRST(&pool->alloc_list);
4062                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4063                         entry = next_entry) {
4064                 LIST_REMOVE(entry, next);
4065                 rte_free(entry);
4066         }
4067
4068         for (entry = LIST_FIRST(&pool->free_list);
4069                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4070                         entry = next_entry) {
4071                 LIST_REMOVE(entry, next);
4072                 rte_free(entry);
4073         }
4074
4075         pool->num_free = 0;
4076         pool->num_alloc = 0;
4077         pool->base = 0;
4078         LIST_INIT(&pool->alloc_list);
4079         LIST_INIT(&pool->free_list);
4080 }
4081
4082 static int
4083 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4084                        uint32_t base)
4085 {
4086         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4087         uint32_t pool_offset;
4088         int insert;
4089
4090         if (pool == NULL) {
4091                 PMD_DRV_LOG(ERR, "Invalid parameter");
4092                 return -EINVAL;
4093         }
4094
4095         pool_offset = base - pool->base;
4096         /* Lookup in alloc list */
4097         LIST_FOREACH(entry, &pool->alloc_list, next) {
4098                 if (entry->base == pool_offset) {
4099                         valid_entry = entry;
4100                         LIST_REMOVE(entry, next);
4101                         break;
4102                 }
4103         }
4104
4105         /* Not find, return */
4106         if (valid_entry == NULL) {
4107                 PMD_DRV_LOG(ERR, "Failed to find entry");
4108                 return -EINVAL;
4109         }
4110
4111         /**
4112          * Found it, move it to free list  and try to merge.
4113          * In order to make merge easier, always sort it by qbase.
4114          * Find adjacent prev and last entries.
4115          */
4116         prev = next = NULL;
4117         LIST_FOREACH(entry, &pool->free_list, next) {
4118                 if (entry->base > valid_entry->base) {
4119                         next = entry;
4120                         break;
4121                 }
4122                 prev = entry;
4123         }
4124
4125         insert = 0;
4126         /* Try to merge with next one*/
4127         if (next != NULL) {
4128                 /* Merge with next one */
4129                 if (valid_entry->base + valid_entry->len == next->base) {
4130                         next->base = valid_entry->base;
4131                         next->len += valid_entry->len;
4132                         rte_free(valid_entry);
4133                         valid_entry = next;
4134                         insert = 1;
4135                 }
4136         }
4137
4138         if (prev != NULL) {
4139                 /* Merge with previous one */
4140                 if (prev->base + prev->len == valid_entry->base) {
4141                         prev->len += valid_entry->len;
4142                         /* If it merge with next one, remove next node */
4143                         if (insert == 1) {
4144                                 LIST_REMOVE(valid_entry, next);
4145                                 rte_free(valid_entry);
4146                         } else {
4147                                 rte_free(valid_entry);
4148                                 insert = 1;
4149                         }
4150                 }
4151         }
4152
4153         /* Not find any entry to merge, insert */
4154         if (insert == 0) {
4155                 if (prev != NULL)
4156                         LIST_INSERT_AFTER(prev, valid_entry, next);
4157                 else if (next != NULL)
4158                         LIST_INSERT_BEFORE(next, valid_entry, next);
4159                 else /* It's empty list, insert to head */
4160                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4161         }
4162
4163         pool->num_free += valid_entry->len;
4164         pool->num_alloc -= valid_entry->len;
4165
4166         return 0;
4167 }
4168
4169 static int
4170 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4171                        uint16_t num)
4172 {
4173         struct pool_entry *entry, *valid_entry;
4174
4175         if (pool == NULL || num == 0) {
4176                 PMD_DRV_LOG(ERR, "Invalid parameter");
4177                 return -EINVAL;
4178         }
4179
4180         if (pool->num_free < num) {
4181                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4182                             num, pool->num_free);
4183                 return -ENOMEM;
4184         }
4185
4186         valid_entry = NULL;
4187         /* Lookup  in free list and find most fit one */
4188         LIST_FOREACH(entry, &pool->free_list, next) {
4189                 if (entry->len >= num) {
4190                         /* Find best one */
4191                         if (entry->len == num) {
4192                                 valid_entry = entry;
4193                                 break;
4194                         }
4195                         if (valid_entry == NULL || valid_entry->len > entry->len)
4196                                 valid_entry = entry;
4197                 }
4198         }
4199
4200         /* Not find one to satisfy the request, return */
4201         if (valid_entry == NULL) {
4202                 PMD_DRV_LOG(ERR, "No valid entry found");
4203                 return -ENOMEM;
4204         }
4205         /**
4206          * The entry have equal queue number as requested,
4207          * remove it from alloc_list.
4208          */
4209         if (valid_entry->len == num) {
4210                 LIST_REMOVE(valid_entry, next);
4211         } else {
4212                 /**
4213                  * The entry have more numbers than requested,
4214                  * create a new entry for alloc_list and minus its
4215                  * queue base and number in free_list.
4216                  */
4217                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4218                 if (entry == NULL) {
4219                         PMD_DRV_LOG(ERR,
4220                                 "Failed to allocate memory for resource pool");
4221                         return -ENOMEM;
4222                 }
4223                 entry->base = valid_entry->base;
4224                 entry->len = num;
4225                 valid_entry->base += num;
4226                 valid_entry->len -= num;
4227                 valid_entry = entry;
4228         }
4229
4230         /* Insert it into alloc list, not sorted */
4231         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4232
4233         pool->num_free -= valid_entry->len;
4234         pool->num_alloc += valid_entry->len;
4235
4236         return valid_entry->base + pool->base;
4237 }
4238
4239 /**
4240  * bitmap_is_subset - Check whether src2 is subset of src1
4241  **/
4242 static inline int
4243 bitmap_is_subset(uint8_t src1, uint8_t src2)
4244 {
4245         return !((src1 ^ src2) & src2);
4246 }
4247
4248 static enum i40e_status_code
4249 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4250 {
4251         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4252
4253         /* If DCB is not supported, only default TC is supported */
4254         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4255                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4256                 return I40E_NOT_SUPPORTED;
4257         }
4258
4259         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4260                 PMD_DRV_LOG(ERR,
4261                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4262                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4263                 return I40E_NOT_SUPPORTED;
4264         }
4265         return I40E_SUCCESS;
4266 }
4267
4268 int
4269 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4270                                 struct i40e_vsi_vlan_pvid_info *info)
4271 {
4272         struct i40e_hw *hw;
4273         struct i40e_vsi_context ctxt;
4274         uint8_t vlan_flags = 0;
4275         int ret;
4276
4277         if (vsi == NULL || info == NULL) {
4278                 PMD_DRV_LOG(ERR, "invalid parameters");
4279                 return I40E_ERR_PARAM;
4280         }
4281
4282         if (info->on) {
4283                 vsi->info.pvid = info->config.pvid;
4284                 /**
4285                  * If insert pvid is enabled, only tagged pkts are
4286                  * allowed to be sent out.
4287                  */
4288                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4289                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4290         } else {
4291                 vsi->info.pvid = 0;
4292                 if (info->config.reject.tagged == 0)
4293                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4294
4295                 if (info->config.reject.untagged == 0)
4296                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4297         }
4298         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4299                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4300         vsi->info.port_vlan_flags |= vlan_flags;
4301         vsi->info.valid_sections =
4302                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4303         memset(&ctxt, 0, sizeof(ctxt));
4304         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4305         ctxt.seid = vsi->seid;
4306
4307         hw = I40E_VSI_TO_HW(vsi);
4308         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4309         if (ret != I40E_SUCCESS)
4310                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4311
4312         return ret;
4313 }
4314
4315 static int
4316 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4317 {
4318         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4319         int i, ret;
4320         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4321
4322         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4323         if (ret != I40E_SUCCESS)
4324                 return ret;
4325
4326         if (!vsi->seid) {
4327                 PMD_DRV_LOG(ERR, "seid not valid");
4328                 return -EINVAL;
4329         }
4330
4331         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4332         tc_bw_data.tc_valid_bits = enabled_tcmap;
4333         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4334                 tc_bw_data.tc_bw_credits[i] =
4335                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4336
4337         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4338         if (ret != I40E_SUCCESS) {
4339                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4340                 return ret;
4341         }
4342
4343         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4344                                         sizeof(vsi->info.qs_handle));
4345         return I40E_SUCCESS;
4346 }
4347
4348 static enum i40e_status_code
4349 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4350                                  struct i40e_aqc_vsi_properties_data *info,
4351                                  uint8_t enabled_tcmap)
4352 {
4353         enum i40e_status_code ret;
4354         int i, total_tc = 0;
4355         uint16_t qpnum_per_tc, bsf, qp_idx;
4356
4357         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4358         if (ret != I40E_SUCCESS)
4359                 return ret;
4360
4361         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4362                 if (enabled_tcmap & (1 << i))
4363                         total_tc++;
4364         if (total_tc == 0)
4365                 total_tc = 1;
4366         vsi->enabled_tc = enabled_tcmap;
4367
4368         /* Number of queues per enabled TC */
4369         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4370         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4371         bsf = rte_bsf32(qpnum_per_tc);
4372
4373         /* Adjust the queue number to actual queues that can be applied */
4374         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4375                 vsi->nb_qps = qpnum_per_tc * total_tc;
4376
4377         /**
4378          * Configure TC and queue mapping parameters, for enabled TC,
4379          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4380          * default queue will serve it.
4381          */
4382         qp_idx = 0;
4383         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4384                 if (vsi->enabled_tc & (1 << i)) {
4385                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4386                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4387                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4388                         qp_idx += qpnum_per_tc;
4389                 } else
4390                         info->tc_mapping[i] = 0;
4391         }
4392
4393         /* Associate queue number with VSI */
4394         if (vsi->type == I40E_VSI_SRIOV) {
4395                 info->mapping_flags |=
4396                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4397                 for (i = 0; i < vsi->nb_qps; i++)
4398                         info->queue_mapping[i] =
4399                                 rte_cpu_to_le_16(vsi->base_queue + i);
4400         } else {
4401                 info->mapping_flags |=
4402                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4403                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4404         }
4405         info->valid_sections |=
4406                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4407
4408         return I40E_SUCCESS;
4409 }
4410
4411 static int
4412 i40e_veb_release(struct i40e_veb *veb)
4413 {
4414         struct i40e_vsi *vsi;
4415         struct i40e_hw *hw;
4416
4417         if (veb == NULL)
4418                 return -EINVAL;
4419
4420         if (!TAILQ_EMPTY(&veb->head)) {
4421                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4422                 return -EACCES;
4423         }
4424         /* associate_vsi field is NULL for floating VEB */
4425         if (veb->associate_vsi != NULL) {
4426                 vsi = veb->associate_vsi;
4427                 hw = I40E_VSI_TO_HW(vsi);
4428
4429                 vsi->uplink_seid = veb->uplink_seid;
4430                 vsi->veb = NULL;
4431         } else {
4432                 veb->associate_pf->main_vsi->floating_veb = NULL;
4433                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4434         }
4435
4436         i40e_aq_delete_element(hw, veb->seid, NULL);
4437         rte_free(veb);
4438         return I40E_SUCCESS;
4439 }
4440
4441 /* Setup a veb */
4442 static struct i40e_veb *
4443 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4444 {
4445         struct i40e_veb *veb;
4446         int ret;
4447         struct i40e_hw *hw;
4448
4449         if (pf == NULL) {
4450                 PMD_DRV_LOG(ERR,
4451                             "veb setup failed, associated PF shouldn't null");
4452                 return NULL;
4453         }
4454         hw = I40E_PF_TO_HW(pf);
4455
4456         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4457         if (!veb) {
4458                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4459                 goto fail;
4460         }
4461
4462         veb->associate_vsi = vsi;
4463         veb->associate_pf = pf;
4464         TAILQ_INIT(&veb->head);
4465         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4466
4467         /* create floating veb if vsi is NULL */
4468         if (vsi != NULL) {
4469                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4470                                       I40E_DEFAULT_TCMAP, false,
4471                                       &veb->seid, false, NULL);
4472         } else {
4473                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4474                                       true, &veb->seid, false, NULL);
4475         }
4476
4477         if (ret != I40E_SUCCESS) {
4478                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4479                             hw->aq.asq_last_status);
4480                 goto fail;
4481         }
4482         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4483
4484         /* get statistics index */
4485         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4486                                 &veb->stats_idx, NULL, NULL, NULL);
4487         if (ret != I40E_SUCCESS) {
4488                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4489                             hw->aq.asq_last_status);
4490                 goto fail;
4491         }
4492         /* Get VEB bandwidth, to be implemented */
4493         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4494         if (vsi)
4495                 vsi->uplink_seid = veb->seid;
4496
4497         return veb;
4498 fail:
4499         rte_free(veb);
4500         return NULL;
4501 }
4502
4503 int
4504 i40e_vsi_release(struct i40e_vsi *vsi)
4505 {
4506         struct i40e_pf *pf;
4507         struct i40e_hw *hw;
4508         struct i40e_vsi_list *vsi_list;
4509         void *temp;
4510         int ret;
4511         struct i40e_mac_filter *f;
4512         uint16_t user_param;
4513
4514         if (!vsi)
4515                 return I40E_SUCCESS;
4516
4517         if (!vsi->adapter)
4518                 return -EFAULT;
4519
4520         user_param = vsi->user_param;
4521
4522         pf = I40E_VSI_TO_PF(vsi);
4523         hw = I40E_VSI_TO_HW(vsi);
4524
4525         /* VSI has child to attach, release child first */
4526         if (vsi->veb) {
4527                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4528                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4529                                 return -1;
4530                 }
4531                 i40e_veb_release(vsi->veb);
4532         }
4533
4534         if (vsi->floating_veb) {
4535                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4536                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4537                                 return -1;
4538                 }
4539         }
4540
4541         /* Remove all macvlan filters of the VSI */
4542         i40e_vsi_remove_all_macvlan_filter(vsi);
4543         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4544                 rte_free(f);
4545
4546         if (vsi->type != I40E_VSI_MAIN &&
4547             ((vsi->type != I40E_VSI_SRIOV) ||
4548             !pf->floating_veb_list[user_param])) {
4549                 /* Remove vsi from parent's sibling list */
4550                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4551                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4552                         return I40E_ERR_PARAM;
4553                 }
4554                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4555                                 &vsi->sib_vsi_list, list);
4556
4557                 /* Remove all switch element of the VSI */
4558                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4559                 if (ret != I40E_SUCCESS)
4560                         PMD_DRV_LOG(ERR, "Failed to delete element");
4561         }
4562
4563         if ((vsi->type == I40E_VSI_SRIOV) &&
4564             pf->floating_veb_list[user_param]) {
4565                 /* Remove vsi from parent's sibling list */
4566                 if (vsi->parent_vsi == NULL ||
4567                     vsi->parent_vsi->floating_veb == NULL) {
4568                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4569                         return I40E_ERR_PARAM;
4570                 }
4571                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4572                              &vsi->sib_vsi_list, list);
4573
4574                 /* Remove all switch element of the VSI */
4575                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4576                 if (ret != I40E_SUCCESS)
4577                         PMD_DRV_LOG(ERR, "Failed to delete element");
4578         }
4579
4580         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4581
4582         if (vsi->type != I40E_VSI_SRIOV)
4583                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4584         rte_free(vsi);
4585
4586         return I40E_SUCCESS;
4587 }
4588
4589 static int
4590 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4591 {
4592         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4593         struct i40e_aqc_remove_macvlan_element_data def_filter;
4594         struct i40e_mac_filter_info filter;
4595         int ret;
4596
4597         if (vsi->type != I40E_VSI_MAIN)
4598                 return I40E_ERR_CONFIG;
4599         memset(&def_filter, 0, sizeof(def_filter));
4600         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4601                                         ETH_ADDR_LEN);
4602         def_filter.vlan_tag = 0;
4603         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4604                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4605         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4606         if (ret != I40E_SUCCESS) {
4607                 struct i40e_mac_filter *f;
4608                 struct ether_addr *mac;
4609
4610                 PMD_DRV_LOG(DEBUG,
4611                             "Cannot remove the default macvlan filter");
4612                 /* It needs to add the permanent mac into mac list */
4613                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4614                 if (f == NULL) {
4615                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4616                         return I40E_ERR_NO_MEMORY;
4617                 }
4618                 mac = &f->mac_info.mac_addr;
4619                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4620                                 ETH_ADDR_LEN);
4621                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4622                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4623                 vsi->mac_num++;
4624
4625                 return ret;
4626         }
4627         (void)rte_memcpy(&filter.mac_addr,
4628                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4629         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4630         return i40e_vsi_add_mac(vsi, &filter);
4631 }
4632
4633 /*
4634  * i40e_vsi_get_bw_config - Query VSI BW Information
4635  * @vsi: the VSI to be queried
4636  *
4637  * Returns 0 on success, negative value on failure
4638  */
4639 static enum i40e_status_code
4640 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4641 {
4642         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4643         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4644         struct i40e_hw *hw = &vsi->adapter->hw;
4645         i40e_status ret;
4646         int i;
4647         uint32_t bw_max;
4648
4649         memset(&bw_config, 0, sizeof(bw_config));
4650         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4651         if (ret != I40E_SUCCESS) {
4652                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4653                             hw->aq.asq_last_status);
4654                 return ret;
4655         }
4656
4657         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4658         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4659                                         &ets_sla_config, NULL);
4660         if (ret != I40E_SUCCESS) {
4661                 PMD_DRV_LOG(ERR,
4662                         "VSI failed to get TC bandwdith configuration %u",
4663                         hw->aq.asq_last_status);
4664                 return ret;
4665         }
4666
4667         /* store and print out BW info */
4668         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4669         vsi->bw_info.bw_max = bw_config.max_bw;
4670         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4671         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4672         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4673                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4674                      I40E_16_BIT_WIDTH);
4675         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4676                 vsi->bw_info.bw_ets_share_credits[i] =
4677                                 ets_sla_config.share_credits[i];
4678                 vsi->bw_info.bw_ets_credits[i] =
4679                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4680                 /* 4 bits per TC, 4th bit is reserved */
4681                 vsi->bw_info.bw_ets_max[i] =
4682                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4683                                   RTE_LEN2MASK(3, uint8_t));
4684                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4685                             vsi->bw_info.bw_ets_share_credits[i]);
4686                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4687                             vsi->bw_info.bw_ets_credits[i]);
4688                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4689                             vsi->bw_info.bw_ets_max[i]);
4690         }
4691
4692         return I40E_SUCCESS;
4693 }
4694
4695 /* i40e_enable_pf_lb
4696  * @pf: pointer to the pf structure
4697  *
4698  * allow loopback on pf
4699  */
4700 static inline void
4701 i40e_enable_pf_lb(struct i40e_pf *pf)
4702 {
4703         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4704         struct i40e_vsi_context ctxt;
4705         int ret;
4706
4707         /* Use the FW API if FW >= v5.0 */
4708         if (hw->aq.fw_maj_ver < 5) {
4709                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4710                 return;
4711         }
4712
4713         memset(&ctxt, 0, sizeof(ctxt));
4714         ctxt.seid = pf->main_vsi_seid;
4715         ctxt.pf_num = hw->pf_id;
4716         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4717         if (ret) {
4718                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4719                             ret, hw->aq.asq_last_status);
4720                 return;
4721         }
4722         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4723         ctxt.info.valid_sections =
4724                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4725         ctxt.info.switch_id |=
4726                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4727
4728         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4729         if (ret)
4730                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4731                             hw->aq.asq_last_status);
4732 }
4733
4734 /* Setup a VSI */
4735 struct i40e_vsi *
4736 i40e_vsi_setup(struct i40e_pf *pf,
4737                enum i40e_vsi_type type,
4738                struct i40e_vsi *uplink_vsi,
4739                uint16_t user_param)
4740 {
4741         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4742         struct i40e_vsi *vsi;
4743         struct i40e_mac_filter_info filter;
4744         int ret;
4745         struct i40e_vsi_context ctxt;
4746         struct ether_addr broadcast =
4747                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4748
4749         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4750             uplink_vsi == NULL) {
4751                 PMD_DRV_LOG(ERR,
4752                         "VSI setup failed, VSI link shouldn't be NULL");
4753                 return NULL;
4754         }
4755
4756         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4757                 PMD_DRV_LOG(ERR,
4758                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4759                 return NULL;
4760         }
4761
4762         /* two situations
4763          * 1.type is not MAIN and uplink vsi is not NULL
4764          * If uplink vsi didn't setup VEB, create one first under veb field
4765          * 2.type is SRIOV and the uplink is NULL
4766          * If floating VEB is NULL, create one veb under floating veb field
4767          */
4768
4769         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4770             uplink_vsi->veb == NULL) {
4771                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4772
4773                 if (uplink_vsi->veb == NULL) {
4774                         PMD_DRV_LOG(ERR, "VEB setup failed");
4775                         return NULL;
4776                 }
4777                 /* set ALLOWLOOPBACk on pf, when veb is created */
4778                 i40e_enable_pf_lb(pf);
4779         }
4780
4781         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4782             pf->main_vsi->floating_veb == NULL) {
4783                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4784
4785                 if (pf->main_vsi->floating_veb == NULL) {
4786                         PMD_DRV_LOG(ERR, "VEB setup failed");
4787                         return NULL;
4788                 }
4789         }
4790
4791         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4792         if (!vsi) {
4793                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4794                 return NULL;
4795         }
4796         TAILQ_INIT(&vsi->mac_list);
4797         vsi->type = type;
4798         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4799         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4800         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4801         vsi->user_param = user_param;
4802         vsi->vlan_anti_spoof_on = 0;
4803         vsi->vlan_filter_on = 0;
4804         /* Allocate queues */
4805         switch (vsi->type) {
4806         case I40E_VSI_MAIN  :
4807                 vsi->nb_qps = pf->lan_nb_qps;
4808                 break;
4809         case I40E_VSI_SRIOV :
4810                 vsi->nb_qps = pf->vf_nb_qps;
4811                 break;
4812         case I40E_VSI_VMDQ2:
4813                 vsi->nb_qps = pf->vmdq_nb_qps;
4814                 break;
4815         case I40E_VSI_FDIR:
4816                 vsi->nb_qps = pf->fdir_nb_qps;
4817                 break;
4818         default:
4819                 goto fail_mem;
4820         }
4821         /*
4822          * The filter status descriptor is reported in rx queue 0,
4823          * while the tx queue for fdir filter programming has no
4824          * such constraints, can be non-zero queues.
4825          * To simplify it, choose FDIR vsi use queue 0 pair.
4826          * To make sure it will use queue 0 pair, queue allocation
4827          * need be done before this function is called
4828          */
4829         if (type != I40E_VSI_FDIR) {
4830                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4831                         if (ret < 0) {
4832                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4833                                                 vsi->seid, ret);
4834                                 goto fail_mem;
4835                         }
4836                         vsi->base_queue = ret;
4837         } else
4838                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4839
4840         /* VF has MSIX interrupt in VF range, don't allocate here */
4841         if (type == I40E_VSI_MAIN) {
4842                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4843                                           RTE_MIN(vsi->nb_qps,
4844                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4845                 if (ret < 0) {
4846                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4847                                     vsi->seid, ret);
4848                         goto fail_queue_alloc;
4849                 }
4850                 vsi->msix_intr = ret;
4851                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4852         } else if (type != I40E_VSI_SRIOV) {
4853                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4854                 if (ret < 0) {
4855                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4856                         goto fail_queue_alloc;
4857                 }
4858                 vsi->msix_intr = ret;
4859                 vsi->nb_msix = 1;
4860         } else {
4861                 vsi->msix_intr = 0;
4862                 vsi->nb_msix = 0;
4863         }
4864
4865         /* Add VSI */
4866         if (type == I40E_VSI_MAIN) {
4867                 /* For main VSI, no need to add since it's default one */
4868                 vsi->uplink_seid = pf->mac_seid;
4869                 vsi->seid = pf->main_vsi_seid;
4870                 /* Bind queues with specific MSIX interrupt */
4871                 /**
4872                  * Needs 2 interrupt at least, one for misc cause which will
4873                  * enabled from OS side, Another for queues binding the
4874                  * interrupt from device side only.
4875                  */
4876
4877                 /* Get default VSI parameters from hardware */
4878                 memset(&ctxt, 0, sizeof(ctxt));
4879                 ctxt.seid = vsi->seid;
4880                 ctxt.pf_num = hw->pf_id;
4881                 ctxt.uplink_seid = vsi->uplink_seid;
4882                 ctxt.vf_num = 0;
4883                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4884                 if (ret != I40E_SUCCESS) {
4885                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4886                         goto fail_msix_alloc;
4887                 }
4888                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4889                         sizeof(struct i40e_aqc_vsi_properties_data));
4890                 vsi->vsi_id = ctxt.vsi_number;
4891                 vsi->info.valid_sections = 0;
4892
4893                 /* Configure tc, enabled TC0 only */
4894                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4895                         I40E_SUCCESS) {
4896                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4897                         goto fail_msix_alloc;
4898                 }
4899
4900                 /* TC, queue mapping */
4901                 memset(&ctxt, 0, sizeof(ctxt));
4902                 vsi->info.valid_sections |=
4903                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4904                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4905                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4906                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4907                         sizeof(struct i40e_aqc_vsi_properties_data));
4908                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4909                                                 I40E_DEFAULT_TCMAP);
4910                 if (ret != I40E_SUCCESS) {
4911                         PMD_DRV_LOG(ERR,
4912                                 "Failed to configure TC queue mapping");
4913                         goto fail_msix_alloc;
4914                 }
4915                 ctxt.seid = vsi->seid;
4916                 ctxt.pf_num = hw->pf_id;
4917                 ctxt.uplink_seid = vsi->uplink_seid;
4918                 ctxt.vf_num = 0;
4919
4920                 /* Update VSI parameters */
4921                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4922                 if (ret != I40E_SUCCESS) {
4923                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4924                         goto fail_msix_alloc;
4925                 }
4926
4927                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4928                                                 sizeof(vsi->info.tc_mapping));
4929                 (void)rte_memcpy(&vsi->info.queue_mapping,
4930                                 &ctxt.info.queue_mapping,
4931                         sizeof(vsi->info.queue_mapping));
4932                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4933                 vsi->info.valid_sections = 0;
4934
4935                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4936                                 ETH_ADDR_LEN);
4937
4938                 /**
4939                  * Updating default filter settings are necessary to prevent
4940                  * reception of tagged packets.
4941                  * Some old firmware configurations load a default macvlan
4942                  * filter which accepts both tagged and untagged packets.
4943                  * The updating is to use a normal filter instead if needed.
4944                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4945                  * The firmware with correct configurations load the default
4946                  * macvlan filter which is expected and cannot be removed.
4947                  */
4948                 i40e_update_default_filter_setting(vsi);
4949                 i40e_config_qinq(hw, vsi);
4950         } else if (type == I40E_VSI_SRIOV) {
4951                 memset(&ctxt, 0, sizeof(ctxt));
4952                 /**
4953                  * For other VSI, the uplink_seid equals to uplink VSI's
4954                  * uplink_seid since they share same VEB
4955                  */
4956                 if (uplink_vsi == NULL)
4957                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4958                 else
4959                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4960                 ctxt.pf_num = hw->pf_id;
4961                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4962                 ctxt.uplink_seid = vsi->uplink_seid;
4963                 ctxt.connection_type = 0x1;
4964                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4965
4966                 /* Use the VEB configuration if FW >= v5.0 */
4967                 if (hw->aq.fw_maj_ver >= 5) {
4968                         /* Configure switch ID */
4969                         ctxt.info.valid_sections |=
4970                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4971                         ctxt.info.switch_id =
4972                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4973                 }
4974
4975                 /* Configure port/vlan */
4976                 ctxt.info.valid_sections |=
4977                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4978                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4979                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4980                                                 hw->func_caps.enabled_tcmap);
4981                 if (ret != I40E_SUCCESS) {
4982                         PMD_DRV_LOG(ERR,
4983                                 "Failed to configure TC queue mapping");
4984                         goto fail_msix_alloc;
4985                 }
4986
4987                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4988                 ctxt.info.valid_sections |=
4989                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4990                 /**
4991                  * Since VSI is not created yet, only configure parameter,
4992                  * will add vsi below.
4993                  */
4994
4995                 i40e_config_qinq(hw, vsi);
4996         } else if (type == I40E_VSI_VMDQ2) {
4997                 memset(&ctxt, 0, sizeof(ctxt));
4998                 /*
4999                  * For other VSI, the uplink_seid equals to uplink VSI's
5000                  * uplink_seid since they share same VEB
5001                  */
5002                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5003                 ctxt.pf_num = hw->pf_id;
5004                 ctxt.vf_num = 0;
5005                 ctxt.uplink_seid = vsi->uplink_seid;
5006                 ctxt.connection_type = 0x1;
5007                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5008
5009                 ctxt.info.valid_sections |=
5010                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5011                 /* user_param carries flag to enable loop back */
5012                 if (user_param) {
5013                         ctxt.info.switch_id =
5014                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5015                         ctxt.info.switch_id |=
5016                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5017                 }
5018
5019                 /* Configure port/vlan */
5020                 ctxt.info.valid_sections |=
5021                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5022                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5023                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5024                                                 I40E_DEFAULT_TCMAP);
5025                 if (ret != I40E_SUCCESS) {
5026                         PMD_DRV_LOG(ERR,
5027                                 "Failed to configure TC queue mapping");
5028                         goto fail_msix_alloc;
5029                 }
5030                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5031                 ctxt.info.valid_sections |=
5032                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5033         } else if (type == I40E_VSI_FDIR) {
5034                 memset(&ctxt, 0, sizeof(ctxt));
5035                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5036                 ctxt.pf_num = hw->pf_id;
5037                 ctxt.vf_num = 0;
5038                 ctxt.uplink_seid = vsi->uplink_seid;
5039                 ctxt.connection_type = 0x1;     /* regular data port */
5040                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5041                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5042                                                 I40E_DEFAULT_TCMAP);
5043                 if (ret != I40E_SUCCESS) {
5044                         PMD_DRV_LOG(ERR,
5045                                 "Failed to configure TC queue mapping.");
5046                         goto fail_msix_alloc;
5047                 }
5048                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5049                 ctxt.info.valid_sections |=
5050                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5051         } else {
5052                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5053                 goto fail_msix_alloc;
5054         }
5055
5056         if (vsi->type != I40E_VSI_MAIN) {
5057                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5058                 if (ret != I40E_SUCCESS) {
5059                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5060                                     hw->aq.asq_last_status);
5061                         goto fail_msix_alloc;
5062                 }
5063                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5064                 vsi->info.valid_sections = 0;
5065                 vsi->seid = ctxt.seid;
5066                 vsi->vsi_id = ctxt.vsi_number;
5067                 vsi->sib_vsi_list.vsi = vsi;
5068                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5069                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5070                                           &vsi->sib_vsi_list, list);
5071                 } else {
5072                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5073                                           &vsi->sib_vsi_list, list);
5074                 }
5075         }
5076
5077         /* MAC/VLAN configuration */
5078         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5079         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5080
5081         ret = i40e_vsi_add_mac(vsi, &filter);
5082         if (ret != I40E_SUCCESS) {
5083                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5084                 goto fail_msix_alloc;
5085         }
5086
5087         /* Get VSI BW information */
5088         i40e_vsi_get_bw_config(vsi);
5089         return vsi;
5090 fail_msix_alloc:
5091         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5092 fail_queue_alloc:
5093         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5094 fail_mem:
5095         rte_free(vsi);
5096         return NULL;
5097 }
5098
5099 /* Configure vlan filter on or off */
5100 int
5101 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5102 {
5103         int i, num;
5104         struct i40e_mac_filter *f;
5105         void *temp;
5106         struct i40e_mac_filter_info *mac_filter;
5107         enum rte_mac_filter_type desired_filter;
5108         int ret = I40E_SUCCESS;
5109
5110         if (on) {
5111                 /* Filter to match MAC and VLAN */
5112                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5113         } else {
5114                 /* Filter to match only MAC */
5115                 desired_filter = RTE_MAC_PERFECT_MATCH;
5116         }
5117
5118         num = vsi->mac_num;
5119
5120         mac_filter = rte_zmalloc("mac_filter_info_data",
5121                                  num * sizeof(*mac_filter), 0);
5122         if (mac_filter == NULL) {
5123                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5124                 return I40E_ERR_NO_MEMORY;
5125         }
5126
5127         i = 0;
5128
5129         /* Remove all existing mac */
5130         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5131                 mac_filter[i] = f->mac_info;
5132                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5133                 if (ret) {
5134                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5135                                     on ? "enable" : "disable");
5136                         goto DONE;
5137                 }
5138                 i++;
5139         }
5140
5141         /* Override with new filter */
5142         for (i = 0; i < num; i++) {
5143                 mac_filter[i].filter_type = desired_filter;
5144                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5145                 if (ret) {
5146                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5147                                     on ? "enable" : "disable");
5148                         goto DONE;
5149                 }
5150         }
5151
5152 DONE:
5153         rte_free(mac_filter);
5154         return ret;
5155 }
5156
5157 /* Configure vlan stripping on or off */
5158 int
5159 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5160 {
5161         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5162         struct i40e_vsi_context ctxt;
5163         uint8_t vlan_flags;
5164         int ret = I40E_SUCCESS;
5165
5166         /* Check if it has been already on or off */
5167         if (vsi->info.valid_sections &
5168                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5169                 if (on) {
5170                         if ((vsi->info.port_vlan_flags &
5171                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5172                                 return 0; /* already on */
5173                 } else {
5174                         if ((vsi->info.port_vlan_flags &
5175                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5176                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5177                                 return 0; /* already off */
5178                 }
5179         }
5180
5181         if (on)
5182                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5183         else
5184                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5185         vsi->info.valid_sections =
5186                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5187         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5188         vsi->info.port_vlan_flags |= vlan_flags;
5189         ctxt.seid = vsi->seid;
5190         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5191         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5192         if (ret)
5193                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5194                             on ? "enable" : "disable");
5195
5196         return ret;
5197 }
5198
5199 static int
5200 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5201 {
5202         struct rte_eth_dev_data *data = dev->data;
5203         int ret;
5204         int mask = 0;
5205
5206         /* Apply vlan offload setting */
5207         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5208         i40e_vlan_offload_set(dev, mask);
5209
5210         /* Apply double-vlan setting, not implemented yet */
5211
5212         /* Apply pvid setting */
5213         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5214                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5215         if (ret)
5216                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5217
5218         return ret;
5219 }
5220
5221 static int
5222 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5223 {
5224         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5225
5226         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5227 }
5228
5229 static int
5230 i40e_update_flow_control(struct i40e_hw *hw)
5231 {
5232 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5233         struct i40e_link_status link_status;
5234         uint32_t rxfc = 0, txfc = 0, reg;
5235         uint8_t an_info;
5236         int ret;
5237
5238         memset(&link_status, 0, sizeof(link_status));
5239         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5240         if (ret != I40E_SUCCESS) {
5241                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5242                 goto write_reg; /* Disable flow control */
5243         }
5244
5245         an_info = hw->phy.link_info.an_info;
5246         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5247                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5248                 ret = I40E_ERR_NOT_READY;
5249                 goto write_reg; /* Disable flow control */
5250         }
5251         /**
5252          * If link auto negotiation is enabled, flow control needs to
5253          * be configured according to it
5254          */
5255         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5256         case I40E_LINK_PAUSE_RXTX:
5257                 rxfc = 1;
5258                 txfc = 1;
5259                 hw->fc.current_mode = I40E_FC_FULL;
5260                 break;
5261         case I40E_AQ_LINK_PAUSE_RX:
5262                 rxfc = 1;
5263                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5264                 break;
5265         case I40E_AQ_LINK_PAUSE_TX:
5266                 txfc = 1;
5267                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5268                 break;
5269         default:
5270                 hw->fc.current_mode = I40E_FC_NONE;
5271                 break;
5272         }
5273
5274 write_reg:
5275         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5276                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5277         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5278         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5279         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5280         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5281
5282         return ret;
5283 }
5284
5285 /* PF setup */
5286 static int
5287 i40e_pf_setup(struct i40e_pf *pf)
5288 {
5289         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5290         struct i40e_filter_control_settings settings;
5291         struct i40e_vsi *vsi;
5292         int ret;
5293
5294         /* Clear all stats counters */
5295         pf->offset_loaded = FALSE;
5296         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5297         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5298         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5299         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5300
5301         ret = i40e_pf_get_switch_config(pf);
5302         if (ret != I40E_SUCCESS) {
5303                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5304                 return ret;
5305         }
5306         if (pf->flags & I40E_FLAG_FDIR) {
5307                 /* make queue allocated first, let FDIR use queue pair 0*/
5308                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5309                 if (ret != I40E_FDIR_QUEUE_ID) {
5310                         PMD_DRV_LOG(ERR,
5311                                 "queue allocation fails for FDIR: ret =%d",
5312                                 ret);
5313                         pf->flags &= ~I40E_FLAG_FDIR;
5314                 }
5315         }
5316         /*  main VSI setup */
5317         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5318         if (!vsi) {
5319                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5320                 return I40E_ERR_NOT_READY;
5321         }
5322         pf->main_vsi = vsi;
5323
5324         /* Configure filter control */
5325         memset(&settings, 0, sizeof(settings));
5326         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5327                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5328         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5329                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5330         else {
5331                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5332                         hw->func_caps.rss_table_size);
5333                 return I40E_ERR_PARAM;
5334         }
5335         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5336                 hw->func_caps.rss_table_size);
5337         pf->hash_lut_size = hw->func_caps.rss_table_size;
5338
5339         /* Enable ethtype and macvlan filters */
5340         settings.enable_ethtype = TRUE;
5341         settings.enable_macvlan = TRUE;
5342         ret = i40e_set_filter_control(hw, &settings);
5343         if (ret)
5344                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5345                                                                 ret);
5346
5347         /* Update flow control according to the auto negotiation */
5348         i40e_update_flow_control(hw);
5349
5350         return I40E_SUCCESS;
5351 }
5352
5353 int
5354 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5355 {
5356         uint32_t reg;
5357         uint16_t j;
5358
5359         /**
5360          * Set or clear TX Queue Disable flags,
5361          * which is required by hardware.
5362          */
5363         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5364         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5365
5366         /* Wait until the request is finished */
5367         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5368                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5369                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5370                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5371                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5372                                                         & 0x1))) {
5373                         break;
5374                 }
5375         }
5376         if (on) {
5377                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5378                         return I40E_SUCCESS; /* already on, skip next steps */
5379
5380                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5381                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5382         } else {
5383                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5384                         return I40E_SUCCESS; /* already off, skip next steps */
5385                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5386         }
5387         /* Write the register */
5388         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5389         /* Check the result */
5390         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5391                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5392                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5393                 if (on) {
5394                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5395                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5396                                 break;
5397                 } else {
5398                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5399                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5400                                 break;
5401                 }
5402         }
5403         /* Check if it is timeout */
5404         if (j >= I40E_CHK_Q_ENA_COUNT) {
5405                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5406                             (on ? "enable" : "disable"), q_idx);
5407                 return I40E_ERR_TIMEOUT;
5408         }
5409
5410         return I40E_SUCCESS;
5411 }
5412
5413 /* Swith on or off the tx queues */
5414 static int
5415 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5416 {
5417         struct rte_eth_dev_data *dev_data = pf->dev_data;
5418         struct i40e_tx_queue *txq;
5419         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5420         uint16_t i;
5421         int ret;
5422
5423         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5424                 txq = dev_data->tx_queues[i];
5425                 /* Don't operate the queue if not configured or
5426                  * if starting only per queue */
5427                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5428                         continue;
5429                 if (on)
5430                         ret = i40e_dev_tx_queue_start(dev, i);
5431                 else
5432                         ret = i40e_dev_tx_queue_stop(dev, i);
5433                 if ( ret != I40E_SUCCESS)
5434                         return ret;
5435         }
5436
5437         return I40E_SUCCESS;
5438 }
5439
5440 int
5441 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5442 {
5443         uint32_t reg;
5444         uint16_t j;
5445
5446         /* Wait until the request is finished */
5447         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5448                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5449                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5450                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5451                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5452                         break;
5453         }
5454
5455         if (on) {
5456                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5457                         return I40E_SUCCESS; /* Already on, skip next steps */
5458                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5459         } else {
5460                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5461                         return I40E_SUCCESS; /* Already off, skip next steps */
5462                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5463         }
5464
5465         /* Write the register */
5466         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5467         /* Check the result */
5468         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5469                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5470                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5471                 if (on) {
5472                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5473                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5474                                 break;
5475                 } else {
5476                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5477                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5478                                 break;
5479                 }
5480         }
5481
5482         /* Check if it is timeout */
5483         if (j >= I40E_CHK_Q_ENA_COUNT) {
5484                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5485                             (on ? "enable" : "disable"), q_idx);
5486                 return I40E_ERR_TIMEOUT;
5487         }
5488
5489         return I40E_SUCCESS;
5490 }
5491 /* Switch on or off the rx queues */
5492 static int
5493 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5494 {
5495         struct rte_eth_dev_data *dev_data = pf->dev_data;
5496         struct i40e_rx_queue *rxq;
5497         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5498         uint16_t i;
5499         int ret;
5500
5501         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5502                 rxq = dev_data->rx_queues[i];
5503                 /* Don't operate the queue if not configured or
5504                  * if starting only per queue */
5505                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5506                         continue;
5507                 if (on)
5508                         ret = i40e_dev_rx_queue_start(dev, i);
5509                 else
5510                         ret = i40e_dev_rx_queue_stop(dev, i);
5511                 if (ret != I40E_SUCCESS)
5512                         return ret;
5513         }
5514
5515         return I40E_SUCCESS;
5516 }
5517
5518 /* Switch on or off all the rx/tx queues */
5519 int
5520 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5521 {
5522         int ret;
5523
5524         if (on) {
5525                 /* enable rx queues before enabling tx queues */
5526                 ret = i40e_dev_switch_rx_queues(pf, on);
5527                 if (ret) {
5528                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5529                         return ret;
5530                 }
5531                 ret = i40e_dev_switch_tx_queues(pf, on);
5532         } else {
5533                 /* Stop tx queues before stopping rx queues */
5534                 ret = i40e_dev_switch_tx_queues(pf, on);
5535                 if (ret) {
5536                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5537                         return ret;
5538                 }
5539                 ret = i40e_dev_switch_rx_queues(pf, on);
5540         }
5541
5542         return ret;
5543 }
5544
5545 /* Initialize VSI for TX */
5546 static int
5547 i40e_dev_tx_init(struct i40e_pf *pf)
5548 {
5549         struct rte_eth_dev_data *data = pf->dev_data;
5550         uint16_t i;
5551         uint32_t ret = I40E_SUCCESS;
5552         struct i40e_tx_queue *txq;
5553
5554         for (i = 0; i < data->nb_tx_queues; i++) {
5555                 txq = data->tx_queues[i];
5556                 if (!txq || !txq->q_set)
5557                         continue;
5558                 ret = i40e_tx_queue_init(txq);
5559                 if (ret != I40E_SUCCESS)
5560                         break;
5561         }
5562         if (ret == I40E_SUCCESS)
5563                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5564                                      ->eth_dev);
5565
5566         return ret;
5567 }
5568
5569 /* Initialize VSI for RX */
5570 static int
5571 i40e_dev_rx_init(struct i40e_pf *pf)
5572 {
5573         struct rte_eth_dev_data *data = pf->dev_data;
5574         int ret = I40E_SUCCESS;
5575         uint16_t i;
5576         struct i40e_rx_queue *rxq;
5577
5578         i40e_pf_config_mq_rx(pf);
5579         for (i = 0; i < data->nb_rx_queues; i++) {
5580                 rxq = data->rx_queues[i];
5581                 if (!rxq || !rxq->q_set)
5582                         continue;
5583
5584                 ret = i40e_rx_queue_init(rxq);
5585                 if (ret != I40E_SUCCESS) {
5586                         PMD_DRV_LOG(ERR,
5587                                 "Failed to do RX queue initialization");
5588                         break;
5589                 }
5590         }
5591         if (ret == I40E_SUCCESS)
5592                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5593                                      ->eth_dev);
5594
5595         return ret;
5596 }
5597
5598 static int
5599 i40e_dev_rxtx_init(struct i40e_pf *pf)
5600 {
5601         int err;
5602
5603         err = i40e_dev_tx_init(pf);
5604         if (err) {
5605                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5606                 return err;
5607         }
5608         err = i40e_dev_rx_init(pf);
5609         if (err) {
5610                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5611                 return err;
5612         }
5613
5614         return err;
5615 }
5616
5617 static int
5618 i40e_vmdq_setup(struct rte_eth_dev *dev)
5619 {
5620         struct rte_eth_conf *conf = &dev->data->dev_conf;
5621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5622         int i, err, conf_vsis, j, loop;
5623         struct i40e_vsi *vsi;
5624         struct i40e_vmdq_info *vmdq_info;
5625         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5626         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5627
5628         /*
5629          * Disable interrupt to avoid message from VF. Furthermore, it will
5630          * avoid race condition in VSI creation/destroy.
5631          */
5632         i40e_pf_disable_irq0(hw);
5633
5634         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5635                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5636                 return -ENOTSUP;
5637         }
5638
5639         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5640         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5641                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5642                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5643                         pf->max_nb_vmdq_vsi);
5644                 return -ENOTSUP;
5645         }
5646
5647         if (pf->vmdq != NULL) {
5648                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5649                 return 0;
5650         }
5651
5652         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5653                                 sizeof(*vmdq_info) * conf_vsis, 0);
5654
5655         if (pf->vmdq == NULL) {
5656                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5657                 return -ENOMEM;
5658         }
5659
5660         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5661
5662         /* Create VMDQ VSI */
5663         for (i = 0; i < conf_vsis; i++) {
5664                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5665                                 vmdq_conf->enable_loop_back);
5666                 if (vsi == NULL) {
5667                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5668                         err = -1;
5669                         goto err_vsi_setup;
5670                 }
5671                 vmdq_info = &pf->vmdq[i];
5672                 vmdq_info->pf = pf;
5673                 vmdq_info->vsi = vsi;
5674         }
5675         pf->nb_cfg_vmdq_vsi = conf_vsis;
5676
5677         /* Configure Vlan */
5678         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5679         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5680                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5681                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5682                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5683                                         vmdq_conf->pool_map[i].vlan_id, j);
5684
5685                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5686                                                 vmdq_conf->pool_map[i].vlan_id);
5687                                 if (err) {
5688                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5689                                         err = -1;
5690                                         goto err_vsi_setup;
5691                                 }
5692                         }
5693                 }
5694         }
5695
5696         i40e_pf_enable_irq0(hw);
5697
5698         return 0;
5699
5700 err_vsi_setup:
5701         for (i = 0; i < conf_vsis; i++)
5702                 if (pf->vmdq[i].vsi == NULL)
5703                         break;
5704                 else
5705                         i40e_vsi_release(pf->vmdq[i].vsi);
5706
5707         rte_free(pf->vmdq);
5708         pf->vmdq = NULL;
5709         i40e_pf_enable_irq0(hw);
5710         return err;
5711 }
5712
5713 static void
5714 i40e_stat_update_32(struct i40e_hw *hw,
5715                    uint32_t reg,
5716                    bool offset_loaded,
5717                    uint64_t *offset,
5718                    uint64_t *stat)
5719 {
5720         uint64_t new_data;
5721
5722         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5723         if (!offset_loaded)
5724                 *offset = new_data;
5725
5726         if (new_data >= *offset)
5727                 *stat = (uint64_t)(new_data - *offset);
5728         else
5729                 *stat = (uint64_t)((new_data +
5730                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5731 }
5732
5733 static void
5734 i40e_stat_update_48(struct i40e_hw *hw,
5735                    uint32_t hireg,
5736                    uint32_t loreg,
5737                    bool offset_loaded,
5738                    uint64_t *offset,
5739                    uint64_t *stat)
5740 {
5741         uint64_t new_data;
5742
5743         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5744         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5745                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5746
5747         if (!offset_loaded)
5748                 *offset = new_data;
5749
5750         if (new_data >= *offset)
5751                 *stat = new_data - *offset;
5752         else
5753                 *stat = (uint64_t)((new_data +
5754                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5755
5756         *stat &= I40E_48_BIT_MASK;
5757 }
5758
5759 /* Disable IRQ0 */
5760 void
5761 i40e_pf_disable_irq0(struct i40e_hw *hw)
5762 {
5763         /* Disable all interrupt types */
5764         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5765         I40E_WRITE_FLUSH(hw);
5766 }
5767
5768 /* Enable IRQ0 */
5769 void
5770 i40e_pf_enable_irq0(struct i40e_hw *hw)
5771 {
5772         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5773                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5774                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5775                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5776         I40E_WRITE_FLUSH(hw);
5777 }
5778
5779 static void
5780 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5781 {
5782         /* read pending request and disable first */
5783         i40e_pf_disable_irq0(hw);
5784         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5785         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5786                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5787
5788         if (no_queue)
5789                 /* Link no queues with irq0 */
5790                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5791                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5792 }
5793
5794 static void
5795 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5796 {
5797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5798         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5799         int i;
5800         uint16_t abs_vf_id;
5801         uint32_t index, offset, val;
5802
5803         if (!pf->vfs)
5804                 return;
5805         /**
5806          * Try to find which VF trigger a reset, use absolute VF id to access
5807          * since the reg is global register.
5808          */
5809         for (i = 0; i < pf->vf_num; i++) {
5810                 abs_vf_id = hw->func_caps.vf_base_id + i;
5811                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5812                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5813                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5814                 /* VFR event occurred */
5815                 if (val & (0x1 << offset)) {
5816                         int ret;
5817
5818                         /* Clear the event first */
5819                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5820                                                         (0x1 << offset));
5821                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5822                         /**
5823                          * Only notify a VF reset event occurred,
5824                          * don't trigger another SW reset
5825                          */
5826                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5827                         if (ret != I40E_SUCCESS)
5828                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5829                 }
5830         }
5831 }
5832
5833 static void
5834 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5835 {
5836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5837         int i;
5838
5839         for (i = 0; i < pf->vf_num; i++)
5840                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5841 }
5842
5843 static void
5844 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5845 {
5846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5847         struct i40e_arq_event_info info;
5848         uint16_t pending, opcode;
5849         int ret;
5850
5851         info.buf_len = I40E_AQ_BUF_SZ;
5852         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5853         if (!info.msg_buf) {
5854                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5855                 return;
5856         }
5857
5858         pending = 1;
5859         while (pending) {
5860                 ret = i40e_clean_arq_element(hw, &info, &pending);
5861
5862                 if (ret != I40E_SUCCESS) {
5863                         PMD_DRV_LOG(INFO,
5864                                 "Failed to read msg from AdminQ, aq_err: %u",
5865                                 hw->aq.asq_last_status);
5866                         break;
5867                 }
5868                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5869
5870                 switch (opcode) {
5871                 case i40e_aqc_opc_send_msg_to_pf:
5872                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5873                         i40e_pf_host_handle_vf_msg(dev,
5874                                         rte_le_to_cpu_16(info.desc.retval),
5875                                         rte_le_to_cpu_32(info.desc.cookie_high),
5876                                         rte_le_to_cpu_32(info.desc.cookie_low),
5877                                         info.msg_buf,
5878                                         info.msg_len);
5879                         break;
5880                 case i40e_aqc_opc_get_link_status:
5881                         ret = i40e_dev_link_update(dev, 0);
5882                         if (!ret)
5883                                 _rte_eth_dev_callback_process(dev,
5884                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5885                         break;
5886                 default:
5887                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5888                                     opcode);
5889                         break;
5890                 }
5891         }
5892         rte_free(info.msg_buf);
5893 }
5894
5895 /**
5896  * Interrupt handler triggered by NIC  for handling
5897  * specific interrupt.
5898  *
5899  * @param handle
5900  *  Pointer to interrupt handle.
5901  * @param param
5902  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5903  *
5904  * @return
5905  *  void
5906  */
5907 static void
5908 i40e_dev_interrupt_handler(void *param)
5909 {
5910         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912         uint32_t icr0;
5913
5914         /* Disable interrupt */
5915         i40e_pf_disable_irq0(hw);
5916
5917         /* read out interrupt causes */
5918         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5919
5920         /* No interrupt event indicated */
5921         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5922                 PMD_DRV_LOG(INFO, "No interrupt event");
5923                 goto done;
5924         }
5925         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5926                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5927         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5928                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5929         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5930                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5931         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5932                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5933         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5934                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5935         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5936                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5937         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5938                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5939
5940         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5941                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5942                 i40e_dev_handle_vfr_event(dev);
5943         }
5944         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5945                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5946                 i40e_dev_handle_aq_msg(dev);
5947         }
5948
5949 done:
5950         /* Enable interrupt */
5951         i40e_pf_enable_irq0(hw);
5952         rte_intr_enable(dev->intr_handle);
5953 }
5954
5955 int
5956 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5957                          struct i40e_macvlan_filter *filter,
5958                          int total)
5959 {
5960         int ele_num, ele_buff_size;
5961         int num, actual_num, i;
5962         uint16_t flags;
5963         int ret = I40E_SUCCESS;
5964         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5965         struct i40e_aqc_add_macvlan_element_data *req_list;
5966
5967         if (filter == NULL  || total == 0)
5968                 return I40E_ERR_PARAM;
5969         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5970         ele_buff_size = hw->aq.asq_buf_size;
5971
5972         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5973         if (req_list == NULL) {
5974                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5975                 return I40E_ERR_NO_MEMORY;
5976         }
5977
5978         num = 0;
5979         do {
5980                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5981                 memset(req_list, 0, ele_buff_size);
5982
5983                 for (i = 0; i < actual_num; i++) {
5984                         (void)rte_memcpy(req_list[i].mac_addr,
5985                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5986                         req_list[i].vlan_tag =
5987                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5988
5989                         switch (filter[num + i].filter_type) {
5990                         case RTE_MAC_PERFECT_MATCH:
5991                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5992                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5993                                 break;
5994                         case RTE_MACVLAN_PERFECT_MATCH:
5995                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5996                                 break;
5997                         case RTE_MAC_HASH_MATCH:
5998                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5999                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6000                                 break;
6001                         case RTE_MACVLAN_HASH_MATCH:
6002                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6003                                 break;
6004                         default:
6005                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6006                                 ret = I40E_ERR_PARAM;
6007                                 goto DONE;
6008                         }
6009
6010                         req_list[i].queue_number = 0;
6011
6012                         req_list[i].flags = rte_cpu_to_le_16(flags);
6013                 }
6014
6015                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6016                                                 actual_num, NULL);
6017                 if (ret != I40E_SUCCESS) {
6018                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6019                         goto DONE;
6020                 }
6021                 num += actual_num;
6022         } while (num < total);
6023
6024 DONE:
6025         rte_free(req_list);
6026         return ret;
6027 }
6028
6029 int
6030 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6031                             struct i40e_macvlan_filter *filter,
6032                             int total)
6033 {
6034         int ele_num, ele_buff_size;
6035         int num, actual_num, i;
6036         uint16_t flags;
6037         int ret = I40E_SUCCESS;
6038         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6039         struct i40e_aqc_remove_macvlan_element_data *req_list;
6040
6041         if (filter == NULL  || total == 0)
6042                 return I40E_ERR_PARAM;
6043
6044         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6045         ele_buff_size = hw->aq.asq_buf_size;
6046
6047         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6048         if (req_list == NULL) {
6049                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6050                 return I40E_ERR_NO_MEMORY;
6051         }
6052
6053         num = 0;
6054         do {
6055                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6056                 memset(req_list, 0, ele_buff_size);
6057
6058                 for (i = 0; i < actual_num; i++) {
6059                         (void)rte_memcpy(req_list[i].mac_addr,
6060                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6061                         req_list[i].vlan_tag =
6062                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6063
6064                         switch (filter[num + i].filter_type) {
6065                         case RTE_MAC_PERFECT_MATCH:
6066                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6067                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6068                                 break;
6069                         case RTE_MACVLAN_PERFECT_MATCH:
6070                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6071                                 break;
6072                         case RTE_MAC_HASH_MATCH:
6073                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6074                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6075                                 break;
6076                         case RTE_MACVLAN_HASH_MATCH:
6077                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6078                                 break;
6079                         default:
6080                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6081                                 ret = I40E_ERR_PARAM;
6082                                 goto DONE;
6083                         }
6084                         req_list[i].flags = rte_cpu_to_le_16(flags);
6085                 }
6086
6087                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6088                                                 actual_num, NULL);
6089                 if (ret != I40E_SUCCESS) {
6090                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6091                         goto DONE;
6092                 }
6093                 num += actual_num;
6094         } while (num < total);
6095
6096 DONE:
6097         rte_free(req_list);
6098         return ret;
6099 }
6100
6101 /* Find out specific MAC filter */
6102 static struct i40e_mac_filter *
6103 i40e_find_mac_filter(struct i40e_vsi *vsi,
6104                          struct ether_addr *macaddr)
6105 {
6106         struct i40e_mac_filter *f;
6107
6108         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6109                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6110                         return f;
6111         }
6112
6113         return NULL;
6114 }
6115
6116 static bool
6117 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6118                          uint16_t vlan_id)
6119 {
6120         uint32_t vid_idx, vid_bit;
6121
6122         if (vlan_id > ETH_VLAN_ID_MAX)
6123                 return 0;
6124
6125         vid_idx = I40E_VFTA_IDX(vlan_id);
6126         vid_bit = I40E_VFTA_BIT(vlan_id);
6127
6128         if (vsi->vfta[vid_idx] & vid_bit)
6129                 return 1;
6130         else
6131                 return 0;
6132 }
6133
6134 static void
6135 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6136                        uint16_t vlan_id, bool on)
6137 {
6138         uint32_t vid_idx, vid_bit;
6139
6140         vid_idx = I40E_VFTA_IDX(vlan_id);
6141         vid_bit = I40E_VFTA_BIT(vlan_id);
6142
6143         if (on)
6144                 vsi->vfta[vid_idx] |= vid_bit;
6145         else
6146                 vsi->vfta[vid_idx] &= ~vid_bit;
6147 }
6148
6149 void
6150 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6151                      uint16_t vlan_id, bool on)
6152 {
6153         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6154         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6155         int ret;
6156
6157         if (vlan_id > ETH_VLAN_ID_MAX)
6158                 return;
6159
6160         i40e_store_vlan_filter(vsi, vlan_id, on);
6161
6162         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6163                 return;
6164
6165         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6166
6167         if (on) {
6168                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6169                                        &vlan_data, 1, NULL);
6170                 if (ret != I40E_SUCCESS)
6171                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6172         } else {
6173                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6174                                           &vlan_data, 1, NULL);
6175                 if (ret != I40E_SUCCESS)
6176                         PMD_DRV_LOG(ERR,
6177                                     "Failed to remove vlan filter");
6178         }
6179 }
6180
6181 /**
6182  * Find all vlan options for specific mac addr,
6183  * return with actual vlan found.
6184  */
6185 int
6186 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6187                            struct i40e_macvlan_filter *mv_f,
6188                            int num, struct ether_addr *addr)
6189 {
6190         int i;
6191         uint32_t j, k;
6192
6193         /**
6194          * Not to use i40e_find_vlan_filter to decrease the loop time,
6195          * although the code looks complex.
6196           */
6197         if (num < vsi->vlan_num)
6198                 return I40E_ERR_PARAM;
6199
6200         i = 0;
6201         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6202                 if (vsi->vfta[j]) {
6203                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6204                                 if (vsi->vfta[j] & (1 << k)) {
6205                                         if (i > num - 1) {
6206                                                 PMD_DRV_LOG(ERR,
6207                                                         "vlan number doesn't match");
6208                                                 return I40E_ERR_PARAM;
6209                                         }
6210                                         (void)rte_memcpy(&mv_f[i].macaddr,
6211                                                         addr, ETH_ADDR_LEN);
6212                                         mv_f[i].vlan_id =
6213                                                 j * I40E_UINT32_BIT_SIZE + k;
6214                                         i++;
6215                                 }
6216                         }
6217                 }
6218         }
6219         return I40E_SUCCESS;
6220 }
6221
6222 static inline int
6223 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6224                            struct i40e_macvlan_filter *mv_f,
6225                            int num,
6226                            uint16_t vlan)
6227 {
6228         int i = 0;
6229         struct i40e_mac_filter *f;
6230
6231         if (num < vsi->mac_num)
6232                 return I40E_ERR_PARAM;
6233
6234         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6235                 if (i > num - 1) {
6236                         PMD_DRV_LOG(ERR, "buffer number not match");
6237                         return I40E_ERR_PARAM;
6238                 }
6239                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6240                                 ETH_ADDR_LEN);
6241                 mv_f[i].vlan_id = vlan;
6242                 mv_f[i].filter_type = f->mac_info.filter_type;
6243                 i++;
6244         }
6245
6246         return I40E_SUCCESS;
6247 }
6248
6249 static int
6250 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6251 {
6252         int i, j, num;
6253         struct i40e_mac_filter *f;
6254         struct i40e_macvlan_filter *mv_f;
6255         int ret = I40E_SUCCESS;
6256
6257         if (vsi == NULL || vsi->mac_num == 0)
6258                 return I40E_ERR_PARAM;
6259
6260         /* Case that no vlan is set */
6261         if (vsi->vlan_num == 0)
6262                 num = vsi->mac_num;
6263         else
6264                 num = vsi->mac_num * vsi->vlan_num;
6265
6266         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6267         if (mv_f == NULL) {
6268                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6269                 return I40E_ERR_NO_MEMORY;
6270         }
6271
6272         i = 0;
6273         if (vsi->vlan_num == 0) {
6274                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6275                         (void)rte_memcpy(&mv_f[i].macaddr,
6276                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6277                         mv_f[i].filter_type = f->mac_info.filter_type;
6278                         mv_f[i].vlan_id = 0;
6279                         i++;
6280                 }
6281         } else {
6282                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6283                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6284                                         vsi->vlan_num, &f->mac_info.mac_addr);
6285                         if (ret != I40E_SUCCESS)
6286                                 goto DONE;
6287                         for (j = i; j < i + vsi->vlan_num; j++)
6288                                 mv_f[j].filter_type = f->mac_info.filter_type;
6289                         i += vsi->vlan_num;
6290                 }
6291         }
6292
6293         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6294 DONE:
6295         rte_free(mv_f);
6296
6297         return ret;
6298 }
6299
6300 int
6301 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6302 {
6303         struct i40e_macvlan_filter *mv_f;
6304         int mac_num;
6305         int ret = I40E_SUCCESS;
6306
6307         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6308                 return I40E_ERR_PARAM;
6309
6310         /* If it's already set, just return */
6311         if (i40e_find_vlan_filter(vsi,vlan))
6312                 return I40E_SUCCESS;
6313
6314         mac_num = vsi->mac_num;
6315
6316         if (mac_num == 0) {
6317                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6318                 return I40E_ERR_PARAM;
6319         }
6320
6321         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6322
6323         if (mv_f == NULL) {
6324                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6325                 return I40E_ERR_NO_MEMORY;
6326         }
6327
6328         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6329
6330         if (ret != I40E_SUCCESS)
6331                 goto DONE;
6332
6333         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6334
6335         if (ret != I40E_SUCCESS)
6336                 goto DONE;
6337
6338         i40e_set_vlan_filter(vsi, vlan, 1);
6339
6340         vsi->vlan_num++;
6341         ret = I40E_SUCCESS;
6342 DONE:
6343         rte_free(mv_f);
6344         return ret;
6345 }
6346
6347 int
6348 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6349 {
6350         struct i40e_macvlan_filter *mv_f;
6351         int mac_num;
6352         int ret = I40E_SUCCESS;
6353
6354         /**
6355          * Vlan 0 is the generic filter for untagged packets
6356          * and can't be removed.
6357          */
6358         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6359                 return I40E_ERR_PARAM;
6360
6361         /* If can't find it, just return */
6362         if (!i40e_find_vlan_filter(vsi, vlan))
6363                 return I40E_ERR_PARAM;
6364
6365         mac_num = vsi->mac_num;
6366
6367         if (mac_num == 0) {
6368                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6369                 return I40E_ERR_PARAM;
6370         }
6371
6372         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6373
6374         if (mv_f == NULL) {
6375                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6376                 return I40E_ERR_NO_MEMORY;
6377         }
6378
6379         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6380
6381         if (ret != I40E_SUCCESS)
6382                 goto DONE;
6383
6384         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6385
6386         if (ret != I40E_SUCCESS)
6387                 goto DONE;
6388
6389         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6390         if (vsi->vlan_num == 1) {
6391                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6392                 if (ret != I40E_SUCCESS)
6393                         goto DONE;
6394
6395                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6396                 if (ret != I40E_SUCCESS)
6397                         goto DONE;
6398         }
6399
6400         i40e_set_vlan_filter(vsi, vlan, 0);
6401
6402         vsi->vlan_num--;
6403         ret = I40E_SUCCESS;
6404 DONE:
6405         rte_free(mv_f);
6406         return ret;
6407 }
6408
6409 int
6410 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6411 {
6412         struct i40e_mac_filter *f;
6413         struct i40e_macvlan_filter *mv_f;
6414         int i, vlan_num = 0;
6415         int ret = I40E_SUCCESS;
6416
6417         /* If it's add and we've config it, return */
6418         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6419         if (f != NULL)
6420                 return I40E_SUCCESS;
6421         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6422                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6423
6424                 /**
6425                  * If vlan_num is 0, that's the first time to add mac,
6426                  * set mask for vlan_id 0.
6427                  */
6428                 if (vsi->vlan_num == 0) {
6429                         i40e_set_vlan_filter(vsi, 0, 1);
6430                         vsi->vlan_num = 1;
6431                 }
6432                 vlan_num = vsi->vlan_num;
6433         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6434                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6435                 vlan_num = 1;
6436
6437         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6438         if (mv_f == NULL) {
6439                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6440                 return I40E_ERR_NO_MEMORY;
6441         }
6442
6443         for (i = 0; i < vlan_num; i++) {
6444                 mv_f[i].filter_type = mac_filter->filter_type;
6445                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6446                                 ETH_ADDR_LEN);
6447         }
6448
6449         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6450                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6451                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6452                                         &mac_filter->mac_addr);
6453                 if (ret != I40E_SUCCESS)
6454                         goto DONE;
6455         }
6456
6457         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6458         if (ret != I40E_SUCCESS)
6459                 goto DONE;
6460
6461         /* Add the mac addr into mac list */
6462         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6463         if (f == NULL) {
6464                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6465                 ret = I40E_ERR_NO_MEMORY;
6466                 goto DONE;
6467         }
6468         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6469                         ETH_ADDR_LEN);
6470         f->mac_info.filter_type = mac_filter->filter_type;
6471         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6472         vsi->mac_num++;
6473
6474         ret = I40E_SUCCESS;
6475 DONE:
6476         rte_free(mv_f);
6477
6478         return ret;
6479 }
6480
6481 int
6482 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6483 {
6484         struct i40e_mac_filter *f;
6485         struct i40e_macvlan_filter *mv_f;
6486         int i, vlan_num;
6487         enum rte_mac_filter_type filter_type;
6488         int ret = I40E_SUCCESS;
6489
6490         /* Can't find it, return an error */
6491         f = i40e_find_mac_filter(vsi, addr);
6492         if (f == NULL)
6493                 return I40E_ERR_PARAM;
6494
6495         vlan_num = vsi->vlan_num;
6496         filter_type = f->mac_info.filter_type;
6497         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6498                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6499                 if (vlan_num == 0) {
6500                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6501                         return I40E_ERR_PARAM;
6502                 }
6503         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6504                         filter_type == RTE_MAC_HASH_MATCH)
6505                 vlan_num = 1;
6506
6507         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6508         if (mv_f == NULL) {
6509                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6510                 return I40E_ERR_NO_MEMORY;
6511         }
6512
6513         for (i = 0; i < vlan_num; i++) {
6514                 mv_f[i].filter_type = filter_type;
6515                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6516                                 ETH_ADDR_LEN);
6517         }
6518         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6519                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6520                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6521                 if (ret != I40E_SUCCESS)
6522                         goto DONE;
6523         }
6524
6525         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6526         if (ret != I40E_SUCCESS)
6527                 goto DONE;
6528
6529         /* Remove the mac addr into mac list */
6530         TAILQ_REMOVE(&vsi->mac_list, f, next);
6531         rte_free(f);
6532         vsi->mac_num--;
6533
6534         ret = I40E_SUCCESS;
6535 DONE:
6536         rte_free(mv_f);
6537         return ret;
6538 }
6539
6540 /* Configure hash enable flags for RSS */
6541 uint64_t
6542 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6543 {
6544         uint64_t hena = 0;
6545
6546         if (!flags)
6547                 return hena;
6548
6549         if (flags & ETH_RSS_FRAG_IPV4)
6550                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6551         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6552                 if (type == I40E_MAC_X722) {
6553                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6554                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6555                 } else
6556                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6557         }
6558         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6559                 if (type == I40E_MAC_X722) {
6560                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6561                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6562                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6563                 } else
6564                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6565         }
6566         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6567                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6568         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6569                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6570         if (flags & ETH_RSS_FRAG_IPV6)
6571                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6572         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6573                 if (type == I40E_MAC_X722) {
6574                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6575                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6576                 } else
6577                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6578         }
6579         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6580                 if (type == I40E_MAC_X722) {
6581                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6582                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6583                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6584                 } else
6585                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6586         }
6587         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6588                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6589         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6590                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6591         if (flags & ETH_RSS_L2_PAYLOAD)
6592                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6593
6594         return hena;
6595 }
6596
6597 /* Parse the hash enable flags */
6598 uint64_t
6599 i40e_parse_hena(uint64_t flags)
6600 {
6601         uint64_t rss_hf = 0;
6602
6603         if (!flags)
6604                 return rss_hf;
6605         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6606                 rss_hf |= ETH_RSS_FRAG_IPV4;
6607         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6608                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6609         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6610                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6611         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6612                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6613         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6614                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6615         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6616                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6617         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6618                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6619         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6620                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6621         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6622                 rss_hf |= ETH_RSS_FRAG_IPV6;
6623         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6624                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6625         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6626                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6627         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6628                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6629         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6630                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6631         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6632                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6633         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6634                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6635         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6636                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6637         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6638                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6639
6640         return rss_hf;
6641 }
6642
6643 /* Disable RSS */
6644 static void
6645 i40e_pf_disable_rss(struct i40e_pf *pf)
6646 {
6647         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6648         uint64_t hena;
6649
6650         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6651         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6652         if (hw->mac.type == I40E_MAC_X722)
6653                 hena &= ~I40E_RSS_HENA_ALL_X722;
6654         else
6655                 hena &= ~I40E_RSS_HENA_ALL;
6656         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6657         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6658         I40E_WRITE_FLUSH(hw);
6659 }
6660
6661 static int
6662 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6663 {
6664         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6665         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6666         int ret = 0;
6667
6668         if (!key || key_len == 0) {
6669                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6670                 return 0;
6671         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6672                 sizeof(uint32_t)) {
6673                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6674                 return -EINVAL;
6675         }
6676
6677         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6678                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6679                         (struct i40e_aqc_get_set_rss_key_data *)key;
6680
6681                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6682                 if (ret)
6683                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6684         } else {
6685                 uint32_t *hash_key = (uint32_t *)key;
6686                 uint16_t i;
6687
6688                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6689                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6690                 I40E_WRITE_FLUSH(hw);
6691         }
6692
6693         return ret;
6694 }
6695
6696 static int
6697 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6698 {
6699         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6700         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6701         int ret;
6702
6703         if (!key || !key_len)
6704                 return -EINVAL;
6705
6706         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6707                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6708                         (struct i40e_aqc_get_set_rss_key_data *)key);
6709                 if (ret) {
6710                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6711                         return ret;
6712                 }
6713         } else {
6714                 uint32_t *key_dw = (uint32_t *)key;
6715                 uint16_t i;
6716
6717                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6718                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6719         }
6720         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6721
6722         return 0;
6723 }
6724
6725 static int
6726 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6727 {
6728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6729         uint64_t rss_hf;
6730         uint64_t hena;
6731         int ret;
6732
6733         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6734                                rss_conf->rss_key_len);
6735         if (ret)
6736                 return ret;
6737
6738         rss_hf = rss_conf->rss_hf;
6739         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6740         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6741         if (hw->mac.type == I40E_MAC_X722)
6742                 hena &= ~I40E_RSS_HENA_ALL_X722;
6743         else
6744                 hena &= ~I40E_RSS_HENA_ALL;
6745         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6746         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6747         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6748         I40E_WRITE_FLUSH(hw);
6749
6750         return 0;
6751 }
6752
6753 static int
6754 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6755                          struct rte_eth_rss_conf *rss_conf)
6756 {
6757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6759         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6760         uint64_t hena;
6761
6762         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6763         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6764         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6765                  ? I40E_RSS_HENA_ALL_X722
6766                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6767                 if (rss_hf != 0) /* Enable RSS */
6768                         return -EINVAL;
6769                 return 0; /* Nothing to do */
6770         }
6771         /* RSS enabled */
6772         if (rss_hf == 0) /* Disable RSS */
6773                 return -EINVAL;
6774
6775         return i40e_hw_rss_hash_set(pf, rss_conf);
6776 }
6777
6778 static int
6779 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6780                            struct rte_eth_rss_conf *rss_conf)
6781 {
6782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6784         uint64_t hena;
6785
6786         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6787                          &rss_conf->rss_key_len);
6788
6789         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6790         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6791         rss_conf->rss_hf = i40e_parse_hena(hena);
6792
6793         return 0;
6794 }
6795
6796 static int
6797 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6798 {
6799         switch (filter_type) {
6800         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6801                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6802                 break;
6803         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6804                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6805                 break;
6806         case RTE_TUNNEL_FILTER_IMAC_TENID:
6807                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6808                 break;
6809         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6810                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6811                 break;
6812         case ETH_TUNNEL_FILTER_IMAC:
6813                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6814                 break;
6815         case ETH_TUNNEL_FILTER_OIP:
6816                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6817                 break;
6818         case ETH_TUNNEL_FILTER_IIP:
6819                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6820                 break;
6821         default:
6822                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6823                 return -EINVAL;
6824         }
6825
6826         return 0;
6827 }
6828
6829 /* Convert tunnel filter structure */
6830 static int
6831 i40e_tunnel_filter_convert(
6832         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6833         struct i40e_tunnel_filter *tunnel_filter)
6834 {
6835         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6836                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6837         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6838                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6839         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6840         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6841              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6842             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6843                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6844         else
6845                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6846         tunnel_filter->input.flags = cld_filter->element.flags;
6847         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6848         tunnel_filter->queue = cld_filter->element.queue_number;
6849         rte_memcpy(tunnel_filter->input.general_fields,
6850                    cld_filter->general_fields,
6851                    sizeof(cld_filter->general_fields));
6852
6853         return 0;
6854 }
6855
6856 /* Check if there exists the tunnel filter */
6857 struct i40e_tunnel_filter *
6858 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6859                              const struct i40e_tunnel_filter_input *input)
6860 {
6861         int ret;
6862
6863         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6864         if (ret < 0)
6865                 return NULL;
6866
6867         return tunnel_rule->hash_map[ret];
6868 }
6869
6870 /* Add a tunnel filter into the SW list */
6871 static int
6872 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6873                              struct i40e_tunnel_filter *tunnel_filter)
6874 {
6875         struct i40e_tunnel_rule *rule = &pf->tunnel;
6876         int ret;
6877
6878         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6879         if (ret < 0) {
6880                 PMD_DRV_LOG(ERR,
6881                             "Failed to insert tunnel filter to hash table %d!",
6882                             ret);
6883                 return ret;
6884         }
6885         rule->hash_map[ret] = tunnel_filter;
6886
6887         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6888
6889         return 0;
6890 }
6891
6892 /* Delete a tunnel filter from the SW list */
6893 int
6894 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6895                           struct i40e_tunnel_filter_input *input)
6896 {
6897         struct i40e_tunnel_rule *rule = &pf->tunnel;
6898         struct i40e_tunnel_filter *tunnel_filter;
6899         int ret;
6900
6901         ret = rte_hash_del_key(rule->hash_table, input);
6902         if (ret < 0) {
6903                 PMD_DRV_LOG(ERR,
6904                             "Failed to delete tunnel filter to hash table %d!",
6905                             ret);
6906                 return ret;
6907         }
6908         tunnel_filter = rule->hash_map[ret];
6909         rule->hash_map[ret] = NULL;
6910
6911         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6912         rte_free(tunnel_filter);
6913
6914         return 0;
6915 }
6916
6917 int
6918 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6919                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6920                         uint8_t add)
6921 {
6922         uint16_t ip_type;
6923         uint32_t ipv4_addr;
6924         uint8_t i, tun_type = 0;
6925         /* internal varialbe to convert ipv6 byte order */
6926         uint32_t convert_ipv6[4];
6927         int val, ret = 0;
6928         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6929         struct i40e_vsi *vsi = pf->main_vsi;
6930         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6931         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6932         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6933         struct i40e_tunnel_filter *tunnel, *node;
6934         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6935
6936         cld_filter = rte_zmalloc("tunnel_filter",
6937                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6938         0);
6939
6940         if (NULL == cld_filter) {
6941                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6942                 return -ENOMEM;
6943         }
6944         pfilter = cld_filter;
6945
6946         ether_addr_copy(&tunnel_filter->outer_mac,
6947                         (struct ether_addr *)&pfilter->element.outer_mac);
6948         ether_addr_copy(&tunnel_filter->inner_mac,
6949                         (struct ether_addr *)&pfilter->element.inner_mac);
6950
6951         pfilter->element.inner_vlan =
6952                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6953         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6954                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6955                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6956                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6957                                 &rte_cpu_to_le_32(ipv4_addr),
6958                                 sizeof(pfilter->element.ipaddr.v4.data));
6959         } else {
6960                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6961                 for (i = 0; i < 4; i++) {
6962                         convert_ipv6[i] =
6963                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6964                 }
6965                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6966                            &convert_ipv6,
6967                            sizeof(pfilter->element.ipaddr.v6.data));
6968         }
6969
6970         /* check tunneled type */
6971         switch (tunnel_filter->tunnel_type) {
6972         case RTE_TUNNEL_TYPE_VXLAN:
6973                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6974                 break;
6975         case RTE_TUNNEL_TYPE_NVGRE:
6976                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6977                 break;
6978         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6979                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6980                 break;
6981         default:
6982                 /* Other tunnel types is not supported. */
6983                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6984                 rte_free(cld_filter);
6985                 return -EINVAL;
6986         }
6987
6988         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6989                                        &pfilter->element.flags);
6990         if (val < 0) {
6991                 rte_free(cld_filter);
6992                 return -EINVAL;
6993         }
6994
6995         pfilter->element.flags |= rte_cpu_to_le_16(
6996                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6997                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6998         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6999         pfilter->element.queue_number =
7000                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7001
7002         /* Check if there is the filter in SW list */
7003         memset(&check_filter, 0, sizeof(check_filter));
7004         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7005         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7006         if (add && node) {
7007                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7008                 return -EINVAL;
7009         }
7010
7011         if (!add && !node) {
7012                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7013                 return -EINVAL;
7014         }
7015
7016         if (add) {
7017                 ret = i40e_aq_add_cloud_filters(hw,
7018                                         vsi->seid, &cld_filter->element, 1);
7019                 if (ret < 0) {
7020                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7021                         return -ENOTSUP;
7022                 }
7023                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7024                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7025                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7026         } else {
7027                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7028                                                    &cld_filter->element, 1);
7029                 if (ret < 0) {
7030                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7031                         return -ENOTSUP;
7032                 }
7033                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7034         }
7035
7036         rte_free(cld_filter);
7037         return ret;
7038 }
7039
7040 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7041 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7042 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7043 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7044 #define I40E_TR_GRE_KEY_MASK                    0x400
7045 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7046 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7047
7048 static enum
7049 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7050 {
7051         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7052         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7053         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7054         enum i40e_status_code status = I40E_SUCCESS;
7055
7056         memset(&filter_replace, 0,
7057                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7058         memset(&filter_replace_buf, 0,
7059                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7060
7061         /* create L1 filter */
7062         filter_replace.old_filter_type =
7063                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7064         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7065         filter_replace.tr_bit = 0;
7066
7067         /* Prepare the buffer, 3 entries */
7068         filter_replace_buf.data[0] =
7069                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7070         filter_replace_buf.data[0] |=
7071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7072         filter_replace_buf.data[2] = 0xFF;
7073         filter_replace_buf.data[3] = 0xFF;
7074         filter_replace_buf.data[4] =
7075                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7076         filter_replace_buf.data[4] |=
7077                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7078         filter_replace_buf.data[7] = 0xF0;
7079         filter_replace_buf.data[8]
7080                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7081         filter_replace_buf.data[8] |=
7082                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7083         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7084                 I40E_TR_GENEVE_KEY_MASK |
7085                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7086         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7087                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7088                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7089
7090         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7091                                                &filter_replace_buf);
7092         return status;
7093 }
7094
7095 static enum
7096 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7097 {
7098         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7099         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7100         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7101         enum i40e_status_code status = I40E_SUCCESS;
7102
7103         /* For MPLSoUDP */
7104         memset(&filter_replace, 0,
7105                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7106         memset(&filter_replace_buf, 0,
7107                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7108         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7109                 I40E_AQC_MIRROR_CLOUD_FILTER;
7110         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7111         filter_replace.new_filter_type =
7112                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7113         /* Prepare the buffer, 2 entries */
7114         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7115         filter_replace_buf.data[0] |=
7116                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7117         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7118         filter_replace_buf.data[4] |=
7119                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7120         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7121                                                &filter_replace_buf);
7122         if (status < 0)
7123                 return status;
7124
7125         /* For MPLSoGRE */
7126         memset(&filter_replace, 0,
7127                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7128         memset(&filter_replace_buf, 0,
7129                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7130
7131         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7132                 I40E_AQC_MIRROR_CLOUD_FILTER;
7133         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7134         filter_replace.new_filter_type =
7135                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7136         /* Prepare the buffer, 2 entries */
7137         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7138         filter_replace_buf.data[0] |=
7139                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7140         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7141         filter_replace_buf.data[4] |=
7142                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7143
7144         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7145                                                &filter_replace_buf);
7146         return status;
7147 }
7148
7149 int
7150 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7151                       struct i40e_tunnel_filter_conf *tunnel_filter,
7152                       uint8_t add)
7153 {
7154         uint16_t ip_type;
7155         uint32_t ipv4_addr;
7156         uint8_t i, tun_type = 0;
7157         /* internal variable to convert ipv6 byte order */
7158         uint32_t convert_ipv6[4];
7159         int val, ret = 0;
7160         struct i40e_pf_vf *vf = NULL;
7161         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7162         struct i40e_vsi *vsi;
7163         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7164         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7165         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7166         struct i40e_tunnel_filter *tunnel, *node;
7167         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7168         uint32_t teid_le;
7169         bool big_buffer = 0;
7170
7171         cld_filter = rte_zmalloc("tunnel_filter",
7172                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7173                          0);
7174
7175         if (cld_filter == NULL) {
7176                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7177                 return -ENOMEM;
7178         }
7179         pfilter = cld_filter;
7180
7181         ether_addr_copy(&tunnel_filter->outer_mac,
7182                         (struct ether_addr *)&pfilter->element.outer_mac);
7183         ether_addr_copy(&tunnel_filter->inner_mac,
7184                         (struct ether_addr *)&pfilter->element.inner_mac);
7185
7186         pfilter->element.inner_vlan =
7187                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7188         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7189                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7190                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7191                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7192                                 &rte_cpu_to_le_32(ipv4_addr),
7193                                 sizeof(pfilter->element.ipaddr.v4.data));
7194         } else {
7195                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7196                 for (i = 0; i < 4; i++) {
7197                         convert_ipv6[i] =
7198                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7199                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7200                 }
7201                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7202                            &convert_ipv6,
7203                            sizeof(pfilter->element.ipaddr.v6.data));
7204         }
7205
7206         /* check tunneled type */
7207         switch (tunnel_filter->tunnel_type) {
7208         case I40E_TUNNEL_TYPE_VXLAN:
7209                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7210                 break;
7211         case I40E_TUNNEL_TYPE_NVGRE:
7212                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7213                 break;
7214         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7215                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7216                 break;
7217         case I40E_TUNNEL_TYPE_MPLSoUDP:
7218                 if (!pf->mpls_replace_flag) {
7219                         i40e_replace_mpls_l1_filter(pf);
7220                         i40e_replace_mpls_cloud_filter(pf);
7221                         pf->mpls_replace_flag = 1;
7222                 }
7223                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7224                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7225                         teid_le >> 4;
7226                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7227                         (teid_le & 0xF) << 12;
7228                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7229                         0x40;
7230                 big_buffer = 1;
7231                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7232                 break;
7233         case I40E_TUNNEL_TYPE_MPLSoGRE:
7234                 if (!pf->mpls_replace_flag) {
7235                         i40e_replace_mpls_l1_filter(pf);
7236                         i40e_replace_mpls_cloud_filter(pf);
7237                         pf->mpls_replace_flag = 1;
7238                 }
7239                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7240                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7241                         teid_le >> 4;
7242                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7243                         (teid_le & 0xF) << 12;
7244                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7245                         0x0;
7246                 big_buffer = 1;
7247                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7248                 break;
7249         case I40E_TUNNEL_TYPE_QINQ:
7250                 if (!pf->qinq_replace_flag) {
7251                         ret = i40e_cloud_filter_qinq_create(pf);
7252                         if (ret < 0)
7253                                 PMD_DRV_LOG(DEBUG,
7254                                             "QinQ tunnel filter already created.");
7255                         pf->qinq_replace_flag = 1;
7256                 }
7257                 /*      Add in the General fields the values of
7258                  *      the Outer and Inner VLAN
7259                  *      Big Buffer should be set, see changes in
7260                  *      i40e_aq_add_cloud_filters
7261                  */
7262                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7263                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7264                 big_buffer = 1;
7265                 break;
7266         default:
7267                 /* Other tunnel types is not supported. */
7268                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7269                 rte_free(cld_filter);
7270                 return -EINVAL;
7271         }
7272
7273         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7274                 pfilter->element.flags =
7275                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7276         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7277                 pfilter->element.flags =
7278                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7279         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7280                 pfilter->element.flags |=
7281                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7282         else {
7283                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7284                                                 &pfilter->element.flags);
7285                 if (val < 0) {
7286                         rte_free(cld_filter);
7287                         return -EINVAL;
7288                 }
7289         }
7290
7291         pfilter->element.flags |= rte_cpu_to_le_16(
7292                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7293                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7294         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7295         pfilter->element.queue_number =
7296                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7297
7298         if (!tunnel_filter->is_to_vf)
7299                 vsi = pf->main_vsi;
7300         else {
7301                 if (tunnel_filter->vf_id >= pf->vf_num) {
7302                         PMD_DRV_LOG(ERR, "Invalid argument.");
7303                         return -EINVAL;
7304                 }
7305                 vf = &pf->vfs[tunnel_filter->vf_id];
7306                 vsi = vf->vsi;
7307         }
7308
7309         /* Check if there is the filter in SW list */
7310         memset(&check_filter, 0, sizeof(check_filter));
7311         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7312         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7313         check_filter.vf_id = tunnel_filter->vf_id;
7314         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7315         if (add && node) {
7316                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7317                 return -EINVAL;
7318         }
7319
7320         if (!add && !node) {
7321                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7322                 return -EINVAL;
7323         }
7324
7325         if (add) {
7326                 if (big_buffer)
7327                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7328                                                    vsi->seid, cld_filter, 1);
7329                 else
7330                         ret = i40e_aq_add_cloud_filters(hw,
7331                                         vsi->seid, &cld_filter->element, 1);
7332                 if (ret < 0) {
7333                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7334                         return -ENOTSUP;
7335                 }
7336                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7337                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7338                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7339         } else {
7340                 if (big_buffer)
7341                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7342                                 hw, vsi->seid, cld_filter, 1);
7343                 else
7344                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7345                                                    &cld_filter->element, 1);
7346                 if (ret < 0) {
7347                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7348                         return -ENOTSUP;
7349                 }
7350                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7351         }
7352
7353         rte_free(cld_filter);
7354         return ret;
7355 }
7356
7357 static int
7358 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7359 {
7360         uint8_t i;
7361
7362         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7363                 if (pf->vxlan_ports[i] == port)
7364                         return i;
7365         }
7366
7367         return -1;
7368 }
7369
7370 static int
7371 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7372 {
7373         int  idx, ret;
7374         uint8_t filter_idx;
7375         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7376
7377         idx = i40e_get_vxlan_port_idx(pf, port);
7378
7379         /* Check if port already exists */
7380         if (idx >= 0) {
7381                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7382                 return -EINVAL;
7383         }
7384
7385         /* Now check if there is space to add the new port */
7386         idx = i40e_get_vxlan_port_idx(pf, 0);
7387         if (idx < 0) {
7388                 PMD_DRV_LOG(ERR,
7389                         "Maximum number of UDP ports reached, not adding port %d",
7390                         port);
7391                 return -ENOSPC;
7392         }
7393
7394         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7395                                         &filter_idx, NULL);
7396         if (ret < 0) {
7397                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7398                 return -1;
7399         }
7400
7401         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7402                          port,  filter_idx);
7403
7404         /* New port: add it and mark its index in the bitmap */
7405         pf->vxlan_ports[idx] = port;
7406         pf->vxlan_bitmap |= (1 << idx);
7407
7408         if (!(pf->flags & I40E_FLAG_VXLAN))
7409                 pf->flags |= I40E_FLAG_VXLAN;
7410
7411         return 0;
7412 }
7413
7414 static int
7415 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7416 {
7417         int idx;
7418         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7419
7420         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7421                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7422                 return -EINVAL;
7423         }
7424
7425         idx = i40e_get_vxlan_port_idx(pf, port);
7426
7427         if (idx < 0) {
7428                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7429                 return -EINVAL;
7430         }
7431
7432         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7433                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7434                 return -1;
7435         }
7436
7437         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7438                         port, idx);
7439
7440         pf->vxlan_ports[idx] = 0;
7441         pf->vxlan_bitmap &= ~(1 << idx);
7442
7443         if (!pf->vxlan_bitmap)
7444                 pf->flags &= ~I40E_FLAG_VXLAN;
7445
7446         return 0;
7447 }
7448
7449 /* Add UDP tunneling port */
7450 static int
7451 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7452                              struct rte_eth_udp_tunnel *udp_tunnel)
7453 {
7454         int ret = 0;
7455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7456
7457         if (udp_tunnel == NULL)
7458                 return -EINVAL;
7459
7460         switch (udp_tunnel->prot_type) {
7461         case RTE_TUNNEL_TYPE_VXLAN:
7462                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7463                 break;
7464
7465         case RTE_TUNNEL_TYPE_GENEVE:
7466         case RTE_TUNNEL_TYPE_TEREDO:
7467                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7468                 ret = -1;
7469                 break;
7470
7471         default:
7472                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7473                 ret = -1;
7474                 break;
7475         }
7476
7477         return ret;
7478 }
7479
7480 /* Remove UDP tunneling port */
7481 static int
7482 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7483                              struct rte_eth_udp_tunnel *udp_tunnel)
7484 {
7485         int ret = 0;
7486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7487
7488         if (udp_tunnel == NULL)
7489                 return -EINVAL;
7490
7491         switch (udp_tunnel->prot_type) {
7492         case RTE_TUNNEL_TYPE_VXLAN:
7493                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7494                 break;
7495         case RTE_TUNNEL_TYPE_GENEVE:
7496         case RTE_TUNNEL_TYPE_TEREDO:
7497                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7498                 ret = -1;
7499                 break;
7500         default:
7501                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7502                 ret = -1;
7503                 break;
7504         }
7505
7506         return ret;
7507 }
7508
7509 /* Calculate the maximum number of contiguous PF queues that are configured */
7510 static int
7511 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7512 {
7513         struct rte_eth_dev_data *data = pf->dev_data;
7514         int i, num;
7515         struct i40e_rx_queue *rxq;
7516
7517         num = 0;
7518         for (i = 0; i < pf->lan_nb_qps; i++) {
7519                 rxq = data->rx_queues[i];
7520                 if (rxq && rxq->q_set)
7521                         num++;
7522                 else
7523                         break;
7524         }
7525
7526         return num;
7527 }
7528
7529 /* Configure RSS */
7530 static int
7531 i40e_pf_config_rss(struct i40e_pf *pf)
7532 {
7533         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7534         struct rte_eth_rss_conf rss_conf;
7535         uint32_t i, lut = 0;
7536         uint16_t j, num;
7537
7538         /*
7539          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7540          * It's necessary to calculate the actual PF queues that are configured.
7541          */
7542         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7543                 num = i40e_pf_calc_configured_queues_num(pf);
7544         else
7545                 num = pf->dev_data->nb_rx_queues;
7546
7547         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7548         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7549                         num);
7550
7551         if (num == 0) {
7552                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7553                 return -ENOTSUP;
7554         }
7555
7556         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7557                 if (j == num)
7558                         j = 0;
7559                 lut = (lut << 8) | (j & ((0x1 <<
7560                         hw->func_caps.rss_table_entry_width) - 1));
7561                 if ((i & 3) == 3)
7562                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7563         }
7564
7565         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7566         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7567                 i40e_pf_disable_rss(pf);
7568                 return 0;
7569         }
7570         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7571                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7572                 /* Random default keys */
7573                 static uint32_t rss_key_default[] = {0x6b793944,
7574                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7575                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7576                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7577
7578                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7579                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7580                                                         sizeof(uint32_t);
7581         }
7582
7583         return i40e_hw_rss_hash_set(pf, &rss_conf);
7584 }
7585
7586 static int
7587 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7588                                struct rte_eth_tunnel_filter_conf *filter)
7589 {
7590         if (pf == NULL || filter == NULL) {
7591                 PMD_DRV_LOG(ERR, "Invalid parameter");
7592                 return -EINVAL;
7593         }
7594
7595         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7596                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7597                 return -EINVAL;
7598         }
7599
7600         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7601                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7602                 return -EINVAL;
7603         }
7604
7605         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7606                 (is_zero_ether_addr(&filter->outer_mac))) {
7607                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7608                 return -EINVAL;
7609         }
7610
7611         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7612                 (is_zero_ether_addr(&filter->inner_mac))) {
7613                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7614                 return -EINVAL;
7615         }
7616
7617         return 0;
7618 }
7619
7620 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7621 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7622 static int
7623 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7624 {
7625         uint32_t val, reg;
7626         int ret = -EINVAL;
7627
7628         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7629         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7630
7631         if (len == 3) {
7632                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7633         } else if (len == 4) {
7634                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7635         } else {
7636                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7637                 return ret;
7638         }
7639
7640         if (reg != val) {
7641                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7642                                                    reg, NULL);
7643                 if (ret != 0)
7644                         return ret;
7645         } else {
7646                 ret = 0;
7647         }
7648         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7649                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7650
7651         return ret;
7652 }
7653
7654 static int
7655 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7656 {
7657         int ret = -EINVAL;
7658
7659         if (!hw || !cfg)
7660                 return -EINVAL;
7661
7662         switch (cfg->cfg_type) {
7663         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7664                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7665                 break;
7666         default:
7667                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7668                 break;
7669         }
7670
7671         return ret;
7672 }
7673
7674 static int
7675 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7676                                enum rte_filter_op filter_op,
7677                                void *arg)
7678 {
7679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7680         int ret = I40E_ERR_PARAM;
7681
7682         switch (filter_op) {
7683         case RTE_ETH_FILTER_SET:
7684                 ret = i40e_dev_global_config_set(hw,
7685                         (struct rte_eth_global_cfg *)arg);
7686                 break;
7687         default:
7688                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7689                 break;
7690         }
7691
7692         return ret;
7693 }
7694
7695 static int
7696 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7697                           enum rte_filter_op filter_op,
7698                           void *arg)
7699 {
7700         struct rte_eth_tunnel_filter_conf *filter;
7701         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7702         int ret = I40E_SUCCESS;
7703
7704         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7705
7706         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7707                 return I40E_ERR_PARAM;
7708
7709         switch (filter_op) {
7710         case RTE_ETH_FILTER_NOP:
7711                 if (!(pf->flags & I40E_FLAG_VXLAN))
7712                         ret = I40E_NOT_SUPPORTED;
7713                 break;
7714         case RTE_ETH_FILTER_ADD:
7715                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7716                 break;
7717         case RTE_ETH_FILTER_DELETE:
7718                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7719                 break;
7720         default:
7721                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7722                 ret = I40E_ERR_PARAM;
7723                 break;
7724         }
7725
7726         return ret;
7727 }
7728
7729 static int
7730 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7731 {
7732         int ret = 0;
7733         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7734
7735         /* RSS setup */
7736         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7737                 ret = i40e_pf_config_rss(pf);
7738         else
7739                 i40e_pf_disable_rss(pf);
7740
7741         return ret;
7742 }
7743
7744 /* Get the symmetric hash enable configurations per port */
7745 static void
7746 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7747 {
7748         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7749
7750         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7751 }
7752
7753 /* Set the symmetric hash enable configurations per port */
7754 static void
7755 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7756 {
7757         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7758
7759         if (enable > 0) {
7760                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7761                         PMD_DRV_LOG(INFO,
7762                                 "Symmetric hash has already been enabled");
7763                         return;
7764                 }
7765                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7766         } else {
7767                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7768                         PMD_DRV_LOG(INFO,
7769                                 "Symmetric hash has already been disabled");
7770                         return;
7771                 }
7772                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7773         }
7774         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7775         I40E_WRITE_FLUSH(hw);
7776 }
7777
7778 /*
7779  * Get global configurations of hash function type and symmetric hash enable
7780  * per flow type (pctype). Note that global configuration means it affects all
7781  * the ports on the same NIC.
7782  */
7783 static int
7784 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7785                                    struct rte_eth_hash_global_conf *g_cfg)
7786 {
7787         uint32_t reg, mask = I40E_FLOW_TYPES;
7788         uint16_t i;
7789         enum i40e_filter_pctype pctype;
7790
7791         memset(g_cfg, 0, sizeof(*g_cfg));
7792         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7793         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7794                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7795         else
7796                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7797         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7798                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7799
7800         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7801                 if (!(mask & (1UL << i)))
7802                         continue;
7803                 mask &= ~(1UL << i);
7804                 /* Bit set indicats the coresponding flow type is supported */
7805                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7806                 /* if flowtype is invalid, continue */
7807                 if (!I40E_VALID_FLOW(i))
7808                         continue;
7809                 pctype = i40e_flowtype_to_pctype(i);
7810                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7811                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7812                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7813         }
7814
7815         return 0;
7816 }
7817
7818 static int
7819 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7820 {
7821         uint32_t i;
7822         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7823
7824         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7825                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7826                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7827                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7828                                                 g_cfg->hash_func);
7829                 return -EINVAL;
7830         }
7831
7832         /*
7833          * As i40e supports less than 32 flow types, only first 32 bits need to
7834          * be checked.
7835          */
7836         mask0 = g_cfg->valid_bit_mask[0];
7837         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7838                 if (i == 0) {
7839                         /* Check if any unsupported flow type configured */
7840                         if ((mask0 | i40e_mask) ^ i40e_mask)
7841                                 goto mask_err;
7842                 } else {
7843                         if (g_cfg->valid_bit_mask[i])
7844                                 goto mask_err;
7845                 }
7846         }
7847
7848         return 0;
7849
7850 mask_err:
7851         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7852
7853         return -EINVAL;
7854 }
7855
7856 /*
7857  * Set global configurations of hash function type and symmetric hash enable
7858  * per flow type (pctype). Note any modifying global configuration will affect
7859  * all the ports on the same NIC.
7860  */
7861 static int
7862 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7863                                    struct rte_eth_hash_global_conf *g_cfg)
7864 {
7865         int ret;
7866         uint16_t i;
7867         uint32_t reg;
7868         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7869         enum i40e_filter_pctype pctype;
7870
7871         /* Check the input parameters */
7872         ret = i40e_hash_global_config_check(g_cfg);
7873         if (ret < 0)
7874                 return ret;
7875
7876         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7877                 if (!(mask0 & (1UL << i)))
7878                         continue;
7879                 mask0 &= ~(1UL << i);
7880                 /* if flowtype is invalid, continue */
7881                 if (!I40E_VALID_FLOW(i))
7882                         continue;
7883                 pctype = i40e_flowtype_to_pctype(i);
7884                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7885                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7886                 if (hw->mac.type == I40E_MAC_X722) {
7887                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7888                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7889                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7890                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7891                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7892                                   reg);
7893                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7894                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7895                                   reg);
7896                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7897                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7898                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7899                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7900                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7901                                   reg);
7902                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7903                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7904                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7905                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7906                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7907                                   reg);
7908                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7909                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7910                                   reg);
7911                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7912                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7913                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7914                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7915                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7916                                   reg);
7917                         } else {
7918                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7919                                   reg);
7920                         }
7921                 } else {
7922                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7923                 }
7924         }
7925
7926         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7927         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7928                 /* Toeplitz */
7929                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7930                         PMD_DRV_LOG(DEBUG,
7931                                 "Hash function already set to Toeplitz");
7932                         goto out;
7933                 }
7934                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7935         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7936                 /* Simple XOR */
7937                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7938                         PMD_DRV_LOG(DEBUG,
7939                                 "Hash function already set to Simple XOR");
7940                         goto out;
7941                 }
7942                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7943         } else
7944                 /* Use the default, and keep it as it is */
7945                 goto out;
7946
7947         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7948
7949 out:
7950         I40E_WRITE_FLUSH(hw);
7951
7952         return 0;
7953 }
7954
7955 /**
7956  * Valid input sets for hash and flow director filters per PCTYPE
7957  */
7958 static uint64_t
7959 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7960                 enum rte_filter_type filter)
7961 {
7962         uint64_t valid;
7963
7964         static const uint64_t valid_hash_inset_table[] = {
7965                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7966                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7967                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7968                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7969                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7970                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7971                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7972                         I40E_INSET_FLEX_PAYLOAD,
7973                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7974                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7975                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7976                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7977                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7978                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7979                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7980                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7981                         I40E_INSET_FLEX_PAYLOAD,
7982                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7983                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7984                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7985                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7986                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7987                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7988                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7989                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7990                         I40E_INSET_FLEX_PAYLOAD,
7991                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7992                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7993                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7994                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7995                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7996                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7997                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7998                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7999                         I40E_INSET_FLEX_PAYLOAD,
8000                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8001                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8002                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8003                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8004                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8005                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8006                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8007                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8008                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8009                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8010                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8011                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8012                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8013                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8014                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8015                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8016                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8017                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8018                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8019                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8020                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8022                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8023                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8024                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8026                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8027                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8028                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8029                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8031                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8032                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8033                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8034                         I40E_INSET_FLEX_PAYLOAD,
8035                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8036                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8037                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8038                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8039                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8040                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8041                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8042                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8043                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8044                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8045                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8046                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8047                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8048                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8049                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8050                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8051                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8052                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8053                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8054                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8055                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8056                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8057                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8058                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8059                         I40E_INSET_FLEX_PAYLOAD,
8060                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8061                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8062                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8063                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8064                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8065                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8066                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8067                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8068                         I40E_INSET_FLEX_PAYLOAD,
8069                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8070                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8071                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8072                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8073                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8074                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8075                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8076                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8077                         I40E_INSET_FLEX_PAYLOAD,
8078                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8079                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8080                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8081                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8082                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8083                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8084                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8085                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8086                         I40E_INSET_FLEX_PAYLOAD,
8087                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8088                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8089                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8090                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8091                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8092                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8093                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8094                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8095                         I40E_INSET_FLEX_PAYLOAD,
8096                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8100                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8101                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8102                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8103                         I40E_INSET_FLEX_PAYLOAD,
8104                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8105                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8106                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8107                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8108                         I40E_INSET_FLEX_PAYLOAD,
8109         };
8110
8111         /**
8112          * Flow director supports only fields defined in
8113          * union rte_eth_fdir_flow.
8114          */
8115         static const uint64_t valid_fdir_inset_table[] = {
8116                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8117                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8119                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8120                 I40E_INSET_IPV4_TTL,
8121                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8122                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8123                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8124                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8125                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8126                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8127                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8128                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8129                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8130                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8131                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8132                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8133                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8134                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8135                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8136                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8137                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8138                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8140                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8142                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8143                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8144                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8145                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8146                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8147                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8148                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8150                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8151                 I40E_INSET_SCTP_VT,
8152                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8153                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8154                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8155                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8156                 I40E_INSET_IPV4_TTL,
8157                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8158                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8159                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8160                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8161                 I40E_INSET_IPV6_HOP_LIMIT,
8162                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8163                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8164                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8165                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8166                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8167                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8169                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8170                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8171                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8172                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8173                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8174                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8175                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8176                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8177                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8178                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8180                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8181                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8182                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8183                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8185                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8186                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8188                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8190                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8191                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8192                 I40E_INSET_SCTP_VT,
8193                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8194                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8195                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8196                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8197                 I40E_INSET_IPV6_HOP_LIMIT,
8198                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8199                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8200                 I40E_INSET_LAST_ETHER_TYPE,
8201         };
8202
8203         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8204                 return 0;
8205         if (filter == RTE_ETH_FILTER_HASH)
8206                 valid = valid_hash_inset_table[pctype];
8207         else
8208                 valid = valid_fdir_inset_table[pctype];
8209
8210         return valid;
8211 }
8212
8213 /**
8214  * Validate if the input set is allowed for a specific PCTYPE
8215  */
8216 int
8217 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8218                 enum rte_filter_type filter, uint64_t inset)
8219 {
8220         uint64_t valid;
8221
8222         valid = i40e_get_valid_input_set(pctype, filter);
8223         if (inset & (~valid))
8224                 return -EINVAL;
8225
8226         return 0;
8227 }
8228
8229 /* default input set fields combination per pctype */
8230 uint64_t
8231 i40e_get_default_input_set(uint16_t pctype)
8232 {
8233         static const uint64_t default_inset_table[] = {
8234                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8235                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8236                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8237                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8238                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8240                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8241                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8242                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8243                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8244                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8245                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8246                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8247                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8248                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8249                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8250                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8251                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8252                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8253                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8254                         I40E_INSET_SCTP_VT,
8255                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8256                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8257                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8258                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8259                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8260                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8261                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8262                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8263                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8264                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8265                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8266                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8267                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8268                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8269                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8270                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8271                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8272                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8273                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8274                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8275                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8276                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8277                         I40E_INSET_SCTP_VT,
8278                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8279                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8280                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8281                         I40E_INSET_LAST_ETHER_TYPE,
8282         };
8283
8284         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8285                 return 0;
8286
8287         return default_inset_table[pctype];
8288 }
8289
8290 /**
8291  * Parse the input set from index to logical bit masks
8292  */
8293 static int
8294 i40e_parse_input_set(uint64_t *inset,
8295                      enum i40e_filter_pctype pctype,
8296                      enum rte_eth_input_set_field *field,
8297                      uint16_t size)
8298 {
8299         uint16_t i, j;
8300         int ret = -EINVAL;
8301
8302         static const struct {
8303                 enum rte_eth_input_set_field field;
8304                 uint64_t inset;
8305         } inset_convert_table[] = {
8306                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8307                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8308                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8309                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8310                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8311                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8312                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8313                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8314                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8315                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8316                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8317                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8318                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8319                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8320                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8321                         I40E_INSET_IPV6_NEXT_HDR},
8322                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8323                         I40E_INSET_IPV6_HOP_LIMIT},
8324                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8325                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8326                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8327                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8328                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8329                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8330                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8331                         I40E_INSET_SCTP_VT},
8332                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8333                         I40E_INSET_TUNNEL_DMAC},
8334                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8335                         I40E_INSET_VLAN_TUNNEL},
8336                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8337                         I40E_INSET_TUNNEL_ID},
8338                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8339                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8340                         I40E_INSET_FLEX_PAYLOAD_W1},
8341                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8342                         I40E_INSET_FLEX_PAYLOAD_W2},
8343                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8344                         I40E_INSET_FLEX_PAYLOAD_W3},
8345                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8346                         I40E_INSET_FLEX_PAYLOAD_W4},
8347                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8348                         I40E_INSET_FLEX_PAYLOAD_W5},
8349                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8350                         I40E_INSET_FLEX_PAYLOAD_W6},
8351                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8352                         I40E_INSET_FLEX_PAYLOAD_W7},
8353                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8354                         I40E_INSET_FLEX_PAYLOAD_W8},
8355         };
8356
8357         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8358                 return ret;
8359
8360         /* Only one item allowed for default or all */
8361         if (size == 1) {
8362                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8363                         *inset = i40e_get_default_input_set(pctype);
8364                         return 0;
8365                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8366                         *inset = I40E_INSET_NONE;
8367                         return 0;
8368                 }
8369         }
8370
8371         for (i = 0, *inset = 0; i < size; i++) {
8372                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8373                         if (field[i] == inset_convert_table[j].field) {
8374                                 *inset |= inset_convert_table[j].inset;
8375                                 break;
8376                         }
8377                 }
8378
8379                 /* It contains unsupported input set, return immediately */
8380                 if (j == RTE_DIM(inset_convert_table))
8381                         return ret;
8382         }
8383
8384         return 0;
8385 }
8386
8387 /**
8388  * Translate the input set from bit masks to register aware bit masks
8389  * and vice versa
8390  */
8391 uint64_t
8392 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8393 {
8394         uint64_t val = 0;
8395         uint16_t i;
8396
8397         struct inset_map {
8398                 uint64_t inset;
8399                 uint64_t inset_reg;
8400         };
8401
8402         static const struct inset_map inset_map_common[] = {
8403                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8404                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8405                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8406                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8407                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8408                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8409                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8410                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8411                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8412                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8413                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8414                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8415                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8416                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8417                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8418                 {I40E_INSET_TUNNEL_DMAC,
8419                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8420                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8421                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8422                 {I40E_INSET_TUNNEL_SRC_PORT,
8423                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8424                 {I40E_INSET_TUNNEL_DST_PORT,
8425                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8426                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8427                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8428                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8429                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8430                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8431                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8432                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8433                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8434                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8435         };
8436
8437     /* some different registers map in x722*/
8438         static const struct inset_map inset_map_diff_x722[] = {
8439                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8440                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8441                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8442                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8443         };
8444
8445         static const struct inset_map inset_map_diff_not_x722[] = {
8446                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8447                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8448                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8449                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8450         };
8451
8452         if (input == 0)
8453                 return val;
8454
8455         /* Translate input set to register aware inset */
8456         if (type == I40E_MAC_X722) {
8457                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8458                         if (input & inset_map_diff_x722[i].inset)
8459                                 val |= inset_map_diff_x722[i].inset_reg;
8460                 }
8461         } else {
8462                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8463                         if (input & inset_map_diff_not_x722[i].inset)
8464                                 val |= inset_map_diff_not_x722[i].inset_reg;
8465                 }
8466         }
8467
8468         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8469                 if (input & inset_map_common[i].inset)
8470                         val |= inset_map_common[i].inset_reg;
8471         }
8472
8473         return val;
8474 }
8475
8476 int
8477 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8478 {
8479         uint8_t i, idx = 0;
8480         uint64_t inset_need_mask = inset;
8481
8482         static const struct {
8483                 uint64_t inset;
8484                 uint32_t mask;
8485         } inset_mask_map[] = {
8486                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8487                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8488                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8489                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8490                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8491                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8492                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8493                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8494         };
8495
8496         if (!inset || !mask || !nb_elem)
8497                 return 0;
8498
8499         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8500                 /* Clear the inset bit, if no MASK is required,
8501                  * for example proto + ttl
8502                  */
8503                 if ((inset & inset_mask_map[i].inset) ==
8504                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8505                         inset_need_mask &= ~inset_mask_map[i].inset;
8506                 if (!inset_need_mask)
8507                         return 0;
8508         }
8509         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8510                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8511                     inset_mask_map[i].inset) {
8512                         if (idx >= nb_elem) {
8513                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8514                                 return -EINVAL;
8515                         }
8516                         mask[idx] = inset_mask_map[i].mask;
8517                         idx++;
8518                 }
8519         }
8520
8521         return idx;
8522 }
8523
8524 void
8525 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8526 {
8527         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8528
8529         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8530         if (reg != val)
8531                 i40e_write_rx_ctl(hw, addr, val);
8532         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8533                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8534 }
8535
8536 static void
8537 i40e_filter_input_set_init(struct i40e_pf *pf)
8538 {
8539         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8540         enum i40e_filter_pctype pctype;
8541         uint64_t input_set, inset_reg;
8542         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8543         int num, i;
8544
8545         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8546              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8547                 if (hw->mac.type == I40E_MAC_X722) {
8548                         if (!I40E_VALID_PCTYPE_X722(pctype))
8549                                 continue;
8550                 } else {
8551                         if (!I40E_VALID_PCTYPE(pctype))
8552                                 continue;
8553                 }
8554
8555                 input_set = i40e_get_default_input_set(pctype);
8556
8557                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8558                                                    I40E_INSET_MASK_NUM_REG);
8559                 if (num < 0)
8560                         return;
8561                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8562                                         input_set);
8563
8564                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8565                                       (uint32_t)(inset_reg & UINT32_MAX));
8566                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8567                                      (uint32_t)((inset_reg >>
8568                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8569                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8570                                       (uint32_t)(inset_reg & UINT32_MAX));
8571                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8572                                      (uint32_t)((inset_reg >>
8573                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8574
8575                 for (i = 0; i < num; i++) {
8576                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8577                                              mask_reg[i]);
8578                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8579                                              mask_reg[i]);
8580                 }
8581                 /*clear unused mask registers of the pctype */
8582                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8583                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8584                                              0);
8585                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8586                                              0);
8587                 }
8588                 I40E_WRITE_FLUSH(hw);
8589
8590                 /* store the default input set */
8591                 pf->hash_input_set[pctype] = input_set;
8592                 pf->fdir.input_set[pctype] = input_set;
8593         }
8594 }
8595
8596 int
8597 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8598                          struct rte_eth_input_set_conf *conf)
8599 {
8600         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8601         enum i40e_filter_pctype pctype;
8602         uint64_t input_set, inset_reg = 0;
8603         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8604         int ret, i, num;
8605
8606         if (!conf) {
8607                 PMD_DRV_LOG(ERR, "Invalid pointer");
8608                 return -EFAULT;
8609         }
8610         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8611             conf->op != RTE_ETH_INPUT_SET_ADD) {
8612                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8613                 return -EINVAL;
8614         }
8615
8616         if (!I40E_VALID_FLOW(conf->flow_type)) {
8617                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8618                 return -EINVAL;
8619         }
8620
8621         if (hw->mac.type == I40E_MAC_X722) {
8622                 /* get translated pctype value in fd pctype register */
8623                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8624                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8625                         conf->flow_type)));
8626         } else
8627                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8628
8629         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8630                                    conf->inset_size);
8631         if (ret) {
8632                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8633                 return -EINVAL;
8634         }
8635         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8636                                     input_set) != 0) {
8637                 PMD_DRV_LOG(ERR, "Invalid input set");
8638                 return -EINVAL;
8639         }
8640         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8641                 /* get inset value in register */
8642                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8643                 inset_reg <<= I40E_32_BIT_WIDTH;
8644                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8645                 input_set |= pf->hash_input_set[pctype];
8646         }
8647         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8648                                            I40E_INSET_MASK_NUM_REG);
8649         if (num < 0)
8650                 return -EINVAL;
8651
8652         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8653
8654         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8655                               (uint32_t)(inset_reg & UINT32_MAX));
8656         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8657                              (uint32_t)((inset_reg >>
8658                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8659
8660         for (i = 0; i < num; i++)
8661                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8662                                      mask_reg[i]);
8663         /*clear unused mask registers of the pctype */
8664         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8665                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8666                                      0);
8667         I40E_WRITE_FLUSH(hw);
8668
8669         pf->hash_input_set[pctype] = input_set;
8670         return 0;
8671 }
8672
8673 int
8674 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8675                          struct rte_eth_input_set_conf *conf)
8676 {
8677         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8678         enum i40e_filter_pctype pctype;
8679         uint64_t input_set, inset_reg = 0;
8680         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8681         int ret, i, num;
8682
8683         if (!hw || !conf) {
8684                 PMD_DRV_LOG(ERR, "Invalid pointer");
8685                 return -EFAULT;
8686         }
8687         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8688             conf->op != RTE_ETH_INPUT_SET_ADD) {
8689                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8690                 return -EINVAL;
8691         }
8692
8693         if (!I40E_VALID_FLOW(conf->flow_type)) {
8694                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8695                 return -EINVAL;
8696         }
8697
8698         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8699
8700         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8701                                    conf->inset_size);
8702         if (ret) {
8703                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8704                 return -EINVAL;
8705         }
8706         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8707                                     input_set) != 0) {
8708                 PMD_DRV_LOG(ERR, "Invalid input set");
8709                 return -EINVAL;
8710         }
8711
8712         /* get inset value in register */
8713         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8714         inset_reg <<= I40E_32_BIT_WIDTH;
8715         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8716
8717         /* Can not change the inset reg for flex payload for fdir,
8718          * it is done by writing I40E_PRTQF_FD_FLXINSET
8719          * in i40e_set_flex_mask_on_pctype.
8720          */
8721         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8722                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8723         else
8724                 input_set |= pf->fdir.input_set[pctype];
8725         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8726                                            I40E_INSET_MASK_NUM_REG);
8727         if (num < 0)
8728                 return -EINVAL;
8729
8730         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8731
8732         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8733                               (uint32_t)(inset_reg & UINT32_MAX));
8734         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8735                              (uint32_t)((inset_reg >>
8736                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8737
8738         for (i = 0; i < num; i++)
8739                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8740                                      mask_reg[i]);
8741         /*clear unused mask registers of the pctype */
8742         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8743                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8744                                      0);
8745         I40E_WRITE_FLUSH(hw);
8746
8747         pf->fdir.input_set[pctype] = input_set;
8748         return 0;
8749 }
8750
8751 static int
8752 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8753 {
8754         int ret = 0;
8755
8756         if (!hw || !info) {
8757                 PMD_DRV_LOG(ERR, "Invalid pointer");
8758                 return -EFAULT;
8759         }
8760
8761         switch (info->info_type) {
8762         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8763                 i40e_get_symmetric_hash_enable_per_port(hw,
8764                                         &(info->info.enable));
8765                 break;
8766         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8767                 ret = i40e_get_hash_filter_global_config(hw,
8768                                 &(info->info.global_conf));
8769                 break;
8770         default:
8771                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8772                                                         info->info_type);
8773                 ret = -EINVAL;
8774                 break;
8775         }
8776
8777         return ret;
8778 }
8779
8780 static int
8781 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8782 {
8783         int ret = 0;
8784
8785         if (!hw || !info) {
8786                 PMD_DRV_LOG(ERR, "Invalid pointer");
8787                 return -EFAULT;
8788         }
8789
8790         switch (info->info_type) {
8791         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8792                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8793                 break;
8794         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8795                 ret = i40e_set_hash_filter_global_config(hw,
8796                                 &(info->info.global_conf));
8797                 break;
8798         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8799                 ret = i40e_hash_filter_inset_select(hw,
8800                                                &(info->info.input_set_conf));
8801                 break;
8802
8803         default:
8804                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8805                                                         info->info_type);
8806                 ret = -EINVAL;
8807                 break;
8808         }
8809
8810         return ret;
8811 }
8812
8813 /* Operations for hash function */
8814 static int
8815 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8816                       enum rte_filter_op filter_op,
8817                       void *arg)
8818 {
8819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8820         int ret = 0;
8821
8822         switch (filter_op) {
8823         case RTE_ETH_FILTER_NOP:
8824                 break;
8825         case RTE_ETH_FILTER_GET:
8826                 ret = i40e_hash_filter_get(hw,
8827                         (struct rte_eth_hash_filter_info *)arg);
8828                 break;
8829         case RTE_ETH_FILTER_SET:
8830                 ret = i40e_hash_filter_set(hw,
8831                         (struct rte_eth_hash_filter_info *)arg);
8832                 break;
8833         default:
8834                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8835                                                                 filter_op);
8836                 ret = -ENOTSUP;
8837                 break;
8838         }
8839
8840         return ret;
8841 }
8842
8843 /* Convert ethertype filter structure */
8844 static int
8845 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8846                               struct i40e_ethertype_filter *filter)
8847 {
8848         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8849         filter->input.ether_type = input->ether_type;
8850         filter->flags = input->flags;
8851         filter->queue = input->queue;
8852
8853         return 0;
8854 }
8855
8856 /* Check if there exists the ehtertype filter */
8857 struct i40e_ethertype_filter *
8858 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8859                                 const struct i40e_ethertype_filter_input *input)
8860 {
8861         int ret;
8862
8863         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8864         if (ret < 0)
8865                 return NULL;
8866
8867         return ethertype_rule->hash_map[ret];
8868 }
8869
8870 /* Add ethertype filter in SW list */
8871 static int
8872 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8873                                 struct i40e_ethertype_filter *filter)
8874 {
8875         struct i40e_ethertype_rule *rule = &pf->ethertype;
8876         int ret;
8877
8878         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8879         if (ret < 0) {
8880                 PMD_DRV_LOG(ERR,
8881                             "Failed to insert ethertype filter"
8882                             " to hash table %d!",
8883                             ret);
8884                 return ret;
8885         }
8886         rule->hash_map[ret] = filter;
8887
8888         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8889
8890         return 0;
8891 }
8892
8893 /* Delete ethertype filter in SW list */
8894 int
8895 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8896                              struct i40e_ethertype_filter_input *input)
8897 {
8898         struct i40e_ethertype_rule *rule = &pf->ethertype;
8899         struct i40e_ethertype_filter *filter;
8900         int ret;
8901
8902         ret = rte_hash_del_key(rule->hash_table, input);
8903         if (ret < 0) {
8904                 PMD_DRV_LOG(ERR,
8905                             "Failed to delete ethertype filter"
8906                             " to hash table %d!",
8907                             ret);
8908                 return ret;
8909         }
8910         filter = rule->hash_map[ret];
8911         rule->hash_map[ret] = NULL;
8912
8913         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8914         rte_free(filter);
8915
8916         return 0;
8917 }
8918
8919 /*
8920  * Configure ethertype filter, which can director packet by filtering
8921  * with mac address and ether_type or only ether_type
8922  */
8923 int
8924 i40e_ethertype_filter_set(struct i40e_pf *pf,
8925                         struct rte_eth_ethertype_filter *filter,
8926                         bool add)
8927 {
8928         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8929         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8930         struct i40e_ethertype_filter *ethertype_filter, *node;
8931         struct i40e_ethertype_filter check_filter;
8932         struct i40e_control_filter_stats stats;
8933         uint16_t flags = 0;
8934         int ret;
8935
8936         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8937                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8938                 return -EINVAL;
8939         }
8940         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8941                 filter->ether_type == ETHER_TYPE_IPv6) {
8942                 PMD_DRV_LOG(ERR,
8943                         "unsupported ether_type(0x%04x) in control packet filter.",
8944                         filter->ether_type);
8945                 return -EINVAL;
8946         }
8947         if (filter->ether_type == ETHER_TYPE_VLAN)
8948                 PMD_DRV_LOG(WARNING,
8949                         "filter vlan ether_type in first tag is not supported.");
8950
8951         /* Check if there is the filter in SW list */
8952         memset(&check_filter, 0, sizeof(check_filter));
8953         i40e_ethertype_filter_convert(filter, &check_filter);
8954         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8955                                                &check_filter.input);
8956         if (add && node) {
8957                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8958                 return -EINVAL;
8959         }
8960
8961         if (!add && !node) {
8962                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8963                 return -EINVAL;
8964         }
8965
8966         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8967                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8968         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8969                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8970         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8971
8972         memset(&stats, 0, sizeof(stats));
8973         ret = i40e_aq_add_rem_control_packet_filter(hw,
8974                         filter->mac_addr.addr_bytes,
8975                         filter->ether_type, flags,
8976                         pf->main_vsi->seid,
8977                         filter->queue, add, &stats, NULL);
8978
8979         PMD_DRV_LOG(INFO,
8980                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8981                 ret, stats.mac_etype_used, stats.etype_used,
8982                 stats.mac_etype_free, stats.etype_free);
8983         if (ret < 0)
8984                 return -ENOSYS;
8985
8986         /* Add or delete a filter in SW list */
8987         if (add) {
8988                 ethertype_filter = rte_zmalloc("ethertype_filter",
8989                                        sizeof(*ethertype_filter), 0);
8990                 rte_memcpy(ethertype_filter, &check_filter,
8991                            sizeof(check_filter));
8992                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8993         } else {
8994                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8995         }
8996
8997         return ret;
8998 }
8999
9000 /*
9001  * Handle operations for ethertype filter.
9002  */
9003 static int
9004 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9005                                 enum rte_filter_op filter_op,
9006                                 void *arg)
9007 {
9008         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9009         int ret = 0;
9010
9011         if (filter_op == RTE_ETH_FILTER_NOP)
9012                 return ret;
9013
9014         if (arg == NULL) {
9015                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9016                             filter_op);
9017                 return -EINVAL;
9018         }
9019
9020         switch (filter_op) {
9021         case RTE_ETH_FILTER_ADD:
9022                 ret = i40e_ethertype_filter_set(pf,
9023                         (struct rte_eth_ethertype_filter *)arg,
9024                         TRUE);
9025                 break;
9026         case RTE_ETH_FILTER_DELETE:
9027                 ret = i40e_ethertype_filter_set(pf,
9028                         (struct rte_eth_ethertype_filter *)arg,
9029                         FALSE);
9030                 break;
9031         default:
9032                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9033                 ret = -ENOSYS;
9034                 break;
9035         }
9036         return ret;
9037 }
9038
9039 static int
9040 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9041                      enum rte_filter_type filter_type,
9042                      enum rte_filter_op filter_op,
9043                      void *arg)
9044 {
9045         int ret = 0;
9046
9047         if (dev == NULL)
9048                 return -EINVAL;
9049
9050         switch (filter_type) {
9051         case RTE_ETH_FILTER_NONE:
9052                 /* For global configuration */
9053                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9054                 break;
9055         case RTE_ETH_FILTER_HASH:
9056                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9057                 break;
9058         case RTE_ETH_FILTER_MACVLAN:
9059                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9060                 break;
9061         case RTE_ETH_FILTER_ETHERTYPE:
9062                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9063                 break;
9064         case RTE_ETH_FILTER_TUNNEL:
9065                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9066                 break;
9067         case RTE_ETH_FILTER_FDIR:
9068                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9069                 break;
9070         case RTE_ETH_FILTER_GENERIC:
9071                 if (filter_op != RTE_ETH_FILTER_GET)
9072                         return -EINVAL;
9073                 *(const void **)arg = &i40e_flow_ops;
9074                 break;
9075         default:
9076                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9077                                                         filter_type);
9078                 ret = -EINVAL;
9079                 break;
9080         }
9081
9082         return ret;
9083 }
9084
9085 /*
9086  * Check and enable Extended Tag.
9087  * Enabling Extended Tag is important for 40G performance.
9088  */
9089 static void
9090 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9091 {
9092         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9093         uint32_t buf = 0;
9094         int ret;
9095
9096         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9097                                       PCI_DEV_CAP_REG);
9098         if (ret < 0) {
9099                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9100                             PCI_DEV_CAP_REG);
9101                 return;
9102         }
9103         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9104                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9105                 return;
9106         }
9107
9108         buf = 0;
9109         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9110                                       PCI_DEV_CTRL_REG);
9111         if (ret < 0) {
9112                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9113                             PCI_DEV_CTRL_REG);
9114                 return;
9115         }
9116         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9117                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9118                 return;
9119         }
9120         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9121         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9122                                        PCI_DEV_CTRL_REG);
9123         if (ret < 0) {
9124                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9125                             PCI_DEV_CTRL_REG);
9126                 return;
9127         }
9128 }
9129
9130 /*
9131  * As some registers wouldn't be reset unless a global hardware reset,
9132  * hardware initialization is needed to put those registers into an
9133  * expected initial state.
9134  */
9135 static void
9136 i40e_hw_init(struct rte_eth_dev *dev)
9137 {
9138         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9139
9140         i40e_enable_extended_tag(dev);
9141
9142         /* clear the PF Queue Filter control register */
9143         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9144
9145         /* Disable symmetric hash per port */
9146         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9147 }
9148
9149 enum i40e_filter_pctype
9150 i40e_flowtype_to_pctype(uint16_t flow_type)
9151 {
9152         static const enum i40e_filter_pctype pctype_table[] = {
9153                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9154                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9155                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9156                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9157                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9158                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9159                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9160                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9161                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9162                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9163                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9164                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9165                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9166                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9167                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9168                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9169                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9170                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9171                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9172         };
9173
9174         return pctype_table[flow_type];
9175 }
9176
9177 uint16_t
9178 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9179 {
9180         static const uint16_t flowtype_table[] = {
9181                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9182                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9183                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9184                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9185                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9186                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9187                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9188                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9189                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9190                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9191                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9192                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9193                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9194                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9195                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9196                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9197                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9198                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9199                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9200                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9201                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9202                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9203                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9204                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9205                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9206                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9207                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9208                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9209                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9210                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9211                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9212         };
9213
9214         return flowtype_table[pctype];
9215 }
9216
9217 /*
9218  * On X710, performance number is far from the expectation on recent firmware
9219  * versions; on XL710, performance number is also far from the expectation on
9220  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9221  * mode is enabled and port MAC address is equal to the packet destination MAC
9222  * address. The fix for this issue may not be integrated in the following
9223  * firmware version. So the workaround in software driver is needed. It needs
9224  * to modify the initial values of 3 internal only registers for both X710 and
9225  * XL710. Note that the values for X710 or XL710 could be different, and the
9226  * workaround can be removed when it is fixed in firmware in the future.
9227  */
9228
9229 /* For both X710 and XL710 */
9230 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9231 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9232 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9233
9234 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9235 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9236
9237 /* For X722 */
9238 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9239 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9240
9241 /* For X710 */
9242 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9243 /* For XL710 */
9244 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9245 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9246
9247 static int
9248 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9249 {
9250         enum i40e_status_code status;
9251         struct i40e_aq_get_phy_abilities_resp phy_ab;
9252         int ret = -ENOTSUP;
9253
9254         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9255                                               NULL);
9256
9257         if (status) {
9258                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9259                         status);
9260                 return ret;
9261         }
9262
9263         return 0;
9264 }
9265
9266 static void
9267 i40e_configure_registers(struct i40e_hw *hw)
9268 {
9269         static struct {
9270                 uint32_t addr;
9271                 uint64_t val;
9272         } reg_table[] = {
9273                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9274                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9275                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9276         };
9277         uint64_t reg;
9278         uint32_t i;
9279         int ret;
9280
9281         for (i = 0; i < RTE_DIM(reg_table); i++) {
9282                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9283                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9284                                 reg_table[i].val =
9285                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9286                         else /* For X710/XL710/XXV710 */
9287                                 if (hw->aq.fw_maj_ver < 6)
9288                                         reg_table[i].val =
9289                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9290                                 else
9291                                         reg_table[i].val =
9292                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9293                 }
9294
9295                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9296                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9297                                 reg_table[i].val =
9298                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9299                         else /* For X710/XL710/XXV710 */
9300                                 reg_table[i].val =
9301                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9302                 }
9303
9304                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9305                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9306                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9307                                 reg_table[i].val =
9308                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9309                         else /* For X710 */
9310                                 reg_table[i].val =
9311                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9312                 }
9313
9314                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9315                                                         &reg, NULL);
9316                 if (ret < 0) {
9317                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9318                                                         reg_table[i].addr);
9319                         break;
9320                 }
9321                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9322                                                 reg_table[i].addr, reg);
9323                 if (reg == reg_table[i].val)
9324                         continue;
9325
9326                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9327                                                 reg_table[i].val, NULL);
9328                 if (ret < 0) {
9329                         PMD_DRV_LOG(ERR,
9330                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9331                                 reg_table[i].val, reg_table[i].addr);
9332                         break;
9333                 }
9334                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9335                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9336         }
9337 }
9338
9339 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9340 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9341 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9342 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9343 static int
9344 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9345 {
9346         uint32_t reg;
9347         int ret;
9348
9349         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9350                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9351                 return -EINVAL;
9352         }
9353
9354         /* Configure for double VLAN RX stripping */
9355         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9356         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9357                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9358                 ret = i40e_aq_debug_write_register(hw,
9359                                                    I40E_VSI_TSR(vsi->vsi_id),
9360                                                    reg, NULL);
9361                 if (ret < 0) {
9362                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9363                                     vsi->vsi_id);
9364                         return I40E_ERR_CONFIG;
9365                 }
9366         }
9367
9368         /* Configure for double VLAN TX insertion */
9369         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9370         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9371                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9372                 ret = i40e_aq_debug_write_register(hw,
9373                                                    I40E_VSI_L2TAGSTXVALID(
9374                                                    vsi->vsi_id), reg, NULL);
9375                 if (ret < 0) {
9376                         PMD_DRV_LOG(ERR,
9377                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9378                                 vsi->vsi_id);
9379                         return I40E_ERR_CONFIG;
9380                 }
9381         }
9382
9383         return 0;
9384 }
9385
9386 /**
9387  * i40e_aq_add_mirror_rule
9388  * @hw: pointer to the hardware structure
9389  * @seid: VEB seid to add mirror rule to
9390  * @dst_id: destination vsi seid
9391  * @entries: Buffer which contains the entities to be mirrored
9392  * @count: number of entities contained in the buffer
9393  * @rule_id:the rule_id of the rule to be added
9394  *
9395  * Add a mirror rule for a given veb.
9396  *
9397  **/
9398 static enum i40e_status_code
9399 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9400                         uint16_t seid, uint16_t dst_id,
9401                         uint16_t rule_type, uint16_t *entries,
9402                         uint16_t count, uint16_t *rule_id)
9403 {
9404         struct i40e_aq_desc desc;
9405         struct i40e_aqc_add_delete_mirror_rule cmd;
9406         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9407                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9408                 &desc.params.raw;
9409         uint16_t buff_len;
9410         enum i40e_status_code status;
9411
9412         i40e_fill_default_direct_cmd_desc(&desc,
9413                                           i40e_aqc_opc_add_mirror_rule);
9414         memset(&cmd, 0, sizeof(cmd));
9415
9416         buff_len = sizeof(uint16_t) * count;
9417         desc.datalen = rte_cpu_to_le_16(buff_len);
9418         if (buff_len > 0)
9419                 desc.flags |= rte_cpu_to_le_16(
9420                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9421         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9422                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9423         cmd.num_entries = rte_cpu_to_le_16(count);
9424         cmd.seid = rte_cpu_to_le_16(seid);
9425         cmd.destination = rte_cpu_to_le_16(dst_id);
9426
9427         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9428         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9429         PMD_DRV_LOG(INFO,
9430                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9431                 hw->aq.asq_last_status, resp->rule_id,
9432                 resp->mirror_rules_used, resp->mirror_rules_free);
9433         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9434
9435         return status;
9436 }
9437
9438 /**
9439  * i40e_aq_del_mirror_rule
9440  * @hw: pointer to the hardware structure
9441  * @seid: VEB seid to add mirror rule to
9442  * @entries: Buffer which contains the entities to be mirrored
9443  * @count: number of entities contained in the buffer
9444  * @rule_id:the rule_id of the rule to be delete
9445  *
9446  * Delete a mirror rule for a given veb.
9447  *
9448  **/
9449 static enum i40e_status_code
9450 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9451                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9452                 uint16_t count, uint16_t rule_id)
9453 {
9454         struct i40e_aq_desc desc;
9455         struct i40e_aqc_add_delete_mirror_rule cmd;
9456         uint16_t buff_len = 0;
9457         enum i40e_status_code status;
9458         void *buff = NULL;
9459
9460         i40e_fill_default_direct_cmd_desc(&desc,
9461                                           i40e_aqc_opc_delete_mirror_rule);
9462         memset(&cmd, 0, sizeof(cmd));
9463         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9464                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9465                                                           I40E_AQ_FLAG_RD));
9466                 cmd.num_entries = count;
9467                 buff_len = sizeof(uint16_t) * count;
9468                 desc.datalen = rte_cpu_to_le_16(buff_len);
9469                 buff = (void *)entries;
9470         } else
9471                 /* rule id is filled in destination field for deleting mirror rule */
9472                 cmd.destination = rte_cpu_to_le_16(rule_id);
9473
9474         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9475                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9476         cmd.seid = rte_cpu_to_le_16(seid);
9477
9478         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9479         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9480
9481         return status;
9482 }
9483
9484 /**
9485  * i40e_mirror_rule_set
9486  * @dev: pointer to the hardware structure
9487  * @mirror_conf: mirror rule info
9488  * @sw_id: mirror rule's sw_id
9489  * @on: enable/disable
9490  *
9491  * set a mirror rule.
9492  *
9493  **/
9494 static int
9495 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9496                         struct rte_eth_mirror_conf *mirror_conf,
9497                         uint8_t sw_id, uint8_t on)
9498 {
9499         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9501         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9502         struct i40e_mirror_rule *parent = NULL;
9503         uint16_t seid, dst_seid, rule_id;
9504         uint16_t i, j = 0;
9505         int ret;
9506
9507         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9508
9509         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9510                 PMD_DRV_LOG(ERR,
9511                         "mirror rule can not be configured without veb or vfs.");
9512                 return -ENOSYS;
9513         }
9514         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9515                 PMD_DRV_LOG(ERR, "mirror table is full.");
9516                 return -ENOSPC;
9517         }
9518         if (mirror_conf->dst_pool > pf->vf_num) {
9519                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9520                                  mirror_conf->dst_pool);
9521                 return -EINVAL;
9522         }
9523
9524         seid = pf->main_vsi->veb->seid;
9525
9526         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9527                 if (sw_id <= it->index) {
9528                         mirr_rule = it;
9529                         break;
9530                 }
9531                 parent = it;
9532         }
9533         if (mirr_rule && sw_id == mirr_rule->index) {
9534                 if (on) {
9535                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9536                         return -EEXIST;
9537                 } else {
9538                         ret = i40e_aq_del_mirror_rule(hw, seid,
9539                                         mirr_rule->rule_type,
9540                                         mirr_rule->entries,
9541                                         mirr_rule->num_entries, mirr_rule->id);
9542                         if (ret < 0) {
9543                                 PMD_DRV_LOG(ERR,
9544                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9545                                         ret, hw->aq.asq_last_status);
9546                                 return -ENOSYS;
9547                         }
9548                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9549                         rte_free(mirr_rule);
9550                         pf->nb_mirror_rule--;
9551                         return 0;
9552                 }
9553         } else if (!on) {
9554                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9555                 return -ENOENT;
9556         }
9557
9558         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9559                                 sizeof(struct i40e_mirror_rule) , 0);
9560         if (!mirr_rule) {
9561                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9562                 return I40E_ERR_NO_MEMORY;
9563         }
9564         switch (mirror_conf->rule_type) {
9565         case ETH_MIRROR_VLAN:
9566                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9567                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9568                                 mirr_rule->entries[j] =
9569                                         mirror_conf->vlan.vlan_id[i];
9570                                 j++;
9571                         }
9572                 }
9573                 if (j == 0) {
9574                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9575                         rte_free(mirr_rule);
9576                         return -EINVAL;
9577                 }
9578                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9579                 break;
9580         case ETH_MIRROR_VIRTUAL_POOL_UP:
9581         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9582                 /* check if the specified pool bit is out of range */
9583                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9584                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9585                         rte_free(mirr_rule);
9586                         return -EINVAL;
9587                 }
9588                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9589                         if (mirror_conf->pool_mask & (1ULL << i)) {
9590                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9591                                 j++;
9592                         }
9593                 }
9594                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9595                         /* add pf vsi to entries */
9596                         mirr_rule->entries[j] = pf->main_vsi_seid;
9597                         j++;
9598                 }
9599                 if (j == 0) {
9600                         PMD_DRV_LOG(ERR, "pool is not specified.");
9601                         rte_free(mirr_rule);
9602                         return -EINVAL;
9603                 }
9604                 /* egress and ingress in aq commands means from switch but not port */
9605                 mirr_rule->rule_type =
9606                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9607                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9608                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9609                 break;
9610         case ETH_MIRROR_UPLINK_PORT:
9611                 /* egress and ingress in aq commands means from switch but not port*/
9612                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9613                 break;
9614         case ETH_MIRROR_DOWNLINK_PORT:
9615                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9616                 break;
9617         default:
9618                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9619                         mirror_conf->rule_type);
9620                 rte_free(mirr_rule);
9621                 return -EINVAL;
9622         }
9623
9624         /* If the dst_pool is equal to vf_num, consider it as PF */
9625         if (mirror_conf->dst_pool == pf->vf_num)
9626                 dst_seid = pf->main_vsi_seid;
9627         else
9628                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9629
9630         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9631                                       mirr_rule->rule_type, mirr_rule->entries,
9632                                       j, &rule_id);
9633         if (ret < 0) {
9634                 PMD_DRV_LOG(ERR,
9635                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9636                         ret, hw->aq.asq_last_status);
9637                 rte_free(mirr_rule);
9638                 return -ENOSYS;
9639         }
9640
9641         mirr_rule->index = sw_id;
9642         mirr_rule->num_entries = j;
9643         mirr_rule->id = rule_id;
9644         mirr_rule->dst_vsi_seid = dst_seid;
9645
9646         if (parent)
9647                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9648         else
9649                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9650
9651         pf->nb_mirror_rule++;
9652         return 0;
9653 }
9654
9655 /**
9656  * i40e_mirror_rule_reset
9657  * @dev: pointer to the device
9658  * @sw_id: mirror rule's sw_id
9659  *
9660  * reset a mirror rule.
9661  *
9662  **/
9663 static int
9664 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9665 {
9666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9668         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9669         uint16_t seid;
9670         int ret;
9671
9672         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9673
9674         seid = pf->main_vsi->veb->seid;
9675
9676         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9677                 if (sw_id == it->index) {
9678                         mirr_rule = it;
9679                         break;
9680                 }
9681         }
9682         if (mirr_rule) {
9683                 ret = i40e_aq_del_mirror_rule(hw, seid,
9684                                 mirr_rule->rule_type,
9685                                 mirr_rule->entries,
9686                                 mirr_rule->num_entries, mirr_rule->id);
9687                 if (ret < 0) {
9688                         PMD_DRV_LOG(ERR,
9689                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9690                                 ret, hw->aq.asq_last_status);
9691                         return -ENOSYS;
9692                 }
9693                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9694                 rte_free(mirr_rule);
9695                 pf->nb_mirror_rule--;
9696         } else {
9697                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9698                 return -ENOENT;
9699         }
9700         return 0;
9701 }
9702
9703 static uint64_t
9704 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9705 {
9706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9707         uint64_t systim_cycles;
9708
9709         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9710         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9711                         << 32;
9712
9713         return systim_cycles;
9714 }
9715
9716 static uint64_t
9717 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9718 {
9719         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9720         uint64_t rx_tstamp;
9721
9722         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9723         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9724                         << 32;
9725
9726         return rx_tstamp;
9727 }
9728
9729 static uint64_t
9730 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9731 {
9732         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9733         uint64_t tx_tstamp;
9734
9735         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9736         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9737                         << 32;
9738
9739         return tx_tstamp;
9740 }
9741
9742 static void
9743 i40e_start_timecounters(struct rte_eth_dev *dev)
9744 {
9745         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9746         struct i40e_adapter *adapter =
9747                         (struct i40e_adapter *)dev->data->dev_private;
9748         struct rte_eth_link link;
9749         uint32_t tsync_inc_l;
9750         uint32_t tsync_inc_h;
9751
9752         /* Get current link speed. */
9753         memset(&link, 0, sizeof(link));
9754         i40e_dev_link_update(dev, 1);
9755         rte_i40e_dev_atomic_read_link_status(dev, &link);
9756
9757         switch (link.link_speed) {
9758         case ETH_SPEED_NUM_40G:
9759                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9760                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9761                 break;
9762         case ETH_SPEED_NUM_10G:
9763                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9764                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9765                 break;
9766         case ETH_SPEED_NUM_1G:
9767                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9768                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9769                 break;
9770         default:
9771                 tsync_inc_l = 0x0;
9772                 tsync_inc_h = 0x0;
9773         }
9774
9775         /* Set the timesync increment value. */
9776         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9777         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9778
9779         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9780         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9781         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9782
9783         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9784         adapter->systime_tc.cc_shift = 0;
9785         adapter->systime_tc.nsec_mask = 0;
9786
9787         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9788         adapter->rx_tstamp_tc.cc_shift = 0;
9789         adapter->rx_tstamp_tc.nsec_mask = 0;
9790
9791         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9792         adapter->tx_tstamp_tc.cc_shift = 0;
9793         adapter->tx_tstamp_tc.nsec_mask = 0;
9794 }
9795
9796 static int
9797 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9798 {
9799         struct i40e_adapter *adapter =
9800                         (struct i40e_adapter *)dev->data->dev_private;
9801
9802         adapter->systime_tc.nsec += delta;
9803         adapter->rx_tstamp_tc.nsec += delta;
9804         adapter->tx_tstamp_tc.nsec += delta;
9805
9806         return 0;
9807 }
9808
9809 static int
9810 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9811 {
9812         uint64_t ns;
9813         struct i40e_adapter *adapter =
9814                         (struct i40e_adapter *)dev->data->dev_private;
9815
9816         ns = rte_timespec_to_ns(ts);
9817
9818         /* Set the timecounters to a new value. */
9819         adapter->systime_tc.nsec = ns;
9820         adapter->rx_tstamp_tc.nsec = ns;
9821         adapter->tx_tstamp_tc.nsec = ns;
9822
9823         return 0;
9824 }
9825
9826 static int
9827 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9828 {
9829         uint64_t ns, systime_cycles;
9830         struct i40e_adapter *adapter =
9831                         (struct i40e_adapter *)dev->data->dev_private;
9832
9833         systime_cycles = i40e_read_systime_cyclecounter(dev);
9834         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9835         *ts = rte_ns_to_timespec(ns);
9836
9837         return 0;
9838 }
9839
9840 static int
9841 i40e_timesync_enable(struct rte_eth_dev *dev)
9842 {
9843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9844         uint32_t tsync_ctl_l;
9845         uint32_t tsync_ctl_h;
9846
9847         /* Stop the timesync system time. */
9848         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9849         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9850         /* Reset the timesync system time value. */
9851         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9852         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9853
9854         i40e_start_timecounters(dev);
9855
9856         /* Clear timesync registers. */
9857         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9858         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9859         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9860         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9861         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9862         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9863
9864         /* Enable timestamping of PTP packets. */
9865         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9866         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9867
9868         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9869         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9870         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9871
9872         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9873         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9874
9875         return 0;
9876 }
9877
9878 static int
9879 i40e_timesync_disable(struct rte_eth_dev *dev)
9880 {
9881         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9882         uint32_t tsync_ctl_l;
9883         uint32_t tsync_ctl_h;
9884
9885         /* Disable timestamping of transmitted PTP packets. */
9886         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9887         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9888
9889         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9890         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9891
9892         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9893         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9894
9895         /* Reset the timesync increment value. */
9896         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9897         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9898
9899         return 0;
9900 }
9901
9902 static int
9903 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9904                                 struct timespec *timestamp, uint32_t flags)
9905 {
9906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9907         struct i40e_adapter *adapter =
9908                 (struct i40e_adapter *)dev->data->dev_private;
9909
9910         uint32_t sync_status;
9911         uint32_t index = flags & 0x03;
9912         uint64_t rx_tstamp_cycles;
9913         uint64_t ns;
9914
9915         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9916         if ((sync_status & (1 << index)) == 0)
9917                 return -EINVAL;
9918
9919         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9920         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9921         *timestamp = rte_ns_to_timespec(ns);
9922
9923         return 0;
9924 }
9925
9926 static int
9927 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9928                                 struct timespec *timestamp)
9929 {
9930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9931         struct i40e_adapter *adapter =
9932                 (struct i40e_adapter *)dev->data->dev_private;
9933
9934         uint32_t sync_status;
9935         uint64_t tx_tstamp_cycles;
9936         uint64_t ns;
9937
9938         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9939         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9940                 return -EINVAL;
9941
9942         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9943         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9944         *timestamp = rte_ns_to_timespec(ns);
9945
9946         return 0;
9947 }
9948
9949 /*
9950  * i40e_parse_dcb_configure - parse dcb configure from user
9951  * @dev: the device being configured
9952  * @dcb_cfg: pointer of the result of parse
9953  * @*tc_map: bit map of enabled traffic classes
9954  *
9955  * Returns 0 on success, negative value on failure
9956  */
9957 static int
9958 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9959                          struct i40e_dcbx_config *dcb_cfg,
9960                          uint8_t *tc_map)
9961 {
9962         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9963         uint8_t i, tc_bw, bw_lf;
9964
9965         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9966
9967         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9968         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9969                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9970                 return -EINVAL;
9971         }
9972
9973         /* assume each tc has the same bw */
9974         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9975         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9976                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9977         /* to ensure the sum of tcbw is equal to 100 */
9978         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9979         for (i = 0; i < bw_lf; i++)
9980                 dcb_cfg->etscfg.tcbwtable[i]++;
9981
9982         /* assume each tc has the same Transmission Selection Algorithm */
9983         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9984                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9985
9986         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9987                 dcb_cfg->etscfg.prioritytable[i] =
9988                                 dcb_rx_conf->dcb_tc[i];
9989
9990         /* FW needs one App to configure HW */
9991         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9992         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9993         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9994         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9995
9996         if (dcb_rx_conf->nb_tcs == 0)
9997                 *tc_map = 1; /* tc0 only */
9998         else
9999                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10000
10001         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10002                 dcb_cfg->pfc.willing = 0;
10003                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10004                 dcb_cfg->pfc.pfcenable = *tc_map;
10005         }
10006         return 0;
10007 }
10008
10009
10010 static enum i40e_status_code
10011 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10012                               struct i40e_aqc_vsi_properties_data *info,
10013                               uint8_t enabled_tcmap)
10014 {
10015         enum i40e_status_code ret;
10016         int i, total_tc = 0;
10017         uint16_t qpnum_per_tc, bsf, qp_idx;
10018         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10019         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10020         uint16_t used_queues;
10021
10022         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10023         if (ret != I40E_SUCCESS)
10024                 return ret;
10025
10026         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10027                 if (enabled_tcmap & (1 << i))
10028                         total_tc++;
10029         }
10030         if (total_tc == 0)
10031                 total_tc = 1;
10032         vsi->enabled_tc = enabled_tcmap;
10033
10034         /* different VSI has different queues assigned */
10035         if (vsi->type == I40E_VSI_MAIN)
10036                 used_queues = dev_data->nb_rx_queues -
10037                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10038         else if (vsi->type == I40E_VSI_VMDQ2)
10039                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10040         else {
10041                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10042                 return I40E_ERR_NO_AVAILABLE_VSI;
10043         }
10044
10045         qpnum_per_tc = used_queues / total_tc;
10046         /* Number of queues per enabled TC */
10047         if (qpnum_per_tc == 0) {
10048                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10049                 return I40E_ERR_INVALID_QP_ID;
10050         }
10051         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10052                                 I40E_MAX_Q_PER_TC);
10053         bsf = rte_bsf32(qpnum_per_tc);
10054
10055         /**
10056          * Configure TC and queue mapping parameters, for enabled TC,
10057          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10058          * default queue will serve it.
10059          */
10060         qp_idx = 0;
10061         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10062                 if (vsi->enabled_tc & (1 << i)) {
10063                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10064                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10065                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10066                         qp_idx += qpnum_per_tc;
10067                 } else
10068                         info->tc_mapping[i] = 0;
10069         }
10070
10071         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10072         if (vsi->type == I40E_VSI_SRIOV) {
10073                 info->mapping_flags |=
10074                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10075                 for (i = 0; i < vsi->nb_qps; i++)
10076                         info->queue_mapping[i] =
10077                                 rte_cpu_to_le_16(vsi->base_queue + i);
10078         } else {
10079                 info->mapping_flags |=
10080                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10081                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10082         }
10083         info->valid_sections |=
10084                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10085
10086         return I40E_SUCCESS;
10087 }
10088
10089 /*
10090  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10091  * @veb: VEB to be configured
10092  * @tc_map: enabled TC bitmap
10093  *
10094  * Returns 0 on success, negative value on failure
10095  */
10096 static enum i40e_status_code
10097 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10098 {
10099         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10100         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10101         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10102         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10103         enum i40e_status_code ret = I40E_SUCCESS;
10104         int i;
10105         uint32_t bw_max;
10106
10107         /* Check if enabled_tc is same as existing or new TCs */
10108         if (veb->enabled_tc == tc_map)
10109                 return ret;
10110
10111         /* configure tc bandwidth */
10112         memset(&veb_bw, 0, sizeof(veb_bw));
10113         veb_bw.tc_valid_bits = tc_map;
10114         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10115         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10116                 if (tc_map & BIT_ULL(i))
10117                         veb_bw.tc_bw_share_credits[i] = 1;
10118         }
10119         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10120                                                    &veb_bw, NULL);
10121         if (ret) {
10122                 PMD_INIT_LOG(ERR,
10123                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10124                         hw->aq.asq_last_status);
10125                 return ret;
10126         }
10127
10128         memset(&ets_query, 0, sizeof(ets_query));
10129         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10130                                                    &ets_query, NULL);
10131         if (ret != I40E_SUCCESS) {
10132                 PMD_DRV_LOG(ERR,
10133                         "Failed to get switch_comp ETS configuration %u",
10134                         hw->aq.asq_last_status);
10135                 return ret;
10136         }
10137         memset(&bw_query, 0, sizeof(bw_query));
10138         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10139                                                   &bw_query, NULL);
10140         if (ret != I40E_SUCCESS) {
10141                 PMD_DRV_LOG(ERR,
10142                         "Failed to get switch_comp bandwidth configuration %u",
10143                         hw->aq.asq_last_status);
10144                 return ret;
10145         }
10146
10147         /* store and print out BW info */
10148         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10149         veb->bw_info.bw_max = ets_query.tc_bw_max;
10150         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10151         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10152         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10153                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10154                      I40E_16_BIT_WIDTH);
10155         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10156                 veb->bw_info.bw_ets_share_credits[i] =
10157                                 bw_query.tc_bw_share_credits[i];
10158                 veb->bw_info.bw_ets_credits[i] =
10159                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10160                 /* 4 bits per TC, 4th bit is reserved */
10161                 veb->bw_info.bw_ets_max[i] =
10162                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10163                                   RTE_LEN2MASK(3, uint8_t));
10164                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10165                             veb->bw_info.bw_ets_share_credits[i]);
10166                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10167                             veb->bw_info.bw_ets_credits[i]);
10168                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10169                             veb->bw_info.bw_ets_max[i]);
10170         }
10171
10172         veb->enabled_tc = tc_map;
10173
10174         return ret;
10175 }
10176
10177
10178 /*
10179  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10180  * @vsi: VSI to be configured
10181  * @tc_map: enabled TC bitmap
10182  *
10183  * Returns 0 on success, negative value on failure
10184  */
10185 static enum i40e_status_code
10186 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10187 {
10188         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10189         struct i40e_vsi_context ctxt;
10190         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10191         enum i40e_status_code ret = I40E_SUCCESS;
10192         int i;
10193
10194         /* Check if enabled_tc is same as existing or new TCs */
10195         if (vsi->enabled_tc == tc_map)
10196                 return ret;
10197
10198         /* configure tc bandwidth */
10199         memset(&bw_data, 0, sizeof(bw_data));
10200         bw_data.tc_valid_bits = tc_map;
10201         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10202         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10203                 if (tc_map & BIT_ULL(i))
10204                         bw_data.tc_bw_credits[i] = 1;
10205         }
10206         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10207         if (ret) {
10208                 PMD_INIT_LOG(ERR,
10209                         "AQ command Config VSI BW allocation per TC failed = %d",
10210                         hw->aq.asq_last_status);
10211                 goto out;
10212         }
10213         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10214                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10215
10216         /* Update Queue Pairs Mapping for currently enabled UPs */
10217         ctxt.seid = vsi->seid;
10218         ctxt.pf_num = hw->pf_id;
10219         ctxt.vf_num = 0;
10220         ctxt.uplink_seid = vsi->uplink_seid;
10221         ctxt.info = vsi->info;
10222         i40e_get_cap(hw);
10223         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10224         if (ret)
10225                 goto out;
10226
10227         /* Update the VSI after updating the VSI queue-mapping information */
10228         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10229         if (ret) {
10230                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10231                         hw->aq.asq_last_status);
10232                 goto out;
10233         }
10234         /* update the local VSI info with updated queue map */
10235         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10236                                         sizeof(vsi->info.tc_mapping));
10237         (void)rte_memcpy(&vsi->info.queue_mapping,
10238                         &ctxt.info.queue_mapping,
10239                 sizeof(vsi->info.queue_mapping));
10240         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10241         vsi->info.valid_sections = 0;
10242
10243         /* query and update current VSI BW information */
10244         ret = i40e_vsi_get_bw_config(vsi);
10245         if (ret) {
10246                 PMD_INIT_LOG(ERR,
10247                          "Failed updating vsi bw info, err %s aq_err %s",
10248                          i40e_stat_str(hw, ret),
10249                          i40e_aq_str(hw, hw->aq.asq_last_status));
10250                 goto out;
10251         }
10252
10253         vsi->enabled_tc = tc_map;
10254
10255 out:
10256         return ret;
10257 }
10258
10259 /*
10260  * i40e_dcb_hw_configure - program the dcb setting to hw
10261  * @pf: pf the configuration is taken on
10262  * @new_cfg: new configuration
10263  * @tc_map: enabled TC bitmap
10264  *
10265  * Returns 0 on success, negative value on failure
10266  */
10267 static enum i40e_status_code
10268 i40e_dcb_hw_configure(struct i40e_pf *pf,
10269                       struct i40e_dcbx_config *new_cfg,
10270                       uint8_t tc_map)
10271 {
10272         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10273         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10274         struct i40e_vsi *main_vsi = pf->main_vsi;
10275         struct i40e_vsi_list *vsi_list;
10276         enum i40e_status_code ret;
10277         int i;
10278         uint32_t val;
10279
10280         /* Use the FW API if FW > v4.4*/
10281         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10282               (hw->aq.fw_maj_ver >= 5))) {
10283                 PMD_INIT_LOG(ERR,
10284                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10285                 return I40E_ERR_FIRMWARE_API_VERSION;
10286         }
10287
10288         /* Check if need reconfiguration */
10289         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10290                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10291                 return I40E_SUCCESS;
10292         }
10293
10294         /* Copy the new config to the current config */
10295         *old_cfg = *new_cfg;
10296         old_cfg->etsrec = old_cfg->etscfg;
10297         ret = i40e_set_dcb_config(hw);
10298         if (ret) {
10299                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10300                          i40e_stat_str(hw, ret),
10301                          i40e_aq_str(hw, hw->aq.asq_last_status));
10302                 return ret;
10303         }
10304         /* set receive Arbiter to RR mode and ETS scheme by default */
10305         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10306                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10307                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10308                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10309                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10310                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10311                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10312                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10313                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10314                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10315                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10316                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10317                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10318         }
10319         /* get local mib to check whether it is configured correctly */
10320         /* IEEE mode */
10321         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10322         /* Get Local DCB Config */
10323         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10324                                      &hw->local_dcbx_config);
10325
10326         /* if Veb is created, need to update TC of it at first */
10327         if (main_vsi->veb) {
10328                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10329                 if (ret)
10330                         PMD_INIT_LOG(WARNING,
10331                                  "Failed configuring TC for VEB seid=%d",
10332                                  main_vsi->veb->seid);
10333         }
10334         /* Update each VSI */
10335         i40e_vsi_config_tc(main_vsi, tc_map);
10336         if (main_vsi->veb) {
10337                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10338                         /* Beside main VSI and VMDQ VSIs, only enable default
10339                          * TC for other VSIs
10340                          */
10341                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10342                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10343                                                          tc_map);
10344                         else
10345                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10346                                                          I40E_DEFAULT_TCMAP);
10347                         if (ret)
10348                                 PMD_INIT_LOG(WARNING,
10349                                         "Failed configuring TC for VSI seid=%d",
10350                                         vsi_list->vsi->seid);
10351                         /* continue */
10352                 }
10353         }
10354         return I40E_SUCCESS;
10355 }
10356
10357 /*
10358  * i40e_dcb_init_configure - initial dcb config
10359  * @dev: device being configured
10360  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10361  *
10362  * Returns 0 on success, negative value on failure
10363  */
10364 static int
10365 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10366 {
10367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10369         int i, ret = 0;
10370
10371         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10372                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10373                 return -ENOTSUP;
10374         }
10375
10376         /* DCB initialization:
10377          * Update DCB configuration from the Firmware and configure
10378          * LLDP MIB change event.
10379          */
10380         if (sw_dcb == TRUE) {
10381                 ret = i40e_init_dcb(hw);
10382                 /* If lldp agent is stopped, the return value from
10383                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10384                  * adminq status. Otherwise, it should return success.
10385                  */
10386                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10387                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10388                         memset(&hw->local_dcbx_config, 0,
10389                                 sizeof(struct i40e_dcbx_config));
10390                         /* set dcb default configuration */
10391                         hw->local_dcbx_config.etscfg.willing = 0;
10392                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10393                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10394                         hw->local_dcbx_config.etscfg.tsatable[0] =
10395                                                 I40E_IEEE_TSA_ETS;
10396                         /* all UPs mapping to TC0 */
10397                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10398                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10399                         hw->local_dcbx_config.etsrec =
10400                                 hw->local_dcbx_config.etscfg;
10401                         hw->local_dcbx_config.pfc.willing = 0;
10402                         hw->local_dcbx_config.pfc.pfccap =
10403                                                 I40E_MAX_TRAFFIC_CLASS;
10404                         /* FW needs one App to configure HW */
10405                         hw->local_dcbx_config.numapps = 1;
10406                         hw->local_dcbx_config.app[0].selector =
10407                                                 I40E_APP_SEL_ETHTYPE;
10408                         hw->local_dcbx_config.app[0].priority = 3;
10409                         hw->local_dcbx_config.app[0].protocolid =
10410                                                 I40E_APP_PROTOID_FCOE;
10411                         ret = i40e_set_dcb_config(hw);
10412                         if (ret) {
10413                                 PMD_INIT_LOG(ERR,
10414                                         "default dcb config fails. err = %d, aq_err = %d.",
10415                                         ret, hw->aq.asq_last_status);
10416                                 return -ENOSYS;
10417                         }
10418                 } else {
10419                         PMD_INIT_LOG(ERR,
10420                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10421                                 ret, hw->aq.asq_last_status);
10422                         return -ENOTSUP;
10423                 }
10424         } else {
10425                 ret = i40e_aq_start_lldp(hw, NULL);
10426                 if (ret != I40E_SUCCESS)
10427                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10428
10429                 ret = i40e_init_dcb(hw);
10430                 if (!ret) {
10431                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10432                                 PMD_INIT_LOG(ERR,
10433                                         "HW doesn't support DCBX offload.");
10434                                 return -ENOTSUP;
10435                         }
10436                 } else {
10437                         PMD_INIT_LOG(ERR,
10438                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10439                                 ret, hw->aq.asq_last_status);
10440                         return -ENOTSUP;
10441                 }
10442         }
10443         return 0;
10444 }
10445
10446 /*
10447  * i40e_dcb_setup - setup dcb related config
10448  * @dev: device being configured
10449  *
10450  * Returns 0 on success, negative value on failure
10451  */
10452 static int
10453 i40e_dcb_setup(struct rte_eth_dev *dev)
10454 {
10455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10456         struct i40e_dcbx_config dcb_cfg;
10457         uint8_t tc_map = 0;
10458         int ret = 0;
10459
10460         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10461                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10462                 return -ENOTSUP;
10463         }
10464
10465         if (pf->vf_num != 0)
10466                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10467
10468         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10469         if (ret) {
10470                 PMD_INIT_LOG(ERR, "invalid dcb config");
10471                 return -EINVAL;
10472         }
10473         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10474         if (ret) {
10475                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10476                 return -ENOSYS;
10477         }
10478
10479         return 0;
10480 }
10481
10482 static int
10483 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10484                       struct rte_eth_dcb_info *dcb_info)
10485 {
10486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10488         struct i40e_vsi *vsi = pf->main_vsi;
10489         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10490         uint16_t bsf, tc_mapping;
10491         int i, j = 0;
10492
10493         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10494                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10495         else
10496                 dcb_info->nb_tcs = 1;
10497         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10498                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10499         for (i = 0; i < dcb_info->nb_tcs; i++)
10500                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10501
10502         /* get queue mapping if vmdq is disabled */
10503         if (!pf->nb_cfg_vmdq_vsi) {
10504                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10505                         if (!(vsi->enabled_tc & (1 << i)))
10506                                 continue;
10507                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10508                         dcb_info->tc_queue.tc_rxq[j][i].base =
10509                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10510                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10511                         dcb_info->tc_queue.tc_txq[j][i].base =
10512                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10513                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10514                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10515                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10516                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10517                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10518                 }
10519                 return 0;
10520         }
10521
10522         /* get queue mapping if vmdq is enabled */
10523         do {
10524                 vsi = pf->vmdq[j].vsi;
10525                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10526                         if (!(vsi->enabled_tc & (1 << i)))
10527                                 continue;
10528                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10529                         dcb_info->tc_queue.tc_rxq[j][i].base =
10530                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10531                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10532                         dcb_info->tc_queue.tc_txq[j][i].base =
10533                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10534                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10535                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10536                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10537                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10538                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10539                 }
10540                 j++;
10541         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10542         return 0;
10543 }
10544
10545 static int
10546 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10547 {
10548         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10549         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10550         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10551         uint16_t interval =
10552                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10553         uint16_t msix_intr;
10554
10555         msix_intr = intr_handle->intr_vec[queue_id];
10556         if (msix_intr == I40E_MISC_VEC_ID)
10557                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10558                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10559                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10560                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10561                                (interval <<
10562                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10563         else
10564                 I40E_WRITE_REG(hw,
10565                                I40E_PFINT_DYN_CTLN(msix_intr -
10566                                                    I40E_RX_VEC_START),
10567                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10568                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10569                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10570                                (interval <<
10571                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10572
10573         I40E_WRITE_FLUSH(hw);
10574         rte_intr_enable(&pci_dev->intr_handle);
10575
10576         return 0;
10577 }
10578
10579 static int
10580 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10581 {
10582         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10583         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10585         uint16_t msix_intr;
10586
10587         msix_intr = intr_handle->intr_vec[queue_id];
10588         if (msix_intr == I40E_MISC_VEC_ID)
10589                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10590         else
10591                 I40E_WRITE_REG(hw,
10592                                I40E_PFINT_DYN_CTLN(msix_intr -
10593                                                    I40E_RX_VEC_START),
10594                                0);
10595         I40E_WRITE_FLUSH(hw);
10596
10597         return 0;
10598 }
10599
10600 static int i40e_get_regs(struct rte_eth_dev *dev,
10601                          struct rte_dev_reg_info *regs)
10602 {
10603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10604         uint32_t *ptr_data = regs->data;
10605         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10606         const struct i40e_reg_info *reg_info;
10607
10608         if (ptr_data == NULL) {
10609                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10610                 regs->width = sizeof(uint32_t);
10611                 return 0;
10612         }
10613
10614         /* The first few registers have to be read using AQ operations */
10615         reg_idx = 0;
10616         while (i40e_regs_adminq[reg_idx].name) {
10617                 reg_info = &i40e_regs_adminq[reg_idx++];
10618                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10619                         for (arr_idx2 = 0;
10620                                         arr_idx2 <= reg_info->count2;
10621                                         arr_idx2++) {
10622                                 reg_offset = arr_idx * reg_info->stride1 +
10623                                         arr_idx2 * reg_info->stride2;
10624                                 reg_offset += reg_info->base_addr;
10625                                 ptr_data[reg_offset >> 2] =
10626                                         i40e_read_rx_ctl(hw, reg_offset);
10627                         }
10628         }
10629
10630         /* The remaining registers can be read using primitives */
10631         reg_idx = 0;
10632         while (i40e_regs_others[reg_idx].name) {
10633                 reg_info = &i40e_regs_others[reg_idx++];
10634                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10635                         for (arr_idx2 = 0;
10636                                         arr_idx2 <= reg_info->count2;
10637                                         arr_idx2++) {
10638                                 reg_offset = arr_idx * reg_info->stride1 +
10639                                         arr_idx2 * reg_info->stride2;
10640                                 reg_offset += reg_info->base_addr;
10641                                 ptr_data[reg_offset >> 2] =
10642                                         I40E_READ_REG(hw, reg_offset);
10643                         }
10644         }
10645
10646         return 0;
10647 }
10648
10649 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10650 {
10651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10652
10653         /* Convert word count to byte count */
10654         return hw->nvm.sr_size << 1;
10655 }
10656
10657 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10658                            struct rte_dev_eeprom_info *eeprom)
10659 {
10660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10661         uint16_t *data = eeprom->data;
10662         uint16_t offset, length, cnt_words;
10663         int ret_code;
10664
10665         offset = eeprom->offset >> 1;
10666         length = eeprom->length >> 1;
10667         cnt_words = length;
10668
10669         if (offset > hw->nvm.sr_size ||
10670                 offset + length > hw->nvm.sr_size) {
10671                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10672                 return -EINVAL;
10673         }
10674
10675         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10676
10677         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10678         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10679                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10680                 return -EIO;
10681         }
10682
10683         return 0;
10684 }
10685
10686 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10687                                       struct ether_addr *mac_addr)
10688 {
10689         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10690
10691         if (!is_valid_assigned_ether_addr(mac_addr)) {
10692                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10693                 return;
10694         }
10695
10696         /* Flags: 0x3 updates port address */
10697         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10698 }
10699
10700 static int
10701 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10702 {
10703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10704         struct rte_eth_dev_data *dev_data = pf->dev_data;
10705         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10706         int ret = 0;
10707
10708         /* check if mtu is within the allowed range */
10709         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10710                 return -EINVAL;
10711
10712         /* mtu setting is forbidden if port is start */
10713         if (dev_data->dev_started) {
10714                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10715                             dev_data->port_id);
10716                 return -EBUSY;
10717         }
10718
10719         if (frame_size > ETHER_MAX_LEN)
10720                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10721         else
10722                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10723
10724         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10725
10726         return ret;
10727 }
10728
10729 /* Restore ethertype filter */
10730 static void
10731 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10732 {
10733         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10734         struct i40e_ethertype_filter_list
10735                 *ethertype_list = &pf->ethertype.ethertype_list;
10736         struct i40e_ethertype_filter *f;
10737         struct i40e_control_filter_stats stats;
10738         uint16_t flags;
10739
10740         TAILQ_FOREACH(f, ethertype_list, rules) {
10741                 flags = 0;
10742                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10743                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10744                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10745                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10746                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10747
10748                 memset(&stats, 0, sizeof(stats));
10749                 i40e_aq_add_rem_control_packet_filter(hw,
10750                                             f->input.mac_addr.addr_bytes,
10751                                             f->input.ether_type,
10752                                             flags, pf->main_vsi->seid,
10753                                             f->queue, 1, &stats, NULL);
10754         }
10755         PMD_DRV_LOG(INFO, "Ethertype filter:"
10756                     " mac_etype_used = %u, etype_used = %u,"
10757                     " mac_etype_free = %u, etype_free = %u",
10758                     stats.mac_etype_used, stats.etype_used,
10759                     stats.mac_etype_free, stats.etype_free);
10760 }
10761
10762 /* Restore tunnel filter */
10763 static void
10764 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10765 {
10766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10767         struct i40e_vsi *vsi;
10768         struct i40e_pf_vf *vf;
10769         struct i40e_tunnel_filter_list
10770                 *tunnel_list = &pf->tunnel.tunnel_list;
10771         struct i40e_tunnel_filter *f;
10772         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10773         bool big_buffer = 0;
10774
10775         TAILQ_FOREACH(f, tunnel_list, rules) {
10776                 if (!f->is_to_vf)
10777                         vsi = pf->main_vsi;
10778                 else {
10779                         vf = &pf->vfs[f->vf_id];
10780                         vsi = vf->vsi;
10781                 }
10782                 memset(&cld_filter, 0, sizeof(cld_filter));
10783                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10784                         (struct ether_addr *)&cld_filter.element.outer_mac);
10785                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10786                         (struct ether_addr *)&cld_filter.element.inner_mac);
10787                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10788                 cld_filter.element.flags = f->input.flags;
10789                 cld_filter.element.tenant_id = f->input.tenant_id;
10790                 cld_filter.element.queue_number = f->queue;
10791                 rte_memcpy(cld_filter.general_fields,
10792                            f->input.general_fields,
10793                            sizeof(f->input.general_fields));
10794
10795                 if (((f->input.flags &
10796                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10797                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10798                     ((f->input.flags &
10799                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10800                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10801                     ((f->input.flags &
10802                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10803                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10804                         big_buffer = 1;
10805
10806                 if (big_buffer)
10807                         i40e_aq_add_cloud_filters_big_buffer(hw,
10808                                              vsi->seid, &cld_filter, 1);
10809                 else
10810                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10811                                                   &cld_filter.element, 1);
10812         }
10813 }
10814
10815 static void
10816 i40e_filter_restore(struct i40e_pf *pf)
10817 {
10818         i40e_ethertype_filter_restore(pf);
10819         i40e_tunnel_filter_restore(pf);
10820         i40e_fdir_filter_restore(pf);
10821 }
10822
10823 static bool
10824 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10825 {
10826         if (strcmp(dev->device->driver->name, drv->driver.name))
10827                 return false;
10828
10829         return true;
10830 }
10831
10832 bool
10833 is_i40e_supported(struct rte_eth_dev *dev)
10834 {
10835         return is_device_supported(dev, &rte_i40e_pmd);
10836 }
10837
10838 /* Create a QinQ cloud filter
10839  *
10840  * The Fortville NIC has limited resources for tunnel filters,
10841  * so we can only reuse existing filters.
10842  *
10843  * In step 1 we define which Field Vector fields can be used for
10844  * filter types.
10845  * As we do not have the inner tag defined as a field,
10846  * we have to define it first, by reusing one of L1 entries.
10847  *
10848  * In step 2 we are replacing one of existing filter types with
10849  * a new one for QinQ.
10850  * As we reusing L1 and replacing L2, some of the default filter
10851  * types will disappear,which depends on L1 and L2 entries we reuse.
10852  *
10853  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10854  *
10855  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10856  *              later when we define the cloud filter.
10857  *      a.      Valid_flags.replace_cloud = 0
10858  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10859  *      c.      New_filter = 0x10
10860  *      d.      TR bit = 0xff (optional, not used here)
10861  *      e.      Buffer – 2 entries:
10862  *              i.      Byte 0 = 8 (outer vlan FV index).
10863  *                      Byte 1 = 0 (rsv)
10864  *                      Byte 2-3 = 0x0fff
10865  *              ii.     Byte 0 = 37 (inner vlan FV index).
10866  *                      Byte 1 =0 (rsv)
10867  *                      Byte 2-3 = 0x0fff
10868  *
10869  * Step 2:
10870  * 2.   Create cloud filter using two L1 filters entries: stag and
10871  *              new filter(outer vlan+ inner vlan)
10872  *      a.      Valid_flags.replace_cloud = 1
10873  *      b.      Old_filter = 1 (instead of outer IP)
10874  *      c.      New_filter = 0x10
10875  *      d.      Buffer – 2 entries:
10876  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10877  *                      Byte 1-3 = 0 (rsv)
10878  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10879  *                      Byte 9-11 = 0 (rsv)
10880  */
10881 static int
10882 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10883 {
10884         int ret = -ENOTSUP;
10885         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10886         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10887         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10888
10889         /* Init */
10890         memset(&filter_replace, 0,
10891                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10892         memset(&filter_replace_buf, 0,
10893                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10894
10895         /* create L1 filter */
10896         filter_replace.old_filter_type =
10897                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10898         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10899         filter_replace.tr_bit = 0;
10900
10901         /* Prepare the buffer, 2 entries */
10902         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10903         filter_replace_buf.data[0] |=
10904                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10905         /* Field Vector 12b mask */
10906         filter_replace_buf.data[2] = 0xff;
10907         filter_replace_buf.data[3] = 0x0f;
10908         filter_replace_buf.data[4] =
10909                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10910         filter_replace_buf.data[4] |=
10911                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10912         /* Field Vector 12b mask */
10913         filter_replace_buf.data[6] = 0xff;
10914         filter_replace_buf.data[7] = 0x0f;
10915         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10916                         &filter_replace_buf);
10917         if (ret != I40E_SUCCESS)
10918                 return ret;
10919
10920         /* Apply the second L2 cloud filter */
10921         memset(&filter_replace, 0,
10922                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10923         memset(&filter_replace_buf, 0,
10924                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10925
10926         /* create L2 filter, input for L2 filter will be L1 filter  */
10927         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10928         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10929         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10930
10931         /* Prepare the buffer, 2 entries */
10932         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10933         filter_replace_buf.data[0] |=
10934                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10935         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10936         filter_replace_buf.data[4] |=
10937                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10938         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10939                         &filter_replace_buf);
10940         return ret;
10941 }
10942
10943 RTE_INIT(i40e_init_log);
10944 static void
10945 i40e_init_log(void)
10946 {
10947         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10948         if (i40e_logtype_init >= 0)
10949                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10950         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10951         if (i40e_logtype_driver >= 0)
10952                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10953 }