drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 115
 116 #define I40E_FLOW_TYPES ( \
 117         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 122         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 127         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 128
 129 /* Additional timesync values. */
 130 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 131 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 132 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 133 #define I40E_PRTTSYN_TSYNENA     0x80000000
 134 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 135 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 136
 137 #define I40E_MAX_PERCENT            100
 138 #define I40E_DEFAULT_DCB_APP_NUM    1
 139 #define I40E_DEFAULT_DCB_APP_PRIO   3
 140
 141 #define I40E_INSET_NONE            0x00000000000000000ULL
 142
 143 /* bit0 ~ bit 7 */
 144 #define I40E_INSET_DMAC            0x0000000000000001ULL
 145 #define I40E_INSET_SMAC            0x0000000000000002ULL
 146 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 147 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 148 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 149
 150 /* bit 8 ~ bit 15 */
 151 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 152 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 153 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 154 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 155 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 156 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 157 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 158
 159 /* bit 16 ~ bit 31 */
 160 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 161 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 162 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 163 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 164 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 165 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 166 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 167 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 168
 169 /* bit 32 ~ bit 47, tunnel fields */
 170 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 171 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 172 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 173 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 174 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 175 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 176
 177 /* bit 48 ~ bit 55 */
 178 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 179
 180 /* bit 56 ~ bit 63, Flex Payload */
 181 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD \
 190         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 191         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 192         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 193         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 194
 195 /**
 196  * Below are values for writing un-exposed registers suggested
 197  * by silicon experts
 198  */
 199 /* Destination MAC address */
 200 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 201 /* Source MAC address */
 202 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 203 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 204 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 205 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 206 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 207 /* Single VLAN tag in the inner L2 header */
 208 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 209 /* Source IPv4 address */
 210 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 211 /* Destination IPv4 address */
 212 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 213 /* Source IPv4 address for X722 */
 214 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 215 /* Destination IPv4 address for X722 */
 216 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 217 /* IPv4 Protocol for X722 */
 218 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 219 /* IPv4 Time to Live for X722 */
 220 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 221 /* IPv4 Type of Service (TOS) */
 222 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 223 /* IPv4 Protocol */
 224 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 225 /* IPv4 Time to Live */
 226 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 227 /* Source IPv6 address */
 228 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 229 /* Destination IPv6 address */
 230 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 231 /* IPv6 Traffic Class (TC) */
 232 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 233 /* IPv6 Next Header */
 234 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 235 /* IPv6 Hop Limit */
 236 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 237 /* Source L4 port */
 238 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 239 /* Destination L4 port */
 240 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 241 /* SCTP verification tag */
 242 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 243 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 244 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 245 /* Source port of tunneling UDP */
 246 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 247 /* Destination port of tunneling UDP */
 248 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 249 /* UDP Tunneling ID, NVGRE/GRE key */
 250 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 251 /* Last ether type */
 252 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 253 /* Tunneling outer destination IPv4 address */
 254 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 255 /* Tunneling outer destination IPv6 address */
 256 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 257 /* 1st word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 259 /* 2nd word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 261 /* 3rd word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 263 /* 4th word of flex payload */
 264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 265 /* 5th word of flex payload */
 266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 267 /* 6th word of flex payload */
 268 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 269 /* 7th word of flex payload */
 270 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 271 /* 8th word of flex payload */
 272 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 273 /* all 8 words flex payload */
 274 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 275 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 276
 277 #define I40E_TRANSLATE_INSET 0
 278 #define I40E_TRANSLATE_REG   1
 279
 280 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 281 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 282 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 283 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 284 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 285 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 286
 287 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 288 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 290         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 291
 292 /* PCI offset for querying capability */
 293 #define PCI_DEV_CAP_REG            0xA4
 294 /* PCI offset for enabling/disabling Extended Tag */
 295 #define PCI_DEV_CTRL_REG           0xA8
 296 /* Bit mask of Extended Tag capability */
 297 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 298 /* Bit shift of Extended Tag enable/disable */
 299 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 300 /* Bit mask of Extended Tag enable/disable */
 301 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 302
 303 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 304 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 305 static int i40e_dev_configure(struct rte_eth_dev *dev);
 306 static int i40e_dev_start(struct rte_eth_dev *dev);
 307 static void i40e_dev_stop(struct rte_eth_dev *dev);
 308 static void i40e_dev_close(struct rte_eth_dev *dev);
 309 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 311 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 313 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 315 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 316                                struct rte_eth_stats *stats);
 317 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 318                                struct rte_eth_xstat *xstats, unsigned n);
 319 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 320                                      struct rte_eth_xstat_name *xstats_names,
 321                                      unsigned limit);
 322 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 323 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 324                                             uint16_t queue_id,
 325                                             uint8_t stat_idx,
 326                                             uint8_t is_rx);
 327 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_dev_info *dev_info);
 329 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 330                                 uint16_t vlan_id,
 331                                 int on);
 332 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 333                               enum rte_vlan_type vlan_type,
 334                               uint16_t tpid);
 335 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 336 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 337                                       uint16_t queue,
 338                                       int on);
 339 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 340 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 341 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 342 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 343                               struct rte_eth_fc_conf *fc_conf);
 344 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 345                               struct rte_eth_fc_conf *fc_conf);
 346 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 347                                        struct rte_eth_pfc_conf *pfc_conf);
 348 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 349                           struct ether_addr *mac_addr,
 350                           uint32_t index,
 351                           uint32_t pool);
 352 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 353 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 354                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 355                                     uint16_t reta_size);
 356 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 357                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                    uint16_t reta_size);
 359
 360 static int i40e_get_cap(struct i40e_hw *hw);
 361 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 362 static int i40e_pf_setup(struct i40e_pf *pf);
 363 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 364 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 365 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 366 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 367 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 368                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 369 static void i40e_stat_update_48(struct i40e_hw *hw,
 370                                uint32_t hireg,
 371                                uint32_t loreg,
 372                                bool offset_loaded,
 373                                uint64_t *offset,
 374                                uint64_t *stat);
 375 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 376 static void i40e_dev_interrupt_handler(
 377                 __rte_unused struct rte_intr_handle *handle, void *param);
 378 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 379                                 uint32_t base, uint32_t num);
 380 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 381 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 382                         uint32_t base);
 383 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 384                         uint16_t num);
 385 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 386 static int i40e_veb_release(struct i40e_veb *veb);
 387 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 388                                                 struct i40e_vsi *vsi);
 389 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 390 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 391 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 392                                              struct i40e_macvlan_filter *mv_f,
 393                                              int num,
 394                                              struct ether_addr *addr);
 395 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 396                                              struct i40e_macvlan_filter *mv_f,
 397                                              int num,
 398                                              uint16_t vlan);
 399 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 400 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 401                                     struct rte_eth_rss_conf *rss_conf);
 402 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 403                                       struct rte_eth_rss_conf *rss_conf);
 404 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 405                                         struct rte_eth_udp_tunnel *udp_tunnel);
 406 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 407                                         struct rte_eth_udp_tunnel *udp_tunnel);
 408 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 409 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 410                         struct rte_eth_ethertype_filter *filter,
 411                         bool add);
 412 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 413                                 enum rte_filter_op filter_op,
 414                                 void *arg);
 415 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 416                                 enum rte_filter_type filter_type,
 417                                 enum rte_filter_op filter_op,
 418                                 void *arg);
 419 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 420                                   struct rte_eth_dcb_info *dcb_info);
 421 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 422 static void i40e_configure_registers(struct i40e_hw *hw);
 423 static void i40e_hw_init(struct rte_eth_dev *dev);
 424 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 425 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 426                         struct rte_eth_mirror_conf *mirror_conf,
 427                         uint8_t sw_id, uint8_t on);
 428 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 429
 430 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 431 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 433                                            struct timespec *timestamp,
 434                                            uint32_t flags);
 435 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp);
 437 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 438
 439 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 440
 441 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 442                                    struct timespec *timestamp);
 443 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 444                                     const struct timespec *timestamp);
 445
 446 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 447                                          uint16_t queue_id);
 448 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 449                                           uint16_t queue_id);
 450
 451 static int i40e_get_regs(struct rte_eth_dev *dev,
 452                          struct rte_dev_reg_info *regs);
 453
 454 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 455
 456 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 457                            struct rte_dev_eeprom_info *eeprom);
 458
 459 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 460                                       struct ether_addr *mac_addr);
 461
 462 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 463
 464 static const struct rte_pci_id pci_id_i40e_map[] = {
 465         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 485         { .vendor_id = 0, /* sentinel */ },
 486 };
 487
 488 static const struct eth_dev_ops i40e_eth_dev_ops = {
 489         .dev_configure                = i40e_dev_configure,
 490         .dev_start                    = i40e_dev_start,
 491         .dev_stop                     = i40e_dev_stop,
 492         .dev_close                    = i40e_dev_close,
 493         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 494         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 495         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 496         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 497         .dev_set_link_up              = i40e_dev_set_link_up,
 498         .dev_set_link_down            = i40e_dev_set_link_down,
 499         .link_update                  = i40e_dev_link_update,
 500         .stats_get                    = i40e_dev_stats_get,
 501         .xstats_get                   = i40e_dev_xstats_get,
 502         .xstats_get_names             = i40e_dev_xstats_get_names,
 503         .stats_reset                  = i40e_dev_stats_reset,
 504         .xstats_reset                 = i40e_dev_stats_reset,
 505         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 506         .dev_infos_get                = i40e_dev_info_get,
 507         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 508         .vlan_filter_set              = i40e_vlan_filter_set,
 509         .vlan_tpid_set                = i40e_vlan_tpid_set,
 510         .vlan_offload_set             = i40e_vlan_offload_set,
 511         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 512         .vlan_pvid_set                = i40e_vlan_pvid_set,
 513         .rx_queue_start               = i40e_dev_rx_queue_start,
 514         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 515         .tx_queue_start               = i40e_dev_tx_queue_start,
 516         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 517         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 518         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 519         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 520         .rx_queue_release             = i40e_dev_rx_queue_release,
 521         .rx_queue_count               = i40e_dev_rx_queue_count,
 522         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 523         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 524         .tx_queue_release             = i40e_dev_tx_queue_release,
 525         .dev_led_on                   = i40e_dev_led_on,
 526         .dev_led_off                  = i40e_dev_led_off,
 527         .flow_ctrl_get                = i40e_flow_ctrl_get,
 528         .flow_ctrl_set                = i40e_flow_ctrl_set,
 529         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 530         .mac_addr_add                 = i40e_macaddr_add,
 531         .mac_addr_remove              = i40e_macaddr_remove,
 532         .reta_update                  = i40e_dev_rss_reta_update,
 533         .reta_query                   = i40e_dev_rss_reta_query,
 534         .rss_hash_update              = i40e_dev_rss_hash_update,
 535         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 536         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 537         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 538         .filter_ctrl                  = i40e_dev_filter_ctrl,
 539         .rxq_info_get                 = i40e_rxq_info_get,
 540         .txq_info_get                 = i40e_txq_info_get,
 541         .mirror_rule_set              = i40e_mirror_rule_set,
 542         .mirror_rule_reset            = i40e_mirror_rule_reset,
 543         .timesync_enable              = i40e_timesync_enable,
 544         .timesync_disable             = i40e_timesync_disable,
 545         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 546         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 547         .get_dcb_info                 = i40e_dev_get_dcb_info,
 548         .timesync_adjust_time         = i40e_timesync_adjust_time,
 549         .timesync_read_time           = i40e_timesync_read_time,
 550         .timesync_write_time          = i40e_timesync_write_time,
 551         .get_reg                      = i40e_get_regs,
 552         .get_eeprom_length            = i40e_get_eeprom_length,
 553         .get_eeprom                   = i40e_get_eeprom,
 554         .mac_addr_set                 = i40e_set_default_mac_addr,
 555         .mtu_set                      = i40e_dev_mtu_set,
 556 };
 557
 558 /* store statistics names and its offset in stats structure */
 559 struct rte_i40e_xstats_name_off {
 560         char name[RTE_ETH_XSTATS_NAME_SIZE];
 561         unsigned offset;
 562 };
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 565         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 566         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 567         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 568         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 569         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 570                 rx_unknown_protocol)},
 571         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 572         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 573         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 574         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 575 };
 576
 577 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 578                 sizeof(rte_i40e_stats_strings[0]))
 579
 580 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 581         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 582                 tx_dropped_link_down)},
 583         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 584         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 585                 illegal_bytes)},
 586         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 587         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 588                 mac_local_faults)},
 589         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 590                 mac_remote_faults)},
 591         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 592                 rx_length_errors)},
 593         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 594         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 595         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 596         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 597         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 598         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 599                 rx_size_127)},
 600         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 601                 rx_size_255)},
 602         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 603                 rx_size_511)},
 604         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 605                 rx_size_1023)},
 606         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 607                 rx_size_1522)},
 608         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 609                 rx_size_big)},
 610         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_undersize)},
 612         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 613                 rx_oversize)},
 614         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 615                 mac_short_packet_dropped)},
 616         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 617                 rx_fragments)},
 618         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 619         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 620         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 621                 tx_size_127)},
 622         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 623                 tx_size_255)},
 624         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 625                 tx_size_511)},
 626         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 627                 tx_size_1023)},
 628         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 629                 tx_size_1522)},
 630         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 631                 tx_size_big)},
 632         {"rx_flow_director_atr_match_packets",
 633                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 634         {"rx_flow_director_sb_match_packets",
 635                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 636         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 637                 tx_lpi_status)},
 638         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 639                 rx_lpi_status)},
 640         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 641                 tx_lpi_count)},
 642         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 643                 rx_lpi_count)},
 644 };
 645
 646 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 647                 sizeof(rte_i40e_hw_port_strings[0]))
 648
 649 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 650         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 651                 priority_xon_rx)},
 652         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 653                 priority_xoff_rx)},
 654 };
 655
 656 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 657                 sizeof(rte_i40e_rxq_prio_strings[0]))
 658
 659 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 660         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 661                 priority_xon_tx)},
 662         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 663                 priority_xoff_tx)},
 664         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 665                 priority_xon_2_xoff)},
 666 };
 667
 668 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 669                 sizeof(rte_i40e_txq_prio_strings[0]))
 670
 671 static struct eth_driver rte_i40e_pmd = {
 672         .pci_drv = {
 673                 .id_table = pci_id_i40e_map,
 674                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 675                         RTE_PCI_DRV_DETACHABLE,
 676                 .probe = rte_eth_dev_pci_probe,
 677                 .remove = rte_eth_dev_pci_remove,
 678         },
 679         .eth_dev_init = eth_i40e_dev_init,
 680         .eth_dev_uninit = eth_i40e_dev_uninit,
 681         .dev_private_size = sizeof(struct i40e_adapter),
 682 };
 683
 684 static inline int
 685 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 686                                      struct rte_eth_link *link)
 687 {
 688         struct rte_eth_link *dst = link;
 689         struct rte_eth_link *src = &(dev->data->dev_link);
 690
 691         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 692                                         *(uint64_t *)src) == 0)
 693                 return -1;
 694
 695         return 0;
 696 }
 697
 698 static inline int
 699 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 700                                       struct rte_eth_link *link)
 701 {
 702         struct rte_eth_link *dst = &(dev->data->dev_link);
 703         struct rte_eth_link *src = link;
 704
 705         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 706                                         *(uint64_t *)src) == 0)
 707                 return -1;
 708
 709         return 0;
 710 }
 711
 712 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 713 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 714 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 715
 716 #ifndef I40E_GLQF_ORT
 717 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 718 #endif
 719 #ifndef I40E_GLQF_PIT
 720 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 721 #endif
 722
 723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 724 {
 725         /*
 726          * Initialize registers for flexible payload, which should be set by NVM.
 727          * This should be removed from code once it is fixed in NVM.
 728          */
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 740         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 741
 742         /* Initialize registers for parsing packet type of QinQ */
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 744         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 745 }
 746
 747 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 748
 749 /*
 750  * Add a ethertype filter to drop all flow control frames transmitted
 751  * from VSIs.
 752 */
 753 static void
 754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 759                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 760         int ret;
 761
 762         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 763                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 764                                 pf->main_vsi_seid, 0,
 765                                 TRUE, NULL, NULL);
 766         if (ret)
 767                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 768                                   " frames from VSIs.");
 769 }
 770
 771 static int
 772 floating_veb_list_handler(__rte_unused const char *key,
 773                           const char *floating_veb_value,
 774                           void *opaque)
 775 {
 776         int idx = 0;
 777         unsigned int count = 0;
 778         char *end = NULL;
 779         int min, max;
 780         bool *vf_floating_veb = opaque;
 781
 782         while (isblank(*floating_veb_value))
 783                 floating_veb_value++;
 784
 785         /* Reset floating VEB configuration for VFs */
 786         for (idx = 0; idx < I40E_MAX_VF; idx++)
 787                 vf_floating_veb[idx] = false;
 788
 789         min = I40E_MAX_VF;
 790         do {
 791                 while (isblank(*floating_veb_value))
 792                         floating_veb_value++;
 793                 if (*floating_veb_value == '\0')
 794                         return -1;
 795                 errno = 0;
 796                 idx = strtoul(floating_veb_value, &end, 10);
 797                 if (errno || end == NULL)
 798                         return -1;
 799                 while (isblank(*end))
 800                         end++;
 801                 if (*end == '-') {
 802                         min = idx;
 803                 } else if ((*end == ';') || (*end == '\0')) {
 804                         max = idx;
 805                         if (min == I40E_MAX_VF)
 806                                 min = idx;
 807                         if (max >= I40E_MAX_VF)
 808                                 max = I40E_MAX_VF - 1;
 809                         for (idx = min; idx <= max; idx++) {
 810                                 vf_floating_veb[idx] = true;
 811                                 count++;
 812                         }
 813                         min = I40E_MAX_VF;
 814                 } else {
 815                         return -1;
 816                 }
 817                 floating_veb_value = end + 1;
 818         } while (*end != '\0');
 819
 820         if (count == 0)
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static void
 827 config_vf_floating_veb(struct rte_devargs *devargs,
 828                        uint16_t floating_veb,
 829                        bool *vf_floating_veb)
 830 {
 831         struct rte_kvargs *kvlist;
 832         int i;
 833         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 834
 835         if (!floating_veb)
 836                 return;
 837         /* All the VFs attach to the floating VEB by default
 838          * when the floating VEB is enabled.
 839          */
 840         for (i = 0; i < I40E_MAX_VF; i++)
 841                 vf_floating_veb[i] = true;
 842
 843         if (devargs == NULL)
 844                 return;
 845
 846         kvlist = rte_kvargs_parse(devargs->args, NULL);
 847         if (kvlist == NULL)
 848                 return;
 849
 850         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         /* When the floating_veb_list parameter exists, all the VFs
 855          * will attach to the legacy VEB firstly, then configure VFs
 856          * to the floating VEB according to the floating_veb_list.
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_list,
 859                                floating_veb_list_handler,
 860                                vf_floating_veb) < 0) {
 861                 rte_kvargs_free(kvlist);
 862                 return;
 863         }
 864         rte_kvargs_free(kvlist);
 865 }
 866
 867 static int
 868 i40e_check_floating_handler(__rte_unused const char *key,
 869                             const char *value,
 870                             __rte_unused void *opaque)
 871 {
 872         if (strcmp(value, "1"))
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static int
 879 is_floating_veb_supported(struct rte_devargs *devargs)
 880 {
 881         struct rte_kvargs *kvlist;
 882         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 883
 884         if (devargs == NULL)
 885                 return 0;
 886
 887         kvlist = rte_kvargs_parse(devargs->args, NULL);
 888         if (kvlist == NULL)
 889                 return 0;
 890
 891         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         /* Floating VEB is enabled when there's key-value:
 896          * enable_floating_veb=1
 897          */
 898         if (rte_kvargs_process(kvlist, floating_veb_key,
 899                                i40e_check_floating_handler, NULL) < 0) {
 900                 rte_kvargs_free(kvlist);
 901                 return 0;
 902         }
 903         rte_kvargs_free(kvlist);
 904
 905         return 1;
 906 }
 907
 908 static void
 909 config_floating_veb(struct rte_eth_dev *dev)
 910 {
 911         struct rte_pci_device *pci_dev = dev->pci_dev;
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914
 915         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 916
 917         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 918                 pf->floating_veb =
 919                         is_floating_veb_supported(pci_dev->device.devargs);
 920                 config_vf_floating_veb(pci_dev->device.devargs,
 921                                        pf->floating_veb,
 922                                        pf->floating_veb_list);
 923         } else {
 924                 pf->floating_veb = false;
 925         }
 926 }
 927
 928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 930
 931 static int
 932 eth_i40e_dev_init(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev;
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937         struct i40e_vsi *vsi;
 938         int ret;
 939         uint32_t len;
 940         uint8_t aq_fail = 0;
 941
 942         PMD_INIT_FUNC_TRACE();
 943
 944         dev->dev_ops = &i40e_eth_dev_ops;
 945         dev->rx_pkt_burst = i40e_recv_pkts;
 946         dev->tx_pkt_burst = i40e_xmit_pkts;
 947
 948         /* for secondary processes, we don't initialise any further as primary
 949          * has already done this work. Only check we don't need a different
 950          * RX function */
 951         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 952                 i40e_set_rx_function(dev);
 953                 i40e_set_tx_function(dev);
 954                 return 0;
 955         }
 956         pci_dev = dev->pci_dev;
 957
 958         rte_eth_copy_pci_info(dev, pci_dev);
 959
 960         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 961         pf->adapter->eth_dev = dev;
 962         pf->dev_data = dev->data;
 963
 964         hw->back = I40E_PF_TO_ADAPTER(pf);
 965         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 966         if (!hw->hw_addr) {
 967                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 968                              "as address is NULL");
 969                 return -ENODEV;
 970         }
 971
 972         hw->vendor_id = pci_dev->id.vendor_id;
 973         hw->device_id = pci_dev->id.device_id;
 974         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 975         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 976         hw->bus.device = pci_dev->addr.devid;
 977         hw->bus.func = pci_dev->addr.function;
 978         hw->adapter_stopped = 0;
 979
 980         /* Make sure all is clean before doing PF reset */
 981         i40e_clear_hw(hw);
 982
 983         /* Initialize the hardware */
 984         i40e_hw_init(dev);
 985
 986         /* Reset here to make sure all is clean for each PF */
 987         ret = i40e_pf_reset(hw);
 988         if (ret) {
 989                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 990                 return ret;
 991         }
 992
 993         /* Initialize the shared code (base driver) */
 994         ret = i40e_init_shared_code(hw);
 995         if (ret) {
 996                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 997                 return ret;
 998         }
 999
1000         /*
1001          * To work around the NVM issue, initialize registers
1002          * for flexible payload and packet type of QinQ by
1003          * software. It should be removed once issues are fixed
1004          * in NVM.
1005          */
1006         i40e_GLQF_reg_init(hw);
1007
1008         /* Initialize the input set for filters (hash and fd) to default value */
1009         i40e_filter_input_set_init(pf);
1010
1011         /* Initialize the parameters for adminq */
1012         i40e_init_adminq_parameter(hw);
1013         ret = i40e_init_adminq(hw);
1014         if (ret != I40E_SUCCESS) {
1015                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1016                 return -EIO;
1017         }
1018         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1019                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1020                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1021                      ((hw->nvm.version >> 12) & 0xf),
1022                      ((hw->nvm.version >> 4) & 0xff),
1023                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1024
1025         /* Need the special FW version to support floating VEB */
1026         config_floating_veb(dev);
1027         /* Clear PXE mode */
1028         i40e_clear_pxe_mode(hw);
1029         ret = i40e_dev_sync_phy_type(hw);
1030         if (ret) {
1031                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1032                 goto err_sync_phy_type;
1033         }
1034         /*
1035          * On X710, performance number is far from the expectation on recent
1036          * firmware versions. The fix for this issue may not be integrated in
1037          * the following firmware version. So the workaround in software driver
1038          * is needed. It needs to modify the initial values of 3 internal only
1039          * registers. Note that the workaround can be removed when it is fixed
1040          * in firmware in the future.
1041          */
1042         i40e_configure_registers(hw);
1043
1044         /* Get hw capabilities */
1045         ret = i40e_get_cap(hw);
1046         if (ret != I40E_SUCCESS) {
1047                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1048                 goto err_get_capabilities;
1049         }
1050
1051         /* Initialize parameters for PF */
1052         ret = i40e_pf_parameter_init(dev);
1053         if (ret != 0) {
1054                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1055                 goto err_parameter_init;
1056         }
1057
1058         /* Initialize the queue management */
1059         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1060         if (ret < 0) {
1061                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1062                 goto err_qp_pool_init;
1063         }
1064         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1065                                 hw->func_caps.num_msix_vectors - 1);
1066         if (ret < 0) {
1067                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1068                 goto err_msix_pool_init;
1069         }
1070
1071         /* Initialize lan hmc */
1072         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1073                                 hw->func_caps.num_rx_qp, 0, 0);
1074         if (ret != I40E_SUCCESS) {
1075                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1076                 goto err_init_lan_hmc;
1077         }
1078
1079         /* Configure lan hmc */
1080         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1081         if (ret != I40E_SUCCESS) {
1082                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1083                 goto err_configure_lan_hmc;
1084         }
1085
1086         /* Get and check the mac address */
1087         i40e_get_mac_addr(hw, hw->mac.addr);
1088         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1089                 PMD_INIT_LOG(ERR, "mac address is not valid");
1090                 ret = -EIO;
1091                 goto err_get_mac_addr;
1092         }
1093         /* Copy the permanent MAC address */
1094         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1095                         (struct ether_addr *) hw->mac.perm_addr);
1096
1097         /* Disable flow control */
1098         hw->fc.requested_mode = I40E_FC_NONE;
1099         i40e_set_fc(hw, &aq_fail, TRUE);
1100
1101         /* Set the global registers with default ether type value */
1102         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1103         if (ret != I40E_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1105                              "VLAN ether type");
1106                 goto err_setup_pf_switch;
1107         }
1108
1109         /* PF setup, which includes VSI setup */
1110         ret = i40e_pf_setup(pf);
1111         if (ret) {
1112                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1113                 goto err_setup_pf_switch;
1114         }
1115
1116         /* reset all stats of the device, including pf and main vsi */
1117         i40e_dev_stats_reset(dev);
1118
1119         vsi = pf->main_vsi;
1120
1121         /* Disable double vlan by default */
1122         i40e_vsi_config_double_vlan(vsi, FALSE);
1123
1124         /* Disable S-TAG identification when floating_veb is disabled */
1125         if (!pf->floating_veb) {
1126                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1127                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1128                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1129                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1130                 }
1131         }
1132
1133         if (!vsi->max_macaddrs)
1134                 len = ETHER_ADDR_LEN;
1135         else
1136                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1137
1138         /* Should be after VSI initialized */
1139         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1140         if (!dev->data->mac_addrs) {
1141                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1142                                         "for storing mac address");
1143                 goto err_mac_alloc;
1144         }
1145         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1146                                         &dev->data->mac_addrs[0]);
1147
1148         /* initialize pf host driver to setup SRIOV resource if applicable */
1149         i40e_pf_host_init(dev);
1150
1151         /* register callback func to eal lib */
1152         rte_intr_callback_register(&(pci_dev->intr_handle),
1153                 i40e_dev_interrupt_handler, (void *)dev);
1154
1155         /* configure and enable device interrupt */
1156         i40e_pf_config_irq0(hw, TRUE);
1157         i40e_pf_enable_irq0(hw);
1158
1159         /* enable uio intr after callback register */
1160         rte_intr_enable(&(pci_dev->intr_handle));
1161         /*
1162          * Add an ethertype filter to drop all flow control frames transmitted
1163          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1164          * frames to wire.
1165          */
1166         i40e_add_tx_flow_control_drop_filter(pf);
1167
1168         /* Set the max frame size to 0x2600 by default,
1169          * in case other drivers changed the default value.
1170          */
1171         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1172
1173         /* initialize mirror rule list */
1174         TAILQ_INIT(&pf->mirror_list);
1175
1176         /* Init dcb to sw mode by default */
1177         ret = i40e_dcb_init_configure(dev, TRUE);
1178         if (ret != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1180                 pf->flags &= ~I40E_FLAG_DCB;
1181         }
1182
1183         return 0;
1184
1185 err_mac_alloc:
1186         i40e_vsi_release(pf->main_vsi);
1187 err_setup_pf_switch:
1188 err_get_mac_addr:
1189 err_configure_lan_hmc:
1190         (void)i40e_shutdown_lan_hmc(hw);
1191 err_init_lan_hmc:
1192         i40e_res_pool_destroy(&pf->msix_pool);
1193 err_msix_pool_init:
1194         i40e_res_pool_destroy(&pf->qp_pool);
1195 err_qp_pool_init:
1196 err_parameter_init:
1197 err_get_capabilities:
1198 err_sync_phy_type:
1199         (void)i40e_shutdown_adminq(hw);
1200
1201         return ret;
1202 }
1203
1204 static int
1205 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1206 {
1207         struct rte_pci_device *pci_dev;
1208         struct i40e_hw *hw;
1209         struct i40e_filter_control_settings settings;
1210         int ret;
1211         uint8_t aq_fail = 0;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216                 return 0;
1217
1218         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219         pci_dev = dev->pci_dev;
1220
1221         if (hw->adapter_stopped == 0)
1222                 i40e_dev_close(dev);
1223
1224         dev->dev_ops = NULL;
1225         dev->rx_pkt_burst = NULL;
1226         dev->tx_pkt_burst = NULL;
1227
1228         /* Clear PXE mode */
1229         i40e_clear_pxe_mode(hw);
1230
1231         /* Unconfigure filter control */
1232         memset(&settings, 0, sizeof(settings));
1233         ret = i40e_set_filter_control(hw, &settings);
1234         if (ret)
1235                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1236                                         ret);
1237
1238         /* Disable flow control */
1239         hw->fc.requested_mode = I40E_FC_NONE;
1240         i40e_set_fc(hw, &aq_fail, TRUE);
1241
1242         /* uninitialize pf host driver */
1243         i40e_pf_host_uninit(dev);
1244
1245         rte_free(dev->data->mac_addrs);
1246         dev->data->mac_addrs = NULL;
1247
1248         /* disable uio intr before callback unregister */
1249         rte_intr_disable(&(pci_dev->intr_handle));
1250
1251         /* register callback func to eal lib */
1252         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1253                 i40e_dev_interrupt_handler, (void *)dev);
1254
1255         return 0;
1256 }
1257
1258 static int
1259 i40e_dev_configure(struct rte_eth_dev *dev)
1260 {
1261         struct i40e_adapter *ad =
1262                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1263         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1264         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1265         int i, ret;
1266
1267         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1268          * bulk allocation or vector Rx preconditions we will reset it.
1269          */
1270         ad->rx_bulk_alloc_allowed = true;
1271         ad->rx_vec_allowed = true;
1272         ad->tx_simple_allowed = true;
1273         ad->tx_vec_allowed = true;
1274
1275         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1276                 ret = i40e_fdir_setup(pf);
1277                 if (ret != I40E_SUCCESS) {
1278                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1279                         return -ENOTSUP;
1280                 }
1281                 ret = i40e_fdir_configure(dev);
1282                 if (ret < 0) {
1283                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1284                         goto err;
1285                 }
1286         } else
1287                 i40e_fdir_teardown(pf);
1288
1289         ret = i40e_dev_init_vlan(dev);
1290         if (ret < 0)
1291                 goto err;
1292
1293         /* VMDQ setup.
1294          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1295          *  RSS setting have different requirements.
1296          *  General PMD driver call sequence are NIC init, configure,
1297          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1298          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1299          *  applicable. So, VMDQ setting has to be done before
1300          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1301          *  For RSS setting, it will try to calculate actual configured RX queue
1302          *  number, which will be available after rx_queue_setup(). dev_start()
1303          *  function is good to place RSS setup.
1304          */
1305         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1306                 ret = i40e_vmdq_setup(dev);
1307                 if (ret)
1308                         goto err;
1309         }
1310
1311         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1312                 ret = i40e_dcb_setup(dev);
1313                 if (ret) {
1314                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1315                         goto err_dcb;
1316                 }
1317         }
1318
1319         return 0;
1320
1321 err_dcb:
1322         /* need to release vmdq resource if exists */
1323         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1324                 i40e_vsi_release(pf->vmdq[i].vsi);
1325                 pf->vmdq[i].vsi = NULL;
1326         }
1327         rte_free(pf->vmdq);
1328         pf->vmdq = NULL;
1329 err:
1330         /* need to release fdir resource if exists */
1331         i40e_fdir_teardown(pf);
1332         return ret;
1333 }
1334
1335 void
1336 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1337 {
1338         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1339         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1340         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1341         uint16_t msix_vect = vsi->msix_intr;
1342         uint16_t i;
1343
1344         for (i = 0; i < vsi->nb_qps; i++) {
1345                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1346                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1347                 rte_wmb();
1348         }
1349
1350         if (vsi->type != I40E_VSI_SRIOV) {
1351                 if (!rte_intr_allow_others(intr_handle)) {
1352                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1353                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1354                         I40E_WRITE_REG(hw,
1355                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1356                                        0);
1357                 } else {
1358                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1359                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1360                         I40E_WRITE_REG(hw,
1361                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1362                                                        msix_vect - 1), 0);
1363                 }
1364         } else {
1365                 uint32_t reg;
1366                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1367                         vsi->user_param + (msix_vect - 1);
1368
1369                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1370                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1371         }
1372         I40E_WRITE_FLUSH(hw);
1373 }
1374
1375 static void
1376 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1377                        int base_queue, int nb_queue)
1378 {
1379         int i;
1380         uint32_t val;
1381         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1382
1383         /* Bind all RX queues to allocated MSIX interrupt */
1384         for (i = 0; i < nb_queue; i++) {
1385                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1386                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1387                         ((base_queue + i + 1) <<
1388                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1389                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1390                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1391
1392                 if (i == nb_queue - 1)
1393                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1394                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1395         }
1396
1397         /* Write first RX queue to Link list register as the head element */
1398         if (vsi->type != I40E_VSI_SRIOV) {
1399                 uint16_t interval =
1400                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1401
1402                 if (msix_vect == I40E_MISC_VEC_ID) {
1403                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1404                                        (base_queue <<
1405                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1406                                        (0x0 <<
1407                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1408                         I40E_WRITE_REG(hw,
1409                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1410                                        interval);
1411                 } else {
1412                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1413                                        (base_queue <<
1414                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417                         I40E_WRITE_REG(hw,
1418                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1419                                                        msix_vect - 1),
1420                                        interval);
1421                 }
1422         } else {
1423                 uint32_t reg;
1424
1425                 if (msix_vect == I40E_MISC_VEC_ID) {
1426                         I40E_WRITE_REG(hw,
1427                                        I40E_VPINT_LNKLST0(vsi->user_param),
1428                                        (base_queue <<
1429                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1430                                        (0x0 <<
1431                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1432                 } else {
1433                         /* num_msix_vectors_vf needs to minus irq0 */
1434                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1435                                 vsi->user_param + (msix_vect - 1);
1436
1437                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1438                                        (base_queue <<
1439                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1440                                        (0x0 <<
1441                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1442                 }
1443         }
1444
1445         I40E_WRITE_FLUSH(hw);
1446 }
1447
1448 void
1449 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1450 {
1451         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1452         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1453         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1454         uint16_t msix_vect = vsi->msix_intr;
1455         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1456         uint16_t queue_idx = 0;
1457         int record = 0;
1458         uint32_t val;
1459         int i;
1460
1461         for (i = 0; i < vsi->nb_qps; i++) {
1462                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1463                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1464         }
1465
1466         /* INTENA flag is not auto-cleared for interrupt */
1467         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1468         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1469                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1470                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1471         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1472
1473         /* VF bind interrupt */
1474         if (vsi->type == I40E_VSI_SRIOV) {
1475                 __vsi_queues_bind_intr(vsi, msix_vect,
1476                                        vsi->base_queue, vsi->nb_qps);
1477                 return;
1478         }
1479
1480         /* PF & VMDq bind interrupt */
1481         if (rte_intr_dp_is_en(intr_handle)) {
1482                 if (vsi->type == I40E_VSI_MAIN) {
1483                         queue_idx = 0;
1484                         record = 1;
1485                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1486                         struct i40e_vsi *main_vsi =
1487                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1488                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1489                         record = 1;
1490                 }
1491         }
1492
1493         for (i = 0; i < vsi->nb_used_qps; i++) {
1494                 if (nb_msix <= 1) {
1495                         if (!rte_intr_allow_others(intr_handle))
1496                                 /* allow to share MISC_VEC_ID */
1497                                 msix_vect = I40E_MISC_VEC_ID;
1498
1499                         /* no enough msix_vect, map all to one */
1500                         __vsi_queues_bind_intr(vsi, msix_vect,
1501                                                vsi->base_queue + i,
1502                                                vsi->nb_used_qps - i);
1503                         for (; !!record && i < vsi->nb_used_qps; i++)
1504                                 intr_handle->intr_vec[queue_idx + i] =
1505                                         msix_vect;
1506                         break;
1507                 }
1508                 /* 1:1 queue/msix_vect mapping */
1509                 __vsi_queues_bind_intr(vsi, msix_vect,
1510                                        vsi->base_queue + i, 1);
1511                 if (!!record)
1512                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1513
1514                 msix_vect++;
1515                 nb_msix--;
1516         }
1517 }
1518
1519 static void
1520 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1521 {
1522         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1523         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1524         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525         uint16_t interval = i40e_calc_itr_interval(\
1526                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1527         uint16_t msix_intr, i;
1528
1529         if (rte_intr_allow_others(intr_handle))
1530                 for (i = 0; i < vsi->nb_msix; i++) {
1531                         msix_intr = vsi->msix_intr + i;
1532                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1533                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1534                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1535                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1536                                 (interval <<
1537                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1538                 }
1539         else
1540                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1541                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1542                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1543                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1544                                (interval <<
1545                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1546
1547         I40E_WRITE_FLUSH(hw);
1548 }
1549
1550 static void
1551 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1552 {
1553         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1554         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1555         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1556         uint16_t msix_intr, i;
1557
1558         if (rte_intr_allow_others(intr_handle))
1559                 for (i = 0; i < vsi->nb_msix; i++) {
1560                         msix_intr = vsi->msix_intr + i;
1561                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1562                                        0);
1563                 }
1564         else
1565                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1566
1567         I40E_WRITE_FLUSH(hw);
1568 }
1569
1570 static inline uint8_t
1571 i40e_parse_link_speeds(uint16_t link_speeds)
1572 {
1573         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1574
1575         if (link_speeds & ETH_LINK_SPEED_40G)
1576                 link_speed |= I40E_LINK_SPEED_40GB;
1577         if (link_speeds & ETH_LINK_SPEED_25G)
1578                 link_speed |= I40E_LINK_SPEED_25GB;
1579         if (link_speeds & ETH_LINK_SPEED_20G)
1580                 link_speed |= I40E_LINK_SPEED_20GB;
1581         if (link_speeds & ETH_LINK_SPEED_10G)
1582                 link_speed |= I40E_LINK_SPEED_10GB;
1583         if (link_speeds & ETH_LINK_SPEED_1G)
1584                 link_speed |= I40E_LINK_SPEED_1GB;
1585         if (link_speeds & ETH_LINK_SPEED_100M)
1586                 link_speed |= I40E_LINK_SPEED_100MB;
1587
1588         return link_speed;
1589 }
1590
1591 static int
1592 i40e_phy_conf_link(struct i40e_hw *hw,
1593                    uint8_t abilities,
1594                    uint8_t force_speed)
1595 {
1596         enum i40e_status_code status;
1597         struct i40e_aq_get_phy_abilities_resp phy_ab;
1598         struct i40e_aq_set_phy_config phy_conf;
1599         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1600                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1601                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1602                         I40E_AQ_PHY_FLAG_LOW_POWER;
1603         const uint8_t advt = I40E_LINK_SPEED_40GB |
1604                         I40E_LINK_SPEED_25GB |
1605                         I40E_LINK_SPEED_10GB |
1606                         I40E_LINK_SPEED_1GB |
1607                         I40E_LINK_SPEED_100MB;
1608         int ret = -ENOTSUP;
1609
1610
1611         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1612                                               NULL);
1613         if (status)
1614                 return ret;
1615
1616         memset(&phy_conf, 0, sizeof(phy_conf));
1617
1618         /* bits 0-2 use the values from get_phy_abilities_resp */
1619         abilities &= ~mask;
1620         abilities |= phy_ab.abilities & mask;
1621
1622         /* update ablities and speed */
1623         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1624                 phy_conf.link_speed = advt;
1625         else
1626                 phy_conf.link_speed = force_speed;
1627
1628         phy_conf.abilities = abilities;
1629
1630         /* use get_phy_abilities_resp value for the rest */
1631         phy_conf.phy_type = phy_ab.phy_type;
1632         phy_conf.eee_capability = phy_ab.eee_capability;
1633         phy_conf.eeer = phy_ab.eeer_val;
1634         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1635
1636         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1637                     phy_ab.abilities, phy_ab.link_speed);
1638         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1639                     phy_conf.abilities, phy_conf.link_speed);
1640
1641         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1642         if (status)
1643                 return ret;
1644
1645         return I40E_SUCCESS;
1646 }
1647
1648 static int
1649 i40e_apply_link_speed(struct rte_eth_dev *dev)
1650 {
1651         uint8_t speed;
1652         uint8_t abilities = 0;
1653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct rte_eth_conf *conf = &dev->data->dev_conf;
1655
1656         speed = i40e_parse_link_speeds(conf->link_speeds);
1657         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1658                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1659         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1660                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1661         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1662
1663         /* Skip changing speed on 40G interfaces, FW does not support */
1664         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1665                 speed =  I40E_LINK_SPEED_UNKNOWN;
1666                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1667         }
1668
1669         return i40e_phy_conf_link(hw, abilities, speed);
1670 }
1671
1672 static int
1673 i40e_dev_start(struct rte_eth_dev *dev)
1674 {
1675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         struct i40e_vsi *main_vsi = pf->main_vsi;
1678         int ret, i;
1679         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1680         uint32_t intr_vector = 0;
1681
1682         hw->adapter_stopped = 0;
1683
1684         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1685                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1686                              dev->data->port_id);
1687                 return -EINVAL;
1688         }
1689
1690         rte_intr_disable(intr_handle);
1691
1692         if ((rte_intr_cap_multiple(intr_handle) ||
1693              !RTE_ETH_DEV_SRIOV(dev).active) &&
1694             dev->data->dev_conf.intr_conf.rxq != 0) {
1695                 intr_vector = dev->data->nb_rx_queues;
1696                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1697                         return -1;
1698         }
1699
1700         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1701                 intr_handle->intr_vec =
1702                         rte_zmalloc("intr_vec",
1703                                     dev->data->nb_rx_queues * sizeof(int),
1704                                     0);
1705                 if (!intr_handle->intr_vec) {
1706                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1707                                      " intr_vec\n", dev->data->nb_rx_queues);
1708                         return -ENOMEM;
1709                 }
1710         }
1711
1712         /* Initialize VSI */
1713         ret = i40e_dev_rxtx_init(pf);
1714         if (ret != I40E_SUCCESS) {
1715                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1716                 goto err_up;
1717         }
1718
1719         /* Map queues with MSIX interrupt */
1720         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1721                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1722         i40e_vsi_queues_bind_intr(main_vsi);
1723         i40e_vsi_enable_queues_intr(main_vsi);
1724
1725         /* Map VMDQ VSI queues with MSIX interrupt */
1726         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1727                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1728                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1729                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1730         }
1731
1732         /* enable FDIR MSIX interrupt */
1733         if (pf->fdir.fdir_vsi) {
1734                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1735                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1736         }
1737
1738         /* Enable all queues which have been configured */
1739         ret = i40e_dev_switch_queues(pf, TRUE);
1740         if (ret != I40E_SUCCESS) {
1741                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1742                 goto err_up;
1743         }
1744
1745         /* Enable receiving broadcast packets */
1746         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1747         if (ret != I40E_SUCCESS)
1748                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1749
1750         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1751                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1752                                                 true, NULL);
1753                 if (ret != I40E_SUCCESS)
1754                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1755         }
1756
1757         /* Apply link configure */
1758         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1759                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1760                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1761                                 ETH_LINK_SPEED_40G)) {
1762                 PMD_DRV_LOG(ERR, "Invalid link setting");
1763                 goto err_up;
1764         }
1765         ret = i40e_apply_link_speed(dev);
1766         if (I40E_SUCCESS != ret) {
1767                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1768                 goto err_up;
1769         }
1770
1771         if (!rte_intr_allow_others(intr_handle)) {
1772                 rte_intr_callback_unregister(intr_handle,
1773                                              i40e_dev_interrupt_handler,
1774                                              (void *)dev);
1775                 /* configure and enable device interrupt */
1776                 i40e_pf_config_irq0(hw, FALSE);
1777                 i40e_pf_enable_irq0(hw);
1778
1779                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1780                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1781                                      " no intr multiplex\n");
1782         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1783                 ret = i40e_aq_set_phy_int_mask(hw,
1784                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1785                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1786                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1787                 if (ret != I40E_SUCCESS)
1788                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1789
1790                 /* Call get_link_info aq commond to enable LSE */
1791                 i40e_dev_link_update(dev, 0);
1792         }
1793
1794         /* enable uio intr after callback register */
1795         rte_intr_enable(intr_handle);
1796
1797         return I40E_SUCCESS;
1798
1799 err_up:
1800         i40e_dev_switch_queues(pf, FALSE);
1801         i40e_dev_clear_queues(dev);
1802
1803         return ret;
1804 }
1805
1806 static void
1807 i40e_dev_stop(struct rte_eth_dev *dev)
1808 {
1809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1810         struct i40e_vsi *main_vsi = pf->main_vsi;
1811         struct i40e_mirror_rule *p_mirror;
1812         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1813         int i;
1814
1815         /* Disable all queues */
1816         i40e_dev_switch_queues(pf, FALSE);
1817
1818         /* un-map queues with interrupt registers */
1819         i40e_vsi_disable_queues_intr(main_vsi);
1820         i40e_vsi_queues_unbind_intr(main_vsi);
1821
1822         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1823                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1824                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1825         }
1826
1827         if (pf->fdir.fdir_vsi) {
1828                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1829                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1830         }
1831         /* Clear all queues and release memory */
1832         i40e_dev_clear_queues(dev);
1833
1834         /* Set link down */
1835         i40e_dev_set_link_down(dev);
1836
1837         /* Remove all mirror rules */
1838         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1839                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1840                 rte_free(p_mirror);
1841         }
1842         pf->nb_mirror_rule = 0;
1843
1844         if (!rte_intr_allow_others(intr_handle))
1845                 /* resume to the default handler */
1846                 rte_intr_callback_register(intr_handle,
1847                                            i40e_dev_interrupt_handler,
1848                                            (void *)dev);
1849
1850         /* Clean datapath event and queue/vec mapping */
1851         rte_intr_efd_disable(intr_handle);
1852         if (intr_handle->intr_vec) {
1853                 rte_free(intr_handle->intr_vec);
1854                 intr_handle->intr_vec = NULL;
1855         }
1856 }
1857
1858 static void
1859 i40e_dev_close(struct rte_eth_dev *dev)
1860 {
1861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1862         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1863         uint32_t reg;
1864         int i;
1865
1866         PMD_INIT_FUNC_TRACE();
1867
1868         i40e_dev_stop(dev);
1869         hw->adapter_stopped = 1;
1870         i40e_dev_free_queues(dev);
1871
1872         /* Disable interrupt */
1873         i40e_pf_disable_irq0(hw);
1874         rte_intr_disable(&(dev->pci_dev->intr_handle));
1875
1876         /* shutdown and destroy the HMC */
1877         i40e_shutdown_lan_hmc(hw);
1878
1879         /* release all the existing VSIs and VEBs */
1880         i40e_fdir_teardown(pf);
1881         i40e_vsi_release(pf->main_vsi);
1882
1883         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1884                 i40e_vsi_release(pf->vmdq[i].vsi);
1885                 pf->vmdq[i].vsi = NULL;
1886         }
1887
1888         rte_free(pf->vmdq);
1889         pf->vmdq = NULL;
1890
1891         /* shutdown the adminq */
1892         i40e_aq_queue_shutdown(hw, true);
1893         i40e_shutdown_adminq(hw);
1894
1895         i40e_res_pool_destroy(&pf->qp_pool);
1896         i40e_res_pool_destroy(&pf->msix_pool);
1897
1898         /* force a PF reset to clean anything leftover */
1899         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1900         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1901                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1902         I40E_WRITE_FLUSH(hw);
1903 }
1904
1905 static void
1906 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1907 {
1908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910         struct i40e_vsi *vsi = pf->main_vsi;
1911         int status;
1912
1913         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1914                                                      true, NULL, true);
1915         if (status != I40E_SUCCESS)
1916                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1917
1918         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1919                                                         TRUE, NULL);
1920         if (status != I40E_SUCCESS)
1921                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1922
1923 }
1924
1925 static void
1926 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1927 {
1928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1929         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct i40e_vsi *vsi = pf->main_vsi;
1931         int status;
1932
1933         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1934                                                      false, NULL, true);
1935         if (status != I40E_SUCCESS)
1936                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1937
1938         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1939                                                         false, NULL);
1940         if (status != I40E_SUCCESS)
1941                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1942 }
1943
1944 static void
1945 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1946 {
1947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         struct i40e_vsi *vsi = pf->main_vsi;
1950         int ret;
1951
1952         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1953         if (ret != I40E_SUCCESS)
1954                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1955 }
1956
1957 static void
1958 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1959 {
1960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1961         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1962         struct i40e_vsi *vsi = pf->main_vsi;
1963         int ret;
1964
1965         if (dev->data->promiscuous == 1)
1966                 return; /* must remain in all_multicast mode */
1967
1968         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1969                                 vsi->seid, FALSE, NULL);
1970         if (ret != I40E_SUCCESS)
1971                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1972 }
1973
1974 /*
1975  * Set device link up.
1976  */
1977 static int
1978 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1979 {
1980         /* re-apply link speed setting */
1981         return i40e_apply_link_speed(dev);
1982 }
1983
1984 /*
1985  * Set device link down.
1986  */
1987 static int
1988 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1989 {
1990         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1991         uint8_t abilities = 0;
1992         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993
1994         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1995                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1996         return i40e_phy_conf_link(hw, abilities, speed);
1997 }
1998
1999 int
2000 i40e_dev_link_update(struct rte_eth_dev *dev,
2001                      int wait_to_complete)
2002 {
2003 #define CHECK_INTERVAL 100  /* 100ms */
2004 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         struct i40e_link_status link_status;
2007         struct rte_eth_link link, old;
2008         int status;
2009         unsigned rep_cnt = MAX_REPEAT_TIME;
2010         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2011
2012         memset(&link, 0, sizeof(link));
2013         memset(&old, 0, sizeof(old));
2014         memset(&link_status, 0, sizeof(link_status));
2015         rte_i40e_dev_atomic_read_link_status(dev, &old);
2016
2017         do {
2018                 /* Get link status information from hardware */
2019                 status = i40e_aq_get_link_info(hw, enable_lse,
2020                                                 &link_status, NULL);
2021                 if (status != I40E_SUCCESS) {
2022                         link.link_speed = ETH_SPEED_NUM_100M;
2023                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2024                         PMD_DRV_LOG(ERR, "Failed to get link info");
2025                         goto out;
2026                 }
2027
2028                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2029                 if (!wait_to_complete)
2030                         break;
2031
2032                 rte_delay_ms(CHECK_INTERVAL);
2033         } while (!link.link_status && rep_cnt--);
2034
2035         if (!link.link_status)
2036                 goto out;
2037
2038         /* i40e uses full duplex only */
2039         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2040
2041         /* Parse the link status */
2042         switch (link_status.link_speed) {
2043         case I40E_LINK_SPEED_100MB:
2044                 link.link_speed = ETH_SPEED_NUM_100M;
2045                 break;
2046         case I40E_LINK_SPEED_1GB:
2047                 link.link_speed = ETH_SPEED_NUM_1G;
2048                 break;
2049         case I40E_LINK_SPEED_10GB:
2050                 link.link_speed = ETH_SPEED_NUM_10G;
2051                 break;
2052         case I40E_LINK_SPEED_20GB:
2053                 link.link_speed = ETH_SPEED_NUM_20G;
2054                 break;
2055         case I40E_LINK_SPEED_25GB:
2056                 link.link_speed = ETH_SPEED_NUM_25G;
2057                 break;
2058         case I40E_LINK_SPEED_40GB:
2059                 link.link_speed = ETH_SPEED_NUM_40G;
2060                 break;
2061         default:
2062                 link.link_speed = ETH_SPEED_NUM_100M;
2063                 break;
2064         }
2065
2066         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2067                         ETH_LINK_SPEED_FIXED);
2068
2069 out:
2070         rte_i40e_dev_atomic_write_link_status(dev, &link);
2071         if (link.link_status == old.link_status)
2072                 return -1;
2073
2074         return 0;
2075 }
2076
2077 /* Get all the statistics of a VSI */
2078 void
2079 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2080 {
2081         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2082         struct i40e_eth_stats *nes = &vsi->eth_stats;
2083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2085
2086         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2087                             vsi->offset_loaded, &oes->rx_bytes,
2088                             &nes->rx_bytes);
2089         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2090                             vsi->offset_loaded, &oes->rx_unicast,
2091                             &nes->rx_unicast);
2092         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2093                             vsi->offset_loaded, &oes->rx_multicast,
2094                             &nes->rx_multicast);
2095         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2096                             vsi->offset_loaded, &oes->rx_broadcast,
2097                             &nes->rx_broadcast);
2098         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2099                             &oes->rx_discards, &nes->rx_discards);
2100         /* GLV_REPC not supported */
2101         /* GLV_RMPC not supported */
2102         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2103                             &oes->rx_unknown_protocol,
2104                             &nes->rx_unknown_protocol);
2105         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2106                             vsi->offset_loaded, &oes->tx_bytes,
2107                             &nes->tx_bytes);
2108         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2109                             vsi->offset_loaded, &oes->tx_unicast,
2110                             &nes->tx_unicast);
2111         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2112                             vsi->offset_loaded, &oes->tx_multicast,
2113                             &nes->tx_multicast);
2114         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2115                             vsi->offset_loaded,  &oes->tx_broadcast,
2116                             &nes->tx_broadcast);
2117         /* GLV_TDPC not supported */
2118         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2119                             &oes->tx_errors, &nes->tx_errors);
2120         vsi->offset_loaded = true;
2121
2122         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2123                     vsi->vsi_id);
2124         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2125         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2126         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2127         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2128         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2129         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2130                     nes->rx_unknown_protocol);
2131         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2132         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2133         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2134         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2135         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2136         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2137         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2138                     vsi->vsi_id);
2139 }
2140
2141 static void
2142 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2143 {
2144         unsigned int i;
2145         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2146         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2147
2148         /* Get statistics of struct i40e_eth_stats */
2149         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2150                             I40E_GLPRT_GORCL(hw->port),
2151                             pf->offset_loaded, &os->eth.rx_bytes,
2152                             &ns->eth.rx_bytes);
2153         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2154                             I40E_GLPRT_UPRCL(hw->port),
2155                             pf->offset_loaded, &os->eth.rx_unicast,
2156                             &ns->eth.rx_unicast);
2157         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2158                             I40E_GLPRT_MPRCL(hw->port),
2159                             pf->offset_loaded, &os->eth.rx_multicast,
2160                             &ns->eth.rx_multicast);
2161         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2162                             I40E_GLPRT_BPRCL(hw->port),
2163                             pf->offset_loaded, &os->eth.rx_broadcast,
2164                             &ns->eth.rx_broadcast);
2165         /* Workaround: CRC size should not be included in byte statistics,
2166          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2167          */
2168         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2169                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2170
2171         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2172                             pf->offset_loaded, &os->eth.rx_discards,
2173                             &ns->eth.rx_discards);
2174         /* GLPRT_REPC not supported */
2175         /* GLPRT_RMPC not supported */
2176         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2177                             pf->offset_loaded,
2178                             &os->eth.rx_unknown_protocol,
2179                             &ns->eth.rx_unknown_protocol);
2180         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2181                             I40E_GLPRT_GOTCL(hw->port),
2182                             pf->offset_loaded, &os->eth.tx_bytes,
2183                             &ns->eth.tx_bytes);
2184         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2185                             I40E_GLPRT_UPTCL(hw->port),
2186                             pf->offset_loaded, &os->eth.tx_unicast,
2187                             &ns->eth.tx_unicast);
2188         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2189                             I40E_GLPRT_MPTCL(hw->port),
2190                             pf->offset_loaded, &os->eth.tx_multicast,
2191                             &ns->eth.tx_multicast);
2192         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2193                             I40E_GLPRT_BPTCL(hw->port),
2194                             pf->offset_loaded, &os->eth.tx_broadcast,
2195                             &ns->eth.tx_broadcast);
2196         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2197                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2198         /* GLPRT_TEPC not supported */
2199
2200         /* additional port specific stats */
2201         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2202                             pf->offset_loaded, &os->tx_dropped_link_down,
2203                             &ns->tx_dropped_link_down);
2204         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2205                             pf->offset_loaded, &os->crc_errors,
2206                             &ns->crc_errors);
2207         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2208                             pf->offset_loaded, &os->illegal_bytes,
2209                             &ns->illegal_bytes);
2210         /* GLPRT_ERRBC not supported */
2211         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2212                             pf->offset_loaded, &os->mac_local_faults,
2213                             &ns->mac_local_faults);
2214         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2215                             pf->offset_loaded, &os->mac_remote_faults,
2216                             &ns->mac_remote_faults);
2217         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2218                             pf->offset_loaded, &os->rx_length_errors,
2219                             &ns->rx_length_errors);
2220         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2221                             pf->offset_loaded, &os->link_xon_rx,
2222                             &ns->link_xon_rx);
2223         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2224                             pf->offset_loaded, &os->link_xoff_rx,
2225                             &ns->link_xoff_rx);
2226         for (i = 0; i < 8; i++) {
2227                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2228                                     pf->offset_loaded,
2229                                     &os->priority_xon_rx[i],
2230                                     &ns->priority_xon_rx[i]);
2231                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2232                                     pf->offset_loaded,
2233                                     &os->priority_xoff_rx[i],
2234                                     &ns->priority_xoff_rx[i]);
2235         }
2236         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2237                             pf->offset_loaded, &os->link_xon_tx,
2238                             &ns->link_xon_tx);
2239         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2240                             pf->offset_loaded, &os->link_xoff_tx,
2241                             &ns->link_xoff_tx);
2242         for (i = 0; i < 8; i++) {
2243                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2244                                     pf->offset_loaded,
2245                                     &os->priority_xon_tx[i],
2246                                     &ns->priority_xon_tx[i]);
2247                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2248                                     pf->offset_loaded,
2249                                     &os->priority_xoff_tx[i],
2250                                     &ns->priority_xoff_tx[i]);
2251                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2252                                     pf->offset_loaded,
2253                                     &os->priority_xon_2_xoff[i],
2254                                     &ns->priority_xon_2_xoff[i]);
2255         }
2256         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2257                             I40E_GLPRT_PRC64L(hw->port),
2258                             pf->offset_loaded, &os->rx_size_64,
2259                             &ns->rx_size_64);
2260         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2261                             I40E_GLPRT_PRC127L(hw->port),
2262                             pf->offset_loaded, &os->rx_size_127,
2263                             &ns->rx_size_127);
2264         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2265                             I40E_GLPRT_PRC255L(hw->port),
2266                             pf->offset_loaded, &os->rx_size_255,
2267                             &ns->rx_size_255);
2268         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2269                             I40E_GLPRT_PRC511L(hw->port),
2270                             pf->offset_loaded, &os->rx_size_511,
2271                             &ns->rx_size_511);
2272         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2273                             I40E_GLPRT_PRC1023L(hw->port),
2274                             pf->offset_loaded, &os->rx_size_1023,
2275                             &ns->rx_size_1023);
2276         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2277                             I40E_GLPRT_PRC1522L(hw->port),
2278                             pf->offset_loaded, &os->rx_size_1522,
2279                             &ns->rx_size_1522);
2280         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2281                             I40E_GLPRT_PRC9522L(hw->port),
2282                             pf->offset_loaded, &os->rx_size_big,
2283                             &ns->rx_size_big);
2284         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2285                             pf->offset_loaded, &os->rx_undersize,
2286                             &ns->rx_undersize);
2287         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2288                             pf->offset_loaded, &os->rx_fragments,
2289                             &ns->rx_fragments);
2290         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2291                             pf->offset_loaded, &os->rx_oversize,
2292                             &ns->rx_oversize);
2293         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2294                             pf->offset_loaded, &os->rx_jabber,
2295                             &ns->rx_jabber);
2296         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2297                             I40E_GLPRT_PTC64L(hw->port),
2298                             pf->offset_loaded, &os->tx_size_64,
2299                             &ns->tx_size_64);
2300         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2301                             I40E_GLPRT_PTC127L(hw->port),
2302                             pf->offset_loaded, &os->tx_size_127,
2303                             &ns->tx_size_127);
2304         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2305                             I40E_GLPRT_PTC255L(hw->port),
2306                             pf->offset_loaded, &os->tx_size_255,
2307                             &ns->tx_size_255);
2308         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2309                             I40E_GLPRT_PTC511L(hw->port),
2310                             pf->offset_loaded, &os->tx_size_511,
2311                             &ns->tx_size_511);
2312         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2313                             I40E_GLPRT_PTC1023L(hw->port),
2314                             pf->offset_loaded, &os->tx_size_1023,
2315                             &ns->tx_size_1023);
2316         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2317                             I40E_GLPRT_PTC1522L(hw->port),
2318                             pf->offset_loaded, &os->tx_size_1522,
2319                             &ns->tx_size_1522);
2320         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2321                             I40E_GLPRT_PTC9522L(hw->port),
2322                             pf->offset_loaded, &os->tx_size_big,
2323                             &ns->tx_size_big);
2324         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2325                            pf->offset_loaded,
2326                            &os->fd_sb_match, &ns->fd_sb_match);
2327         /* GLPRT_MSPDC not supported */
2328         /* GLPRT_XEC not supported */
2329
2330         pf->offset_loaded = true;
2331
2332         if (pf->main_vsi)
2333                 i40e_update_vsi_stats(pf->main_vsi);
2334 }
2335
2336 /* Get all statistics of a port */
2337 static void
2338 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2339 {
2340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2343         unsigned i;
2344
2345         /* call read registers - updates values, now write them to struct */
2346         i40e_read_stats_registers(pf, hw);
2347
2348         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2349                         pf->main_vsi->eth_stats.rx_multicast +
2350                         pf->main_vsi->eth_stats.rx_broadcast -
2351                         pf->main_vsi->eth_stats.rx_discards;
2352         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2353                         pf->main_vsi->eth_stats.tx_multicast +
2354                         pf->main_vsi->eth_stats.tx_broadcast;
2355         stats->ibytes   = ns->eth.rx_bytes;
2356         stats->obytes   = ns->eth.tx_bytes;
2357         stats->oerrors  = ns->eth.tx_errors +
2358                         pf->main_vsi->eth_stats.tx_errors;
2359
2360         /* Rx Errors */
2361         stats->imissed  = ns->eth.rx_discards +
2362                         pf->main_vsi->eth_stats.rx_discards;
2363         stats->ierrors  = ns->crc_errors +
2364                         ns->rx_length_errors + ns->rx_undersize +
2365                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2366
2367         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2368         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2369         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2370         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2371         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2372         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2373         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2374                     ns->eth.rx_unknown_protocol);
2375         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2376         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2377         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2378         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2379         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2380         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2381
2382         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2383                     ns->tx_dropped_link_down);
2384         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2385         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2386                     ns->illegal_bytes);
2387         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2388         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2389                     ns->mac_local_faults);
2390         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2391                     ns->mac_remote_faults);
2392         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2393                     ns->rx_length_errors);
2394         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2395         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2396         for (i = 0; i < 8; i++) {
2397                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2398                                 i, ns->priority_xon_rx[i]);
2399                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2400                                 i, ns->priority_xoff_rx[i]);
2401         }
2402         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2403         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2404         for (i = 0; i < 8; i++) {
2405                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2406                                 i, ns->priority_xon_tx[i]);
2407                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2408                                 i, ns->priority_xoff_tx[i]);
2409                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2410                                 i, ns->priority_xon_2_xoff[i]);
2411         }
2412         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2413         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2414         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2415         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2416         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2417         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2418         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2419         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2420         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2421         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2422         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2423         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2424         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2425         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2426         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2427         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2428         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2429         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2430         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2431                         ns->mac_short_packet_dropped);
2432         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2433                     ns->checksum_error);
2434         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2435         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2436 }
2437
2438 /* Reset the statistics */
2439 static void
2440 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2441 {
2442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2444
2445         /* Mark PF and VSI stats to update the offset, aka "reset" */
2446         pf->offset_loaded = false;
2447         if (pf->main_vsi)
2448                 pf->main_vsi->offset_loaded = false;
2449
2450         /* read the stats, reading current register values into offset */
2451         i40e_read_stats_registers(pf, hw);
2452 }
2453
2454 static uint32_t
2455 i40e_xstats_calc_num(void)
2456 {
2457         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2458                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2459                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2460 }
2461
2462 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2463                                      struct rte_eth_xstat_name *xstats_names,
2464                                      __rte_unused unsigned limit)
2465 {
2466         unsigned count = 0;
2467         unsigned i, prio;
2468
2469         if (xstats_names == NULL)
2470                 return i40e_xstats_calc_num();
2471
2472         /* Note: limit checked in rte_eth_xstats_names() */
2473
2474         /* Get stats from i40e_eth_stats struct */
2475         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2476                 snprintf(xstats_names[count].name,
2477                          sizeof(xstats_names[count].name),
2478                          "%s", rte_i40e_stats_strings[i].name);
2479                 count++;
2480         }
2481
2482         /* Get individiual stats from i40e_hw_port struct */
2483         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2484                 snprintf(xstats_names[count].name,
2485                         sizeof(xstats_names[count].name),
2486                          "%s", rte_i40e_hw_port_strings[i].name);
2487                 count++;
2488         }
2489
2490         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2491                 for (prio = 0; prio < 8; prio++) {
2492                         snprintf(xstats_names[count].name,
2493                                  sizeof(xstats_names[count].name),
2494                                  "rx_priority%u_%s", prio,
2495                                  rte_i40e_rxq_prio_strings[i].name);
2496                         count++;
2497                 }
2498         }
2499
2500         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2501                 for (prio = 0; prio < 8; prio++) {
2502                         snprintf(xstats_names[count].name,
2503                                  sizeof(xstats_names[count].name),
2504                                  "tx_priority%u_%s", prio,
2505                                  rte_i40e_txq_prio_strings[i].name);
2506                         count++;
2507                 }
2508         }
2509         return count;
2510 }
2511
2512 static int
2513 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2514                     unsigned n)
2515 {
2516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2517         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2518         unsigned i, count, prio;
2519         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2520
2521         count = i40e_xstats_calc_num();
2522         if (n < count)
2523                 return count;
2524
2525         i40e_read_stats_registers(pf, hw);
2526
2527         if (xstats == NULL)
2528                 return 0;
2529
2530         count = 0;
2531
2532         /* Get stats from i40e_eth_stats struct */
2533         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2534                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2535                         rte_i40e_stats_strings[i].offset);
2536                 count++;
2537         }
2538
2539         /* Get individiual stats from i40e_hw_port struct */
2540         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2541                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2542                         rte_i40e_hw_port_strings[i].offset);
2543                 count++;
2544         }
2545
2546         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2547                 for (prio = 0; prio < 8; prio++) {
2548                         xstats[count].value =
2549                                 *(uint64_t *)(((char *)hw_stats) +
2550                                 rte_i40e_rxq_prio_strings[i].offset +
2551                                 (sizeof(uint64_t) * prio));
2552                         count++;
2553                 }
2554         }
2555
2556         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2557                 for (prio = 0; prio < 8; prio++) {
2558                         xstats[count].value =
2559                                 *(uint64_t *)(((char *)hw_stats) +
2560                                 rte_i40e_txq_prio_strings[i].offset +
2561                                 (sizeof(uint64_t) * prio));
2562                         count++;
2563                 }
2564         }
2565
2566         return count;
2567 }
2568
2569 static int
2570 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2571                                  __rte_unused uint16_t queue_id,
2572                                  __rte_unused uint8_t stat_idx,
2573                                  __rte_unused uint8_t is_rx)
2574 {
2575         PMD_INIT_FUNC_TRACE();
2576
2577         return -ENOSYS;
2578 }
2579
2580 static void
2581 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2582 {
2583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         struct i40e_vsi *vsi = pf->main_vsi;
2586
2587         dev_info->max_rx_queues = vsi->nb_qps;
2588         dev_info->max_tx_queues = vsi->nb_qps;
2589         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2590         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2591         dev_info->max_mac_addrs = vsi->max_macaddrs;
2592         dev_info->max_vfs = dev->pci_dev->max_vfs;
2593         dev_info->rx_offload_capa =
2594                 DEV_RX_OFFLOAD_VLAN_STRIP |
2595                 DEV_RX_OFFLOAD_QINQ_STRIP |
2596                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2597                 DEV_RX_OFFLOAD_UDP_CKSUM |
2598                 DEV_RX_OFFLOAD_TCP_CKSUM;
2599         dev_info->tx_offload_capa =
2600                 DEV_TX_OFFLOAD_VLAN_INSERT |
2601                 DEV_TX_OFFLOAD_QINQ_INSERT |
2602                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2603                 DEV_TX_OFFLOAD_UDP_CKSUM |
2604                 DEV_TX_OFFLOAD_TCP_CKSUM |
2605                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2606                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2607                 DEV_TX_OFFLOAD_TCP_TSO |
2608                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2609                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2610                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2611                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2612         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2613                                                 sizeof(uint32_t);
2614         dev_info->reta_size = pf->hash_lut_size;
2615         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2616
2617         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2618                 .rx_thresh = {
2619                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2620                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2621                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2622                 },
2623                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2624                 .rx_drop_en = 0,
2625         };
2626
2627         dev_info->default_txconf = (struct rte_eth_txconf) {
2628                 .tx_thresh = {
2629                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2630                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2631                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2632                 },
2633                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2634                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2635                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2636                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2637         };
2638
2639         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2640                 .nb_max = I40E_MAX_RING_DESC,
2641                 .nb_min = I40E_MIN_RING_DESC,
2642                 .nb_align = I40E_ALIGN_RING_DESC,
2643         };
2644
2645         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2646                 .nb_max = I40E_MAX_RING_DESC,
2647                 .nb_min = I40E_MIN_RING_DESC,
2648                 .nb_align = I40E_ALIGN_RING_DESC,
2649         };
2650
2651         if (pf->flags & I40E_FLAG_VMDQ) {
2652                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2653                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2654                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2655                                                 pf->max_nb_vmdq_vsi;
2656                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2657                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2658                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2659         }
2660
2661         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2662                 /* For XL710 */
2663                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2664         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2665                 /* For XXV710 */
2666                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2667         else
2668                 /* For X710 */
2669                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2670 }
2671
2672 static int
2673 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2674 {
2675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2676         struct i40e_vsi *vsi = pf->main_vsi;
2677         PMD_INIT_FUNC_TRACE();
2678
2679         if (on)
2680                 return i40e_vsi_add_vlan(vsi, vlan_id);
2681         else
2682                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2683 }
2684
2685 static int
2686 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2687                    enum rte_vlan_type vlan_type,
2688                    uint16_t tpid)
2689 {
2690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2691         uint64_t reg_r = 0, reg_w = 0;
2692         uint16_t reg_id = 0;
2693         int ret = 0;
2694         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2695
2696         switch (vlan_type) {
2697         case ETH_VLAN_TYPE_OUTER:
2698                 if (qinq)
2699                         reg_id = 2;
2700                 else
2701                         reg_id = 3;
2702                 break;
2703         case ETH_VLAN_TYPE_INNER:
2704                 if (qinq)
2705                         reg_id = 3;
2706                 else {
2707                         ret = -EINVAL;
2708                         PMD_DRV_LOG(ERR,
2709                                 "Unsupported vlan type in single vlan.\n");
2710                         return ret;
2711                 }
2712                 break;
2713         default:
2714                 ret = -EINVAL;
2715                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2716                 return ret;
2717         }
2718         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2719                                           &reg_r, NULL);
2720         if (ret != I40E_SUCCESS) {
2721                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2722                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2723                 ret = -EIO;
2724                 return ret;
2725         }
2726         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2727                     "0x%08"PRIx64"", reg_id, reg_r);
2728
2729         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2730         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2731         if (reg_r == reg_w) {
2732                 ret = 0;
2733                 PMD_DRV_LOG(DEBUG, "No need to write");
2734                 return ret;
2735         }
2736
2737         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2738                                            reg_w, NULL);
2739         if (ret != I40E_SUCCESS) {
2740                 ret = -EIO;
2741                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2742                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2743                 return ret;
2744         }
2745         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2746                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2747
2748         return ret;
2749 }
2750
2751 static void
2752 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2753 {
2754         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2755         struct i40e_vsi *vsi = pf->main_vsi;
2756
2757         if (mask & ETH_VLAN_FILTER_MASK) {
2758                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2759                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2760                 else
2761                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2762         }
2763
2764         if (mask & ETH_VLAN_STRIP_MASK) {
2765                 /* Enable or disable VLAN stripping */
2766                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2767                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2768                 else
2769                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2770         }
2771
2772         if (mask & ETH_VLAN_EXTEND_MASK) {
2773                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2774                         i40e_vsi_config_double_vlan(vsi, TRUE);
2775                         /* Set global registers with default ether type value */
2776                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2777                                            ETHER_TYPE_VLAN);
2778                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2779                                            ETHER_TYPE_VLAN);
2780                 }
2781                 else
2782                         i40e_vsi_config_double_vlan(vsi, FALSE);
2783         }
2784 }
2785
2786 static void
2787 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2788                           __rte_unused uint16_t queue,
2789                           __rte_unused int on)
2790 {
2791         PMD_INIT_FUNC_TRACE();
2792 }
2793
2794 static int
2795 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2796 {
2797         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2798         struct i40e_vsi *vsi = pf->main_vsi;
2799         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2800         struct i40e_vsi_vlan_pvid_info info;
2801
2802         memset(&info, 0, sizeof(info));
2803         info.on = on;
2804         if (info.on)
2805                 info.config.pvid = pvid;
2806         else {
2807                 info.config.reject.tagged =
2808                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2809                 info.config.reject.untagged =
2810                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2811         }
2812
2813         return i40e_vsi_vlan_pvid_set(vsi, &info);
2814 }
2815
2816 static int
2817 i40e_dev_led_on(struct rte_eth_dev *dev)
2818 {
2819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         uint32_t mode = i40e_led_get(hw);
2821
2822         if (mode == 0)
2823                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2824
2825         return 0;
2826 }
2827
2828 static int
2829 i40e_dev_led_off(struct rte_eth_dev *dev)
2830 {
2831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         uint32_t mode = i40e_led_get(hw);
2833
2834         if (mode != 0)
2835                 i40e_led_set(hw, 0, false);
2836
2837         return 0;
2838 }
2839
2840 static int
2841 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2842 {
2843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2845
2846         fc_conf->pause_time = pf->fc_conf.pause_time;
2847         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2848         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2849
2850          /* Return current mode according to actual setting*/
2851         switch (hw->fc.current_mode) {
2852         case I40E_FC_FULL:
2853                 fc_conf->mode = RTE_FC_FULL;
2854                 break;
2855         case I40E_FC_TX_PAUSE:
2856                 fc_conf->mode = RTE_FC_TX_PAUSE;
2857                 break;
2858         case I40E_FC_RX_PAUSE:
2859                 fc_conf->mode = RTE_FC_RX_PAUSE;
2860                 break;
2861         case I40E_FC_NONE:
2862         default:
2863                 fc_conf->mode = RTE_FC_NONE;
2864         };
2865
2866         return 0;
2867 }
2868
2869 static int
2870 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2871 {
2872         uint32_t mflcn_reg, fctrl_reg, reg;
2873         uint32_t max_high_water;
2874         uint8_t i, aq_failure;
2875         int err;
2876         struct i40e_hw *hw;
2877         struct i40e_pf *pf;
2878         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2879                 [RTE_FC_NONE] = I40E_FC_NONE,
2880                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2881                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2882                 [RTE_FC_FULL] = I40E_FC_FULL
2883         };
2884
2885         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2886
2887         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2888         if ((fc_conf->high_water > max_high_water) ||
2889                         (fc_conf->high_water < fc_conf->low_water)) {
2890                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2891                         "High_water must <= %d.", max_high_water);
2892                 return -EINVAL;
2893         }
2894
2895         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2897         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2898
2899         pf->fc_conf.pause_time = fc_conf->pause_time;
2900         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2901         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2902
2903         PMD_INIT_FUNC_TRACE();
2904
2905         /* All the link flow control related enable/disable register
2906          * configuration is handle by the F/W
2907          */
2908         err = i40e_set_fc(hw, &aq_failure, true);
2909         if (err < 0)
2910                 return -ENOSYS;
2911
2912         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2913                 /* Configure flow control refresh threshold,
2914                  * the value for stat_tx_pause_refresh_timer[8]
2915                  * is used for global pause operation.
2916                  */
2917
2918                 I40E_WRITE_REG(hw,
2919                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2920                                pf->fc_conf.pause_time);
2921
2922                 /* configure the timer value included in transmitted pause
2923                  * frame,
2924                  * the value for stat_tx_pause_quanta[8] is used for global
2925                  * pause operation
2926                  */
2927                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2928                                pf->fc_conf.pause_time);
2929
2930                 fctrl_reg = I40E_READ_REG(hw,
2931                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2932
2933                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2934                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2935                 else
2936                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2937
2938                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2939                                fctrl_reg);
2940         } else {
2941                 /* Configure pause time (2 TCs per register) */
2942                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2943                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2944                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2945
2946                 /* Configure flow control refresh threshold value */
2947                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2948                                pf->fc_conf.pause_time / 2);
2949
2950                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2951
2952                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2953                  *depending on configuration
2954                  */
2955                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2956                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2957                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2958                 } else {
2959                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2960                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2961                 }
2962
2963                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2964         }
2965
2966         /* config the water marker both based on the packets and bytes */
2967         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2968                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2969                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2970         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2971                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2972                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2973         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2974                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2975                        << I40E_KILOSHIFT);
2976         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2977                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2978                        << I40E_KILOSHIFT);
2979
2980         I40E_WRITE_FLUSH(hw);
2981
2982         return 0;
2983 }
2984
2985 static int
2986 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2987                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2988 {
2989         PMD_INIT_FUNC_TRACE();
2990
2991         return -ENOSYS;
2992 }
2993
2994 /* Add a MAC address, and update filters */
2995 static void
2996 i40e_macaddr_add(struct rte_eth_dev *dev,
2997                  struct ether_addr *mac_addr,
2998                  __rte_unused uint32_t index,
2999                  uint32_t pool)
3000 {
3001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3002         struct i40e_mac_filter_info mac_filter;
3003         struct i40e_vsi *vsi;
3004         int ret;
3005
3006         /* If VMDQ not enabled or configured, return */
3007         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3008                           !pf->nb_cfg_vmdq_vsi)) {
3009                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3010                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3011                         pool);
3012                 return;
3013         }
3014
3015         if (pool > pf->nb_cfg_vmdq_vsi) {
3016                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3017                                 pool, pf->nb_cfg_vmdq_vsi);
3018                 return;
3019         }
3020
3021         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3022         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3023                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3024         else
3025                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3026
3027         if (pool == 0)
3028                 vsi = pf->main_vsi;
3029         else
3030                 vsi = pf->vmdq[pool - 1].vsi;
3031
3032         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3033         if (ret != I40E_SUCCESS) {
3034                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3035                 return;
3036         }
3037 }
3038
3039 /* Remove a MAC address, and update filters */
3040 static void
3041 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3042 {
3043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3044         struct i40e_vsi *vsi;
3045         struct rte_eth_dev_data *data = dev->data;
3046         struct ether_addr *macaddr;
3047         int ret;
3048         uint32_t i;
3049         uint64_t pool_sel;
3050
3051         macaddr = &(data->mac_addrs[index]);
3052
3053         pool_sel = dev->data->mac_pool_sel[index];
3054
3055         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3056                 if (pool_sel & (1ULL << i)) {
3057                         if (i == 0)
3058                                 vsi = pf->main_vsi;
3059                         else {
3060                                 /* No VMDQ pool enabled or configured */
3061                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3062                                         (i > pf->nb_cfg_vmdq_vsi)) {
3063                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3064                                                         "/configured");
3065                                         return;
3066                                 }
3067                                 vsi = pf->vmdq[i - 1].vsi;
3068                         }
3069                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3070
3071                         if (ret) {
3072                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3073                                 return;
3074                         }
3075                 }
3076         }
3077 }
3078
3079 /* Set perfect match or hash match of MAC and VLAN for a VF */
3080 static int
3081 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3082                  struct rte_eth_mac_filter *filter,
3083                  bool add)
3084 {
3085         struct i40e_hw *hw;
3086         struct i40e_mac_filter_info mac_filter;
3087         struct ether_addr old_mac;
3088         struct ether_addr *new_mac;
3089         struct i40e_pf_vf *vf = NULL;
3090         uint16_t vf_id;
3091         int ret;
3092
3093         if (pf == NULL) {
3094                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3095                 return -EINVAL;
3096         }
3097         hw = I40E_PF_TO_HW(pf);
3098
3099         if (filter == NULL) {
3100                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3101                 return -EINVAL;
3102         }
3103
3104         new_mac = &filter->mac_addr;
3105
3106         if (is_zero_ether_addr(new_mac)) {
3107                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3108                 return -EINVAL;
3109         }
3110
3111         vf_id = filter->dst_id;
3112
3113         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3114                 PMD_DRV_LOG(ERR, "Invalid argument.");
3115                 return -EINVAL;
3116         }
3117         vf = &pf->vfs[vf_id];
3118
3119         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3120                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3121                 return -EINVAL;
3122         }
3123
3124         if (add) {
3125                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3126                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3127                                 ETHER_ADDR_LEN);
3128                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3129                                  ETHER_ADDR_LEN);
3130
3131                 mac_filter.filter_type = filter->filter_type;
3132                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3133                 if (ret != I40E_SUCCESS) {
3134                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3135                         return -1;
3136                 }
3137                 ether_addr_copy(new_mac, &pf->dev_addr);
3138         } else {
3139                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3140                                 ETHER_ADDR_LEN);
3141                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3142                 if (ret != I40E_SUCCESS) {
3143                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3144                         return -1;
3145                 }
3146
3147                 /* Clear device address as it has been removed */
3148                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3149                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3150         }
3151
3152         return 0;
3153 }
3154
3155 /* MAC filter handle */
3156 static int
3157 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3158                 void *arg)
3159 {
3160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3161         struct rte_eth_mac_filter *filter;
3162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3163         int ret = I40E_NOT_SUPPORTED;
3164
3165         filter = (struct rte_eth_mac_filter *)(arg);
3166
3167         switch (filter_op) {
3168         case RTE_ETH_FILTER_NOP:
3169                 ret = I40E_SUCCESS;
3170                 break;
3171         case RTE_ETH_FILTER_ADD:
3172                 i40e_pf_disable_irq0(hw);
3173                 if (filter->is_vf)
3174                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3175                 i40e_pf_enable_irq0(hw);
3176                 break;
3177         case RTE_ETH_FILTER_DELETE:
3178                 i40e_pf_disable_irq0(hw);
3179                 if (filter->is_vf)
3180                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3181                 i40e_pf_enable_irq0(hw);
3182                 break;
3183         default:
3184                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3185                 ret = I40E_ERR_PARAM;
3186                 break;
3187         }
3188
3189         return ret;
3190 }
3191
3192 static int
3193 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3194 {
3195         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3196         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3197         int ret;
3198
3199         if (!lut)
3200                 return -EINVAL;
3201
3202         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3203                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3204                                           lut, lut_size);
3205                 if (ret) {
3206                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3207                         return ret;
3208                 }
3209         } else {
3210                 uint32_t *lut_dw = (uint32_t *)lut;
3211                 uint16_t i, lut_size_dw = lut_size / 4;
3212
3213                 for (i = 0; i < lut_size_dw; i++)
3214                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3215         }
3216
3217         return 0;
3218 }
3219
3220 static int
3221 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3222 {
3223         struct i40e_pf *pf;
3224         struct i40e_hw *hw;
3225         int ret;
3226
3227         if (!vsi || !lut)
3228                 return -EINVAL;
3229
3230         pf = I40E_VSI_TO_PF(vsi);
3231         hw = I40E_VSI_TO_HW(vsi);
3232
3233         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3234                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3235                                           lut, lut_size);
3236                 if (ret) {
3237                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3238                         return ret;
3239                 }
3240         } else {
3241                 uint32_t *lut_dw = (uint32_t *)lut;
3242                 uint16_t i, lut_size_dw = lut_size / 4;
3243
3244                 for (i = 0; i < lut_size_dw; i++)
3245                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3246                 I40E_WRITE_FLUSH(hw);
3247         }
3248
3249         return 0;
3250 }
3251
3252 static int
3253 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3254                          struct rte_eth_rss_reta_entry64 *reta_conf,
3255                          uint16_t reta_size)
3256 {
3257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3258         uint16_t i, lut_size = pf->hash_lut_size;
3259         uint16_t idx, shift;
3260         uint8_t *lut;
3261         int ret;
3262
3263         if (reta_size != lut_size ||
3264                 reta_size > ETH_RSS_RETA_SIZE_512) {
3265                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3266                         "(%d) doesn't match the number hardware can supported "
3267                                         "(%d)\n", reta_size, lut_size);
3268                 return -EINVAL;
3269         }
3270
3271         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3272         if (!lut) {
3273                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3274                 return -ENOMEM;
3275         }
3276         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3277         if (ret)
3278                 goto out;
3279         for (i = 0; i < reta_size; i++) {
3280                 idx = i / RTE_RETA_GROUP_SIZE;
3281                 shift = i % RTE_RETA_GROUP_SIZE;
3282                 if (reta_conf[idx].mask & (1ULL << shift))
3283                         lut[i] = reta_conf[idx].reta[shift];
3284         }
3285         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3286
3287 out:
3288         rte_free(lut);
3289
3290         return ret;
3291 }
3292
3293 static int
3294 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3295                         struct rte_eth_rss_reta_entry64 *reta_conf,
3296                         uint16_t reta_size)
3297 {
3298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3299         uint16_t i, lut_size = pf->hash_lut_size;
3300         uint16_t idx, shift;
3301         uint8_t *lut;
3302         int ret;
3303
3304         if (reta_size != lut_size ||
3305                 reta_size > ETH_RSS_RETA_SIZE_512) {
3306                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3307                         "(%d) doesn't match the number hardware can supported "
3308                                         "(%d)\n", reta_size, lut_size);
3309                 return -EINVAL;
3310         }
3311
3312         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3313         if (!lut) {
3314                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3315                 return -ENOMEM;
3316         }
3317
3318         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3319         if (ret)
3320                 goto out;
3321         for (i = 0; i < reta_size; i++) {
3322                 idx = i / RTE_RETA_GROUP_SIZE;
3323                 shift = i % RTE_RETA_GROUP_SIZE;
3324                 if (reta_conf[idx].mask & (1ULL << shift))
3325                         reta_conf[idx].reta[shift] = lut[i];
3326         }
3327
3328 out:
3329         rte_free(lut);
3330
3331         return ret;
3332 }
3333
3334 /**
3335  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3336  * @hw:   pointer to the HW structure
3337  * @mem:  pointer to mem struct to fill out
3338  * @size: size of memory requested
3339  * @alignment: what to align the allocation to
3340  **/
3341 enum i40e_status_code
3342 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3343                         struct i40e_dma_mem *mem,
3344                         u64 size,
3345                         u32 alignment)
3346 {
3347         const struct rte_memzone *mz = NULL;
3348         char z_name[RTE_MEMZONE_NAMESIZE];
3349
3350         if (!mem)
3351                 return I40E_ERR_PARAM;
3352
3353         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3354         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3355                                          alignment, RTE_PGSIZE_2M);
3356         if (!mz)
3357                 return I40E_ERR_NO_MEMORY;
3358
3359         mem->size = size;
3360         mem->va = mz->addr;
3361         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3362         mem->zone = (const void *)mz;
3363         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3364                     "%"PRIu64, mz->name, mem->pa);
3365
3366         return I40E_SUCCESS;
3367 }
3368
3369 /**
3370  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3371  * @hw:   pointer to the HW structure
3372  * @mem:  ptr to mem struct to free
3373  **/
3374 enum i40e_status_code
3375 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3376                     struct i40e_dma_mem *mem)
3377 {
3378         if (!mem)
3379                 return I40E_ERR_PARAM;
3380
3381         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3382                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3383                     mem->pa);
3384         rte_memzone_free((const struct rte_memzone *)mem->zone);
3385         mem->zone = NULL;
3386         mem->va = NULL;
3387         mem->pa = (u64)0;
3388
3389         return I40E_SUCCESS;
3390 }
3391
3392 /**
3393  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3394  * @hw:   pointer to the HW structure
3395  * @mem:  pointer to mem struct to fill out
3396  * @size: size of memory requested
3397  **/
3398 enum i40e_status_code
3399 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3400                          struct i40e_virt_mem *mem,
3401                          u32 size)
3402 {
3403         if (!mem)
3404                 return I40E_ERR_PARAM;
3405
3406         mem->size = size;
3407         mem->va = rte_zmalloc("i40e", size, 0);
3408
3409         if (mem->va)
3410                 return I40E_SUCCESS;
3411         else
3412                 return I40E_ERR_NO_MEMORY;
3413 }
3414
3415 /**
3416  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3417  * @hw:   pointer to the HW structure
3418  * @mem:  pointer to mem struct to free
3419  **/
3420 enum i40e_status_code
3421 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3422                      struct i40e_virt_mem *mem)
3423 {
3424         if (!mem)
3425                 return I40E_ERR_PARAM;
3426
3427         rte_free(mem->va);
3428         mem->va = NULL;
3429
3430         return I40E_SUCCESS;
3431 }
3432
3433 void
3434 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3435 {
3436         rte_spinlock_init(&sp->spinlock);
3437 }
3438
3439 void
3440 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3441 {
3442         rte_spinlock_lock(&sp->spinlock);
3443 }
3444
3445 void
3446 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3447 {
3448         rte_spinlock_unlock(&sp->spinlock);
3449 }
3450
3451 void
3452 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3453 {
3454         return;
3455 }
3456
3457 /**
3458  * Get the hardware capabilities, which will be parsed
3459  * and saved into struct i40e_hw.
3460  */
3461 static int
3462 i40e_get_cap(struct i40e_hw *hw)
3463 {
3464         struct i40e_aqc_list_capabilities_element_resp *buf;
3465         uint16_t len, size = 0;
3466         int ret;
3467
3468         /* Calculate a huge enough buff for saving response data temporarily */
3469         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3470                                                 I40E_MAX_CAP_ELE_NUM;
3471         buf = rte_zmalloc("i40e", len, 0);
3472         if (!buf) {
3473                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3474                 return I40E_ERR_NO_MEMORY;
3475         }
3476
3477         /* Get, parse the capabilities and save it to hw */
3478         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3479                         i40e_aqc_opc_list_func_capabilities, NULL);
3480         if (ret != I40E_SUCCESS)
3481                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3482
3483         /* Free the temporary buffer after being used */
3484         rte_free(buf);
3485
3486         return ret;
3487 }
3488
3489 static int
3490 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3491 {
3492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3493         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3494         uint16_t qp_count = 0, vsi_count = 0;
3495
3496         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3497                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3498                 return -EINVAL;
3499         }
3500         /* Add the parameter init for LFC */
3501         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3502         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3503         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3504
3505         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3506         pf->max_num_vsi = hw->func_caps.num_vsis;
3507         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3508         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3509         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3510
3511         /* FDir queue/VSI allocation */
3512         pf->fdir_qp_offset = 0;
3513         if (hw->func_caps.fd) {
3514                 pf->flags |= I40E_FLAG_FDIR;
3515                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3516         } else {
3517                 pf->fdir_nb_qps = 0;
3518         }
3519         qp_count += pf->fdir_nb_qps;
3520         vsi_count += 1;
3521
3522         /* LAN queue/VSI allocation */
3523         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3524         if (!hw->func_caps.rss) {
3525                 pf->lan_nb_qps = 1;
3526         } else {
3527                 pf->flags |= I40E_FLAG_RSS;
3528                 if (hw->mac.type == I40E_MAC_X722)
3529                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3530                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3531         }
3532         qp_count += pf->lan_nb_qps;
3533         vsi_count += 1;
3534
3535         /* VF queue/VSI allocation */
3536         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3537         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3538                 pf->flags |= I40E_FLAG_SRIOV;
3539                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3540                 pf->vf_num = dev->pci_dev->max_vfs;
3541                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3542                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3543                             pf->vf_nb_qps * pf->vf_num);
3544         } else {
3545                 pf->vf_nb_qps = 0;
3546                 pf->vf_num = 0;
3547         }
3548         qp_count += pf->vf_nb_qps * pf->vf_num;
3549         vsi_count += pf->vf_num;
3550
3551         /* VMDq queue/VSI allocation */
3552         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3553         pf->vmdq_nb_qps = 0;
3554         pf->max_nb_vmdq_vsi = 0;
3555         if (hw->func_caps.vmdq) {
3556                 if (qp_count < hw->func_caps.num_tx_qp &&
3557                         vsi_count < hw->func_caps.num_vsis) {
3558                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3559                                 qp_count) / pf->vmdq_nb_qp_max;
3560
3561                         /* Limit the maximum number of VMDq vsi to the maximum
3562                          * ethdev can support
3563                          */
3564                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3565                                 hw->func_caps.num_vsis - vsi_count);
3566                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3567                                 ETH_64_POOLS);
3568                         if (pf->max_nb_vmdq_vsi) {
3569                                 pf->flags |= I40E_FLAG_VMDQ;
3570                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3571                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3572                                             "per VMDQ VSI, in total %u queues",
3573                                             pf->max_nb_vmdq_vsi,
3574                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3575                                             pf->max_nb_vmdq_vsi);
3576                         } else {
3577                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3578                                             "VMDq");
3579                         }
3580                 } else {
3581                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3582                 }
3583         }
3584         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3585         vsi_count += pf->max_nb_vmdq_vsi;
3586
3587         if (hw->func_caps.dcb)
3588                 pf->flags |= I40E_FLAG_DCB;
3589
3590         if (qp_count > hw->func_caps.num_tx_qp) {
3591                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3592                             "the hardware maximum %u", qp_count,
3593                             hw->func_caps.num_tx_qp);
3594                 return -EINVAL;
3595         }
3596         if (vsi_count > hw->func_caps.num_vsis) {
3597                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3598                             "the hardware maximum %u", vsi_count,
3599                             hw->func_caps.num_vsis);
3600                 return -EINVAL;
3601         }
3602
3603         return 0;
3604 }
3605
3606 static int
3607 i40e_pf_get_switch_config(struct i40e_pf *pf)
3608 {
3609         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3610         struct i40e_aqc_get_switch_config_resp *switch_config;
3611         struct i40e_aqc_switch_config_element_resp *element;
3612         uint16_t start_seid = 0, num_reported;
3613         int ret;
3614
3615         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3616                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3617         if (!switch_config) {
3618                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3619                 return -ENOMEM;
3620         }
3621
3622         /* Get the switch configurations */
3623         ret = i40e_aq_get_switch_config(hw, switch_config,
3624                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3625         if (ret != I40E_SUCCESS) {
3626                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3627                 goto fail;
3628         }
3629         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3630         if (num_reported != 1) { /* The number should be 1 */
3631                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3632                 goto fail;
3633         }
3634
3635         /* Parse the switch configuration elements */
3636         element = &(switch_config->element[0]);
3637         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3638                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3639                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3640         } else
3641                 PMD_DRV_LOG(INFO, "Unknown element type");
3642
3643 fail:
3644         rte_free(switch_config);
3645
3646         return ret;
3647 }
3648
3649 static int
3650 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3651                         uint32_t num)
3652 {
3653         struct pool_entry *entry;
3654
3655         if (pool == NULL || num == 0)
3656                 return -EINVAL;
3657
3658         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3659         if (entry == NULL) {
3660                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3661                 return -ENOMEM;
3662         }
3663
3664         /* queue heap initialize */
3665         pool->num_free = num;
3666         pool->num_alloc = 0;
3667         pool->base = base;
3668         LIST_INIT(&pool->alloc_list);
3669         LIST_INIT(&pool->free_list);
3670
3671         /* Initialize element  */
3672         entry->base = 0;
3673         entry->len = num;
3674
3675         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3676         return 0;
3677 }
3678
3679 static void
3680 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3681 {
3682         struct pool_entry *entry, *next_entry;
3683
3684         if (pool == NULL)
3685                 return;
3686
3687         for (entry = LIST_FIRST(&pool->alloc_list);
3688                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3689                         entry = next_entry) {
3690                 LIST_REMOVE(entry, next);
3691                 rte_free(entry);
3692         }
3693
3694         for (entry = LIST_FIRST(&pool->free_list);
3695                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3696                         entry = next_entry) {
3697                 LIST_REMOVE(entry, next);
3698                 rte_free(entry);
3699         }
3700
3701         pool->num_free = 0;
3702         pool->num_alloc = 0;
3703         pool->base = 0;
3704         LIST_INIT(&pool->alloc_list);
3705         LIST_INIT(&pool->free_list);
3706 }
3707
3708 static int
3709 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3710                        uint32_t base)
3711 {
3712         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3713         uint32_t pool_offset;
3714         int insert;
3715
3716         if (pool == NULL) {
3717                 PMD_DRV_LOG(ERR, "Invalid parameter");
3718                 return -EINVAL;
3719         }
3720
3721         pool_offset = base - pool->base;
3722         /* Lookup in alloc list */
3723         LIST_FOREACH(entry, &pool->alloc_list, next) {
3724                 if (entry->base == pool_offset) {
3725                         valid_entry = entry;
3726                         LIST_REMOVE(entry, next);
3727                         break;
3728                 }
3729         }
3730
3731         /* Not find, return */
3732         if (valid_entry == NULL) {
3733                 PMD_DRV_LOG(ERR, "Failed to find entry");
3734                 return -EINVAL;
3735         }
3736
3737         /**
3738          * Found it, move it to free list  and try to merge.
3739          * In order to make merge easier, always sort it by qbase.
3740          * Find adjacent prev and last entries.
3741          */
3742         prev = next = NULL;
3743         LIST_FOREACH(entry, &pool->free_list, next) {
3744                 if (entry->base > valid_entry->base) {
3745                         next = entry;
3746                         break;
3747                 }
3748                 prev = entry;
3749         }
3750
3751         insert = 0;
3752         /* Try to merge with next one*/
3753         if (next != NULL) {
3754                 /* Merge with next one */
3755                 if (valid_entry->base + valid_entry->len == next->base) {
3756                         next->base = valid_entry->base;
3757                         next->len += valid_entry->len;
3758                         rte_free(valid_entry);
3759                         valid_entry = next;
3760                         insert = 1;
3761                 }
3762         }
3763
3764         if (prev != NULL) {
3765                 /* Merge with previous one */
3766                 if (prev->base + prev->len == valid_entry->base) {
3767                         prev->len += valid_entry->len;
3768                         /* If it merge with next one, remove next node */
3769                         if (insert == 1) {
3770                                 LIST_REMOVE(valid_entry, next);
3771                                 rte_free(valid_entry);
3772                         } else {
3773                                 rte_free(valid_entry);
3774                                 insert = 1;
3775                         }
3776                 }
3777         }
3778
3779         /* Not find any entry to merge, insert */
3780         if (insert == 0) {
3781                 if (prev != NULL)
3782                         LIST_INSERT_AFTER(prev, valid_entry, next);
3783                 else if (next != NULL)
3784                         LIST_INSERT_BEFORE(next, valid_entry, next);
3785                 else /* It's empty list, insert to head */
3786                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3787         }
3788
3789         pool->num_free += valid_entry->len;
3790         pool->num_alloc -= valid_entry->len;
3791
3792         return 0;
3793 }
3794
3795 static int
3796 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3797                        uint16_t num)
3798 {
3799         struct pool_entry *entry, *valid_entry;
3800
3801         if (pool == NULL || num == 0) {
3802                 PMD_DRV_LOG(ERR, "Invalid parameter");
3803                 return -EINVAL;
3804         }
3805
3806         if (pool->num_free < num) {
3807                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3808                             num, pool->num_free);
3809                 return -ENOMEM;
3810         }
3811
3812         valid_entry = NULL;
3813         /* Lookup  in free list and find most fit one */
3814         LIST_FOREACH(entry, &pool->free_list, next) {
3815                 if (entry->len >= num) {
3816                         /* Find best one */
3817                         if (entry->len == num) {
3818                                 valid_entry = entry;
3819                                 break;
3820                         }
3821                         if (valid_entry == NULL || valid_entry->len > entry->len)
3822                                 valid_entry = entry;
3823                 }
3824         }
3825
3826         /* Not find one to satisfy the request, return */
3827         if (valid_entry == NULL) {
3828                 PMD_DRV_LOG(ERR, "No valid entry found");
3829                 return -ENOMEM;
3830         }
3831         /**
3832          * The entry have equal queue number as requested,
3833          * remove it from alloc_list.
3834          */
3835         if (valid_entry->len == num) {
3836                 LIST_REMOVE(valid_entry, next);
3837         } else {
3838                 /**
3839                  * The entry have more numbers than requested,
3840                  * create a new entry for alloc_list and minus its
3841                  * queue base and number in free_list.
3842                  */
3843                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3844                 if (entry == NULL) {
3845                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3846                                     "resource pool");
3847                         return -ENOMEM;
3848                 }
3849                 entry->base = valid_entry->base;
3850                 entry->len = num;
3851                 valid_entry->base += num;
3852                 valid_entry->len -= num;
3853                 valid_entry = entry;
3854         }
3855
3856         /* Insert it into alloc list, not sorted */
3857         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3858
3859         pool->num_free -= valid_entry->len;
3860         pool->num_alloc += valid_entry->len;
3861
3862         return valid_entry->base + pool->base;
3863 }
3864
3865 /**
3866  * bitmap_is_subset - Check whether src2 is subset of src1
3867  **/
3868 static inline int
3869 bitmap_is_subset(uint8_t src1, uint8_t src2)
3870 {
3871         return !((src1 ^ src2) & src2);
3872 }
3873
3874 static enum i40e_status_code
3875 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3876 {
3877         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3878
3879         /* If DCB is not supported, only default TC is supported */
3880         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3881                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3882                 return I40E_NOT_SUPPORTED;
3883         }
3884
3885         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3886                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3887                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3888                             enabled_tcmap);
3889                 return I40E_NOT_SUPPORTED;
3890         }
3891         return I40E_SUCCESS;
3892 }
3893
3894 int
3895 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3896                                 struct i40e_vsi_vlan_pvid_info *info)
3897 {
3898         struct i40e_hw *hw;
3899         struct i40e_vsi_context ctxt;
3900         uint8_t vlan_flags = 0;
3901         int ret;
3902
3903         if (vsi == NULL || info == NULL) {
3904                 PMD_DRV_LOG(ERR, "invalid parameters");
3905                 return I40E_ERR_PARAM;
3906         }
3907
3908         if (info->on) {
3909                 vsi->info.pvid = info->config.pvid;
3910                 /**
3911                  * If insert pvid is enabled, only tagged pkts are
3912                  * allowed to be sent out.
3913                  */
3914                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3915                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3916         } else {
3917                 vsi->info.pvid = 0;
3918                 if (info->config.reject.tagged == 0)
3919                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3920
3921                 if (info->config.reject.untagged == 0)
3922                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3923         }
3924         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3925                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3926         vsi->info.port_vlan_flags |= vlan_flags;
3927         vsi->info.valid_sections =
3928                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3929         memset(&ctxt, 0, sizeof(ctxt));
3930         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3931         ctxt.seid = vsi->seid;
3932
3933         hw = I40E_VSI_TO_HW(vsi);
3934         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3935         if (ret != I40E_SUCCESS)
3936                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3937
3938         return ret;
3939 }
3940
3941 static int
3942 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3943 {
3944         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3945         int i, ret;
3946         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3947
3948         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3949         if (ret != I40E_SUCCESS)
3950                 return ret;
3951
3952         if (!vsi->seid) {
3953                 PMD_DRV_LOG(ERR, "seid not valid");
3954                 return -EINVAL;
3955         }
3956
3957         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3958         tc_bw_data.tc_valid_bits = enabled_tcmap;
3959         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3960                 tc_bw_data.tc_bw_credits[i] =
3961                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3962
3963         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3964         if (ret != I40E_SUCCESS) {
3965                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3966                 return ret;
3967         }
3968
3969         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3970                                         sizeof(vsi->info.qs_handle));
3971         return I40E_SUCCESS;
3972 }
3973
3974 static enum i40e_status_code
3975 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3976                                  struct i40e_aqc_vsi_properties_data *info,
3977                                  uint8_t enabled_tcmap)
3978 {
3979         enum i40e_status_code ret;
3980         int i, total_tc = 0;
3981         uint16_t qpnum_per_tc, bsf, qp_idx;
3982
3983         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3984         if (ret != I40E_SUCCESS)
3985                 return ret;
3986
3987         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3988                 if (enabled_tcmap & (1 << i))
3989                         total_tc++;
3990         vsi->enabled_tc = enabled_tcmap;
3991
3992         /* Number of queues per enabled TC */
3993         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3994         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3995         bsf = rte_bsf32(qpnum_per_tc);
3996
3997         /* Adjust the queue number to actual queues that can be applied */
3998         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3999                 vsi->nb_qps = qpnum_per_tc * total_tc;
4000
4001         /**
4002          * Configure TC and queue mapping parameters, for enabled TC,
4003          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4004          * default queue will serve it.
4005          */
4006         qp_idx = 0;
4007         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4008                 if (vsi->enabled_tc & (1 << i)) {
4009                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4010                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4011                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4012                         qp_idx += qpnum_per_tc;
4013                 } else
4014                         info->tc_mapping[i] = 0;
4015         }
4016
4017         /* Associate queue number with VSI */
4018         if (vsi->type == I40E_VSI_SRIOV) {
4019                 info->mapping_flags |=
4020                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4021                 for (i = 0; i < vsi->nb_qps; i++)
4022                         info->queue_mapping[i] =
4023                                 rte_cpu_to_le_16(vsi->base_queue + i);
4024         } else {
4025                 info->mapping_flags |=
4026                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4027                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4028         }
4029         info->valid_sections |=
4030                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4031
4032         return I40E_SUCCESS;
4033 }
4034
4035 static int
4036 i40e_veb_release(struct i40e_veb *veb)
4037 {
4038         struct i40e_vsi *vsi;
4039         struct i40e_hw *hw;
4040
4041         if (veb == NULL)
4042                 return -EINVAL;
4043
4044         if (!TAILQ_EMPTY(&veb->head)) {
4045                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4046                 return -EACCES;
4047         }
4048         /* associate_vsi field is NULL for floating VEB */
4049         if (veb->associate_vsi != NULL) {
4050                 vsi = veb->associate_vsi;
4051                 hw = I40E_VSI_TO_HW(vsi);
4052
4053                 vsi->uplink_seid = veb->uplink_seid;
4054                 vsi->veb = NULL;
4055         } else {
4056                 veb->associate_pf->main_vsi->floating_veb = NULL;
4057                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4058         }
4059
4060         i40e_aq_delete_element(hw, veb->seid, NULL);
4061         rte_free(veb);
4062         return I40E_SUCCESS;
4063 }
4064
4065 /* Setup a veb */
4066 static struct i40e_veb *
4067 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4068 {
4069         struct i40e_veb *veb;
4070         int ret;
4071         struct i40e_hw *hw;
4072
4073         if (pf == NULL) {
4074                 PMD_DRV_LOG(ERR,
4075                             "veb setup failed, associated PF shouldn't null");
4076                 return NULL;
4077         }
4078         hw = I40E_PF_TO_HW(pf);
4079
4080         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4081         if (!veb) {
4082                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4083                 goto fail;
4084         }
4085
4086         veb->associate_vsi = vsi;
4087         veb->associate_pf = pf;
4088         TAILQ_INIT(&veb->head);
4089         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4090
4091         /* create floating veb if vsi is NULL */
4092         if (vsi != NULL) {
4093                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4094                                       I40E_DEFAULT_TCMAP, false,
4095                                       &veb->seid, false, NULL);
4096         } else {
4097                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4098                                       true, &veb->seid, false, NULL);
4099         }
4100
4101         if (ret != I40E_SUCCESS) {
4102                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4103                             hw->aq.asq_last_status);
4104                 goto fail;
4105         }
4106
4107         /* get statistics index */
4108         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4109                                 &veb->stats_idx, NULL, NULL, NULL);
4110         if (ret != I40E_SUCCESS) {
4111                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4112                             hw->aq.asq_last_status);
4113                 goto fail;
4114         }
4115         /* Get VEB bandwidth, to be implemented */
4116         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4117         if (vsi)
4118                 vsi->uplink_seid = veb->seid;
4119
4120         return veb;
4121 fail:
4122         rte_free(veb);
4123         return NULL;
4124 }
4125
4126 int
4127 i40e_vsi_release(struct i40e_vsi *vsi)
4128 {
4129         struct i40e_pf *pf;
4130         struct i40e_hw *hw;
4131         struct i40e_vsi_list *vsi_list;
4132         void *temp;
4133         int ret;
4134         struct i40e_mac_filter *f;
4135         uint16_t user_param;
4136
4137         if (!vsi)
4138                 return I40E_SUCCESS;
4139
4140         user_param = vsi->user_param;
4141
4142         pf = I40E_VSI_TO_PF(vsi);
4143         hw = I40E_VSI_TO_HW(vsi);
4144
4145         /* VSI has child to attach, release child first */
4146         if (vsi->veb) {
4147                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4148                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4149                                 return -1;
4150                 }
4151                 i40e_veb_release(vsi->veb);
4152         }
4153
4154         if (vsi->floating_veb) {
4155                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4156                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4157                                 return -1;
4158                 }
4159         }
4160
4161         /* Remove all macvlan filters of the VSI */
4162         i40e_vsi_remove_all_macvlan_filter(vsi);
4163         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4164                 rte_free(f);
4165
4166         if (vsi->type != I40E_VSI_MAIN &&
4167             ((vsi->type != I40E_VSI_SRIOV) ||
4168             !pf->floating_veb_list[user_param])) {
4169                 /* Remove vsi from parent's sibling list */
4170                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4171                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4172                         return I40E_ERR_PARAM;
4173                 }
4174                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4175                                 &vsi->sib_vsi_list, list);
4176
4177                 /* Remove all switch element of the VSI */
4178                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4179                 if (ret != I40E_SUCCESS)
4180                         PMD_DRV_LOG(ERR, "Failed to delete element");
4181         }
4182
4183         if ((vsi->type == I40E_VSI_SRIOV) &&
4184             pf->floating_veb_list[user_param]) {
4185                 /* Remove vsi from parent's sibling list */
4186                 if (vsi->parent_vsi == NULL ||
4187                     vsi->parent_vsi->floating_veb == NULL) {
4188                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4189                         return I40E_ERR_PARAM;
4190                 }
4191                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4192                              &vsi->sib_vsi_list, list);
4193
4194                 /* Remove all switch element of the VSI */
4195                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4196                 if (ret != I40E_SUCCESS)
4197                         PMD_DRV_LOG(ERR, "Failed to delete element");
4198         }
4199
4200         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4201
4202         if (vsi->type != I40E_VSI_SRIOV)
4203                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4204         rte_free(vsi);
4205
4206         return I40E_SUCCESS;
4207 }
4208
4209 static int
4210 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4211 {
4212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4213         struct i40e_aqc_remove_macvlan_element_data def_filter;
4214         struct i40e_mac_filter_info filter;
4215         int ret;
4216
4217         if (vsi->type != I40E_VSI_MAIN)
4218                 return I40E_ERR_CONFIG;
4219         memset(&def_filter, 0, sizeof(def_filter));
4220         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4221                                         ETH_ADDR_LEN);
4222         def_filter.vlan_tag = 0;
4223         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4224                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4225         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4226         if (ret != I40E_SUCCESS) {
4227                 struct i40e_mac_filter *f;
4228                 struct ether_addr *mac;
4229
4230                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4231                             "macvlan filter");
4232                 /* It needs to add the permanent mac into mac list */
4233                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4234                 if (f == NULL) {
4235                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4236                         return I40E_ERR_NO_MEMORY;
4237                 }
4238                 mac = &f->mac_info.mac_addr;
4239                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4240                                 ETH_ADDR_LEN);
4241                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4242                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4243                 vsi->mac_num++;
4244
4245                 return ret;
4246         }
4247         (void)rte_memcpy(&filter.mac_addr,
4248                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4249         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4250         return i40e_vsi_add_mac(vsi, &filter);
4251 }
4252
4253 /*
4254  * i40e_vsi_get_bw_config - Query VSI BW Information
4255  * @vsi: the VSI to be queried
4256  *
4257  * Returns 0 on success, negative value on failure
4258  */
4259 static enum i40e_status_code
4260 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4261 {
4262         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4263         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4264         struct i40e_hw *hw = &vsi->adapter->hw;
4265         i40e_status ret;
4266         int i;
4267         uint32_t bw_max;
4268
4269         memset(&bw_config, 0, sizeof(bw_config));
4270         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4271         if (ret != I40E_SUCCESS) {
4272                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4273                             hw->aq.asq_last_status);
4274                 return ret;
4275         }
4276
4277         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4278         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4279                                         &ets_sla_config, NULL);
4280         if (ret != I40E_SUCCESS) {
4281                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4282                             "configuration %u", hw->aq.asq_last_status);
4283                 return ret;
4284         }
4285
4286         /* store and print out BW info */
4287         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4288         vsi->bw_info.bw_max = bw_config.max_bw;
4289         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4290         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4291         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4292                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4293                      I40E_16_BIT_WIDTH);
4294         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4295                 vsi->bw_info.bw_ets_share_credits[i] =
4296                                 ets_sla_config.share_credits[i];
4297                 vsi->bw_info.bw_ets_credits[i] =
4298                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4299                 /* 4 bits per TC, 4th bit is reserved */
4300                 vsi->bw_info.bw_ets_max[i] =
4301                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4302                                   RTE_LEN2MASK(3, uint8_t));
4303                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4304                             vsi->bw_info.bw_ets_share_credits[i]);
4305                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4306                             vsi->bw_info.bw_ets_credits[i]);
4307                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4308                             vsi->bw_info.bw_ets_max[i]);
4309         }
4310
4311         return I40E_SUCCESS;
4312 }
4313
4314 /* i40e_enable_pf_lb
4315  * @pf: pointer to the pf structure
4316  *
4317  * allow loopback on pf
4318  */
4319 static inline void
4320 i40e_enable_pf_lb(struct i40e_pf *pf)
4321 {
4322         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4323         struct i40e_vsi_context ctxt;
4324         int ret;
4325
4326         /* Use the FW API if FW >= v5.0 */
4327         if (hw->aq.fw_maj_ver < 5) {
4328                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4329                 return;
4330         }
4331
4332         memset(&ctxt, 0, sizeof(ctxt));
4333         ctxt.seid = pf->main_vsi_seid;
4334         ctxt.pf_num = hw->pf_id;
4335         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4336         if (ret) {
4337                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4338                             ret, hw->aq.asq_last_status);
4339                 return;
4340         }
4341         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4342         ctxt.info.valid_sections =
4343                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4344         ctxt.info.switch_id |=
4345                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4346
4347         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4348         if (ret)
4349                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4350                             hw->aq.asq_last_status);
4351 }
4352
4353 /* Setup a VSI */
4354 struct i40e_vsi *
4355 i40e_vsi_setup(struct i40e_pf *pf,
4356                enum i40e_vsi_type type,
4357                struct i40e_vsi *uplink_vsi,
4358                uint16_t user_param)
4359 {
4360         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4361         struct i40e_vsi *vsi;
4362         struct i40e_mac_filter_info filter;
4363         int ret;
4364         struct i40e_vsi_context ctxt;
4365         struct ether_addr broadcast =
4366                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4367
4368         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4369             uplink_vsi == NULL) {
4370                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4371                             "VSI link shouldn't be NULL");
4372                 return NULL;
4373         }
4374
4375         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4376                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4377                             "uplink VSI should be NULL");
4378                 return NULL;
4379         }
4380
4381         /* two situations
4382          * 1.type is not MAIN and uplink vsi is not NULL
4383          * If uplink vsi didn't setup VEB, create one first under veb field
4384          * 2.type is SRIOV and the uplink is NULL
4385          * If floating VEB is NULL, create one veb under floating veb field
4386          */
4387
4388         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4389             uplink_vsi->veb == NULL) {
4390                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4391
4392                 if (uplink_vsi->veb == NULL) {
4393                         PMD_DRV_LOG(ERR, "VEB setup failed");
4394                         return NULL;
4395                 }
4396                 /* set ALLOWLOOPBACk on pf, when veb is created */
4397                 i40e_enable_pf_lb(pf);
4398         }
4399
4400         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4401             pf->main_vsi->floating_veb == NULL) {
4402                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4403
4404                 if (pf->main_vsi->floating_veb == NULL) {
4405                         PMD_DRV_LOG(ERR, "VEB setup failed");
4406                         return NULL;
4407                 }
4408         }
4409
4410         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4411         if (!vsi) {
4412                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4413                 return NULL;
4414         }
4415         TAILQ_INIT(&vsi->mac_list);
4416         vsi->type = type;
4417         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4418         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4419         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4420         vsi->user_param = user_param;
4421         /* Allocate queues */
4422         switch (vsi->type) {
4423         case I40E_VSI_MAIN  :
4424                 vsi->nb_qps = pf->lan_nb_qps;
4425                 break;
4426         case I40E_VSI_SRIOV :
4427                 vsi->nb_qps = pf->vf_nb_qps;
4428                 break;
4429         case I40E_VSI_VMDQ2:
4430                 vsi->nb_qps = pf->vmdq_nb_qps;
4431                 break;
4432         case I40E_VSI_FDIR:
4433                 vsi->nb_qps = pf->fdir_nb_qps;
4434                 break;
4435         default:
4436                 goto fail_mem;
4437         }
4438         /*
4439          * The filter status descriptor is reported in rx queue 0,
4440          * while the tx queue for fdir filter programming has no
4441          * such constraints, can be non-zero queues.
4442          * To simplify it, choose FDIR vsi use queue 0 pair.
4443          * To make sure it will use queue 0 pair, queue allocation
4444          * need be done before this function is called
4445          */
4446         if (type != I40E_VSI_FDIR) {
4447                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4448                         if (ret < 0) {
4449                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4450                                                 vsi->seid, ret);
4451                                 goto fail_mem;
4452                         }
4453                         vsi->base_queue = ret;
4454         } else
4455                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4456
4457         /* VF has MSIX interrupt in VF range, don't allocate here */
4458         if (type == I40E_VSI_MAIN) {
4459                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4460                                           RTE_MIN(vsi->nb_qps,
4461                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4462                 if (ret < 0) {
4463                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4464                                     vsi->seid, ret);
4465                         goto fail_queue_alloc;
4466                 }
4467                 vsi->msix_intr = ret;
4468                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4469         } else if (type != I40E_VSI_SRIOV) {
4470                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4471                 if (ret < 0) {
4472                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4473                         goto fail_queue_alloc;
4474                 }
4475                 vsi->msix_intr = ret;
4476                 vsi->nb_msix = 1;
4477         } else {
4478                 vsi->msix_intr = 0;
4479                 vsi->nb_msix = 0;
4480         }
4481
4482         /* Add VSI */
4483         if (type == I40E_VSI_MAIN) {
4484                 /* For main VSI, no need to add since it's default one */
4485                 vsi->uplink_seid = pf->mac_seid;
4486                 vsi->seid = pf->main_vsi_seid;
4487                 /* Bind queues with specific MSIX interrupt */
4488                 /**
4489                  * Needs 2 interrupt at least, one for misc cause which will
4490                  * enabled from OS side, Another for queues binding the
4491                  * interrupt from device side only.
4492                  */
4493
4494                 /* Get default VSI parameters from hardware */
4495                 memset(&ctxt, 0, sizeof(ctxt));
4496                 ctxt.seid = vsi->seid;
4497                 ctxt.pf_num = hw->pf_id;
4498                 ctxt.uplink_seid = vsi->uplink_seid;
4499                 ctxt.vf_num = 0;
4500                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4501                 if (ret != I40E_SUCCESS) {
4502                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4503                         goto fail_msix_alloc;
4504                 }
4505                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4506                         sizeof(struct i40e_aqc_vsi_properties_data));
4507                 vsi->vsi_id = ctxt.vsi_number;
4508                 vsi->info.valid_sections = 0;
4509
4510                 /* Configure tc, enabled TC0 only */
4511                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4512                         I40E_SUCCESS) {
4513                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4514                         goto fail_msix_alloc;
4515                 }
4516
4517                 /* TC, queue mapping */
4518                 memset(&ctxt, 0, sizeof(ctxt));
4519                 vsi->info.valid_sections |=
4520                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4521                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4522                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4523                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4524                         sizeof(struct i40e_aqc_vsi_properties_data));
4525                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4526                                                 I40E_DEFAULT_TCMAP);
4527                 if (ret != I40E_SUCCESS) {
4528                         PMD_DRV_LOG(ERR, "Failed to configure "
4529                                     "TC queue mapping");
4530                         goto fail_msix_alloc;
4531                 }
4532                 ctxt.seid = vsi->seid;
4533                 ctxt.pf_num = hw->pf_id;
4534                 ctxt.uplink_seid = vsi->uplink_seid;
4535                 ctxt.vf_num = 0;
4536
4537                 /* Update VSI parameters */
4538                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4539                 if (ret != I40E_SUCCESS) {
4540                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4541                         goto fail_msix_alloc;
4542                 }
4543
4544                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4545                                                 sizeof(vsi->info.tc_mapping));
4546                 (void)rte_memcpy(&vsi->info.queue_mapping,
4547                                 &ctxt.info.queue_mapping,
4548                         sizeof(vsi->info.queue_mapping));
4549                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4550                 vsi->info.valid_sections = 0;
4551
4552                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4553                                 ETH_ADDR_LEN);
4554
4555                 /**
4556                  * Updating default filter settings are necessary to prevent
4557                  * reception of tagged packets.
4558                  * Some old firmware configurations load a default macvlan
4559                  * filter which accepts both tagged and untagged packets.
4560                  * The updating is to use a normal filter instead if needed.
4561                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4562                  * The firmware with correct configurations load the default
4563                  * macvlan filter which is expected and cannot be removed.
4564                  */
4565                 i40e_update_default_filter_setting(vsi);
4566                 i40e_config_qinq(hw, vsi);
4567         } else if (type == I40E_VSI_SRIOV) {
4568                 memset(&ctxt, 0, sizeof(ctxt));
4569                 /**
4570                  * For other VSI, the uplink_seid equals to uplink VSI's
4571                  * uplink_seid since they share same VEB
4572                  */
4573                 if (uplink_vsi == NULL)
4574                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4575                 else
4576                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4577                 ctxt.pf_num = hw->pf_id;
4578                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4579                 ctxt.uplink_seid = vsi->uplink_seid;
4580                 ctxt.connection_type = 0x1;
4581                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4582
4583                 /* Use the VEB configuration if FW >= v5.0 */
4584                 if (hw->aq.fw_maj_ver >= 5) {
4585                         /* Configure switch ID */
4586                         ctxt.info.valid_sections |=
4587                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4588                         ctxt.info.switch_id =
4589                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4590                 }
4591
4592                 /* Configure port/vlan */
4593                 ctxt.info.valid_sections |=
4594                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4595                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4596                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4597                                                 I40E_DEFAULT_TCMAP);
4598                 if (ret != I40E_SUCCESS) {
4599                         PMD_DRV_LOG(ERR, "Failed to configure "
4600                                     "TC queue mapping");
4601                         goto fail_msix_alloc;
4602                 }
4603                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4604                 ctxt.info.valid_sections |=
4605                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4606                 /**
4607                  * Since VSI is not created yet, only configure parameter,
4608                  * will add vsi below.
4609                  */
4610
4611                 i40e_config_qinq(hw, vsi);
4612         } else if (type == I40E_VSI_VMDQ2) {
4613                 memset(&ctxt, 0, sizeof(ctxt));
4614                 /*
4615                  * For other VSI, the uplink_seid equals to uplink VSI's
4616                  * uplink_seid since they share same VEB
4617                  */
4618                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4619                 ctxt.pf_num = hw->pf_id;
4620                 ctxt.vf_num = 0;
4621                 ctxt.uplink_seid = vsi->uplink_seid;
4622                 ctxt.connection_type = 0x1;
4623                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4624
4625                 ctxt.info.valid_sections |=
4626                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4627                 /* user_param carries flag to enable loop back */
4628                 if (user_param) {
4629                         ctxt.info.switch_id =
4630                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4631                         ctxt.info.switch_id |=
4632                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4633                 }
4634
4635                 /* Configure port/vlan */
4636                 ctxt.info.valid_sections |=
4637                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4638                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4639                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4640                                                 I40E_DEFAULT_TCMAP);
4641                 if (ret != I40E_SUCCESS) {
4642                         PMD_DRV_LOG(ERR, "Failed to configure "
4643                                         "TC queue mapping");
4644                         goto fail_msix_alloc;
4645                 }
4646                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4647                 ctxt.info.valid_sections |=
4648                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4649         } else if (type == I40E_VSI_FDIR) {
4650                 memset(&ctxt, 0, sizeof(ctxt));
4651                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4652                 ctxt.pf_num = hw->pf_id;
4653                 ctxt.vf_num = 0;
4654                 ctxt.uplink_seid = vsi->uplink_seid;
4655                 ctxt.connection_type = 0x1;     /* regular data port */
4656                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4657                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4658                                                 I40E_DEFAULT_TCMAP);
4659                 if (ret != I40E_SUCCESS) {
4660                         PMD_DRV_LOG(ERR, "Failed to configure "
4661                                         "TC queue mapping.");
4662                         goto fail_msix_alloc;
4663                 }
4664                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4665                 ctxt.info.valid_sections |=
4666                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4667         } else {
4668                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4669                 goto fail_msix_alloc;
4670         }
4671
4672         if (vsi->type != I40E_VSI_MAIN) {
4673                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4674                 if (ret != I40E_SUCCESS) {
4675                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4676                                     hw->aq.asq_last_status);
4677                         goto fail_msix_alloc;
4678                 }
4679                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4680                 vsi->info.valid_sections = 0;
4681                 vsi->seid = ctxt.seid;
4682                 vsi->vsi_id = ctxt.vsi_number;
4683                 vsi->sib_vsi_list.vsi = vsi;
4684                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4685                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4686                                           &vsi->sib_vsi_list, list);
4687                 } else {
4688                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4689                                           &vsi->sib_vsi_list, list);
4690                 }
4691         }
4692
4693         /* MAC/VLAN configuration */
4694         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4695         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4696
4697         ret = i40e_vsi_add_mac(vsi, &filter);
4698         if (ret != I40E_SUCCESS) {
4699                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4700                 goto fail_msix_alloc;
4701         }
4702
4703         /* Get VSI BW information */
4704         i40e_vsi_get_bw_config(vsi);
4705         return vsi;
4706 fail_msix_alloc:
4707         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4708 fail_queue_alloc:
4709         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4710 fail_mem:
4711         rte_free(vsi);
4712         return NULL;
4713 }
4714
4715 /* Configure vlan filter on or off */
4716 int
4717 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4718 {
4719         int i, num;
4720         struct i40e_mac_filter *f;
4721         void *temp;
4722         struct i40e_mac_filter_info *mac_filter;
4723         enum rte_mac_filter_type desired_filter;
4724         int ret = I40E_SUCCESS;
4725
4726         if (on) {
4727                 /* Filter to match MAC and VLAN */
4728                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4729         } else {
4730                 /* Filter to match only MAC */
4731                 desired_filter = RTE_MAC_PERFECT_MATCH;
4732         }
4733
4734         num = vsi->mac_num;
4735
4736         mac_filter = rte_zmalloc("mac_filter_info_data",
4737                                  num * sizeof(*mac_filter), 0);
4738         if (mac_filter == NULL) {
4739                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4740                 return I40E_ERR_NO_MEMORY;
4741         }
4742
4743         i = 0;
4744
4745         /* Remove all existing mac */
4746         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4747                 mac_filter[i] = f->mac_info;
4748                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4749                 if (ret) {
4750                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4751                                     on ? "enable" : "disable");
4752                         goto DONE;
4753                 }
4754                 i++;
4755         }
4756
4757         /* Override with new filter */
4758         for (i = 0; i < num; i++) {
4759                 mac_filter[i].filter_type = desired_filter;
4760                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4761                 if (ret) {
4762                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4763                                     on ? "enable" : "disable");
4764                         goto DONE;
4765                 }
4766         }
4767
4768 DONE:
4769         rte_free(mac_filter);
4770         return ret;
4771 }
4772
4773 /* Configure vlan stripping on or off */
4774 int
4775 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4776 {
4777         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4778         struct i40e_vsi_context ctxt;
4779         uint8_t vlan_flags;
4780         int ret = I40E_SUCCESS;
4781
4782         /* Check if it has been already on or off */
4783         if (vsi->info.valid_sections &
4784                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4785                 if (on) {
4786                         if ((vsi->info.port_vlan_flags &
4787                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4788                                 return 0; /* already on */
4789                 } else {
4790                         if ((vsi->info.port_vlan_flags &
4791                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4792                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4793                                 return 0; /* already off */
4794                 }
4795         }
4796
4797         if (on)
4798                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4799         else
4800                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4801         vsi->info.valid_sections =
4802                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4803         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4804         vsi->info.port_vlan_flags |= vlan_flags;
4805         ctxt.seid = vsi->seid;
4806         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4807         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4808         if (ret)
4809                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4810                             on ? "enable" : "disable");
4811
4812         return ret;
4813 }
4814
4815 static int
4816 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4817 {
4818         struct rte_eth_dev_data *data = dev->data;
4819         int ret;
4820         int mask = 0;
4821
4822         /* Apply vlan offload setting */
4823         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4824         i40e_vlan_offload_set(dev, mask);
4825
4826         /* Apply double-vlan setting, not implemented yet */
4827
4828         /* Apply pvid setting */
4829         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4830                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4831         if (ret)
4832                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4833
4834         return ret;
4835 }
4836
4837 static int
4838 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4839 {
4840         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4841
4842         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4843 }
4844
4845 static int
4846 i40e_update_flow_control(struct i40e_hw *hw)
4847 {
4848 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4849         struct i40e_link_status link_status;
4850         uint32_t rxfc = 0, txfc = 0, reg;
4851         uint8_t an_info;
4852         int ret;
4853
4854         memset(&link_status, 0, sizeof(link_status));
4855         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4856         if (ret != I40E_SUCCESS) {
4857                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4858                 goto write_reg; /* Disable flow control */
4859         }
4860
4861         an_info = hw->phy.link_info.an_info;
4862         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4863                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4864                 ret = I40E_ERR_NOT_READY;
4865                 goto write_reg; /* Disable flow control */
4866         }
4867         /**
4868          * If link auto negotiation is enabled, flow control needs to
4869          * be configured according to it
4870          */
4871         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4872         case I40E_LINK_PAUSE_RXTX:
4873                 rxfc = 1;
4874                 txfc = 1;
4875                 hw->fc.current_mode = I40E_FC_FULL;
4876                 break;
4877         case I40E_AQ_LINK_PAUSE_RX:
4878                 rxfc = 1;
4879                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4880                 break;
4881         case I40E_AQ_LINK_PAUSE_TX:
4882                 txfc = 1;
4883                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4884                 break;
4885         default:
4886                 hw->fc.current_mode = I40E_FC_NONE;
4887                 break;
4888         }
4889
4890 write_reg:
4891         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4892                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4893         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4894         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4895         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4896         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4897
4898         return ret;
4899 }
4900
4901 /* PF setup */
4902 static int
4903 i40e_pf_setup(struct i40e_pf *pf)
4904 {
4905         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4906         struct i40e_filter_control_settings settings;
4907         struct i40e_vsi *vsi;
4908         int ret;
4909
4910         /* Clear all stats counters */
4911         pf->offset_loaded = FALSE;
4912         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4913         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4914
4915         ret = i40e_pf_get_switch_config(pf);
4916         if (ret != I40E_SUCCESS) {
4917                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4918                 return ret;
4919         }
4920         if (pf->flags & I40E_FLAG_FDIR) {
4921                 /* make queue allocated first, let FDIR use queue pair 0*/
4922                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4923                 if (ret != I40E_FDIR_QUEUE_ID) {
4924                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4925                                     " ret =%d", ret);
4926                         pf->flags &= ~I40E_FLAG_FDIR;
4927                 }
4928         }
4929         /*  main VSI setup */
4930         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4931         if (!vsi) {
4932                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4933                 return I40E_ERR_NOT_READY;
4934         }
4935         pf->main_vsi = vsi;
4936
4937         /* Configure filter control */
4938         memset(&settings, 0, sizeof(settings));
4939         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4940                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4941         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4942                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4943         else {
4944                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4945                                                 hw->func_caps.rss_table_size);
4946                 return I40E_ERR_PARAM;
4947         }
4948         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4949                         "size: %u\n", hw->func_caps.rss_table_size);
4950         pf->hash_lut_size = hw->func_caps.rss_table_size;
4951
4952         /* Enable ethtype and macvlan filters */
4953         settings.enable_ethtype = TRUE;
4954         settings.enable_macvlan = TRUE;
4955         ret = i40e_set_filter_control(hw, &settings);
4956         if (ret)
4957                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4958                                                                 ret);
4959
4960         /* Update flow control according to the auto negotiation */
4961         i40e_update_flow_control(hw);
4962
4963         return I40E_SUCCESS;
4964 }
4965
4966 int
4967 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4968 {
4969         uint32_t reg;
4970         uint16_t j;
4971
4972         /**
4973          * Set or clear TX Queue Disable flags,
4974          * which is required by hardware.
4975          */
4976         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4977         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4978
4979         /* Wait until the request is finished */
4980         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4981                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4982                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4983                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4984                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4985                                                         & 0x1))) {
4986                         break;
4987                 }
4988         }
4989         if (on) {
4990                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4991                         return I40E_SUCCESS; /* already on, skip next steps */
4992
4993                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4994                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4995         } else {
4996                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4997                         return I40E_SUCCESS; /* already off, skip next steps */
4998                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4999         }
5000         /* Write the register */
5001         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5002         /* Check the result */
5003         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5004                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5005                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5006                 if (on) {
5007                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5008                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5009                                 break;
5010                 } else {
5011                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5012                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5013                                 break;
5014                 }
5015         }
5016         /* Check if it is timeout */
5017         if (j >= I40E_CHK_Q_ENA_COUNT) {
5018                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5019                             (on ? "enable" : "disable"), q_idx);
5020                 return I40E_ERR_TIMEOUT;
5021         }
5022
5023         return I40E_SUCCESS;
5024 }
5025
5026 /* Swith on or off the tx queues */
5027 static int
5028 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5029 {
5030         struct rte_eth_dev_data *dev_data = pf->dev_data;
5031         struct i40e_tx_queue *txq;
5032         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5033         uint16_t i;
5034         int ret;
5035
5036         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5037                 txq = dev_data->tx_queues[i];
5038                 /* Don't operate the queue if not configured or
5039                  * if starting only per queue */
5040                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5041                         continue;
5042                 if (on)
5043                         ret = i40e_dev_tx_queue_start(dev, i);
5044                 else
5045                         ret = i40e_dev_tx_queue_stop(dev, i);
5046                 if ( ret != I40E_SUCCESS)
5047                         return ret;
5048         }
5049
5050         return I40E_SUCCESS;
5051 }
5052
5053 int
5054 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5055 {
5056         uint32_t reg;
5057         uint16_t j;
5058
5059         /* Wait until the request is finished */
5060         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5061                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5062                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5063                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5064                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5065                         break;
5066         }
5067
5068         if (on) {
5069                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5070                         return I40E_SUCCESS; /* Already on, skip next steps */
5071                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5072         } else {
5073                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5074                         return I40E_SUCCESS; /* Already off, skip next steps */
5075                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5076         }
5077
5078         /* Write the register */
5079         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5080         /* Check the result */
5081         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5082                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5083                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5084                 if (on) {
5085                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5086                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5087                                 break;
5088                 } else {
5089                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5090                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5091                                 break;
5092                 }
5093         }
5094
5095         /* Check if it is timeout */
5096         if (j >= I40E_CHK_Q_ENA_COUNT) {
5097                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5098                             (on ? "enable" : "disable"), q_idx);
5099                 return I40E_ERR_TIMEOUT;
5100         }
5101
5102         return I40E_SUCCESS;
5103 }
5104 /* Switch on or off the rx queues */
5105 static int
5106 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5107 {
5108         struct rte_eth_dev_data *dev_data = pf->dev_data;
5109         struct i40e_rx_queue *rxq;
5110         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5111         uint16_t i;
5112         int ret;
5113
5114         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5115                 rxq = dev_data->rx_queues[i];
5116                 /* Don't operate the queue if not configured or
5117                  * if starting only per queue */
5118                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5119                         continue;
5120                 if (on)
5121                         ret = i40e_dev_rx_queue_start(dev, i);
5122                 else
5123                         ret = i40e_dev_rx_queue_stop(dev, i);
5124                 if (ret != I40E_SUCCESS)
5125                         return ret;
5126         }
5127
5128         return I40E_SUCCESS;
5129 }
5130
5131 /* Switch on or off all the rx/tx queues */
5132 int
5133 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5134 {
5135         int ret;
5136
5137         if (on) {
5138                 /* enable rx queues before enabling tx queues */
5139                 ret = i40e_dev_switch_rx_queues(pf, on);
5140                 if (ret) {
5141                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5142                         return ret;
5143                 }
5144                 ret = i40e_dev_switch_tx_queues(pf, on);
5145         } else {
5146                 /* Stop tx queues before stopping rx queues */
5147                 ret = i40e_dev_switch_tx_queues(pf, on);
5148                 if (ret) {
5149                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5150                         return ret;
5151                 }
5152                 ret = i40e_dev_switch_rx_queues(pf, on);
5153         }
5154
5155         return ret;
5156 }
5157
5158 /* Initialize VSI for TX */
5159 static int
5160 i40e_dev_tx_init(struct i40e_pf *pf)
5161 {
5162         struct rte_eth_dev_data *data = pf->dev_data;
5163         uint16_t i;
5164         uint32_t ret = I40E_SUCCESS;
5165         struct i40e_tx_queue *txq;
5166
5167         for (i = 0; i < data->nb_tx_queues; i++) {
5168                 txq = data->tx_queues[i];
5169                 if (!txq || !txq->q_set)
5170                         continue;
5171                 ret = i40e_tx_queue_init(txq);
5172                 if (ret != I40E_SUCCESS)
5173                         break;
5174         }
5175         if (ret == I40E_SUCCESS)
5176                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5177                                      ->eth_dev);
5178
5179         return ret;
5180 }
5181
5182 /* Initialize VSI for RX */
5183 static int
5184 i40e_dev_rx_init(struct i40e_pf *pf)
5185 {
5186         struct rte_eth_dev_data *data = pf->dev_data;
5187         int ret = I40E_SUCCESS;
5188         uint16_t i;
5189         struct i40e_rx_queue *rxq;
5190
5191         i40e_pf_config_mq_rx(pf);
5192         for (i = 0; i < data->nb_rx_queues; i++) {
5193                 rxq = data->rx_queues[i];
5194                 if (!rxq || !rxq->q_set)
5195                         continue;
5196
5197                 ret = i40e_rx_queue_init(rxq);
5198                 if (ret != I40E_SUCCESS) {
5199                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5200                                     "initialization");
5201                         break;
5202                 }
5203         }
5204         if (ret == I40E_SUCCESS)
5205                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5206                                      ->eth_dev);
5207
5208         return ret;
5209 }
5210
5211 static int
5212 i40e_dev_rxtx_init(struct i40e_pf *pf)
5213 {
5214         int err;
5215
5216         err = i40e_dev_tx_init(pf);
5217         if (err) {
5218                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5219                 return err;
5220         }
5221         err = i40e_dev_rx_init(pf);
5222         if (err) {
5223                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5224                 return err;
5225         }
5226
5227         return err;
5228 }
5229
5230 static int
5231 i40e_vmdq_setup(struct rte_eth_dev *dev)
5232 {
5233         struct rte_eth_conf *conf = &dev->data->dev_conf;
5234         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5235         int i, err, conf_vsis, j, loop;
5236         struct i40e_vsi *vsi;
5237         struct i40e_vmdq_info *vmdq_info;
5238         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5239         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5240
5241         /*
5242          * Disable interrupt to avoid message from VF. Furthermore, it will
5243          * avoid race condition in VSI creation/destroy.
5244          */
5245         i40e_pf_disable_irq0(hw);
5246
5247         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5248                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5249                 return -ENOTSUP;
5250         }
5251
5252         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5253         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5254                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5255                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5256                         pf->max_nb_vmdq_vsi);
5257                 return -ENOTSUP;
5258         }
5259
5260         if (pf->vmdq != NULL) {
5261                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5262                 return 0;
5263         }
5264
5265         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5266                                 sizeof(*vmdq_info) * conf_vsis, 0);
5267
5268         if (pf->vmdq == NULL) {
5269                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5270                 return -ENOMEM;
5271         }
5272
5273         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5274
5275         /* Create VMDQ VSI */
5276         for (i = 0; i < conf_vsis; i++) {
5277                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5278                                 vmdq_conf->enable_loop_back);
5279                 if (vsi == NULL) {
5280                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5281                         err = -1;
5282                         goto err_vsi_setup;
5283                 }
5284                 vmdq_info = &pf->vmdq[i];
5285                 vmdq_info->pf = pf;
5286                 vmdq_info->vsi = vsi;
5287         }
5288         pf->nb_cfg_vmdq_vsi = conf_vsis;
5289
5290         /* Configure Vlan */
5291         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5292         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5293                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5294                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5295                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5296                                         vmdq_conf->pool_map[i].vlan_id, j);
5297
5298                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5299                                                 vmdq_conf->pool_map[i].vlan_id);
5300                                 if (err) {
5301                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5302                                         err = -1;
5303                                         goto err_vsi_setup;
5304                                 }
5305                         }
5306                 }
5307         }
5308
5309         i40e_pf_enable_irq0(hw);
5310
5311         return 0;
5312
5313 err_vsi_setup:
5314         for (i = 0; i < conf_vsis; i++)
5315                 if (pf->vmdq[i].vsi == NULL)
5316                         break;
5317                 else
5318                         i40e_vsi_release(pf->vmdq[i].vsi);
5319
5320         rte_free(pf->vmdq);
5321         pf->vmdq = NULL;
5322         i40e_pf_enable_irq0(hw);
5323         return err;
5324 }
5325
5326 static void
5327 i40e_stat_update_32(struct i40e_hw *hw,
5328                    uint32_t reg,
5329                    bool offset_loaded,
5330                    uint64_t *offset,
5331                    uint64_t *stat)
5332 {
5333         uint64_t new_data;
5334
5335         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5336         if (!offset_loaded)
5337                 *offset = new_data;
5338
5339         if (new_data >= *offset)
5340                 *stat = (uint64_t)(new_data - *offset);
5341         else
5342                 *stat = (uint64_t)((new_data +
5343                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5344 }
5345
5346 static void
5347 i40e_stat_update_48(struct i40e_hw *hw,
5348                    uint32_t hireg,
5349                    uint32_t loreg,
5350                    bool offset_loaded,
5351                    uint64_t *offset,
5352                    uint64_t *stat)
5353 {
5354         uint64_t new_data;
5355
5356         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5357         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5358                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5359
5360         if (!offset_loaded)
5361                 *offset = new_data;
5362
5363         if (new_data >= *offset)
5364                 *stat = new_data - *offset;
5365         else
5366                 *stat = (uint64_t)((new_data +
5367                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5368
5369         *stat &= I40E_48_BIT_MASK;
5370 }
5371
5372 /* Disable IRQ0 */
5373 void
5374 i40e_pf_disable_irq0(struct i40e_hw *hw)
5375 {
5376         /* Disable all interrupt types */
5377         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5378         I40E_WRITE_FLUSH(hw);
5379 }
5380
5381 /* Enable IRQ0 */
5382 void
5383 i40e_pf_enable_irq0(struct i40e_hw *hw)
5384 {
5385         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5386                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5387                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5388                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5389         I40E_WRITE_FLUSH(hw);
5390 }
5391
5392 static void
5393 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5394 {
5395         /* read pending request and disable first */
5396         i40e_pf_disable_irq0(hw);
5397         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5398         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5399                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5400
5401         if (no_queue)
5402                 /* Link no queues with irq0 */
5403                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5404                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5405 }
5406
5407 static void
5408 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5409 {
5410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5412         int i;
5413         uint16_t abs_vf_id;
5414         uint32_t index, offset, val;
5415
5416         if (!pf->vfs)
5417                 return;
5418         /**
5419          * Try to find which VF trigger a reset, use absolute VF id to access
5420          * since the reg is global register.
5421          */
5422         for (i = 0; i < pf->vf_num; i++) {
5423                 abs_vf_id = hw->func_caps.vf_base_id + i;
5424                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5425                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5426                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5427                 /* VFR event occured */
5428                 if (val & (0x1 << offset)) {
5429                         int ret;
5430
5431                         /* Clear the event first */
5432                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5433                                                         (0x1 << offset));
5434                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5435                         /**
5436                          * Only notify a VF reset event occured,
5437                          * don't trigger another SW reset
5438                          */
5439                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5440                         if (ret != I40E_SUCCESS)
5441                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5442                 }
5443         }
5444 }
5445
5446 static void
5447 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5448 {
5449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5450         struct i40e_virtchnl_pf_event event;
5451         int i;
5452
5453         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5454         event.event_data.link_event.link_status =
5455                 dev->data->dev_link.link_status;
5456         event.event_data.link_event.link_speed =
5457                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5458
5459         for (i = 0; i < pf->vf_num; i++)
5460                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5461                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5462 }
5463
5464 static void
5465 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5466 {
5467         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5468         struct i40e_arq_event_info info;
5469         uint16_t pending, opcode;
5470         int ret;
5471
5472         info.buf_len = I40E_AQ_BUF_SZ;
5473         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5474         if (!info.msg_buf) {
5475                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5476                 return;
5477         }
5478
5479         pending = 1;
5480         while (pending) {
5481                 ret = i40e_clean_arq_element(hw, &info, &pending);
5482
5483                 if (ret != I40E_SUCCESS) {
5484                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5485                                     "aq_err: %u", hw->aq.asq_last_status);
5486                         break;
5487                 }
5488                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5489
5490                 switch (opcode) {
5491                 case i40e_aqc_opc_send_msg_to_pf:
5492                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5493                         i40e_pf_host_handle_vf_msg(dev,
5494                                         rte_le_to_cpu_16(info.desc.retval),
5495                                         rte_le_to_cpu_32(info.desc.cookie_high),
5496                                         rte_le_to_cpu_32(info.desc.cookie_low),
5497                                         info.msg_buf,
5498                                         info.msg_len);
5499                         break;
5500                 case i40e_aqc_opc_get_link_status:
5501                         ret = i40e_dev_link_update(dev, 0);
5502                         if (!ret) {
5503                                 i40e_notify_all_vfs_link_status(dev);
5504                                 _rte_eth_dev_callback_process(dev,
5505                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5506                         }
5507                         break;
5508                 default:
5509                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5510                                     opcode);
5511                         break;
5512                 }
5513         }
5514         rte_free(info.msg_buf);
5515 }
5516
5517 /**
5518  * Interrupt handler triggered by NIC  for handling
5519  * specific interrupt.
5520  *
5521  * @param handle
5522  *  Pointer to interrupt handle.
5523  * @param param
5524  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5525  *
5526  * @return
5527  *  void
5528  */
5529 static void
5530 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5531                            void *param)
5532 {
5533         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5534         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5535         uint32_t icr0;
5536
5537         /* Disable interrupt */
5538         i40e_pf_disable_irq0(hw);
5539
5540         /* read out interrupt causes */
5541         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5542
5543         /* No interrupt event indicated */
5544         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5545                 PMD_DRV_LOG(INFO, "No interrupt event");
5546                 goto done;
5547         }
5548 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5549         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5550                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5551         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5552                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5553         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5554                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5555         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5556                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5557         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5558                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5559         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5560                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5561         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5562                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5563 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5564
5565         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5566                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5567                 i40e_dev_handle_vfr_event(dev);
5568         }
5569         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5570                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5571                 i40e_dev_handle_aq_msg(dev);
5572         }
5573
5574 done:
5575         /* Enable interrupt */
5576         i40e_pf_enable_irq0(hw);
5577         rte_intr_enable(&(dev->pci_dev->intr_handle));
5578 }
5579
5580 static int
5581 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5582                          struct i40e_macvlan_filter *filter,
5583                          int total)
5584 {
5585         int ele_num, ele_buff_size;
5586         int num, actual_num, i;
5587         uint16_t flags;
5588         int ret = I40E_SUCCESS;
5589         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5590         struct i40e_aqc_add_macvlan_element_data *req_list;
5591
5592         if (filter == NULL  || total == 0)
5593                 return I40E_ERR_PARAM;
5594         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5595         ele_buff_size = hw->aq.asq_buf_size;
5596
5597         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5598         if (req_list == NULL) {
5599                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5600                 return I40E_ERR_NO_MEMORY;
5601         }
5602
5603         num = 0;
5604         do {
5605                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5606                 memset(req_list, 0, ele_buff_size);
5607
5608                 for (i = 0; i < actual_num; i++) {
5609                         (void)rte_memcpy(req_list[i].mac_addr,
5610                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5611                         req_list[i].vlan_tag =
5612                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5613
5614                         switch (filter[num + i].filter_type) {
5615                         case RTE_MAC_PERFECT_MATCH:
5616                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5617                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5618                                 break;
5619                         case RTE_MACVLAN_PERFECT_MATCH:
5620                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5621                                 break;
5622                         case RTE_MAC_HASH_MATCH:
5623                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5624                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5625                                 break;
5626                         case RTE_MACVLAN_HASH_MATCH:
5627                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5628                                 break;
5629                         default:
5630                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5631                                 ret = I40E_ERR_PARAM;
5632                                 goto DONE;
5633                         }
5634
5635                         req_list[i].queue_number = 0;
5636
5637                         req_list[i].flags = rte_cpu_to_le_16(flags);
5638                 }
5639
5640                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5641                                                 actual_num, NULL);
5642                 if (ret != I40E_SUCCESS) {
5643                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5644                         goto DONE;
5645                 }
5646                 num += actual_num;
5647         } while (num < total);
5648
5649 DONE:
5650         rte_free(req_list);
5651         return ret;
5652 }
5653
5654 static int
5655 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5656                             struct i40e_macvlan_filter *filter,
5657                             int total)
5658 {
5659         int ele_num, ele_buff_size;
5660         int num, actual_num, i;
5661         uint16_t flags;
5662         int ret = I40E_SUCCESS;
5663         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5664         struct i40e_aqc_remove_macvlan_element_data *req_list;
5665
5666         if (filter == NULL  || total == 0)
5667                 return I40E_ERR_PARAM;
5668
5669         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5670         ele_buff_size = hw->aq.asq_buf_size;
5671
5672         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5673         if (req_list == NULL) {
5674                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5675                 return I40E_ERR_NO_MEMORY;
5676         }
5677
5678         num = 0;
5679         do {
5680                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5681                 memset(req_list, 0, ele_buff_size);
5682
5683                 for (i = 0; i < actual_num; i++) {
5684                         (void)rte_memcpy(req_list[i].mac_addr,
5685                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5686                         req_list[i].vlan_tag =
5687                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5688
5689                         switch (filter[num + i].filter_type) {
5690                         case RTE_MAC_PERFECT_MATCH:
5691                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5692                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5693                                 break;
5694                         case RTE_MACVLAN_PERFECT_MATCH:
5695                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5696                                 break;
5697                         case RTE_MAC_HASH_MATCH:
5698                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5699                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5700                                 break;
5701                         case RTE_MACVLAN_HASH_MATCH:
5702                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5703                                 break;
5704                         default:
5705                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5706                                 ret = I40E_ERR_PARAM;
5707                                 goto DONE;
5708                         }
5709                         req_list[i].flags = rte_cpu_to_le_16(flags);
5710                 }
5711
5712                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5713                                                 actual_num, NULL);
5714                 if (ret != I40E_SUCCESS) {
5715                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5716                         goto DONE;
5717                 }
5718                 num += actual_num;
5719         } while (num < total);
5720
5721 DONE:
5722         rte_free(req_list);
5723         return ret;
5724 }
5725
5726 /* Find out specific MAC filter */
5727 static struct i40e_mac_filter *
5728 i40e_find_mac_filter(struct i40e_vsi *vsi,
5729                          struct ether_addr *macaddr)
5730 {
5731         struct i40e_mac_filter *f;
5732
5733         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5734                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5735                         return f;
5736         }
5737
5738         return NULL;
5739 }
5740
5741 static bool
5742 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5743                          uint16_t vlan_id)
5744 {
5745         uint32_t vid_idx, vid_bit;
5746
5747         if (vlan_id > ETH_VLAN_ID_MAX)
5748                 return 0;
5749
5750         vid_idx = I40E_VFTA_IDX(vlan_id);
5751         vid_bit = I40E_VFTA_BIT(vlan_id);
5752
5753         if (vsi->vfta[vid_idx] & vid_bit)
5754                 return 1;
5755         else
5756                 return 0;
5757 }
5758
5759 static void
5760 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5761                          uint16_t vlan_id, bool on)
5762 {
5763         uint32_t vid_idx, vid_bit;
5764
5765         if (vlan_id > ETH_VLAN_ID_MAX)
5766                 return;
5767
5768         vid_idx = I40E_VFTA_IDX(vlan_id);
5769         vid_bit = I40E_VFTA_BIT(vlan_id);
5770
5771         if (on)
5772                 vsi->vfta[vid_idx] |= vid_bit;
5773         else
5774                 vsi->vfta[vid_idx] &= ~vid_bit;
5775 }
5776
5777 /**
5778  * Find all vlan options for specific mac addr,
5779  * return with actual vlan found.
5780  */
5781 static inline int
5782 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5783                            struct i40e_macvlan_filter *mv_f,
5784                            int num, struct ether_addr *addr)
5785 {
5786         int i;
5787         uint32_t j, k;
5788
5789         /**
5790          * Not to use i40e_find_vlan_filter to decrease the loop time,
5791          * although the code looks complex.
5792           */
5793         if (num < vsi->vlan_num)
5794                 return I40E_ERR_PARAM;
5795
5796         i = 0;
5797         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5798                 if (vsi->vfta[j]) {
5799                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5800                                 if (vsi->vfta[j] & (1 << k)) {
5801                                         if (i > num - 1) {
5802                                                 PMD_DRV_LOG(ERR, "vlan number "
5803                                                             "not match");
5804                                                 return I40E_ERR_PARAM;
5805                                         }
5806                                         (void)rte_memcpy(&mv_f[i].macaddr,
5807                                                         addr, ETH_ADDR_LEN);
5808                                         mv_f[i].vlan_id =
5809                                                 j * I40E_UINT32_BIT_SIZE + k;
5810                                         i++;
5811                                 }
5812                         }
5813                 }
5814         }
5815         return I40E_SUCCESS;
5816 }
5817
5818 static inline int
5819 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5820                            struct i40e_macvlan_filter *mv_f,
5821                            int num,
5822                            uint16_t vlan)
5823 {
5824         int i = 0;
5825         struct i40e_mac_filter *f;
5826
5827         if (num < vsi->mac_num)
5828                 return I40E_ERR_PARAM;
5829
5830         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5831                 if (i > num - 1) {
5832                         PMD_DRV_LOG(ERR, "buffer number not match");
5833                         return I40E_ERR_PARAM;
5834                 }
5835                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5836                                 ETH_ADDR_LEN);
5837                 mv_f[i].vlan_id = vlan;
5838                 mv_f[i].filter_type = f->mac_info.filter_type;
5839                 i++;
5840         }
5841
5842         return I40E_SUCCESS;
5843 }
5844
5845 static int
5846 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5847 {
5848         int i, num;
5849         struct i40e_mac_filter *f;
5850         struct i40e_macvlan_filter *mv_f;
5851         int ret = I40E_SUCCESS;
5852
5853         if (vsi == NULL || vsi->mac_num == 0)
5854                 return I40E_ERR_PARAM;
5855
5856         /* Case that no vlan is set */
5857         if (vsi->vlan_num == 0)
5858                 num = vsi->mac_num;
5859         else
5860                 num = vsi->mac_num * vsi->vlan_num;
5861
5862         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5863         if (mv_f == NULL) {
5864                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5865                 return I40E_ERR_NO_MEMORY;
5866         }
5867
5868         i = 0;
5869         if (vsi->vlan_num == 0) {
5870                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5871                         (void)rte_memcpy(&mv_f[i].macaddr,
5872                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5873                         mv_f[i].vlan_id = 0;
5874                         i++;
5875                 }
5876         } else {
5877                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5878                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5879                                         vsi->vlan_num, &f->mac_info.mac_addr);
5880                         if (ret != I40E_SUCCESS)
5881                                 goto DONE;
5882                         i += vsi->vlan_num;
5883                 }
5884         }
5885
5886         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5887 DONE:
5888         rte_free(mv_f);
5889
5890         return ret;
5891 }
5892
5893 int
5894 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5895 {
5896         struct i40e_macvlan_filter *mv_f;
5897         int mac_num;
5898         int ret = I40E_SUCCESS;
5899
5900         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5901                 return I40E_ERR_PARAM;
5902
5903         /* If it's already set, just return */
5904         if (i40e_find_vlan_filter(vsi,vlan))
5905                 return I40E_SUCCESS;
5906
5907         mac_num = vsi->mac_num;
5908
5909         if (mac_num == 0) {
5910                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5911                 return I40E_ERR_PARAM;
5912         }
5913
5914         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5915
5916         if (mv_f == NULL) {
5917                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5918                 return I40E_ERR_NO_MEMORY;
5919         }
5920
5921         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5922
5923         if (ret != I40E_SUCCESS)
5924                 goto DONE;
5925
5926         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5927
5928         if (ret != I40E_SUCCESS)
5929                 goto DONE;
5930
5931         i40e_set_vlan_filter(vsi, vlan, 1);
5932
5933         vsi->vlan_num++;
5934         ret = I40E_SUCCESS;
5935 DONE:
5936         rte_free(mv_f);
5937         return ret;
5938 }
5939
5940 int
5941 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5942 {
5943         struct i40e_macvlan_filter *mv_f;
5944         int mac_num;
5945         int ret = I40E_SUCCESS;
5946
5947         /**
5948          * Vlan 0 is the generic filter for untagged packets
5949          * and can't be removed.
5950          */
5951         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5952                 return I40E_ERR_PARAM;
5953
5954         /* If can't find it, just return */
5955         if (!i40e_find_vlan_filter(vsi, vlan))
5956                 return I40E_ERR_PARAM;
5957
5958         mac_num = vsi->mac_num;
5959
5960         if (mac_num == 0) {
5961                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5962                 return I40E_ERR_PARAM;
5963         }
5964
5965         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5966
5967         if (mv_f == NULL) {
5968                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5969                 return I40E_ERR_NO_MEMORY;
5970         }
5971
5972         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5973
5974         if (ret != I40E_SUCCESS)
5975                 goto DONE;
5976
5977         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5978
5979         if (ret != I40E_SUCCESS)
5980                 goto DONE;
5981
5982         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5983         if (vsi->vlan_num == 1) {
5984                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5985                 if (ret != I40E_SUCCESS)
5986                         goto DONE;
5987
5988                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5989                 if (ret != I40E_SUCCESS)
5990                         goto DONE;
5991         }
5992
5993         i40e_set_vlan_filter(vsi, vlan, 0);
5994
5995         vsi->vlan_num--;
5996         ret = I40E_SUCCESS;
5997 DONE:
5998         rte_free(mv_f);
5999         return ret;
6000 }
6001
6002 int
6003 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6004 {
6005         struct i40e_mac_filter *f;
6006         struct i40e_macvlan_filter *mv_f;
6007         int i, vlan_num = 0;
6008         int ret = I40E_SUCCESS;
6009
6010         /* If it's add and we've config it, return */
6011         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6012         if (f != NULL)
6013                 return I40E_SUCCESS;
6014         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6015                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6016
6017                 /**
6018                  * If vlan_num is 0, that's the first time to add mac,
6019                  * set mask for vlan_id 0.
6020                  */
6021                 if (vsi->vlan_num == 0) {
6022                         i40e_set_vlan_filter(vsi, 0, 1);
6023                         vsi->vlan_num = 1;
6024                 }
6025                 vlan_num = vsi->vlan_num;
6026         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6027                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6028                 vlan_num = 1;
6029
6030         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6031         if (mv_f == NULL) {
6032                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6033                 return I40E_ERR_NO_MEMORY;
6034         }
6035
6036         for (i = 0; i < vlan_num; i++) {
6037                 mv_f[i].filter_type = mac_filter->filter_type;
6038                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6039                                 ETH_ADDR_LEN);
6040         }
6041
6042         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6043                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6044                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6045                                         &mac_filter->mac_addr);
6046                 if (ret != I40E_SUCCESS)
6047                         goto DONE;
6048         }
6049
6050         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6051         if (ret != I40E_SUCCESS)
6052                 goto DONE;
6053
6054         /* Add the mac addr into mac list */
6055         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6056         if (f == NULL) {
6057                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6058                 ret = I40E_ERR_NO_MEMORY;
6059                 goto DONE;
6060         }
6061         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6062                         ETH_ADDR_LEN);
6063         f->mac_info.filter_type = mac_filter->filter_type;
6064         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6065         vsi->mac_num++;
6066
6067         ret = I40E_SUCCESS;
6068 DONE:
6069         rte_free(mv_f);
6070
6071         return ret;
6072 }
6073
6074 int
6075 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6076 {
6077         struct i40e_mac_filter *f;
6078         struct i40e_macvlan_filter *mv_f;
6079         int i, vlan_num;
6080         enum rte_mac_filter_type filter_type;
6081         int ret = I40E_SUCCESS;
6082
6083         /* Can't find it, return an error */
6084         f = i40e_find_mac_filter(vsi, addr);
6085         if (f == NULL)
6086                 return I40E_ERR_PARAM;
6087
6088         vlan_num = vsi->vlan_num;
6089         filter_type = f->mac_info.filter_type;
6090         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6091                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6092                 if (vlan_num == 0) {
6093                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6094                         return I40E_ERR_PARAM;
6095                 }
6096         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6097                         filter_type == RTE_MAC_HASH_MATCH)
6098                 vlan_num = 1;
6099
6100         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6101         if (mv_f == NULL) {
6102                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6103                 return I40E_ERR_NO_MEMORY;
6104         }
6105
6106         for (i = 0; i < vlan_num; i++) {
6107                 mv_f[i].filter_type = filter_type;
6108                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6109                                 ETH_ADDR_LEN);
6110         }
6111         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6112                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6113                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6114                 if (ret != I40E_SUCCESS)
6115                         goto DONE;
6116         }
6117
6118         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6119         if (ret != I40E_SUCCESS)
6120                 goto DONE;
6121
6122         /* Remove the mac addr into mac list */
6123         TAILQ_REMOVE(&vsi->mac_list, f, next);
6124         rte_free(f);
6125         vsi->mac_num--;
6126
6127         ret = I40E_SUCCESS;
6128 DONE:
6129         rte_free(mv_f);
6130         return ret;
6131 }
6132
6133 /* Configure hash enable flags for RSS */
6134 uint64_t
6135 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6136 {
6137         uint64_t hena = 0;
6138
6139         if (!flags)
6140                 return hena;
6141
6142         if (flags & ETH_RSS_FRAG_IPV4)
6143                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6144         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6145                 if (type == I40E_MAC_X722) {
6146                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6147                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6148                 } else
6149                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6150         }
6151         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6152                 if (type == I40E_MAC_X722) {
6153                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6154                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6155                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6156                 } else
6157                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6158         }
6159         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6160                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6161         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6162                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6163         if (flags & ETH_RSS_FRAG_IPV6)
6164                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6165         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6166                 if (type == I40E_MAC_X722) {
6167                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6168                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6169                 } else
6170                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6171         }
6172         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6173                 if (type == I40E_MAC_X722) {
6174                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6175                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6176                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6177                 } else
6178                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6179         }
6180         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6181                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6182         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6183                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6184         if (flags & ETH_RSS_L2_PAYLOAD)
6185                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6186
6187         return hena;
6188 }
6189
6190 /* Parse the hash enable flags */
6191 uint64_t
6192 i40e_parse_hena(uint64_t flags)
6193 {
6194         uint64_t rss_hf = 0;
6195
6196         if (!flags)
6197                 return rss_hf;
6198         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6199                 rss_hf |= ETH_RSS_FRAG_IPV4;
6200         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6201                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6202 #ifdef X722_SUPPORT
6203         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6204                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6205 #endif
6206         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6207                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6208 #ifdef X722_SUPPORT
6209         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6210                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6211         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6212                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6213 #endif
6214         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6215                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6216         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6217                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6218         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6219                 rss_hf |= ETH_RSS_FRAG_IPV6;
6220         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6221                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6222 #ifdef X722_SUPPORT
6223         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6224                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6225 #endif
6226         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6227                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6228 #ifdef X722_SUPPORT
6229         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6230                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6231         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6232                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6233 #endif
6234         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6235                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6236         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6237                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6238         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6239                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6240
6241         return rss_hf;
6242 }
6243
6244 /* Disable RSS */
6245 static void
6246 i40e_pf_disable_rss(struct i40e_pf *pf)
6247 {
6248         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6249         uint64_t hena;
6250
6251         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6252         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6253         if (hw->mac.type == I40E_MAC_X722)
6254                 hena &= ~I40E_RSS_HENA_ALL_X722;
6255         else
6256                 hena &= ~I40E_RSS_HENA_ALL;
6257         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6258         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6259         I40E_WRITE_FLUSH(hw);
6260 }
6261
6262 static int
6263 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6264 {
6265         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6266         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6267         int ret = 0;
6268
6269         if (!key || key_len == 0) {
6270                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6271                 return 0;
6272         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6273                 sizeof(uint32_t)) {
6274                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6275                 return -EINVAL;
6276         }
6277
6278         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6279                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6280                         (struct i40e_aqc_get_set_rss_key_data *)key;
6281
6282                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6283                 if (ret)
6284                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6285                                      "via AQ");
6286         } else {
6287                 uint32_t *hash_key = (uint32_t *)key;
6288                 uint16_t i;
6289
6290                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6291                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6292                 I40E_WRITE_FLUSH(hw);
6293         }
6294
6295         return ret;
6296 }
6297
6298 static int
6299 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6300 {
6301         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6302         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6303         int ret;
6304
6305         if (!key || !key_len)
6306                 return -EINVAL;
6307
6308         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6309                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6310                         (struct i40e_aqc_get_set_rss_key_data *)key);
6311                 if (ret) {
6312                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6313                         return ret;
6314                 }
6315         } else {
6316                 uint32_t *key_dw = (uint32_t *)key;
6317                 uint16_t i;
6318
6319                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6320                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6321         }
6322         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6323
6324         return 0;
6325 }
6326
6327 static int
6328 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6329 {
6330         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6331         uint64_t rss_hf;
6332         uint64_t hena;
6333         int ret;
6334
6335         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6336                                rss_conf->rss_key_len);
6337         if (ret)
6338                 return ret;
6339
6340         rss_hf = rss_conf->rss_hf;
6341         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6342         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6343         if (hw->mac.type == I40E_MAC_X722)
6344                 hena &= ~I40E_RSS_HENA_ALL_X722;
6345         else
6346                 hena &= ~I40E_RSS_HENA_ALL;
6347         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6348         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6349         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6350         I40E_WRITE_FLUSH(hw);
6351
6352         return 0;
6353 }
6354
6355 static int
6356 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6357                          struct rte_eth_rss_conf *rss_conf)
6358 {
6359         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6360         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6361         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6362         uint64_t hena;
6363
6364         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6365         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6366         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6367                  ? I40E_RSS_HENA_ALL_X722
6368                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6369                 if (rss_hf != 0) /* Enable RSS */
6370                         return -EINVAL;
6371                 return 0; /* Nothing to do */
6372         }
6373         /* RSS enabled */
6374         if (rss_hf == 0) /* Disable RSS */
6375                 return -EINVAL;
6376
6377         return i40e_hw_rss_hash_set(pf, rss_conf);
6378 }
6379
6380 static int
6381 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6382                            struct rte_eth_rss_conf *rss_conf)
6383 {
6384         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6385         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6386         uint64_t hena;
6387
6388         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6389                          &rss_conf->rss_key_len);
6390
6391         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6392         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6393         rss_conf->rss_hf = i40e_parse_hena(hena);
6394
6395         return 0;
6396 }
6397
6398 static int
6399 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6400 {
6401         switch (filter_type) {
6402         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6403                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6404                 break;
6405         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6406                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6407                 break;
6408         case RTE_TUNNEL_FILTER_IMAC_TENID:
6409                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6410                 break;
6411         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6412                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6413                 break;
6414         case ETH_TUNNEL_FILTER_IMAC:
6415                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6416                 break;
6417         case ETH_TUNNEL_FILTER_OIP:
6418                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6419                 break;
6420         case ETH_TUNNEL_FILTER_IIP:
6421                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6422                 break;
6423         default:
6424                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6425                 return -EINVAL;
6426         }
6427
6428         return 0;
6429 }
6430
6431 static int
6432 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6433                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6434                         uint8_t add)
6435 {
6436         uint16_t ip_type;
6437         uint32_t ipv4_addr;
6438         uint8_t i, tun_type = 0;
6439         /* internal varialbe to convert ipv6 byte order */
6440         uint32_t convert_ipv6[4];
6441         int val, ret = 0;
6442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6443         struct i40e_vsi *vsi = pf->main_vsi;
6444         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6445         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6446
6447         cld_filter = rte_zmalloc("tunnel_filter",
6448                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6449                 0);
6450
6451         if (NULL == cld_filter) {
6452                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6453                 return -EINVAL;
6454         }
6455         pfilter = cld_filter;
6456
6457         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6458         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6459
6460         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6461         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6462                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6463                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6464                 rte_memcpy(&pfilter->ipaddr.v4.data,
6465                                 &rte_cpu_to_le_32(ipv4_addr),
6466                                 sizeof(pfilter->ipaddr.v4.data));
6467         } else {
6468                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6469                 for (i = 0; i < 4; i++) {
6470                         convert_ipv6[i] =
6471                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6472                 }
6473                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6474                                 sizeof(pfilter->ipaddr.v6.data));
6475         }
6476
6477         /* check tunneled type */
6478         switch (tunnel_filter->tunnel_type) {
6479         case RTE_TUNNEL_TYPE_VXLAN:
6480                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6481                 break;
6482         case RTE_TUNNEL_TYPE_NVGRE:
6483                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6484                 break;
6485         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6486                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6487                 break;
6488         default:
6489                 /* Other tunnel types is not supported. */
6490                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6491                 rte_free(cld_filter);
6492                 return -EINVAL;
6493         }
6494
6495         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6496                                                 &pfilter->flags);
6497         if (val < 0) {
6498                 rte_free(cld_filter);
6499                 return -EINVAL;
6500         }
6501
6502         pfilter->flags |= rte_cpu_to_le_16(
6503                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6504                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6505         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6506         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6507
6508         if (add)
6509                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6510         else
6511                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6512                                                 cld_filter, 1);
6513
6514         rte_free(cld_filter);
6515         return ret;
6516 }
6517
6518 static int
6519 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6520 {
6521         uint8_t i;
6522
6523         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6524                 if (pf->vxlan_ports[i] == port)
6525                         return i;
6526         }
6527
6528         return -1;
6529 }
6530
6531 static int
6532 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6533 {
6534         int  idx, ret;
6535         uint8_t filter_idx;
6536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6537
6538         idx = i40e_get_vxlan_port_idx(pf, port);
6539
6540         /* Check if port already exists */
6541         if (idx >= 0) {
6542                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6543                 return -EINVAL;
6544         }
6545
6546         /* Now check if there is space to add the new port */
6547         idx = i40e_get_vxlan_port_idx(pf, 0);
6548         if (idx < 0) {
6549                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6550                         "not adding port %d", port);
6551                 return -ENOSPC;
6552         }
6553
6554         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6555                                         &filter_idx, NULL);
6556         if (ret < 0) {
6557                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6558                 return -1;
6559         }
6560
6561         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6562                          port,  filter_idx);
6563
6564         /* New port: add it and mark its index in the bitmap */
6565         pf->vxlan_ports[idx] = port;
6566         pf->vxlan_bitmap |= (1 << idx);
6567
6568         if (!(pf->flags & I40E_FLAG_VXLAN))
6569                 pf->flags |= I40E_FLAG_VXLAN;
6570
6571         return 0;
6572 }
6573
6574 static int
6575 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6576 {
6577         int idx;
6578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6579
6580         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6581                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6582                 return -EINVAL;
6583         }
6584
6585         idx = i40e_get_vxlan_port_idx(pf, port);
6586
6587         if (idx < 0) {
6588                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6589                 return -EINVAL;
6590         }
6591
6592         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6593                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6594                 return -1;
6595         }
6596
6597         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6598                         port, idx);
6599
6600         pf->vxlan_ports[idx] = 0;
6601         pf->vxlan_bitmap &= ~(1 << idx);
6602
6603         if (!pf->vxlan_bitmap)
6604                 pf->flags &= ~I40E_FLAG_VXLAN;
6605
6606         return 0;
6607 }
6608
6609 /* Add UDP tunneling port */
6610 static int
6611 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6612                              struct rte_eth_udp_tunnel *udp_tunnel)
6613 {
6614         int ret = 0;
6615         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6616
6617         if (udp_tunnel == NULL)
6618                 return -EINVAL;
6619
6620         switch (udp_tunnel->prot_type) {
6621         case RTE_TUNNEL_TYPE_VXLAN:
6622                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6623                 break;
6624
6625         case RTE_TUNNEL_TYPE_GENEVE:
6626         case RTE_TUNNEL_TYPE_TEREDO:
6627                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6628                 ret = -1;
6629                 break;
6630
6631         default:
6632                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6633                 ret = -1;
6634                 break;
6635         }
6636
6637         return ret;
6638 }
6639
6640 /* Remove UDP tunneling port */
6641 static int
6642 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6643                              struct rte_eth_udp_tunnel *udp_tunnel)
6644 {
6645         int ret = 0;
6646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6647
6648         if (udp_tunnel == NULL)
6649                 return -EINVAL;
6650
6651         switch (udp_tunnel->prot_type) {
6652         case RTE_TUNNEL_TYPE_VXLAN:
6653                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6654                 break;
6655         case RTE_TUNNEL_TYPE_GENEVE:
6656         case RTE_TUNNEL_TYPE_TEREDO:
6657                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6658                 ret = -1;
6659                 break;
6660         default:
6661                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6662                 ret = -1;
6663                 break;
6664         }
6665
6666         return ret;
6667 }
6668
6669 /* Calculate the maximum number of contiguous PF queues that are configured */
6670 static int
6671 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6672 {
6673         struct rte_eth_dev_data *data = pf->dev_data;
6674         int i, num;
6675         struct i40e_rx_queue *rxq;
6676
6677         num = 0;
6678         for (i = 0; i < pf->lan_nb_qps; i++) {
6679                 rxq = data->rx_queues[i];
6680                 if (rxq && rxq->q_set)
6681                         num++;
6682                 else
6683                         break;
6684         }
6685
6686         return num;
6687 }
6688
6689 /* Configure RSS */
6690 static int
6691 i40e_pf_config_rss(struct i40e_pf *pf)
6692 {
6693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6694         struct rte_eth_rss_conf rss_conf;
6695         uint32_t i, lut = 0;
6696         uint16_t j, num;
6697
6698         /*
6699          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6700          * It's necessary to calulate the actual PF queues that are configured.
6701          */
6702         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6703                 num = i40e_pf_calc_configured_queues_num(pf);
6704         else
6705                 num = pf->dev_data->nb_rx_queues;
6706
6707         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6708         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6709                         num);
6710
6711         if (num == 0) {
6712                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6713                 return -ENOTSUP;
6714         }
6715
6716         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6717                 if (j == num)
6718                         j = 0;
6719                 lut = (lut << 8) | (j & ((0x1 <<
6720                         hw->func_caps.rss_table_entry_width) - 1));
6721                 if ((i & 3) == 3)
6722                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6723         }
6724
6725         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6726         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6727                 i40e_pf_disable_rss(pf);
6728                 return 0;
6729         }
6730         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6731                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6732                 /* Random default keys */
6733                 static uint32_t rss_key_default[] = {0x6b793944,
6734                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6735                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6736                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6737
6738                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6739                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6740                                                         sizeof(uint32_t);
6741         }
6742
6743         return i40e_hw_rss_hash_set(pf, &rss_conf);
6744 }
6745
6746 static int
6747 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6748                                struct rte_eth_tunnel_filter_conf *filter)
6749 {
6750         if (pf == NULL || filter == NULL) {
6751                 PMD_DRV_LOG(ERR, "Invalid parameter");
6752                 return -EINVAL;
6753         }
6754
6755         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6756                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6757                 return -EINVAL;
6758         }
6759
6760         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6761                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6762                 return -EINVAL;
6763         }
6764
6765         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6766                 (is_zero_ether_addr(&filter->outer_mac))) {
6767                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6768                 return -EINVAL;
6769         }
6770
6771         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6772                 (is_zero_ether_addr(&filter->inner_mac))) {
6773                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6774                 return -EINVAL;
6775         }
6776
6777         return 0;
6778 }
6779
6780 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6781 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6782 static int
6783 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6784 {
6785         uint32_t val, reg;
6786         int ret = -EINVAL;
6787
6788         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6789         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6790
6791         if (len == 3) {
6792                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6793         } else if (len == 4) {
6794                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6795         } else {
6796                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6797                 return ret;
6798         }
6799
6800         if (reg != val) {
6801                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6802                                                    reg, NULL);
6803                 if (ret != 0)
6804                         return ret;
6805         } else {
6806                 ret = 0;
6807         }
6808         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6809                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6810
6811         return ret;
6812 }
6813
6814 static int
6815 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6816 {
6817         int ret = -EINVAL;
6818
6819         if (!hw || !cfg)
6820                 return -EINVAL;
6821
6822         switch (cfg->cfg_type) {
6823         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6824                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6825                 break;
6826         default:
6827                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6828                 break;
6829         }
6830
6831         return ret;
6832 }
6833
6834 static int
6835 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6836                                enum rte_filter_op filter_op,
6837                                void *arg)
6838 {
6839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6840         int ret = I40E_ERR_PARAM;
6841
6842         switch (filter_op) {
6843         case RTE_ETH_FILTER_SET:
6844                 ret = i40e_dev_global_config_set(hw,
6845                         (struct rte_eth_global_cfg *)arg);
6846                 break;
6847         default:
6848                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6849                 break;
6850         }
6851
6852         return ret;
6853 }
6854
6855 static int
6856 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6857                           enum rte_filter_op filter_op,
6858                           void *arg)
6859 {
6860         struct rte_eth_tunnel_filter_conf *filter;
6861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6862         int ret = I40E_SUCCESS;
6863
6864         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6865
6866         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6867                 return I40E_ERR_PARAM;
6868
6869         switch (filter_op) {
6870         case RTE_ETH_FILTER_NOP:
6871                 if (!(pf->flags & I40E_FLAG_VXLAN))
6872                         ret = I40E_NOT_SUPPORTED;
6873                 break;
6874         case RTE_ETH_FILTER_ADD:
6875                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6876                 break;
6877         case RTE_ETH_FILTER_DELETE:
6878                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6879                 break;
6880         default:
6881                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6882                 ret = I40E_ERR_PARAM;
6883                 break;
6884         }
6885
6886         return ret;
6887 }
6888
6889 static int
6890 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6891 {
6892         int ret = 0;
6893         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6894
6895         /* RSS setup */
6896         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6897                 ret = i40e_pf_config_rss(pf);
6898         else
6899                 i40e_pf_disable_rss(pf);
6900
6901         return ret;
6902 }
6903
6904 /* Get the symmetric hash enable configurations per port */
6905 static void
6906 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6907 {
6908         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6909
6910         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6911 }
6912
6913 /* Set the symmetric hash enable configurations per port */
6914 static void
6915 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6916 {
6917         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6918
6919         if (enable > 0) {
6920                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6921                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6922                                                         "been enabled");
6923                         return;
6924                 }
6925                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6926         } else {
6927                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6928                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6929                                                         "been disabled");
6930                         return;
6931                 }
6932                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6933         }
6934         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6935         I40E_WRITE_FLUSH(hw);
6936 }
6937
6938 /*
6939  * Get global configurations of hash function type and symmetric hash enable
6940  * per flow type (pctype). Note that global configuration means it affects all
6941  * the ports on the same NIC.
6942  */
6943 static int
6944 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6945                                    struct rte_eth_hash_global_conf *g_cfg)
6946 {
6947         uint32_t reg, mask = I40E_FLOW_TYPES;
6948         uint16_t i;
6949         enum i40e_filter_pctype pctype;
6950
6951         memset(g_cfg, 0, sizeof(*g_cfg));
6952         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6953         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6954                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6955         else
6956                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6957         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6958                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6959
6960         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6961                 if (!(mask & (1UL << i)))
6962                         continue;
6963                 mask &= ~(1UL << i);
6964                 /* Bit set indicats the coresponding flow type is supported */
6965                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6966                 /* if flowtype is invalid, continue */
6967                 if (!I40E_VALID_FLOW(i))
6968                         continue;
6969                 pctype = i40e_flowtype_to_pctype(i);
6970                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6971                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6972                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6973         }
6974
6975         return 0;
6976 }
6977
6978 static int
6979 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6980 {
6981         uint32_t i;
6982         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6983
6984         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6985                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6986                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6987                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6988                                                 g_cfg->hash_func);
6989                 return -EINVAL;
6990         }
6991
6992         /*
6993          * As i40e supports less than 32 flow types, only first 32 bits need to
6994          * be checked.
6995          */
6996         mask0 = g_cfg->valid_bit_mask[0];
6997         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6998                 if (i == 0) {
6999                         /* Check if any unsupported flow type configured */
7000                         if ((mask0 | i40e_mask) ^ i40e_mask)
7001                                 goto mask_err;
7002                 } else {
7003                         if (g_cfg->valid_bit_mask[i])
7004                                 goto mask_err;
7005                 }
7006         }
7007
7008         return 0;
7009
7010 mask_err:
7011         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7012
7013         return -EINVAL;
7014 }
7015
7016 /*
7017  * Set global configurations of hash function type and symmetric hash enable
7018  * per flow type (pctype). Note any modifying global configuration will affect
7019  * all the ports on the same NIC.
7020  */
7021 static int
7022 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7023                                    struct rte_eth_hash_global_conf *g_cfg)
7024 {
7025         int ret;
7026         uint16_t i;
7027         uint32_t reg;
7028         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7029         enum i40e_filter_pctype pctype;
7030
7031         /* Check the input parameters */
7032         ret = i40e_hash_global_config_check(g_cfg);
7033         if (ret < 0)
7034                 return ret;
7035
7036         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7037                 if (!(mask0 & (1UL << i)))
7038                         continue;
7039                 mask0 &= ~(1UL << i);
7040                 /* if flowtype is invalid, continue */
7041                 if (!I40E_VALID_FLOW(i))
7042                         continue;
7043                 pctype = i40e_flowtype_to_pctype(i);
7044                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7045                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7046                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7047         }
7048
7049         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7050         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7051                 /* Toeplitz */
7052                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7053                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7054                                                                 "Toeplitz");
7055                         goto out;
7056                 }
7057                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7058         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7059                 /* Simple XOR */
7060                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7061                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7062                                                         "Simple XOR");
7063                         goto out;
7064                 }
7065                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7066         } else
7067                 /* Use the default, and keep it as it is */
7068                 goto out;
7069
7070         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7071
7072 out:
7073         I40E_WRITE_FLUSH(hw);
7074
7075         return 0;
7076 }
7077
7078 /**
7079  * Valid input sets for hash and flow director filters per PCTYPE
7080  */
7081 static uint64_t
7082 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7083                 enum rte_filter_type filter)
7084 {
7085         uint64_t valid;
7086
7087         static const uint64_t valid_hash_inset_table[] = {
7088                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7092                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7093                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7094                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7095                         I40E_INSET_FLEX_PAYLOAD,
7096                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7100                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7101                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7102                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7103                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7104                         I40E_INSET_FLEX_PAYLOAD,
7105 #ifdef X722_SUPPORT
7106                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7110                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7111                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7112                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7113                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7114                         I40E_INSET_FLEX_PAYLOAD,
7115                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7116                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7117                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7118                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7119                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7120                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7121                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7122                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7123                         I40E_INSET_FLEX_PAYLOAD,
7124 #endif
7125                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7129                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7130                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7131                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7132                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7133                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7134 #ifdef X722_SUPPORT
7135                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7136                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7137                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7138                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7139                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7140                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7141                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7142                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7143                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7144 #endif
7145                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7146                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7147                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7148                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7149                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7150                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7151                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7152                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7153                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7154                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7158                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7159                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7160                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7161                         I40E_INSET_FLEX_PAYLOAD,
7162                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7163                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7164                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7165                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7166                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7167                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7168                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7169                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7170                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7171                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7172                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7173                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7174                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7175                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7176                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7177                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7178 #ifdef X722_SUPPORT
7179                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7180                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7181                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7182                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7183                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7184                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7185                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7186                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7187                         I40E_INSET_FLEX_PAYLOAD,
7188                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7192                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7193                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7194                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7195                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7196                         I40E_INSET_FLEX_PAYLOAD,
7197 #endif
7198                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7199                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7200                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7201                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7202                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7203                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7204                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7205                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7206                         I40E_INSET_FLEX_PAYLOAD,
7207 #ifdef X722_SUPPORT
7208                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7209                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7210                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7211                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7212                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7213                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7214                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7215                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7216                         I40E_INSET_FLEX_PAYLOAD,
7217 #endif
7218                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7219                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7220                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7221                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7222                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7223                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7224                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7225                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7226                         I40E_INSET_FLEX_PAYLOAD,
7227                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7228                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7229                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7230                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7231                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7232                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7233                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7234                         I40E_INSET_FLEX_PAYLOAD,
7235                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7236                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7237                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7238                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7239                         I40E_INSET_FLEX_PAYLOAD,
7240         };
7241
7242         /**
7243          * Flow director supports only fields defined in
7244          * union rte_eth_fdir_flow.
7245          */
7246         static const uint64_t valid_fdir_inset_table[] = {
7247                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7248                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7249                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7250                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7251                 I40E_INSET_IPV4_TTL,
7252                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7253                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7254                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7255                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7256                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7257 #ifdef X722_SUPPORT
7258                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7259                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7260                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7261                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7262                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7263                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7264                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7265                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7266                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7267                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7268 #endif
7269                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7270                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7271                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7272                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7273                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7274 #ifdef X722_SUPPORT
7275                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7276                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7277                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7278                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7279                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7280 #endif
7281                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7286                 I40E_INSET_SCTP_VT,
7287                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7288                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7289                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7290                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7291                 I40E_INSET_IPV4_TTL,
7292                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7293                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7294                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7295                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7296                 I40E_INSET_IPV6_HOP_LIMIT,
7297                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7298                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7299                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7300                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7301                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7302 #ifdef X722_SUPPORT
7303                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7304                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7305                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7306                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7307                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7308                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7309                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7310                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7311                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7312                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7313 #endif
7314                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7315                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7316                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7317                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7318                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7319 #ifdef X722_SUPPORT
7320                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7321                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7322                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7323                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7324                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7325 #endif
7326                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7327                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7328                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7329                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7330                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7331                 I40E_INSET_SCTP_VT,
7332                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7333                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7334                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7335                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7336                 I40E_INSET_IPV6_HOP_LIMIT,
7337                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7339                 I40E_INSET_LAST_ETHER_TYPE,
7340         };
7341
7342         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7343                 return 0;
7344         if (filter == RTE_ETH_FILTER_HASH)
7345                 valid = valid_hash_inset_table[pctype];
7346         else
7347                 valid = valid_fdir_inset_table[pctype];
7348
7349         return valid;
7350 }
7351
7352 /**
7353  * Validate if the input set is allowed for a specific PCTYPE
7354  */
7355 static int
7356 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7357                 enum rte_filter_type filter, uint64_t inset)
7358 {
7359         uint64_t valid;
7360
7361         valid = i40e_get_valid_input_set(pctype, filter);
7362         if (inset & (~valid))
7363                 return -EINVAL;
7364
7365         return 0;
7366 }
7367
7368 /* default input set fields combination per pctype */
7369 static uint64_t
7370 i40e_get_default_input_set(uint16_t pctype)
7371 {
7372         static const uint64_t default_inset_table[] = {
7373                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7374                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7375                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7376                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7377                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7378 #ifdef X722_SUPPORT
7379                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7380                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7381                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7382                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7383                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7384                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7385 #endif
7386                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7387                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7388                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7389 #ifdef X722_SUPPORT
7390                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7391                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7393 #endif
7394                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7395                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7397                         I40E_INSET_SCTP_VT,
7398                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7399                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7400                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7401                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7402                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7403                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7404                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7405 #ifdef X722_SUPPORT
7406                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7407                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7408                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7409                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7410                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7411                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7412 #endif
7413                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7414                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7415                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7416 #ifdef X722_SUPPORT
7417                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7418                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7419                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7420 #endif
7421                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7422                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7423                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7424                         I40E_INSET_SCTP_VT,
7425                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7426                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7427                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7428                         I40E_INSET_LAST_ETHER_TYPE,
7429         };
7430
7431         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7432                 return 0;
7433
7434         return default_inset_table[pctype];
7435 }
7436
7437 /**
7438  * Parse the input set from index to logical bit masks
7439  */
7440 static int
7441 i40e_parse_input_set(uint64_t *inset,
7442                      enum i40e_filter_pctype pctype,
7443                      enum rte_eth_input_set_field *field,
7444                      uint16_t size)
7445 {
7446         uint16_t i, j;
7447         int ret = -EINVAL;
7448
7449         static const struct {
7450                 enum rte_eth_input_set_field field;
7451                 uint64_t inset;
7452         } inset_convert_table[] = {
7453                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7454                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7455                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7456                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7457                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7458                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7459                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7460                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7461                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7462                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7463                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7464                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7465                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7466                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7467                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7468                         I40E_INSET_IPV6_NEXT_HDR},
7469                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7470                         I40E_INSET_IPV6_HOP_LIMIT},
7471                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7472                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7473                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7474                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7475                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7476                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7477                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7478                         I40E_INSET_SCTP_VT},
7479                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7480                         I40E_INSET_TUNNEL_DMAC},
7481                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7482                         I40E_INSET_VLAN_TUNNEL},
7483                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7484                         I40E_INSET_TUNNEL_ID},
7485                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7486                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7487                         I40E_INSET_FLEX_PAYLOAD_W1},
7488                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7489                         I40E_INSET_FLEX_PAYLOAD_W2},
7490                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7491                         I40E_INSET_FLEX_PAYLOAD_W3},
7492                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7493                         I40E_INSET_FLEX_PAYLOAD_W4},
7494                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7495                         I40E_INSET_FLEX_PAYLOAD_W5},
7496                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7497                         I40E_INSET_FLEX_PAYLOAD_W6},
7498                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7499                         I40E_INSET_FLEX_PAYLOAD_W7},
7500                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7501                         I40E_INSET_FLEX_PAYLOAD_W8},
7502         };
7503
7504         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7505                 return ret;
7506
7507         /* Only one item allowed for default or all */
7508         if (size == 1) {
7509                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7510                         *inset = i40e_get_default_input_set(pctype);
7511                         return 0;
7512                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7513                         *inset = I40E_INSET_NONE;
7514                         return 0;
7515                 }
7516         }
7517
7518         for (i = 0, *inset = 0; i < size; i++) {
7519                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7520                         if (field[i] == inset_convert_table[j].field) {
7521                                 *inset |= inset_convert_table[j].inset;
7522                                 break;
7523                         }
7524                 }
7525
7526                 /* It contains unsupported input set, return immediately */
7527                 if (j == RTE_DIM(inset_convert_table))
7528                         return ret;
7529         }
7530
7531         return 0;
7532 }
7533
7534 /**
7535  * Translate the input set from bit masks to register aware bit masks
7536  * and vice versa
7537  */
7538 static uint64_t
7539 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7540 {
7541         uint64_t val = 0;
7542         uint16_t i;
7543
7544         struct inset_map {
7545                 uint64_t inset;
7546                 uint64_t inset_reg;
7547         };
7548
7549         static const struct inset_map inset_map_common[] = {
7550                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7551                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7552                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7553                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7554                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7555                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7556                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7557                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7558                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7559                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7560                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7561                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7562                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7563                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7564                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7565                 {I40E_INSET_TUNNEL_DMAC,
7566                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7567                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7568                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7569                 {I40E_INSET_TUNNEL_SRC_PORT,
7570                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7571                 {I40E_INSET_TUNNEL_DST_PORT,
7572                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7573                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7574                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7575                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7576                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7577                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7578                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7579                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7580                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7581                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7582         };
7583
7584     /* some different registers map in x722*/
7585         static const struct inset_map inset_map_diff_x722[] = {
7586                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7587                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7588                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7589                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7590         };
7591
7592         static const struct inset_map inset_map_diff_not_x722[] = {
7593                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7594                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7595                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7596                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7597         };
7598
7599         if (input == 0)
7600                 return val;
7601
7602         /* Translate input set to register aware inset */
7603         if (type == I40E_MAC_X722) {
7604                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7605                         if (input & inset_map_diff_x722[i].inset)
7606                                 val |= inset_map_diff_x722[i].inset_reg;
7607                 }
7608         } else {
7609                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7610                         if (input & inset_map_diff_not_x722[i].inset)
7611                                 val |= inset_map_diff_not_x722[i].inset_reg;
7612                 }
7613         }
7614
7615         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7616                 if (input & inset_map_common[i].inset)
7617                         val |= inset_map_common[i].inset_reg;
7618         }
7619
7620         return val;
7621 }
7622
7623 static int
7624 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7625 {
7626         uint8_t i, idx = 0;
7627         uint64_t inset_need_mask = inset;
7628
7629         static const struct {
7630                 uint64_t inset;
7631                 uint32_t mask;
7632         } inset_mask_map[] = {
7633                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7634                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7635                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7636                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7637                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7638                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7639                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7640                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7641         };
7642
7643         if (!inset || !mask || !nb_elem)
7644                 return 0;
7645
7646         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7647                 /* Clear the inset bit, if no MASK is required,
7648                  * for example proto + ttl
7649                  */
7650                 if ((inset & inset_mask_map[i].inset) ==
7651                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7652                         inset_need_mask &= ~inset_mask_map[i].inset;
7653                 if (!inset_need_mask)
7654                         return 0;
7655         }
7656         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7657                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7658                     inset_mask_map[i].inset) {
7659                         if (idx >= nb_elem) {
7660                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7661                                 return -EINVAL;
7662                         }
7663                         mask[idx] = inset_mask_map[i].mask;
7664                         idx++;
7665                 }
7666         }
7667
7668         return idx;
7669 }
7670
7671 static void
7672 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7673 {
7674         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7675
7676         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7677         if (reg != val)
7678                 i40e_write_rx_ctl(hw, addr, val);
7679         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7680                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7681 }
7682
7683 static void
7684 i40e_filter_input_set_init(struct i40e_pf *pf)
7685 {
7686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7687         enum i40e_filter_pctype pctype;
7688         uint64_t input_set, inset_reg;
7689         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7690         int num, i;
7691
7692         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7693              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7694                 if (hw->mac.type == I40E_MAC_X722) {
7695                         if (!I40E_VALID_PCTYPE_X722(pctype))
7696                                 continue;
7697                 } else {
7698                         if (!I40E_VALID_PCTYPE(pctype))
7699                                 continue;
7700                 }
7701
7702                 input_set = i40e_get_default_input_set(pctype);
7703
7704                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7705                                                    I40E_INSET_MASK_NUM_REG);
7706                 if (num < 0)
7707                         return;
7708                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7709                                         input_set);
7710
7711                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7712                                       (uint32_t)(inset_reg & UINT32_MAX));
7713                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7714                                      (uint32_t)((inset_reg >>
7715                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7716                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7717                                       (uint32_t)(inset_reg & UINT32_MAX));
7718                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7719                                      (uint32_t)((inset_reg >>
7720                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7721
7722                 for (i = 0; i < num; i++) {
7723                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7724                                              mask_reg[i]);
7725                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7726                                              mask_reg[i]);
7727                 }
7728                 /*clear unused mask registers of the pctype */
7729                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7730                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7731                                              0);
7732                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7733                                              0);
7734                 }
7735                 I40E_WRITE_FLUSH(hw);
7736
7737                 /* store the default input set */
7738                 pf->hash_input_set[pctype] = input_set;
7739                 pf->fdir.input_set[pctype] = input_set;
7740         }
7741 }
7742
7743 int
7744 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7745                          struct rte_eth_input_set_conf *conf)
7746 {
7747         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7748         enum i40e_filter_pctype pctype;
7749         uint64_t input_set, inset_reg = 0;
7750         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7751         int ret, i, num;
7752
7753         if (!conf) {
7754                 PMD_DRV_LOG(ERR, "Invalid pointer");
7755                 return -EFAULT;
7756         }
7757         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7758             conf->op != RTE_ETH_INPUT_SET_ADD) {
7759                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7760                 return -EINVAL;
7761         }
7762
7763         if (!I40E_VALID_FLOW(conf->flow_type)) {
7764                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7765                 return -EINVAL;
7766         }
7767
7768         if (hw->mac.type == I40E_MAC_X722) {
7769                 /* get translated pctype value in fd pctype register */
7770                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7771                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7772                         conf->flow_type)));
7773         } else
7774                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7775
7776         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7777                                    conf->inset_size);
7778         if (ret) {
7779                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7780                 return -EINVAL;
7781         }
7782         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7783                                     input_set) != 0) {
7784                 PMD_DRV_LOG(ERR, "Invalid input set");
7785                 return -EINVAL;
7786         }
7787         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7788                 /* get inset value in register */
7789                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7790                 inset_reg <<= I40E_32_BIT_WIDTH;
7791                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7792                 input_set |= pf->hash_input_set[pctype];
7793         }
7794         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7795                                            I40E_INSET_MASK_NUM_REG);
7796         if (num < 0)
7797                 return -EINVAL;
7798
7799         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7800
7801         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7802                               (uint32_t)(inset_reg & UINT32_MAX));
7803         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7804                              (uint32_t)((inset_reg >>
7805                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7806
7807         for (i = 0; i < num; i++)
7808                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7809                                      mask_reg[i]);
7810         /*clear unused mask registers of the pctype */
7811         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7812                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7813                                      0);
7814         I40E_WRITE_FLUSH(hw);
7815
7816         pf->hash_input_set[pctype] = input_set;
7817         return 0;
7818 }
7819
7820 int
7821 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7822                          struct rte_eth_input_set_conf *conf)
7823 {
7824         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7825         enum i40e_filter_pctype pctype;
7826         uint64_t input_set, inset_reg = 0;
7827         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7828         int ret, i, num;
7829
7830         if (!hw || !conf) {
7831                 PMD_DRV_LOG(ERR, "Invalid pointer");
7832                 return -EFAULT;
7833         }
7834         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7835             conf->op != RTE_ETH_INPUT_SET_ADD) {
7836                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7837                 return -EINVAL;
7838         }
7839
7840         if (!I40E_VALID_FLOW(conf->flow_type)) {
7841                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7842                 return -EINVAL;
7843         }
7844
7845         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7846
7847         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7848                                    conf->inset_size);
7849         if (ret) {
7850                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7851                 return -EINVAL;
7852         }
7853         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7854                                     input_set) != 0) {
7855                 PMD_DRV_LOG(ERR, "Invalid input set");
7856                 return -EINVAL;
7857         }
7858
7859         /* get inset value in register */
7860         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7861         inset_reg <<= I40E_32_BIT_WIDTH;
7862         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7863
7864         /* Can not change the inset reg for flex payload for fdir,
7865          * it is done by writing I40E_PRTQF_FD_FLXINSET
7866          * in i40e_set_flex_mask_on_pctype.
7867          */
7868         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7869                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7870         else
7871                 input_set |= pf->fdir.input_set[pctype];
7872         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7873                                            I40E_INSET_MASK_NUM_REG);
7874         if (num < 0)
7875                 return -EINVAL;
7876
7877         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7878
7879         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7880                               (uint32_t)(inset_reg & UINT32_MAX));
7881         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7882                              (uint32_t)((inset_reg >>
7883                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7884
7885         for (i = 0; i < num; i++)
7886                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7887                                      mask_reg[i]);
7888         /*clear unused mask registers of the pctype */
7889         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7890                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7891                                      0);
7892         I40E_WRITE_FLUSH(hw);
7893
7894         pf->fdir.input_set[pctype] = input_set;
7895         return 0;
7896 }
7897
7898 static int
7899 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7900 {
7901         int ret = 0;
7902
7903         if (!hw || !info) {
7904                 PMD_DRV_LOG(ERR, "Invalid pointer");
7905                 return -EFAULT;
7906         }
7907
7908         switch (info->info_type) {
7909         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7910                 i40e_get_symmetric_hash_enable_per_port(hw,
7911                                         &(info->info.enable));
7912                 break;
7913         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7914                 ret = i40e_get_hash_filter_global_config(hw,
7915                                 &(info->info.global_conf));
7916                 break;
7917         default:
7918                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7919                                                         info->info_type);
7920                 ret = -EINVAL;
7921                 break;
7922         }
7923
7924         return ret;
7925 }
7926
7927 static int
7928 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7929 {
7930         int ret = 0;
7931
7932         if (!hw || !info) {
7933                 PMD_DRV_LOG(ERR, "Invalid pointer");
7934                 return -EFAULT;
7935         }
7936
7937         switch (info->info_type) {
7938         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7939                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7940                 break;
7941         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7942                 ret = i40e_set_hash_filter_global_config(hw,
7943                                 &(info->info.global_conf));
7944                 break;
7945         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7946                 ret = i40e_hash_filter_inset_select(hw,
7947                                                &(info->info.input_set_conf));
7948                 break;
7949
7950         default:
7951                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7952                                                         info->info_type);
7953                 ret = -EINVAL;
7954                 break;
7955         }
7956
7957         return ret;
7958 }
7959
7960 /* Operations for hash function */
7961 static int
7962 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7963                       enum rte_filter_op filter_op,
7964                       void *arg)
7965 {
7966         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7967         int ret = 0;
7968
7969         switch (filter_op) {
7970         case RTE_ETH_FILTER_NOP:
7971                 break;
7972         case RTE_ETH_FILTER_GET:
7973                 ret = i40e_hash_filter_get(hw,
7974                         (struct rte_eth_hash_filter_info *)arg);
7975                 break;
7976         case RTE_ETH_FILTER_SET:
7977                 ret = i40e_hash_filter_set(hw,
7978                         (struct rte_eth_hash_filter_info *)arg);
7979                 break;
7980         default:
7981                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7982                                                                 filter_op);
7983                 ret = -ENOTSUP;
7984                 break;
7985         }
7986
7987         return ret;
7988 }
7989
7990 /*
7991  * Configure ethertype filter, which can director packet by filtering
7992  * with mac address and ether_type or only ether_type
7993  */
7994 static int
7995 i40e_ethertype_filter_set(struct i40e_pf *pf,
7996                         struct rte_eth_ethertype_filter *filter,
7997                         bool add)
7998 {
7999         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8000         struct i40e_control_filter_stats stats;
8001         uint16_t flags = 0;
8002         int ret;
8003
8004         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8005                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8006                 return -EINVAL;
8007         }
8008         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8009                 filter->ether_type == ETHER_TYPE_IPv6) {
8010                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8011                         " control packet filter.", filter->ether_type);
8012                 return -EINVAL;
8013         }
8014         if (filter->ether_type == ETHER_TYPE_VLAN)
8015                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8016                         " not supported.");
8017
8018         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8019                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8020         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8021                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8022         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8023
8024         memset(&stats, 0, sizeof(stats));
8025         ret = i40e_aq_add_rem_control_packet_filter(hw,
8026                         filter->mac_addr.addr_bytes,
8027                         filter->ether_type, flags,
8028                         pf->main_vsi->seid,
8029                         filter->queue, add, &stats, NULL);
8030
8031         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8032                          " mac_etype_used = %u, etype_used = %u,"
8033                          " mac_etype_free = %u, etype_free = %u\n",
8034                          ret, stats.mac_etype_used, stats.etype_used,
8035                          stats.mac_etype_free, stats.etype_free);
8036         if (ret < 0)
8037                 return -ENOSYS;
8038         return 0;
8039 }
8040
8041 /*
8042  * Handle operations for ethertype filter.
8043  */
8044 static int
8045 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8046                                 enum rte_filter_op filter_op,
8047                                 void *arg)
8048 {
8049         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8050         int ret = 0;
8051
8052         if (filter_op == RTE_ETH_FILTER_NOP)
8053                 return ret;
8054
8055         if (arg == NULL) {
8056                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8057                             filter_op);
8058                 return -EINVAL;
8059         }
8060
8061         switch (filter_op) {
8062         case RTE_ETH_FILTER_ADD:
8063                 ret = i40e_ethertype_filter_set(pf,
8064                         (struct rte_eth_ethertype_filter *)arg,
8065                         TRUE);
8066                 break;
8067         case RTE_ETH_FILTER_DELETE:
8068                 ret = i40e_ethertype_filter_set(pf,
8069                         (struct rte_eth_ethertype_filter *)arg,
8070                         FALSE);
8071                 break;
8072         default:
8073                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8074                 ret = -ENOSYS;
8075                 break;
8076         }
8077         return ret;
8078 }
8079
8080 static int
8081 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8082                      enum rte_filter_type filter_type,
8083                      enum rte_filter_op filter_op,
8084                      void *arg)
8085 {
8086         int ret = 0;
8087
8088         if (dev == NULL)
8089                 return -EINVAL;
8090
8091         switch (filter_type) {
8092         case RTE_ETH_FILTER_NONE:
8093                 /* For global configuration */
8094                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8095                 break;
8096         case RTE_ETH_FILTER_HASH:
8097                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8098                 break;
8099         case RTE_ETH_FILTER_MACVLAN:
8100                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8101                 break;
8102         case RTE_ETH_FILTER_ETHERTYPE:
8103                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8104                 break;
8105         case RTE_ETH_FILTER_TUNNEL:
8106                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8107                 break;
8108         case RTE_ETH_FILTER_FDIR:
8109                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8110                 break;
8111         default:
8112                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8113                                                         filter_type);
8114                 ret = -EINVAL;
8115                 break;
8116         }
8117
8118         return ret;
8119 }
8120
8121 /*
8122  * Check and enable Extended Tag.
8123  * Enabling Extended Tag is important for 40G performance.
8124  */
8125 static void
8126 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8127 {
8128         uint32_t buf = 0;
8129         int ret;
8130
8131         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8132                                       PCI_DEV_CAP_REG);
8133         if (ret < 0) {
8134                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8135                             PCI_DEV_CAP_REG);
8136                 return;
8137         }
8138         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8139                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8140                 return;
8141         }
8142
8143         buf = 0;
8144         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8145                                       PCI_DEV_CTRL_REG);
8146         if (ret < 0) {
8147                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8148                             PCI_DEV_CTRL_REG);
8149                 return;
8150         }
8151         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8152                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8153                 return;
8154         }
8155         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8156         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8157                                        PCI_DEV_CTRL_REG);
8158         if (ret < 0) {
8159                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8160                             PCI_DEV_CTRL_REG);
8161                 return;
8162         }
8163 }
8164
8165 /*
8166  * As some registers wouldn't be reset unless a global hardware reset,
8167  * hardware initialization is needed to put those registers into an
8168  * expected initial state.
8169  */
8170 static void
8171 i40e_hw_init(struct rte_eth_dev *dev)
8172 {
8173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8174
8175         i40e_enable_extended_tag(dev);
8176
8177         /* clear the PF Queue Filter control register */
8178         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8179
8180         /* Disable symmetric hash per port */
8181         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8182 }
8183
8184 enum i40e_filter_pctype
8185 i40e_flowtype_to_pctype(uint16_t flow_type)
8186 {
8187         static const enum i40e_filter_pctype pctype_table[] = {
8188                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8189                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8190                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8191                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8192                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8193                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8194                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8195                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8196                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8197                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8198                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8199                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8200                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8201                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8202                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8203                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8204                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8205                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8206                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8207         };
8208
8209         return pctype_table[flow_type];
8210 }
8211
8212 uint16_t
8213 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8214 {
8215         static const uint16_t flowtype_table[] = {
8216                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8217                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8218                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8219 #ifdef X722_SUPPORT
8220                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8221                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8222                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8223                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8224 #endif
8225                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8226                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8227 #ifdef X722_SUPPORT
8228                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8229                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8230 #endif
8231                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8232                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8233                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8234                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8235                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8236                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8237                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8238 #ifdef X722_SUPPORT
8239                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8240                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8241                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8242                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8243 #endif
8244                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8245                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8246 #ifdef X722_SUPPORT
8247                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8248                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8249 #endif
8250                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8251                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8252                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8253                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8254                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8255         };
8256
8257         return flowtype_table[pctype];
8258 }
8259
8260 /*
8261  * On X710, performance number is far from the expectation on recent firmware
8262  * versions; on XL710, performance number is also far from the expectation on
8263  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8264  * mode is enabled and port MAC address is equal to the packet destination MAC
8265  * address. The fix for this issue may not be integrated in the following
8266  * firmware version. So the workaround in software driver is needed. It needs
8267  * to modify the initial values of 3 internal only registers for both X710 and
8268  * XL710. Note that the values for X710 or XL710 could be different, and the
8269  * workaround can be removed when it is fixed in firmware in the future.
8270  */
8271
8272 /* For both X710 and XL710 */
8273 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8274 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8275
8276 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8277 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8278
8279 /* For X710 */
8280 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8281 /* For XL710 */
8282 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8283 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8284
8285 static int
8286 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8287 {
8288         enum i40e_status_code status;
8289         struct i40e_aq_get_phy_abilities_resp phy_ab;
8290         int ret = -ENOTSUP;
8291
8292         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8293                                               NULL);
8294
8295         if (status)
8296                 return ret;
8297
8298         return 0;
8299 }
8300
8301
8302 static void
8303 i40e_configure_registers(struct i40e_hw *hw)
8304 {
8305         static struct {
8306                 uint32_t addr;
8307                 uint64_t val;
8308         } reg_table[] = {
8309                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8310                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8311                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8312         };
8313         uint64_t reg;
8314         uint32_t i;
8315         int ret;
8316
8317         for (i = 0; i < RTE_DIM(reg_table); i++) {
8318                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8319                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8320                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8321                                 reg_table[i].val =
8322                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8323                         else /* For X710 */
8324                                 reg_table[i].val =
8325                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8326                 }
8327
8328                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8329                                                         &reg, NULL);
8330                 if (ret < 0) {
8331                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8332                                                         reg_table[i].addr);
8333                         break;
8334                 }
8335                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8336                                                 reg_table[i].addr, reg);
8337                 if (reg == reg_table[i].val)
8338                         continue;
8339
8340                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8341                                                 reg_table[i].val, NULL);
8342                 if (ret < 0) {
8343                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8344                                 "address of 0x%"PRIx32, reg_table[i].val,
8345                                                         reg_table[i].addr);
8346                         break;
8347                 }
8348                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8349                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8350         }
8351 }
8352
8353 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8354 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8355 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8356 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8357 static int
8358 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8359 {
8360         uint32_t reg;
8361         int ret;
8362
8363         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8364                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8365                 return -EINVAL;
8366         }
8367
8368         /* Configure for double VLAN RX stripping */
8369         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8370         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8371                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8372                 ret = i40e_aq_debug_write_register(hw,
8373                                                    I40E_VSI_TSR(vsi->vsi_id),
8374                                                    reg, NULL);
8375                 if (ret < 0) {
8376                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8377                                     vsi->vsi_id);
8378                         return I40E_ERR_CONFIG;
8379                 }
8380         }
8381
8382         /* Configure for double VLAN TX insertion */
8383         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8384         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8385                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8386                 ret = i40e_aq_debug_write_register(hw,
8387                                                    I40E_VSI_L2TAGSTXVALID(
8388                                                    vsi->vsi_id), reg, NULL);
8389                 if (ret < 0) {
8390                         PMD_DRV_LOG(ERR, "Failed to update "
8391                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8392                         return I40E_ERR_CONFIG;
8393                 }
8394         }
8395
8396         return 0;
8397 }
8398
8399 /**
8400  * i40e_aq_add_mirror_rule
8401  * @hw: pointer to the hardware structure
8402  * @seid: VEB seid to add mirror rule to
8403  * @dst_id: destination vsi seid
8404  * @entries: Buffer which contains the entities to be mirrored
8405  * @count: number of entities contained in the buffer
8406  * @rule_id:the rule_id of the rule to be added
8407  *
8408  * Add a mirror rule for a given veb.
8409  *
8410  **/
8411 static enum i40e_status_code
8412 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8413                         uint16_t seid, uint16_t dst_id,
8414                         uint16_t rule_type, uint16_t *entries,
8415                         uint16_t count, uint16_t *rule_id)
8416 {
8417         struct i40e_aq_desc desc;
8418         struct i40e_aqc_add_delete_mirror_rule cmd;
8419         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8420                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8421                 &desc.params.raw;
8422         uint16_t buff_len;
8423         enum i40e_status_code status;
8424
8425         i40e_fill_default_direct_cmd_desc(&desc,
8426                                           i40e_aqc_opc_add_mirror_rule);
8427         memset(&cmd, 0, sizeof(cmd));
8428
8429         buff_len = sizeof(uint16_t) * count;
8430         desc.datalen = rte_cpu_to_le_16(buff_len);
8431         if (buff_len > 0)
8432                 desc.flags |= rte_cpu_to_le_16(
8433                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8434         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8435                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8436         cmd.num_entries = rte_cpu_to_le_16(count);
8437         cmd.seid = rte_cpu_to_le_16(seid);
8438         cmd.destination = rte_cpu_to_le_16(dst_id);
8439
8440         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8441         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8442         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8443                          "rule_id = %u"
8444                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8445                          hw->aq.asq_last_status, resp->rule_id,
8446                          resp->mirror_rules_used, resp->mirror_rules_free);
8447         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8448
8449         return status;
8450 }
8451
8452 /**
8453  * i40e_aq_del_mirror_rule
8454  * @hw: pointer to the hardware structure
8455  * @seid: VEB seid to add mirror rule to
8456  * @entries: Buffer which contains the entities to be mirrored
8457  * @count: number of entities contained in the buffer
8458  * @rule_id:the rule_id of the rule to be delete
8459  *
8460  * Delete a mirror rule for a given veb.
8461  *
8462  **/
8463 static enum i40e_status_code
8464 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8465                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8466                 uint16_t count, uint16_t rule_id)
8467 {
8468         struct i40e_aq_desc desc;
8469         struct i40e_aqc_add_delete_mirror_rule cmd;
8470         uint16_t buff_len = 0;
8471         enum i40e_status_code status;
8472         void *buff = NULL;
8473
8474         i40e_fill_default_direct_cmd_desc(&desc,
8475                                           i40e_aqc_opc_delete_mirror_rule);
8476         memset(&cmd, 0, sizeof(cmd));
8477         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8478                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8479                                                           I40E_AQ_FLAG_RD));
8480                 cmd.num_entries = count;
8481                 buff_len = sizeof(uint16_t) * count;
8482                 desc.datalen = rte_cpu_to_le_16(buff_len);
8483                 buff = (void *)entries;
8484         } else
8485                 /* rule id is filled in destination field for deleting mirror rule */
8486                 cmd.destination = rte_cpu_to_le_16(rule_id);
8487
8488         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8489                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8490         cmd.seid = rte_cpu_to_le_16(seid);
8491
8492         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8493         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8494
8495         return status;
8496 }
8497
8498 /**
8499  * i40e_mirror_rule_set
8500  * @dev: pointer to the hardware structure
8501  * @mirror_conf: mirror rule info
8502  * @sw_id: mirror rule's sw_id
8503  * @on: enable/disable
8504  *
8505  * set a mirror rule.
8506  *
8507  **/
8508 static int
8509 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8510                         struct rte_eth_mirror_conf *mirror_conf,
8511                         uint8_t sw_id, uint8_t on)
8512 {
8513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8515         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8516         struct i40e_mirror_rule *parent = NULL;
8517         uint16_t seid, dst_seid, rule_id;
8518         uint16_t i, j = 0;
8519         int ret;
8520
8521         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8522
8523         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8524                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8525                         " without veb or vfs.");
8526                 return -ENOSYS;
8527         }
8528         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8529                 PMD_DRV_LOG(ERR, "mirror table is full.");
8530                 return -ENOSPC;
8531         }
8532         if (mirror_conf->dst_pool > pf->vf_num) {
8533                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8534                                  mirror_conf->dst_pool);
8535                 return -EINVAL;
8536         }
8537
8538         seid = pf->main_vsi->veb->seid;
8539
8540         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8541                 if (sw_id <= it->index) {
8542                         mirr_rule = it;
8543                         break;
8544                 }
8545                 parent = it;
8546         }
8547         if (mirr_rule && sw_id == mirr_rule->index) {
8548                 if (on) {
8549                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8550                         return -EEXIST;
8551                 } else {
8552                         ret = i40e_aq_del_mirror_rule(hw, seid,
8553                                         mirr_rule->rule_type,
8554                                         mirr_rule->entries,
8555                                         mirr_rule->num_entries, mirr_rule->id);
8556                         if (ret < 0) {
8557                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8558                                                    " ret = %d, aq_err = %d.",
8559                                                    ret, hw->aq.asq_last_status);
8560                                 return -ENOSYS;
8561                         }
8562                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8563                         rte_free(mirr_rule);
8564                         pf->nb_mirror_rule--;
8565                         return 0;
8566                 }
8567         } else if (!on) {
8568                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8569                 return -ENOENT;
8570         }
8571
8572         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8573                                 sizeof(struct i40e_mirror_rule) , 0);
8574         if (!mirr_rule) {
8575                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8576                 return I40E_ERR_NO_MEMORY;
8577         }
8578         switch (mirror_conf->rule_type) {
8579         case ETH_MIRROR_VLAN:
8580                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8581                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8582                                 mirr_rule->entries[j] =
8583                                         mirror_conf->vlan.vlan_id[i];
8584                                 j++;
8585                         }
8586                 }
8587                 if (j == 0) {
8588                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8589                         rte_free(mirr_rule);
8590                         return -EINVAL;
8591                 }
8592                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8593                 break;
8594         case ETH_MIRROR_VIRTUAL_POOL_UP:
8595         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8596                 /* check if the specified pool bit is out of range */
8597                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8598                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8599                         rte_free(mirr_rule);
8600                         return -EINVAL;
8601                 }
8602                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8603                         if (mirror_conf->pool_mask & (1ULL << i)) {
8604                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8605                                 j++;
8606                         }
8607                 }
8608                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8609                         /* add pf vsi to entries */
8610                         mirr_rule->entries[j] = pf->main_vsi_seid;
8611                         j++;
8612                 }
8613                 if (j == 0) {
8614                         PMD_DRV_LOG(ERR, "pool is not specified.");
8615                         rte_free(mirr_rule);
8616                         return -EINVAL;
8617                 }
8618                 /* egress and ingress in aq commands means from switch but not port */
8619                 mirr_rule->rule_type =
8620                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8621                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8622                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8623                 break;
8624         case ETH_MIRROR_UPLINK_PORT:
8625                 /* egress and ingress in aq commands means from switch but not port*/
8626                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8627                 break;
8628         case ETH_MIRROR_DOWNLINK_PORT:
8629                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8630                 break;
8631         default:
8632                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8633                         mirror_conf->rule_type);
8634                 rte_free(mirr_rule);
8635                 return -EINVAL;
8636         }
8637
8638         /* If the dst_pool is equal to vf_num, consider it as PF */
8639         if (mirror_conf->dst_pool == pf->vf_num)
8640                 dst_seid = pf->main_vsi_seid;
8641         else
8642                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8643
8644         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8645                                       mirr_rule->rule_type, mirr_rule->entries,
8646                                       j, &rule_id);
8647         if (ret < 0) {
8648                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8649                                    " ret = %d, aq_err = %d.",
8650                                    ret, hw->aq.asq_last_status);
8651                 rte_free(mirr_rule);
8652                 return -ENOSYS;
8653         }
8654
8655         mirr_rule->index = sw_id;
8656         mirr_rule->num_entries = j;
8657         mirr_rule->id = rule_id;
8658         mirr_rule->dst_vsi_seid = dst_seid;
8659
8660         if (parent)
8661                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8662         else
8663                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8664
8665         pf->nb_mirror_rule++;
8666         return 0;
8667 }
8668
8669 /**
8670  * i40e_mirror_rule_reset
8671  * @dev: pointer to the device
8672  * @sw_id: mirror rule's sw_id
8673  *
8674  * reset a mirror rule.
8675  *
8676  **/
8677 static int
8678 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8679 {
8680         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8682         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8683         uint16_t seid;
8684         int ret;
8685
8686         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8687
8688         seid = pf->main_vsi->veb->seid;
8689
8690         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8691                 if (sw_id == it->index) {
8692                         mirr_rule = it;
8693                         break;
8694                 }
8695         }
8696         if (mirr_rule) {
8697                 ret = i40e_aq_del_mirror_rule(hw, seid,
8698                                 mirr_rule->rule_type,
8699                                 mirr_rule->entries,
8700                                 mirr_rule->num_entries, mirr_rule->id);
8701                 if (ret < 0) {
8702                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8703                                            " status = %d, aq_err = %d.",
8704                                            ret, hw->aq.asq_last_status);
8705                         return -ENOSYS;
8706                 }
8707                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8708                 rte_free(mirr_rule);
8709                 pf->nb_mirror_rule--;
8710         } else {
8711                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8712                 return -ENOENT;
8713         }
8714         return 0;
8715 }
8716
8717 static uint64_t
8718 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8719 {
8720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8721         uint64_t systim_cycles;
8722
8723         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8724         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8725                         << 32;
8726
8727         return systim_cycles;
8728 }
8729
8730 static uint64_t
8731 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8732 {
8733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8734         uint64_t rx_tstamp;
8735
8736         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8737         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8738                         << 32;
8739
8740         return rx_tstamp;
8741 }
8742
8743 static uint64_t
8744 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8745 {
8746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8747         uint64_t tx_tstamp;
8748
8749         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8750         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8751                         << 32;
8752
8753         return tx_tstamp;
8754 }
8755
8756 static void
8757 i40e_start_timecounters(struct rte_eth_dev *dev)
8758 {
8759         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8760         struct i40e_adapter *adapter =
8761                         (struct i40e_adapter *)dev->data->dev_private;
8762         struct rte_eth_link link;
8763         uint32_t tsync_inc_l;
8764         uint32_t tsync_inc_h;
8765
8766         /* Get current link speed. */
8767         memset(&link, 0, sizeof(link));
8768         i40e_dev_link_update(dev, 1);
8769         rte_i40e_dev_atomic_read_link_status(dev, &link);
8770
8771         switch (link.link_speed) {
8772         case ETH_SPEED_NUM_40G:
8773                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8774                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8775                 break;
8776         case ETH_SPEED_NUM_10G:
8777                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8778                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8779                 break;
8780         case ETH_SPEED_NUM_1G:
8781                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8782                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8783                 break;
8784         default:
8785                 tsync_inc_l = 0x0;
8786                 tsync_inc_h = 0x0;
8787         }
8788
8789         /* Set the timesync increment value. */
8790         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8791         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8792
8793         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8794         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8795         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8796
8797         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8798         adapter->systime_tc.cc_shift = 0;
8799         adapter->systime_tc.nsec_mask = 0;
8800
8801         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8802         adapter->rx_tstamp_tc.cc_shift = 0;
8803         adapter->rx_tstamp_tc.nsec_mask = 0;
8804
8805         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8806         adapter->tx_tstamp_tc.cc_shift = 0;
8807         adapter->tx_tstamp_tc.nsec_mask = 0;
8808 }
8809
8810 static int
8811 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8812 {
8813         struct i40e_adapter *adapter =
8814                         (struct i40e_adapter *)dev->data->dev_private;
8815
8816         adapter->systime_tc.nsec += delta;
8817         adapter->rx_tstamp_tc.nsec += delta;
8818         adapter->tx_tstamp_tc.nsec += delta;
8819
8820         return 0;
8821 }
8822
8823 static int
8824 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8825 {
8826         uint64_t ns;
8827         struct i40e_adapter *adapter =
8828                         (struct i40e_adapter *)dev->data->dev_private;
8829
8830         ns = rte_timespec_to_ns(ts);
8831
8832         /* Set the timecounters to a new value. */
8833         adapter->systime_tc.nsec = ns;
8834         adapter->rx_tstamp_tc.nsec = ns;
8835         adapter->tx_tstamp_tc.nsec = ns;
8836
8837         return 0;
8838 }
8839
8840 static int
8841 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8842 {
8843         uint64_t ns, systime_cycles;
8844         struct i40e_adapter *adapter =
8845                         (struct i40e_adapter *)dev->data->dev_private;
8846
8847         systime_cycles = i40e_read_systime_cyclecounter(dev);
8848         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8849         *ts = rte_ns_to_timespec(ns);
8850
8851         return 0;
8852 }
8853
8854 static int
8855 i40e_timesync_enable(struct rte_eth_dev *dev)
8856 {
8857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8858         uint32_t tsync_ctl_l;
8859         uint32_t tsync_ctl_h;
8860
8861         /* Stop the timesync system time. */
8862         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8863         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8864         /* Reset the timesync system time value. */
8865         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8866         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8867
8868         i40e_start_timecounters(dev);
8869
8870         /* Clear timesync registers. */
8871         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8872         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8873         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8874         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8875         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8876         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8877
8878         /* Enable timestamping of PTP packets. */
8879         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8880         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8881
8882         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8883         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8884         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8885
8886         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8887         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8888
8889         return 0;
8890 }
8891
8892 static int
8893 i40e_timesync_disable(struct rte_eth_dev *dev)
8894 {
8895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8896         uint32_t tsync_ctl_l;
8897         uint32_t tsync_ctl_h;
8898
8899         /* Disable timestamping of transmitted PTP packets. */
8900         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8901         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8902
8903         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8904         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8905
8906         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8907         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8908
8909         /* Reset the timesync increment value. */
8910         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8911         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8912
8913         return 0;
8914 }
8915
8916 static int
8917 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8918                                 struct timespec *timestamp, uint32_t flags)
8919 {
8920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8921         struct i40e_adapter *adapter =
8922                 (struct i40e_adapter *)dev->data->dev_private;
8923
8924         uint32_t sync_status;
8925         uint32_t index = flags & 0x03;
8926         uint64_t rx_tstamp_cycles;
8927         uint64_t ns;
8928
8929         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8930         if ((sync_status & (1 << index)) == 0)
8931                 return -EINVAL;
8932
8933         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8934         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8935         *timestamp = rte_ns_to_timespec(ns);
8936
8937         return 0;
8938 }
8939
8940 static int
8941 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8942                                 struct timespec *timestamp)
8943 {
8944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8945         struct i40e_adapter *adapter =
8946                 (struct i40e_adapter *)dev->data->dev_private;
8947
8948         uint32_t sync_status;
8949         uint64_t tx_tstamp_cycles;
8950         uint64_t ns;
8951
8952         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8953         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8954                 return -EINVAL;
8955
8956         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8957         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8958         *timestamp = rte_ns_to_timespec(ns);
8959
8960         return 0;
8961 }
8962
8963 /*
8964  * i40e_parse_dcb_configure - parse dcb configure from user
8965  * @dev: the device being configured
8966  * @dcb_cfg: pointer of the result of parse
8967  * @*tc_map: bit map of enabled traffic classes
8968  *
8969  * Returns 0 on success, negative value on failure
8970  */
8971 static int
8972 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8973                          struct i40e_dcbx_config *dcb_cfg,
8974                          uint8_t *tc_map)
8975 {
8976         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8977         uint8_t i, tc_bw, bw_lf;
8978
8979         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8980
8981         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8982         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8983                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8984                 return -EINVAL;
8985         }
8986
8987         /* assume each tc has the same bw */
8988         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8989         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8990                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8991         /* to ensure the sum of tcbw is equal to 100 */
8992         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8993         for (i = 0; i < bw_lf; i++)
8994                 dcb_cfg->etscfg.tcbwtable[i]++;
8995
8996         /* assume each tc has the same Transmission Selection Algorithm */
8997         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8998                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8999
9000         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9001                 dcb_cfg->etscfg.prioritytable[i] =
9002                                 dcb_rx_conf->dcb_tc[i];
9003
9004         /* FW needs one App to configure HW */
9005         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9006         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9007         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9008         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9009
9010         if (dcb_rx_conf->nb_tcs == 0)
9011                 *tc_map = 1; /* tc0 only */
9012         else
9013                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9014
9015         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9016                 dcb_cfg->pfc.willing = 0;
9017                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9018                 dcb_cfg->pfc.pfcenable = *tc_map;
9019         }
9020         return 0;
9021 }
9022
9023
9024 static enum i40e_status_code
9025 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9026                               struct i40e_aqc_vsi_properties_data *info,
9027                               uint8_t enabled_tcmap)
9028 {
9029         enum i40e_status_code ret;
9030         int i, total_tc = 0;
9031         uint16_t qpnum_per_tc, bsf, qp_idx;
9032         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9033         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9034         uint16_t used_queues;
9035
9036         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9037         if (ret != I40E_SUCCESS)
9038                 return ret;
9039
9040         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9041                 if (enabled_tcmap & (1 << i))
9042                         total_tc++;
9043         }
9044         if (total_tc == 0)
9045                 total_tc = 1;
9046         vsi->enabled_tc = enabled_tcmap;
9047
9048         /* different VSI has different queues assigned */
9049         if (vsi->type == I40E_VSI_MAIN)
9050                 used_queues = dev_data->nb_rx_queues -
9051                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9052         else if (vsi->type == I40E_VSI_VMDQ2)
9053                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9054         else {
9055                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9056                 return I40E_ERR_NO_AVAILABLE_VSI;
9057         }
9058
9059         qpnum_per_tc = used_queues / total_tc;
9060         /* Number of queues per enabled TC */
9061         if (qpnum_per_tc == 0) {
9062                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9063                 return I40E_ERR_INVALID_QP_ID;
9064         }
9065         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9066                                 I40E_MAX_Q_PER_TC);
9067         bsf = rte_bsf32(qpnum_per_tc);
9068
9069         /**
9070          * Configure TC and queue mapping parameters, for enabled TC,
9071          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9072          * default queue will serve it.
9073          */
9074         qp_idx = 0;
9075         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9076                 if (vsi->enabled_tc & (1 << i)) {
9077                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9078                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9079                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9080                         qp_idx += qpnum_per_tc;
9081                 } else
9082                         info->tc_mapping[i] = 0;
9083         }
9084
9085         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9086         if (vsi->type == I40E_VSI_SRIOV) {
9087                 info->mapping_flags |=
9088                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9089                 for (i = 0; i < vsi->nb_qps; i++)
9090                         info->queue_mapping[i] =
9091                                 rte_cpu_to_le_16(vsi->base_queue + i);
9092         } else {
9093                 info->mapping_flags |=
9094                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9095                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9096         }
9097         info->valid_sections |=
9098                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9099
9100         return I40E_SUCCESS;
9101 }
9102
9103 /*
9104  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9105  * @veb: VEB to be configured
9106  * @tc_map: enabled TC bitmap
9107  *
9108  * Returns 0 on success, negative value on failure
9109  */
9110 static enum i40e_status_code
9111 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9112 {
9113         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9114         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9115         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9116         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9117         enum i40e_status_code ret = I40E_SUCCESS;
9118         int i;
9119         uint32_t bw_max;
9120
9121         /* Check if enabled_tc is same as existing or new TCs */
9122         if (veb->enabled_tc == tc_map)
9123                 return ret;
9124
9125         /* configure tc bandwidth */
9126         memset(&veb_bw, 0, sizeof(veb_bw));
9127         veb_bw.tc_valid_bits = tc_map;
9128         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9129         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9130                 if (tc_map & BIT_ULL(i))
9131                         veb_bw.tc_bw_share_credits[i] = 1;
9132         }
9133         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9134                                                    &veb_bw, NULL);
9135         if (ret) {
9136                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9137                                   " per TC failed = %d",
9138                                   hw->aq.asq_last_status);
9139                 return ret;
9140         }
9141
9142         memset(&ets_query, 0, sizeof(ets_query));
9143         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9144                                                    &ets_query, NULL);
9145         if (ret != I40E_SUCCESS) {
9146                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9147                                  " configuration %u", hw->aq.asq_last_status);
9148                 return ret;
9149         }
9150         memset(&bw_query, 0, sizeof(bw_query));
9151         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9152                                                   &bw_query, NULL);
9153         if (ret != I40E_SUCCESS) {
9154                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9155                                  " configuration %u", hw->aq.asq_last_status);
9156                 return ret;
9157         }
9158
9159         /* store and print out BW info */
9160         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9161         veb->bw_info.bw_max = ets_query.tc_bw_max;
9162         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9163         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9164         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9165                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9166                      I40E_16_BIT_WIDTH);
9167         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9168                 veb->bw_info.bw_ets_share_credits[i] =
9169                                 bw_query.tc_bw_share_credits[i];
9170                 veb->bw_info.bw_ets_credits[i] =
9171                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9172                 /* 4 bits per TC, 4th bit is reserved */
9173                 veb->bw_info.bw_ets_max[i] =
9174                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9175                                   RTE_LEN2MASK(3, uint8_t));
9176                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9177                             veb->bw_info.bw_ets_share_credits[i]);
9178                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9179                             veb->bw_info.bw_ets_credits[i]);
9180                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9181                             veb->bw_info.bw_ets_max[i]);
9182         }
9183
9184         veb->enabled_tc = tc_map;
9185
9186         return ret;
9187 }
9188
9189
9190 /*
9191  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9192  * @vsi: VSI to be configured
9193  * @tc_map: enabled TC bitmap
9194  *
9195  * Returns 0 on success, negative value on failure
9196  */
9197 static enum i40e_status_code
9198 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9199 {
9200         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9201         struct i40e_vsi_context ctxt;
9202         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9203         enum i40e_status_code ret = I40E_SUCCESS;
9204         int i;
9205
9206         /* Check if enabled_tc is same as existing or new TCs */
9207         if (vsi->enabled_tc == tc_map)
9208                 return ret;
9209
9210         /* configure tc bandwidth */
9211         memset(&bw_data, 0, sizeof(bw_data));
9212         bw_data.tc_valid_bits = tc_map;
9213         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9214         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9215                 if (tc_map & BIT_ULL(i))
9216                         bw_data.tc_bw_credits[i] = 1;
9217         }
9218         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9219         if (ret) {
9220                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9221                         " per TC failed = %d",
9222                         hw->aq.asq_last_status);
9223                 goto out;
9224         }
9225         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9226                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9227
9228         /* Update Queue Pairs Mapping for currently enabled UPs */
9229         ctxt.seid = vsi->seid;
9230         ctxt.pf_num = hw->pf_id;
9231         ctxt.vf_num = 0;
9232         ctxt.uplink_seid = vsi->uplink_seid;
9233         ctxt.info = vsi->info;
9234         i40e_get_cap(hw);
9235         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9236         if (ret)
9237                 goto out;
9238
9239         /* Update the VSI after updating the VSI queue-mapping information */
9240         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9241         if (ret) {
9242                 PMD_INIT_LOG(ERR, "Failed to configure "
9243                             "TC queue mapping = %d",
9244                             hw->aq.asq_last_status);
9245                 goto out;
9246         }
9247         /* update the local VSI info with updated queue map */
9248         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9249                                         sizeof(vsi->info.tc_mapping));
9250         (void)rte_memcpy(&vsi->info.queue_mapping,
9251                         &ctxt.info.queue_mapping,
9252                 sizeof(vsi->info.queue_mapping));
9253         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9254         vsi->info.valid_sections = 0;
9255
9256         /* query and update current VSI BW information */
9257         ret = i40e_vsi_get_bw_config(vsi);
9258         if (ret) {
9259                 PMD_INIT_LOG(ERR,
9260                          "Failed updating vsi bw info, err %s aq_err %s",
9261                          i40e_stat_str(hw, ret),
9262                          i40e_aq_str(hw, hw->aq.asq_last_status));
9263                 goto out;
9264         }
9265
9266         vsi->enabled_tc = tc_map;
9267
9268 out:
9269         return ret;
9270 }
9271
9272 /*
9273  * i40e_dcb_hw_configure - program the dcb setting to hw
9274  * @pf: pf the configuration is taken on
9275  * @new_cfg: new configuration
9276  * @tc_map: enabled TC bitmap
9277  *
9278  * Returns 0 on success, negative value on failure
9279  */
9280 static enum i40e_status_code
9281 i40e_dcb_hw_configure(struct i40e_pf *pf,
9282                       struct i40e_dcbx_config *new_cfg,
9283                       uint8_t tc_map)
9284 {
9285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9286         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9287         struct i40e_vsi *main_vsi = pf->main_vsi;
9288         struct i40e_vsi_list *vsi_list;
9289         enum i40e_status_code ret;
9290         int i;
9291         uint32_t val;
9292
9293         /* Use the FW API if FW > v4.4*/
9294         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9295               (hw->aq.fw_maj_ver >= 5))) {
9296                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9297                                   " to configure DCB");
9298                 return I40E_ERR_FIRMWARE_API_VERSION;
9299         }
9300
9301         /* Check if need reconfiguration */
9302         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9303                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9304                 return I40E_SUCCESS;
9305         }
9306
9307         /* Copy the new config to the current config */
9308         *old_cfg = *new_cfg;
9309         old_cfg->etsrec = old_cfg->etscfg;
9310         ret = i40e_set_dcb_config(hw);
9311         if (ret) {
9312                 PMD_INIT_LOG(ERR,
9313                          "Set DCB Config failed, err %s aq_err %s\n",
9314                          i40e_stat_str(hw, ret),
9315                          i40e_aq_str(hw, hw->aq.asq_last_status));
9316                 return ret;
9317         }
9318         /* set receive Arbiter to RR mode and ETS scheme by default */
9319         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9320                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9321                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9322                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9323                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9324                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9325                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9326                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9327                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9328                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9329                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9330                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9331                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9332         }
9333         /* get local mib to check whether it is configured correctly */
9334         /* IEEE mode */
9335         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9336         /* Get Local DCB Config */
9337         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9338                                      &hw->local_dcbx_config);
9339
9340         /* if Veb is created, need to update TC of it at first */
9341         if (main_vsi->veb) {
9342                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9343                 if (ret)
9344                         PMD_INIT_LOG(WARNING,
9345                                  "Failed configuring TC for VEB seid=%d\n",
9346                                  main_vsi->veb->seid);
9347         }
9348         /* Update each VSI */
9349         i40e_vsi_config_tc(main_vsi, tc_map);
9350         if (main_vsi->veb) {
9351                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9352                         /* Beside main VSI and VMDQ VSIs, only enable default
9353                          * TC for other VSIs
9354                          */
9355                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9356                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9357                                                          tc_map);
9358                         else
9359                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9360                                                          I40E_DEFAULT_TCMAP);
9361                         if (ret)
9362                                 PMD_INIT_LOG(WARNING,
9363                                          "Failed configuring TC for VSI seid=%d\n",
9364                                          vsi_list->vsi->seid);
9365                         /* continue */
9366                 }
9367         }
9368         return I40E_SUCCESS;
9369 }
9370
9371 /*
9372  * i40e_dcb_init_configure - initial dcb config
9373  * @dev: device being configured
9374  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9375  *
9376  * Returns 0 on success, negative value on failure
9377  */
9378 static int
9379 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9380 {
9381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9382         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9383         int ret = 0;
9384
9385         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9386                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9387                 return -ENOTSUP;
9388         }
9389
9390         /* DCB initialization:
9391          * Update DCB configuration from the Firmware and configure
9392          * LLDP MIB change event.
9393          */
9394         if (sw_dcb == TRUE) {
9395                 ret = i40e_init_dcb(hw);
9396                 /* If lldp agent is stopped, the return value from
9397                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9398                  * adminq status. Otherwise, it should return success.
9399                  */
9400                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9401                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9402                         memset(&hw->local_dcbx_config, 0,
9403                                 sizeof(struct i40e_dcbx_config));
9404                         /* set dcb default configuration */
9405                         hw->local_dcbx_config.etscfg.willing = 0;
9406                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9407                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9408                         hw->local_dcbx_config.etscfg.tsatable[0] =
9409                                                 I40E_IEEE_TSA_ETS;
9410                         hw->local_dcbx_config.etsrec =
9411                                 hw->local_dcbx_config.etscfg;
9412                         hw->local_dcbx_config.pfc.willing = 0;
9413                         hw->local_dcbx_config.pfc.pfccap =
9414                                                 I40E_MAX_TRAFFIC_CLASS;
9415                         /* FW needs one App to configure HW */
9416                         hw->local_dcbx_config.numapps = 1;
9417                         hw->local_dcbx_config.app[0].selector =
9418                                                 I40E_APP_SEL_ETHTYPE;
9419                         hw->local_dcbx_config.app[0].priority = 3;
9420                         hw->local_dcbx_config.app[0].protocolid =
9421                                                 I40E_APP_PROTOID_FCOE;
9422                         ret = i40e_set_dcb_config(hw);
9423                         if (ret) {
9424                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9425                                         " err = %d, aq_err = %d.", ret,
9426                                           hw->aq.asq_last_status);
9427                                 return -ENOSYS;
9428                         }
9429                 } else {
9430                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9431                                           " err = %d, aq_err = %d.", ret,
9432                                           hw->aq.asq_last_status);
9433                         return -ENOTSUP;
9434                 }
9435         } else {
9436                 ret = i40e_aq_start_lldp(hw, NULL);
9437                 if (ret != I40E_SUCCESS)
9438                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9439
9440                 ret = i40e_init_dcb(hw);
9441                 if (!ret) {
9442                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9443                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9444                                                   " DCBX offload.");
9445                                 return -ENOTSUP;
9446                         }
9447                 } else {
9448                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9449                                           " aq_err = %d.", ret,
9450                                           hw->aq.asq_last_status);
9451                         return -ENOTSUP;
9452                 }
9453         }
9454         return 0;
9455 }
9456
9457 /*
9458  * i40e_dcb_setup - setup dcb related config
9459  * @dev: device being configured
9460  *
9461  * Returns 0 on success, negative value on failure
9462  */
9463 static int
9464 i40e_dcb_setup(struct rte_eth_dev *dev)
9465 {
9466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9467         struct i40e_dcbx_config dcb_cfg;
9468         uint8_t tc_map = 0;
9469         int ret = 0;
9470
9471         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9472                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9473                 return -ENOTSUP;
9474         }
9475
9476         if (pf->vf_num != 0)
9477                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9478
9479         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9480         if (ret) {
9481                 PMD_INIT_LOG(ERR, "invalid dcb config");
9482                 return -EINVAL;
9483         }
9484         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9485         if (ret) {
9486                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9487                 return -ENOSYS;
9488         }
9489
9490         return 0;
9491 }
9492
9493 static int
9494 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9495                       struct rte_eth_dcb_info *dcb_info)
9496 {
9497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9498         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9499         struct i40e_vsi *vsi = pf->main_vsi;
9500         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9501         uint16_t bsf, tc_mapping;
9502         int i, j = 0;
9503
9504         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9505                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9506         else
9507                 dcb_info->nb_tcs = 1;
9508         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9509                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9510         for (i = 0; i < dcb_info->nb_tcs; i++)
9511                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9512
9513         /* get queue mapping if vmdq is disabled */
9514         if (!pf->nb_cfg_vmdq_vsi) {
9515                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9516                         if (!(vsi->enabled_tc & (1 << i)))
9517                                 continue;
9518                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9519                         dcb_info->tc_queue.tc_rxq[j][i].base =
9520                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9521                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9522                         dcb_info->tc_queue.tc_txq[j][i].base =
9523                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9524                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9525                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9526                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9527                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9528                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9529                 }
9530                 return 0;
9531         }
9532
9533         /* get queue mapping if vmdq is enabled */
9534         do {
9535                 vsi = pf->vmdq[j].vsi;
9536                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9537                         if (!(vsi->enabled_tc & (1 << i)))
9538                                 continue;
9539                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9540                         dcb_info->tc_queue.tc_rxq[j][i].base =
9541                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9542                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9543                         dcb_info->tc_queue.tc_txq[j][i].base =
9544                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9545                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9546                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9547                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9548                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9549                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9550                 }
9551                 j++;
9552         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9553         return 0;
9554 }
9555
9556 static int
9557 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9558 {
9559         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9561         uint16_t interval =
9562                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9563         uint16_t msix_intr;
9564
9565         msix_intr = intr_handle->intr_vec[queue_id];
9566         if (msix_intr == I40E_MISC_VEC_ID)
9567                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9568                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9569                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9570                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9571                                (interval <<
9572                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9573         else
9574                 I40E_WRITE_REG(hw,
9575                                I40E_PFINT_DYN_CTLN(msix_intr -
9576                                                    I40E_RX_VEC_START),
9577                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9578                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9579                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9580                                (interval <<
9581                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9582
9583         I40E_WRITE_FLUSH(hw);
9584         rte_intr_enable(&dev->pci_dev->intr_handle);
9585
9586         return 0;
9587 }
9588
9589 static int
9590 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9591 {
9592         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9593         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9594         uint16_t msix_intr;
9595
9596         msix_intr = intr_handle->intr_vec[queue_id];
9597         if (msix_intr == I40E_MISC_VEC_ID)
9598                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9599         else
9600                 I40E_WRITE_REG(hw,
9601                                I40E_PFINT_DYN_CTLN(msix_intr -
9602                                                    I40E_RX_VEC_START),
9603                                0);
9604         I40E_WRITE_FLUSH(hw);
9605
9606         return 0;
9607 }
9608
9609 static int i40e_get_regs(struct rte_eth_dev *dev,
9610                          struct rte_dev_reg_info *regs)
9611 {
9612         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9613         uint32_t *ptr_data = regs->data;
9614         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9615         const struct i40e_reg_info *reg_info;
9616
9617         if (ptr_data == NULL) {
9618                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9619                 regs->width = sizeof(uint32_t);
9620                 return 0;
9621         }
9622
9623         /* The first few registers have to be read using AQ operations */
9624         reg_idx = 0;
9625         while (i40e_regs_adminq[reg_idx].name) {
9626                 reg_info = &i40e_regs_adminq[reg_idx++];
9627                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9628                         for (arr_idx2 = 0;
9629                                         arr_idx2 <= reg_info->count2;
9630                                         arr_idx2++) {
9631                                 reg_offset = arr_idx * reg_info->stride1 +
9632                                         arr_idx2 * reg_info->stride2;
9633                                 reg_offset += reg_info->base_addr;
9634                                 ptr_data[reg_offset >> 2] =
9635                                         i40e_read_rx_ctl(hw, reg_offset);
9636                         }
9637         }
9638
9639         /* The remaining registers can be read using primitives */
9640         reg_idx = 0;
9641         while (i40e_regs_others[reg_idx].name) {
9642                 reg_info = &i40e_regs_others[reg_idx++];
9643                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9644                         for (arr_idx2 = 0;
9645                                         arr_idx2 <= reg_info->count2;
9646                                         arr_idx2++) {
9647                                 reg_offset = arr_idx * reg_info->stride1 +
9648                                         arr_idx2 * reg_info->stride2;
9649                                 reg_offset += reg_info->base_addr;
9650                                 ptr_data[reg_offset >> 2] =
9651                                         I40E_READ_REG(hw, reg_offset);
9652                         }
9653         }
9654
9655         return 0;
9656 }
9657
9658 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9659 {
9660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9661
9662         /* Convert word count to byte count */
9663         return hw->nvm.sr_size << 1;
9664 }
9665
9666 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9667                            struct rte_dev_eeprom_info *eeprom)
9668 {
9669         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9670         uint16_t *data = eeprom->data;
9671         uint16_t offset, length, cnt_words;
9672         int ret_code;
9673
9674         offset = eeprom->offset >> 1;
9675         length = eeprom->length >> 1;
9676         cnt_words = length;
9677
9678         if (offset > hw->nvm.sr_size ||
9679                 offset + length > hw->nvm.sr_size) {
9680                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9681                 return -EINVAL;
9682         }
9683
9684         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9685
9686         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9687         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9688                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9689                 return -EIO;
9690         }
9691
9692         return 0;
9693 }
9694
9695 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9696                                       struct ether_addr *mac_addr)
9697 {
9698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9699
9700         if (!is_valid_assigned_ether_addr(mac_addr)) {
9701                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9702                 return;
9703         }
9704
9705         /* Flags: 0x3 updates port address */
9706         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9707 }
9708
9709 static int
9710 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9711 {
9712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9713         struct rte_eth_dev_data *dev_data = pf->dev_data;
9714         uint32_t frame_size = mtu + ETHER_HDR_LEN
9715                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9716         int ret = 0;
9717
9718         /* check if mtu is within the allowed range */
9719         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9720                 return -EINVAL;
9721
9722         /* mtu setting is forbidden if port is start */
9723         if (dev_data->dev_started) {
9724                 PMD_DRV_LOG(ERR,
9725                             "port %d must be stopped before configuration\n",
9726                             dev_data->port_id);
9727                 return -EBUSY;
9728         }
9729
9730         if (frame_size > ETHER_MAX_LEN)
9731                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9732         else
9733                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9734
9735         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9736
9737         return ret;
9738 }