drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int i40e_dev_configure(struct rte_eth_dev *dev);
 249 static int i40e_dev_start(struct rte_eth_dev *dev);
 250 static void i40e_dev_stop(struct rte_eth_dev *dev);
 251 static void i40e_dev_close(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 294                           struct ether_addr *mac_addr,
 295                           uint32_t index,
 296                           uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 313                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 314 static void i40e_stat_update_48(struct i40e_hw *hw,
 315                                uint32_t hireg,
 316                                uint32_t loreg,
 317                                bool offset_loaded,
 318                                uint64_t *offset,
 319                                uint64_t *stat);
 320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 322                                        void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              struct ether_addr *addr);
 340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 341                                              struct i40e_macvlan_filter *mv_f,
 342                                              int num,
 343                                              uint16_t vlan);
 344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 346                                     struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 348                                       struct rte_eth_rss_conf *rss_conf);
 349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                         struct rte_eth_udp_tunnel *udp_tunnel);
 353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 358                                 enum rte_filter_type filter_type,
 359                                 enum rte_filter_op filter_op,
 360                                 void *arg);
 361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 362                                   struct rte_eth_dcb_info *dcb_info);
 363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 364 static void i40e_configure_registers(struct i40e_hw *hw);
 365 static void i40e_hw_init(struct rte_eth_dev *dev);
 366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 483         .tx_queue_release             = i40e_dev_tx_queue_release,
 484         .dev_led_on                   = i40e_dev_led_on,
 485         .dev_led_off                  = i40e_dev_led_off,
 486         .flow_ctrl_get                = i40e_flow_ctrl_get,
 487         .flow_ctrl_set                = i40e_flow_ctrl_set,
 488         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 489         .mac_addr_add                 = i40e_macaddr_add,
 490         .mac_addr_remove              = i40e_macaddr_remove,
 491         .reta_update                  = i40e_dev_rss_reta_update,
 492         .reta_query                   = i40e_dev_rss_reta_query,
 493         .rss_hash_update              = i40e_dev_rss_hash_update,
 494         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 495         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 496         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 497         .filter_ctrl                  = i40e_dev_filter_ctrl,
 498         .rxq_info_get                 = i40e_rxq_info_get,
 499         .txq_info_get                 = i40e_txq_info_get,
 500         .mirror_rule_set              = i40e_mirror_rule_set,
 501         .mirror_rule_reset            = i40e_mirror_rule_reset,
 502         .timesync_enable              = i40e_timesync_enable,
 503         .timesync_disable             = i40e_timesync_disable,
 504         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 505         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 506         .get_dcb_info                 = i40e_dev_get_dcb_info,
 507         .timesync_adjust_time         = i40e_timesync_adjust_time,
 508         .timesync_read_time           = i40e_timesync_read_time,
 509         .timesync_write_time          = i40e_timesync_write_time,
 510         .get_reg                      = i40e_get_regs,
 511         .get_eeprom_length            = i40e_get_eeprom_length,
 512         .get_eeprom                   = i40e_get_eeprom,
 513         .mac_addr_set                 = i40e_set_default_mac_addr,
 514         .mtu_set                      = i40e_dev_mtu_set,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static struct eth_driver rte_i40e_pmd = {
 631         .pci_drv = {
 632                 .id_table = pci_id_i40e_map,
 633                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 634                 .probe = rte_eth_dev_pci_probe,
 635                 .remove = rte_eth_dev_pci_remove,
 636         },
 637         .eth_dev_init = eth_i40e_dev_init,
 638         .eth_dev_uninit = eth_i40e_dev_uninit,
 639         .dev_private_size = sizeof(struct i40e_adapter),
 640 };
 641
 642 static inline int
 643 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 644                                      struct rte_eth_link *link)
 645 {
 646         struct rte_eth_link *dst = link;
 647         struct rte_eth_link *src = &(dev->data->dev_link);
 648
 649         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 650                                         *(uint64_t *)src) == 0)
 651                 return -1;
 652
 653         return 0;
 654 }
 655
 656 static inline int
 657 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 658                                       struct rte_eth_link *link)
 659 {
 660         struct rte_eth_link *dst = &(dev->data->dev_link);
 661         struct rte_eth_link *src = link;
 662
 663         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 664                                         *(uint64_t *)src) == 0)
 665                 return -1;
 666
 667         return 0;
 668 }
 669
 670 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 671 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 672 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 673
 674 #ifndef I40E_GLQF_ORT
 675 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 676 #endif
 677 #ifndef I40E_GLQF_PIT
 678 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 679 #endif
 680
 681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 682 {
 683         /*
 684          * Initialize registers for flexible payload, which should be set by NVM.
 685          * This should be removed from code once it is fixed in NVM.
 686          */
 687         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 688         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 697         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 698         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 699
 700         /* Initialize registers for parsing packet type of QinQ */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 702         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 703 }
 704
 705 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 706
 707 /*
 708  * Add a ethertype filter to drop all flow control frames transmitted
 709  * from VSIs.
 710 */
 711 static void
 712 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 713 {
 714         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 715         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 716                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 717                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 718         int ret;
 719
 720         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 721                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 722                                 pf->main_vsi_seid, 0,
 723                                 TRUE, NULL, NULL);
 724         if (ret)
 725                 PMD_INIT_LOG(ERR,
 726                         "Failed to add filter to drop flow control frames from VSIs.");
 727 }
 728
 729 static int
 730 floating_veb_list_handler(__rte_unused const char *key,
 731                           const char *floating_veb_value,
 732                           void *opaque)
 733 {
 734         int idx = 0;
 735         unsigned int count = 0;
 736         char *end = NULL;
 737         int min, max;
 738         bool *vf_floating_veb = opaque;
 739
 740         while (isblank(*floating_veb_value))
 741                 floating_veb_value++;
 742
 743         /* Reset floating VEB configuration for VFs */
 744         for (idx = 0; idx < I40E_MAX_VF; idx++)
 745                 vf_floating_veb[idx] = false;
 746
 747         min = I40E_MAX_VF;
 748         do {
 749                 while (isblank(*floating_veb_value))
 750                         floating_veb_value++;
 751                 if (*floating_veb_value == '\0')
 752                         return -1;
 753                 errno = 0;
 754                 idx = strtoul(floating_veb_value, &end, 10);
 755                 if (errno || end == NULL)
 756                         return -1;
 757                 while (isblank(*end))
 758                         end++;
 759                 if (*end == '-') {
 760                         min = idx;
 761                 } else if ((*end == ';') || (*end == '\0')) {
 762                         max = idx;
 763                         if (min == I40E_MAX_VF)
 764                                 min = idx;
 765                         if (max >= I40E_MAX_VF)
 766                                 max = I40E_MAX_VF - 1;
 767                         for (idx = min; idx <= max; idx++) {
 768                                 vf_floating_veb[idx] = true;
 769                                 count++;
 770                         }
 771                         min = I40E_MAX_VF;
 772                 } else {
 773                         return -1;
 774                 }
 775                 floating_veb_value = end + 1;
 776         } while (*end != '\0');
 777
 778         if (count == 0)
 779                 return -1;
 780
 781         return 0;
 782 }
 783
 784 static void
 785 config_vf_floating_veb(struct rte_devargs *devargs,
 786                        uint16_t floating_veb,
 787                        bool *vf_floating_veb)
 788 {
 789         struct rte_kvargs *kvlist;
 790         int i;
 791         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 792
 793         if (!floating_veb)
 794                 return;
 795         /* All the VFs attach to the floating VEB by default
 796          * when the floating VEB is enabled.
 797          */
 798         for (i = 0; i < I40E_MAX_VF; i++)
 799                 vf_floating_veb[i] = true;
 800
 801         if (devargs == NULL)
 802                 return;
 803
 804         kvlist = rte_kvargs_parse(devargs->args, NULL);
 805         if (kvlist == NULL)
 806                 return;
 807
 808         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 809                 rte_kvargs_free(kvlist);
 810                 return;
 811         }
 812         /* When the floating_veb_list parameter exists, all the VFs
 813          * will attach to the legacy VEB firstly, then configure VFs
 814          * to the floating VEB according to the floating_veb_list.
 815          */
 816         if (rte_kvargs_process(kvlist, floating_veb_list,
 817                                floating_veb_list_handler,
 818                                vf_floating_veb) < 0) {
 819                 rte_kvargs_free(kvlist);
 820                 return;
 821         }
 822         rte_kvargs_free(kvlist);
 823 }
 824
 825 static int
 826 i40e_check_floating_handler(__rte_unused const char *key,
 827                             const char *value,
 828                             __rte_unused void *opaque)
 829 {
 830         if (strcmp(value, "1"))
 831                 return -1;
 832
 833         return 0;
 834 }
 835
 836 static int
 837 is_floating_veb_supported(struct rte_devargs *devargs)
 838 {
 839         struct rte_kvargs *kvlist;
 840         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 841
 842         if (devargs == NULL)
 843                 return 0;
 844
 845         kvlist = rte_kvargs_parse(devargs->args, NULL);
 846         if (kvlist == NULL)
 847                 return 0;
 848
 849         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 850                 rte_kvargs_free(kvlist);
 851                 return 0;
 852         }
 853         /* Floating VEB is enabled when there's key-value:
 854          * enable_floating_veb=1
 855          */
 856         if (rte_kvargs_process(kvlist, floating_veb_key,
 857                                i40e_check_floating_handler, NULL) < 0) {
 858                 rte_kvargs_free(kvlist);
 859                 return 0;
 860         }
 861         rte_kvargs_free(kvlist);
 862
 863         return 1;
 864 }
 865
 866 static void
 867 config_floating_veb(struct rte_eth_dev *dev)
 868 {
 869         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 871         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 872
 873         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 874
 875         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 876                 pf->floating_veb =
 877                         is_floating_veb_supported(pci_dev->device.devargs);
 878                 config_vf_floating_veb(pci_dev->device.devargs,
 879                                        pf->floating_veb,
 880                                        pf->floating_veb_list);
 881         } else {
 882                 pf->floating_veb = false;
 883         }
 884 }
 885
 886 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 887 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 888
 889 static int
 890 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 891 {
 892         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 893         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 894         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 895         int ret;
 896
 897         struct rte_hash_parameters ethertype_hash_params = {
 898                 .name = ethertype_hash_name,
 899                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 900                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 901                 .hash_func = rte_hash_crc,
 902         };
 903
 904         /* Initialize ethertype filter rule list and hash */
 905         TAILQ_INIT(&ethertype_rule->ethertype_list);
 906         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 907                  "ethertype_%s", dev->data->name);
 908         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 909         if (!ethertype_rule->hash_table) {
 910                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 911                 return -EINVAL;
 912         }
 913         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 914                                        sizeof(struct i40e_ethertype_filter *) *
 915                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 916                                        0);
 917         if (!ethertype_rule->hash_map) {
 918                 PMD_INIT_LOG(ERR,
 919                              "Failed to allocate memory for ethertype hash map!");
 920                 ret = -ENOMEM;
 921                 goto err_ethertype_hash_map_alloc;
 922         }
 923
 924         return 0;
 925
 926 err_ethertype_hash_map_alloc:
 927         rte_hash_free(ethertype_rule->hash_table);
 928
 929         return ret;
 930 }
 931
 932 static int
 933 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 934 {
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 937         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 938         int ret;
 939
 940         struct rte_hash_parameters tunnel_hash_params = {
 941                 .name = tunnel_hash_name,
 942                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 943                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 944                 .hash_func = rte_hash_crc,
 945         };
 946
 947         /* Initialize tunnel filter rule list and hash */
 948         TAILQ_INIT(&tunnel_rule->tunnel_list);
 949         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 950                  "tunnel_%s", dev->data->name);
 951         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 952         if (!tunnel_rule->hash_table) {
 953                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 954                 return -EINVAL;
 955         }
 956         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 957                                     sizeof(struct i40e_tunnel_filter *) *
 958                                     I40E_MAX_TUNNEL_FILTER_NUM,
 959                                     0);
 960         if (!tunnel_rule->hash_map) {
 961                 PMD_INIT_LOG(ERR,
 962                              "Failed to allocate memory for tunnel hash map!");
 963                 ret = -ENOMEM;
 964                 goto err_tunnel_hash_map_alloc;
 965         }
 966
 967         return 0;
 968
 969 err_tunnel_hash_map_alloc:
 970         rte_hash_free(tunnel_rule->hash_table);
 971
 972         return ret;
 973 }
 974
 975 static int
 976 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 977 {
 978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 979         struct i40e_fdir_info *fdir_info = &pf->fdir;
 980         char fdir_hash_name[RTE_HASH_NAMESIZE];
 981         int ret;
 982
 983         struct rte_hash_parameters fdir_hash_params = {
 984                 .name = fdir_hash_name,
 985                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 986                 .key_len = sizeof(struct rte_eth_fdir_input),
 987                 .hash_func = rte_hash_crc,
 988         };
 989
 990         /* Initialize flow director filter rule list and hash */
 991         TAILQ_INIT(&fdir_info->fdir_list);
 992         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 993                  "fdir_%s", dev->data->name);
 994         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 995         if (!fdir_info->hash_table) {
 996                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 997                 return -EINVAL;
 998         }
 999         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1000                                           sizeof(struct i40e_fdir_filter *) *
1001                                           I40E_MAX_FDIR_FILTER_NUM,
1002                                           0);
1003         if (!fdir_info->hash_map) {
1004                 PMD_INIT_LOG(ERR,
1005                              "Failed to allocate memory for fdir hash map!");
1006                 ret = -ENOMEM;
1007                 goto err_fdir_hash_map_alloc;
1008         }
1009         return 0;
1010
1011 err_fdir_hash_map_alloc:
1012         rte_hash_free(fdir_info->hash_table);
1013
1014         return ret;
1015 }
1016
1017 static int
1018 eth_i40e_dev_init(struct rte_eth_dev *dev)
1019 {
1020         struct rte_pci_device *pci_dev;
1021         struct rte_intr_handle *intr_handle;
1022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024         struct i40e_vsi *vsi;
1025         int ret;
1026         uint32_t len;
1027         uint8_t aq_fail = 0;
1028
1029         PMD_INIT_FUNC_TRACE();
1030
1031         dev->dev_ops = &i40e_eth_dev_ops;
1032         dev->rx_pkt_burst = i40e_recv_pkts;
1033         dev->tx_pkt_burst = i40e_xmit_pkts;
1034         dev->tx_pkt_prepare = i40e_prep_pkts;
1035
1036         /* for secondary processes, we don't initialise any further as primary
1037          * has already done this work. Only check we don't need a different
1038          * RX function */
1039         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040                 i40e_set_rx_function(dev);
1041                 i40e_set_tx_function(dev);
1042                 return 0;
1043         }
1044         pci_dev = I40E_DEV_TO_PCI(dev);
1045         intr_handle = &pci_dev->intr_handle;
1046
1047         rte_eth_copy_pci_info(dev, pci_dev);
1048         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1049
1050         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1051         pf->adapter->eth_dev = dev;
1052         pf->dev_data = dev->data;
1053
1054         hw->back = I40E_PF_TO_ADAPTER(pf);
1055         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1056         if (!hw->hw_addr) {
1057                 PMD_INIT_LOG(ERR,
1058                         "Hardware is not available, as address is NULL");
1059                 return -ENODEV;
1060         }
1061
1062         hw->vendor_id = pci_dev->id.vendor_id;
1063         hw->device_id = pci_dev->id.device_id;
1064         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1065         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1066         hw->bus.device = pci_dev->addr.devid;
1067         hw->bus.func = pci_dev->addr.function;
1068         hw->adapter_stopped = 0;
1069
1070         /* Make sure all is clean before doing PF reset */
1071         i40e_clear_hw(hw);
1072
1073         /* Initialize the hardware */
1074         i40e_hw_init(dev);
1075
1076         /* Reset here to make sure all is clean for each PF */
1077         ret = i40e_pf_reset(hw);
1078         if (ret) {
1079                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1080                 return ret;
1081         }
1082
1083         /* Initialize the shared code (base driver) */
1084         ret = i40e_init_shared_code(hw);
1085         if (ret) {
1086                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1087                 return ret;
1088         }
1089
1090         /*
1091          * To work around the NVM issue, initialize registers
1092          * for flexible payload and packet type of QinQ by
1093          * software. It should be removed once issues are fixed
1094          * in NVM.
1095          */
1096         i40e_GLQF_reg_init(hw);
1097
1098         /* Initialize the input set for filters (hash and fd) to default value */
1099         i40e_filter_input_set_init(pf);
1100
1101         /* Initialize the parameters for adminq */
1102         i40e_init_adminq_parameter(hw);
1103         ret = i40e_init_adminq(hw);
1104         if (ret != I40E_SUCCESS) {
1105                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1106                 return -EIO;
1107         }
1108         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1109                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1110                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1111                      ((hw->nvm.version >> 12) & 0xf),
1112                      ((hw->nvm.version >> 4) & 0xff),
1113                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1114
1115         /* Need the special FW version to support floating VEB */
1116         config_floating_veb(dev);
1117         /* Clear PXE mode */
1118         i40e_clear_pxe_mode(hw);
1119         ret = i40e_dev_sync_phy_type(hw);
1120         if (ret) {
1121                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1122                 goto err_sync_phy_type;
1123         }
1124         /*
1125          * On X710, performance number is far from the expectation on recent
1126          * firmware versions. The fix for this issue may not be integrated in
1127          * the following firmware version. So the workaround in software driver
1128          * is needed. It needs to modify the initial values of 3 internal only
1129          * registers. Note that the workaround can be removed when it is fixed
1130          * in firmware in the future.
1131          */
1132         i40e_configure_registers(hw);
1133
1134         /* Get hw capabilities */
1135         ret = i40e_get_cap(hw);
1136         if (ret != I40E_SUCCESS) {
1137                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1138                 goto err_get_capabilities;
1139         }
1140
1141         /* Initialize parameters for PF */
1142         ret = i40e_pf_parameter_init(dev);
1143         if (ret != 0) {
1144                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1145                 goto err_parameter_init;
1146         }
1147
1148         /* Initialize the queue management */
1149         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1150         if (ret < 0) {
1151                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1152                 goto err_qp_pool_init;
1153         }
1154         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1155                                 hw->func_caps.num_msix_vectors - 1);
1156         if (ret < 0) {
1157                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1158                 goto err_msix_pool_init;
1159         }
1160
1161         /* Initialize lan hmc */
1162         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1163                                 hw->func_caps.num_rx_qp, 0, 0);
1164         if (ret != I40E_SUCCESS) {
1165                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1166                 goto err_init_lan_hmc;
1167         }
1168
1169         /* Configure lan hmc */
1170         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1171         if (ret != I40E_SUCCESS) {
1172                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1173                 goto err_configure_lan_hmc;
1174         }
1175
1176         /* Get and check the mac address */
1177         i40e_get_mac_addr(hw, hw->mac.addr);
1178         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "mac address is not valid");
1180                 ret = -EIO;
1181                 goto err_get_mac_addr;
1182         }
1183         /* Copy the permanent MAC address */
1184         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1185                         (struct ether_addr *) hw->mac.perm_addr);
1186
1187         /* Disable flow control */
1188         hw->fc.requested_mode = I40E_FC_NONE;
1189         i40e_set_fc(hw, &aq_fail, TRUE);
1190
1191         /* Set the global registers with default ether type value */
1192         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR,
1195                         "Failed to set the default outer VLAN ether type");
1196                 goto err_setup_pf_switch;
1197         }
1198
1199         /* PF setup, which includes VSI setup */
1200         ret = i40e_pf_setup(pf);
1201         if (ret) {
1202                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1203                 goto err_setup_pf_switch;
1204         }
1205
1206         /* reset all stats of the device, including pf and main vsi */
1207         i40e_dev_stats_reset(dev);
1208
1209         vsi = pf->main_vsi;
1210
1211         /* Disable double vlan by default */
1212         i40e_vsi_config_double_vlan(vsi, FALSE);
1213
1214         /* Disable S-TAG identification when floating_veb is disabled */
1215         if (!pf->floating_veb) {
1216                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1217                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1218                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1219                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1220                 }
1221         }
1222
1223         if (!vsi->max_macaddrs)
1224                 len = ETHER_ADDR_LEN;
1225         else
1226                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1227
1228         /* Should be after VSI initialized */
1229         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1230         if (!dev->data->mac_addrs) {
1231                 PMD_INIT_LOG(ERR,
1232                         "Failed to allocated memory for storing mac address");
1233                 goto err_mac_alloc;
1234         }
1235         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1236                                         &dev->data->mac_addrs[0]);
1237
1238         /* initialize pf host driver to setup SRIOV resource if applicable */
1239         i40e_pf_host_init(dev);
1240
1241         /* register callback func to eal lib */
1242         rte_intr_callback_register(intr_handle,
1243                                    i40e_dev_interrupt_handler, dev);
1244
1245         /* configure and enable device interrupt */
1246         i40e_pf_config_irq0(hw, TRUE);
1247         i40e_pf_enable_irq0(hw);
1248
1249         /* enable uio intr after callback register */
1250         rte_intr_enable(intr_handle);
1251         /*
1252          * Add an ethertype filter to drop all flow control frames transmitted
1253          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1254          * frames to wire.
1255          */
1256         i40e_add_tx_flow_control_drop_filter(pf);
1257
1258         /* Set the max frame size to 0x2600 by default,
1259          * in case other drivers changed the default value.
1260          */
1261         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1262
1263         /* initialize mirror rule list */
1264         TAILQ_INIT(&pf->mirror_list);
1265
1266         /* Init dcb to sw mode by default */
1267         ret = i40e_dcb_init_configure(dev, TRUE);
1268         if (ret != I40E_SUCCESS) {
1269                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1270                 pf->flags &= ~I40E_FLAG_DCB;
1271         }
1272
1273         ret = i40e_init_ethtype_filter_list(dev);
1274         if (ret < 0)
1275                 goto err_init_ethtype_filter_list;
1276         ret = i40e_init_tunnel_filter_list(dev);
1277         if (ret < 0)
1278                 goto err_init_tunnel_filter_list;
1279         ret = i40e_init_fdir_filter_list(dev);
1280         if (ret < 0)
1281                 goto err_init_fdir_filter_list;
1282
1283         return 0;
1284
1285 err_init_fdir_filter_list:
1286         rte_free(pf->tunnel.hash_table);
1287         rte_free(pf->tunnel.hash_map);
1288 err_init_tunnel_filter_list:
1289         rte_free(pf->ethertype.hash_table);
1290         rte_free(pf->ethertype.hash_map);
1291 err_init_ethtype_filter_list:
1292         rte_free(dev->data->mac_addrs);
1293 err_mac_alloc:
1294         i40e_vsi_release(pf->main_vsi);
1295 err_setup_pf_switch:
1296 err_get_mac_addr:
1297 err_configure_lan_hmc:
1298         (void)i40e_shutdown_lan_hmc(hw);
1299 err_init_lan_hmc:
1300         i40e_res_pool_destroy(&pf->msix_pool);
1301 err_msix_pool_init:
1302         i40e_res_pool_destroy(&pf->qp_pool);
1303 err_qp_pool_init:
1304 err_parameter_init:
1305 err_get_capabilities:
1306 err_sync_phy_type:
1307         (void)i40e_shutdown_adminq(hw);
1308
1309         return ret;
1310 }
1311
1312 static void
1313 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1314 {
1315         struct i40e_ethertype_filter *p_ethertype;
1316         struct i40e_ethertype_rule *ethertype_rule;
1317
1318         ethertype_rule = &pf->ethertype;
1319         /* Remove all ethertype filter rules and hash */
1320         if (ethertype_rule->hash_map)
1321                 rte_free(ethertype_rule->hash_map);
1322         if (ethertype_rule->hash_table)
1323                 rte_hash_free(ethertype_rule->hash_table);
1324
1325         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1326                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1327                              p_ethertype, rules);
1328                 rte_free(p_ethertype);
1329         }
1330 }
1331
1332 static void
1333 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1334 {
1335         struct i40e_tunnel_filter *p_tunnel;
1336         struct i40e_tunnel_rule *tunnel_rule;
1337
1338         tunnel_rule = &pf->tunnel;
1339         /* Remove all tunnel director rules and hash */
1340         if (tunnel_rule->hash_map)
1341                 rte_free(tunnel_rule->hash_map);
1342         if (tunnel_rule->hash_table)
1343                 rte_hash_free(tunnel_rule->hash_table);
1344
1345         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1346                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1347                 rte_free(p_tunnel);
1348         }
1349 }
1350
1351 static void
1352 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1353 {
1354         struct i40e_fdir_filter *p_fdir;
1355         struct i40e_fdir_info *fdir_info;
1356
1357         fdir_info = &pf->fdir;
1358         /* Remove all flow director rules and hash */
1359         if (fdir_info->hash_map)
1360                 rte_free(fdir_info->hash_map);
1361         if (fdir_info->hash_table)
1362                 rte_hash_free(fdir_info->hash_table);
1363
1364         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1366                 rte_free(p_fdir);
1367         }
1368 }
1369
1370 static int
1371 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1372 {
1373         struct i40e_pf *pf;
1374         struct rte_pci_device *pci_dev;
1375         struct rte_intr_handle *intr_handle;
1376         struct i40e_hw *hw;
1377         struct i40e_filter_control_settings settings;
1378         struct rte_flow *p_flow;
1379         int ret;
1380         uint8_t aq_fail = 0;
1381
1382         PMD_INIT_FUNC_TRACE();
1383
1384         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1385                 return 0;
1386
1387         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1388         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389         pci_dev = I40E_DEV_TO_PCI(dev);
1390         intr_handle = &pci_dev->intr_handle;
1391
1392         if (hw->adapter_stopped == 0)
1393                 i40e_dev_close(dev);
1394
1395         dev->dev_ops = NULL;
1396         dev->rx_pkt_burst = NULL;
1397         dev->tx_pkt_burst = NULL;
1398
1399         /* Clear PXE mode */
1400         i40e_clear_pxe_mode(hw);
1401
1402         /* Unconfigure filter control */
1403         memset(&settings, 0, sizeof(settings));
1404         ret = i40e_set_filter_control(hw, &settings);
1405         if (ret)
1406                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1407                                         ret);
1408
1409         /* Disable flow control */
1410         hw->fc.requested_mode = I40E_FC_NONE;
1411         i40e_set_fc(hw, &aq_fail, TRUE);
1412
1413         /* uninitialize pf host driver */
1414         i40e_pf_host_uninit(dev);
1415
1416         rte_free(dev->data->mac_addrs);
1417         dev->data->mac_addrs = NULL;
1418
1419         /* disable uio intr before callback unregister */
1420         rte_intr_disable(intr_handle);
1421
1422         /* register callback func to eal lib */
1423         rte_intr_callback_unregister(intr_handle,
1424                                      i40e_dev_interrupt_handler, dev);
1425
1426         i40e_rm_ethtype_filter_list(pf);
1427         i40e_rm_tunnel_filter_list(pf);
1428         i40e_rm_fdir_filter_list(pf);
1429
1430         /* Remove all flows */
1431         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1432                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1433                 rte_free(p_flow);
1434         }
1435
1436         return 0;
1437 }
1438
1439 static int
1440 i40e_dev_configure(struct rte_eth_dev *dev)
1441 {
1442         struct i40e_adapter *ad =
1443                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1445         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1446         int i, ret;
1447
1448         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1449          * bulk allocation or vector Rx preconditions we will reset it.
1450          */
1451         ad->rx_bulk_alloc_allowed = true;
1452         ad->rx_vec_allowed = true;
1453         ad->tx_simple_allowed = true;
1454         ad->tx_vec_allowed = true;
1455
1456         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1457                 ret = i40e_fdir_setup(pf);
1458                 if (ret != I40E_SUCCESS) {
1459                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1460                         return -ENOTSUP;
1461                 }
1462                 ret = i40e_fdir_configure(dev);
1463                 if (ret < 0) {
1464                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1465                         goto err;
1466                 }
1467         } else
1468                 i40e_fdir_teardown(pf);
1469
1470         ret = i40e_dev_init_vlan(dev);
1471         if (ret < 0)
1472                 goto err;
1473
1474         /* VMDQ setup.
1475          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1476          *  RSS setting have different requirements.
1477          *  General PMD driver call sequence are NIC init, configure,
1478          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1479          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1480          *  applicable. So, VMDQ setting has to be done before
1481          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1482          *  For RSS setting, it will try to calculate actual configured RX queue
1483          *  number, which will be available after rx_queue_setup(). dev_start()
1484          *  function is good to place RSS setup.
1485          */
1486         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1487                 ret = i40e_vmdq_setup(dev);
1488                 if (ret)
1489                         goto err;
1490         }
1491
1492         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1493                 ret = i40e_dcb_setup(dev);
1494                 if (ret) {
1495                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1496                         goto err_dcb;
1497                 }
1498         }
1499
1500         TAILQ_INIT(&pf->flow_list);
1501
1502         return 0;
1503
1504 err_dcb:
1505         /* need to release vmdq resource if exists */
1506         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1507                 i40e_vsi_release(pf->vmdq[i].vsi);
1508                 pf->vmdq[i].vsi = NULL;
1509         }
1510         rte_free(pf->vmdq);
1511         pf->vmdq = NULL;
1512 err:
1513         /* need to release fdir resource if exists */
1514         i40e_fdir_teardown(pf);
1515         return ret;
1516 }
1517
1518 void
1519 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1520 {
1521         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1523         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1524         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525         uint16_t msix_vect = vsi->msix_intr;
1526         uint16_t i;
1527
1528         for (i = 0; i < vsi->nb_qps; i++) {
1529                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1530                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1531                 rte_wmb();
1532         }
1533
1534         if (vsi->type != I40E_VSI_SRIOV) {
1535                 if (!rte_intr_allow_others(intr_handle)) {
1536                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1537                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1538                         I40E_WRITE_REG(hw,
1539                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1540                                        0);
1541                 } else {
1542                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1543                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1544                         I40E_WRITE_REG(hw,
1545                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1546                                                        msix_vect - 1), 0);
1547                 }
1548         } else {
1549                 uint32_t reg;
1550                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1551                         vsi->user_param + (msix_vect - 1);
1552
1553                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1554                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1555         }
1556         I40E_WRITE_FLUSH(hw);
1557 }
1558
1559 static void
1560 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1561                        int base_queue, int nb_queue)
1562 {
1563         int i;
1564         uint32_t val;
1565         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1566
1567         /* Bind all RX queues to allocated MSIX interrupt */
1568         for (i = 0; i < nb_queue; i++) {
1569                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1570                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1571                         ((base_queue + i + 1) <<
1572                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1573                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1574                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1575
1576                 if (i == nb_queue - 1)
1577                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1578                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1579         }
1580
1581         /* Write first RX queue to Link list register as the head element */
1582         if (vsi->type != I40E_VSI_SRIOV) {
1583                 uint16_t interval =
1584                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1585
1586                 if (msix_vect == I40E_MISC_VEC_ID) {
1587                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1588                                        (base_queue <<
1589                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1590                                        (0x0 <<
1591                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1592                         I40E_WRITE_REG(hw,
1593                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1594                                        interval);
1595                 } else {
1596                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1597                                        (base_queue <<
1598                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1599                                        (0x0 <<
1600                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1601                         I40E_WRITE_REG(hw,
1602                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1603                                                        msix_vect - 1),
1604                                        interval);
1605                 }
1606         } else {
1607                 uint32_t reg;
1608
1609                 if (msix_vect == I40E_MISC_VEC_ID) {
1610                         I40E_WRITE_REG(hw,
1611                                        I40E_VPINT_LNKLST0(vsi->user_param),
1612                                        (base_queue <<
1613                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1614                                        (0x0 <<
1615                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1616                 } else {
1617                         /* num_msix_vectors_vf needs to minus irq0 */
1618                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1619                                 vsi->user_param + (msix_vect - 1);
1620
1621                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1622                                        (base_queue <<
1623                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1624                                        (0x0 <<
1625                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1626                 }
1627         }
1628
1629         I40E_WRITE_FLUSH(hw);
1630 }
1631
1632 void
1633 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1634 {
1635         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1637         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1638         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1639         uint16_t msix_vect = vsi->msix_intr;
1640         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1641         uint16_t queue_idx = 0;
1642         int record = 0;
1643         uint32_t val;
1644         int i;
1645
1646         for (i = 0; i < vsi->nb_qps; i++) {
1647                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1648                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1649         }
1650
1651         /* INTENA flag is not auto-cleared for interrupt */
1652         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1653         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1654                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1655                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1656         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1657
1658         /* VF bind interrupt */
1659         if (vsi->type == I40E_VSI_SRIOV) {
1660                 __vsi_queues_bind_intr(vsi, msix_vect,
1661                                        vsi->base_queue, vsi->nb_qps);
1662                 return;
1663         }
1664
1665         /* PF & VMDq bind interrupt */
1666         if (rte_intr_dp_is_en(intr_handle)) {
1667                 if (vsi->type == I40E_VSI_MAIN) {
1668                         queue_idx = 0;
1669                         record = 1;
1670                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1671                         struct i40e_vsi *main_vsi =
1672                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1673                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1674                         record = 1;
1675                 }
1676         }
1677
1678         for (i = 0; i < vsi->nb_used_qps; i++) {
1679                 if (nb_msix <= 1) {
1680                         if (!rte_intr_allow_others(intr_handle))
1681                                 /* allow to share MISC_VEC_ID */
1682                                 msix_vect = I40E_MISC_VEC_ID;
1683
1684                         /* no enough msix_vect, map all to one */
1685                         __vsi_queues_bind_intr(vsi, msix_vect,
1686                                                vsi->base_queue + i,
1687                                                vsi->nb_used_qps - i);
1688                         for (; !!record && i < vsi->nb_used_qps; i++)
1689                                 intr_handle->intr_vec[queue_idx + i] =
1690                                         msix_vect;
1691                         break;
1692                 }
1693                 /* 1:1 queue/msix_vect mapping */
1694                 __vsi_queues_bind_intr(vsi, msix_vect,
1695                                        vsi->base_queue + i, 1);
1696                 if (!!record)
1697                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1698
1699                 msix_vect++;
1700                 nb_msix--;
1701         }
1702 }
1703
1704 static void
1705 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1706 {
1707         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1708         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1709         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1710         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1711         uint16_t interval = i40e_calc_itr_interval(\
1712                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1713         uint16_t msix_intr, i;
1714
1715         if (rte_intr_allow_others(intr_handle))
1716                 for (i = 0; i < vsi->nb_msix; i++) {
1717                         msix_intr = vsi->msix_intr + i;
1718                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1719                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1720                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1721                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1722                                 (interval <<
1723                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1724                 }
1725         else
1726                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1727                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1728                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1729                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1730                                (interval <<
1731                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1732
1733         I40E_WRITE_FLUSH(hw);
1734 }
1735
1736 static void
1737 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1738 {
1739         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1740         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1741         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1743         uint16_t msix_intr, i;
1744
1745         if (rte_intr_allow_others(intr_handle))
1746                 for (i = 0; i < vsi->nb_msix; i++) {
1747                         msix_intr = vsi->msix_intr + i;
1748                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1749                                        0);
1750                 }
1751         else
1752                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1753
1754         I40E_WRITE_FLUSH(hw);
1755 }
1756
1757 static inline uint8_t
1758 i40e_parse_link_speeds(uint16_t link_speeds)
1759 {
1760         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1761
1762         if (link_speeds & ETH_LINK_SPEED_40G)
1763                 link_speed |= I40E_LINK_SPEED_40GB;
1764         if (link_speeds & ETH_LINK_SPEED_25G)
1765                 link_speed |= I40E_LINK_SPEED_25GB;
1766         if (link_speeds & ETH_LINK_SPEED_20G)
1767                 link_speed |= I40E_LINK_SPEED_20GB;
1768         if (link_speeds & ETH_LINK_SPEED_10G)
1769                 link_speed |= I40E_LINK_SPEED_10GB;
1770         if (link_speeds & ETH_LINK_SPEED_1G)
1771                 link_speed |= I40E_LINK_SPEED_1GB;
1772         if (link_speeds & ETH_LINK_SPEED_100M)
1773                 link_speed |= I40E_LINK_SPEED_100MB;
1774
1775         return link_speed;
1776 }
1777
1778 static int
1779 i40e_phy_conf_link(struct i40e_hw *hw,
1780                    uint8_t abilities,
1781                    uint8_t force_speed)
1782 {
1783         enum i40e_status_code status;
1784         struct i40e_aq_get_phy_abilities_resp phy_ab;
1785         struct i40e_aq_set_phy_config phy_conf;
1786         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1787                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1788                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1789                         I40E_AQ_PHY_FLAG_LOW_POWER;
1790         const uint8_t advt = I40E_LINK_SPEED_40GB |
1791                         I40E_LINK_SPEED_25GB |
1792                         I40E_LINK_SPEED_10GB |
1793                         I40E_LINK_SPEED_1GB |
1794                         I40E_LINK_SPEED_100MB;
1795         int ret = -ENOTSUP;
1796
1797
1798         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1799                                               NULL);
1800         if (status)
1801                 return ret;
1802
1803         memset(&phy_conf, 0, sizeof(phy_conf));
1804
1805         /* bits 0-2 use the values from get_phy_abilities_resp */
1806         abilities &= ~mask;
1807         abilities |= phy_ab.abilities & mask;
1808
1809         /* update ablities and speed */
1810         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1811                 phy_conf.link_speed = advt;
1812         else
1813                 phy_conf.link_speed = force_speed;
1814
1815         phy_conf.abilities = abilities;
1816
1817         /* use get_phy_abilities_resp value for the rest */
1818         phy_conf.phy_type = phy_ab.phy_type;
1819         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1820         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1821         phy_conf.eee_capability = phy_ab.eee_capability;
1822         phy_conf.eeer = phy_ab.eeer_val;
1823         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1824
1825         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1826                     phy_ab.abilities, phy_ab.link_speed);
1827         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1828                     phy_conf.abilities, phy_conf.link_speed);
1829
1830         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1831         if (status)
1832                 return ret;
1833
1834         return I40E_SUCCESS;
1835 }
1836
1837 static int
1838 i40e_apply_link_speed(struct rte_eth_dev *dev)
1839 {
1840         uint8_t speed;
1841         uint8_t abilities = 0;
1842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843         struct rte_eth_conf *conf = &dev->data->dev_conf;
1844
1845         speed = i40e_parse_link_speeds(conf->link_speeds);
1846         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1847         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1848                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1849         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1850
1851         /* Skip changing speed on 40G interfaces, FW does not support */
1852         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1853                 speed =  I40E_LINK_SPEED_UNKNOWN;
1854                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1855         }
1856
1857         return i40e_phy_conf_link(hw, abilities, speed);
1858 }
1859
1860 static int
1861 i40e_dev_start(struct rte_eth_dev *dev)
1862 {
1863         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865         struct i40e_vsi *main_vsi = pf->main_vsi;
1866         int ret, i;
1867         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1869         uint32_t intr_vector = 0;
1870
1871         hw->adapter_stopped = 0;
1872
1873         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1874                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1875                              dev->data->port_id);
1876                 return -EINVAL;
1877         }
1878
1879         rte_intr_disable(intr_handle);
1880
1881         if ((rte_intr_cap_multiple(intr_handle) ||
1882              !RTE_ETH_DEV_SRIOV(dev).active) &&
1883             dev->data->dev_conf.intr_conf.rxq != 0) {
1884                 intr_vector = dev->data->nb_rx_queues;
1885                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1886                 if (ret)
1887                         return ret;
1888         }
1889
1890         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1891                 intr_handle->intr_vec =
1892                         rte_zmalloc("intr_vec",
1893                                     dev->data->nb_rx_queues * sizeof(int),
1894                                     0);
1895                 if (!intr_handle->intr_vec) {
1896                         PMD_INIT_LOG(ERR,
1897                                 "Failed to allocate %d rx_queues intr_vec\n",
1898                                 dev->data->nb_rx_queues);
1899                         return -ENOMEM;
1900                 }
1901         }
1902
1903         /* Initialize VSI */
1904         ret = i40e_dev_rxtx_init(pf);
1905         if (ret != I40E_SUCCESS) {
1906                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1907                 goto err_up;
1908         }
1909
1910         /* Map queues with MSIX interrupt */
1911         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1912                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1913         i40e_vsi_queues_bind_intr(main_vsi);
1914         i40e_vsi_enable_queues_intr(main_vsi);
1915
1916         /* Map VMDQ VSI queues with MSIX interrupt */
1917         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1918                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1919                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1920                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1921         }
1922
1923         /* enable FDIR MSIX interrupt */
1924         if (pf->fdir.fdir_vsi) {
1925                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1926                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1927         }
1928
1929         /* Enable all queues which have been configured */
1930         ret = i40e_dev_switch_queues(pf, TRUE);
1931         if (ret != I40E_SUCCESS) {
1932                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1933                 goto err_up;
1934         }
1935
1936         /* Enable receiving broadcast packets */
1937         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1938         if (ret != I40E_SUCCESS)
1939                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1940
1941         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1942                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1943                                                 true, NULL);
1944                 if (ret != I40E_SUCCESS)
1945                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1946         }
1947
1948         /* Apply link configure */
1949         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1950                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1951                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1952                                 ETH_LINK_SPEED_40G)) {
1953                 PMD_DRV_LOG(ERR, "Invalid link setting");
1954                 goto err_up;
1955         }
1956         ret = i40e_apply_link_speed(dev);
1957         if (I40E_SUCCESS != ret) {
1958                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1959                 goto err_up;
1960         }
1961
1962         if (!rte_intr_allow_others(intr_handle)) {
1963                 rte_intr_callback_unregister(intr_handle,
1964                                              i40e_dev_interrupt_handler,
1965                                              (void *)dev);
1966                 /* configure and enable device interrupt */
1967                 i40e_pf_config_irq0(hw, FALSE);
1968                 i40e_pf_enable_irq0(hw);
1969
1970                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1971                         PMD_INIT_LOG(INFO,
1972                                 "lsc won't enable because of no intr multiplex\n");
1973         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1974                 ret = i40e_aq_set_phy_int_mask(hw,
1975                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1976                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1977                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1978                 if (ret != I40E_SUCCESS)
1979                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1980
1981                 /* Call get_link_info aq commond to enable LSE */
1982                 i40e_dev_link_update(dev, 0);
1983         }
1984
1985         /* enable uio intr after callback register */
1986         rte_intr_enable(intr_handle);
1987
1988         i40e_filter_restore(pf);
1989
1990         return I40E_SUCCESS;
1991
1992 err_up:
1993         i40e_dev_switch_queues(pf, FALSE);
1994         i40e_dev_clear_queues(dev);
1995
1996         return ret;
1997 }
1998
1999 static void
2000 i40e_dev_stop(struct rte_eth_dev *dev)
2001 {
2002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003         struct i40e_vsi *main_vsi = pf->main_vsi;
2004         struct i40e_mirror_rule *p_mirror;
2005         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2007         int i;
2008
2009         /* Disable all queues */
2010         i40e_dev_switch_queues(pf, FALSE);
2011
2012         /* un-map queues with interrupt registers */
2013         i40e_vsi_disable_queues_intr(main_vsi);
2014         i40e_vsi_queues_unbind_intr(main_vsi);
2015
2016         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2018                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2019         }
2020
2021         if (pf->fdir.fdir_vsi) {
2022                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2023                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2024         }
2025         /* Clear all queues and release memory */
2026         i40e_dev_clear_queues(dev);
2027
2028         /* Set link down */
2029         i40e_dev_set_link_down(dev);
2030
2031         /* Remove all mirror rules */
2032         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2033                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2034                 rte_free(p_mirror);
2035         }
2036         pf->nb_mirror_rule = 0;
2037
2038         if (!rte_intr_allow_others(intr_handle))
2039                 /* resume to the default handler */
2040                 rte_intr_callback_register(intr_handle,
2041                                            i40e_dev_interrupt_handler,
2042                                            (void *)dev);
2043
2044         /* Clean datapath event and queue/vec mapping */
2045         rte_intr_efd_disable(intr_handle);
2046         if (intr_handle->intr_vec) {
2047                 rte_free(intr_handle->intr_vec);
2048                 intr_handle->intr_vec = NULL;
2049         }
2050 }
2051
2052 static void
2053 i40e_dev_close(struct rte_eth_dev *dev)
2054 {
2055         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2059         uint32_t reg;
2060         int i;
2061
2062         PMD_INIT_FUNC_TRACE();
2063
2064         i40e_dev_stop(dev);
2065         hw->adapter_stopped = 1;
2066         i40e_dev_free_queues(dev);
2067
2068         /* Disable interrupt */
2069         i40e_pf_disable_irq0(hw);
2070         rte_intr_disable(intr_handle);
2071
2072         /* shutdown and destroy the HMC */
2073         i40e_shutdown_lan_hmc(hw);
2074
2075         /* release all the existing VSIs and VEBs */
2076         i40e_fdir_teardown(pf);
2077         i40e_vsi_release(pf->main_vsi);
2078
2079         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2080                 i40e_vsi_release(pf->vmdq[i].vsi);
2081                 pf->vmdq[i].vsi = NULL;
2082         }
2083
2084         rte_free(pf->vmdq);
2085         pf->vmdq = NULL;
2086
2087         /* shutdown the adminq */
2088         i40e_aq_queue_shutdown(hw, true);
2089         i40e_shutdown_adminq(hw);
2090
2091         i40e_res_pool_destroy(&pf->qp_pool);
2092         i40e_res_pool_destroy(&pf->msix_pool);
2093
2094         /* force a PF reset to clean anything leftover */
2095         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2096         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2097                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2098         I40E_WRITE_FLUSH(hw);
2099 }
2100
2101 static void
2102 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2103 {
2104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         struct i40e_vsi *vsi = pf->main_vsi;
2107         int status;
2108
2109         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2110                                                      true, NULL, true);
2111         if (status != I40E_SUCCESS)
2112                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2113
2114         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2115                                                         TRUE, NULL);
2116         if (status != I40E_SUCCESS)
2117                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2118
2119 }
2120
2121 static void
2122 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2123 {
2124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126         struct i40e_vsi *vsi = pf->main_vsi;
2127         int status;
2128
2129         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2130                                                      false, NULL, true);
2131         if (status != I40E_SUCCESS)
2132                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2133
2134         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2135                                                         false, NULL);
2136         if (status != I40E_SUCCESS)
2137                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2138 }
2139
2140 static void
2141 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2142 {
2143         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2144         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145         struct i40e_vsi *vsi = pf->main_vsi;
2146         int ret;
2147
2148         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2149         if (ret != I40E_SUCCESS)
2150                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2151 }
2152
2153 static void
2154 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2155 {
2156         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158         struct i40e_vsi *vsi = pf->main_vsi;
2159         int ret;
2160
2161         if (dev->data->promiscuous == 1)
2162                 return; /* must remain in all_multicast mode */
2163
2164         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2165                                 vsi->seid, FALSE, NULL);
2166         if (ret != I40E_SUCCESS)
2167                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2168 }
2169
2170 /*
2171  * Set device link up.
2172  */
2173 static int
2174 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2175 {
2176         /* re-apply link speed setting */
2177         return i40e_apply_link_speed(dev);
2178 }
2179
2180 /*
2181  * Set device link down.
2182  */
2183 static int
2184 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2185 {
2186         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2187         uint8_t abilities = 0;
2188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2189
2190         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2191         return i40e_phy_conf_link(hw, abilities, speed);
2192 }
2193
2194 int
2195 i40e_dev_link_update(struct rte_eth_dev *dev,
2196                      int wait_to_complete)
2197 {
2198 #define CHECK_INTERVAL 100  /* 100ms */
2199 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         struct i40e_link_status link_status;
2202         struct rte_eth_link link, old;
2203         int status;
2204         unsigned rep_cnt = MAX_REPEAT_TIME;
2205         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2206
2207         memset(&link, 0, sizeof(link));
2208         memset(&old, 0, sizeof(old));
2209         memset(&link_status, 0, sizeof(link_status));
2210         rte_i40e_dev_atomic_read_link_status(dev, &old);
2211
2212         do {
2213                 /* Get link status information from hardware */
2214                 status = i40e_aq_get_link_info(hw, enable_lse,
2215                                                 &link_status, NULL);
2216                 if (status != I40E_SUCCESS) {
2217                         link.link_speed = ETH_SPEED_NUM_100M;
2218                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2219                         PMD_DRV_LOG(ERR, "Failed to get link info");
2220                         goto out;
2221                 }
2222
2223                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2224                 if (!wait_to_complete)
2225                         break;
2226
2227                 rte_delay_ms(CHECK_INTERVAL);
2228         } while (!link.link_status && rep_cnt--);
2229
2230         if (!link.link_status)
2231                 goto out;
2232
2233         /* i40e uses full duplex only */
2234         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2235
2236         /* Parse the link status */
2237         switch (link_status.link_speed) {
2238         case I40E_LINK_SPEED_100MB:
2239                 link.link_speed = ETH_SPEED_NUM_100M;
2240                 break;
2241         case I40E_LINK_SPEED_1GB:
2242                 link.link_speed = ETH_SPEED_NUM_1G;
2243                 break;
2244         case I40E_LINK_SPEED_10GB:
2245                 link.link_speed = ETH_SPEED_NUM_10G;
2246                 break;
2247         case I40E_LINK_SPEED_20GB:
2248                 link.link_speed = ETH_SPEED_NUM_20G;
2249                 break;
2250         case I40E_LINK_SPEED_25GB:
2251                 link.link_speed = ETH_SPEED_NUM_25G;
2252                 break;
2253         case I40E_LINK_SPEED_40GB:
2254                 link.link_speed = ETH_SPEED_NUM_40G;
2255                 break;
2256         default:
2257                 link.link_speed = ETH_SPEED_NUM_100M;
2258                 break;
2259         }
2260
2261         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2262                         ETH_LINK_SPEED_FIXED);
2263
2264 out:
2265         rte_i40e_dev_atomic_write_link_status(dev, &link);
2266         if (link.link_status == old.link_status)
2267                 return -1;
2268
2269         return 0;
2270 }
2271
2272 /* Get all the statistics of a VSI */
2273 void
2274 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2275 {
2276         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2277         struct i40e_eth_stats *nes = &vsi->eth_stats;
2278         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2279         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2280
2281         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2282                             vsi->offset_loaded, &oes->rx_bytes,
2283                             &nes->rx_bytes);
2284         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2285                             vsi->offset_loaded, &oes->rx_unicast,
2286                             &nes->rx_unicast);
2287         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2288                             vsi->offset_loaded, &oes->rx_multicast,
2289                             &nes->rx_multicast);
2290         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2291                             vsi->offset_loaded, &oes->rx_broadcast,
2292                             &nes->rx_broadcast);
2293         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2294                             &oes->rx_discards, &nes->rx_discards);
2295         /* GLV_REPC not supported */
2296         /* GLV_RMPC not supported */
2297         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2298                             &oes->rx_unknown_protocol,
2299                             &nes->rx_unknown_protocol);
2300         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2301                             vsi->offset_loaded, &oes->tx_bytes,
2302                             &nes->tx_bytes);
2303         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2304                             vsi->offset_loaded, &oes->tx_unicast,
2305                             &nes->tx_unicast);
2306         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2307                             vsi->offset_loaded, &oes->tx_multicast,
2308                             &nes->tx_multicast);
2309         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2310                             vsi->offset_loaded,  &oes->tx_broadcast,
2311                             &nes->tx_broadcast);
2312         /* GLV_TDPC not supported */
2313         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2314                             &oes->tx_errors, &nes->tx_errors);
2315         vsi->offset_loaded = true;
2316
2317         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2318                     vsi->vsi_id);
2319         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2320         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2321         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2322         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2323         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2324         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2325                     nes->rx_unknown_protocol);
2326         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2327         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2328         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2329         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2330         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2331         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2332         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2333                     vsi->vsi_id);
2334 }
2335
2336 static void
2337 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2338 {
2339         unsigned int i;
2340         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2341         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2342
2343         /* Get statistics of struct i40e_eth_stats */
2344         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2345                             I40E_GLPRT_GORCL(hw->port),
2346                             pf->offset_loaded, &os->eth.rx_bytes,
2347                             &ns->eth.rx_bytes);
2348         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2349                             I40E_GLPRT_UPRCL(hw->port),
2350                             pf->offset_loaded, &os->eth.rx_unicast,
2351                             &ns->eth.rx_unicast);
2352         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2353                             I40E_GLPRT_MPRCL(hw->port),
2354                             pf->offset_loaded, &os->eth.rx_multicast,
2355                             &ns->eth.rx_multicast);
2356         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2357                             I40E_GLPRT_BPRCL(hw->port),
2358                             pf->offset_loaded, &os->eth.rx_broadcast,
2359                             &ns->eth.rx_broadcast);
2360         /* Workaround: CRC size should not be included in byte statistics,
2361          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2362          */
2363         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2364                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2365
2366         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2367                             pf->offset_loaded, &os->eth.rx_discards,
2368                             &ns->eth.rx_discards);
2369         /* GLPRT_REPC not supported */
2370         /* GLPRT_RMPC not supported */
2371         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2372                             pf->offset_loaded,
2373                             &os->eth.rx_unknown_protocol,
2374                             &ns->eth.rx_unknown_protocol);
2375         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2376                             I40E_GLPRT_GOTCL(hw->port),
2377                             pf->offset_loaded, &os->eth.tx_bytes,
2378                             &ns->eth.tx_bytes);
2379         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2380                             I40E_GLPRT_UPTCL(hw->port),
2381                             pf->offset_loaded, &os->eth.tx_unicast,
2382                             &ns->eth.tx_unicast);
2383         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2384                             I40E_GLPRT_MPTCL(hw->port),
2385                             pf->offset_loaded, &os->eth.tx_multicast,
2386                             &ns->eth.tx_multicast);
2387         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2388                             I40E_GLPRT_BPTCL(hw->port),
2389                             pf->offset_loaded, &os->eth.tx_broadcast,
2390                             &ns->eth.tx_broadcast);
2391         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2392                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2393         /* GLPRT_TEPC not supported */
2394
2395         /* additional port specific stats */
2396         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2397                             pf->offset_loaded, &os->tx_dropped_link_down,
2398                             &ns->tx_dropped_link_down);
2399         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2400                             pf->offset_loaded, &os->crc_errors,
2401                             &ns->crc_errors);
2402         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2403                             pf->offset_loaded, &os->illegal_bytes,
2404                             &ns->illegal_bytes);
2405         /* GLPRT_ERRBC not supported */
2406         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2407                             pf->offset_loaded, &os->mac_local_faults,
2408                             &ns->mac_local_faults);
2409         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2410                             pf->offset_loaded, &os->mac_remote_faults,
2411                             &ns->mac_remote_faults);
2412         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2413                             pf->offset_loaded, &os->rx_length_errors,
2414                             &ns->rx_length_errors);
2415         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2416                             pf->offset_loaded, &os->link_xon_rx,
2417                             &ns->link_xon_rx);
2418         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2419                             pf->offset_loaded, &os->link_xoff_rx,
2420                             &ns->link_xoff_rx);
2421         for (i = 0; i < 8; i++) {
2422                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2423                                     pf->offset_loaded,
2424                                     &os->priority_xon_rx[i],
2425                                     &ns->priority_xon_rx[i]);
2426                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2427                                     pf->offset_loaded,
2428                                     &os->priority_xoff_rx[i],
2429                                     &ns->priority_xoff_rx[i]);
2430         }
2431         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2432                             pf->offset_loaded, &os->link_xon_tx,
2433                             &ns->link_xon_tx);
2434         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2435                             pf->offset_loaded, &os->link_xoff_tx,
2436                             &ns->link_xoff_tx);
2437         for (i = 0; i < 8; i++) {
2438                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2439                                     pf->offset_loaded,
2440                                     &os->priority_xon_tx[i],
2441                                     &ns->priority_xon_tx[i]);
2442                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2443                                     pf->offset_loaded,
2444                                     &os->priority_xoff_tx[i],
2445                                     &ns->priority_xoff_tx[i]);
2446                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2447                                     pf->offset_loaded,
2448                                     &os->priority_xon_2_xoff[i],
2449                                     &ns->priority_xon_2_xoff[i]);
2450         }
2451         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2452                             I40E_GLPRT_PRC64L(hw->port),
2453                             pf->offset_loaded, &os->rx_size_64,
2454                             &ns->rx_size_64);
2455         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2456                             I40E_GLPRT_PRC127L(hw->port),
2457                             pf->offset_loaded, &os->rx_size_127,
2458                             &ns->rx_size_127);
2459         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2460                             I40E_GLPRT_PRC255L(hw->port),
2461                             pf->offset_loaded, &os->rx_size_255,
2462                             &ns->rx_size_255);
2463         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2464                             I40E_GLPRT_PRC511L(hw->port),
2465                             pf->offset_loaded, &os->rx_size_511,
2466                             &ns->rx_size_511);
2467         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2468                             I40E_GLPRT_PRC1023L(hw->port),
2469                             pf->offset_loaded, &os->rx_size_1023,
2470                             &ns->rx_size_1023);
2471         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2472                             I40E_GLPRT_PRC1522L(hw->port),
2473                             pf->offset_loaded, &os->rx_size_1522,
2474                             &ns->rx_size_1522);
2475         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2476                             I40E_GLPRT_PRC9522L(hw->port),
2477                             pf->offset_loaded, &os->rx_size_big,
2478                             &ns->rx_size_big);
2479         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2480                             pf->offset_loaded, &os->rx_undersize,
2481                             &ns->rx_undersize);
2482         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2483                             pf->offset_loaded, &os->rx_fragments,
2484                             &ns->rx_fragments);
2485         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2486                             pf->offset_loaded, &os->rx_oversize,
2487                             &ns->rx_oversize);
2488         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2489                             pf->offset_loaded, &os->rx_jabber,
2490                             &ns->rx_jabber);
2491         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2492                             I40E_GLPRT_PTC64L(hw->port),
2493                             pf->offset_loaded, &os->tx_size_64,
2494                             &ns->tx_size_64);
2495         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2496                             I40E_GLPRT_PTC127L(hw->port),
2497                             pf->offset_loaded, &os->tx_size_127,
2498                             &ns->tx_size_127);
2499         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2500                             I40E_GLPRT_PTC255L(hw->port),
2501                             pf->offset_loaded, &os->tx_size_255,
2502                             &ns->tx_size_255);
2503         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2504                             I40E_GLPRT_PTC511L(hw->port),
2505                             pf->offset_loaded, &os->tx_size_511,
2506                             &ns->tx_size_511);
2507         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2508                             I40E_GLPRT_PTC1023L(hw->port),
2509                             pf->offset_loaded, &os->tx_size_1023,
2510                             &ns->tx_size_1023);
2511         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2512                             I40E_GLPRT_PTC1522L(hw->port),
2513                             pf->offset_loaded, &os->tx_size_1522,
2514                             &ns->tx_size_1522);
2515         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2516                             I40E_GLPRT_PTC9522L(hw->port),
2517                             pf->offset_loaded, &os->tx_size_big,
2518                             &ns->tx_size_big);
2519         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2520                            pf->offset_loaded,
2521                            &os->fd_sb_match, &ns->fd_sb_match);
2522         /* GLPRT_MSPDC not supported */
2523         /* GLPRT_XEC not supported */
2524
2525         pf->offset_loaded = true;
2526
2527         if (pf->main_vsi)
2528                 i40e_update_vsi_stats(pf->main_vsi);
2529 }
2530
2531 /* Get all statistics of a port */
2532 static void
2533 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2534 {
2535         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2536         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2538         unsigned i;
2539
2540         /* call read registers - updates values, now write them to struct */
2541         i40e_read_stats_registers(pf, hw);
2542
2543         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2544                         pf->main_vsi->eth_stats.rx_multicast +
2545                         pf->main_vsi->eth_stats.rx_broadcast -
2546                         pf->main_vsi->eth_stats.rx_discards;
2547         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2548                         pf->main_vsi->eth_stats.tx_multicast +
2549                         pf->main_vsi->eth_stats.tx_broadcast;
2550         stats->ibytes   = ns->eth.rx_bytes;
2551         stats->obytes   = ns->eth.tx_bytes;
2552         stats->oerrors  = ns->eth.tx_errors +
2553                         pf->main_vsi->eth_stats.tx_errors;
2554
2555         /* Rx Errors */
2556         stats->imissed  = ns->eth.rx_discards +
2557                         pf->main_vsi->eth_stats.rx_discards;
2558         stats->ierrors  = ns->crc_errors +
2559                         ns->rx_length_errors + ns->rx_undersize +
2560                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2561
2562         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2563         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2564         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2565         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2566         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2567         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2568         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2569                     ns->eth.rx_unknown_protocol);
2570         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2571         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2572         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2573         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2574         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2575         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2576
2577         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2578                     ns->tx_dropped_link_down);
2579         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2580         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2581                     ns->illegal_bytes);
2582         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2583         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2584                     ns->mac_local_faults);
2585         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2586                     ns->mac_remote_faults);
2587         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2588                     ns->rx_length_errors);
2589         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2590         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2591         for (i = 0; i < 8; i++) {
2592                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2593                                 i, ns->priority_xon_rx[i]);
2594                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2595                                 i, ns->priority_xoff_rx[i]);
2596         }
2597         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2598         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2599         for (i = 0; i < 8; i++) {
2600                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2601                                 i, ns->priority_xon_tx[i]);
2602                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2603                                 i, ns->priority_xoff_tx[i]);
2604                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2605                                 i, ns->priority_xon_2_xoff[i]);
2606         }
2607         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2608         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2609         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2610         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2611         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2612         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2613         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2614         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2615         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2616         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2617         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2618         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2619         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2620         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2621         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2622         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2623         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2624         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2625         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2626                         ns->mac_short_packet_dropped);
2627         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2628                     ns->checksum_error);
2629         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2630         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2631 }
2632
2633 /* Reset the statistics */
2634 static void
2635 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2636 {
2637         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2639
2640         /* Mark PF and VSI stats to update the offset, aka "reset" */
2641         pf->offset_loaded = false;
2642         if (pf->main_vsi)
2643                 pf->main_vsi->offset_loaded = false;
2644
2645         /* read the stats, reading current register values into offset */
2646         i40e_read_stats_registers(pf, hw);
2647 }
2648
2649 static uint32_t
2650 i40e_xstats_calc_num(void)
2651 {
2652         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2653                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2654                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2655 }
2656
2657 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2658                                      struct rte_eth_xstat_name *xstats_names,
2659                                      __rte_unused unsigned limit)
2660 {
2661         unsigned count = 0;
2662         unsigned i, prio;
2663
2664         if (xstats_names == NULL)
2665                 return i40e_xstats_calc_num();
2666
2667         /* Note: limit checked in rte_eth_xstats_names() */
2668
2669         /* Get stats from i40e_eth_stats struct */
2670         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2671                 snprintf(xstats_names[count].name,
2672                          sizeof(xstats_names[count].name),
2673                          "%s", rte_i40e_stats_strings[i].name);
2674                 count++;
2675         }
2676
2677         /* Get individiual stats from i40e_hw_port struct */
2678         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2679                 snprintf(xstats_names[count].name,
2680                         sizeof(xstats_names[count].name),
2681                          "%s", rte_i40e_hw_port_strings[i].name);
2682                 count++;
2683         }
2684
2685         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2686                 for (prio = 0; prio < 8; prio++) {
2687                         snprintf(xstats_names[count].name,
2688                                  sizeof(xstats_names[count].name),
2689                                  "rx_priority%u_%s", prio,
2690                                  rte_i40e_rxq_prio_strings[i].name);
2691                         count++;
2692                 }
2693         }
2694
2695         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2696                 for (prio = 0; prio < 8; prio++) {
2697                         snprintf(xstats_names[count].name,
2698                                  sizeof(xstats_names[count].name),
2699                                  "tx_priority%u_%s", prio,
2700                                  rte_i40e_txq_prio_strings[i].name);
2701                         count++;
2702                 }
2703         }
2704         return count;
2705 }
2706
2707 static int
2708 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2709                     unsigned n)
2710 {
2711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713         unsigned i, count, prio;
2714         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2715
2716         count = i40e_xstats_calc_num();
2717         if (n < count)
2718                 return count;
2719
2720         i40e_read_stats_registers(pf, hw);
2721
2722         if (xstats == NULL)
2723                 return 0;
2724
2725         count = 0;
2726
2727         /* Get stats from i40e_eth_stats struct */
2728         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2729                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2730                         rte_i40e_stats_strings[i].offset);
2731                 xstats[count].id = count;
2732                 count++;
2733         }
2734
2735         /* Get individiual stats from i40e_hw_port struct */
2736         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2737                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2738                         rte_i40e_hw_port_strings[i].offset);
2739                 xstats[count].id = count;
2740                 count++;
2741         }
2742
2743         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2744                 for (prio = 0; prio < 8; prio++) {
2745                         xstats[count].value =
2746                                 *(uint64_t *)(((char *)hw_stats) +
2747                                 rte_i40e_rxq_prio_strings[i].offset +
2748                                 (sizeof(uint64_t) * prio));
2749                         xstats[count].id = count;
2750                         count++;
2751                 }
2752         }
2753
2754         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2755                 for (prio = 0; prio < 8; prio++) {
2756                         xstats[count].value =
2757                                 *(uint64_t *)(((char *)hw_stats) +
2758                                 rte_i40e_txq_prio_strings[i].offset +
2759                                 (sizeof(uint64_t) * prio));
2760                         xstats[count].id = count;
2761                         count++;
2762                 }
2763         }
2764
2765         return count;
2766 }
2767
2768 static int
2769 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2770                                  __rte_unused uint16_t queue_id,
2771                                  __rte_unused uint8_t stat_idx,
2772                                  __rte_unused uint8_t is_rx)
2773 {
2774         PMD_INIT_FUNC_TRACE();
2775
2776         return -ENOSYS;
2777 }
2778
2779 static int
2780 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2781 {
2782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2783         u32 full_ver;
2784         u8 ver, patch;
2785         u16 build;
2786         int ret;
2787
2788         full_ver = hw->nvm.oem_ver;
2789         ver = (u8)(full_ver >> 24);
2790         build = (u16)((full_ver >> 8) & 0xffff);
2791         patch = (u8)(full_ver & 0xff);
2792
2793         ret = snprintf(fw_version, fw_size,
2794                  "%d.%d%d 0x%08x %d.%d.%d",
2795                  ((hw->nvm.version >> 12) & 0xf),
2796                  ((hw->nvm.version >> 4) & 0xff),
2797                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2798                  ver, build, patch);
2799
2800         ret += 1; /* add the size of '\0' */
2801         if (fw_size < (u32)ret)
2802                 return ret;
2803         else
2804                 return 0;
2805 }
2806
2807 static void
2808 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2809 {
2810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812         struct i40e_vsi *vsi = pf->main_vsi;
2813         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2814
2815         dev_info->pci_dev = pci_dev;
2816         dev_info->max_rx_queues = vsi->nb_qps;
2817         dev_info->max_tx_queues = vsi->nb_qps;
2818         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2819         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2820         dev_info->max_mac_addrs = vsi->max_macaddrs;
2821         dev_info->max_vfs = pci_dev->max_vfs;
2822         dev_info->rx_offload_capa =
2823                 DEV_RX_OFFLOAD_VLAN_STRIP |
2824                 DEV_RX_OFFLOAD_QINQ_STRIP |
2825                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2826                 DEV_RX_OFFLOAD_UDP_CKSUM |
2827                 DEV_RX_OFFLOAD_TCP_CKSUM;
2828         dev_info->tx_offload_capa =
2829                 DEV_TX_OFFLOAD_VLAN_INSERT |
2830                 DEV_TX_OFFLOAD_QINQ_INSERT |
2831                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2832                 DEV_TX_OFFLOAD_UDP_CKSUM |
2833                 DEV_TX_OFFLOAD_TCP_CKSUM |
2834                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2835                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2836                 DEV_TX_OFFLOAD_TCP_TSO |
2837                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2838                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2839                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2840                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2841         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2842                                                 sizeof(uint32_t);
2843         dev_info->reta_size = pf->hash_lut_size;
2844         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2845
2846         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2847                 .rx_thresh = {
2848                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2849                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2850                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2851                 },
2852                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2853                 .rx_drop_en = 0,
2854         };
2855
2856         dev_info->default_txconf = (struct rte_eth_txconf) {
2857                 .tx_thresh = {
2858                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2859                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2860                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2861                 },
2862                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2863                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2864                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2865                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2866         };
2867
2868         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2869                 .nb_max = I40E_MAX_RING_DESC,
2870                 .nb_min = I40E_MIN_RING_DESC,
2871                 .nb_align = I40E_ALIGN_RING_DESC,
2872         };
2873
2874         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2875                 .nb_max = I40E_MAX_RING_DESC,
2876                 .nb_min = I40E_MIN_RING_DESC,
2877                 .nb_align = I40E_ALIGN_RING_DESC,
2878                 .nb_seg_max = I40E_TX_MAX_SEG,
2879                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2880         };
2881
2882         if (pf->flags & I40E_FLAG_VMDQ) {
2883                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2884                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2885                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2886                                                 pf->max_nb_vmdq_vsi;
2887                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2888                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2889                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2890         }
2891
2892         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2893                 /* For XL710 */
2894                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2895         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2896                 /* For XXV710 */
2897                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2898         else
2899                 /* For X710 */
2900                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2901 }
2902
2903 static int
2904 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2905 {
2906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2907         struct i40e_vsi *vsi = pf->main_vsi;
2908         PMD_INIT_FUNC_TRACE();
2909
2910         if (on)
2911                 return i40e_vsi_add_vlan(vsi, vlan_id);
2912         else
2913                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2914 }
2915
2916 static int
2917 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2918                    enum rte_vlan_type vlan_type,
2919                    uint16_t tpid)
2920 {
2921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922         uint64_t reg_r = 0, reg_w = 0;
2923         uint16_t reg_id = 0;
2924         int ret = 0;
2925         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2926
2927         switch (vlan_type) {
2928         case ETH_VLAN_TYPE_OUTER:
2929                 if (qinq)
2930                         reg_id = 2;
2931                 else
2932                         reg_id = 3;
2933                 break;
2934         case ETH_VLAN_TYPE_INNER:
2935                 if (qinq)
2936                         reg_id = 3;
2937                 else {
2938                         ret = -EINVAL;
2939                         PMD_DRV_LOG(ERR,
2940                                 "Unsupported vlan type in single vlan.\n");
2941                         return ret;
2942                 }
2943                 break;
2944         default:
2945                 ret = -EINVAL;
2946                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2947                 return ret;
2948         }
2949         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2950                                           &reg_r, NULL);
2951         if (ret != I40E_SUCCESS) {
2952                 PMD_DRV_LOG(ERR,
2953                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2954                            reg_id);
2955                 ret = -EIO;
2956                 return ret;
2957         }
2958         PMD_DRV_LOG(DEBUG,
2959                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2960                 reg_id, reg_r);
2961
2962         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2963         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2964         if (reg_r == reg_w) {
2965                 ret = 0;
2966                 PMD_DRV_LOG(DEBUG, "No need to write");
2967                 return ret;
2968         }
2969
2970         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2971                                            reg_w, NULL);
2972         if (ret != I40E_SUCCESS) {
2973                 ret = -EIO;
2974                 PMD_DRV_LOG(ERR,
2975                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2976                         reg_id);
2977                 return ret;
2978         }
2979         PMD_DRV_LOG(DEBUG,
2980                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2981                 reg_w, reg_id);
2982
2983         return ret;
2984 }
2985
2986 static void
2987 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2988 {
2989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990         struct i40e_vsi *vsi = pf->main_vsi;
2991
2992         if (mask & ETH_VLAN_FILTER_MASK) {
2993                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2994                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2995                 else
2996                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2997         }
2998
2999         if (mask & ETH_VLAN_STRIP_MASK) {
3000                 /* Enable or disable VLAN stripping */
3001                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3002                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3003                 else
3004                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3005         }
3006
3007         if (mask & ETH_VLAN_EXTEND_MASK) {
3008                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3009                         i40e_vsi_config_double_vlan(vsi, TRUE);
3010                         /* Set global registers with default ether type value */
3011                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3012                                            ETHER_TYPE_VLAN);
3013                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3014                                            ETHER_TYPE_VLAN);
3015                 }
3016                 else
3017                         i40e_vsi_config_double_vlan(vsi, FALSE);
3018         }
3019 }
3020
3021 static void
3022 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3023                           __rte_unused uint16_t queue,
3024                           __rte_unused int on)
3025 {
3026         PMD_INIT_FUNC_TRACE();
3027 }
3028
3029 static int
3030 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3031 {
3032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3033         struct i40e_vsi *vsi = pf->main_vsi;
3034         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3035         struct i40e_vsi_vlan_pvid_info info;
3036
3037         memset(&info, 0, sizeof(info));
3038         info.on = on;
3039         if (info.on)
3040                 info.config.pvid = pvid;
3041         else {
3042                 info.config.reject.tagged =
3043                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3044                 info.config.reject.untagged =
3045                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3046         }
3047
3048         return i40e_vsi_vlan_pvid_set(vsi, &info);
3049 }
3050
3051 static int
3052 i40e_dev_led_on(struct rte_eth_dev *dev)
3053 {
3054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055         uint32_t mode = i40e_led_get(hw);
3056
3057         if (mode == 0)
3058                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3059
3060         return 0;
3061 }
3062
3063 static int
3064 i40e_dev_led_off(struct rte_eth_dev *dev)
3065 {
3066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067         uint32_t mode = i40e_led_get(hw);
3068
3069         if (mode != 0)
3070                 i40e_led_set(hw, 0, false);
3071
3072         return 0;
3073 }
3074
3075 static int
3076 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3077 {
3078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3080
3081         fc_conf->pause_time = pf->fc_conf.pause_time;
3082         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3083         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3084
3085          /* Return current mode according to actual setting*/
3086         switch (hw->fc.current_mode) {
3087         case I40E_FC_FULL:
3088                 fc_conf->mode = RTE_FC_FULL;
3089                 break;
3090         case I40E_FC_TX_PAUSE:
3091                 fc_conf->mode = RTE_FC_TX_PAUSE;
3092                 break;
3093         case I40E_FC_RX_PAUSE:
3094                 fc_conf->mode = RTE_FC_RX_PAUSE;
3095                 break;
3096         case I40E_FC_NONE:
3097         default:
3098                 fc_conf->mode = RTE_FC_NONE;
3099         };
3100
3101         return 0;
3102 }
3103
3104 static int
3105 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3106 {
3107         uint32_t mflcn_reg, fctrl_reg, reg;
3108         uint32_t max_high_water;
3109         uint8_t i, aq_failure;
3110         int err;
3111         struct i40e_hw *hw;
3112         struct i40e_pf *pf;
3113         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3114                 [RTE_FC_NONE] = I40E_FC_NONE,
3115                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3116                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3117                 [RTE_FC_FULL] = I40E_FC_FULL
3118         };
3119
3120         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3121
3122         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3123         if ((fc_conf->high_water > max_high_water) ||
3124                         (fc_conf->high_water < fc_conf->low_water)) {
3125                 PMD_INIT_LOG(ERR,
3126                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3127                         max_high_water);
3128                 return -EINVAL;
3129         }
3130
3131         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3133         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3134
3135         pf->fc_conf.pause_time = fc_conf->pause_time;
3136         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3137         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3138
3139         PMD_INIT_FUNC_TRACE();
3140
3141         /* All the link flow control related enable/disable register
3142          * configuration is handle by the F/W
3143          */
3144         err = i40e_set_fc(hw, &aq_failure, true);
3145         if (err < 0)
3146                 return -ENOSYS;
3147
3148         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3149                 /* Configure flow control refresh threshold,
3150                  * the value for stat_tx_pause_refresh_timer[8]
3151                  * is used for global pause operation.
3152                  */
3153
3154                 I40E_WRITE_REG(hw,
3155                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3156                                pf->fc_conf.pause_time);
3157
3158                 /* configure the timer value included in transmitted pause
3159                  * frame,
3160                  * the value for stat_tx_pause_quanta[8] is used for global
3161                  * pause operation
3162                  */
3163                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3164                                pf->fc_conf.pause_time);
3165
3166                 fctrl_reg = I40E_READ_REG(hw,
3167                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3168
3169                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3170                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3171                 else
3172                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3173
3174                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3175                                fctrl_reg);
3176         } else {
3177                 /* Configure pause time (2 TCs per register) */
3178                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3179                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3180                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3181
3182                 /* Configure flow control refresh threshold value */
3183                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3184                                pf->fc_conf.pause_time / 2);
3185
3186                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3187
3188                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3189                  *depending on configuration
3190                  */
3191                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3192                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3193                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3194                 } else {
3195                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3196                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3197                 }
3198
3199                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3200         }
3201
3202         /* config the water marker both based on the packets and bytes */
3203         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3204                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3205                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3206         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3207                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3208                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3209         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3210                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3211                        << I40E_KILOSHIFT);
3212         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3213                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3214                        << I40E_KILOSHIFT);
3215
3216         I40E_WRITE_FLUSH(hw);
3217
3218         return 0;
3219 }
3220
3221 static int
3222 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3223                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3224 {
3225         PMD_INIT_FUNC_TRACE();
3226
3227         return -ENOSYS;
3228 }
3229
3230 /* Add a MAC address, and update filters */
3231 static void
3232 i40e_macaddr_add(struct rte_eth_dev *dev,
3233                  struct ether_addr *mac_addr,
3234                  __rte_unused uint32_t index,
3235                  uint32_t pool)
3236 {
3237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3238         struct i40e_mac_filter_info mac_filter;
3239         struct i40e_vsi *vsi;
3240         int ret;
3241
3242         /* If VMDQ not enabled or configured, return */
3243         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3244                           !pf->nb_cfg_vmdq_vsi)) {
3245                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3246                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3247                         pool);
3248                 return;
3249         }
3250
3251         if (pool > pf->nb_cfg_vmdq_vsi) {
3252                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3253                                 pool, pf->nb_cfg_vmdq_vsi);
3254                 return;
3255         }
3256
3257         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3258         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3259                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3260         else
3261                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3262
3263         if (pool == 0)
3264                 vsi = pf->main_vsi;
3265         else
3266                 vsi = pf->vmdq[pool - 1].vsi;
3267
3268         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3269         if (ret != I40E_SUCCESS) {
3270                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3271                 return;
3272         }
3273 }
3274
3275 /* Remove a MAC address, and update filters */
3276 static void
3277 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3278 {
3279         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280         struct i40e_vsi *vsi;
3281         struct rte_eth_dev_data *data = dev->data;
3282         struct ether_addr *macaddr;
3283         int ret;
3284         uint32_t i;
3285         uint64_t pool_sel;
3286
3287         macaddr = &(data->mac_addrs[index]);
3288
3289         pool_sel = dev->data->mac_pool_sel[index];
3290
3291         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3292                 if (pool_sel & (1ULL << i)) {
3293                         if (i == 0)
3294                                 vsi = pf->main_vsi;
3295                         else {
3296                                 /* No VMDQ pool enabled or configured */
3297                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3298                                         (i > pf->nb_cfg_vmdq_vsi)) {
3299                                         PMD_DRV_LOG(ERR,
3300                                                 "No VMDQ pool enabled/configured");
3301                                         return;
3302                                 }
3303                                 vsi = pf->vmdq[i - 1].vsi;
3304                         }
3305                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3306
3307                         if (ret) {
3308                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3309                                 return;
3310                         }
3311                 }
3312         }
3313 }
3314
3315 /* Set perfect match or hash match of MAC and VLAN for a VF */
3316 static int
3317 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3318                  struct rte_eth_mac_filter *filter,
3319                  bool add)
3320 {
3321         struct i40e_hw *hw;
3322         struct i40e_mac_filter_info mac_filter;
3323         struct ether_addr old_mac;
3324         struct ether_addr *new_mac;
3325         struct i40e_pf_vf *vf = NULL;
3326         uint16_t vf_id;
3327         int ret;
3328
3329         if (pf == NULL) {
3330                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3331                 return -EINVAL;
3332         }
3333         hw = I40E_PF_TO_HW(pf);
3334
3335         if (filter == NULL) {
3336                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3337                 return -EINVAL;
3338         }
3339
3340         new_mac = &filter->mac_addr;
3341
3342         if (is_zero_ether_addr(new_mac)) {
3343                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3344                 return -EINVAL;
3345         }
3346
3347         vf_id = filter->dst_id;
3348
3349         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3350                 PMD_DRV_LOG(ERR, "Invalid argument.");
3351                 return -EINVAL;
3352         }
3353         vf = &pf->vfs[vf_id];
3354
3355         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3356                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3357                 return -EINVAL;
3358         }
3359
3360         if (add) {
3361                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3362                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3363                                 ETHER_ADDR_LEN);
3364                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3365                                  ETHER_ADDR_LEN);
3366
3367                 mac_filter.filter_type = filter->filter_type;
3368                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3369                 if (ret != I40E_SUCCESS) {
3370                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3371                         return -1;
3372                 }
3373                 ether_addr_copy(new_mac, &pf->dev_addr);
3374         } else {
3375                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3376                                 ETHER_ADDR_LEN);
3377                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3378                 if (ret != I40E_SUCCESS) {
3379                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3380                         return -1;
3381                 }
3382
3383                 /* Clear device address as it has been removed */
3384                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3385                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3386         }
3387
3388         return 0;
3389 }
3390
3391 /* MAC filter handle */
3392 static int
3393 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3394                 void *arg)
3395 {
3396         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3397         struct rte_eth_mac_filter *filter;
3398         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3399         int ret = I40E_NOT_SUPPORTED;
3400
3401         filter = (struct rte_eth_mac_filter *)(arg);
3402
3403         switch (filter_op) {
3404         case RTE_ETH_FILTER_NOP:
3405                 ret = I40E_SUCCESS;
3406                 break;
3407         case RTE_ETH_FILTER_ADD:
3408                 i40e_pf_disable_irq0(hw);
3409                 if (filter->is_vf)
3410                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3411                 i40e_pf_enable_irq0(hw);
3412                 break;
3413         case RTE_ETH_FILTER_DELETE:
3414                 i40e_pf_disable_irq0(hw);
3415                 if (filter->is_vf)
3416                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3417                 i40e_pf_enable_irq0(hw);
3418                 break;
3419         default:
3420                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3421                 ret = I40E_ERR_PARAM;
3422                 break;
3423         }
3424
3425         return ret;
3426 }
3427
3428 static int
3429 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3430 {
3431         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3432         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3433         int ret;
3434
3435         if (!lut)
3436                 return -EINVAL;
3437
3438         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3439                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3440                                           lut, lut_size);
3441                 if (ret) {
3442                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3443                         return ret;
3444                 }
3445         } else {
3446                 uint32_t *lut_dw = (uint32_t *)lut;
3447                 uint16_t i, lut_size_dw = lut_size / 4;
3448
3449                 for (i = 0; i < lut_size_dw; i++)
3450                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3451         }
3452
3453         return 0;
3454 }
3455
3456 static int
3457 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3458 {
3459         struct i40e_pf *pf;
3460         struct i40e_hw *hw;
3461         int ret;
3462
3463         if (!vsi || !lut)
3464                 return -EINVAL;
3465
3466         pf = I40E_VSI_TO_PF(vsi);
3467         hw = I40E_VSI_TO_HW(vsi);
3468
3469         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3470                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3471                                           lut, lut_size);
3472                 if (ret) {
3473                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3474                         return ret;
3475                 }
3476         } else {
3477                 uint32_t *lut_dw = (uint32_t *)lut;
3478                 uint16_t i, lut_size_dw = lut_size / 4;
3479
3480                 for (i = 0; i < lut_size_dw; i++)
3481                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3482                 I40E_WRITE_FLUSH(hw);
3483         }
3484
3485         return 0;
3486 }
3487
3488 static int
3489 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3490                          struct rte_eth_rss_reta_entry64 *reta_conf,
3491                          uint16_t reta_size)
3492 {
3493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3494         uint16_t i, lut_size = pf->hash_lut_size;
3495         uint16_t idx, shift;
3496         uint8_t *lut;
3497         int ret;
3498
3499         if (reta_size != lut_size ||
3500                 reta_size > ETH_RSS_RETA_SIZE_512) {
3501                 PMD_DRV_LOG(ERR,
3502                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3503                         reta_size, lut_size);
3504                 return -EINVAL;
3505         }
3506
3507         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3508         if (!lut) {
3509                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3510                 return -ENOMEM;
3511         }
3512         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3513         if (ret)
3514                 goto out;
3515         for (i = 0; i < reta_size; i++) {
3516                 idx = i / RTE_RETA_GROUP_SIZE;
3517                 shift = i % RTE_RETA_GROUP_SIZE;
3518                 if (reta_conf[idx].mask & (1ULL << shift))
3519                         lut[i] = reta_conf[idx].reta[shift];
3520         }
3521         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3522
3523 out:
3524         rte_free(lut);
3525
3526         return ret;
3527 }
3528
3529 static int
3530 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3531                         struct rte_eth_rss_reta_entry64 *reta_conf,
3532                         uint16_t reta_size)
3533 {
3534         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3535         uint16_t i, lut_size = pf->hash_lut_size;
3536         uint16_t idx, shift;
3537         uint8_t *lut;
3538         int ret;
3539
3540         if (reta_size != lut_size ||
3541                 reta_size > ETH_RSS_RETA_SIZE_512) {
3542                 PMD_DRV_LOG(ERR,
3543                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3544                         reta_size, lut_size);
3545                 return -EINVAL;
3546         }
3547
3548         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3549         if (!lut) {
3550                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3551                 return -ENOMEM;
3552         }
3553
3554         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3555         if (ret)
3556                 goto out;
3557         for (i = 0; i < reta_size; i++) {
3558                 idx = i / RTE_RETA_GROUP_SIZE;
3559                 shift = i % RTE_RETA_GROUP_SIZE;
3560                 if (reta_conf[idx].mask & (1ULL << shift))
3561                         reta_conf[idx].reta[shift] = lut[i];
3562         }
3563
3564 out:
3565         rte_free(lut);
3566
3567         return ret;
3568 }
3569
3570 /**
3571  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3572  * @hw:   pointer to the HW structure
3573  * @mem:  pointer to mem struct to fill out
3574  * @size: size of memory requested
3575  * @alignment: what to align the allocation to
3576  **/
3577 enum i40e_status_code
3578 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3579                         struct i40e_dma_mem *mem,
3580                         u64 size,
3581                         u32 alignment)
3582 {
3583         const struct rte_memzone *mz = NULL;
3584         char z_name[RTE_MEMZONE_NAMESIZE];
3585
3586         if (!mem)
3587                 return I40E_ERR_PARAM;
3588
3589         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3590         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3591                                          alignment, RTE_PGSIZE_2M);
3592         if (!mz)
3593                 return I40E_ERR_NO_MEMORY;
3594
3595         mem->size = size;
3596         mem->va = mz->addr;
3597         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3598         mem->zone = (const void *)mz;
3599         PMD_DRV_LOG(DEBUG,
3600                 "memzone %s allocated with physical address: %"PRIu64,
3601                 mz->name, mem->pa);
3602
3603         return I40E_SUCCESS;
3604 }
3605
3606 /**
3607  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3608  * @hw:   pointer to the HW structure
3609  * @mem:  ptr to mem struct to free
3610  **/
3611 enum i40e_status_code
3612 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3613                     struct i40e_dma_mem *mem)
3614 {
3615         if (!mem)
3616                 return I40E_ERR_PARAM;
3617
3618         PMD_DRV_LOG(DEBUG,
3619                 "memzone %s to be freed with physical address: %"PRIu64,
3620                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3621         rte_memzone_free((const struct rte_memzone *)mem->zone);
3622         mem->zone = NULL;
3623         mem->va = NULL;
3624         mem->pa = (u64)0;
3625
3626         return I40E_SUCCESS;
3627 }
3628
3629 /**
3630  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3631  * @hw:   pointer to the HW structure
3632  * @mem:  pointer to mem struct to fill out
3633  * @size: size of memory requested
3634  **/
3635 enum i40e_status_code
3636 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3637                          struct i40e_virt_mem *mem,
3638                          u32 size)
3639 {
3640         if (!mem)
3641                 return I40E_ERR_PARAM;
3642
3643         mem->size = size;
3644         mem->va = rte_zmalloc("i40e", size, 0);
3645
3646         if (mem->va)
3647                 return I40E_SUCCESS;
3648         else
3649                 return I40E_ERR_NO_MEMORY;
3650 }
3651
3652 /**
3653  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3654  * @hw:   pointer to the HW structure
3655  * @mem:  pointer to mem struct to free
3656  **/
3657 enum i40e_status_code
3658 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3659                      struct i40e_virt_mem *mem)
3660 {
3661         if (!mem)
3662                 return I40E_ERR_PARAM;
3663
3664         rte_free(mem->va);
3665         mem->va = NULL;
3666
3667         return I40E_SUCCESS;
3668 }
3669
3670 void
3671 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3672 {
3673         rte_spinlock_init(&sp->spinlock);
3674 }
3675
3676 void
3677 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3678 {
3679         rte_spinlock_lock(&sp->spinlock);
3680 }
3681
3682 void
3683 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3684 {
3685         rte_spinlock_unlock(&sp->spinlock);
3686 }
3687
3688 void
3689 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3690 {
3691         return;
3692 }
3693
3694 /**
3695  * Get the hardware capabilities, which will be parsed
3696  * and saved into struct i40e_hw.
3697  */
3698 static int
3699 i40e_get_cap(struct i40e_hw *hw)
3700 {
3701         struct i40e_aqc_list_capabilities_element_resp *buf;
3702         uint16_t len, size = 0;
3703         int ret;
3704
3705         /* Calculate a huge enough buff for saving response data temporarily */
3706         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3707                                                 I40E_MAX_CAP_ELE_NUM;
3708         buf = rte_zmalloc("i40e", len, 0);
3709         if (!buf) {
3710                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3711                 return I40E_ERR_NO_MEMORY;
3712         }
3713
3714         /* Get, parse the capabilities and save it to hw */
3715         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3716                         i40e_aqc_opc_list_func_capabilities, NULL);
3717         if (ret != I40E_SUCCESS)
3718                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3719
3720         /* Free the temporary buffer after being used */
3721         rte_free(buf);
3722
3723         return ret;
3724 }
3725
3726 static int
3727 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3728 {
3729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3731         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3732         uint16_t qp_count = 0, vsi_count = 0;
3733
3734         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3735                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3736                 return -EINVAL;
3737         }
3738         /* Add the parameter init for LFC */
3739         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3740         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3741         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3742
3743         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3744         pf->max_num_vsi = hw->func_caps.num_vsis;
3745         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3746         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3747         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3748
3749         /* FDir queue/VSI allocation */
3750         pf->fdir_qp_offset = 0;
3751         if (hw->func_caps.fd) {
3752                 pf->flags |= I40E_FLAG_FDIR;
3753                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3754         } else {
3755                 pf->fdir_nb_qps = 0;
3756         }
3757         qp_count += pf->fdir_nb_qps;
3758         vsi_count += 1;
3759
3760         /* LAN queue/VSI allocation */
3761         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3762         if (!hw->func_caps.rss) {
3763                 pf->lan_nb_qps = 1;
3764         } else {
3765                 pf->flags |= I40E_FLAG_RSS;
3766                 if (hw->mac.type == I40E_MAC_X722)
3767                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3768                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3769         }
3770         qp_count += pf->lan_nb_qps;
3771         vsi_count += 1;
3772
3773         /* VF queue/VSI allocation */
3774         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3775         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3776                 pf->flags |= I40E_FLAG_SRIOV;
3777                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3778                 pf->vf_num = pci_dev->max_vfs;
3779                 PMD_DRV_LOG(DEBUG,
3780                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3781                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3782         } else {
3783                 pf->vf_nb_qps = 0;
3784                 pf->vf_num = 0;
3785         }
3786         qp_count += pf->vf_nb_qps * pf->vf_num;
3787         vsi_count += pf->vf_num;
3788
3789         /* VMDq queue/VSI allocation */
3790         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3791         pf->vmdq_nb_qps = 0;
3792         pf->max_nb_vmdq_vsi = 0;
3793         if (hw->func_caps.vmdq) {
3794                 if (qp_count < hw->func_caps.num_tx_qp &&
3795                         vsi_count < hw->func_caps.num_vsis) {
3796                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3797                                 qp_count) / pf->vmdq_nb_qp_max;
3798
3799                         /* Limit the maximum number of VMDq vsi to the maximum
3800                          * ethdev can support
3801                          */
3802                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3803                                 hw->func_caps.num_vsis - vsi_count);
3804                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3805                                 ETH_64_POOLS);
3806                         if (pf->max_nb_vmdq_vsi) {
3807                                 pf->flags |= I40E_FLAG_VMDQ;
3808                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3809                                 PMD_DRV_LOG(DEBUG,
3810                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3811                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3812                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3813                         } else {
3814                                 PMD_DRV_LOG(INFO,
3815                                         "No enough queues left for VMDq");
3816                         }
3817                 } else {
3818                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3819                 }
3820         }
3821         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3822         vsi_count += pf->max_nb_vmdq_vsi;
3823
3824         if (hw->func_caps.dcb)
3825                 pf->flags |= I40E_FLAG_DCB;
3826
3827         if (qp_count > hw->func_caps.num_tx_qp) {
3828                 PMD_DRV_LOG(ERR,
3829                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3830                         qp_count, hw->func_caps.num_tx_qp);
3831                 return -EINVAL;
3832         }
3833         if (vsi_count > hw->func_caps.num_vsis) {
3834                 PMD_DRV_LOG(ERR,
3835                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3836                         vsi_count, hw->func_caps.num_vsis);
3837                 return -EINVAL;
3838         }
3839
3840         return 0;
3841 }
3842
3843 static int
3844 i40e_pf_get_switch_config(struct i40e_pf *pf)
3845 {
3846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3847         struct i40e_aqc_get_switch_config_resp *switch_config;
3848         struct i40e_aqc_switch_config_element_resp *element;
3849         uint16_t start_seid = 0, num_reported;
3850         int ret;
3851
3852         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3853                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3854         if (!switch_config) {
3855                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3856                 return -ENOMEM;
3857         }
3858
3859         /* Get the switch configurations */
3860         ret = i40e_aq_get_switch_config(hw, switch_config,
3861                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3862         if (ret != I40E_SUCCESS) {
3863                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3864                 goto fail;
3865         }
3866         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3867         if (num_reported != 1) { /* The number should be 1 */
3868                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3869                 goto fail;
3870         }
3871
3872         /* Parse the switch configuration elements */
3873         element = &(switch_config->element[0]);
3874         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3875                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3876                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3877         } else
3878                 PMD_DRV_LOG(INFO, "Unknown element type");
3879
3880 fail:
3881         rte_free(switch_config);
3882
3883         return ret;
3884 }
3885
3886 static int
3887 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3888                         uint32_t num)
3889 {
3890         struct pool_entry *entry;
3891
3892         if (pool == NULL || num == 0)
3893                 return -EINVAL;
3894
3895         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3896         if (entry == NULL) {
3897                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3898                 return -ENOMEM;
3899         }
3900
3901         /* queue heap initialize */
3902         pool->num_free = num;
3903         pool->num_alloc = 0;
3904         pool->base = base;
3905         LIST_INIT(&pool->alloc_list);
3906         LIST_INIT(&pool->free_list);
3907
3908         /* Initialize element  */
3909         entry->base = 0;
3910         entry->len = num;
3911
3912         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3913         return 0;
3914 }
3915
3916 static void
3917 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3918 {
3919         struct pool_entry *entry, *next_entry;
3920
3921         if (pool == NULL)
3922                 return;
3923
3924         for (entry = LIST_FIRST(&pool->alloc_list);
3925                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3926                         entry = next_entry) {
3927                 LIST_REMOVE(entry, next);
3928                 rte_free(entry);
3929         }
3930
3931         for (entry = LIST_FIRST(&pool->free_list);
3932                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3933                         entry = next_entry) {
3934                 LIST_REMOVE(entry, next);
3935                 rte_free(entry);
3936         }
3937
3938         pool->num_free = 0;
3939         pool->num_alloc = 0;
3940         pool->base = 0;
3941         LIST_INIT(&pool->alloc_list);
3942         LIST_INIT(&pool->free_list);
3943 }
3944
3945 static int
3946 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3947                        uint32_t base)
3948 {
3949         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3950         uint32_t pool_offset;
3951         int insert;
3952
3953         if (pool == NULL) {
3954                 PMD_DRV_LOG(ERR, "Invalid parameter");
3955                 return -EINVAL;
3956         }
3957
3958         pool_offset = base - pool->base;
3959         /* Lookup in alloc list */
3960         LIST_FOREACH(entry, &pool->alloc_list, next) {
3961                 if (entry->base == pool_offset) {
3962                         valid_entry = entry;
3963                         LIST_REMOVE(entry, next);
3964                         break;
3965                 }
3966         }
3967
3968         /* Not find, return */
3969         if (valid_entry == NULL) {
3970                 PMD_DRV_LOG(ERR, "Failed to find entry");
3971                 return -EINVAL;
3972         }
3973
3974         /**
3975          * Found it, move it to free list  and try to merge.
3976          * In order to make merge easier, always sort it by qbase.
3977          * Find adjacent prev and last entries.
3978          */
3979         prev = next = NULL;
3980         LIST_FOREACH(entry, &pool->free_list, next) {
3981                 if (entry->base > valid_entry->base) {
3982                         next = entry;
3983                         break;
3984                 }
3985                 prev = entry;
3986         }
3987
3988         insert = 0;
3989         /* Try to merge with next one*/
3990         if (next != NULL) {
3991                 /* Merge with next one */
3992                 if (valid_entry->base + valid_entry->len == next->base) {
3993                         next->base = valid_entry->base;
3994                         next->len += valid_entry->len;
3995                         rte_free(valid_entry);
3996                         valid_entry = next;
3997                         insert = 1;
3998                 }
3999         }
4000
4001         if (prev != NULL) {
4002                 /* Merge with previous one */
4003                 if (prev->base + prev->len == valid_entry->base) {
4004                         prev->len += valid_entry->len;
4005                         /* If it merge with next one, remove next node */
4006                         if (insert == 1) {
4007                                 LIST_REMOVE(valid_entry, next);
4008                                 rte_free(valid_entry);
4009                         } else {
4010                                 rte_free(valid_entry);
4011                                 insert = 1;
4012                         }
4013                 }
4014         }
4015
4016         /* Not find any entry to merge, insert */
4017         if (insert == 0) {
4018                 if (prev != NULL)
4019                         LIST_INSERT_AFTER(prev, valid_entry, next);
4020                 else if (next != NULL)
4021                         LIST_INSERT_BEFORE(next, valid_entry, next);
4022                 else /* It's empty list, insert to head */
4023                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4024         }
4025
4026         pool->num_free += valid_entry->len;
4027         pool->num_alloc -= valid_entry->len;
4028
4029         return 0;
4030 }
4031
4032 static int
4033 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4034                        uint16_t num)
4035 {
4036         struct pool_entry *entry, *valid_entry;
4037
4038         if (pool == NULL || num == 0) {
4039                 PMD_DRV_LOG(ERR, "Invalid parameter");
4040                 return -EINVAL;
4041         }
4042
4043         if (pool->num_free < num) {
4044                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4045                             num, pool->num_free);
4046                 return -ENOMEM;
4047         }
4048
4049         valid_entry = NULL;
4050         /* Lookup  in free list and find most fit one */
4051         LIST_FOREACH(entry, &pool->free_list, next) {
4052                 if (entry->len >= num) {
4053                         /* Find best one */
4054                         if (entry->len == num) {
4055                                 valid_entry = entry;
4056                                 break;
4057                         }
4058                         if (valid_entry == NULL || valid_entry->len > entry->len)
4059                                 valid_entry = entry;
4060                 }
4061         }
4062
4063         /* Not find one to satisfy the request, return */
4064         if (valid_entry == NULL) {
4065                 PMD_DRV_LOG(ERR, "No valid entry found");
4066                 return -ENOMEM;
4067         }
4068         /**
4069          * The entry have equal queue number as requested,
4070          * remove it from alloc_list.
4071          */
4072         if (valid_entry->len == num) {
4073                 LIST_REMOVE(valid_entry, next);
4074         } else {
4075                 /**
4076                  * The entry have more numbers than requested,
4077                  * create a new entry for alloc_list and minus its
4078                  * queue base and number in free_list.
4079                  */
4080                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4081                 if (entry == NULL) {
4082                         PMD_DRV_LOG(ERR,
4083                                 "Failed to allocate memory for resource pool");
4084                         return -ENOMEM;
4085                 }
4086                 entry->base = valid_entry->base;
4087                 entry->len = num;
4088                 valid_entry->base += num;
4089                 valid_entry->len -= num;
4090                 valid_entry = entry;
4091         }
4092
4093         /* Insert it into alloc list, not sorted */
4094         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4095
4096         pool->num_free -= valid_entry->len;
4097         pool->num_alloc += valid_entry->len;
4098
4099         return valid_entry->base + pool->base;
4100 }
4101
4102 /**
4103  * bitmap_is_subset - Check whether src2 is subset of src1
4104  **/
4105 static inline int
4106 bitmap_is_subset(uint8_t src1, uint8_t src2)
4107 {
4108         return !((src1 ^ src2) & src2);
4109 }
4110
4111 static enum i40e_status_code
4112 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4113 {
4114         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4115
4116         /* If DCB is not supported, only default TC is supported */
4117         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4118                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4119                 return I40E_NOT_SUPPORTED;
4120         }
4121
4122         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4123                 PMD_DRV_LOG(ERR,
4124                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4125                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4126                 return I40E_NOT_SUPPORTED;
4127         }
4128         return I40E_SUCCESS;
4129 }
4130
4131 int
4132 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4133                                 struct i40e_vsi_vlan_pvid_info *info)
4134 {
4135         struct i40e_hw *hw;
4136         struct i40e_vsi_context ctxt;
4137         uint8_t vlan_flags = 0;
4138         int ret;
4139
4140         if (vsi == NULL || info == NULL) {
4141                 PMD_DRV_LOG(ERR, "invalid parameters");
4142                 return I40E_ERR_PARAM;
4143         }
4144
4145         if (info->on) {
4146                 vsi->info.pvid = info->config.pvid;
4147                 /**
4148                  * If insert pvid is enabled, only tagged pkts are
4149                  * allowed to be sent out.
4150                  */
4151                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4152                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4153         } else {
4154                 vsi->info.pvid = 0;
4155                 if (info->config.reject.tagged == 0)
4156                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4157
4158                 if (info->config.reject.untagged == 0)
4159                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4160         }
4161         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4162                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4163         vsi->info.port_vlan_flags |= vlan_flags;
4164         vsi->info.valid_sections =
4165                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4166         memset(&ctxt, 0, sizeof(ctxt));
4167         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4168         ctxt.seid = vsi->seid;
4169
4170         hw = I40E_VSI_TO_HW(vsi);
4171         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4172         if (ret != I40E_SUCCESS)
4173                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4174
4175         return ret;
4176 }
4177
4178 static int
4179 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4180 {
4181         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4182         int i, ret;
4183         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4184
4185         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4186         if (ret != I40E_SUCCESS)
4187                 return ret;
4188
4189         if (!vsi->seid) {
4190                 PMD_DRV_LOG(ERR, "seid not valid");
4191                 return -EINVAL;
4192         }
4193
4194         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4195         tc_bw_data.tc_valid_bits = enabled_tcmap;
4196         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4197                 tc_bw_data.tc_bw_credits[i] =
4198                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4199
4200         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4201         if (ret != I40E_SUCCESS) {
4202                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4203                 return ret;
4204         }
4205
4206         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4207                                         sizeof(vsi->info.qs_handle));
4208         return I40E_SUCCESS;
4209 }
4210
4211 static enum i40e_status_code
4212 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4213                                  struct i40e_aqc_vsi_properties_data *info,
4214                                  uint8_t enabled_tcmap)
4215 {
4216         enum i40e_status_code ret;
4217         int i, total_tc = 0;
4218         uint16_t qpnum_per_tc, bsf, qp_idx;
4219
4220         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4221         if (ret != I40E_SUCCESS)
4222                 return ret;
4223
4224         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4225                 if (enabled_tcmap & (1 << i))
4226                         total_tc++;
4227         vsi->enabled_tc = enabled_tcmap;
4228
4229         /* Number of queues per enabled TC */
4230         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4231         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4232         bsf = rte_bsf32(qpnum_per_tc);
4233
4234         /* Adjust the queue number to actual queues that can be applied */
4235         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4236                 vsi->nb_qps = qpnum_per_tc * total_tc;
4237
4238         /**
4239          * Configure TC and queue mapping parameters, for enabled TC,
4240          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4241          * default queue will serve it.
4242          */
4243         qp_idx = 0;
4244         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4245                 if (vsi->enabled_tc & (1 << i)) {
4246                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4247                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4248                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4249                         qp_idx += qpnum_per_tc;
4250                 } else
4251                         info->tc_mapping[i] = 0;
4252         }
4253
4254         /* Associate queue number with VSI */
4255         if (vsi->type == I40E_VSI_SRIOV) {
4256                 info->mapping_flags |=
4257                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4258                 for (i = 0; i < vsi->nb_qps; i++)
4259                         info->queue_mapping[i] =
4260                                 rte_cpu_to_le_16(vsi->base_queue + i);
4261         } else {
4262                 info->mapping_flags |=
4263                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4264                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4265         }
4266         info->valid_sections |=
4267                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4268
4269         return I40E_SUCCESS;
4270 }
4271
4272 static int
4273 i40e_veb_release(struct i40e_veb *veb)
4274 {
4275         struct i40e_vsi *vsi;
4276         struct i40e_hw *hw;
4277
4278         if (veb == NULL)
4279                 return -EINVAL;
4280
4281         if (!TAILQ_EMPTY(&veb->head)) {
4282                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4283                 return -EACCES;
4284         }
4285         /* associate_vsi field is NULL for floating VEB */
4286         if (veb->associate_vsi != NULL) {
4287                 vsi = veb->associate_vsi;
4288                 hw = I40E_VSI_TO_HW(vsi);
4289
4290                 vsi->uplink_seid = veb->uplink_seid;
4291                 vsi->veb = NULL;
4292         } else {
4293                 veb->associate_pf->main_vsi->floating_veb = NULL;
4294                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4295         }
4296
4297         i40e_aq_delete_element(hw, veb->seid, NULL);
4298         rte_free(veb);
4299         return I40E_SUCCESS;
4300 }
4301
4302 /* Setup a veb */
4303 static struct i40e_veb *
4304 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4305 {
4306         struct i40e_veb *veb;
4307         int ret;
4308         struct i40e_hw *hw;
4309
4310         if (pf == NULL) {
4311                 PMD_DRV_LOG(ERR,
4312                             "veb setup failed, associated PF shouldn't null");
4313                 return NULL;
4314         }
4315         hw = I40E_PF_TO_HW(pf);
4316
4317         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4318         if (!veb) {
4319                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4320                 goto fail;
4321         }
4322
4323         veb->associate_vsi = vsi;
4324         veb->associate_pf = pf;
4325         TAILQ_INIT(&veb->head);
4326         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4327
4328         /* create floating veb if vsi is NULL */
4329         if (vsi != NULL) {
4330                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4331                                       I40E_DEFAULT_TCMAP, false,
4332                                       &veb->seid, false, NULL);
4333         } else {
4334                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4335                                       true, &veb->seid, false, NULL);
4336         }
4337
4338         if (ret != I40E_SUCCESS) {
4339                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4340                             hw->aq.asq_last_status);
4341                 goto fail;
4342         }
4343
4344         /* get statistics index */
4345         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4346                                 &veb->stats_idx, NULL, NULL, NULL);
4347         if (ret != I40E_SUCCESS) {
4348                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4349                             hw->aq.asq_last_status);
4350                 goto fail;
4351         }
4352         /* Get VEB bandwidth, to be implemented */
4353         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4354         if (vsi)
4355                 vsi->uplink_seid = veb->seid;
4356
4357         return veb;
4358 fail:
4359         rte_free(veb);
4360         return NULL;
4361 }
4362
4363 int
4364 i40e_vsi_release(struct i40e_vsi *vsi)
4365 {
4366         struct i40e_pf *pf;
4367         struct i40e_hw *hw;
4368         struct i40e_vsi_list *vsi_list;
4369         void *temp;
4370         int ret;
4371         struct i40e_mac_filter *f;
4372         uint16_t user_param;
4373
4374         if (!vsi)
4375                 return I40E_SUCCESS;
4376
4377         user_param = vsi->user_param;
4378
4379         pf = I40E_VSI_TO_PF(vsi);
4380         hw = I40E_VSI_TO_HW(vsi);
4381
4382         /* VSI has child to attach, release child first */
4383         if (vsi->veb) {
4384                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4385                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4386                                 return -1;
4387                 }
4388                 i40e_veb_release(vsi->veb);
4389         }
4390
4391         if (vsi->floating_veb) {
4392                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4393                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4394                                 return -1;
4395                 }
4396         }
4397
4398         /* Remove all macvlan filters of the VSI */
4399         i40e_vsi_remove_all_macvlan_filter(vsi);
4400         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4401                 rte_free(f);
4402
4403         if (vsi->type != I40E_VSI_MAIN &&
4404             ((vsi->type != I40E_VSI_SRIOV) ||
4405             !pf->floating_veb_list[user_param])) {
4406                 /* Remove vsi from parent's sibling list */
4407                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4408                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4409                         return I40E_ERR_PARAM;
4410                 }
4411                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4412                                 &vsi->sib_vsi_list, list);
4413
4414                 /* Remove all switch element of the VSI */
4415                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4416                 if (ret != I40E_SUCCESS)
4417                         PMD_DRV_LOG(ERR, "Failed to delete element");
4418         }
4419
4420         if ((vsi->type == I40E_VSI_SRIOV) &&
4421             pf->floating_veb_list[user_param]) {
4422                 /* Remove vsi from parent's sibling list */
4423                 if (vsi->parent_vsi == NULL ||
4424                     vsi->parent_vsi->floating_veb == NULL) {
4425                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4426                         return I40E_ERR_PARAM;
4427                 }
4428                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4429                              &vsi->sib_vsi_list, list);
4430
4431                 /* Remove all switch element of the VSI */
4432                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4433                 if (ret != I40E_SUCCESS)
4434                         PMD_DRV_LOG(ERR, "Failed to delete element");
4435         }
4436
4437         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4438
4439         if (vsi->type != I40E_VSI_SRIOV)
4440                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4441         rte_free(vsi);
4442
4443         return I40E_SUCCESS;
4444 }
4445
4446 static int
4447 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4448 {
4449         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4450         struct i40e_aqc_remove_macvlan_element_data def_filter;
4451         struct i40e_mac_filter_info filter;
4452         int ret;
4453
4454         if (vsi->type != I40E_VSI_MAIN)
4455                 return I40E_ERR_CONFIG;
4456         memset(&def_filter, 0, sizeof(def_filter));
4457         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4458                                         ETH_ADDR_LEN);
4459         def_filter.vlan_tag = 0;
4460         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4461                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4462         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4463         if (ret != I40E_SUCCESS) {
4464                 struct i40e_mac_filter *f;
4465                 struct ether_addr *mac;
4466
4467                 PMD_DRV_LOG(WARNING,
4468                         "Cannot remove the default macvlan filter");
4469                 /* It needs to add the permanent mac into mac list */
4470                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4471                 if (f == NULL) {
4472                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4473                         return I40E_ERR_NO_MEMORY;
4474                 }
4475                 mac = &f->mac_info.mac_addr;
4476                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4477                                 ETH_ADDR_LEN);
4478                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4479                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4480                 vsi->mac_num++;
4481
4482                 return ret;
4483         }
4484         (void)rte_memcpy(&filter.mac_addr,
4485                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4486         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4487         return i40e_vsi_add_mac(vsi, &filter);
4488 }
4489
4490 /*
4491  * i40e_vsi_get_bw_config - Query VSI BW Information
4492  * @vsi: the VSI to be queried
4493  *
4494  * Returns 0 on success, negative value on failure
4495  */
4496 static enum i40e_status_code
4497 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4498 {
4499         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4500         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4501         struct i40e_hw *hw = &vsi->adapter->hw;
4502         i40e_status ret;
4503         int i;
4504         uint32_t bw_max;
4505
4506         memset(&bw_config, 0, sizeof(bw_config));
4507         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4508         if (ret != I40E_SUCCESS) {
4509                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4510                             hw->aq.asq_last_status);
4511                 return ret;
4512         }
4513
4514         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4515         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4516                                         &ets_sla_config, NULL);
4517         if (ret != I40E_SUCCESS) {
4518                 PMD_DRV_LOG(ERR,
4519                         "VSI failed to get TC bandwdith configuration %u",
4520                         hw->aq.asq_last_status);
4521                 return ret;
4522         }
4523
4524         /* store and print out BW info */
4525         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4526         vsi->bw_info.bw_max = bw_config.max_bw;
4527         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4528         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4529         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4530                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4531                      I40E_16_BIT_WIDTH);
4532         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4533                 vsi->bw_info.bw_ets_share_credits[i] =
4534                                 ets_sla_config.share_credits[i];
4535                 vsi->bw_info.bw_ets_credits[i] =
4536                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4537                 /* 4 bits per TC, 4th bit is reserved */
4538                 vsi->bw_info.bw_ets_max[i] =
4539                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4540                                   RTE_LEN2MASK(3, uint8_t));
4541                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4542                             vsi->bw_info.bw_ets_share_credits[i]);
4543                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4544                             vsi->bw_info.bw_ets_credits[i]);
4545                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4546                             vsi->bw_info.bw_ets_max[i]);
4547         }
4548
4549         return I40E_SUCCESS;
4550 }
4551
4552 /* i40e_enable_pf_lb
4553  * @pf: pointer to the pf structure
4554  *
4555  * allow loopback on pf
4556  */
4557 static inline void
4558 i40e_enable_pf_lb(struct i40e_pf *pf)
4559 {
4560         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4561         struct i40e_vsi_context ctxt;
4562         int ret;
4563
4564         /* Use the FW API if FW >= v5.0 */
4565         if (hw->aq.fw_maj_ver < 5) {
4566                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4567                 return;
4568         }
4569
4570         memset(&ctxt, 0, sizeof(ctxt));
4571         ctxt.seid = pf->main_vsi_seid;
4572         ctxt.pf_num = hw->pf_id;
4573         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4574         if (ret) {
4575                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4576                             ret, hw->aq.asq_last_status);
4577                 return;
4578         }
4579         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4580         ctxt.info.valid_sections =
4581                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4582         ctxt.info.switch_id |=
4583                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4584
4585         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4586         if (ret)
4587                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4588                             hw->aq.asq_last_status);
4589 }
4590
4591 /* Setup a VSI */
4592 struct i40e_vsi *
4593 i40e_vsi_setup(struct i40e_pf *pf,
4594                enum i40e_vsi_type type,
4595                struct i40e_vsi *uplink_vsi,
4596                uint16_t user_param)
4597 {
4598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4599         struct i40e_vsi *vsi;
4600         struct i40e_mac_filter_info filter;
4601         int ret;
4602         struct i40e_vsi_context ctxt;
4603         struct ether_addr broadcast =
4604                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4605
4606         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4607             uplink_vsi == NULL) {
4608                 PMD_DRV_LOG(ERR,
4609                         "VSI setup failed, VSI link shouldn't be NULL");
4610                 return NULL;
4611         }
4612
4613         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4614                 PMD_DRV_LOG(ERR,
4615                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4616                 return NULL;
4617         }
4618
4619         /* two situations
4620          * 1.type is not MAIN and uplink vsi is not NULL
4621          * If uplink vsi didn't setup VEB, create one first under veb field
4622          * 2.type is SRIOV and the uplink is NULL
4623          * If floating VEB is NULL, create one veb under floating veb field
4624          */
4625
4626         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4627             uplink_vsi->veb == NULL) {
4628                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4629
4630                 if (uplink_vsi->veb == NULL) {
4631                         PMD_DRV_LOG(ERR, "VEB setup failed");
4632                         return NULL;
4633                 }
4634                 /* set ALLOWLOOPBACk on pf, when veb is created */
4635                 i40e_enable_pf_lb(pf);
4636         }
4637
4638         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4639             pf->main_vsi->floating_veb == NULL) {
4640                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4641
4642                 if (pf->main_vsi->floating_veb == NULL) {
4643                         PMD_DRV_LOG(ERR, "VEB setup failed");
4644                         return NULL;
4645                 }
4646         }
4647
4648         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4649         if (!vsi) {
4650                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4651                 return NULL;
4652         }
4653         TAILQ_INIT(&vsi->mac_list);
4654         vsi->type = type;
4655         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4656         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4657         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4658         vsi->user_param = user_param;
4659         vsi->vlan_anti_spoof_on = 0;
4660         /* Allocate queues */
4661         switch (vsi->type) {
4662         case I40E_VSI_MAIN  :
4663                 vsi->nb_qps = pf->lan_nb_qps;
4664                 break;
4665         case I40E_VSI_SRIOV :
4666                 vsi->nb_qps = pf->vf_nb_qps;
4667                 break;
4668         case I40E_VSI_VMDQ2:
4669                 vsi->nb_qps = pf->vmdq_nb_qps;
4670                 break;
4671         case I40E_VSI_FDIR:
4672                 vsi->nb_qps = pf->fdir_nb_qps;
4673                 break;
4674         default:
4675                 goto fail_mem;
4676         }
4677         /*
4678          * The filter status descriptor is reported in rx queue 0,
4679          * while the tx queue for fdir filter programming has no
4680          * such constraints, can be non-zero queues.
4681          * To simplify it, choose FDIR vsi use queue 0 pair.
4682          * To make sure it will use queue 0 pair, queue allocation
4683          * need be done before this function is called
4684          */
4685         if (type != I40E_VSI_FDIR) {
4686                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4687                         if (ret < 0) {
4688                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4689                                                 vsi->seid, ret);
4690                                 goto fail_mem;
4691                         }
4692                         vsi->base_queue = ret;
4693         } else
4694                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4695
4696         /* VF has MSIX interrupt in VF range, don't allocate here */
4697         if (type == I40E_VSI_MAIN) {
4698                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4699                                           RTE_MIN(vsi->nb_qps,
4700                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4701                 if (ret < 0) {
4702                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4703                                     vsi->seid, ret);
4704                         goto fail_queue_alloc;
4705                 }
4706                 vsi->msix_intr = ret;
4707                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4708         } else if (type != I40E_VSI_SRIOV) {
4709                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4710                 if (ret < 0) {
4711                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4712                         goto fail_queue_alloc;
4713                 }
4714                 vsi->msix_intr = ret;
4715                 vsi->nb_msix = 1;
4716         } else {
4717                 vsi->msix_intr = 0;
4718                 vsi->nb_msix = 0;
4719         }
4720
4721         /* Add VSI */
4722         if (type == I40E_VSI_MAIN) {
4723                 /* For main VSI, no need to add since it's default one */
4724                 vsi->uplink_seid = pf->mac_seid;
4725                 vsi->seid = pf->main_vsi_seid;
4726                 /* Bind queues with specific MSIX interrupt */
4727                 /**
4728                  * Needs 2 interrupt at least, one for misc cause which will
4729                  * enabled from OS side, Another for queues binding the
4730                  * interrupt from device side only.
4731                  */
4732
4733                 /* Get default VSI parameters from hardware */
4734                 memset(&ctxt, 0, sizeof(ctxt));
4735                 ctxt.seid = vsi->seid;
4736                 ctxt.pf_num = hw->pf_id;
4737                 ctxt.uplink_seid = vsi->uplink_seid;
4738                 ctxt.vf_num = 0;
4739                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4740                 if (ret != I40E_SUCCESS) {
4741                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4742                         goto fail_msix_alloc;
4743                 }
4744                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4745                         sizeof(struct i40e_aqc_vsi_properties_data));
4746                 vsi->vsi_id = ctxt.vsi_number;
4747                 vsi->info.valid_sections = 0;
4748
4749                 /* Configure tc, enabled TC0 only */
4750                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4751                         I40E_SUCCESS) {
4752                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4753                         goto fail_msix_alloc;
4754                 }
4755
4756                 /* TC, queue mapping */
4757                 memset(&ctxt, 0, sizeof(ctxt));
4758                 vsi->info.valid_sections |=
4759                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4760                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4761                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4762                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4763                         sizeof(struct i40e_aqc_vsi_properties_data));
4764                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4765                                                 I40E_DEFAULT_TCMAP);
4766                 if (ret != I40E_SUCCESS) {
4767                         PMD_DRV_LOG(ERR,
4768                                 "Failed to configure TC queue mapping");
4769                         goto fail_msix_alloc;
4770                 }
4771                 ctxt.seid = vsi->seid;
4772                 ctxt.pf_num = hw->pf_id;
4773                 ctxt.uplink_seid = vsi->uplink_seid;
4774                 ctxt.vf_num = 0;
4775
4776                 /* Update VSI parameters */
4777                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4778                 if (ret != I40E_SUCCESS) {
4779                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4780                         goto fail_msix_alloc;
4781                 }
4782
4783                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4784                                                 sizeof(vsi->info.tc_mapping));
4785                 (void)rte_memcpy(&vsi->info.queue_mapping,
4786                                 &ctxt.info.queue_mapping,
4787                         sizeof(vsi->info.queue_mapping));
4788                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4789                 vsi->info.valid_sections = 0;
4790
4791                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4792                                 ETH_ADDR_LEN);
4793
4794                 /**
4795                  * Updating default filter settings are necessary to prevent
4796                  * reception of tagged packets.
4797                  * Some old firmware configurations load a default macvlan
4798                  * filter which accepts both tagged and untagged packets.
4799                  * The updating is to use a normal filter instead if needed.
4800                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4801                  * The firmware with correct configurations load the default
4802                  * macvlan filter which is expected and cannot be removed.
4803                  */
4804                 i40e_update_default_filter_setting(vsi);
4805                 i40e_config_qinq(hw, vsi);
4806         } else if (type == I40E_VSI_SRIOV) {
4807                 memset(&ctxt, 0, sizeof(ctxt));
4808                 /**
4809                  * For other VSI, the uplink_seid equals to uplink VSI's
4810                  * uplink_seid since they share same VEB
4811                  */
4812                 if (uplink_vsi == NULL)
4813                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4814                 else
4815                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4816                 ctxt.pf_num = hw->pf_id;
4817                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4818                 ctxt.uplink_seid = vsi->uplink_seid;
4819                 ctxt.connection_type = 0x1;
4820                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4821
4822                 /* Use the VEB configuration if FW >= v5.0 */
4823                 if (hw->aq.fw_maj_ver >= 5) {
4824                         /* Configure switch ID */
4825                         ctxt.info.valid_sections |=
4826                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4827                         ctxt.info.switch_id =
4828                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4829                 }
4830
4831                 /* Configure port/vlan */
4832                 ctxt.info.valid_sections |=
4833                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4834                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4835                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4836                                                 I40E_DEFAULT_TCMAP);
4837                 if (ret != I40E_SUCCESS) {
4838                         PMD_DRV_LOG(ERR,
4839                                 "Failed to configure TC queue mapping");
4840                         goto fail_msix_alloc;
4841                 }
4842                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4843                 ctxt.info.valid_sections |=
4844                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4845                 /**
4846                  * Since VSI is not created yet, only configure parameter,
4847                  * will add vsi below.
4848                  */
4849
4850                 i40e_config_qinq(hw, vsi);
4851         } else if (type == I40E_VSI_VMDQ2) {
4852                 memset(&ctxt, 0, sizeof(ctxt));
4853                 /*
4854                  * For other VSI, the uplink_seid equals to uplink VSI's
4855                  * uplink_seid since they share same VEB
4856                  */
4857                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4858                 ctxt.pf_num = hw->pf_id;
4859                 ctxt.vf_num = 0;
4860                 ctxt.uplink_seid = vsi->uplink_seid;
4861                 ctxt.connection_type = 0x1;
4862                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4863
4864                 ctxt.info.valid_sections |=
4865                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4866                 /* user_param carries flag to enable loop back */
4867                 if (user_param) {
4868                         ctxt.info.switch_id =
4869                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4870                         ctxt.info.switch_id |=
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4872                 }
4873
4874                 /* Configure port/vlan */
4875                 ctxt.info.valid_sections |=
4876                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4877                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4878                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4879                                                 I40E_DEFAULT_TCMAP);
4880                 if (ret != I40E_SUCCESS) {
4881                         PMD_DRV_LOG(ERR,
4882                                 "Failed to configure TC queue mapping");
4883                         goto fail_msix_alloc;
4884                 }
4885                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4886                 ctxt.info.valid_sections |=
4887                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4888         } else if (type == I40E_VSI_FDIR) {
4889                 memset(&ctxt, 0, sizeof(ctxt));
4890                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4891                 ctxt.pf_num = hw->pf_id;
4892                 ctxt.vf_num = 0;
4893                 ctxt.uplink_seid = vsi->uplink_seid;
4894                 ctxt.connection_type = 0x1;     /* regular data port */
4895                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4896                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4897                                                 I40E_DEFAULT_TCMAP);
4898                 if (ret != I40E_SUCCESS) {
4899                         PMD_DRV_LOG(ERR,
4900                                 "Failed to configure TC queue mapping.");
4901                         goto fail_msix_alloc;
4902                 }
4903                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4904                 ctxt.info.valid_sections |=
4905                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4906         } else {
4907                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4908                 goto fail_msix_alloc;
4909         }
4910
4911         if (vsi->type != I40E_VSI_MAIN) {
4912                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4913                 if (ret != I40E_SUCCESS) {
4914                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4915                                     hw->aq.asq_last_status);
4916                         goto fail_msix_alloc;
4917                 }
4918                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4919                 vsi->info.valid_sections = 0;
4920                 vsi->seid = ctxt.seid;
4921                 vsi->vsi_id = ctxt.vsi_number;
4922                 vsi->sib_vsi_list.vsi = vsi;
4923                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4924                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4925                                           &vsi->sib_vsi_list, list);
4926                 } else {
4927                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4928                                           &vsi->sib_vsi_list, list);
4929                 }
4930         }
4931
4932         /* MAC/VLAN configuration */
4933         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4934         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4935
4936         ret = i40e_vsi_add_mac(vsi, &filter);
4937         if (ret != I40E_SUCCESS) {
4938                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4939                 goto fail_msix_alloc;
4940         }
4941
4942         /* Get VSI BW information */
4943         i40e_vsi_get_bw_config(vsi);
4944         return vsi;
4945 fail_msix_alloc:
4946         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4947 fail_queue_alloc:
4948         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4949 fail_mem:
4950         rte_free(vsi);
4951         return NULL;
4952 }
4953
4954 /* Configure vlan filter on or off */
4955 int
4956 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4957 {
4958         int i, num;
4959         struct i40e_mac_filter *f;
4960         void *temp;
4961         struct i40e_mac_filter_info *mac_filter;
4962         enum rte_mac_filter_type desired_filter;
4963         int ret = I40E_SUCCESS;
4964
4965         if (on) {
4966                 /* Filter to match MAC and VLAN */
4967                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4968         } else {
4969                 /* Filter to match only MAC */
4970                 desired_filter = RTE_MAC_PERFECT_MATCH;
4971         }
4972
4973         num = vsi->mac_num;
4974
4975         mac_filter = rte_zmalloc("mac_filter_info_data",
4976                                  num * sizeof(*mac_filter), 0);
4977         if (mac_filter == NULL) {
4978                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4979                 return I40E_ERR_NO_MEMORY;
4980         }
4981
4982         i = 0;
4983
4984         /* Remove all existing mac */
4985         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4986                 mac_filter[i] = f->mac_info;
4987                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4988                 if (ret) {
4989                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4990                                     on ? "enable" : "disable");
4991                         goto DONE;
4992                 }
4993                 i++;
4994         }
4995
4996         /* Override with new filter */
4997         for (i = 0; i < num; i++) {
4998                 mac_filter[i].filter_type = desired_filter;
4999                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5000                 if (ret) {
5001                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5002                                     on ? "enable" : "disable");
5003                         goto DONE;
5004                 }
5005         }
5006
5007 DONE:
5008         rte_free(mac_filter);
5009         return ret;
5010 }
5011
5012 /* Configure vlan stripping on or off */
5013 int
5014 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5015 {
5016         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5017         struct i40e_vsi_context ctxt;
5018         uint8_t vlan_flags;
5019         int ret = I40E_SUCCESS;
5020
5021         /* Check if it has been already on or off */
5022         if (vsi->info.valid_sections &
5023                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5024                 if (on) {
5025                         if ((vsi->info.port_vlan_flags &
5026                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5027                                 return 0; /* already on */
5028                 } else {
5029                         if ((vsi->info.port_vlan_flags &
5030                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5031                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5032                                 return 0; /* already off */
5033                 }
5034         }
5035
5036         if (on)
5037                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5038         else
5039                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5040         vsi->info.valid_sections =
5041                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5042         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5043         vsi->info.port_vlan_flags |= vlan_flags;
5044         ctxt.seid = vsi->seid;
5045         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5046         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5047         if (ret)
5048                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5049                             on ? "enable" : "disable");
5050
5051         return ret;
5052 }
5053
5054 static int
5055 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5056 {
5057         struct rte_eth_dev_data *data = dev->data;
5058         int ret;
5059         int mask = 0;
5060
5061         /* Apply vlan offload setting */
5062         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5063         i40e_vlan_offload_set(dev, mask);
5064
5065         /* Apply double-vlan setting, not implemented yet */
5066
5067         /* Apply pvid setting */
5068         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5069                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5070         if (ret)
5071                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5072
5073         return ret;
5074 }
5075
5076 static int
5077 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5078 {
5079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5080
5081         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5082 }
5083
5084 static int
5085 i40e_update_flow_control(struct i40e_hw *hw)
5086 {
5087 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5088         struct i40e_link_status link_status;
5089         uint32_t rxfc = 0, txfc = 0, reg;
5090         uint8_t an_info;
5091         int ret;
5092
5093         memset(&link_status, 0, sizeof(link_status));
5094         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5095         if (ret != I40E_SUCCESS) {
5096                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5097                 goto write_reg; /* Disable flow control */
5098         }
5099
5100         an_info = hw->phy.link_info.an_info;
5101         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5102                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5103                 ret = I40E_ERR_NOT_READY;
5104                 goto write_reg; /* Disable flow control */
5105         }
5106         /**
5107          * If link auto negotiation is enabled, flow control needs to
5108          * be configured according to it
5109          */
5110         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5111         case I40E_LINK_PAUSE_RXTX:
5112                 rxfc = 1;
5113                 txfc = 1;
5114                 hw->fc.current_mode = I40E_FC_FULL;
5115                 break;
5116         case I40E_AQ_LINK_PAUSE_RX:
5117                 rxfc = 1;
5118                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5119                 break;
5120         case I40E_AQ_LINK_PAUSE_TX:
5121                 txfc = 1;
5122                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5123                 break;
5124         default:
5125                 hw->fc.current_mode = I40E_FC_NONE;
5126                 break;
5127         }
5128
5129 write_reg:
5130         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5131                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5132         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5133         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5134         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5135         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5136
5137         return ret;
5138 }
5139
5140 /* PF setup */
5141 static int
5142 i40e_pf_setup(struct i40e_pf *pf)
5143 {
5144         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5145         struct i40e_filter_control_settings settings;
5146         struct i40e_vsi *vsi;
5147         int ret;
5148
5149         /* Clear all stats counters */
5150         pf->offset_loaded = FALSE;
5151         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5152         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5153
5154         ret = i40e_pf_get_switch_config(pf);
5155         if (ret != I40E_SUCCESS) {
5156                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5157                 return ret;
5158         }
5159         if (pf->flags & I40E_FLAG_FDIR) {
5160                 /* make queue allocated first, let FDIR use queue pair 0*/
5161                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5162                 if (ret != I40E_FDIR_QUEUE_ID) {
5163                         PMD_DRV_LOG(ERR,
5164                                 "queue allocation fails for FDIR: ret =%d",
5165                                 ret);
5166                         pf->flags &= ~I40E_FLAG_FDIR;
5167                 }
5168         }
5169         /*  main VSI setup */
5170         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5171         if (!vsi) {
5172                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5173                 return I40E_ERR_NOT_READY;
5174         }
5175         pf->main_vsi = vsi;
5176
5177         /* Configure filter control */
5178         memset(&settings, 0, sizeof(settings));
5179         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5180                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5181         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5182                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5183         else {
5184                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5185                                                 hw->func_caps.rss_table_size);
5186                 return I40E_ERR_PARAM;
5187         }
5188         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u\n",
5189                 hw->func_caps.rss_table_size);
5190         pf->hash_lut_size = hw->func_caps.rss_table_size;
5191
5192         /* Enable ethtype and macvlan filters */
5193         settings.enable_ethtype = TRUE;
5194         settings.enable_macvlan = TRUE;
5195         ret = i40e_set_filter_control(hw, &settings);
5196         if (ret)
5197                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5198                                                                 ret);
5199
5200         /* Update flow control according to the auto negotiation */
5201         i40e_update_flow_control(hw);
5202
5203         return I40E_SUCCESS;
5204 }
5205
5206 int
5207 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5208 {
5209         uint32_t reg;
5210         uint16_t j;
5211
5212         /**
5213          * Set or clear TX Queue Disable flags,
5214          * which is required by hardware.
5215          */
5216         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5217         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5218
5219         /* Wait until the request is finished */
5220         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5221                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5222                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5223                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5224                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5225                                                         & 0x1))) {
5226                         break;
5227                 }
5228         }
5229         if (on) {
5230                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5231                         return I40E_SUCCESS; /* already on, skip next steps */
5232
5233                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5234                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5235         } else {
5236                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5237                         return I40E_SUCCESS; /* already off, skip next steps */
5238                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5239         }
5240         /* Write the register */
5241         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5242         /* Check the result */
5243         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5244                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5245                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5246                 if (on) {
5247                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5248                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5249                                 break;
5250                 } else {
5251                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5252                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5253                                 break;
5254                 }
5255         }
5256         /* Check if it is timeout */
5257         if (j >= I40E_CHK_Q_ENA_COUNT) {
5258                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5259                             (on ? "enable" : "disable"), q_idx);
5260                 return I40E_ERR_TIMEOUT;
5261         }
5262
5263         return I40E_SUCCESS;
5264 }
5265
5266 /* Swith on or off the tx queues */
5267 static int
5268 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5269 {
5270         struct rte_eth_dev_data *dev_data = pf->dev_data;
5271         struct i40e_tx_queue *txq;
5272         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5273         uint16_t i;
5274         int ret;
5275
5276         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5277                 txq = dev_data->tx_queues[i];
5278                 /* Don't operate the queue if not configured or
5279                  * if starting only per queue */
5280                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5281                         continue;
5282                 if (on)
5283                         ret = i40e_dev_tx_queue_start(dev, i);
5284                 else
5285                         ret = i40e_dev_tx_queue_stop(dev, i);
5286                 if ( ret != I40E_SUCCESS)
5287                         return ret;
5288         }
5289
5290         return I40E_SUCCESS;
5291 }
5292
5293 int
5294 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5295 {
5296         uint32_t reg;
5297         uint16_t j;
5298
5299         /* Wait until the request is finished */
5300         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5301                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5302                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5303                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5304                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5305                         break;
5306         }
5307
5308         if (on) {
5309                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5310                         return I40E_SUCCESS; /* Already on, skip next steps */
5311                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5312         } else {
5313                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5314                         return I40E_SUCCESS; /* Already off, skip next steps */
5315                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5316         }
5317
5318         /* Write the register */
5319         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5320         /* Check the result */
5321         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5322                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5323                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5324                 if (on) {
5325                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5326                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5327                                 break;
5328                 } else {
5329                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5330                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5331                                 break;
5332                 }
5333         }
5334
5335         /* Check if it is timeout */
5336         if (j >= I40E_CHK_Q_ENA_COUNT) {
5337                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5338                             (on ? "enable" : "disable"), q_idx);
5339                 return I40E_ERR_TIMEOUT;
5340         }
5341
5342         return I40E_SUCCESS;
5343 }
5344 /* Switch on or off the rx queues */
5345 static int
5346 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5347 {
5348         struct rte_eth_dev_data *dev_data = pf->dev_data;
5349         struct i40e_rx_queue *rxq;
5350         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5351         uint16_t i;
5352         int ret;
5353
5354         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5355                 rxq = dev_data->rx_queues[i];
5356                 /* Don't operate the queue if not configured or
5357                  * if starting only per queue */
5358                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5359                         continue;
5360                 if (on)
5361                         ret = i40e_dev_rx_queue_start(dev, i);
5362                 else
5363                         ret = i40e_dev_rx_queue_stop(dev, i);
5364                 if (ret != I40E_SUCCESS)
5365                         return ret;
5366         }
5367
5368         return I40E_SUCCESS;
5369 }
5370
5371 /* Switch on or off all the rx/tx queues */
5372 int
5373 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5374 {
5375         int ret;
5376
5377         if (on) {
5378                 /* enable rx queues before enabling tx queues */
5379                 ret = i40e_dev_switch_rx_queues(pf, on);
5380                 if (ret) {
5381                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5382                         return ret;
5383                 }
5384                 ret = i40e_dev_switch_tx_queues(pf, on);
5385         } else {
5386                 /* Stop tx queues before stopping rx queues */
5387                 ret = i40e_dev_switch_tx_queues(pf, on);
5388                 if (ret) {
5389                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5390                         return ret;
5391                 }
5392                 ret = i40e_dev_switch_rx_queues(pf, on);
5393         }
5394
5395         return ret;
5396 }
5397
5398 /* Initialize VSI for TX */
5399 static int
5400 i40e_dev_tx_init(struct i40e_pf *pf)
5401 {
5402         struct rte_eth_dev_data *data = pf->dev_data;
5403         uint16_t i;
5404         uint32_t ret = I40E_SUCCESS;
5405         struct i40e_tx_queue *txq;
5406
5407         for (i = 0; i < data->nb_tx_queues; i++) {
5408                 txq = data->tx_queues[i];
5409                 if (!txq || !txq->q_set)
5410                         continue;
5411                 ret = i40e_tx_queue_init(txq);
5412                 if (ret != I40E_SUCCESS)
5413                         break;
5414         }
5415         if (ret == I40E_SUCCESS)
5416                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5417                                      ->eth_dev);
5418
5419         return ret;
5420 }
5421
5422 /* Initialize VSI for RX */
5423 static int
5424 i40e_dev_rx_init(struct i40e_pf *pf)
5425 {
5426         struct rte_eth_dev_data *data = pf->dev_data;
5427         int ret = I40E_SUCCESS;
5428         uint16_t i;
5429         struct i40e_rx_queue *rxq;
5430
5431         i40e_pf_config_mq_rx(pf);
5432         for (i = 0; i < data->nb_rx_queues; i++) {
5433                 rxq = data->rx_queues[i];
5434                 if (!rxq || !rxq->q_set)
5435                         continue;
5436
5437                 ret = i40e_rx_queue_init(rxq);
5438                 if (ret != I40E_SUCCESS) {
5439                         PMD_DRV_LOG(ERR,
5440                                 "Failed to do RX queue initialization");
5441                         break;
5442                 }
5443         }
5444         if (ret == I40E_SUCCESS)
5445                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5446                                      ->eth_dev);
5447
5448         return ret;
5449 }
5450
5451 static int
5452 i40e_dev_rxtx_init(struct i40e_pf *pf)
5453 {
5454         int err;
5455
5456         err = i40e_dev_tx_init(pf);
5457         if (err) {
5458                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5459                 return err;
5460         }
5461         err = i40e_dev_rx_init(pf);
5462         if (err) {
5463                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5464                 return err;
5465         }
5466
5467         return err;
5468 }
5469
5470 static int
5471 i40e_vmdq_setup(struct rte_eth_dev *dev)
5472 {
5473         struct rte_eth_conf *conf = &dev->data->dev_conf;
5474         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5475         int i, err, conf_vsis, j, loop;
5476         struct i40e_vsi *vsi;
5477         struct i40e_vmdq_info *vmdq_info;
5478         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5479         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5480
5481         /*
5482          * Disable interrupt to avoid message from VF. Furthermore, it will
5483          * avoid race condition in VSI creation/destroy.
5484          */
5485         i40e_pf_disable_irq0(hw);
5486
5487         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5488                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5489                 return -ENOTSUP;
5490         }
5491
5492         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5493         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5494                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5495                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5496                         pf->max_nb_vmdq_vsi);
5497                 return -ENOTSUP;
5498         }
5499
5500         if (pf->vmdq != NULL) {
5501                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5502                 return 0;
5503         }
5504
5505         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5506                                 sizeof(*vmdq_info) * conf_vsis, 0);
5507
5508         if (pf->vmdq == NULL) {
5509                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5510                 return -ENOMEM;
5511         }
5512
5513         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5514
5515         /* Create VMDQ VSI */
5516         for (i = 0; i < conf_vsis; i++) {
5517                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5518                                 vmdq_conf->enable_loop_back);
5519                 if (vsi == NULL) {
5520                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5521                         err = -1;
5522                         goto err_vsi_setup;
5523                 }
5524                 vmdq_info = &pf->vmdq[i];
5525                 vmdq_info->pf = pf;
5526                 vmdq_info->vsi = vsi;
5527         }
5528         pf->nb_cfg_vmdq_vsi = conf_vsis;
5529
5530         /* Configure Vlan */
5531         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5532         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5533                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5534                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5535                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5536                                         vmdq_conf->pool_map[i].vlan_id, j);
5537
5538                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5539                                                 vmdq_conf->pool_map[i].vlan_id);
5540                                 if (err) {
5541                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5542                                         err = -1;
5543                                         goto err_vsi_setup;
5544                                 }
5545                         }
5546                 }
5547         }
5548
5549         i40e_pf_enable_irq0(hw);
5550
5551         return 0;
5552
5553 err_vsi_setup:
5554         for (i = 0; i < conf_vsis; i++)
5555                 if (pf->vmdq[i].vsi == NULL)
5556                         break;
5557                 else
5558                         i40e_vsi_release(pf->vmdq[i].vsi);
5559
5560         rte_free(pf->vmdq);
5561         pf->vmdq = NULL;
5562         i40e_pf_enable_irq0(hw);
5563         return err;
5564 }
5565
5566 static void
5567 i40e_stat_update_32(struct i40e_hw *hw,
5568                    uint32_t reg,
5569                    bool offset_loaded,
5570                    uint64_t *offset,
5571                    uint64_t *stat)
5572 {
5573         uint64_t new_data;
5574
5575         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5576         if (!offset_loaded)
5577                 *offset = new_data;
5578
5579         if (new_data >= *offset)
5580                 *stat = (uint64_t)(new_data - *offset);
5581         else
5582                 *stat = (uint64_t)((new_data +
5583                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5584 }
5585
5586 static void
5587 i40e_stat_update_48(struct i40e_hw *hw,
5588                    uint32_t hireg,
5589                    uint32_t loreg,
5590                    bool offset_loaded,
5591                    uint64_t *offset,
5592                    uint64_t *stat)
5593 {
5594         uint64_t new_data;
5595
5596         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5597         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5598                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5599
5600         if (!offset_loaded)
5601                 *offset = new_data;
5602
5603         if (new_data >= *offset)
5604                 *stat = new_data - *offset;
5605         else
5606                 *stat = (uint64_t)((new_data +
5607                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5608
5609         *stat &= I40E_48_BIT_MASK;
5610 }
5611
5612 /* Disable IRQ0 */
5613 void
5614 i40e_pf_disable_irq0(struct i40e_hw *hw)
5615 {
5616         /* Disable all interrupt types */
5617         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5618         I40E_WRITE_FLUSH(hw);
5619 }
5620
5621 /* Enable IRQ0 */
5622 void
5623 i40e_pf_enable_irq0(struct i40e_hw *hw)
5624 {
5625         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5626                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5627                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5628                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5629         I40E_WRITE_FLUSH(hw);
5630 }
5631
5632 static void
5633 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5634 {
5635         /* read pending request and disable first */
5636         i40e_pf_disable_irq0(hw);
5637         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5638         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5639                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5640
5641         if (no_queue)
5642                 /* Link no queues with irq0 */
5643                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5644                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5645 }
5646
5647 static void
5648 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5649 {
5650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5651         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5652         int i;
5653         uint16_t abs_vf_id;
5654         uint32_t index, offset, val;
5655
5656         if (!pf->vfs)
5657                 return;
5658         /**
5659          * Try to find which VF trigger a reset, use absolute VF id to access
5660          * since the reg is global register.
5661          */
5662         for (i = 0; i < pf->vf_num; i++) {
5663                 abs_vf_id = hw->func_caps.vf_base_id + i;
5664                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5665                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5666                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5667                 /* VFR event occured */
5668                 if (val & (0x1 << offset)) {
5669                         int ret;
5670
5671                         /* Clear the event first */
5672                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5673                                                         (0x1 << offset));
5674                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5675                         /**
5676                          * Only notify a VF reset event occured,
5677                          * don't trigger another SW reset
5678                          */
5679                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5680                         if (ret != I40E_SUCCESS)
5681                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5682                 }
5683         }
5684 }
5685
5686 static void
5687 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5688 {
5689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5690         struct i40e_virtchnl_pf_event event;
5691         int i;
5692
5693         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5694         event.event_data.link_event.link_status =
5695                 dev->data->dev_link.link_status;
5696         event.event_data.link_event.link_speed =
5697                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5698
5699         for (i = 0; i < pf->vf_num; i++)
5700                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5701                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5702 }
5703
5704 static void
5705 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5706 {
5707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5708         struct i40e_arq_event_info info;
5709         uint16_t pending, opcode;
5710         int ret;
5711
5712         info.buf_len = I40E_AQ_BUF_SZ;
5713         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5714         if (!info.msg_buf) {
5715                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5716                 return;
5717         }
5718
5719         pending = 1;
5720         while (pending) {
5721                 ret = i40e_clean_arq_element(hw, &info, &pending);
5722
5723                 if (ret != I40E_SUCCESS) {
5724                         PMD_DRV_LOG(INFO,
5725                                 "Failed to read msg from AdminQ, aq_err: %u",
5726                                 hw->aq.asq_last_status);
5727                         break;
5728                 }
5729                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5730
5731                 switch (opcode) {
5732                 case i40e_aqc_opc_send_msg_to_pf:
5733                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5734                         i40e_pf_host_handle_vf_msg(dev,
5735                                         rte_le_to_cpu_16(info.desc.retval),
5736                                         rte_le_to_cpu_32(info.desc.cookie_high),
5737                                         rte_le_to_cpu_32(info.desc.cookie_low),
5738                                         info.msg_buf,
5739                                         info.msg_len);
5740                         break;
5741                 case i40e_aqc_opc_get_link_status:
5742                         ret = i40e_dev_link_update(dev, 0);
5743                         if (!ret) {
5744                                 i40e_notify_all_vfs_link_status(dev);
5745                                 _rte_eth_dev_callback_process(dev,
5746                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5747                         }
5748                         break;
5749                 default:
5750                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5751                                     opcode);
5752                         break;
5753                 }
5754         }
5755         rte_free(info.msg_buf);
5756 }
5757
5758 /**
5759  * Interrupt handler triggered by NIC  for handling
5760  * specific interrupt.
5761  *
5762  * @param handle
5763  *  Pointer to interrupt handle.
5764  * @param param
5765  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5766  *
5767  * @return
5768  *  void
5769  */
5770 static void
5771 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5772                            void *param)
5773 {
5774         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5776         uint32_t icr0;
5777
5778         /* Disable interrupt */
5779         i40e_pf_disable_irq0(hw);
5780
5781         /* read out interrupt causes */
5782         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5783
5784         /* No interrupt event indicated */
5785         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5786                 PMD_DRV_LOG(INFO, "No interrupt event");
5787                 goto done;
5788         }
5789 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5790         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5791                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5792         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5793                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5794         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5795                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5796         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5797                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5798         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5799                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5800         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5801                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5802         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5803                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5804 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5805
5806         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5807                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5808                 i40e_dev_handle_vfr_event(dev);
5809         }
5810         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5811                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5812                 i40e_dev_handle_aq_msg(dev);
5813         }
5814
5815 done:
5816         /* Enable interrupt */
5817         i40e_pf_enable_irq0(hw);
5818         rte_intr_enable(intr_handle);
5819 }
5820
5821 static int
5822 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5823                          struct i40e_macvlan_filter *filter,
5824                          int total)
5825 {
5826         int ele_num, ele_buff_size;
5827         int num, actual_num, i;
5828         uint16_t flags;
5829         int ret = I40E_SUCCESS;
5830         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5831         struct i40e_aqc_add_macvlan_element_data *req_list;
5832
5833         if (filter == NULL  || total == 0)
5834                 return I40E_ERR_PARAM;
5835         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5836         ele_buff_size = hw->aq.asq_buf_size;
5837
5838         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5839         if (req_list == NULL) {
5840                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5841                 return I40E_ERR_NO_MEMORY;
5842         }
5843
5844         num = 0;
5845         do {
5846                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5847                 memset(req_list, 0, ele_buff_size);
5848
5849                 for (i = 0; i < actual_num; i++) {
5850                         (void)rte_memcpy(req_list[i].mac_addr,
5851                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5852                         req_list[i].vlan_tag =
5853                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5854
5855                         switch (filter[num + i].filter_type) {
5856                         case RTE_MAC_PERFECT_MATCH:
5857                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5858                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5859                                 break;
5860                         case RTE_MACVLAN_PERFECT_MATCH:
5861                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5862                                 break;
5863                         case RTE_MAC_HASH_MATCH:
5864                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5865                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5866                                 break;
5867                         case RTE_MACVLAN_HASH_MATCH:
5868                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5869                                 break;
5870                         default:
5871                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5872                                 ret = I40E_ERR_PARAM;
5873                                 goto DONE;
5874                         }
5875
5876                         req_list[i].queue_number = 0;
5877
5878                         req_list[i].flags = rte_cpu_to_le_16(flags);
5879                 }
5880
5881                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5882                                                 actual_num, NULL);
5883                 if (ret != I40E_SUCCESS) {
5884                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5885                         goto DONE;
5886                 }
5887                 num += actual_num;
5888         } while (num < total);
5889
5890 DONE:
5891         rte_free(req_list);
5892         return ret;
5893 }
5894
5895 static int
5896 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5897                             struct i40e_macvlan_filter *filter,
5898                             int total)
5899 {
5900         int ele_num, ele_buff_size;
5901         int num, actual_num, i;
5902         uint16_t flags;
5903         int ret = I40E_SUCCESS;
5904         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5905         struct i40e_aqc_remove_macvlan_element_data *req_list;
5906
5907         if (filter == NULL  || total == 0)
5908                 return I40E_ERR_PARAM;
5909
5910         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5911         ele_buff_size = hw->aq.asq_buf_size;
5912
5913         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5914         if (req_list == NULL) {
5915                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5916                 return I40E_ERR_NO_MEMORY;
5917         }
5918
5919         num = 0;
5920         do {
5921                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5922                 memset(req_list, 0, ele_buff_size);
5923
5924                 for (i = 0; i < actual_num; i++) {
5925                         (void)rte_memcpy(req_list[i].mac_addr,
5926                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5927                         req_list[i].vlan_tag =
5928                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5929
5930                         switch (filter[num + i].filter_type) {
5931                         case RTE_MAC_PERFECT_MATCH:
5932                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5933                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5934                                 break;
5935                         case RTE_MACVLAN_PERFECT_MATCH:
5936                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5937                                 break;
5938                         case RTE_MAC_HASH_MATCH:
5939                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5940                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5941                                 break;
5942                         case RTE_MACVLAN_HASH_MATCH:
5943                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5944                                 break;
5945                         default:
5946                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5947                                 ret = I40E_ERR_PARAM;
5948                                 goto DONE;
5949                         }
5950                         req_list[i].flags = rte_cpu_to_le_16(flags);
5951                 }
5952
5953                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5954                                                 actual_num, NULL);
5955                 if (ret != I40E_SUCCESS) {
5956                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5957                         goto DONE;
5958                 }
5959                 num += actual_num;
5960         } while (num < total);
5961
5962 DONE:
5963         rte_free(req_list);
5964         return ret;
5965 }
5966
5967 /* Find out specific MAC filter */
5968 static struct i40e_mac_filter *
5969 i40e_find_mac_filter(struct i40e_vsi *vsi,
5970                          struct ether_addr *macaddr)
5971 {
5972         struct i40e_mac_filter *f;
5973
5974         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5975                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5976                         return f;
5977         }
5978
5979         return NULL;
5980 }
5981
5982 static bool
5983 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5984                          uint16_t vlan_id)
5985 {
5986         uint32_t vid_idx, vid_bit;
5987
5988         if (vlan_id > ETH_VLAN_ID_MAX)
5989                 return 0;
5990
5991         vid_idx = I40E_VFTA_IDX(vlan_id);
5992         vid_bit = I40E_VFTA_BIT(vlan_id);
5993
5994         if (vsi->vfta[vid_idx] & vid_bit)
5995                 return 1;
5996         else
5997                 return 0;
5998 }
5999
6000 static void
6001 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6002                        uint16_t vlan_id, bool on)
6003 {
6004         uint32_t vid_idx, vid_bit;
6005
6006         vid_idx = I40E_VFTA_IDX(vlan_id);
6007         vid_bit = I40E_VFTA_BIT(vlan_id);
6008
6009         if (on)
6010                 vsi->vfta[vid_idx] |= vid_bit;
6011         else
6012                 vsi->vfta[vid_idx] &= ~vid_bit;
6013 }
6014
6015 static void
6016 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6017                      uint16_t vlan_id, bool on)
6018 {
6019         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6020         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6021         int ret;
6022
6023         if (vlan_id > ETH_VLAN_ID_MAX)
6024                 return;
6025
6026         i40e_store_vlan_filter(vsi, vlan_id, on);
6027
6028         if (!vsi->vlan_anti_spoof_on || !vlan_id)
6029                 return;
6030
6031         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6032
6033         if (on) {
6034                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6035                                        &vlan_data, 1, NULL);
6036                 if (ret != I40E_SUCCESS)
6037                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6038         } else {
6039                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6040                                           &vlan_data, 1, NULL);
6041                 if (ret != I40E_SUCCESS)
6042                         PMD_DRV_LOG(ERR,
6043                                     "Failed to remove vlan filter");
6044         }
6045 }
6046
6047 /**
6048  * Find all vlan options for specific mac addr,
6049  * return with actual vlan found.
6050  */
6051 static inline int
6052 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6053                            struct i40e_macvlan_filter *mv_f,
6054                            int num, struct ether_addr *addr)
6055 {
6056         int i;
6057         uint32_t j, k;
6058
6059         /**
6060          * Not to use i40e_find_vlan_filter to decrease the loop time,
6061          * although the code looks complex.
6062           */
6063         if (num < vsi->vlan_num)
6064                 return I40E_ERR_PARAM;
6065
6066         i = 0;
6067         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6068                 if (vsi->vfta[j]) {
6069                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6070                                 if (vsi->vfta[j] & (1 << k)) {
6071                                         if (i > num - 1) {
6072                                                 PMD_DRV_LOG(ERR,
6073                                                         "vlan number doesn't match");
6074                                                 return I40E_ERR_PARAM;
6075                                         }
6076                                         (void)rte_memcpy(&mv_f[i].macaddr,
6077                                                         addr, ETH_ADDR_LEN);
6078                                         mv_f[i].vlan_id =
6079                                                 j * I40E_UINT32_BIT_SIZE + k;
6080                                         i++;
6081                                 }
6082                         }
6083                 }
6084         }
6085         return I40E_SUCCESS;
6086 }
6087
6088 static inline int
6089 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6090                            struct i40e_macvlan_filter *mv_f,
6091                            int num,
6092                            uint16_t vlan)
6093 {
6094         int i = 0;
6095         struct i40e_mac_filter *f;
6096
6097         if (num < vsi->mac_num)
6098                 return I40E_ERR_PARAM;
6099
6100         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6101                 if (i > num - 1) {
6102                         PMD_DRV_LOG(ERR, "buffer number not match");
6103                         return I40E_ERR_PARAM;
6104                 }
6105                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6106                                 ETH_ADDR_LEN);
6107                 mv_f[i].vlan_id = vlan;
6108                 mv_f[i].filter_type = f->mac_info.filter_type;
6109                 i++;
6110         }
6111
6112         return I40E_SUCCESS;
6113 }
6114
6115 static int
6116 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6117 {
6118         int i, num;
6119         struct i40e_mac_filter *f;
6120         struct i40e_macvlan_filter *mv_f;
6121         int ret = I40E_SUCCESS;
6122
6123         if (vsi == NULL || vsi->mac_num == 0)
6124                 return I40E_ERR_PARAM;
6125
6126         /* Case that no vlan is set */
6127         if (vsi->vlan_num == 0)
6128                 num = vsi->mac_num;
6129         else
6130                 num = vsi->mac_num * vsi->vlan_num;
6131
6132         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6133         if (mv_f == NULL) {
6134                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6135                 return I40E_ERR_NO_MEMORY;
6136         }
6137
6138         i = 0;
6139         if (vsi->vlan_num == 0) {
6140                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6141                         (void)rte_memcpy(&mv_f[i].macaddr,
6142                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6143                         mv_f[i].vlan_id = 0;
6144                         i++;
6145                 }
6146         } else {
6147                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6148                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6149                                         vsi->vlan_num, &f->mac_info.mac_addr);
6150                         if (ret != I40E_SUCCESS)
6151                                 goto DONE;
6152                         i += vsi->vlan_num;
6153                 }
6154         }
6155
6156         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6157 DONE:
6158         rte_free(mv_f);
6159
6160         return ret;
6161 }
6162
6163 int
6164 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6165 {
6166         struct i40e_macvlan_filter *mv_f;
6167         int mac_num;
6168         int ret = I40E_SUCCESS;
6169
6170         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6171                 return I40E_ERR_PARAM;
6172
6173         /* If it's already set, just return */
6174         if (i40e_find_vlan_filter(vsi,vlan))
6175                 return I40E_SUCCESS;
6176
6177         mac_num = vsi->mac_num;
6178
6179         if (mac_num == 0) {
6180                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6181                 return I40E_ERR_PARAM;
6182         }
6183
6184         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6185
6186         if (mv_f == NULL) {
6187                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6188                 return I40E_ERR_NO_MEMORY;
6189         }
6190
6191         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6192
6193         if (ret != I40E_SUCCESS)
6194                 goto DONE;
6195
6196         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6197
6198         if (ret != I40E_SUCCESS)
6199                 goto DONE;
6200
6201         i40e_set_vlan_filter(vsi, vlan, 1);
6202
6203         vsi->vlan_num++;
6204         ret = I40E_SUCCESS;
6205 DONE:
6206         rte_free(mv_f);
6207         return ret;
6208 }
6209
6210 int
6211 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6212 {
6213         struct i40e_macvlan_filter *mv_f;
6214         int mac_num;
6215         int ret = I40E_SUCCESS;
6216
6217         /**
6218          * Vlan 0 is the generic filter for untagged packets
6219          * and can't be removed.
6220          */
6221         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6222                 return I40E_ERR_PARAM;
6223
6224         /* If can't find it, just return */
6225         if (!i40e_find_vlan_filter(vsi, vlan))
6226                 return I40E_ERR_PARAM;
6227
6228         mac_num = vsi->mac_num;
6229
6230         if (mac_num == 0) {
6231                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6232                 return I40E_ERR_PARAM;
6233         }
6234
6235         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6236
6237         if (mv_f == NULL) {
6238                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6239                 return I40E_ERR_NO_MEMORY;
6240         }
6241
6242         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6243
6244         if (ret != I40E_SUCCESS)
6245                 goto DONE;
6246
6247         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6248
6249         if (ret != I40E_SUCCESS)
6250                 goto DONE;
6251
6252         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6253         if (vsi->vlan_num == 1) {
6254                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6255                 if (ret != I40E_SUCCESS)
6256                         goto DONE;
6257
6258                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6259                 if (ret != I40E_SUCCESS)
6260                         goto DONE;
6261         }
6262
6263         i40e_set_vlan_filter(vsi, vlan, 0);
6264
6265         vsi->vlan_num--;
6266         ret = I40E_SUCCESS;
6267 DONE:
6268         rte_free(mv_f);
6269         return ret;
6270 }
6271
6272 int
6273 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6274 {
6275         struct i40e_mac_filter *f;
6276         struct i40e_macvlan_filter *mv_f;
6277         int i, vlan_num = 0;
6278         int ret = I40E_SUCCESS;
6279
6280         /* If it's add and we've config it, return */
6281         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6282         if (f != NULL)
6283                 return I40E_SUCCESS;
6284         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6285                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6286
6287                 /**
6288                  * If vlan_num is 0, that's the first time to add mac,
6289                  * set mask for vlan_id 0.
6290                  */
6291                 if (vsi->vlan_num == 0) {
6292                         i40e_set_vlan_filter(vsi, 0, 1);
6293                         vsi->vlan_num = 1;
6294                 }
6295                 vlan_num = vsi->vlan_num;
6296         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6297                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6298                 vlan_num = 1;
6299
6300         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6301         if (mv_f == NULL) {
6302                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6303                 return I40E_ERR_NO_MEMORY;
6304         }
6305
6306         for (i = 0; i < vlan_num; i++) {
6307                 mv_f[i].filter_type = mac_filter->filter_type;
6308                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6309                                 ETH_ADDR_LEN);
6310         }
6311
6312         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6313                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6314                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6315                                         &mac_filter->mac_addr);
6316                 if (ret != I40E_SUCCESS)
6317                         goto DONE;
6318         }
6319
6320         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6321         if (ret != I40E_SUCCESS)
6322                 goto DONE;
6323
6324         /* Add the mac addr into mac list */
6325         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6326         if (f == NULL) {
6327                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6328                 ret = I40E_ERR_NO_MEMORY;
6329                 goto DONE;
6330         }
6331         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6332                         ETH_ADDR_LEN);
6333         f->mac_info.filter_type = mac_filter->filter_type;
6334         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6335         vsi->mac_num++;
6336
6337         ret = I40E_SUCCESS;
6338 DONE:
6339         rte_free(mv_f);
6340
6341         return ret;
6342 }
6343
6344 int
6345 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6346 {
6347         struct i40e_mac_filter *f;
6348         struct i40e_macvlan_filter *mv_f;
6349         int i, vlan_num;
6350         enum rte_mac_filter_type filter_type;
6351         int ret = I40E_SUCCESS;
6352
6353         /* Can't find it, return an error */
6354         f = i40e_find_mac_filter(vsi, addr);
6355         if (f == NULL)
6356                 return I40E_ERR_PARAM;
6357
6358         vlan_num = vsi->vlan_num;
6359         filter_type = f->mac_info.filter_type;
6360         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6361                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6362                 if (vlan_num == 0) {
6363                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6364                         return I40E_ERR_PARAM;
6365                 }
6366         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6367                         filter_type == RTE_MAC_HASH_MATCH)
6368                 vlan_num = 1;
6369
6370         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6371         if (mv_f == NULL) {
6372                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6373                 return I40E_ERR_NO_MEMORY;
6374         }
6375
6376         for (i = 0; i < vlan_num; i++) {
6377                 mv_f[i].filter_type = filter_type;
6378                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6379                                 ETH_ADDR_LEN);
6380         }
6381         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6382                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6383                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6384                 if (ret != I40E_SUCCESS)
6385                         goto DONE;
6386         }
6387
6388         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6389         if (ret != I40E_SUCCESS)
6390                 goto DONE;
6391
6392         /* Remove the mac addr into mac list */
6393         TAILQ_REMOVE(&vsi->mac_list, f, next);
6394         rte_free(f);
6395         vsi->mac_num--;
6396
6397         ret = I40E_SUCCESS;
6398 DONE:
6399         rte_free(mv_f);
6400         return ret;
6401 }
6402
6403 /* Configure hash enable flags for RSS */
6404 uint64_t
6405 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6406 {
6407         uint64_t hena = 0;
6408
6409         if (!flags)
6410                 return hena;
6411
6412         if (flags & ETH_RSS_FRAG_IPV4)
6413                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6414         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6415                 if (type == I40E_MAC_X722) {
6416                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6417                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6418                 } else
6419                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6420         }
6421         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6422                 if (type == I40E_MAC_X722) {
6423                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6424                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6425                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6426                 } else
6427                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6428         }
6429         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6430                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6431         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6432                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6433         if (flags & ETH_RSS_FRAG_IPV6)
6434                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6435         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6436                 if (type == I40E_MAC_X722) {
6437                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6438                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6439                 } else
6440                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6441         }
6442         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6443                 if (type == I40E_MAC_X722) {
6444                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6445                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6446                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6447                 } else
6448                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6449         }
6450         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6451                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6452         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6453                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6454         if (flags & ETH_RSS_L2_PAYLOAD)
6455                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6456
6457         return hena;
6458 }
6459
6460 /* Parse the hash enable flags */
6461 uint64_t
6462 i40e_parse_hena(uint64_t flags)
6463 {
6464         uint64_t rss_hf = 0;
6465
6466         if (!flags)
6467                 return rss_hf;
6468         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6469                 rss_hf |= ETH_RSS_FRAG_IPV4;
6470         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6471                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6472         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6473                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6474         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6475                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6476         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6477                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6478         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6479                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6480         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6481                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6482         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6483                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6484         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6485                 rss_hf |= ETH_RSS_FRAG_IPV6;
6486         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6487                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6488         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6489                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6490         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6491                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6492         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6493                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6494         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6495                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6496         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6497                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6498         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6499                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6500         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6501                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6502
6503         return rss_hf;
6504 }
6505
6506 /* Disable RSS */
6507 static void
6508 i40e_pf_disable_rss(struct i40e_pf *pf)
6509 {
6510         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6511         uint64_t hena;
6512
6513         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6514         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6515         if (hw->mac.type == I40E_MAC_X722)
6516                 hena &= ~I40E_RSS_HENA_ALL_X722;
6517         else
6518                 hena &= ~I40E_RSS_HENA_ALL;
6519         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6520         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6521         I40E_WRITE_FLUSH(hw);
6522 }
6523
6524 static int
6525 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6526 {
6527         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6528         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6529         int ret = 0;
6530
6531         if (!key || key_len == 0) {
6532                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6533                 return 0;
6534         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6535                 sizeof(uint32_t)) {
6536                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6537                 return -EINVAL;
6538         }
6539
6540         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6541                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6542                         (struct i40e_aqc_get_set_rss_key_data *)key;
6543
6544                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6545                 if (ret)
6546                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6547         } else {
6548                 uint32_t *hash_key = (uint32_t *)key;
6549                 uint16_t i;
6550
6551                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6552                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6553                 I40E_WRITE_FLUSH(hw);
6554         }
6555
6556         return ret;
6557 }
6558
6559 static int
6560 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6561 {
6562         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6563         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6564         int ret;
6565
6566         if (!key || !key_len)
6567                 return -EINVAL;
6568
6569         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6570                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6571                         (struct i40e_aqc_get_set_rss_key_data *)key);
6572                 if (ret) {
6573                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6574                         return ret;
6575                 }
6576         } else {
6577                 uint32_t *key_dw = (uint32_t *)key;
6578                 uint16_t i;
6579
6580                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6581                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6582         }
6583         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6584
6585         return 0;
6586 }
6587
6588 static int
6589 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6590 {
6591         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6592         uint64_t rss_hf;
6593         uint64_t hena;
6594         int ret;
6595
6596         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6597                                rss_conf->rss_key_len);
6598         if (ret)
6599                 return ret;
6600
6601         rss_hf = rss_conf->rss_hf;
6602         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6603         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6604         if (hw->mac.type == I40E_MAC_X722)
6605                 hena &= ~I40E_RSS_HENA_ALL_X722;
6606         else
6607                 hena &= ~I40E_RSS_HENA_ALL;
6608         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6609         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6610         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6611         I40E_WRITE_FLUSH(hw);
6612
6613         return 0;
6614 }
6615
6616 static int
6617 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6618                          struct rte_eth_rss_conf *rss_conf)
6619 {
6620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6621         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6622         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6623         uint64_t hena;
6624
6625         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6626         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6627         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6628                  ? I40E_RSS_HENA_ALL_X722
6629                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6630                 if (rss_hf != 0) /* Enable RSS */
6631                         return -EINVAL;
6632                 return 0; /* Nothing to do */
6633         }
6634         /* RSS enabled */
6635         if (rss_hf == 0) /* Disable RSS */
6636                 return -EINVAL;
6637
6638         return i40e_hw_rss_hash_set(pf, rss_conf);
6639 }
6640
6641 static int
6642 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6643                            struct rte_eth_rss_conf *rss_conf)
6644 {
6645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6647         uint64_t hena;
6648
6649         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6650                          &rss_conf->rss_key_len);
6651
6652         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6653         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6654         rss_conf->rss_hf = i40e_parse_hena(hena);
6655
6656         return 0;
6657 }
6658
6659 static int
6660 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6661 {
6662         switch (filter_type) {
6663         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6664                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6665                 break;
6666         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6667                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6668                 break;
6669         case RTE_TUNNEL_FILTER_IMAC_TENID:
6670                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6671                 break;
6672         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6673                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6674                 break;
6675         case ETH_TUNNEL_FILTER_IMAC:
6676                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6677                 break;
6678         case ETH_TUNNEL_FILTER_OIP:
6679                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6680                 break;
6681         case ETH_TUNNEL_FILTER_IIP:
6682                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6683                 break;
6684         default:
6685                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6686                 return -EINVAL;
6687         }
6688
6689         return 0;
6690 }
6691
6692 /* Convert tunnel filter structure */
6693 static int
6694 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6695                            *cld_filter,
6696                            struct i40e_tunnel_filter *tunnel_filter)
6697 {
6698         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6699                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6700         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6701                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6702         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6703         tunnel_filter->input.flags = cld_filter->flags;
6704         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6705         tunnel_filter->queue = cld_filter->queue_number;
6706
6707         return 0;
6708 }
6709
6710 /* Check if there exists the tunnel filter */
6711 struct i40e_tunnel_filter *
6712 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6713                              const struct i40e_tunnel_filter_input *input)
6714 {
6715         int ret;
6716
6717         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6718         if (ret < 0)
6719                 return NULL;
6720
6721         return tunnel_rule->hash_map[ret];
6722 }
6723
6724 /* Add a tunnel filter into the SW list */
6725 static int
6726 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6727                              struct i40e_tunnel_filter *tunnel_filter)
6728 {
6729         struct i40e_tunnel_rule *rule = &pf->tunnel;
6730         int ret;
6731
6732         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6733         if (ret < 0) {
6734                 PMD_DRV_LOG(ERR,
6735                             "Failed to insert tunnel filter to hash table %d!",
6736                             ret);
6737                 return ret;
6738         }
6739         rule->hash_map[ret] = tunnel_filter;
6740
6741         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6742
6743         return 0;
6744 }
6745
6746 /* Delete a tunnel filter from the SW list */
6747 int
6748 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6749                           struct i40e_tunnel_filter_input *input)
6750 {
6751         struct i40e_tunnel_rule *rule = &pf->tunnel;
6752         struct i40e_tunnel_filter *tunnel_filter;
6753         int ret;
6754
6755         ret = rte_hash_del_key(rule->hash_table, input);
6756         if (ret < 0) {
6757                 PMD_DRV_LOG(ERR,
6758                             "Failed to delete tunnel filter to hash table %d!",
6759                             ret);
6760                 return ret;
6761         }
6762         tunnel_filter = rule->hash_map[ret];
6763         rule->hash_map[ret] = NULL;
6764
6765         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6766         rte_free(tunnel_filter);
6767
6768         return 0;
6769 }
6770
6771 int
6772 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6773                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6774                         uint8_t add)
6775 {
6776         uint16_t ip_type;
6777         uint32_t ipv4_addr;
6778         uint8_t i, tun_type = 0;
6779         /* internal varialbe to convert ipv6 byte order */
6780         uint32_t convert_ipv6[4];
6781         int val, ret = 0;
6782         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6783         struct i40e_vsi *vsi = pf->main_vsi;
6784         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6785         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6786         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6787         struct i40e_tunnel_filter *tunnel, *node;
6788         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6789
6790         cld_filter = rte_zmalloc("tunnel_filter",
6791                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6792                 0);
6793
6794         if (NULL == cld_filter) {
6795                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6796                 return -EINVAL;
6797         }
6798         pfilter = cld_filter;
6799
6800         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6801         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6802
6803         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6804         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6805                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6806                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6807                 rte_memcpy(&pfilter->ipaddr.v4.data,
6808                                 &rte_cpu_to_le_32(ipv4_addr),
6809                                 sizeof(pfilter->ipaddr.v4.data));
6810         } else {
6811                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6812                 for (i = 0; i < 4; i++) {
6813                         convert_ipv6[i] =
6814                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6815                 }
6816                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6817                                 sizeof(pfilter->ipaddr.v6.data));
6818         }
6819
6820         /* check tunneled type */
6821         switch (tunnel_filter->tunnel_type) {
6822         case RTE_TUNNEL_TYPE_VXLAN:
6823                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6824                 break;
6825         case RTE_TUNNEL_TYPE_NVGRE:
6826                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6827                 break;
6828         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6829                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6830                 break;
6831         default:
6832                 /* Other tunnel types is not supported. */
6833                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6834                 rte_free(cld_filter);
6835                 return -EINVAL;
6836         }
6837
6838         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6839                                                 &pfilter->flags);
6840         if (val < 0) {
6841                 rte_free(cld_filter);
6842                 return -EINVAL;
6843         }
6844
6845         pfilter->flags |= rte_cpu_to_le_16(
6846                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6847                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6848         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6849         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6850
6851         /* Check if there is the filter in SW list */
6852         memset(&check_filter, 0, sizeof(check_filter));
6853         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6854         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6855         if (add && node) {
6856                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6857                 return -EINVAL;
6858         }
6859
6860         if (!add && !node) {
6861                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6862                 return -EINVAL;
6863         }
6864
6865         if (add) {
6866                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6867                 if (ret < 0) {
6868                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6869                         return ret;
6870                 }
6871                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6872                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6873                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6874         } else {
6875                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6876                                                    cld_filter, 1);
6877                 if (ret < 0) {
6878                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6879                         return ret;
6880                 }
6881                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6882         }
6883
6884         rte_free(cld_filter);
6885         return ret;
6886 }
6887
6888 static int
6889 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6890 {
6891         uint8_t i;
6892
6893         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6894                 if (pf->vxlan_ports[i] == port)
6895                         return i;
6896         }
6897
6898         return -1;
6899 }
6900
6901 static int
6902 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6903 {
6904         int  idx, ret;
6905         uint8_t filter_idx;
6906         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6907
6908         idx = i40e_get_vxlan_port_idx(pf, port);
6909
6910         /* Check if port already exists */
6911         if (idx >= 0) {
6912                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6913                 return -EINVAL;
6914         }
6915
6916         /* Now check if there is space to add the new port */
6917         idx = i40e_get_vxlan_port_idx(pf, 0);
6918         if (idx < 0) {
6919                 PMD_DRV_LOG(ERR,
6920                         "Maximum number of UDP ports reached, not adding port %d",
6921                         port);
6922                 return -ENOSPC;
6923         }
6924
6925         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6926                                         &filter_idx, NULL);
6927         if (ret < 0) {
6928                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6929                 return -1;
6930         }
6931
6932         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6933                          port,  filter_idx);
6934
6935         /* New port: add it and mark its index in the bitmap */
6936         pf->vxlan_ports[idx] = port;
6937         pf->vxlan_bitmap |= (1 << idx);
6938
6939         if (!(pf->flags & I40E_FLAG_VXLAN))
6940                 pf->flags |= I40E_FLAG_VXLAN;
6941
6942         return 0;
6943 }
6944
6945 static int
6946 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6947 {
6948         int idx;
6949         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6950
6951         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6952                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6953                 return -EINVAL;
6954         }
6955
6956         idx = i40e_get_vxlan_port_idx(pf, port);
6957
6958         if (idx < 0) {
6959                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6960                 return -EINVAL;
6961         }
6962
6963         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6964                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6965                 return -1;
6966         }
6967
6968         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6969                         port, idx);
6970
6971         pf->vxlan_ports[idx] = 0;
6972         pf->vxlan_bitmap &= ~(1 << idx);
6973
6974         if (!pf->vxlan_bitmap)
6975                 pf->flags &= ~I40E_FLAG_VXLAN;
6976
6977         return 0;
6978 }
6979
6980 /* Add UDP tunneling port */
6981 static int
6982 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6983                              struct rte_eth_udp_tunnel *udp_tunnel)
6984 {
6985         int ret = 0;
6986         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6987
6988         if (udp_tunnel == NULL)
6989                 return -EINVAL;
6990
6991         switch (udp_tunnel->prot_type) {
6992         case RTE_TUNNEL_TYPE_VXLAN:
6993                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6994                 break;
6995
6996         case RTE_TUNNEL_TYPE_GENEVE:
6997         case RTE_TUNNEL_TYPE_TEREDO:
6998                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6999                 ret = -1;
7000                 break;
7001
7002         default:
7003                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7004                 ret = -1;
7005                 break;
7006         }
7007
7008         return ret;
7009 }
7010
7011 /* Remove UDP tunneling port */
7012 static int
7013 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7014                              struct rte_eth_udp_tunnel *udp_tunnel)
7015 {
7016         int ret = 0;
7017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7018
7019         if (udp_tunnel == NULL)
7020                 return -EINVAL;
7021
7022         switch (udp_tunnel->prot_type) {
7023         case RTE_TUNNEL_TYPE_VXLAN:
7024                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7025                 break;
7026         case RTE_TUNNEL_TYPE_GENEVE:
7027         case RTE_TUNNEL_TYPE_TEREDO:
7028                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7029                 ret = -1;
7030                 break;
7031         default:
7032                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7033                 ret = -1;
7034                 break;
7035         }
7036
7037         return ret;
7038 }
7039
7040 /* Calculate the maximum number of contiguous PF queues that are configured */
7041 static int
7042 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7043 {
7044         struct rte_eth_dev_data *data = pf->dev_data;
7045         int i, num;
7046         struct i40e_rx_queue *rxq;
7047
7048         num = 0;
7049         for (i = 0; i < pf->lan_nb_qps; i++) {
7050                 rxq = data->rx_queues[i];
7051                 if (rxq && rxq->q_set)
7052                         num++;
7053                 else
7054                         break;
7055         }
7056
7057         return num;
7058 }
7059
7060 /* Configure RSS */
7061 static int
7062 i40e_pf_config_rss(struct i40e_pf *pf)
7063 {
7064         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7065         struct rte_eth_rss_conf rss_conf;
7066         uint32_t i, lut = 0;
7067         uint16_t j, num;
7068
7069         /*
7070          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7071          * It's necessary to calulate the actual PF queues that are configured.
7072          */
7073         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7074                 num = i40e_pf_calc_configured_queues_num(pf);
7075         else
7076                 num = pf->dev_data->nb_rx_queues;
7077
7078         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7079         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7080                         num);
7081
7082         if (num == 0) {
7083                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7084                 return -ENOTSUP;
7085         }
7086
7087         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7088                 if (j == num)
7089                         j = 0;
7090                 lut = (lut << 8) | (j & ((0x1 <<
7091                         hw->func_caps.rss_table_entry_width) - 1));
7092                 if ((i & 3) == 3)
7093                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7094         }
7095
7096         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7097         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7098                 i40e_pf_disable_rss(pf);
7099                 return 0;
7100         }
7101         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7102                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7103                 /* Random default keys */
7104                 static uint32_t rss_key_default[] = {0x6b793944,
7105                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7106                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7107                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7108
7109                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7110                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7111                                                         sizeof(uint32_t);
7112         }
7113
7114         return i40e_hw_rss_hash_set(pf, &rss_conf);
7115 }
7116
7117 static int
7118 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7119                                struct rte_eth_tunnel_filter_conf *filter)
7120 {
7121         if (pf == NULL || filter == NULL) {
7122                 PMD_DRV_LOG(ERR, "Invalid parameter");
7123                 return -EINVAL;
7124         }
7125
7126         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7127                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7128                 return -EINVAL;
7129         }
7130
7131         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7132                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7133                 return -EINVAL;
7134         }
7135
7136         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7137                 (is_zero_ether_addr(&filter->outer_mac))) {
7138                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7139                 return -EINVAL;
7140         }
7141
7142         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7143                 (is_zero_ether_addr(&filter->inner_mac))) {
7144                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7145                 return -EINVAL;
7146         }
7147
7148         return 0;
7149 }
7150
7151 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7152 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7153 static int
7154 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7155 {
7156         uint32_t val, reg;
7157         int ret = -EINVAL;
7158
7159         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7160         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7161
7162         if (len == 3) {
7163                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7164         } else if (len == 4) {
7165                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7166         } else {
7167                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7168                 return ret;
7169         }
7170
7171         if (reg != val) {
7172                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7173                                                    reg, NULL);
7174                 if (ret != 0)
7175                         return ret;
7176         } else {
7177                 ret = 0;
7178         }
7179         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7180                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7181
7182         return ret;
7183 }
7184
7185 static int
7186 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7187 {
7188         int ret = -EINVAL;
7189
7190         if (!hw || !cfg)
7191                 return -EINVAL;
7192
7193         switch (cfg->cfg_type) {
7194         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7195                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7196                 break;
7197         default:
7198                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7199                 break;
7200         }
7201
7202         return ret;
7203 }
7204
7205 static int
7206 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7207                                enum rte_filter_op filter_op,
7208                                void *arg)
7209 {
7210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7211         int ret = I40E_ERR_PARAM;
7212
7213         switch (filter_op) {
7214         case RTE_ETH_FILTER_SET:
7215                 ret = i40e_dev_global_config_set(hw,
7216                         (struct rte_eth_global_cfg *)arg);
7217                 break;
7218         default:
7219                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7220                 break;
7221         }
7222
7223         return ret;
7224 }
7225
7226 static int
7227 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7228                           enum rte_filter_op filter_op,
7229                           void *arg)
7230 {
7231         struct rte_eth_tunnel_filter_conf *filter;
7232         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7233         int ret = I40E_SUCCESS;
7234
7235         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7236
7237         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7238                 return I40E_ERR_PARAM;
7239
7240         switch (filter_op) {
7241         case RTE_ETH_FILTER_NOP:
7242                 if (!(pf->flags & I40E_FLAG_VXLAN))
7243                         ret = I40E_NOT_SUPPORTED;
7244                 break;
7245         case RTE_ETH_FILTER_ADD:
7246                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7247                 break;
7248         case RTE_ETH_FILTER_DELETE:
7249                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7250                 break;
7251         default:
7252                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7253                 ret = I40E_ERR_PARAM;
7254                 break;
7255         }
7256
7257         return ret;
7258 }
7259
7260 static int
7261 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7262 {
7263         int ret = 0;
7264         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7265
7266         /* RSS setup */
7267         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7268                 ret = i40e_pf_config_rss(pf);
7269         else
7270                 i40e_pf_disable_rss(pf);
7271
7272         return ret;
7273 }
7274
7275 /* Get the symmetric hash enable configurations per port */
7276 static void
7277 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7278 {
7279         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7280
7281         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7282 }
7283
7284 /* Set the symmetric hash enable configurations per port */
7285 static void
7286 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7287 {
7288         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7289
7290         if (enable > 0) {
7291                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7292                         PMD_DRV_LOG(INFO,
7293                                 "Symmetric hash has already been enabled");
7294                         return;
7295                 }
7296                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7297         } else {
7298                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7299                         PMD_DRV_LOG(INFO,
7300                                 "Symmetric hash has already been disabled");
7301                         return;
7302                 }
7303                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7304         }
7305         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7306         I40E_WRITE_FLUSH(hw);
7307 }
7308
7309 /*
7310  * Get global configurations of hash function type and symmetric hash enable
7311  * per flow type (pctype). Note that global configuration means it affects all
7312  * the ports on the same NIC.
7313  */
7314 static int
7315 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7316                                    struct rte_eth_hash_global_conf *g_cfg)
7317 {
7318         uint32_t reg, mask = I40E_FLOW_TYPES;
7319         uint16_t i;
7320         enum i40e_filter_pctype pctype;
7321
7322         memset(g_cfg, 0, sizeof(*g_cfg));
7323         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7324         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7325                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7326         else
7327                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7328         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7329                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7330
7331         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7332                 if (!(mask & (1UL << i)))
7333                         continue;
7334                 mask &= ~(1UL << i);
7335                 /* Bit set indicats the coresponding flow type is supported */
7336                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7337                 /* if flowtype is invalid, continue */
7338                 if (!I40E_VALID_FLOW(i))
7339                         continue;
7340                 pctype = i40e_flowtype_to_pctype(i);
7341                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7342                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7343                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7344         }
7345
7346         return 0;
7347 }
7348
7349 static int
7350 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7351 {
7352         uint32_t i;
7353         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7354
7355         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7356                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7357                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7358                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7359                                                 g_cfg->hash_func);
7360                 return -EINVAL;
7361         }
7362
7363         /*
7364          * As i40e supports less than 32 flow types, only first 32 bits need to
7365          * be checked.
7366          */
7367         mask0 = g_cfg->valid_bit_mask[0];
7368         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7369                 if (i == 0) {
7370                         /* Check if any unsupported flow type configured */
7371                         if ((mask0 | i40e_mask) ^ i40e_mask)
7372                                 goto mask_err;
7373                 } else {
7374                         if (g_cfg->valid_bit_mask[i])
7375                                 goto mask_err;
7376                 }
7377         }
7378
7379         return 0;
7380
7381 mask_err:
7382         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7383
7384         return -EINVAL;
7385 }
7386
7387 /*
7388  * Set global configurations of hash function type and symmetric hash enable
7389  * per flow type (pctype). Note any modifying global configuration will affect
7390  * all the ports on the same NIC.
7391  */
7392 static int
7393 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7394                                    struct rte_eth_hash_global_conf *g_cfg)
7395 {
7396         int ret;
7397         uint16_t i;
7398         uint32_t reg;
7399         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7400         enum i40e_filter_pctype pctype;
7401
7402         /* Check the input parameters */
7403         ret = i40e_hash_global_config_check(g_cfg);
7404         if (ret < 0)
7405                 return ret;
7406
7407         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7408                 if (!(mask0 & (1UL << i)))
7409                         continue;
7410                 mask0 &= ~(1UL << i);
7411                 /* if flowtype is invalid, continue */
7412                 if (!I40E_VALID_FLOW(i))
7413                         continue;
7414                 pctype = i40e_flowtype_to_pctype(i);
7415                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7416                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7417                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7418         }
7419
7420         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7421         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7422                 /* Toeplitz */
7423                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7424                         PMD_DRV_LOG(DEBUG,
7425                                 "Hash function already set to Toeplitz");
7426                         goto out;
7427                 }
7428                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7429         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7430                 /* Simple XOR */
7431                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7432                         PMD_DRV_LOG(DEBUG,
7433                                 "Hash function already set to Simple XOR");
7434                         goto out;
7435                 }
7436                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7437         } else
7438                 /* Use the default, and keep it as it is */
7439                 goto out;
7440
7441         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7442
7443 out:
7444         I40E_WRITE_FLUSH(hw);
7445
7446         return 0;
7447 }
7448
7449 /**
7450  * Valid input sets for hash and flow director filters per PCTYPE
7451  */
7452 static uint64_t
7453 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7454                 enum rte_filter_type filter)
7455 {
7456         uint64_t valid;
7457
7458         static const uint64_t valid_hash_inset_table[] = {
7459                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7460                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7461                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7462                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7463                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7464                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7465                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7466                         I40E_INSET_FLEX_PAYLOAD,
7467                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7468                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7469                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7470                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7471                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7472                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7474                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7475                         I40E_INSET_FLEX_PAYLOAD,
7476                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7477                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7478                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7479                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7480                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7481                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7482                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7483                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7484                         I40E_INSET_FLEX_PAYLOAD,
7485                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7486                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7487                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7488                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7489                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7490                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7491                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7492                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7493                         I40E_INSET_FLEX_PAYLOAD,
7494                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7495                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7496                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7497                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7498                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7499                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7500                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7501                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7502                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7503                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7504                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7505                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7506                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7507                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7508                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7509                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7510                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7511                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7512                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7513                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7514                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7515                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7516                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7517                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7518                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7519                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7520                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7521                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7522                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7523                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7524                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7525                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7526                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7527                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7528                         I40E_INSET_FLEX_PAYLOAD,
7529                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7530                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7531                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7532                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7533                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7534                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7535                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7536                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7537                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7538                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7539                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7540                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7541                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7542                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7543                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7544                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7545                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7546                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7547                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7548                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7549                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7550                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7551                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7552                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7553                         I40E_INSET_FLEX_PAYLOAD,
7554                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7555                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7556                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7557                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7558                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7559                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7560                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7561                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7562                         I40E_INSET_FLEX_PAYLOAD,
7563                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7564                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7565                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7566                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7567                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7568                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7569                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7570                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7571                         I40E_INSET_FLEX_PAYLOAD,
7572                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7573                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7574                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7575                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7576                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7577                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7578                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7579                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7580                         I40E_INSET_FLEX_PAYLOAD,
7581                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7582                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7583                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7584                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7585                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7586                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7587                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7588                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7589                         I40E_INSET_FLEX_PAYLOAD,
7590                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7591                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7592                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7593                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7594                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7595                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7596                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7597                         I40E_INSET_FLEX_PAYLOAD,
7598                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7599                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7600                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7601                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7602                         I40E_INSET_FLEX_PAYLOAD,
7603         };
7604
7605         /**
7606          * Flow director supports only fields defined in
7607          * union rte_eth_fdir_flow.
7608          */
7609         static const uint64_t valid_fdir_inset_table[] = {
7610                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7611                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7613                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7614                 I40E_INSET_IPV4_TTL,
7615                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7616                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7617                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7618                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7619                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7620                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7621                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7622                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7623                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7624                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7625                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7626                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7627                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7628                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7629                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7630                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7631                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7632                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7633                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7634                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7635                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7636                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7637                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7638                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7639                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7640                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7641                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7642                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7643                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7644                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7645                 I40E_INSET_SCTP_VT,
7646                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7647                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7649                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7650                 I40E_INSET_IPV4_TTL,
7651                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7652                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7653                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7654                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7655                 I40E_INSET_IPV6_HOP_LIMIT,
7656                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7657                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7658                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7659                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7660                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7661                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7662                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7663                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7664                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7665                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7666                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7667                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7668                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7669                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7670                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7671                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7672                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7673                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7674                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7675                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7676                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7677                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7678                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7679                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7680                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7681                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7682                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7683                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7684                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7685                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7686                 I40E_INSET_SCTP_VT,
7687                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7688                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7689                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7690                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7691                 I40E_INSET_IPV6_HOP_LIMIT,
7692                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7693                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7694                 I40E_INSET_LAST_ETHER_TYPE,
7695         };
7696
7697         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7698                 return 0;
7699         if (filter == RTE_ETH_FILTER_HASH)
7700                 valid = valid_hash_inset_table[pctype];
7701         else
7702                 valid = valid_fdir_inset_table[pctype];
7703
7704         return valid;
7705 }
7706
7707 /**
7708  * Validate if the input set is allowed for a specific PCTYPE
7709  */
7710 static int
7711 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7712                 enum rte_filter_type filter, uint64_t inset)
7713 {
7714         uint64_t valid;
7715
7716         valid = i40e_get_valid_input_set(pctype, filter);
7717         if (inset & (~valid))
7718                 return -EINVAL;
7719
7720         return 0;
7721 }
7722
7723 /* default input set fields combination per pctype */
7724 uint64_t
7725 i40e_get_default_input_set(uint16_t pctype)
7726 {
7727         static const uint64_t default_inset_table[] = {
7728                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7729                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7730                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7731                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7732                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7733                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7734                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7735                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7736                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7737                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7738                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7739                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7740                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7741                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7742                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7743                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7744                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7745                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7746                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7747                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7748                         I40E_INSET_SCTP_VT,
7749                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7750                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7751                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7752                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7753                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7754                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7757                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7759                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7760                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7761                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7762                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7763                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7764                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7765                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7766                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7767                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7768                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7769                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7770                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7771                         I40E_INSET_SCTP_VT,
7772                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7773                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7774                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7775                         I40E_INSET_LAST_ETHER_TYPE,
7776         };
7777
7778         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7779                 return 0;
7780
7781         return default_inset_table[pctype];
7782 }
7783
7784 /**
7785  * Parse the input set from index to logical bit masks
7786  */
7787 static int
7788 i40e_parse_input_set(uint64_t *inset,
7789                      enum i40e_filter_pctype pctype,
7790                      enum rte_eth_input_set_field *field,
7791                      uint16_t size)
7792 {
7793         uint16_t i, j;
7794         int ret = -EINVAL;
7795
7796         static const struct {
7797                 enum rte_eth_input_set_field field;
7798                 uint64_t inset;
7799         } inset_convert_table[] = {
7800                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7801                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7802                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7803                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7804                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7805                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7806                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7807                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7808                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7809                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7810                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7811                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7812                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7813                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7814                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7815                         I40E_INSET_IPV6_NEXT_HDR},
7816                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7817                         I40E_INSET_IPV6_HOP_LIMIT},
7818                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7819                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7820                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7821                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7822                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7823                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7824                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7825                         I40E_INSET_SCTP_VT},
7826                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7827                         I40E_INSET_TUNNEL_DMAC},
7828                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7829                         I40E_INSET_VLAN_TUNNEL},
7830                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7831                         I40E_INSET_TUNNEL_ID},
7832                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7833                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7834                         I40E_INSET_FLEX_PAYLOAD_W1},
7835                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7836                         I40E_INSET_FLEX_PAYLOAD_W2},
7837                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7838                         I40E_INSET_FLEX_PAYLOAD_W3},
7839                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7840                         I40E_INSET_FLEX_PAYLOAD_W4},
7841                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7842                         I40E_INSET_FLEX_PAYLOAD_W5},
7843                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7844                         I40E_INSET_FLEX_PAYLOAD_W6},
7845                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7846                         I40E_INSET_FLEX_PAYLOAD_W7},
7847                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7848                         I40E_INSET_FLEX_PAYLOAD_W8},
7849         };
7850
7851         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7852                 return ret;
7853
7854         /* Only one item allowed for default or all */
7855         if (size == 1) {
7856                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7857                         *inset = i40e_get_default_input_set(pctype);
7858                         return 0;
7859                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7860                         *inset = I40E_INSET_NONE;
7861                         return 0;
7862                 }
7863         }
7864
7865         for (i = 0, *inset = 0; i < size; i++) {
7866                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7867                         if (field[i] == inset_convert_table[j].field) {
7868                                 *inset |= inset_convert_table[j].inset;
7869                                 break;
7870                         }
7871                 }
7872
7873                 /* It contains unsupported input set, return immediately */
7874                 if (j == RTE_DIM(inset_convert_table))
7875                         return ret;
7876         }
7877
7878         return 0;
7879 }
7880
7881 /**
7882  * Translate the input set from bit masks to register aware bit masks
7883  * and vice versa
7884  */
7885 static uint64_t
7886 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7887 {
7888         uint64_t val = 0;
7889         uint16_t i;
7890
7891         struct inset_map {
7892                 uint64_t inset;
7893                 uint64_t inset_reg;
7894         };
7895
7896         static const struct inset_map inset_map_common[] = {
7897                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7898                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7899                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7900                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7901                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7902                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7903                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7904                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7905                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7906                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7907                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7908                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7909                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7910                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7911                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7912                 {I40E_INSET_TUNNEL_DMAC,
7913                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7914                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7915                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7916                 {I40E_INSET_TUNNEL_SRC_PORT,
7917                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7918                 {I40E_INSET_TUNNEL_DST_PORT,
7919                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7920                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7921                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7922                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7923                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7924                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7925                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7926                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7927                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7928                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7929         };
7930
7931     /* some different registers map in x722*/
7932         static const struct inset_map inset_map_diff_x722[] = {
7933                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7934                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7935                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7936                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7937         };
7938
7939         static const struct inset_map inset_map_diff_not_x722[] = {
7940                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7941                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7942                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7943                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7944         };
7945
7946         if (input == 0)
7947                 return val;
7948
7949         /* Translate input set to register aware inset */
7950         if (type == I40E_MAC_X722) {
7951                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7952                         if (input & inset_map_diff_x722[i].inset)
7953                                 val |= inset_map_diff_x722[i].inset_reg;
7954                 }
7955         } else {
7956                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7957                         if (input & inset_map_diff_not_x722[i].inset)
7958                                 val |= inset_map_diff_not_x722[i].inset_reg;
7959                 }
7960         }
7961
7962         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7963                 if (input & inset_map_common[i].inset)
7964                         val |= inset_map_common[i].inset_reg;
7965         }
7966
7967         return val;
7968 }
7969
7970 static int
7971 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7972 {
7973         uint8_t i, idx = 0;
7974         uint64_t inset_need_mask = inset;
7975
7976         static const struct {
7977                 uint64_t inset;
7978                 uint32_t mask;
7979         } inset_mask_map[] = {
7980                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7981                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7982                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7983                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7984                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7985                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7986                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7987                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7988         };
7989
7990         if (!inset || !mask || !nb_elem)
7991                 return 0;
7992
7993         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7994                 /* Clear the inset bit, if no MASK is required,
7995                  * for example proto + ttl
7996                  */
7997                 if ((inset & inset_mask_map[i].inset) ==
7998                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7999                         inset_need_mask &= ~inset_mask_map[i].inset;
8000                 if (!inset_need_mask)
8001                         return 0;
8002         }
8003         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8004                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8005                     inset_mask_map[i].inset) {
8006                         if (idx >= nb_elem) {
8007                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8008                                 return -EINVAL;
8009                         }
8010                         mask[idx] = inset_mask_map[i].mask;
8011                         idx++;
8012                 }
8013         }
8014
8015         return idx;
8016 }
8017
8018 static void
8019 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8020 {
8021         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8022
8023         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8024         if (reg != val)
8025                 i40e_write_rx_ctl(hw, addr, val);
8026         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8027                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8028 }
8029
8030 static void
8031 i40e_filter_input_set_init(struct i40e_pf *pf)
8032 {
8033         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8034         enum i40e_filter_pctype pctype;
8035         uint64_t input_set, inset_reg;
8036         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8037         int num, i;
8038
8039         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8040              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8041                 if (hw->mac.type == I40E_MAC_X722) {
8042                         if (!I40E_VALID_PCTYPE_X722(pctype))
8043                                 continue;
8044                 } else {
8045                         if (!I40E_VALID_PCTYPE(pctype))
8046                                 continue;
8047                 }
8048
8049                 input_set = i40e_get_default_input_set(pctype);
8050
8051                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8052                                                    I40E_INSET_MASK_NUM_REG);
8053                 if (num < 0)
8054                         return;
8055                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8056                                         input_set);
8057
8058                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8059                                       (uint32_t)(inset_reg & UINT32_MAX));
8060                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8061                                      (uint32_t)((inset_reg >>
8062                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8063                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8064                                       (uint32_t)(inset_reg & UINT32_MAX));
8065                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8066                                      (uint32_t)((inset_reg >>
8067                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8068
8069                 for (i = 0; i < num; i++) {
8070                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8071                                              mask_reg[i]);
8072                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8073                                              mask_reg[i]);
8074                 }
8075                 /*clear unused mask registers of the pctype */
8076                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8077                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8078                                              0);
8079                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8080                                              0);
8081                 }
8082                 I40E_WRITE_FLUSH(hw);
8083
8084                 /* store the default input set */
8085                 pf->hash_input_set[pctype] = input_set;
8086                 pf->fdir.input_set[pctype] = input_set;
8087         }
8088 }
8089
8090 int
8091 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8092                          struct rte_eth_input_set_conf *conf)
8093 {
8094         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8095         enum i40e_filter_pctype pctype;
8096         uint64_t input_set, inset_reg = 0;
8097         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8098         int ret, i, num;
8099
8100         if (!conf) {
8101                 PMD_DRV_LOG(ERR, "Invalid pointer");
8102                 return -EFAULT;
8103         }
8104         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8105             conf->op != RTE_ETH_INPUT_SET_ADD) {
8106                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8107                 return -EINVAL;
8108         }
8109
8110         if (!I40E_VALID_FLOW(conf->flow_type)) {
8111                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8112                 return -EINVAL;
8113         }
8114
8115         if (hw->mac.type == I40E_MAC_X722) {
8116                 /* get translated pctype value in fd pctype register */
8117                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8118                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8119                         conf->flow_type)));
8120         } else
8121                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8122
8123         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8124                                    conf->inset_size);
8125         if (ret) {
8126                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8127                 return -EINVAL;
8128         }
8129         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8130                                     input_set) != 0) {
8131                 PMD_DRV_LOG(ERR, "Invalid input set");
8132                 return -EINVAL;
8133         }
8134         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8135                 /* get inset value in register */
8136                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8137                 inset_reg <<= I40E_32_BIT_WIDTH;
8138                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8139                 input_set |= pf->hash_input_set[pctype];
8140         }
8141         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8142                                            I40E_INSET_MASK_NUM_REG);
8143         if (num < 0)
8144                 return -EINVAL;
8145
8146         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8147
8148         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8149                               (uint32_t)(inset_reg & UINT32_MAX));
8150         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8151                              (uint32_t)((inset_reg >>
8152                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8153
8154         for (i = 0; i < num; i++)
8155                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8156                                      mask_reg[i]);
8157         /*clear unused mask registers of the pctype */
8158         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8159                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8160                                      0);
8161         I40E_WRITE_FLUSH(hw);
8162
8163         pf->hash_input_set[pctype] = input_set;
8164         return 0;
8165 }
8166
8167 int
8168 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8169                          struct rte_eth_input_set_conf *conf)
8170 {
8171         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8172         enum i40e_filter_pctype pctype;
8173         uint64_t input_set, inset_reg = 0;
8174         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8175         int ret, i, num;
8176
8177         if (!hw || !conf) {
8178                 PMD_DRV_LOG(ERR, "Invalid pointer");
8179                 return -EFAULT;
8180         }
8181         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8182             conf->op != RTE_ETH_INPUT_SET_ADD) {
8183                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8184                 return -EINVAL;
8185         }
8186
8187         if (!I40E_VALID_FLOW(conf->flow_type)) {
8188                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8189                 return -EINVAL;
8190         }
8191
8192         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8193
8194         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8195                                    conf->inset_size);
8196         if (ret) {
8197                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8198                 return -EINVAL;
8199         }
8200         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8201                                     input_set) != 0) {
8202                 PMD_DRV_LOG(ERR, "Invalid input set");
8203                 return -EINVAL;
8204         }
8205
8206         /* get inset value in register */
8207         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8208         inset_reg <<= I40E_32_BIT_WIDTH;
8209         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8210
8211         /* Can not change the inset reg for flex payload for fdir,
8212          * it is done by writing I40E_PRTQF_FD_FLXINSET
8213          * in i40e_set_flex_mask_on_pctype.
8214          */
8215         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8216                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8217         else
8218                 input_set |= pf->fdir.input_set[pctype];
8219         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8220                                            I40E_INSET_MASK_NUM_REG);
8221         if (num < 0)
8222                 return -EINVAL;
8223
8224         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8225
8226         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8227                               (uint32_t)(inset_reg & UINT32_MAX));
8228         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8229                              (uint32_t)((inset_reg >>
8230                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8231
8232         for (i = 0; i < num; i++)
8233                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8234                                      mask_reg[i]);
8235         /*clear unused mask registers of the pctype */
8236         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8237                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8238                                      0);
8239         I40E_WRITE_FLUSH(hw);
8240
8241         pf->fdir.input_set[pctype] = input_set;
8242         return 0;
8243 }
8244
8245 static int
8246 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8247 {
8248         int ret = 0;
8249
8250         if (!hw || !info) {
8251                 PMD_DRV_LOG(ERR, "Invalid pointer");
8252                 return -EFAULT;
8253         }
8254
8255         switch (info->info_type) {
8256         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8257                 i40e_get_symmetric_hash_enable_per_port(hw,
8258                                         &(info->info.enable));
8259                 break;
8260         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8261                 ret = i40e_get_hash_filter_global_config(hw,
8262                                 &(info->info.global_conf));
8263                 break;
8264         default:
8265                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8266                                                         info->info_type);
8267                 ret = -EINVAL;
8268                 break;
8269         }
8270
8271         return ret;
8272 }
8273
8274 static int
8275 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8276 {
8277         int ret = 0;
8278
8279         if (!hw || !info) {
8280                 PMD_DRV_LOG(ERR, "Invalid pointer");
8281                 return -EFAULT;
8282         }
8283
8284         switch (info->info_type) {
8285         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8286                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8287                 break;
8288         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8289                 ret = i40e_set_hash_filter_global_config(hw,
8290                                 &(info->info.global_conf));
8291                 break;
8292         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8293                 ret = i40e_hash_filter_inset_select(hw,
8294                                                &(info->info.input_set_conf));
8295                 break;
8296
8297         default:
8298                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8299                                                         info->info_type);
8300                 ret = -EINVAL;
8301                 break;
8302         }
8303
8304         return ret;
8305 }
8306
8307 /* Operations for hash function */
8308 static int
8309 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8310                       enum rte_filter_op filter_op,
8311                       void *arg)
8312 {
8313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8314         int ret = 0;
8315
8316         switch (filter_op) {
8317         case RTE_ETH_FILTER_NOP:
8318                 break;
8319         case RTE_ETH_FILTER_GET:
8320                 ret = i40e_hash_filter_get(hw,
8321                         (struct rte_eth_hash_filter_info *)arg);
8322                 break;
8323         case RTE_ETH_FILTER_SET:
8324                 ret = i40e_hash_filter_set(hw,
8325                         (struct rte_eth_hash_filter_info *)arg);
8326                 break;
8327         default:
8328                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8329                                                                 filter_op);
8330                 ret = -ENOTSUP;
8331                 break;
8332         }
8333
8334         return ret;
8335 }
8336
8337 /* Convert ethertype filter structure */
8338 static int
8339 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8340                               struct i40e_ethertype_filter *filter)
8341 {
8342         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8343         filter->input.ether_type = input->ether_type;
8344         filter->flags = input->flags;
8345         filter->queue = input->queue;
8346
8347         return 0;
8348 }
8349
8350 /* Check if there exists the ehtertype filter */
8351 struct i40e_ethertype_filter *
8352 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8353                                 const struct i40e_ethertype_filter_input *input)
8354 {
8355         int ret;
8356
8357         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8358         if (ret < 0)
8359                 return NULL;
8360
8361         return ethertype_rule->hash_map[ret];
8362 }
8363
8364 /* Add ethertype filter in SW list */
8365 static int
8366 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8367                                 struct i40e_ethertype_filter *filter)
8368 {
8369         struct i40e_ethertype_rule *rule = &pf->ethertype;
8370         int ret;
8371
8372         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8373         if (ret < 0) {
8374                 PMD_DRV_LOG(ERR,
8375                             "Failed to insert ethertype filter"
8376                             " to hash table %d!",
8377                             ret);
8378                 return ret;
8379         }
8380         rule->hash_map[ret] = filter;
8381
8382         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8383
8384         return 0;
8385 }
8386
8387 /* Delete ethertype filter in SW list */
8388 int
8389 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8390                              struct i40e_ethertype_filter_input *input)
8391 {
8392         struct i40e_ethertype_rule *rule = &pf->ethertype;
8393         struct i40e_ethertype_filter *filter;
8394         int ret;
8395
8396         ret = rte_hash_del_key(rule->hash_table, input);
8397         if (ret < 0) {
8398                 PMD_DRV_LOG(ERR,
8399                             "Failed to delete ethertype filter"
8400                             " to hash table %d!",
8401                             ret);
8402                 return ret;
8403         }
8404         filter = rule->hash_map[ret];
8405         rule->hash_map[ret] = NULL;
8406
8407         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8408         rte_free(filter);
8409
8410         return 0;
8411 }
8412
8413 /*
8414  * Configure ethertype filter, which can director packet by filtering
8415  * with mac address and ether_type or only ether_type
8416  */
8417 int
8418 i40e_ethertype_filter_set(struct i40e_pf *pf,
8419                         struct rte_eth_ethertype_filter *filter,
8420                         bool add)
8421 {
8422         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8423         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8424         struct i40e_ethertype_filter *ethertype_filter, *node;
8425         struct i40e_ethertype_filter check_filter;
8426         struct i40e_control_filter_stats stats;
8427         uint16_t flags = 0;
8428         int ret;
8429
8430         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8431                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8432                 return -EINVAL;
8433         }
8434         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8435                 filter->ether_type == ETHER_TYPE_IPv6) {
8436                 PMD_DRV_LOG(ERR,
8437                         "unsupported ether_type(0x%04x) in control packet filter.",
8438                         filter->ether_type);
8439                 return -EINVAL;
8440         }
8441         if (filter->ether_type == ETHER_TYPE_VLAN)
8442                 PMD_DRV_LOG(WARNING,
8443                         "filter vlan ether_type in first tag is not supported.");
8444
8445         /* Check if there is the filter in SW list */
8446         memset(&check_filter, 0, sizeof(check_filter));
8447         i40e_ethertype_filter_convert(filter, &check_filter);
8448         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8449                                                &check_filter.input);
8450         if (add && node) {
8451                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8452                 return -EINVAL;
8453         }
8454
8455         if (!add && !node) {
8456                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8457                 return -EINVAL;
8458         }
8459
8460         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8461                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8462         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8463                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8464         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8465
8466         memset(&stats, 0, sizeof(stats));
8467         ret = i40e_aq_add_rem_control_packet_filter(hw,
8468                         filter->mac_addr.addr_bytes,
8469                         filter->ether_type, flags,
8470                         pf->main_vsi->seid,
8471                         filter->queue, add, &stats, NULL);
8472
8473         PMD_DRV_LOG(INFO,
8474                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u\n",
8475                 ret, stats.mac_etype_used, stats.etype_used,
8476                 stats.mac_etype_free, stats.etype_free);
8477         if (ret < 0)
8478                 return -ENOSYS;
8479
8480         /* Add or delete a filter in SW list */
8481         if (add) {
8482                 ethertype_filter = rte_zmalloc("ethertype_filter",
8483                                        sizeof(*ethertype_filter), 0);
8484                 rte_memcpy(ethertype_filter, &check_filter,
8485                            sizeof(check_filter));
8486                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8487         } else {
8488                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8489         }
8490
8491         return ret;
8492 }
8493
8494 /*
8495  * Handle operations for ethertype filter.
8496  */
8497 static int
8498 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8499                                 enum rte_filter_op filter_op,
8500                                 void *arg)
8501 {
8502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8503         int ret = 0;
8504
8505         if (filter_op == RTE_ETH_FILTER_NOP)
8506                 return ret;
8507
8508         if (arg == NULL) {
8509                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8510                             filter_op);
8511                 return -EINVAL;
8512         }
8513
8514         switch (filter_op) {
8515         case RTE_ETH_FILTER_ADD:
8516                 ret = i40e_ethertype_filter_set(pf,
8517                         (struct rte_eth_ethertype_filter *)arg,
8518                         TRUE);
8519                 break;
8520         case RTE_ETH_FILTER_DELETE:
8521                 ret = i40e_ethertype_filter_set(pf,
8522                         (struct rte_eth_ethertype_filter *)arg,
8523                         FALSE);
8524                 break;
8525         default:
8526                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8527                 ret = -ENOSYS;
8528                 break;
8529         }
8530         return ret;
8531 }
8532
8533 static int
8534 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8535                      enum rte_filter_type filter_type,
8536                      enum rte_filter_op filter_op,
8537                      void *arg)
8538 {
8539         int ret = 0;
8540
8541         if (dev == NULL)
8542                 return -EINVAL;
8543
8544         switch (filter_type) {
8545         case RTE_ETH_FILTER_NONE:
8546                 /* For global configuration */
8547                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8548                 break;
8549         case RTE_ETH_FILTER_HASH:
8550                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8551                 break;
8552         case RTE_ETH_FILTER_MACVLAN:
8553                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8554                 break;
8555         case RTE_ETH_FILTER_ETHERTYPE:
8556                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8557                 break;
8558         case RTE_ETH_FILTER_TUNNEL:
8559                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8560                 break;
8561         case RTE_ETH_FILTER_FDIR:
8562                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8563                 break;
8564         case RTE_ETH_FILTER_GENERIC:
8565                 if (filter_op != RTE_ETH_FILTER_GET)
8566                         return -EINVAL;
8567                 *(const void **)arg = &i40e_flow_ops;
8568                 break;
8569         default:
8570                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8571                                                         filter_type);
8572                 ret = -EINVAL;
8573                 break;
8574         }
8575
8576         return ret;
8577 }
8578
8579 /*
8580  * Check and enable Extended Tag.
8581  * Enabling Extended Tag is important for 40G performance.
8582  */
8583 static void
8584 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8585 {
8586         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8587         uint32_t buf = 0;
8588         int ret;
8589
8590         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8591                                       PCI_DEV_CAP_REG);
8592         if (ret < 0) {
8593                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8594                             PCI_DEV_CAP_REG);
8595                 return;
8596         }
8597         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8598                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8599                 return;
8600         }
8601
8602         buf = 0;
8603         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8604                                       PCI_DEV_CTRL_REG);
8605         if (ret < 0) {
8606                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8607                             PCI_DEV_CTRL_REG);
8608                 return;
8609         }
8610         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8611                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8612                 return;
8613         }
8614         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8615         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8616                                        PCI_DEV_CTRL_REG);
8617         if (ret < 0) {
8618                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8619                             PCI_DEV_CTRL_REG);
8620                 return;
8621         }
8622 }
8623
8624 /*
8625  * As some registers wouldn't be reset unless a global hardware reset,
8626  * hardware initialization is needed to put those registers into an
8627  * expected initial state.
8628  */
8629 static void
8630 i40e_hw_init(struct rte_eth_dev *dev)
8631 {
8632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8633
8634         i40e_enable_extended_tag(dev);
8635
8636         /* clear the PF Queue Filter control register */
8637         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8638
8639         /* Disable symmetric hash per port */
8640         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8641 }
8642
8643 enum i40e_filter_pctype
8644 i40e_flowtype_to_pctype(uint16_t flow_type)
8645 {
8646         static const enum i40e_filter_pctype pctype_table[] = {
8647                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8648                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8649                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8650                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8651                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8652                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8653                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8654                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8655                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8656                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8657                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8658                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8659                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8660                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8661                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8662                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8663                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8664                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8665                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8666         };
8667
8668         return pctype_table[flow_type];
8669 }
8670
8671 uint16_t
8672 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8673 {
8674         static const uint16_t flowtype_table[] = {
8675                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8676                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8677                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8678                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8679                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8680                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8681                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8682                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8683                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8684                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8685                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8686                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8687                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8688                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8689                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8690                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8691                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8692                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8693                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8694                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8695                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8696                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8697                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8698                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8699                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8700                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8701                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8702                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8703                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8704                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8705                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8706         };
8707
8708         return flowtype_table[pctype];
8709 }
8710
8711 /*
8712  * On X710, performance number is far from the expectation on recent firmware
8713  * versions; on XL710, performance number is also far from the expectation on
8714  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8715  * mode is enabled and port MAC address is equal to the packet destination MAC
8716  * address. The fix for this issue may not be integrated in the following
8717  * firmware version. So the workaround in software driver is needed. It needs
8718  * to modify the initial values of 3 internal only registers for both X710 and
8719  * XL710. Note that the values for X710 or XL710 could be different, and the
8720  * workaround can be removed when it is fixed in firmware in the future.
8721  */
8722
8723 /* For both X710 and XL710 */
8724 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8725 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8726
8727 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8728 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8729
8730 /* For X710 */
8731 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8732 /* For XL710 */
8733 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8734 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8735
8736 static int
8737 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8738 {
8739         enum i40e_status_code status;
8740         struct i40e_aq_get_phy_abilities_resp phy_ab;
8741         int ret = -ENOTSUP;
8742
8743         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8744                                               NULL);
8745
8746         if (status)
8747                 return ret;
8748
8749         return 0;
8750 }
8751
8752
8753 static void
8754 i40e_configure_registers(struct i40e_hw *hw)
8755 {
8756         static struct {
8757                 uint32_t addr;
8758                 uint64_t val;
8759         } reg_table[] = {
8760                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8761                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8762                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8763         };
8764         uint64_t reg;
8765         uint32_t i;
8766         int ret;
8767
8768         for (i = 0; i < RTE_DIM(reg_table); i++) {
8769                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8770                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8771                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8772                                 reg_table[i].val =
8773                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8774                         else /* For X710 */
8775                                 reg_table[i].val =
8776                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8777                 }
8778
8779                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8780                                                         &reg, NULL);
8781                 if (ret < 0) {
8782                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8783                                                         reg_table[i].addr);
8784                         break;
8785                 }
8786                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8787                                                 reg_table[i].addr, reg);
8788                 if (reg == reg_table[i].val)
8789                         continue;
8790
8791                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8792                                                 reg_table[i].val, NULL);
8793                 if (ret < 0) {
8794                         PMD_DRV_LOG(ERR,
8795                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8796                                 reg_table[i].val, reg_table[i].addr);
8797                         break;
8798                 }
8799                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8800                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8801         }
8802 }
8803
8804 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8805 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8806 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8807 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8808 static int
8809 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8810 {
8811         uint32_t reg;
8812         int ret;
8813
8814         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8815                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8816                 return -EINVAL;
8817         }
8818
8819         /* Configure for double VLAN RX stripping */
8820         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8821         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8822                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8823                 ret = i40e_aq_debug_write_register(hw,
8824                                                    I40E_VSI_TSR(vsi->vsi_id),
8825                                                    reg, NULL);
8826                 if (ret < 0) {
8827                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8828                                     vsi->vsi_id);
8829                         return I40E_ERR_CONFIG;
8830                 }
8831         }
8832
8833         /* Configure for double VLAN TX insertion */
8834         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8835         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8836                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8837                 ret = i40e_aq_debug_write_register(hw,
8838                                                    I40E_VSI_L2TAGSTXVALID(
8839                                                    vsi->vsi_id), reg, NULL);
8840                 if (ret < 0) {
8841                         PMD_DRV_LOG(ERR,
8842                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8843                                 vsi->vsi_id);
8844                         return I40E_ERR_CONFIG;
8845                 }
8846         }
8847
8848         return 0;
8849 }
8850
8851 /**
8852  * i40e_aq_add_mirror_rule
8853  * @hw: pointer to the hardware structure
8854  * @seid: VEB seid to add mirror rule to
8855  * @dst_id: destination vsi seid
8856  * @entries: Buffer which contains the entities to be mirrored
8857  * @count: number of entities contained in the buffer
8858  * @rule_id:the rule_id of the rule to be added
8859  *
8860  * Add a mirror rule for a given veb.
8861  *
8862  **/
8863 static enum i40e_status_code
8864 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8865                         uint16_t seid, uint16_t dst_id,
8866                         uint16_t rule_type, uint16_t *entries,
8867                         uint16_t count, uint16_t *rule_id)
8868 {
8869         struct i40e_aq_desc desc;
8870         struct i40e_aqc_add_delete_mirror_rule cmd;
8871         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8872                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8873                 &desc.params.raw;
8874         uint16_t buff_len;
8875         enum i40e_status_code status;
8876
8877         i40e_fill_default_direct_cmd_desc(&desc,
8878                                           i40e_aqc_opc_add_mirror_rule);
8879         memset(&cmd, 0, sizeof(cmd));
8880
8881         buff_len = sizeof(uint16_t) * count;
8882         desc.datalen = rte_cpu_to_le_16(buff_len);
8883         if (buff_len > 0)
8884                 desc.flags |= rte_cpu_to_le_16(
8885                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8886         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8887                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8888         cmd.num_entries = rte_cpu_to_le_16(count);
8889         cmd.seid = rte_cpu_to_le_16(seid);
8890         cmd.destination = rte_cpu_to_le_16(dst_id);
8891
8892         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8893         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8894         PMD_DRV_LOG(INFO,
8895                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8896                 hw->aq.asq_last_status, resp->rule_id,
8897                 resp->mirror_rules_used, resp->mirror_rules_free);
8898         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8899
8900         return status;
8901 }
8902
8903 /**
8904  * i40e_aq_del_mirror_rule
8905  * @hw: pointer to the hardware structure
8906  * @seid: VEB seid to add mirror rule to
8907  * @entries: Buffer which contains the entities to be mirrored
8908  * @count: number of entities contained in the buffer
8909  * @rule_id:the rule_id of the rule to be delete
8910  *
8911  * Delete a mirror rule for a given veb.
8912  *
8913  **/
8914 static enum i40e_status_code
8915 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8916                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8917                 uint16_t count, uint16_t rule_id)
8918 {
8919         struct i40e_aq_desc desc;
8920         struct i40e_aqc_add_delete_mirror_rule cmd;
8921         uint16_t buff_len = 0;
8922         enum i40e_status_code status;
8923         void *buff = NULL;
8924
8925         i40e_fill_default_direct_cmd_desc(&desc,
8926                                           i40e_aqc_opc_delete_mirror_rule);
8927         memset(&cmd, 0, sizeof(cmd));
8928         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8929                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8930                                                           I40E_AQ_FLAG_RD));
8931                 cmd.num_entries = count;
8932                 buff_len = sizeof(uint16_t) * count;
8933                 desc.datalen = rte_cpu_to_le_16(buff_len);
8934                 buff = (void *)entries;
8935         } else
8936                 /* rule id is filled in destination field for deleting mirror rule */
8937                 cmd.destination = rte_cpu_to_le_16(rule_id);
8938
8939         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8940                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8941         cmd.seid = rte_cpu_to_le_16(seid);
8942
8943         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8944         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8945
8946         return status;
8947 }
8948
8949 /**
8950  * i40e_mirror_rule_set
8951  * @dev: pointer to the hardware structure
8952  * @mirror_conf: mirror rule info
8953  * @sw_id: mirror rule's sw_id
8954  * @on: enable/disable
8955  *
8956  * set a mirror rule.
8957  *
8958  **/
8959 static int
8960 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8961                         struct rte_eth_mirror_conf *mirror_conf,
8962                         uint8_t sw_id, uint8_t on)
8963 {
8964         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8966         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8967         struct i40e_mirror_rule *parent = NULL;
8968         uint16_t seid, dst_seid, rule_id;
8969         uint16_t i, j = 0;
8970         int ret;
8971
8972         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8973
8974         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8975                 PMD_DRV_LOG(ERR,
8976                         "mirror rule can not be configured without veb or vfs.");
8977                 return -ENOSYS;
8978         }
8979         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8980                 PMD_DRV_LOG(ERR, "mirror table is full.");
8981                 return -ENOSPC;
8982         }
8983         if (mirror_conf->dst_pool > pf->vf_num) {
8984                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8985                                  mirror_conf->dst_pool);
8986                 return -EINVAL;
8987         }
8988
8989         seid = pf->main_vsi->veb->seid;
8990
8991         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8992                 if (sw_id <= it->index) {
8993                         mirr_rule = it;
8994                         break;
8995                 }
8996                 parent = it;
8997         }
8998         if (mirr_rule && sw_id == mirr_rule->index) {
8999                 if (on) {
9000                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9001                         return -EEXIST;
9002                 } else {
9003                         ret = i40e_aq_del_mirror_rule(hw, seid,
9004                                         mirr_rule->rule_type,
9005                                         mirr_rule->entries,
9006                                         mirr_rule->num_entries, mirr_rule->id);
9007                         if (ret < 0) {
9008                                 PMD_DRV_LOG(ERR,
9009                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9010                                         ret, hw->aq.asq_last_status);
9011                                 return -ENOSYS;
9012                         }
9013                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9014                         rte_free(mirr_rule);
9015                         pf->nb_mirror_rule--;
9016                         return 0;
9017                 }
9018         } else if (!on) {
9019                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9020                 return -ENOENT;
9021         }
9022
9023         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9024                                 sizeof(struct i40e_mirror_rule) , 0);
9025         if (!mirr_rule) {
9026                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9027                 return I40E_ERR_NO_MEMORY;
9028         }
9029         switch (mirror_conf->rule_type) {
9030         case ETH_MIRROR_VLAN:
9031                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9032                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9033                                 mirr_rule->entries[j] =
9034                                         mirror_conf->vlan.vlan_id[i];
9035                                 j++;
9036                         }
9037                 }
9038                 if (j == 0) {
9039                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9040                         rte_free(mirr_rule);
9041                         return -EINVAL;
9042                 }
9043                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9044                 break;
9045         case ETH_MIRROR_VIRTUAL_POOL_UP:
9046         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9047                 /* check if the specified pool bit is out of range */
9048                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9049                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9050                         rte_free(mirr_rule);
9051                         return -EINVAL;
9052                 }
9053                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9054                         if (mirror_conf->pool_mask & (1ULL << i)) {
9055                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9056                                 j++;
9057                         }
9058                 }
9059                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9060                         /* add pf vsi to entries */
9061                         mirr_rule->entries[j] = pf->main_vsi_seid;
9062                         j++;
9063                 }
9064                 if (j == 0) {
9065                         PMD_DRV_LOG(ERR, "pool is not specified.");
9066                         rte_free(mirr_rule);
9067                         return -EINVAL;
9068                 }
9069                 /* egress and ingress in aq commands means from switch but not port */
9070                 mirr_rule->rule_type =
9071                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9072                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9073                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9074                 break;
9075         case ETH_MIRROR_UPLINK_PORT:
9076                 /* egress and ingress in aq commands means from switch but not port*/
9077                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9078                 break;
9079         case ETH_MIRROR_DOWNLINK_PORT:
9080                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9081                 break;
9082         default:
9083                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9084                         mirror_conf->rule_type);
9085                 rte_free(mirr_rule);
9086                 return -EINVAL;
9087         }
9088
9089         /* If the dst_pool is equal to vf_num, consider it as PF */
9090         if (mirror_conf->dst_pool == pf->vf_num)
9091                 dst_seid = pf->main_vsi_seid;
9092         else
9093                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9094
9095         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9096                                       mirr_rule->rule_type, mirr_rule->entries,
9097                                       j, &rule_id);
9098         if (ret < 0) {
9099                 PMD_DRV_LOG(ERR,
9100                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9101                         ret, hw->aq.asq_last_status);
9102                 rte_free(mirr_rule);
9103                 return -ENOSYS;
9104         }
9105
9106         mirr_rule->index = sw_id;
9107         mirr_rule->num_entries = j;
9108         mirr_rule->id = rule_id;
9109         mirr_rule->dst_vsi_seid = dst_seid;
9110
9111         if (parent)
9112                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9113         else
9114                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9115
9116         pf->nb_mirror_rule++;
9117         return 0;
9118 }
9119
9120 /**
9121  * i40e_mirror_rule_reset
9122  * @dev: pointer to the device
9123  * @sw_id: mirror rule's sw_id
9124  *
9125  * reset a mirror rule.
9126  *
9127  **/
9128 static int
9129 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9130 {
9131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9132         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9133         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9134         uint16_t seid;
9135         int ret;
9136
9137         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9138
9139         seid = pf->main_vsi->veb->seid;
9140
9141         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9142                 if (sw_id == it->index) {
9143                         mirr_rule = it;
9144                         break;
9145                 }
9146         }
9147         if (mirr_rule) {
9148                 ret = i40e_aq_del_mirror_rule(hw, seid,
9149                                 mirr_rule->rule_type,
9150                                 mirr_rule->entries,
9151                                 mirr_rule->num_entries, mirr_rule->id);
9152                 if (ret < 0) {
9153                         PMD_DRV_LOG(ERR,
9154                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9155                                 ret, hw->aq.asq_last_status);
9156                         return -ENOSYS;
9157                 }
9158                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9159                 rte_free(mirr_rule);
9160                 pf->nb_mirror_rule--;
9161         } else {
9162                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9163                 return -ENOENT;
9164         }
9165         return 0;
9166 }
9167
9168 static uint64_t
9169 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9170 {
9171         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9172         uint64_t systim_cycles;
9173
9174         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9175         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9176                         << 32;
9177
9178         return systim_cycles;
9179 }
9180
9181 static uint64_t
9182 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9183 {
9184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9185         uint64_t rx_tstamp;
9186
9187         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9188         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9189                         << 32;
9190
9191         return rx_tstamp;
9192 }
9193
9194 static uint64_t
9195 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9196 {
9197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9198         uint64_t tx_tstamp;
9199
9200         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9201         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9202                         << 32;
9203
9204         return tx_tstamp;
9205 }
9206
9207 static void
9208 i40e_start_timecounters(struct rte_eth_dev *dev)
9209 {
9210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9211         struct i40e_adapter *adapter =
9212                         (struct i40e_adapter *)dev->data->dev_private;
9213         struct rte_eth_link link;
9214         uint32_t tsync_inc_l;
9215         uint32_t tsync_inc_h;
9216
9217         /* Get current link speed. */
9218         memset(&link, 0, sizeof(link));
9219         i40e_dev_link_update(dev, 1);
9220         rte_i40e_dev_atomic_read_link_status(dev, &link);
9221
9222         switch (link.link_speed) {
9223         case ETH_SPEED_NUM_40G:
9224                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9225                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9226                 break;
9227         case ETH_SPEED_NUM_10G:
9228                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9229                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9230                 break;
9231         case ETH_SPEED_NUM_1G:
9232                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9233                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9234                 break;
9235         default:
9236                 tsync_inc_l = 0x0;
9237                 tsync_inc_h = 0x0;
9238         }
9239
9240         /* Set the timesync increment value. */
9241         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9242         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9243
9244         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9245         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9246         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9247
9248         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9249         adapter->systime_tc.cc_shift = 0;
9250         adapter->systime_tc.nsec_mask = 0;
9251
9252         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9253         adapter->rx_tstamp_tc.cc_shift = 0;
9254         adapter->rx_tstamp_tc.nsec_mask = 0;
9255
9256         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9257         adapter->tx_tstamp_tc.cc_shift = 0;
9258         adapter->tx_tstamp_tc.nsec_mask = 0;
9259 }
9260
9261 static int
9262 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9263 {
9264         struct i40e_adapter *adapter =
9265                         (struct i40e_adapter *)dev->data->dev_private;
9266
9267         adapter->systime_tc.nsec += delta;
9268         adapter->rx_tstamp_tc.nsec += delta;
9269         adapter->tx_tstamp_tc.nsec += delta;
9270
9271         return 0;
9272 }
9273
9274 static int
9275 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9276 {
9277         uint64_t ns;
9278         struct i40e_adapter *adapter =
9279                         (struct i40e_adapter *)dev->data->dev_private;
9280
9281         ns = rte_timespec_to_ns(ts);
9282
9283         /* Set the timecounters to a new value. */
9284         adapter->systime_tc.nsec = ns;
9285         adapter->rx_tstamp_tc.nsec = ns;
9286         adapter->tx_tstamp_tc.nsec = ns;
9287
9288         return 0;
9289 }
9290
9291 static int
9292 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9293 {
9294         uint64_t ns, systime_cycles;
9295         struct i40e_adapter *adapter =
9296                         (struct i40e_adapter *)dev->data->dev_private;
9297
9298         systime_cycles = i40e_read_systime_cyclecounter(dev);
9299         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9300         *ts = rte_ns_to_timespec(ns);
9301
9302         return 0;
9303 }
9304
9305 static int
9306 i40e_timesync_enable(struct rte_eth_dev *dev)
9307 {
9308         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9309         uint32_t tsync_ctl_l;
9310         uint32_t tsync_ctl_h;
9311
9312         /* Stop the timesync system time. */
9313         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9314         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9315         /* Reset the timesync system time value. */
9316         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9317         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9318
9319         i40e_start_timecounters(dev);
9320
9321         /* Clear timesync registers. */
9322         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9323         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9324         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9325         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9326         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9327         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9328
9329         /* Enable timestamping of PTP packets. */
9330         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9331         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9332
9333         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9334         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9335         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9336
9337         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9338         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9339
9340         return 0;
9341 }
9342
9343 static int
9344 i40e_timesync_disable(struct rte_eth_dev *dev)
9345 {
9346         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9347         uint32_t tsync_ctl_l;
9348         uint32_t tsync_ctl_h;
9349
9350         /* Disable timestamping of transmitted PTP packets. */
9351         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9352         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9353
9354         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9355         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9356
9357         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9358         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9359
9360         /* Reset the timesync increment value. */
9361         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9362         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9363
9364         return 0;
9365 }
9366
9367 static int
9368 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9369                                 struct timespec *timestamp, uint32_t flags)
9370 {
9371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9372         struct i40e_adapter *adapter =
9373                 (struct i40e_adapter *)dev->data->dev_private;
9374
9375         uint32_t sync_status;
9376         uint32_t index = flags & 0x03;
9377         uint64_t rx_tstamp_cycles;
9378         uint64_t ns;
9379
9380         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9381         if ((sync_status & (1 << index)) == 0)
9382                 return -EINVAL;
9383
9384         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9385         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9386         *timestamp = rte_ns_to_timespec(ns);
9387
9388         return 0;
9389 }
9390
9391 static int
9392 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9393                                 struct timespec *timestamp)
9394 {
9395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9396         struct i40e_adapter *adapter =
9397                 (struct i40e_adapter *)dev->data->dev_private;
9398
9399         uint32_t sync_status;
9400         uint64_t tx_tstamp_cycles;
9401         uint64_t ns;
9402
9403         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9404         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9405                 return -EINVAL;
9406
9407         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9408         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9409         *timestamp = rte_ns_to_timespec(ns);
9410
9411         return 0;
9412 }
9413
9414 /*
9415  * i40e_parse_dcb_configure - parse dcb configure from user
9416  * @dev: the device being configured
9417  * @dcb_cfg: pointer of the result of parse
9418  * @*tc_map: bit map of enabled traffic classes
9419  *
9420  * Returns 0 on success, negative value on failure
9421  */
9422 static int
9423 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9424                          struct i40e_dcbx_config *dcb_cfg,
9425                          uint8_t *tc_map)
9426 {
9427         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9428         uint8_t i, tc_bw, bw_lf;
9429
9430         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9431
9432         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9433         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9434                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9435                 return -EINVAL;
9436         }
9437
9438         /* assume each tc has the same bw */
9439         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9440         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9441                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9442         /* to ensure the sum of tcbw is equal to 100 */
9443         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9444         for (i = 0; i < bw_lf; i++)
9445                 dcb_cfg->etscfg.tcbwtable[i]++;
9446
9447         /* assume each tc has the same Transmission Selection Algorithm */
9448         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9449                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9450
9451         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9452                 dcb_cfg->etscfg.prioritytable[i] =
9453                                 dcb_rx_conf->dcb_tc[i];
9454
9455         /* FW needs one App to configure HW */
9456         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9457         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9458         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9459         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9460
9461         if (dcb_rx_conf->nb_tcs == 0)
9462                 *tc_map = 1; /* tc0 only */
9463         else
9464                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9465
9466         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9467                 dcb_cfg->pfc.willing = 0;
9468                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9469                 dcb_cfg->pfc.pfcenable = *tc_map;
9470         }
9471         return 0;
9472 }
9473
9474
9475 static enum i40e_status_code
9476 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9477                               struct i40e_aqc_vsi_properties_data *info,
9478                               uint8_t enabled_tcmap)
9479 {
9480         enum i40e_status_code ret;
9481         int i, total_tc = 0;
9482         uint16_t qpnum_per_tc, bsf, qp_idx;
9483         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9484         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9485         uint16_t used_queues;
9486
9487         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9488         if (ret != I40E_SUCCESS)
9489                 return ret;
9490
9491         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9492                 if (enabled_tcmap & (1 << i))
9493                         total_tc++;
9494         }
9495         if (total_tc == 0)
9496                 total_tc = 1;
9497         vsi->enabled_tc = enabled_tcmap;
9498
9499         /* different VSI has different queues assigned */
9500         if (vsi->type == I40E_VSI_MAIN)
9501                 used_queues = dev_data->nb_rx_queues -
9502                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9503         else if (vsi->type == I40E_VSI_VMDQ2)
9504                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9505         else {
9506                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9507                 return I40E_ERR_NO_AVAILABLE_VSI;
9508         }
9509
9510         qpnum_per_tc = used_queues / total_tc;
9511         /* Number of queues per enabled TC */
9512         if (qpnum_per_tc == 0) {
9513                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9514                 return I40E_ERR_INVALID_QP_ID;
9515         }
9516         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9517                                 I40E_MAX_Q_PER_TC);
9518         bsf = rte_bsf32(qpnum_per_tc);
9519
9520         /**
9521          * Configure TC and queue mapping parameters, for enabled TC,
9522          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9523          * default queue will serve it.
9524          */
9525         qp_idx = 0;
9526         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9527                 if (vsi->enabled_tc & (1 << i)) {
9528                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9529                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9530                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9531                         qp_idx += qpnum_per_tc;
9532                 } else
9533                         info->tc_mapping[i] = 0;
9534         }
9535
9536         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9537         if (vsi->type == I40E_VSI_SRIOV) {
9538                 info->mapping_flags |=
9539                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9540                 for (i = 0; i < vsi->nb_qps; i++)
9541                         info->queue_mapping[i] =
9542                                 rte_cpu_to_le_16(vsi->base_queue + i);
9543         } else {
9544                 info->mapping_flags |=
9545                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9546                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9547         }
9548         info->valid_sections |=
9549                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9550
9551         return I40E_SUCCESS;
9552 }
9553
9554 /*
9555  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9556  * @veb: VEB to be configured
9557  * @tc_map: enabled TC bitmap
9558  *
9559  * Returns 0 on success, negative value on failure
9560  */
9561 static enum i40e_status_code
9562 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9563 {
9564         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9565         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9566         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9567         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9568         enum i40e_status_code ret = I40E_SUCCESS;
9569         int i;
9570         uint32_t bw_max;
9571
9572         /* Check if enabled_tc is same as existing or new TCs */
9573         if (veb->enabled_tc == tc_map)
9574                 return ret;
9575
9576         /* configure tc bandwidth */
9577         memset(&veb_bw, 0, sizeof(veb_bw));
9578         veb_bw.tc_valid_bits = tc_map;
9579         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9580         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9581                 if (tc_map & BIT_ULL(i))
9582                         veb_bw.tc_bw_share_credits[i] = 1;
9583         }
9584         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9585                                                    &veb_bw, NULL);
9586         if (ret) {
9587                 PMD_INIT_LOG(ERR,
9588                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9589                         hw->aq.asq_last_status);
9590                 return ret;
9591         }
9592
9593         memset(&ets_query, 0, sizeof(ets_query));
9594         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9595                                                    &ets_query, NULL);
9596         if (ret != I40E_SUCCESS) {
9597                 PMD_DRV_LOG(ERR,
9598                         "Failed to get switch_comp ETS configuration %u",
9599                         hw->aq.asq_last_status);
9600                 return ret;
9601         }
9602         memset(&bw_query, 0, sizeof(bw_query));
9603         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9604                                                   &bw_query, NULL);
9605         if (ret != I40E_SUCCESS) {
9606                 PMD_DRV_LOG(ERR,
9607                         "Failed to get switch_comp bandwidth configuration %u",
9608                         hw->aq.asq_last_status);
9609                 return ret;
9610         }
9611
9612         /* store and print out BW info */
9613         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9614         veb->bw_info.bw_max = ets_query.tc_bw_max;
9615         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9616         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9617         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9618                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9619                      I40E_16_BIT_WIDTH);
9620         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9621                 veb->bw_info.bw_ets_share_credits[i] =
9622                                 bw_query.tc_bw_share_credits[i];
9623                 veb->bw_info.bw_ets_credits[i] =
9624                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9625                 /* 4 bits per TC, 4th bit is reserved */
9626                 veb->bw_info.bw_ets_max[i] =
9627                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9628                                   RTE_LEN2MASK(3, uint8_t));
9629                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9630                             veb->bw_info.bw_ets_share_credits[i]);
9631                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9632                             veb->bw_info.bw_ets_credits[i]);
9633                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9634                             veb->bw_info.bw_ets_max[i]);
9635         }
9636
9637         veb->enabled_tc = tc_map;
9638
9639         return ret;
9640 }
9641
9642
9643 /*
9644  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9645  * @vsi: VSI to be configured
9646  * @tc_map: enabled TC bitmap
9647  *
9648  * Returns 0 on success, negative value on failure
9649  */
9650 static enum i40e_status_code
9651 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9652 {
9653         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9654         struct i40e_vsi_context ctxt;
9655         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9656         enum i40e_status_code ret = I40E_SUCCESS;
9657         int i;
9658
9659         /* Check if enabled_tc is same as existing or new TCs */
9660         if (vsi->enabled_tc == tc_map)
9661                 return ret;
9662
9663         /* configure tc bandwidth */
9664         memset(&bw_data, 0, sizeof(bw_data));
9665         bw_data.tc_valid_bits = tc_map;
9666         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9667         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9668                 if (tc_map & BIT_ULL(i))
9669                         bw_data.tc_bw_credits[i] = 1;
9670         }
9671         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9672         if (ret) {
9673                 PMD_INIT_LOG(ERR,
9674                         "AQ command Config VSI BW allocation per TC failed = %d",
9675                         hw->aq.asq_last_status);
9676                 goto out;
9677         }
9678         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9679                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9680
9681         /* Update Queue Pairs Mapping for currently enabled UPs */
9682         ctxt.seid = vsi->seid;
9683         ctxt.pf_num = hw->pf_id;
9684         ctxt.vf_num = 0;
9685         ctxt.uplink_seid = vsi->uplink_seid;
9686         ctxt.info = vsi->info;
9687         i40e_get_cap(hw);
9688         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9689         if (ret)
9690                 goto out;
9691
9692         /* Update the VSI after updating the VSI queue-mapping information */
9693         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9694         if (ret) {
9695                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9696                         hw->aq.asq_last_status);
9697                 goto out;
9698         }
9699         /* update the local VSI info with updated queue map */
9700         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9701                                         sizeof(vsi->info.tc_mapping));
9702         (void)rte_memcpy(&vsi->info.queue_mapping,
9703                         &ctxt.info.queue_mapping,
9704                 sizeof(vsi->info.queue_mapping));
9705         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9706         vsi->info.valid_sections = 0;
9707
9708         /* query and update current VSI BW information */
9709         ret = i40e_vsi_get_bw_config(vsi);
9710         if (ret) {
9711                 PMD_INIT_LOG(ERR,
9712                          "Failed updating vsi bw info, err %s aq_err %s",
9713                          i40e_stat_str(hw, ret),
9714                          i40e_aq_str(hw, hw->aq.asq_last_status));
9715                 goto out;
9716         }
9717
9718         vsi->enabled_tc = tc_map;
9719
9720 out:
9721         return ret;
9722 }
9723
9724 /*
9725  * i40e_dcb_hw_configure - program the dcb setting to hw
9726  * @pf: pf the configuration is taken on
9727  * @new_cfg: new configuration
9728  * @tc_map: enabled TC bitmap
9729  *
9730  * Returns 0 on success, negative value on failure
9731  */
9732 static enum i40e_status_code
9733 i40e_dcb_hw_configure(struct i40e_pf *pf,
9734                       struct i40e_dcbx_config *new_cfg,
9735                       uint8_t tc_map)
9736 {
9737         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9738         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9739         struct i40e_vsi *main_vsi = pf->main_vsi;
9740         struct i40e_vsi_list *vsi_list;
9741         enum i40e_status_code ret;
9742         int i;
9743         uint32_t val;
9744
9745         /* Use the FW API if FW > v4.4*/
9746         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9747               (hw->aq.fw_maj_ver >= 5))) {
9748                 PMD_INIT_LOG(ERR,
9749                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9750                 return I40E_ERR_FIRMWARE_API_VERSION;
9751         }
9752
9753         /* Check if need reconfiguration */
9754         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9755                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9756                 return I40E_SUCCESS;
9757         }
9758
9759         /* Copy the new config to the current config */
9760         *old_cfg = *new_cfg;
9761         old_cfg->etsrec = old_cfg->etscfg;
9762         ret = i40e_set_dcb_config(hw);
9763         if (ret) {
9764                 PMD_INIT_LOG(ERR,
9765                          "Set DCB Config failed, err %s aq_err %s\n",
9766                          i40e_stat_str(hw, ret),
9767                          i40e_aq_str(hw, hw->aq.asq_last_status));
9768                 return ret;
9769         }
9770         /* set receive Arbiter to RR mode and ETS scheme by default */
9771         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9772                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9773                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9774                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9775                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9776                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9777                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9778                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9779                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9780                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9781                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9782                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9783                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9784         }
9785         /* get local mib to check whether it is configured correctly */
9786         /* IEEE mode */
9787         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9788         /* Get Local DCB Config */
9789         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9790                                      &hw->local_dcbx_config);
9791
9792         /* if Veb is created, need to update TC of it at first */
9793         if (main_vsi->veb) {
9794                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9795                 if (ret)
9796                         PMD_INIT_LOG(WARNING,
9797                                  "Failed configuring TC for VEB seid=%d\n",
9798                                  main_vsi->veb->seid);
9799         }
9800         /* Update each VSI */
9801         i40e_vsi_config_tc(main_vsi, tc_map);
9802         if (main_vsi->veb) {
9803                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9804                         /* Beside main VSI and VMDQ VSIs, only enable default
9805                          * TC for other VSIs
9806                          */
9807                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9808                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9809                                                          tc_map);
9810                         else
9811                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9812                                                          I40E_DEFAULT_TCMAP);
9813                         if (ret)
9814                                 PMD_INIT_LOG(WARNING,
9815                                         "Failed configuring TC for VSI seid=%d\n",
9816                                         vsi_list->vsi->seid);
9817                         /* continue */
9818                 }
9819         }
9820         return I40E_SUCCESS;
9821 }
9822
9823 /*
9824  * i40e_dcb_init_configure - initial dcb config
9825  * @dev: device being configured
9826  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9827  *
9828  * Returns 0 on success, negative value on failure
9829  */
9830 static int
9831 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9832 {
9833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9835         int ret = 0;
9836
9837         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9838                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9839                 return -ENOTSUP;
9840         }
9841
9842         /* DCB initialization:
9843          * Update DCB configuration from the Firmware and configure
9844          * LLDP MIB change event.
9845          */
9846         if (sw_dcb == TRUE) {
9847                 ret = i40e_init_dcb(hw);
9848                 /* If lldp agent is stopped, the return value from
9849                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9850                  * adminq status. Otherwise, it should return success.
9851                  */
9852                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9853                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9854                         memset(&hw->local_dcbx_config, 0,
9855                                 sizeof(struct i40e_dcbx_config));
9856                         /* set dcb default configuration */
9857                         hw->local_dcbx_config.etscfg.willing = 0;
9858                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9859                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9860                         hw->local_dcbx_config.etscfg.tsatable[0] =
9861                                                 I40E_IEEE_TSA_ETS;
9862                         hw->local_dcbx_config.etsrec =
9863                                 hw->local_dcbx_config.etscfg;
9864                         hw->local_dcbx_config.pfc.willing = 0;
9865                         hw->local_dcbx_config.pfc.pfccap =
9866                                                 I40E_MAX_TRAFFIC_CLASS;
9867                         /* FW needs one App to configure HW */
9868                         hw->local_dcbx_config.numapps = 1;
9869                         hw->local_dcbx_config.app[0].selector =
9870                                                 I40E_APP_SEL_ETHTYPE;
9871                         hw->local_dcbx_config.app[0].priority = 3;
9872                         hw->local_dcbx_config.app[0].protocolid =
9873                                                 I40E_APP_PROTOID_FCOE;
9874                         ret = i40e_set_dcb_config(hw);
9875                         if (ret) {
9876                                 PMD_INIT_LOG(ERR,
9877                                         "default dcb config fails. err = %d, aq_err = %d.",
9878                                         ret, hw->aq.asq_last_status);
9879                                 return -ENOSYS;
9880                         }
9881                 } else {
9882                         PMD_INIT_LOG(ERR,
9883                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9884                                 ret, hw->aq.asq_last_status);
9885                         return -ENOTSUP;
9886                 }
9887         } else {
9888                 ret = i40e_aq_start_lldp(hw, NULL);
9889                 if (ret != I40E_SUCCESS)
9890                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9891
9892                 ret = i40e_init_dcb(hw);
9893                 if (!ret) {
9894                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9895                                 PMD_INIT_LOG(ERR,
9896                                         "HW doesn't support DCBX offload.");
9897                                 return -ENOTSUP;
9898                         }
9899                 } else {
9900                         PMD_INIT_LOG(ERR,
9901                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9902                                 ret, hw->aq.asq_last_status);
9903                         return -ENOTSUP;
9904                 }
9905         }
9906         return 0;
9907 }
9908
9909 /*
9910  * i40e_dcb_setup - setup dcb related config
9911  * @dev: device being configured
9912  *
9913  * Returns 0 on success, negative value on failure
9914  */
9915 static int
9916 i40e_dcb_setup(struct rte_eth_dev *dev)
9917 {
9918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9919         struct i40e_dcbx_config dcb_cfg;
9920         uint8_t tc_map = 0;
9921         int ret = 0;
9922
9923         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9924                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9925                 return -ENOTSUP;
9926         }
9927
9928         if (pf->vf_num != 0)
9929                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9930
9931         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9932         if (ret) {
9933                 PMD_INIT_LOG(ERR, "invalid dcb config");
9934                 return -EINVAL;
9935         }
9936         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9937         if (ret) {
9938                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9939                 return -ENOSYS;
9940         }
9941
9942         return 0;
9943 }
9944
9945 static int
9946 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9947                       struct rte_eth_dcb_info *dcb_info)
9948 {
9949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9951         struct i40e_vsi *vsi = pf->main_vsi;
9952         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9953         uint16_t bsf, tc_mapping;
9954         int i, j = 0;
9955
9956         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9957                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9958         else
9959                 dcb_info->nb_tcs = 1;
9960         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9961                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9962         for (i = 0; i < dcb_info->nb_tcs; i++)
9963                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9964
9965         /* get queue mapping if vmdq is disabled */
9966         if (!pf->nb_cfg_vmdq_vsi) {
9967                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9968                         if (!(vsi->enabled_tc & (1 << i)))
9969                                 continue;
9970                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9971                         dcb_info->tc_queue.tc_rxq[j][i].base =
9972                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9973                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9974                         dcb_info->tc_queue.tc_txq[j][i].base =
9975                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9976                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9977                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9978                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9979                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9980                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9981                 }
9982                 return 0;
9983         }
9984
9985         /* get queue mapping if vmdq is enabled */
9986         do {
9987                 vsi = pf->vmdq[j].vsi;
9988                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9989                         if (!(vsi->enabled_tc & (1 << i)))
9990                                 continue;
9991                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9992                         dcb_info->tc_queue.tc_rxq[j][i].base =
9993                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9994                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9995                         dcb_info->tc_queue.tc_txq[j][i].base =
9996                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9997                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9998                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9999                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10000                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10001                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10002                 }
10003                 j++;
10004         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10005         return 0;
10006 }
10007
10008 static int
10009 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10010 {
10011         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10012         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10014         uint16_t interval =
10015                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10016         uint16_t msix_intr;
10017
10018         msix_intr = intr_handle->intr_vec[queue_id];
10019         if (msix_intr == I40E_MISC_VEC_ID)
10020                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10021                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10022                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10023                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10024                                (interval <<
10025                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10026         else
10027                 I40E_WRITE_REG(hw,
10028                                I40E_PFINT_DYN_CTLN(msix_intr -
10029                                                    I40E_RX_VEC_START),
10030                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10031                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10032                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10033                                (interval <<
10034                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10035
10036         I40E_WRITE_FLUSH(hw);
10037         rte_intr_enable(&pci_dev->intr_handle);
10038
10039         return 0;
10040 }
10041
10042 static int
10043 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10044 {
10045         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10046         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10048         uint16_t msix_intr;
10049
10050         msix_intr = intr_handle->intr_vec[queue_id];
10051         if (msix_intr == I40E_MISC_VEC_ID)
10052                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10053         else
10054                 I40E_WRITE_REG(hw,
10055                                I40E_PFINT_DYN_CTLN(msix_intr -
10056                                                    I40E_RX_VEC_START),
10057                                0);
10058         I40E_WRITE_FLUSH(hw);
10059
10060         return 0;
10061 }
10062
10063 static int i40e_get_regs(struct rte_eth_dev *dev,
10064                          struct rte_dev_reg_info *regs)
10065 {
10066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10067         uint32_t *ptr_data = regs->data;
10068         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10069         const struct i40e_reg_info *reg_info;
10070
10071         if (ptr_data == NULL) {
10072                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10073                 regs->width = sizeof(uint32_t);
10074                 return 0;
10075         }
10076
10077         /* The first few registers have to be read using AQ operations */
10078         reg_idx = 0;
10079         while (i40e_regs_adminq[reg_idx].name) {
10080                 reg_info = &i40e_regs_adminq[reg_idx++];
10081                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10082                         for (arr_idx2 = 0;
10083                                         arr_idx2 <= reg_info->count2;
10084                                         arr_idx2++) {
10085                                 reg_offset = arr_idx * reg_info->stride1 +
10086                                         arr_idx2 * reg_info->stride2;
10087                                 reg_offset += reg_info->base_addr;
10088                                 ptr_data[reg_offset >> 2] =
10089                                         i40e_read_rx_ctl(hw, reg_offset);
10090                         }
10091         }
10092
10093         /* The remaining registers can be read using primitives */
10094         reg_idx = 0;
10095         while (i40e_regs_others[reg_idx].name) {
10096                 reg_info = &i40e_regs_others[reg_idx++];
10097                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10098                         for (arr_idx2 = 0;
10099                                         arr_idx2 <= reg_info->count2;
10100                                         arr_idx2++) {
10101                                 reg_offset = arr_idx * reg_info->stride1 +
10102                                         arr_idx2 * reg_info->stride2;
10103                                 reg_offset += reg_info->base_addr;
10104                                 ptr_data[reg_offset >> 2] =
10105                                         I40E_READ_REG(hw, reg_offset);
10106                         }
10107         }
10108
10109         return 0;
10110 }
10111
10112 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10113 {
10114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10115
10116         /* Convert word count to byte count */
10117         return hw->nvm.sr_size << 1;
10118 }
10119
10120 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10121                            struct rte_dev_eeprom_info *eeprom)
10122 {
10123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10124         uint16_t *data = eeprom->data;
10125         uint16_t offset, length, cnt_words;
10126         int ret_code;
10127
10128         offset = eeprom->offset >> 1;
10129         length = eeprom->length >> 1;
10130         cnt_words = length;
10131
10132         if (offset > hw->nvm.sr_size ||
10133                 offset + length > hw->nvm.sr_size) {
10134                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10135                 return -EINVAL;
10136         }
10137
10138         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10139
10140         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10141         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10142                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10143                 return -EIO;
10144         }
10145
10146         return 0;
10147 }
10148
10149 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10150                                       struct ether_addr *mac_addr)
10151 {
10152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10153
10154         if (!is_valid_assigned_ether_addr(mac_addr)) {
10155                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10156                 return;
10157         }
10158
10159         /* Flags: 0x3 updates port address */
10160         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10161 }
10162
10163 static int
10164 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10165 {
10166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10167         struct rte_eth_dev_data *dev_data = pf->dev_data;
10168         uint32_t frame_size = mtu + ETHER_HDR_LEN
10169                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10170         int ret = 0;
10171
10172         /* check if mtu is within the allowed range */
10173         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10174                 return -EINVAL;
10175
10176         /* mtu setting is forbidden if port is start */
10177         if (dev_data->dev_started) {
10178                 PMD_DRV_LOG(ERR,
10179                             "port %d must be stopped before configuration\n",
10180                             dev_data->port_id);
10181                 return -EBUSY;
10182         }
10183
10184         if (frame_size > ETHER_MAX_LEN)
10185                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10186         else
10187                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10188
10189         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10190
10191         return ret;
10192 }
10193
10194 /* Restore ethertype filter */
10195 static void
10196 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10197 {
10198         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10199         struct i40e_ethertype_filter_list
10200                 *ethertype_list = &pf->ethertype.ethertype_list;
10201         struct i40e_ethertype_filter *f;
10202         struct i40e_control_filter_stats stats;
10203         uint16_t flags;
10204
10205         TAILQ_FOREACH(f, ethertype_list, rules) {
10206                 flags = 0;
10207                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10208                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10209                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10210                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10211                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10212
10213                 memset(&stats, 0, sizeof(stats));
10214                 i40e_aq_add_rem_control_packet_filter(hw,
10215                                             f->input.mac_addr.addr_bytes,
10216                                             f->input.ether_type,
10217                                             flags, pf->main_vsi->seid,
10218                                             f->queue, 1, &stats, NULL);
10219         }
10220         PMD_DRV_LOG(INFO, "Ethertype filter:"
10221                     " mac_etype_used = %u, etype_used = %u,"
10222                     " mac_etype_free = %u, etype_free = %u\n",
10223                     stats.mac_etype_used, stats.etype_used,
10224                     stats.mac_etype_free, stats.etype_free);
10225 }
10226
10227 /* Restore tunnel filter */
10228 static void
10229 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10230 {
10231         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10232         struct i40e_vsi *vsi = pf->main_vsi;
10233         struct i40e_tunnel_filter_list
10234                 *tunnel_list = &pf->tunnel.tunnel_list;
10235         struct i40e_tunnel_filter *f;
10236         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10237
10238         TAILQ_FOREACH(f, tunnel_list, rules) {
10239                 memset(&cld_filter, 0, sizeof(cld_filter));
10240                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10241                 cld_filter.queue_number = f->queue;
10242                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10243         }
10244 }
10245
10246 static void
10247 i40e_filter_restore(struct i40e_pf *pf)
10248 {
10249         i40e_ethertype_filter_restore(pf);
10250         i40e_tunnel_filter_restore(pf);
10251         i40e_fdir_filter_restore(pf);
10252 }
10253
10254 static int
10255 is_i40e_pmd(const char *driver_name)
10256 {
10257         if (!strstr(driver_name, "i40e"))
10258                 return -ENOTSUP;
10259
10260         if (strstr(driver_name, "i40e_vf"))
10261                 return -ENOTSUP;
10262
10263         return 0;
10264 }
10265
10266 int
10267 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10268 {
10269         struct rte_eth_dev *dev;
10270         struct i40e_pf *pf;
10271
10272         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10273
10274         dev = &rte_eth_devices[port];
10275
10276         if (is_i40e_pmd(dev->data->drv_name))
10277                 return -ENOTSUP;
10278
10279         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10280
10281         if (vf >= pf->vf_num || !pf->vfs) {
10282                 PMD_DRV_LOG(ERR, "Invalid argument.");
10283                 return -EINVAL;
10284         }
10285
10286         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10287
10288         return 0;
10289 }
10290
10291 int
10292 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10293 {
10294         struct rte_eth_dev *dev;
10295         struct i40e_pf *pf;
10296         struct i40e_vsi *vsi;
10297         struct i40e_hw *hw;
10298         struct i40e_vsi_context ctxt;
10299         int ret;
10300
10301         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10302
10303         dev = &rte_eth_devices[port];
10304
10305         if (is_i40e_pmd(dev->data->drv_name))
10306                 return -ENOTSUP;
10307
10308         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10309
10310         if (vf_id >= pf->vf_num || !pf->vfs) {
10311                 PMD_DRV_LOG(ERR, "Invalid argument.");
10312                 return -EINVAL;
10313         }
10314
10315         vsi = pf->vfs[vf_id].vsi;
10316         if (!vsi) {
10317                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10318                 return -EINVAL;
10319         }
10320
10321         /* Check if it has been already on or off */
10322         if (vsi->info.valid_sections &
10323                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10324                 if (on) {
10325                         if ((vsi->info.sec_flags &
10326                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10327                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10328                                 return 0; /* already on */
10329                 } else {
10330                         if ((vsi->info.sec_flags &
10331                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10332                                 return 0; /* already off */
10333                 }
10334         }
10335
10336         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10337         if (on)
10338                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10339         else
10340                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10341
10342         memset(&ctxt, 0, sizeof(ctxt));
10343         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10344         ctxt.seid = vsi->seid;
10345
10346         hw = I40E_VSI_TO_HW(vsi);
10347         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10348         if (ret != I40E_SUCCESS) {
10349                 ret = -ENOTSUP;
10350                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10351         }
10352
10353         return ret;
10354 }
10355
10356 static int
10357 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10358 {
10359         uint32_t j, k;
10360         uint16_t vlan_id;
10361         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10362         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10363         int ret;
10364
10365         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10366                 if (!vsi->vfta[j])
10367                         continue;
10368
10369                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10370                         if (!(vsi->vfta[j] & (1 << k)))
10371                                 continue;
10372
10373                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10374                         if (!vlan_id)
10375                                 continue;
10376
10377                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10378                         if (add)
10379                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10380                                                        &vlan_data, 1, NULL);
10381                         else
10382                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10383                                                           &vlan_data, 1, NULL);
10384                         if (ret != I40E_SUCCESS) {
10385                                 PMD_DRV_LOG(ERR,
10386                                             "Failed to add/rm vlan filter");
10387                                 return ret;
10388                         }
10389                 }
10390         }
10391
10392         return I40E_SUCCESS;
10393 }
10394
10395 int
10396 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10397 {
10398         struct rte_eth_dev *dev;
10399         struct i40e_pf *pf;
10400         struct i40e_vsi *vsi;
10401         struct i40e_hw *hw;
10402         struct i40e_vsi_context ctxt;
10403         int ret;
10404
10405         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10406
10407         dev = &rte_eth_devices[port];
10408
10409         if (is_i40e_pmd(dev->data->drv_name))
10410                 return -ENOTSUP;
10411
10412         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10413
10414         if (vf_id >= pf->vf_num || !pf->vfs) {
10415                 PMD_DRV_LOG(ERR, "Invalid argument.");
10416                 return -EINVAL;
10417         }
10418
10419         vsi = pf->vfs[vf_id].vsi;
10420         if (!vsi) {
10421                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10422                 return -EINVAL;
10423         }
10424
10425         /* Check if it has been already on or off */
10426         if (vsi->vlan_anti_spoof_on == on)
10427                 return 0; /* already on or off */
10428
10429         vsi->vlan_anti_spoof_on = on;
10430         ret = i40e_add_rm_all_vlan_filter(vsi, on);
10431         if (ret) {
10432                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10433                 return -ENOTSUP;
10434         }
10435
10436         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10437         if (on)
10438                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10439         else
10440                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10441
10442         memset(&ctxt, 0, sizeof(ctxt));
10443         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10444         ctxt.seid = vsi->seid;
10445
10446         hw = I40E_VSI_TO_HW(vsi);
10447         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10448         if (ret != I40E_SUCCESS) {
10449                 ret = -ENOTSUP;
10450                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10451         }
10452
10453         return ret;
10454 }
10455
10456 static int
10457 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10458 {
10459         struct i40e_mac_filter *f;
10460         struct i40e_macvlan_filter *mv_f;
10461         int i, vlan_num;
10462         enum rte_mac_filter_type filter_type;
10463         int ret = I40E_SUCCESS;
10464         void *temp;
10465
10466         /* remove all the MACs */
10467         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10468                 vlan_num = vsi->vlan_num;
10469                 filter_type = f->mac_info.filter_type;
10470                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10471                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10472                         if (vlan_num == 0) {
10473                                 PMD_DRV_LOG(ERR,
10474                                             "VLAN number shouldn't be 0\n");
10475                                 return I40E_ERR_PARAM;
10476                         }
10477                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10478                            filter_type == RTE_MAC_HASH_MATCH)
10479                         vlan_num = 1;
10480
10481                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10482                 if (!mv_f) {
10483                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10484                         return I40E_ERR_NO_MEMORY;
10485                 }
10486
10487                 for (i = 0; i < vlan_num; i++) {
10488                         mv_f[i].filter_type = filter_type;
10489                         (void)rte_memcpy(&mv_f[i].macaddr,
10490                                          &f->mac_info.mac_addr,
10491                                          ETH_ADDR_LEN);
10492                 }
10493                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10494                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10495                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10496                                                          &f->mac_info.mac_addr);
10497                         if (ret != I40E_SUCCESS) {
10498                                 rte_free(mv_f);
10499                                 return ret;
10500                         }
10501                 }
10502
10503                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10504                 if (ret != I40E_SUCCESS) {
10505                         rte_free(mv_f);
10506                         return ret;
10507                 }
10508
10509                 rte_free(mv_f);
10510                 ret = I40E_SUCCESS;
10511         }
10512
10513         return ret;
10514 }
10515
10516 static int
10517 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10518 {
10519         struct i40e_mac_filter *f;
10520         struct i40e_macvlan_filter *mv_f;
10521         int i, vlan_num = 0;
10522         int ret = I40E_SUCCESS;
10523         void *temp;
10524
10525         /* restore all the MACs */
10526         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10527                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10528                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10529                         /**
10530                          * If vlan_num is 0, that's the first time to add mac,
10531                          * set mask for vlan_id 0.
10532                          */
10533                         if (vsi->vlan_num == 0) {
10534                                 i40e_set_vlan_filter(vsi, 0, 1);
10535                                 vsi->vlan_num = 1;
10536                         }
10537                         vlan_num = vsi->vlan_num;
10538                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10539                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10540                         vlan_num = 1;
10541
10542                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10543                 if (!mv_f) {
10544                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10545                         return I40E_ERR_NO_MEMORY;
10546                 }
10547
10548                 for (i = 0; i < vlan_num; i++) {
10549                         mv_f[i].filter_type = f->mac_info.filter_type;
10550                         (void)rte_memcpy(&mv_f[i].macaddr,
10551                                          &f->mac_info.mac_addr,
10552                                          ETH_ADDR_LEN);
10553                 }
10554
10555                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10556                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10557                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10558                                                          &f->mac_info.mac_addr);
10559                         if (ret != I40E_SUCCESS) {
10560                                 rte_free(mv_f);
10561                                 return ret;
10562                         }
10563                 }
10564
10565                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10566                 if (ret != I40E_SUCCESS) {
10567                         rte_free(mv_f);
10568                         return ret;
10569                 }
10570
10571                 rte_free(mv_f);
10572                 ret = I40E_SUCCESS;
10573         }
10574
10575         return ret;
10576 }
10577
10578 static int
10579 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10580 {
10581         struct i40e_vsi_context ctxt;
10582         struct i40e_hw *hw;
10583         int ret;
10584
10585         if (!vsi)
10586                 return -EINVAL;
10587
10588         hw = I40E_VSI_TO_HW(vsi);
10589
10590         /* Use the FW API if FW >= v5.0 */
10591         if (hw->aq.fw_maj_ver < 5) {
10592                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10593                 return -ENOTSUP;
10594         }
10595
10596         /* Check if it has been already on or off */
10597         if (vsi->info.valid_sections &
10598                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10599                 if (on) {
10600                         if ((vsi->info.switch_id &
10601                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10602                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10603                                 return 0; /* already on */
10604                 } else {
10605                         if ((vsi->info.switch_id &
10606                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10607                                 return 0; /* already off */
10608                 }
10609         }
10610
10611         /* remove all the MAC and VLAN first */
10612         ret = i40e_vsi_rm_mac_filter(vsi);
10613         if (ret) {
10614                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10615                 return ret;
10616         }
10617         if (vsi->vlan_anti_spoof_on) {
10618                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10619                 if (ret) {
10620                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10621                         return ret;
10622                 }
10623         }
10624
10625         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10626         if (on)
10627                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10628         else
10629                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10630
10631         memset(&ctxt, 0, sizeof(ctxt));
10632         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10633         ctxt.seid = vsi->seid;
10634
10635         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10636         if (ret != I40E_SUCCESS) {
10637                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10638                 return ret;
10639         }
10640
10641         /* add all the MAC and VLAN back */
10642         ret = i40e_vsi_restore_mac_filter(vsi);
10643         if (ret)
10644                 return ret;
10645         if (vsi->vlan_anti_spoof_on) {
10646                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10647                 if (ret)
10648                         return ret;
10649         }
10650
10651         return ret;
10652 }
10653
10654 int
10655 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10656 {
10657         struct rte_eth_dev *dev;
10658         struct i40e_pf *pf;
10659         struct i40e_pf_vf *vf;
10660         struct i40e_vsi *vsi;
10661         uint16_t vf_id;
10662         int ret;
10663
10664         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10665
10666         dev = &rte_eth_devices[port];
10667
10668         if (is_i40e_pmd(dev->data->drv_name))
10669                 return -ENOTSUP;
10670
10671         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10672
10673         /* setup PF TX loopback */
10674         vsi = pf->main_vsi;
10675         ret = i40e_vsi_set_tx_loopback(vsi, on);
10676         if (ret)
10677                 return -ENOTSUP;
10678
10679         /* setup TX loopback for all the VFs */
10680         if (!pf->vfs) {
10681                 /* if no VF, do nothing. */
10682                 return 0;
10683         }
10684
10685         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10686                 vf = &pf->vfs[vf_id];
10687                 vsi = vf->vsi;
10688
10689                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10690                 if (ret)
10691                         return -ENOTSUP;
10692         }
10693
10694         return ret;
10695 }
10696
10697 int
10698 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10699 {
10700         struct rte_eth_dev *dev;
10701         struct i40e_pf *pf;
10702         struct i40e_vsi *vsi;
10703         struct i40e_hw *hw;
10704         int ret;
10705
10706         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10707
10708         dev = &rte_eth_devices[port];
10709
10710         if (is_i40e_pmd(dev->data->drv_name))
10711                 return -ENOTSUP;
10712
10713         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10714
10715         if (vf_id >= pf->vf_num || !pf->vfs) {
10716                 PMD_DRV_LOG(ERR, "Invalid argument.");
10717                 return -EINVAL;
10718         }
10719
10720         vsi = pf->vfs[vf_id].vsi;
10721         if (!vsi) {
10722                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10723                 return -EINVAL;
10724         }
10725
10726         hw = I40E_VSI_TO_HW(vsi);
10727
10728         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10729                                                   on, NULL, true);
10730         if (ret != I40E_SUCCESS) {
10731                 ret = -ENOTSUP;
10732                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10733         }
10734
10735         return ret;
10736 }
10737
10738 int
10739 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10740 {
10741         struct rte_eth_dev *dev;
10742         struct i40e_pf *pf;
10743         struct i40e_vsi *vsi;
10744         struct i40e_hw *hw;
10745         int ret;
10746
10747         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10748
10749         dev = &rte_eth_devices[port];
10750
10751         if (is_i40e_pmd(dev->data->drv_name))
10752                 return -ENOTSUP;
10753
10754         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10755
10756         if (vf_id >= pf->vf_num || !pf->vfs) {
10757                 PMD_DRV_LOG(ERR, "Invalid argument.");
10758                 return -EINVAL;
10759         }
10760
10761         vsi = pf->vfs[vf_id].vsi;
10762         if (!vsi) {
10763                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10764                 return -EINVAL;
10765         }
10766
10767         hw = I40E_VSI_TO_HW(vsi);
10768
10769         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10770                                                     on, NULL);
10771         if (ret != I40E_SUCCESS) {
10772                 ret = -ENOTSUP;
10773                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10774         }
10775
10776         return ret;
10777 }