drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "base/i40e_dcb.h"
  60 #include "i40e_ethdev.h"
  61 #include "i40e_rxtx.h"
  62 #include "i40e_pf.h"
  63
  64 /* Maximun number of MAC addresses */
  65 #define I40E_NUM_MACADDR_MAX       64
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 /* Default queue interrupt throttling time in microseconds */
  79 #define I40E_ITR_INDEX_DEFAULT          0
  80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  81 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA  0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 143 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 144 static int i40e_dev_configure(struct rte_eth_dev *dev);
 145 static int i40e_dev_start(struct rte_eth_dev *dev);
 146 static void i40e_dev_stop(struct rte_eth_dev *dev);
 147 static void i40e_dev_close(struct rte_eth_dev *dev);
 148 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 149 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 150 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 151 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 152 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 153 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 154 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 155                                struct rte_eth_stats *stats);
 156 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 157 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 158                                             uint16_t queue_id,
 159                                             uint8_t stat_idx,
 160                                             uint8_t is_rx);
 161 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 162                               struct rte_eth_dev_info *dev_info);
 163 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 164                                 uint16_t vlan_id,
 165                                 int on);
 166 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 167 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 168 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 169                                       uint16_t queue,
 170                                       int on);
 171 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 172 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 173 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 174 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 175                               struct rte_eth_fc_conf *fc_conf);
 176 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 177                               struct rte_eth_fc_conf *fc_conf);
 178 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 179                                        struct rte_eth_pfc_conf *pfc_conf);
 180 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 181                           struct ether_addr *mac_addr,
 182                           uint32_t index,
 183                           uint32_t pool);
 184 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 185 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 187                                     uint16_t reta_size);
 188 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 190                                    uint16_t reta_size);
 191
 192 static int i40e_get_cap(struct i40e_hw *hw);
 193 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 194 static int i40e_pf_setup(struct i40e_pf *pf);
 195 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 196 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 197 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 198 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 199 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 200                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 201 static void i40e_stat_update_48(struct i40e_hw *hw,
 202                                uint32_t hireg,
 203                                uint32_t loreg,
 204                                bool offset_loaded,
 205                                uint64_t *offset,
 206                                uint64_t *stat);
 207 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 208 static void i40e_dev_interrupt_handler(
 209                 __rte_unused struct rte_intr_handle *handle, void *param);
 210 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 211                                 uint32_t base, uint32_t num);
 212 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 213 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 214                         uint32_t base);
 215 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 216                         uint16_t num);
 217 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 218 static int i40e_veb_release(struct i40e_veb *veb);
 219 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 220                                                 struct i40e_vsi *vsi);
 221 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 222 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 223 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 224                                              struct i40e_macvlan_filter *mv_f,
 225                                              int num,
 226                                              struct ether_addr *addr);
 227 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 228                                              struct i40e_macvlan_filter *mv_f,
 229                                              int num,
 230                                              uint16_t vlan);
 231 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 232 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 233                                     struct rte_eth_rss_conf *rss_conf);
 234 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 235                                       struct rte_eth_rss_conf *rss_conf);
 236 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 237                                 struct rte_eth_udp_tunnel *udp_tunnel);
 238 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 239                                 struct rte_eth_udp_tunnel *udp_tunnel);
 240 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 241                         struct rte_eth_ethertype_filter *filter,
 242                         bool add);
 243 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 244                                 enum rte_filter_op filter_op,
 245                                 void *arg);
 246 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 247                                 enum rte_filter_type filter_type,
 248                                 enum rte_filter_op filter_op,
 249                                 void *arg);
 250 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 251                                   struct rte_eth_dcb_info *dcb_info);
 252 static void i40e_configure_registers(struct i40e_hw *hw);
 253 static void i40e_hw_init(struct i40e_hw *hw);
 254 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 255 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 256                         struct rte_eth_mirror_conf *mirror_conf,
 257                         uint8_t sw_id, uint8_t on);
 258 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 259
 260 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 261 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 262 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 263                                            struct timespec *timestamp,
 264                                            uint32_t flags);
 265 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 266                                            struct timespec *timestamp);
 267
 268 static const struct rte_pci_id pci_id_i40e_map[] = {
 269 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 270 #include "rte_pci_dev_ids.h"
 271 { .vendor_id = 0, /* sentinel */ },
 272 };
 273
 274 static const struct eth_dev_ops i40e_eth_dev_ops = {
 275         .dev_configure                = i40e_dev_configure,
 276         .dev_start                    = i40e_dev_start,
 277         .dev_stop                     = i40e_dev_stop,
 278         .dev_close                    = i40e_dev_close,
 279         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 280         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 281         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 282         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 283         .dev_set_link_up              = i40e_dev_set_link_up,
 284         .dev_set_link_down            = i40e_dev_set_link_down,
 285         .link_update                  = i40e_dev_link_update,
 286         .stats_get                    = i40e_dev_stats_get,
 287         .stats_reset                  = i40e_dev_stats_reset,
 288         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 289         .dev_infos_get                = i40e_dev_info_get,
 290         .vlan_filter_set              = i40e_vlan_filter_set,
 291         .vlan_tpid_set                = i40e_vlan_tpid_set,
 292         .vlan_offload_set             = i40e_vlan_offload_set,
 293         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 294         .vlan_pvid_set                = i40e_vlan_pvid_set,
 295         .rx_queue_start               = i40e_dev_rx_queue_start,
 296         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 297         .tx_queue_start               = i40e_dev_tx_queue_start,
 298         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 299         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 300         .rx_queue_release             = i40e_dev_rx_queue_release,
 301         .rx_queue_count               = i40e_dev_rx_queue_count,
 302         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 303         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 304         .tx_queue_release             = i40e_dev_tx_queue_release,
 305         .dev_led_on                   = i40e_dev_led_on,
 306         .dev_led_off                  = i40e_dev_led_off,
 307         .flow_ctrl_get                = i40e_flow_ctrl_get,
 308         .flow_ctrl_set                = i40e_flow_ctrl_set,
 309         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 310         .mac_addr_add                 = i40e_macaddr_add,
 311         .mac_addr_remove              = i40e_macaddr_remove,
 312         .reta_update                  = i40e_dev_rss_reta_update,
 313         .reta_query                   = i40e_dev_rss_reta_query,
 314         .rss_hash_update              = i40e_dev_rss_hash_update,
 315         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 316         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 317         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 318         .filter_ctrl                  = i40e_dev_filter_ctrl,
 319         .rxq_info_get                 = i40e_rxq_info_get,
 320         .txq_info_get                 = i40e_txq_info_get,
 321         .mirror_rule_set              = i40e_mirror_rule_set,
 322         .mirror_rule_reset            = i40e_mirror_rule_reset,
 323         .timesync_enable              = i40e_timesync_enable,
 324         .timesync_disable             = i40e_timesync_disable,
 325         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 326         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 327         .get_dcb_info                 = i40e_dev_get_dcb_info,
 328 };
 329
 330 static struct eth_driver rte_i40e_pmd = {
 331         .pci_drv = {
 332                 .name = "rte_i40e_pmd",
 333                 .id_table = pci_id_i40e_map,
 334                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 335                         RTE_PCI_DRV_DETACHABLE,
 336         },
 337         .eth_dev_init = eth_i40e_dev_init,
 338         .eth_dev_uninit = eth_i40e_dev_uninit,
 339         .dev_private_size = sizeof(struct i40e_adapter),
 340 };
 341
 342 static inline int
 343 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 344                                      struct rte_eth_link *link)
 345 {
 346         struct rte_eth_link *dst = link;
 347         struct rte_eth_link *src = &(dev->data->dev_link);
 348
 349         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 350                                         *(uint64_t *)src) == 0)
 351                 return -1;
 352
 353         return 0;
 354 }
 355
 356 static inline int
 357 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 358                                       struct rte_eth_link *link)
 359 {
 360         struct rte_eth_link *dst = &(dev->data->dev_link);
 361         struct rte_eth_link *src = link;
 362
 363         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 364                                         *(uint64_t *)src) == 0)
 365                 return -1;
 366
 367         return 0;
 368 }
 369
 370 /*
 371  * Driver initialization routine.
 372  * Invoked once at EAL init time.
 373  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 374  */
 375 static int
 376 rte_i40e_pmd_init(const char *name __rte_unused,
 377                   const char *params __rte_unused)
 378 {
 379         PMD_INIT_FUNC_TRACE();
 380         rte_eth_driver_register(&rte_i40e_pmd);
 381
 382         return 0;
 383 }
 384
 385 static struct rte_driver rte_i40e_driver = {
 386         .type = PMD_PDEV,
 387         .init = rte_i40e_pmd_init,
 388 };
 389
 390 PMD_REGISTER_DRIVER(rte_i40e_driver);
 391
 392 /*
 393  * Initialize registers for flexible payload, which should be set by NVM.
 394  * This should be removed from code once it is fixed in NVM.
 395  */
 396 #ifndef I40E_GLQF_ORT
 397 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 398 #endif
 399 #ifndef I40E_GLQF_PIT
 400 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 401 #endif
 402
 403 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 404 {
 405         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 406         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 407         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 408         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 409         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 410         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 411         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 412         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 413         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 414         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 415
 416         /* GLQF_PIT Registers */
 417         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 418         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 419 }
 420
 421 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 422
 423 /*
 424  * Add a ethertype filter to drop all flow control frames transmitted
 425  * from VSIs.
 426 */
 427 static void
 428 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 429 {
 430         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 431         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 432                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 433                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 434         int ret;
 435
 436         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 437                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 438                                 pf->main_vsi_seid, 0,
 439                                 TRUE, NULL, NULL);
 440         if (ret)
 441                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 442                                   " frames from VSIs.");
 443 }
 444
 445 static int
 446 eth_i40e_dev_init(struct rte_eth_dev *dev)
 447 {
 448         struct rte_pci_device *pci_dev;
 449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 451         struct i40e_vsi *vsi;
 452         int ret;
 453         uint32_t len;
 454         uint8_t aq_fail = 0;
 455
 456         PMD_INIT_FUNC_TRACE();
 457
 458         dev->dev_ops = &i40e_eth_dev_ops;
 459         dev->rx_pkt_burst = i40e_recv_pkts;
 460         dev->tx_pkt_burst = i40e_xmit_pkts;
 461
 462         /* for secondary processes, we don't initialise any further as primary
 463          * has already done this work. Only check we don't need a different
 464          * RX function */
 465         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 466                 i40e_set_rx_function(dev);
 467                 i40e_set_tx_function(dev);
 468                 return 0;
 469         }
 470         pci_dev = dev->pci_dev;
 471         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 472         pf->adapter->eth_dev = dev;
 473         pf->dev_data = dev->data;
 474
 475         hw->back = I40E_PF_TO_ADAPTER(pf);
 476         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 477         if (!hw->hw_addr) {
 478                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 479                              "as address is NULL");
 480                 return -ENODEV;
 481         }
 482
 483         hw->vendor_id = pci_dev->id.vendor_id;
 484         hw->device_id = pci_dev->id.device_id;
 485         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 486         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 487         hw->bus.device = pci_dev->addr.devid;
 488         hw->bus.func = pci_dev->addr.function;
 489         hw->adapter_stopped = 0;
 490
 491         /* Make sure all is clean before doing PF reset */
 492         i40e_clear_hw(hw);
 493
 494         /* Initialize the hardware */
 495         i40e_hw_init(hw);
 496
 497         /* Reset here to make sure all is clean for each PF */
 498         ret = i40e_pf_reset(hw);
 499         if (ret) {
 500                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 501                 return ret;
 502         }
 503
 504         /* Initialize the shared code (base driver) */
 505         ret = i40e_init_shared_code(hw);
 506         if (ret) {
 507                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 508                 return ret;
 509         }
 510
 511         /*
 512          * To work around the NVM issue,initialize registers
 513          * for flexible payload by software.
 514          * It should be removed once issues are fixed in NVM.
 515          */
 516         i40e_flex_payload_reg_init(hw);
 517
 518         /* Initialize the parameters for adminq */
 519         i40e_init_adminq_parameter(hw);
 520         ret = i40e_init_adminq(hw);
 521         if (ret != I40E_SUCCESS) {
 522                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 523                 return -EIO;
 524         }
 525         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 526                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 527                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 528                      ((hw->nvm.version >> 12) & 0xf),
 529                      ((hw->nvm.version >> 4) & 0xff),
 530                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 531
 532         /* Clear PXE mode */
 533         i40e_clear_pxe_mode(hw);
 534
 535         /*
 536          * On X710, performance number is far from the expectation on recent
 537          * firmware versions. The fix for this issue may not be integrated in
 538          * the following firmware version. So the workaround in software driver
 539          * is needed. It needs to modify the initial values of 3 internal only
 540          * registers. Note that the workaround can be removed when it is fixed
 541          * in firmware in the future.
 542          */
 543         i40e_configure_registers(hw);
 544
 545         /* Get hw capabilities */
 546         ret = i40e_get_cap(hw);
 547         if (ret != I40E_SUCCESS) {
 548                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 549                 goto err_get_capabilities;
 550         }
 551
 552         /* Initialize parameters for PF */
 553         ret = i40e_pf_parameter_init(dev);
 554         if (ret != 0) {
 555                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 556                 goto err_parameter_init;
 557         }
 558
 559         /* Initialize the queue management */
 560         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 561         if (ret < 0) {
 562                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 563                 goto err_qp_pool_init;
 564         }
 565         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 566                                 hw->func_caps.num_msix_vectors - 1);
 567         if (ret < 0) {
 568                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 569                 goto err_msix_pool_init;
 570         }
 571
 572         /* Initialize lan hmc */
 573         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 574                                 hw->func_caps.num_rx_qp, 0, 0);
 575         if (ret != I40E_SUCCESS) {
 576                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 577                 goto err_init_lan_hmc;
 578         }
 579
 580         /* Configure lan hmc */
 581         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 582         if (ret != I40E_SUCCESS) {
 583                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 584                 goto err_configure_lan_hmc;
 585         }
 586
 587         /* Get and check the mac address */
 588         i40e_get_mac_addr(hw, hw->mac.addr);
 589         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 590                 PMD_INIT_LOG(ERR, "mac address is not valid");
 591                 ret = -EIO;
 592                 goto err_get_mac_addr;
 593         }
 594         /* Copy the permanent MAC address */
 595         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 596                         (struct ether_addr *) hw->mac.perm_addr);
 597
 598         /* Disable flow control */
 599         hw->fc.requested_mode = I40E_FC_NONE;
 600         i40e_set_fc(hw, &aq_fail, TRUE);
 601
 602         /* PF setup, which includes VSI setup */
 603         ret = i40e_pf_setup(pf);
 604         if (ret) {
 605                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 606                 goto err_setup_pf_switch;
 607         }
 608
 609         vsi = pf->main_vsi;
 610
 611         /* Disable double vlan by default */
 612         i40e_vsi_config_double_vlan(vsi, FALSE);
 613
 614         if (!vsi->max_macaddrs)
 615                 len = ETHER_ADDR_LEN;
 616         else
 617                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 618
 619         /* Should be after VSI initialized */
 620         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 621         if (!dev->data->mac_addrs) {
 622                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 623                                         "for storing mac address");
 624                 goto err_mac_alloc;
 625         }
 626         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 627                                         &dev->data->mac_addrs[0]);
 628
 629         /* initialize pf host driver to setup SRIOV resource if applicable */
 630         i40e_pf_host_init(dev);
 631
 632         /* register callback func to eal lib */
 633         rte_intr_callback_register(&(pci_dev->intr_handle),
 634                 i40e_dev_interrupt_handler, (void *)dev);
 635
 636         /* configure and enable device interrupt */
 637         i40e_pf_config_irq0(hw);
 638         i40e_pf_enable_irq0(hw);
 639
 640         /* enable uio intr after callback register */
 641         rte_intr_enable(&(pci_dev->intr_handle));
 642         /*
 643          * Add an ethertype filter to drop all flow control frames transmitted
 644          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 645          * frames to wire.
 646          */
 647         i40e_add_tx_flow_control_drop_filter(pf);
 648
 649         /* initialize mirror rule list */
 650         TAILQ_INIT(&pf->mirror_list);
 651
 652         /* Init dcb to sw mode by default */
 653         ret = i40e_dcb_init_configure(dev, TRUE);
 654         if (ret != I40E_SUCCESS) {
 655                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 656                 pf->flags &= ~I40E_FLAG_DCB;
 657         }
 658
 659         return 0;
 660
 661 err_mac_alloc:
 662         i40e_vsi_release(pf->main_vsi);
 663 err_setup_pf_switch:
 664 err_get_mac_addr:
 665 err_configure_lan_hmc:
 666         (void)i40e_shutdown_lan_hmc(hw);
 667 err_init_lan_hmc:
 668         i40e_res_pool_destroy(&pf->msix_pool);
 669 err_msix_pool_init:
 670         i40e_res_pool_destroy(&pf->qp_pool);
 671 err_qp_pool_init:
 672 err_parameter_init:
 673 err_get_capabilities:
 674         (void)i40e_shutdown_adminq(hw);
 675
 676         return ret;
 677 }
 678
 679 static int
 680 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 681 {
 682         struct rte_pci_device *pci_dev;
 683         struct i40e_hw *hw;
 684         struct i40e_filter_control_settings settings;
 685         int ret;
 686         uint8_t aq_fail = 0;
 687
 688         PMD_INIT_FUNC_TRACE();
 689
 690         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 691                 return 0;
 692
 693         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 694         pci_dev = dev->pci_dev;
 695
 696         if (hw->adapter_stopped == 0)
 697                 i40e_dev_close(dev);
 698
 699         dev->dev_ops = NULL;
 700         dev->rx_pkt_burst = NULL;
 701         dev->tx_pkt_burst = NULL;
 702
 703         /* Disable LLDP */
 704         ret = i40e_aq_stop_lldp(hw, true, NULL);
 705         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 706                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 707
 708         /* Clear PXE mode */
 709         i40e_clear_pxe_mode(hw);
 710
 711         /* Unconfigure filter control */
 712         memset(&settings, 0, sizeof(settings));
 713         ret = i40e_set_filter_control(hw, &settings);
 714         if (ret)
 715                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 716                                         ret);
 717
 718         /* Disable flow control */
 719         hw->fc.requested_mode = I40E_FC_NONE;
 720         i40e_set_fc(hw, &aq_fail, TRUE);
 721
 722         /* uninitialize pf host driver */
 723         i40e_pf_host_uninit(dev);
 724
 725         rte_free(dev->data->mac_addrs);
 726         dev->data->mac_addrs = NULL;
 727
 728         /* disable uio intr before callback unregister */
 729         rte_intr_disable(&(pci_dev->intr_handle));
 730
 731         /* register callback func to eal lib */
 732         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 733                 i40e_dev_interrupt_handler, (void *)dev);
 734
 735         return 0;
 736 }
 737
 738 static int
 739 i40e_dev_configure(struct rte_eth_dev *dev)
 740 {
 741         struct i40e_adapter *ad =
 742                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 744         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 745         int i, ret;
 746
 747         /* Initialize to TRUE. If any of Rx queues doesn't meet the
 748          * bulk allocation or vector Rx preconditions we will reset it.
 749          */
 750         ad->rx_bulk_alloc_allowed = true;
 751         ad->rx_vec_allowed = true;
 752         ad->tx_simple_allowed = true;
 753         ad->tx_vec_allowed = true;
 754
 755         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 756                 ret = i40e_fdir_setup(pf);
 757                 if (ret != I40E_SUCCESS) {
 758                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 759                         return -ENOTSUP;
 760                 }
 761                 ret = i40e_fdir_configure(dev);
 762                 if (ret < 0) {
 763                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 764                         goto err;
 765                 }
 766         } else
 767                 i40e_fdir_teardown(pf);
 768
 769         ret = i40e_dev_init_vlan(dev);
 770         if (ret < 0)
 771                 goto err;
 772
 773         /* VMDQ setup.
 774          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 775          *  RSS setting have different requirements.
 776          *  General PMD driver call sequence are NIC init, configure,
 777          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 778          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 779          *  applicable. So, VMDQ setting has to be done before
 780          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 781          *  For RSS setting, it will try to calculate actual configured RX queue
 782          *  number, which will be available after rx_queue_setup(). dev_start()
 783          *  function is good to place RSS setup.
 784          */
 785         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 786                 ret = i40e_vmdq_setup(dev);
 787                 if (ret)
 788                         goto err;
 789         }
 790
 791         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
 792                 ret = i40e_dcb_setup(dev);
 793                 if (ret) {
 794                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
 795                         goto err_dcb;
 796                 }
 797         }
 798
 799         return 0;
 800
 801 err_dcb:
 802         /* need to release vmdq resource if exists */
 803         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 804                 i40e_vsi_release(pf->vmdq[i].vsi);
 805                 pf->vmdq[i].vsi = NULL;
 806         }
 807         rte_free(pf->vmdq);
 808         pf->vmdq = NULL;
 809 err:
 810         /* need to release fdir resource if exists */
 811         i40e_fdir_teardown(pf);
 812         return ret;
 813 }
 814
 815 void
 816 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 817 {
 818         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 819         uint16_t msix_vect = vsi->msix_intr;
 820         uint16_t i;
 821
 822         for (i = 0; i < vsi->nb_qps; i++) {
 823                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 824                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 825                 rte_wmb();
 826         }
 827
 828         if (vsi->type != I40E_VSI_SRIOV) {
 829                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 830                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 831                                 msix_vect - 1), 0);
 832         } else {
 833                 uint32_t reg;
 834                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 835                         vsi->user_param + (msix_vect - 1);
 836
 837                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 838         }
 839         I40E_WRITE_FLUSH(hw);
 840 }
 841
 842 static inline uint16_t
 843 i40e_calc_itr_interval(int16_t interval)
 844 {
 845         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 846                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 847
 848         /* Convert to hardware count, as writing each 1 represents 2 us */
 849         return (interval/2);
 850 }
 851
 852 void
 853 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 854 {
 855         uint32_t val;
 856         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 857         uint16_t msix_vect = vsi->msix_intr;
 858         int i;
 859
 860         for (i = 0; i < vsi->nb_qps; i++)
 861                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 862
 863         /* Bind all RX queues to allocated MSIX interrupt */
 864         for (i = 0; i < vsi->nb_qps; i++) {
 865                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 866                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 867                         ((vsi->base_queue + i + 1) <<
 868                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 869                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 870                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 871
 872                 if (i == vsi->nb_qps - 1)
 873                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 874                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 875         }
 876
 877         /* Write first RX queue to Link list register as the head element */
 878         if (vsi->type != I40E_VSI_SRIOV) {
 879                 uint16_t interval =
 880                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 881
 882                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 883                                                 (vsi->base_queue <<
 884                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 885                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 886
 887                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 888                                                 msix_vect - 1), interval);
 889
 890 #ifndef I40E_GLINT_CTL
 891 #define I40E_GLINT_CTL                     0x0003F800
 892 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 893 #endif
 894                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 895                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 896                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 897         } else {
 898                 uint32_t reg;
 899
 900                 /* num_msix_vectors_vf needs to minus irq0 */
 901                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 902                         vsi->user_param + (msix_vect - 1);
 903
 904                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 905                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 906                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 907         }
 908
 909         I40E_WRITE_FLUSH(hw);
 910 }
 911
 912 static void
 913 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 914 {
 915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 916         uint16_t interval = i40e_calc_itr_interval(\
 917                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 918
 919         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 920                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 921                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 922                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 923                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 924 }
 925
 926 static void
 927 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 928 {
 929         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 930
 931         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 932 }
 933
 934 static inline uint8_t
 935 i40e_parse_link_speed(uint16_t eth_link_speed)
 936 {
 937         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 938
 939         switch (eth_link_speed) {
 940         case ETH_LINK_SPEED_40G:
 941                 link_speed = I40E_LINK_SPEED_40GB;
 942                 break;
 943         case ETH_LINK_SPEED_20G:
 944                 link_speed = I40E_LINK_SPEED_20GB;
 945                 break;
 946         case ETH_LINK_SPEED_10G:
 947                 link_speed = I40E_LINK_SPEED_10GB;
 948                 break;
 949         case ETH_LINK_SPEED_1000:
 950                 link_speed = I40E_LINK_SPEED_1GB;
 951                 break;
 952         case ETH_LINK_SPEED_100:
 953                 link_speed = I40E_LINK_SPEED_100MB;
 954                 break;
 955         }
 956
 957         return link_speed;
 958 }
 959
 960 static int
 961 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 962 {
 963         enum i40e_status_code status;
 964         struct i40e_aq_get_phy_abilities_resp phy_ab;
 965         struct i40e_aq_set_phy_config phy_conf;
 966         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 967                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 968                         I40E_AQ_PHY_FLAG_LOW_POWER;
 969         const uint8_t advt = I40E_LINK_SPEED_40GB |
 970                         I40E_LINK_SPEED_10GB |
 971                         I40E_LINK_SPEED_1GB |
 972                         I40E_LINK_SPEED_100MB;
 973         int ret = -ENOTSUP;
 974
 975         /* Skip it on 40G interfaces, as a workaround for the link issue */
 976         if (i40e_is_40G_device(hw->device_id))
 977                 return I40E_SUCCESS;
 978
 979         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 980                                               NULL);
 981         if (status)
 982                 return ret;
 983
 984         memset(&phy_conf, 0, sizeof(phy_conf));
 985
 986         /* bits 0-2 use the values from get_phy_abilities_resp */
 987         abilities &= ~mask;
 988         abilities |= phy_ab.abilities & mask;
 989
 990         /* update ablities and speed */
 991         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 992                 phy_conf.link_speed = advt;
 993         else
 994                 phy_conf.link_speed = force_speed;
 995
 996         phy_conf.abilities = abilities;
 997
 998         /* use get_phy_abilities_resp value for the rest */
 999         phy_conf.phy_type = phy_ab.phy_type;
1000         phy_conf.eee_capability = phy_ab.eee_capability;
1001         phy_conf.eeer = phy_ab.eeer_val;
1002         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1003
1004         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1005                     phy_ab.abilities, phy_ab.link_speed);
1006         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1007                     phy_conf.abilities, phy_conf.link_speed);
1008
1009         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1010         if (status)
1011                 return ret;
1012
1013         return I40E_SUCCESS;
1014 }
1015
1016 static int
1017 i40e_apply_link_speed(struct rte_eth_dev *dev)
1018 {
1019         uint8_t speed;
1020         uint8_t abilities = 0;
1021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022         struct rte_eth_conf *conf = &dev->data->dev_conf;
1023
1024         speed = i40e_parse_link_speed(conf->link_speed);
1025         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1026         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1027                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1028         else
1029                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1030
1031         return i40e_phy_conf_link(hw, abilities, speed);
1032 }
1033
1034 static int
1035 i40e_dev_start(struct rte_eth_dev *dev)
1036 {
1037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039         struct i40e_vsi *main_vsi = pf->main_vsi;
1040         int ret, i;
1041
1042         hw->adapter_stopped = 0;
1043
1044         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1045                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1046                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1047                              dev->data->dev_conf.link_duplex,
1048                              dev->data->port_id);
1049                 return -EINVAL;
1050         }
1051
1052         /* Initialize VSI */
1053         ret = i40e_dev_rxtx_init(pf);
1054         if (ret != I40E_SUCCESS) {
1055                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1056                 goto err_up;
1057         }
1058
1059         /* Map queues with MSIX interrupt */
1060         i40e_vsi_queues_bind_intr(main_vsi);
1061         i40e_vsi_enable_queues_intr(main_vsi);
1062
1063         /* Map VMDQ VSI queues with MSIX interrupt */
1064         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1065                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1066                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1067         }
1068
1069         /* enable FDIR MSIX interrupt */
1070         if (pf->fdir.fdir_vsi) {
1071                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1072                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1073         }
1074
1075         /* Enable all queues which have been configured */
1076         ret = i40e_dev_switch_queues(pf, TRUE);
1077         if (ret != I40E_SUCCESS) {
1078                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1079                 goto err_up;
1080         }
1081
1082         /* Enable receiving broadcast packets */
1083         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1084         if (ret != I40E_SUCCESS)
1085                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1086
1087         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1088                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1089                                                 true, NULL);
1090                 if (ret != I40E_SUCCESS)
1091                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1092         }
1093
1094         /* Apply link configure */
1095         ret = i40e_apply_link_speed(dev);
1096         if (I40E_SUCCESS != ret) {
1097                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1098                 goto err_up;
1099         }
1100
1101         return I40E_SUCCESS;
1102
1103 err_up:
1104         i40e_dev_switch_queues(pf, FALSE);
1105         i40e_dev_clear_queues(dev);
1106
1107         return ret;
1108 }
1109
1110 static void
1111 i40e_dev_stop(struct rte_eth_dev *dev)
1112 {
1113         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1114         struct i40e_vsi *main_vsi = pf->main_vsi;
1115         struct i40e_mirror_rule *p_mirror;
1116         int i;
1117
1118         /* Disable all queues */
1119         i40e_dev_switch_queues(pf, FALSE);
1120
1121         /* un-map queues with interrupt registers */
1122         i40e_vsi_disable_queues_intr(main_vsi);
1123         i40e_vsi_queues_unbind_intr(main_vsi);
1124
1125         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1126                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1127                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1128         }
1129
1130         if (pf->fdir.fdir_vsi) {
1131                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1132                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1133         }
1134         /* Clear all queues and release memory */
1135         i40e_dev_clear_queues(dev);
1136
1137         /* Set link down */
1138         i40e_dev_set_link_down(dev);
1139
1140         /* Remove all mirror rules */
1141         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1142                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1143                 rte_free(p_mirror);
1144         }
1145         pf->nb_mirror_rule = 0;
1146
1147 }
1148
1149 static void
1150 i40e_dev_close(struct rte_eth_dev *dev)
1151 {
1152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154         uint32_t reg;
1155         int i;
1156
1157         PMD_INIT_FUNC_TRACE();
1158
1159         i40e_dev_stop(dev);
1160         hw->adapter_stopped = 1;
1161         i40e_dev_free_queues(dev);
1162
1163         /* Disable interrupt */
1164         i40e_pf_disable_irq0(hw);
1165         rte_intr_disable(&(dev->pci_dev->intr_handle));
1166
1167         /* shutdown and destroy the HMC */
1168         i40e_shutdown_lan_hmc(hw);
1169
1170         /* release all the existing VSIs and VEBs */
1171         i40e_fdir_teardown(pf);
1172         i40e_vsi_release(pf->main_vsi);
1173
1174         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1175                 i40e_vsi_release(pf->vmdq[i].vsi);
1176                 pf->vmdq[i].vsi = NULL;
1177         }
1178
1179         rte_free(pf->vmdq);
1180         pf->vmdq = NULL;
1181
1182         /* shutdown the adminq */
1183         i40e_aq_queue_shutdown(hw, true);
1184         i40e_shutdown_adminq(hw);
1185
1186         i40e_res_pool_destroy(&pf->qp_pool);
1187         i40e_res_pool_destroy(&pf->msix_pool);
1188
1189         /* force a PF reset to clean anything leftover */
1190         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1191         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1192                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1193         I40E_WRITE_FLUSH(hw);
1194 }
1195
1196 static void
1197 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1198 {
1199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1201         struct i40e_vsi *vsi = pf->main_vsi;
1202         int status;
1203
1204         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1205                                                         true, NULL);
1206         if (status != I40E_SUCCESS)
1207                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1208
1209         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1210                                                         TRUE, NULL);
1211         if (status != I40E_SUCCESS)
1212                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1213
1214 }
1215
1216 static void
1217 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1218 {
1219         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1220         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1221         struct i40e_vsi *vsi = pf->main_vsi;
1222         int status;
1223
1224         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1225                                                         false, NULL);
1226         if (status != I40E_SUCCESS)
1227                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1228
1229         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1230                                                         false, NULL);
1231         if (status != I40E_SUCCESS)
1232                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1233 }
1234
1235 static void
1236 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1237 {
1238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240         struct i40e_vsi *vsi = pf->main_vsi;
1241         int ret;
1242
1243         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1244         if (ret != I40E_SUCCESS)
1245                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1246 }
1247
1248 static void
1249 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1250 {
1251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1253         struct i40e_vsi *vsi = pf->main_vsi;
1254         int ret;
1255
1256         if (dev->data->promiscuous == 1)
1257                 return; /* must remain in all_multicast mode */
1258
1259         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1260                                 vsi->seid, FALSE, NULL);
1261         if (ret != I40E_SUCCESS)
1262                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1263 }
1264
1265 /*
1266  * Set device link up.
1267  */
1268 static int
1269 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1270 {
1271         /* re-apply link speed setting */
1272         return i40e_apply_link_speed(dev);
1273 }
1274
1275 /*
1276  * Set device link down.
1277  */
1278 static int
1279 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1280 {
1281         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1282         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284
1285         return i40e_phy_conf_link(hw, abilities, speed);
1286 }
1287
1288 int
1289 i40e_dev_link_update(struct rte_eth_dev *dev,
1290                      int wait_to_complete)
1291 {
1292 #define CHECK_INTERVAL 100  /* 100ms */
1293 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1295         struct i40e_link_status link_status;
1296         struct rte_eth_link link, old;
1297         int status;
1298         unsigned rep_cnt = MAX_REPEAT_TIME;
1299
1300         memset(&link, 0, sizeof(link));
1301         memset(&old, 0, sizeof(old));
1302         memset(&link_status, 0, sizeof(link_status));
1303         rte_i40e_dev_atomic_read_link_status(dev, &old);
1304
1305         do {
1306                 /* Get link status information from hardware */
1307                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1308                 if (status != I40E_SUCCESS) {
1309                         link.link_speed = ETH_LINK_SPEED_100;
1310                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1311                         PMD_DRV_LOG(ERR, "Failed to get link info");
1312                         goto out;
1313                 }
1314
1315                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1316                 if (!wait_to_complete)
1317                         break;
1318
1319                 rte_delay_ms(CHECK_INTERVAL);
1320         } while (!link.link_status && rep_cnt--);
1321
1322         if (!link.link_status)
1323                 goto out;
1324
1325         /* i40e uses full duplex only */
1326         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1327
1328         /* Parse the link status */
1329         switch (link_status.link_speed) {
1330         case I40E_LINK_SPEED_100MB:
1331                 link.link_speed = ETH_LINK_SPEED_100;
1332                 break;
1333         case I40E_LINK_SPEED_1GB:
1334                 link.link_speed = ETH_LINK_SPEED_1000;
1335                 break;
1336         case I40E_LINK_SPEED_10GB:
1337                 link.link_speed = ETH_LINK_SPEED_10G;
1338                 break;
1339         case I40E_LINK_SPEED_20GB:
1340                 link.link_speed = ETH_LINK_SPEED_20G;
1341                 break;
1342         case I40E_LINK_SPEED_40GB:
1343                 link.link_speed = ETH_LINK_SPEED_40G;
1344                 break;
1345         default:
1346                 link.link_speed = ETH_LINK_SPEED_100;
1347                 break;
1348         }
1349
1350 out:
1351         rte_i40e_dev_atomic_write_link_status(dev, &link);
1352         if (link.link_status == old.link_status)
1353                 return -1;
1354
1355         return 0;
1356 }
1357
1358 /* Get all the statistics of a VSI */
1359 void
1360 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1361 {
1362         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1363         struct i40e_eth_stats *nes = &vsi->eth_stats;
1364         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1365         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1366
1367         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1368                             vsi->offset_loaded, &oes->rx_bytes,
1369                             &nes->rx_bytes);
1370         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1371                             vsi->offset_loaded, &oes->rx_unicast,
1372                             &nes->rx_unicast);
1373         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1374                             vsi->offset_loaded, &oes->rx_multicast,
1375                             &nes->rx_multicast);
1376         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1377                             vsi->offset_loaded, &oes->rx_broadcast,
1378                             &nes->rx_broadcast);
1379         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1380                             &oes->rx_discards, &nes->rx_discards);
1381         /* GLV_REPC not supported */
1382         /* GLV_RMPC not supported */
1383         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1384                             &oes->rx_unknown_protocol,
1385                             &nes->rx_unknown_protocol);
1386         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1387                             vsi->offset_loaded, &oes->tx_bytes,
1388                             &nes->tx_bytes);
1389         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1390                             vsi->offset_loaded, &oes->tx_unicast,
1391                             &nes->tx_unicast);
1392         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1393                             vsi->offset_loaded, &oes->tx_multicast,
1394                             &nes->tx_multicast);
1395         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1396                             vsi->offset_loaded,  &oes->tx_broadcast,
1397                             &nes->tx_broadcast);
1398         /* GLV_TDPC not supported */
1399         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1400                             &oes->tx_errors, &nes->tx_errors);
1401         vsi->offset_loaded = true;
1402
1403         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1404                     vsi->vsi_id);
1405         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1406         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1407         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1408         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1409         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1410         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1411                     nes->rx_unknown_protocol);
1412         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1413         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1414         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1415         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1416         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1417         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1418         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1419                     vsi->vsi_id);
1420 }
1421
1422 /* Get all statistics of a port */
1423 static void
1424 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1425 {
1426         uint32_t i;
1427         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1428         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1430         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1431
1432         /* Get statistics of struct i40e_eth_stats */
1433         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1434                             I40E_GLPRT_GORCL(hw->port),
1435                             pf->offset_loaded, &os->eth.rx_bytes,
1436                             &ns->eth.rx_bytes);
1437         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1438                             I40E_GLPRT_UPRCL(hw->port),
1439                             pf->offset_loaded, &os->eth.rx_unicast,
1440                             &ns->eth.rx_unicast);
1441         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1442                             I40E_GLPRT_MPRCL(hw->port),
1443                             pf->offset_loaded, &os->eth.rx_multicast,
1444                             &ns->eth.rx_multicast);
1445         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1446                             I40E_GLPRT_BPRCL(hw->port),
1447                             pf->offset_loaded, &os->eth.rx_broadcast,
1448                             &ns->eth.rx_broadcast);
1449         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1450                             pf->offset_loaded, &os->eth.rx_discards,
1451                             &ns->eth.rx_discards);
1452         /* GLPRT_REPC not supported */
1453         /* GLPRT_RMPC not supported */
1454         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1455                             pf->offset_loaded,
1456                             &os->eth.rx_unknown_protocol,
1457                             &ns->eth.rx_unknown_protocol);
1458         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1459                             I40E_GLPRT_GOTCL(hw->port),
1460                             pf->offset_loaded, &os->eth.tx_bytes,
1461                             &ns->eth.tx_bytes);
1462         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1463                             I40E_GLPRT_UPTCL(hw->port),
1464                             pf->offset_loaded, &os->eth.tx_unicast,
1465                             &ns->eth.tx_unicast);
1466         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1467                             I40E_GLPRT_MPTCL(hw->port),
1468                             pf->offset_loaded, &os->eth.tx_multicast,
1469                             &ns->eth.tx_multicast);
1470         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1471                             I40E_GLPRT_BPTCL(hw->port),
1472                             pf->offset_loaded, &os->eth.tx_broadcast,
1473                             &ns->eth.tx_broadcast);
1474         /* GLPRT_TEPC not supported */
1475
1476         /* additional port specific stats */
1477         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1478                             pf->offset_loaded, &os->tx_dropped_link_down,
1479                             &ns->tx_dropped_link_down);
1480         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1481                             pf->offset_loaded, &os->crc_errors,
1482                             &ns->crc_errors);
1483         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1484                             pf->offset_loaded, &os->illegal_bytes,
1485                             &ns->illegal_bytes);
1486         /* GLPRT_ERRBC not supported */
1487         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1488                             pf->offset_loaded, &os->mac_local_faults,
1489                             &ns->mac_local_faults);
1490         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1491                             pf->offset_loaded, &os->mac_remote_faults,
1492                             &ns->mac_remote_faults);
1493         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1494                             pf->offset_loaded, &os->rx_length_errors,
1495                             &ns->rx_length_errors);
1496         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1497                             pf->offset_loaded, &os->link_xon_rx,
1498                             &ns->link_xon_rx);
1499         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1500                             pf->offset_loaded, &os->link_xoff_rx,
1501                             &ns->link_xoff_rx);
1502         for (i = 0; i < 8; i++) {
1503                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1504                                     pf->offset_loaded,
1505                                     &os->priority_xon_rx[i],
1506                                     &ns->priority_xon_rx[i]);
1507                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1508                                     pf->offset_loaded,
1509                                     &os->priority_xoff_rx[i],
1510                                     &ns->priority_xoff_rx[i]);
1511         }
1512         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1513                             pf->offset_loaded, &os->link_xon_tx,
1514                             &ns->link_xon_tx);
1515         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1516                             pf->offset_loaded, &os->link_xoff_tx,
1517                             &ns->link_xoff_tx);
1518         for (i = 0; i < 8; i++) {
1519                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1520                                     pf->offset_loaded,
1521                                     &os->priority_xon_tx[i],
1522                                     &ns->priority_xon_tx[i]);
1523                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1524                                     pf->offset_loaded,
1525                                     &os->priority_xoff_tx[i],
1526                                     &ns->priority_xoff_tx[i]);
1527                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1528                                     pf->offset_loaded,
1529                                     &os->priority_xon_2_xoff[i],
1530                                     &ns->priority_xon_2_xoff[i]);
1531         }
1532         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1533                             I40E_GLPRT_PRC64L(hw->port),
1534                             pf->offset_loaded, &os->rx_size_64,
1535                             &ns->rx_size_64);
1536         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1537                             I40E_GLPRT_PRC127L(hw->port),
1538                             pf->offset_loaded, &os->rx_size_127,
1539                             &ns->rx_size_127);
1540         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1541                             I40E_GLPRT_PRC255L(hw->port),
1542                             pf->offset_loaded, &os->rx_size_255,
1543                             &ns->rx_size_255);
1544         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1545                             I40E_GLPRT_PRC511L(hw->port),
1546                             pf->offset_loaded, &os->rx_size_511,
1547                             &ns->rx_size_511);
1548         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1549                             I40E_GLPRT_PRC1023L(hw->port),
1550                             pf->offset_loaded, &os->rx_size_1023,
1551                             &ns->rx_size_1023);
1552         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1553                             I40E_GLPRT_PRC1522L(hw->port),
1554                             pf->offset_loaded, &os->rx_size_1522,
1555                             &ns->rx_size_1522);
1556         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1557                             I40E_GLPRT_PRC9522L(hw->port),
1558                             pf->offset_loaded, &os->rx_size_big,
1559                             &ns->rx_size_big);
1560         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1561                             pf->offset_loaded, &os->rx_undersize,
1562                             &ns->rx_undersize);
1563         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1564                             pf->offset_loaded, &os->rx_fragments,
1565                             &ns->rx_fragments);
1566         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1567                             pf->offset_loaded, &os->rx_oversize,
1568                             &ns->rx_oversize);
1569         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1570                             pf->offset_loaded, &os->rx_jabber,
1571                             &ns->rx_jabber);
1572         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1573                             I40E_GLPRT_PTC64L(hw->port),
1574                             pf->offset_loaded, &os->tx_size_64,
1575                             &ns->tx_size_64);
1576         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1577                             I40E_GLPRT_PTC127L(hw->port),
1578                             pf->offset_loaded, &os->tx_size_127,
1579                             &ns->tx_size_127);
1580         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1581                             I40E_GLPRT_PTC255L(hw->port),
1582                             pf->offset_loaded, &os->tx_size_255,
1583                             &ns->tx_size_255);
1584         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1585                             I40E_GLPRT_PTC511L(hw->port),
1586                             pf->offset_loaded, &os->tx_size_511,
1587                             &ns->tx_size_511);
1588         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1589                             I40E_GLPRT_PTC1023L(hw->port),
1590                             pf->offset_loaded, &os->tx_size_1023,
1591                             &ns->tx_size_1023);
1592         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1593                             I40E_GLPRT_PTC1522L(hw->port),
1594                             pf->offset_loaded, &os->tx_size_1522,
1595                             &ns->tx_size_1522);
1596         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1597                             I40E_GLPRT_PTC9522L(hw->port),
1598                             pf->offset_loaded, &os->tx_size_big,
1599                             &ns->tx_size_big);
1600         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1601                            pf->offset_loaded,
1602                            &os->fd_sb_match, &ns->fd_sb_match);
1603         /* GLPRT_MSPDC not supported */
1604         /* GLPRT_XEC not supported */
1605
1606         pf->offset_loaded = true;
1607
1608         if (pf->main_vsi)
1609                 i40e_update_vsi_stats(pf->main_vsi);
1610
1611         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1612                                                 ns->eth.rx_broadcast;
1613         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1614                                                 ns->eth.tx_broadcast;
1615         stats->ibytes   = ns->eth.rx_bytes;
1616         stats->obytes   = ns->eth.tx_bytes;
1617         stats->oerrors  = ns->eth.tx_errors;
1618         stats->imcasts  = ns->eth.rx_multicast;
1619         stats->fdirmatch = ns->fd_sb_match;
1620
1621         /* Rx Errors */
1622         stats->ibadcrc  = ns->crc_errors;
1623         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1624                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1625         stats->imissed  = ns->eth.rx_discards;
1626         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1627
1628         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1629         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1630         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1631         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1632         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1633         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1634         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1635                     ns->eth.rx_unknown_protocol);
1636         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1637         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1638         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1639         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1640         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1641         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1642
1643         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1644                     ns->tx_dropped_link_down);
1645         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1646         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1647                     ns->illegal_bytes);
1648         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1649         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1650                     ns->mac_local_faults);
1651         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1652                     ns->mac_remote_faults);
1653         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1654                     ns->rx_length_errors);
1655         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1656         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1657         for (i = 0; i < 8; i++) {
1658                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1659                                 i, ns->priority_xon_rx[i]);
1660                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1661                                 i, ns->priority_xoff_rx[i]);
1662         }
1663         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1664         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1665         for (i = 0; i < 8; i++) {
1666                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1667                                 i, ns->priority_xon_tx[i]);
1668                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1669                                 i, ns->priority_xoff_tx[i]);
1670                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1671                                 i, ns->priority_xon_2_xoff[i]);
1672         }
1673         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1674         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1675         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1676         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1677         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1678         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1679         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1680         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1681         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1682         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1683         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1684         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1685         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1686         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1687         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1688         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1689         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1690         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1691         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1692                         ns->mac_short_packet_dropped);
1693         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1694                     ns->checksum_error);
1695         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1696         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1697 }
1698
1699 /* Reset the statistics */
1700 static void
1701 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1702 {
1703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1704
1705         /* It results in reloading the start point of each counter */
1706         pf->offset_loaded = false;
1707 }
1708
1709 static int
1710 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1711                                  __rte_unused uint16_t queue_id,
1712                                  __rte_unused uint8_t stat_idx,
1713                                  __rte_unused uint8_t is_rx)
1714 {
1715         PMD_INIT_FUNC_TRACE();
1716
1717         return -ENOSYS;
1718 }
1719
1720 static void
1721 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1722 {
1723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1724         struct i40e_vsi *vsi = pf->main_vsi;
1725
1726         dev_info->max_rx_queues = vsi->nb_qps;
1727         dev_info->max_tx_queues = vsi->nb_qps;
1728         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1729         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1730         dev_info->max_mac_addrs = vsi->max_macaddrs;
1731         dev_info->max_vfs = dev->pci_dev->max_vfs;
1732         dev_info->rx_offload_capa =
1733                 DEV_RX_OFFLOAD_VLAN_STRIP |
1734                 DEV_RX_OFFLOAD_QINQ_STRIP |
1735                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1736                 DEV_RX_OFFLOAD_UDP_CKSUM |
1737                 DEV_RX_OFFLOAD_TCP_CKSUM;
1738         dev_info->tx_offload_capa =
1739                 DEV_TX_OFFLOAD_VLAN_INSERT |
1740                 DEV_TX_OFFLOAD_QINQ_INSERT |
1741                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1742                 DEV_TX_OFFLOAD_UDP_CKSUM |
1743                 DEV_TX_OFFLOAD_TCP_CKSUM |
1744                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1745                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1746                 DEV_TX_OFFLOAD_TCP_TSO;
1747         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1748                                                 sizeof(uint32_t);
1749         dev_info->reta_size = pf->hash_lut_size;
1750         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1751
1752         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1753                 .rx_thresh = {
1754                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1755                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1756                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1757                 },
1758                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1759                 .rx_drop_en = 0,
1760         };
1761
1762         dev_info->default_txconf = (struct rte_eth_txconf) {
1763                 .tx_thresh = {
1764                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1765                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1766                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1767                 },
1768                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1769                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1770                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1771                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1772         };
1773
1774         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1775                 .nb_max = I40E_MAX_RING_DESC,
1776                 .nb_min = I40E_MIN_RING_DESC,
1777                 .nb_align = I40E_ALIGN_RING_DESC,
1778         };
1779
1780         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1781                 .nb_max = I40E_MAX_RING_DESC,
1782                 .nb_min = I40E_MIN_RING_DESC,
1783                 .nb_align = I40E_ALIGN_RING_DESC,
1784         };
1785
1786         if (pf->flags & I40E_FLAG_VMDQ) {
1787                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1788                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1789                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1790                                                 pf->max_nb_vmdq_vsi;
1791                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1792                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1793                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1794         }
1795 }
1796
1797 static int
1798 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1799 {
1800         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1801         struct i40e_vsi *vsi = pf->main_vsi;
1802         PMD_INIT_FUNC_TRACE();
1803
1804         if (on)
1805                 return i40e_vsi_add_vlan(vsi, vlan_id);
1806         else
1807                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1808 }
1809
1810 static void
1811 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1812                    __rte_unused uint16_t tpid)
1813 {
1814         PMD_INIT_FUNC_TRACE();
1815 }
1816
1817 static void
1818 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1819 {
1820         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1821         struct i40e_vsi *vsi = pf->main_vsi;
1822
1823         if (mask & ETH_VLAN_STRIP_MASK) {
1824                 /* Enable or disable VLAN stripping */
1825                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1826                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1827                 else
1828                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1829         }
1830
1831         if (mask & ETH_VLAN_EXTEND_MASK) {
1832                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1833                         i40e_vsi_config_double_vlan(vsi, TRUE);
1834                 else
1835                         i40e_vsi_config_double_vlan(vsi, FALSE);
1836         }
1837 }
1838
1839 static void
1840 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1841                           __rte_unused uint16_t queue,
1842                           __rte_unused int on)
1843 {
1844         PMD_INIT_FUNC_TRACE();
1845 }
1846
1847 static int
1848 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1849 {
1850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1851         struct i40e_vsi *vsi = pf->main_vsi;
1852         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1853         struct i40e_vsi_vlan_pvid_info info;
1854
1855         memset(&info, 0, sizeof(info));
1856         info.on = on;
1857         if (info.on)
1858                 info.config.pvid = pvid;
1859         else {
1860                 info.config.reject.tagged =
1861                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1862                 info.config.reject.untagged =
1863                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1864         }
1865
1866         return i40e_vsi_vlan_pvid_set(vsi, &info);
1867 }
1868
1869 static int
1870 i40e_dev_led_on(struct rte_eth_dev *dev)
1871 {
1872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1873         uint32_t mode = i40e_led_get(hw);
1874
1875         if (mode == 0)
1876                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1877
1878         return 0;
1879 }
1880
1881 static int
1882 i40e_dev_led_off(struct rte_eth_dev *dev)
1883 {
1884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1885         uint32_t mode = i40e_led_get(hw);
1886
1887         if (mode != 0)
1888                 i40e_led_set(hw, 0, false);
1889
1890         return 0;
1891 }
1892
1893 static int
1894 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1895 {
1896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1898
1899         fc_conf->pause_time = pf->fc_conf.pause_time;
1900         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
1901         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
1902
1903          /* Return current mode according to actual setting*/
1904         switch (hw->fc.current_mode) {
1905         case I40E_FC_FULL:
1906                 fc_conf->mode = RTE_FC_FULL;
1907                 break;
1908         case I40E_FC_TX_PAUSE:
1909                 fc_conf->mode = RTE_FC_TX_PAUSE;
1910                 break;
1911         case I40E_FC_RX_PAUSE:
1912                 fc_conf->mode = RTE_FC_RX_PAUSE;
1913                 break;
1914         case I40E_FC_NONE:
1915         default:
1916                 fc_conf->mode = RTE_FC_NONE;
1917         };
1918
1919         return 0;
1920 }
1921
1922 static int
1923 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1924 {
1925         uint32_t mflcn_reg, fctrl_reg, reg;
1926         uint32_t max_high_water;
1927         uint8_t i, aq_failure;
1928         int err;
1929         struct i40e_hw *hw;
1930         struct i40e_pf *pf;
1931         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
1932                 [RTE_FC_NONE] = I40E_FC_NONE,
1933                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
1934                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
1935                 [RTE_FC_FULL] = I40E_FC_FULL
1936         };
1937
1938         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
1939
1940         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
1941         if ((fc_conf->high_water > max_high_water) ||
1942                         (fc_conf->high_water < fc_conf->low_water)) {
1943                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
1944                         "High_water must <= %d.", max_high_water);
1945                 return -EINVAL;
1946         }
1947
1948         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1950         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
1951
1952         pf->fc_conf.pause_time = fc_conf->pause_time;
1953         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
1954         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
1955
1956         PMD_INIT_FUNC_TRACE();
1957
1958         /* All the link flow control related enable/disable register
1959          * configuration is handle by the F/W
1960          */
1961         err = i40e_set_fc(hw, &aq_failure, true);
1962         if (err < 0)
1963                 return -ENOSYS;
1964
1965         if (i40e_is_40G_device(hw->device_id)) {
1966                 /* Configure flow control refresh threshold,
1967                  * the value for stat_tx_pause_refresh_timer[8]
1968                  * is used for global pause operation.
1969                  */
1970
1971                 I40E_WRITE_REG(hw,
1972                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
1973                                pf->fc_conf.pause_time);
1974
1975                 /* configure the timer value included in transmitted pause
1976                  * frame,
1977                  * the value for stat_tx_pause_quanta[8] is used for global
1978                  * pause operation
1979                  */
1980                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
1981                                pf->fc_conf.pause_time);
1982
1983                 fctrl_reg = I40E_READ_REG(hw,
1984                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
1985
1986                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1987                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
1988                 else
1989                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
1990
1991                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
1992                                fctrl_reg);
1993         } else {
1994                 /* Configure pause time (2 TCs per register) */
1995                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
1996                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
1997                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
1998
1999                 /* Configure flow control refresh threshold value */
2000                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2001                                pf->fc_conf.pause_time / 2);
2002
2003                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2004
2005                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2006                  *depending on configuration
2007                  */
2008                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2009                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2010                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2011                 } else {
2012                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2013                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2014                 }
2015
2016                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2017         }
2018
2019         /* config the water marker both based on the packets and bytes */
2020         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2021                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2022                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2023         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2024                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2025                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2026         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2027                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2028                        << I40E_KILOSHIFT);
2029         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2030                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2031                        << I40E_KILOSHIFT);
2032
2033         I40E_WRITE_FLUSH(hw);
2034
2035         return 0;
2036 }
2037
2038 static int
2039 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2040                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2041 {
2042         PMD_INIT_FUNC_TRACE();
2043
2044         return -ENOSYS;
2045 }
2046
2047 /* Add a MAC address, and update filters */
2048 static void
2049 i40e_macaddr_add(struct rte_eth_dev *dev,
2050                  struct ether_addr *mac_addr,
2051                  __rte_unused uint32_t index,
2052                  uint32_t pool)
2053 {
2054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2055         struct i40e_mac_filter_info mac_filter;
2056         struct i40e_vsi *vsi;
2057         int ret;
2058
2059         /* If VMDQ not enabled or configured, return */
2060         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2061                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2062                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2063                         pool);
2064                 return;
2065         }
2066
2067         if (pool > pf->nb_cfg_vmdq_vsi) {
2068                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2069                                 pool, pf->nb_cfg_vmdq_vsi);
2070                 return;
2071         }
2072
2073         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2074         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2075
2076         if (pool == 0)
2077                 vsi = pf->main_vsi;
2078         else
2079                 vsi = pf->vmdq[pool - 1].vsi;
2080
2081         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2082         if (ret != I40E_SUCCESS) {
2083                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2084                 return;
2085         }
2086 }
2087
2088 /* Remove a MAC address, and update filters */
2089 static void
2090 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2091 {
2092         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2093         struct i40e_vsi *vsi;
2094         struct rte_eth_dev_data *data = dev->data;
2095         struct ether_addr *macaddr;
2096         int ret;
2097         uint32_t i;
2098         uint64_t pool_sel;
2099
2100         macaddr = &(data->mac_addrs[index]);
2101
2102         pool_sel = dev->data->mac_pool_sel[index];
2103
2104         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2105                 if (pool_sel & (1ULL << i)) {
2106                         if (i == 0)
2107                                 vsi = pf->main_vsi;
2108                         else {
2109                                 /* No VMDQ pool enabled or configured */
2110                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2111                                         (i > pf->nb_cfg_vmdq_vsi)) {
2112                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2113                                                         "/configured");
2114                                         return;
2115                                 }
2116                                 vsi = pf->vmdq[i - 1].vsi;
2117                         }
2118                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2119
2120                         if (ret) {
2121                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2122                                 return;
2123                         }
2124                 }
2125         }
2126 }
2127
2128 /* Set perfect match or hash match of MAC and VLAN for a VF */
2129 static int
2130 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2131                  struct rte_eth_mac_filter *filter,
2132                  bool add)
2133 {
2134         struct i40e_hw *hw;
2135         struct i40e_mac_filter_info mac_filter;
2136         struct ether_addr old_mac;
2137         struct ether_addr *new_mac;
2138         struct i40e_pf_vf *vf = NULL;
2139         uint16_t vf_id;
2140         int ret;
2141
2142         if (pf == NULL) {
2143                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2144                 return -EINVAL;
2145         }
2146         hw = I40E_PF_TO_HW(pf);
2147
2148         if (filter == NULL) {
2149                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2150                 return -EINVAL;
2151         }
2152
2153         new_mac = &filter->mac_addr;
2154
2155         if (is_zero_ether_addr(new_mac)) {
2156                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2157                 return -EINVAL;
2158         }
2159
2160         vf_id = filter->dst_id;
2161
2162         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2163                 PMD_DRV_LOG(ERR, "Invalid argument.");
2164                 return -EINVAL;
2165         }
2166         vf = &pf->vfs[vf_id];
2167
2168         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2169                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2170                 return -EINVAL;
2171         }
2172
2173         if (add) {
2174                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2175                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2176                                 ETHER_ADDR_LEN);
2177                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2178                                  ETHER_ADDR_LEN);
2179
2180                 mac_filter.filter_type = filter->filter_type;
2181                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2182                 if (ret != I40E_SUCCESS) {
2183                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2184                         return -1;
2185                 }
2186                 ether_addr_copy(new_mac, &pf->dev_addr);
2187         } else {
2188                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2189                                 ETHER_ADDR_LEN);
2190                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2191                 if (ret != I40E_SUCCESS) {
2192                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2193                         return -1;
2194                 }
2195
2196                 /* Clear device address as it has been removed */
2197                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2198                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2199         }
2200
2201         return 0;
2202 }
2203
2204 /* MAC filter handle */
2205 static int
2206 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2207                 void *arg)
2208 {
2209         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2210         struct rte_eth_mac_filter *filter;
2211         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2212         int ret = I40E_NOT_SUPPORTED;
2213
2214         filter = (struct rte_eth_mac_filter *)(arg);
2215
2216         switch (filter_op) {
2217         case RTE_ETH_FILTER_NOP:
2218                 ret = I40E_SUCCESS;
2219                 break;
2220         case RTE_ETH_FILTER_ADD:
2221                 i40e_pf_disable_irq0(hw);
2222                 if (filter->is_vf)
2223                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2224                 i40e_pf_enable_irq0(hw);
2225                 break;
2226         case RTE_ETH_FILTER_DELETE:
2227                 i40e_pf_disable_irq0(hw);
2228                 if (filter->is_vf)
2229                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2230                 i40e_pf_enable_irq0(hw);
2231                 break;
2232         default:
2233                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2234                 ret = I40E_ERR_PARAM;
2235                 break;
2236         }
2237
2238         return ret;
2239 }
2240
2241 static int
2242 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2243                          struct rte_eth_rss_reta_entry64 *reta_conf,
2244                          uint16_t reta_size)
2245 {
2246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint32_t lut, l;
2249         uint16_t i, j, lut_size = pf->hash_lut_size;
2250         uint16_t idx, shift;
2251         uint8_t mask;
2252
2253         if (reta_size != lut_size ||
2254                 reta_size > ETH_RSS_RETA_SIZE_512) {
2255                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2256                         "(%d) doesn't match the number hardware can supported "
2257                                         "(%d)\n", reta_size, lut_size);
2258                 return -EINVAL;
2259         }
2260
2261         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2262                 idx = i / RTE_RETA_GROUP_SIZE;
2263                 shift = i % RTE_RETA_GROUP_SIZE;
2264                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2265                                                 I40E_4_BIT_MASK);
2266                 if (!mask)
2267                         continue;
2268                 if (mask == I40E_4_BIT_MASK)
2269                         l = 0;
2270                 else
2271                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2272                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2273                         if (mask & (0x1 << j))
2274                                 lut |= reta_conf[idx].reta[shift + j] <<
2275                                                         (CHAR_BIT * j);
2276                         else
2277                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2278                 }
2279                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2280         }
2281
2282         return 0;
2283 }
2284
2285 static int
2286 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2287                         struct rte_eth_rss_reta_entry64 *reta_conf,
2288                         uint16_t reta_size)
2289 {
2290         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2291         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292         uint32_t lut;
2293         uint16_t i, j, lut_size = pf->hash_lut_size;
2294         uint16_t idx, shift;
2295         uint8_t mask;
2296
2297         if (reta_size != lut_size ||
2298                 reta_size > ETH_RSS_RETA_SIZE_512) {
2299                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2300                         "(%d) doesn't match the number hardware can supported "
2301                                         "(%d)\n", reta_size, lut_size);
2302                 return -EINVAL;
2303         }
2304
2305         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2306                 idx = i / RTE_RETA_GROUP_SIZE;
2307                 shift = i % RTE_RETA_GROUP_SIZE;
2308                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2309                                                 I40E_4_BIT_MASK);
2310                 if (!mask)
2311                         continue;
2312
2313                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2314                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2315                         if (mask & (0x1 << j))
2316                                 reta_conf[idx].reta[shift + j] = ((lut >>
2317                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2318                 }
2319         }
2320
2321         return 0;
2322 }
2323
2324 /**
2325  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2326  * @hw:   pointer to the HW structure
2327  * @mem:  pointer to mem struct to fill out
2328  * @size: size of memory requested
2329  * @alignment: what to align the allocation to
2330  **/
2331 enum i40e_status_code
2332 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2333                         struct i40e_dma_mem *mem,
2334                         u64 size,
2335                         u32 alignment)
2336 {
2337         static uint64_t id = 0;
2338         const struct rte_memzone *mz = NULL;
2339         char z_name[RTE_MEMZONE_NAMESIZE];
2340
2341         if (!mem)
2342                 return I40E_ERR_PARAM;
2343
2344         id++;
2345         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2346 #ifdef RTE_LIBRTE_XEN_DOM0
2347         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2348                                          alignment, RTE_PGSIZE_2M);
2349 #else
2350         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2351                                          alignment);
2352 #endif
2353         if (!mz)
2354                 return I40E_ERR_NO_MEMORY;
2355
2356         mem->id = id;
2357         mem->size = size;
2358         mem->va = mz->addr;
2359 #ifdef RTE_LIBRTE_XEN_DOM0
2360         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2361 #else
2362         mem->pa = mz->phys_addr;
2363 #endif
2364
2365         return I40E_SUCCESS;
2366 }
2367
2368 /**
2369  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2370  * @hw:   pointer to the HW structure
2371  * @mem:  ptr to mem struct to free
2372  **/
2373 enum i40e_status_code
2374 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2375                     struct i40e_dma_mem *mem)
2376 {
2377         if (!mem || !mem->va)
2378                 return I40E_ERR_PARAM;
2379
2380         mem->va = NULL;
2381         mem->pa = (u64)0;
2382
2383         return I40E_SUCCESS;
2384 }
2385
2386 /**
2387  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2388  * @hw:   pointer to the HW structure
2389  * @mem:  pointer to mem struct to fill out
2390  * @size: size of memory requested
2391  **/
2392 enum i40e_status_code
2393 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2394                          struct i40e_virt_mem *mem,
2395                          u32 size)
2396 {
2397         if (!mem)
2398                 return I40E_ERR_PARAM;
2399
2400         mem->size = size;
2401         mem->va = rte_zmalloc("i40e", size, 0);
2402
2403         if (mem->va)
2404                 return I40E_SUCCESS;
2405         else
2406                 return I40E_ERR_NO_MEMORY;
2407 }
2408
2409 /**
2410  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2411  * @hw:   pointer to the HW structure
2412  * @mem:  pointer to mem struct to free
2413  **/
2414 enum i40e_status_code
2415 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2416                      struct i40e_virt_mem *mem)
2417 {
2418         if (!mem)
2419                 return I40E_ERR_PARAM;
2420
2421         rte_free(mem->va);
2422         mem->va = NULL;
2423
2424         return I40E_SUCCESS;
2425 }
2426
2427 void
2428 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2429 {
2430         rte_spinlock_init(&sp->spinlock);
2431 }
2432
2433 void
2434 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2435 {
2436         rte_spinlock_lock(&sp->spinlock);
2437 }
2438
2439 void
2440 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2441 {
2442         rte_spinlock_unlock(&sp->spinlock);
2443 }
2444
2445 void
2446 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2447 {
2448         return;
2449 }
2450
2451 /**
2452  * Get the hardware capabilities, which will be parsed
2453  * and saved into struct i40e_hw.
2454  */
2455 static int
2456 i40e_get_cap(struct i40e_hw *hw)
2457 {
2458         struct i40e_aqc_list_capabilities_element_resp *buf;
2459         uint16_t len, size = 0;
2460         int ret;
2461
2462         /* Calculate a huge enough buff for saving response data temporarily */
2463         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2464                                                 I40E_MAX_CAP_ELE_NUM;
2465         buf = rte_zmalloc("i40e", len, 0);
2466         if (!buf) {
2467                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2468                 return I40E_ERR_NO_MEMORY;
2469         }
2470
2471         /* Get, parse the capabilities and save it to hw */
2472         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2473                         i40e_aqc_opc_list_func_capabilities, NULL);
2474         if (ret != I40E_SUCCESS)
2475                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2476
2477         /* Free the temporary buffer after being used */
2478         rte_free(buf);
2479
2480         return ret;
2481 }
2482
2483 static int
2484 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2485 {
2486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2487         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2488         uint16_t sum_queues = 0, sum_vsis, left_queues;
2489
2490         /* First check if FW support SRIOV */
2491         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2492                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2493                 return -EINVAL;
2494         }
2495         /* Add the parameter init for LFC */
2496         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2497         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2498         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2499
2500         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2501         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2502         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2503         /* Allocate queues for pf */
2504         if (hw->func_caps.rss) {
2505                 pf->flags |= I40E_FLAG_RSS;
2506                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2507                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2508                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2509         } else
2510                 pf->lan_nb_qps = 1;
2511         sum_queues = pf->lan_nb_qps;
2512         /* Default VSI is not counted in */
2513         sum_vsis = 0;
2514         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2515
2516         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2517                 pf->flags |= I40E_FLAG_SRIOV;
2518                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2519                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2520                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2521                                      "max supported %u.",
2522                                      dev->pci_dev->max_vfs,
2523                                      hw->func_caps.num_vfs);
2524                         return -EINVAL;
2525                 }
2526                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2527                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2528                                      "max support %u queues.",
2529                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2530                         return -EINVAL;
2531                 }
2532                 pf->vf_num = dev->pci_dev->max_vfs;
2533                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2534                 sum_vsis   += pf->vf_num;
2535                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2536                              pf->vf_num, pf->vf_nb_qps);
2537         } else
2538                 pf->vf_num = 0;
2539
2540         if (hw->func_caps.vmdq) {
2541                 pf->flags |= I40E_FLAG_VMDQ;
2542                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2543                 pf->max_nb_vmdq_vsi = 1;
2544                 /*
2545                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2546                  * later.
2547                  */
2548                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2549                 sum_vsis += pf->max_nb_vmdq_vsi;
2550         } else {
2551                 pf->vmdq_nb_qps = 0;
2552                 pf->max_nb_vmdq_vsi = 0;
2553         }
2554         pf->nb_cfg_vmdq_vsi = 0;
2555
2556         if (hw->func_caps.fd) {
2557                 pf->flags |= I40E_FLAG_FDIR;
2558                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2559                 /**
2560                  * Each flow director consumes one VSI and one queue,
2561                  * but can't calculate out predictably here.
2562                  */
2563         }
2564
2565         if (hw->func_caps.dcb)
2566                 pf->flags |= I40E_FLAG_DCB;
2567
2568         if (sum_vsis > pf->max_num_vsi ||
2569                 sum_queues > hw->func_caps.num_rx_qp) {
2570                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2571                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2572                              pf->max_num_vsi, sum_vsis);
2573                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2574                              hw->func_caps.num_rx_qp, sum_queues);
2575                 return -EINVAL;
2576         }
2577
2578         /* Adjust VMDQ setting to support as many VMs as possible */
2579         if (pf->flags & I40E_FLAG_VMDQ) {
2580                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2581
2582                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2583                                         pf->max_num_vsi - sum_vsis);
2584
2585                 /* Limit the max VMDQ number that rte_ether that can support  */
2586                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2587                                         ETH_64_POOLS - 1);
2588
2589                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2590                                 pf->max_nb_vmdq_vsi);
2591                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2592         }
2593
2594         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2595          * cause */
2596         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2597                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2598                              sum_vsis, hw->func_caps.num_msix_vectors);
2599                 return -EINVAL;
2600         }
2601         return I40E_SUCCESS;
2602 }
2603
2604 static int
2605 i40e_pf_get_switch_config(struct i40e_pf *pf)
2606 {
2607         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2608         struct i40e_aqc_get_switch_config_resp *switch_config;
2609         struct i40e_aqc_switch_config_element_resp *element;
2610         uint16_t start_seid = 0, num_reported;
2611         int ret;
2612
2613         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2614                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2615         if (!switch_config) {
2616                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2617                 return -ENOMEM;
2618         }
2619
2620         /* Get the switch configurations */
2621         ret = i40e_aq_get_switch_config(hw, switch_config,
2622                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2623         if (ret != I40E_SUCCESS) {
2624                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2625                 goto fail;
2626         }
2627         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2628         if (num_reported != 1) { /* The number should be 1 */
2629                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2630                 goto fail;
2631         }
2632
2633         /* Parse the switch configuration elements */
2634         element = &(switch_config->element[0]);
2635         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2636                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2637                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2638         } else
2639                 PMD_DRV_LOG(INFO, "Unknown element type");
2640
2641 fail:
2642         rte_free(switch_config);
2643
2644         return ret;
2645 }
2646
2647 static int
2648 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2649                         uint32_t num)
2650 {
2651         struct pool_entry *entry;
2652
2653         if (pool == NULL || num == 0)
2654                 return -EINVAL;
2655
2656         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2657         if (entry == NULL) {
2658                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2659                 return -ENOMEM;
2660         }
2661
2662         /* queue heap initialize */
2663         pool->num_free = num;
2664         pool->num_alloc = 0;
2665         pool->base = base;
2666         LIST_INIT(&pool->alloc_list);
2667         LIST_INIT(&pool->free_list);
2668
2669         /* Initialize element  */
2670         entry->base = 0;
2671         entry->len = num;
2672
2673         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2674         return 0;
2675 }
2676
2677 static void
2678 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2679 {
2680         struct pool_entry *entry;
2681
2682         if (pool == NULL)
2683                 return;
2684
2685         LIST_FOREACH(entry, &pool->alloc_list, next) {
2686                 LIST_REMOVE(entry, next);
2687                 rte_free(entry);
2688         }
2689
2690         LIST_FOREACH(entry, &pool->free_list, next) {
2691                 LIST_REMOVE(entry, next);
2692                 rte_free(entry);
2693         }
2694
2695         pool->num_free = 0;
2696         pool->num_alloc = 0;
2697         pool->base = 0;
2698         LIST_INIT(&pool->alloc_list);
2699         LIST_INIT(&pool->free_list);
2700 }
2701
2702 static int
2703 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2704                        uint32_t base)
2705 {
2706         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2707         uint32_t pool_offset;
2708         int insert;
2709
2710         if (pool == NULL) {
2711                 PMD_DRV_LOG(ERR, "Invalid parameter");
2712                 return -EINVAL;
2713         }
2714
2715         pool_offset = base - pool->base;
2716         /* Lookup in alloc list */
2717         LIST_FOREACH(entry, &pool->alloc_list, next) {
2718                 if (entry->base == pool_offset) {
2719                         valid_entry = entry;
2720                         LIST_REMOVE(entry, next);
2721                         break;
2722                 }
2723         }
2724
2725         /* Not find, return */
2726         if (valid_entry == NULL) {
2727                 PMD_DRV_LOG(ERR, "Failed to find entry");
2728                 return -EINVAL;
2729         }
2730
2731         /**
2732          * Found it, move it to free list  and try to merge.
2733          * In order to make merge easier, always sort it by qbase.
2734          * Find adjacent prev and last entries.
2735          */
2736         prev = next = NULL;
2737         LIST_FOREACH(entry, &pool->free_list, next) {
2738                 if (entry->base > valid_entry->base) {
2739                         next = entry;
2740                         break;
2741                 }
2742                 prev = entry;
2743         }
2744
2745         insert = 0;
2746         /* Try to merge with next one*/
2747         if (next != NULL) {
2748                 /* Merge with next one */
2749                 if (valid_entry->base + valid_entry->len == next->base) {
2750                         next->base = valid_entry->base;
2751                         next->len += valid_entry->len;
2752                         rte_free(valid_entry);
2753                         valid_entry = next;
2754                         insert = 1;
2755                 }
2756         }
2757
2758         if (prev != NULL) {
2759                 /* Merge with previous one */
2760                 if (prev->base + prev->len == valid_entry->base) {
2761                         prev->len += valid_entry->len;
2762                         /* If it merge with next one, remove next node */
2763                         if (insert == 1) {
2764                                 LIST_REMOVE(valid_entry, next);
2765                                 rte_free(valid_entry);
2766                         } else {
2767                                 rte_free(valid_entry);
2768                                 insert = 1;
2769                         }
2770                 }
2771         }
2772
2773         /* Not find any entry to merge, insert */
2774         if (insert == 0) {
2775                 if (prev != NULL)
2776                         LIST_INSERT_AFTER(prev, valid_entry, next);
2777                 else if (next != NULL)
2778                         LIST_INSERT_BEFORE(next, valid_entry, next);
2779                 else /* It's empty list, insert to head */
2780                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2781         }
2782
2783         pool->num_free += valid_entry->len;
2784         pool->num_alloc -= valid_entry->len;
2785
2786         return 0;
2787 }
2788
2789 static int
2790 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2791                        uint16_t num)
2792 {
2793         struct pool_entry *entry, *valid_entry;
2794
2795         if (pool == NULL || num == 0) {
2796                 PMD_DRV_LOG(ERR, "Invalid parameter");
2797                 return -EINVAL;
2798         }
2799
2800         if (pool->num_free < num) {
2801                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2802                             num, pool->num_free);
2803                 return -ENOMEM;
2804         }
2805
2806         valid_entry = NULL;
2807         /* Lookup  in free list and find most fit one */
2808         LIST_FOREACH(entry, &pool->free_list, next) {
2809                 if (entry->len >= num) {
2810                         /* Find best one */
2811                         if (entry->len == num) {
2812                                 valid_entry = entry;
2813                                 break;
2814                         }
2815                         if (valid_entry == NULL || valid_entry->len > entry->len)
2816                                 valid_entry = entry;
2817                 }
2818         }
2819
2820         /* Not find one to satisfy the request, return */
2821         if (valid_entry == NULL) {
2822                 PMD_DRV_LOG(ERR, "No valid entry found");
2823                 return -ENOMEM;
2824         }
2825         /**
2826          * The entry have equal queue number as requested,
2827          * remove it from alloc_list.
2828          */
2829         if (valid_entry->len == num) {
2830                 LIST_REMOVE(valid_entry, next);
2831         } else {
2832                 /**
2833                  * The entry have more numbers than requested,
2834                  * create a new entry for alloc_list and minus its
2835                  * queue base and number in free_list.
2836                  */
2837                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2838                 if (entry == NULL) {
2839                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2840                                     "resource pool");
2841                         return -ENOMEM;
2842                 }
2843                 entry->base = valid_entry->base;
2844                 entry->len = num;
2845                 valid_entry->base += num;
2846                 valid_entry->len -= num;
2847                 valid_entry = entry;
2848         }
2849
2850         /* Insert it into alloc list, not sorted */
2851         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2852
2853         pool->num_free -= valid_entry->len;
2854         pool->num_alloc += valid_entry->len;
2855
2856         return (valid_entry->base + pool->base);
2857 }
2858
2859 /**
2860  * bitmap_is_subset - Check whether src2 is subset of src1
2861  **/
2862 static inline int
2863 bitmap_is_subset(uint8_t src1, uint8_t src2)
2864 {
2865         return !((src1 ^ src2) & src2);
2866 }
2867
2868 static int
2869 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2870 {
2871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2872
2873         /* If DCB is not supported, only default TC is supported */
2874         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2875                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2876                 return -EINVAL;
2877         }
2878
2879         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2880                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2881                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2882                             enabled_tcmap);
2883                 return -EINVAL;
2884         }
2885         return I40E_SUCCESS;
2886 }
2887
2888 int
2889 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2890                                 struct i40e_vsi_vlan_pvid_info *info)
2891 {
2892         struct i40e_hw *hw;
2893         struct i40e_vsi_context ctxt;
2894         uint8_t vlan_flags = 0;
2895         int ret;
2896
2897         if (vsi == NULL || info == NULL) {
2898                 PMD_DRV_LOG(ERR, "invalid parameters");
2899                 return I40E_ERR_PARAM;
2900         }
2901
2902         if (info->on) {
2903                 vsi->info.pvid = info->config.pvid;
2904                 /**
2905                  * If insert pvid is enabled, only tagged pkts are
2906                  * allowed to be sent out.
2907                  */
2908                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2909                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2910         } else {
2911                 vsi->info.pvid = 0;
2912                 if (info->config.reject.tagged == 0)
2913                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2914
2915                 if (info->config.reject.untagged == 0)
2916                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2917         }
2918         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2919                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2920         vsi->info.port_vlan_flags |= vlan_flags;
2921         vsi->info.valid_sections =
2922                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2923         memset(&ctxt, 0, sizeof(ctxt));
2924         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2925         ctxt.seid = vsi->seid;
2926
2927         hw = I40E_VSI_TO_HW(vsi);
2928         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2929         if (ret != I40E_SUCCESS)
2930                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2931
2932         return ret;
2933 }
2934
2935 static int
2936 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2937 {
2938         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2939         int i, ret;
2940         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2941
2942         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2943         if (ret != I40E_SUCCESS)
2944                 return ret;
2945
2946         if (!vsi->seid) {
2947                 PMD_DRV_LOG(ERR, "seid not valid");
2948                 return -EINVAL;
2949         }
2950
2951         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2952         tc_bw_data.tc_valid_bits = enabled_tcmap;
2953         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2954                 tc_bw_data.tc_bw_credits[i] =
2955                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2956
2957         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2958         if (ret != I40E_SUCCESS) {
2959                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2960                 return ret;
2961         }
2962
2963         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2964                                         sizeof(vsi->info.qs_handle));
2965         return I40E_SUCCESS;
2966 }
2967
2968 static int
2969 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2970                                  struct i40e_aqc_vsi_properties_data *info,
2971                                  uint8_t enabled_tcmap)
2972 {
2973         int ret, i, total_tc = 0;
2974         uint16_t qpnum_per_tc, bsf, qp_idx;
2975
2976         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2977         if (ret != I40E_SUCCESS)
2978                 return ret;
2979
2980         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2981                 if (enabled_tcmap & (1 << i))
2982                         total_tc++;
2983         vsi->enabled_tc = enabled_tcmap;
2984
2985         /* Number of queues per enabled TC */
2986         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2987         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2988         bsf = rte_bsf32(qpnum_per_tc);
2989
2990         /* Adjust the queue number to actual queues that can be applied */
2991         vsi->nb_qps = qpnum_per_tc * total_tc;
2992
2993         /**
2994          * Configure TC and queue mapping parameters, for enabled TC,
2995          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2996          * default queue will serve it.
2997          */
2998         qp_idx = 0;
2999         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3000                 if (vsi->enabled_tc & (1 << i)) {
3001                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3002                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3003                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3004                         qp_idx += qpnum_per_tc;
3005                 } else
3006                         info->tc_mapping[i] = 0;
3007         }
3008
3009         /* Associate queue number with VSI */
3010         if (vsi->type == I40E_VSI_SRIOV) {
3011                 info->mapping_flags |=
3012                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3013                 for (i = 0; i < vsi->nb_qps; i++)
3014                         info->queue_mapping[i] =
3015                                 rte_cpu_to_le_16(vsi->base_queue + i);
3016         } else {
3017                 info->mapping_flags |=
3018                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3019                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3020         }
3021         info->valid_sections |=
3022                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3023
3024         return I40E_SUCCESS;
3025 }
3026
3027 static int
3028 i40e_veb_release(struct i40e_veb *veb)
3029 {
3030         struct i40e_vsi *vsi;
3031         struct i40e_hw *hw;
3032
3033         if (veb == NULL || veb->associate_vsi == NULL)
3034                 return -EINVAL;
3035
3036         if (!TAILQ_EMPTY(&veb->head)) {
3037                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3038                 return -EACCES;
3039         }
3040
3041         vsi = veb->associate_vsi;
3042         hw = I40E_VSI_TO_HW(vsi);
3043
3044         vsi->uplink_seid = veb->uplink_seid;
3045         i40e_aq_delete_element(hw, veb->seid, NULL);
3046         rte_free(veb);
3047         vsi->veb = NULL;
3048         return I40E_SUCCESS;
3049 }
3050
3051 /* Setup a veb */
3052 static struct i40e_veb *
3053 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3054 {
3055         struct i40e_veb *veb;
3056         int ret;
3057         struct i40e_hw *hw;
3058
3059         if (NULL == pf || vsi == NULL) {
3060                 PMD_DRV_LOG(ERR, "veb setup failed, "
3061                             "associated VSI shouldn't null");
3062                 return NULL;
3063         }
3064         hw = I40E_PF_TO_HW(pf);
3065
3066         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3067         if (!veb) {
3068                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3069                 goto fail;
3070         }
3071
3072         veb->associate_vsi = vsi;
3073         TAILQ_INIT(&veb->head);
3074         veb->uplink_seid = vsi->uplink_seid;
3075
3076         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3077                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3078
3079         if (ret != I40E_SUCCESS) {
3080                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3081                             hw->aq.asq_last_status);
3082                 goto fail;
3083         }
3084
3085         /* get statistics index */
3086         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3087                                 &veb->stats_idx, NULL, NULL, NULL);
3088         if (ret != I40E_SUCCESS) {
3089                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3090                             hw->aq.asq_last_status);
3091                 goto fail;
3092         }
3093
3094         /* Get VEB bandwidth, to be implemented */
3095         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3096         vsi->uplink_seid = veb->seid;
3097
3098         return veb;
3099 fail:
3100         rte_free(veb);
3101         return NULL;
3102 }
3103
3104 int
3105 i40e_vsi_release(struct i40e_vsi *vsi)
3106 {
3107         struct i40e_pf *pf;
3108         struct i40e_hw *hw;
3109         struct i40e_vsi_list *vsi_list;
3110         int ret;
3111         struct i40e_mac_filter *f;
3112
3113         if (!vsi)
3114                 return I40E_SUCCESS;
3115
3116         pf = I40E_VSI_TO_PF(vsi);
3117         hw = I40E_VSI_TO_HW(vsi);
3118
3119         /* VSI has child to attach, release child first */
3120         if (vsi->veb) {
3121                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3122                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3123                                 return -1;
3124                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3125                 }
3126                 i40e_veb_release(vsi->veb);
3127         }
3128
3129         /* Remove all macvlan filters of the VSI */
3130         i40e_vsi_remove_all_macvlan_filter(vsi);
3131         TAILQ_FOREACH(f, &vsi->mac_list, next)
3132                 rte_free(f);
3133
3134         if (vsi->type != I40E_VSI_MAIN) {
3135                 /* Remove vsi from parent's sibling list */
3136                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3137                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3138                         return I40E_ERR_PARAM;
3139                 }
3140                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3141                                 &vsi->sib_vsi_list, list);
3142
3143                 /* Remove all switch element of the VSI */
3144                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3145                 if (ret != I40E_SUCCESS)
3146                         PMD_DRV_LOG(ERR, "Failed to delete element");
3147         }
3148         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3149
3150         if (vsi->type != I40E_VSI_SRIOV)
3151                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3152         rte_free(vsi);
3153
3154         return I40E_SUCCESS;
3155 }
3156
3157 static int
3158 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3159 {
3160         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3161         struct i40e_aqc_remove_macvlan_element_data def_filter;
3162         struct i40e_mac_filter_info filter;
3163         int ret;
3164
3165         if (vsi->type != I40E_VSI_MAIN)
3166                 return I40E_ERR_CONFIG;
3167         memset(&def_filter, 0, sizeof(def_filter));
3168         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3169                                         ETH_ADDR_LEN);
3170         def_filter.vlan_tag = 0;
3171         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3172                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3173         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3174         if (ret != I40E_SUCCESS) {
3175                 struct i40e_mac_filter *f;
3176                 struct ether_addr *mac;
3177
3178                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3179                             "macvlan filter");
3180                 /* It needs to add the permanent mac into mac list */
3181                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3182                 if (f == NULL) {
3183                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3184                         return I40E_ERR_NO_MEMORY;
3185                 }
3186                 mac = &f->mac_info.mac_addr;
3187                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3188                                 ETH_ADDR_LEN);
3189                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3190                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3191                 vsi->mac_num++;
3192
3193                 return ret;
3194         }
3195         (void)rte_memcpy(&filter.mac_addr,
3196                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3197         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3198         return i40e_vsi_add_mac(vsi, &filter);
3199 }
3200
3201 static int
3202 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3203 {
3204         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3205         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3206         struct i40e_hw *hw = &vsi->adapter->hw;
3207         i40e_status ret;
3208         int i;
3209
3210         memset(&bw_config, 0, sizeof(bw_config));
3211         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3212         if (ret != I40E_SUCCESS) {
3213                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3214                             hw->aq.asq_last_status);
3215                 return ret;
3216         }
3217
3218         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3219         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3220                                         &ets_sla_config, NULL);
3221         if (ret != I40E_SUCCESS) {
3222                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3223                             "configuration %u", hw->aq.asq_last_status);
3224                 return ret;
3225         }
3226
3227         /* Not store the info yet, just print out */
3228         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3229         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3230         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3231                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3232                             ets_sla_config.share_credits[i]);
3233                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3234                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3235                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3236                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3237                             (i * 4));
3238         }
3239
3240         return 0;
3241 }
3242
3243 /* Setup a VSI */
3244 struct i40e_vsi *
3245 i40e_vsi_setup(struct i40e_pf *pf,
3246                enum i40e_vsi_type type,
3247                struct i40e_vsi *uplink_vsi,
3248                uint16_t user_param)
3249 {
3250         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3251         struct i40e_vsi *vsi;
3252         struct i40e_mac_filter_info filter;
3253         int ret;
3254         struct i40e_vsi_context ctxt;
3255         struct ether_addr broadcast =
3256                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3257
3258         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3259                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3260                             "VSI link shouldn't be NULL");
3261                 return NULL;
3262         }
3263
3264         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3265                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3266                             "uplink VSI should be NULL");
3267                 return NULL;
3268         }
3269
3270         /* If uplink vsi didn't setup VEB, create one first */
3271         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3272                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3273
3274                 if (NULL == uplink_vsi->veb) {
3275                         PMD_DRV_LOG(ERR, "VEB setup failed");
3276                         return NULL;
3277                 }
3278         }
3279
3280         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3281         if (!vsi) {
3282                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3283                 return NULL;
3284         }
3285         TAILQ_INIT(&vsi->mac_list);
3286         vsi->type = type;
3287         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3288         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3289         vsi->parent_vsi = uplink_vsi;
3290         vsi->user_param = user_param;
3291         /* Allocate queues */
3292         switch (vsi->type) {
3293         case I40E_VSI_MAIN  :
3294                 vsi->nb_qps = pf->lan_nb_qps;
3295                 break;
3296         case I40E_VSI_SRIOV :
3297                 vsi->nb_qps = pf->vf_nb_qps;
3298                 break;
3299         case I40E_VSI_VMDQ2:
3300                 vsi->nb_qps = pf->vmdq_nb_qps;
3301                 break;
3302         case I40E_VSI_FDIR:
3303                 vsi->nb_qps = pf->fdir_nb_qps;
3304                 break;
3305         default:
3306                 goto fail_mem;
3307         }
3308         /*
3309          * The filter status descriptor is reported in rx queue 0,
3310          * while the tx queue for fdir filter programming has no
3311          * such constraints, can be non-zero queues.
3312          * To simplify it, choose FDIR vsi use queue 0 pair.
3313          * To make sure it will use queue 0 pair, queue allocation
3314          * need be done before this function is called
3315          */
3316         if (type != I40E_VSI_FDIR) {
3317                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3318                         if (ret < 0) {
3319                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3320                                                 vsi->seid, ret);
3321                                 goto fail_mem;
3322                         }
3323                         vsi->base_queue = ret;
3324         } else
3325                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3326
3327         /* VF has MSIX interrupt in VF range, don't allocate here */
3328         if (type != I40E_VSI_SRIOV) {
3329                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3330                 if (ret < 0) {
3331                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3332                         goto fail_queue_alloc;
3333                 }
3334                 vsi->msix_intr = ret;
3335         } else
3336                 vsi->msix_intr = 0;
3337         /* Add VSI */
3338         if (type == I40E_VSI_MAIN) {
3339                 /* For main VSI, no need to add since it's default one */
3340                 vsi->uplink_seid = pf->mac_seid;
3341                 vsi->seid = pf->main_vsi_seid;
3342                 /* Bind queues with specific MSIX interrupt */
3343                 /**
3344                  * Needs 2 interrupt at least, one for misc cause which will
3345                  * enabled from OS side, Another for queues binding the
3346                  * interrupt from device side only.
3347                  */
3348
3349                 /* Get default VSI parameters from hardware */
3350                 memset(&ctxt, 0, sizeof(ctxt));
3351                 ctxt.seid = vsi->seid;
3352                 ctxt.pf_num = hw->pf_id;
3353                 ctxt.uplink_seid = vsi->uplink_seid;
3354                 ctxt.vf_num = 0;
3355                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3356                 if (ret != I40E_SUCCESS) {
3357                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3358                         goto fail_msix_alloc;
3359                 }
3360                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3361                         sizeof(struct i40e_aqc_vsi_properties_data));
3362                 vsi->vsi_id = ctxt.vsi_number;
3363                 vsi->info.valid_sections = 0;
3364
3365                 /* Configure tc, enabled TC0 only */
3366                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3367                         I40E_SUCCESS) {
3368                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3369                         goto fail_msix_alloc;
3370                 }
3371
3372                 /* TC, queue mapping */
3373                 memset(&ctxt, 0, sizeof(ctxt));
3374                 vsi->info.valid_sections |=
3375                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3376                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3377                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3378                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3379                         sizeof(struct i40e_aqc_vsi_properties_data));
3380                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3381                                                 I40E_DEFAULT_TCMAP);
3382                 if (ret != I40E_SUCCESS) {
3383                         PMD_DRV_LOG(ERR, "Failed to configure "
3384                                     "TC queue mapping");
3385                         goto fail_msix_alloc;
3386                 }
3387                 ctxt.seid = vsi->seid;
3388                 ctxt.pf_num = hw->pf_id;
3389                 ctxt.uplink_seid = vsi->uplink_seid;
3390                 ctxt.vf_num = 0;
3391
3392                 /* Update VSI parameters */
3393                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3394                 if (ret != I40E_SUCCESS) {
3395                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3396                         goto fail_msix_alloc;
3397                 }
3398
3399                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3400                                                 sizeof(vsi->info.tc_mapping));
3401                 (void)rte_memcpy(&vsi->info.queue_mapping,
3402                                 &ctxt.info.queue_mapping,
3403                         sizeof(vsi->info.queue_mapping));
3404                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3405                 vsi->info.valid_sections = 0;
3406
3407                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3408                                 ETH_ADDR_LEN);
3409
3410                 /**
3411                  * Updating default filter settings are necessary to prevent
3412                  * reception of tagged packets.
3413                  * Some old firmware configurations load a default macvlan
3414                  * filter which accepts both tagged and untagged packets.
3415                  * The updating is to use a normal filter instead if needed.
3416                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3417                  * The firmware with correct configurations load the default
3418                  * macvlan filter which is expected and cannot be removed.
3419                  */
3420                 i40e_update_default_filter_setting(vsi);
3421                 i40e_config_qinq(hw, vsi);
3422         } else if (type == I40E_VSI_SRIOV) {
3423                 memset(&ctxt, 0, sizeof(ctxt));
3424                 /**
3425                  * For other VSI, the uplink_seid equals to uplink VSI's
3426                  * uplink_seid since they share same VEB
3427                  */
3428                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3429                 ctxt.pf_num = hw->pf_id;
3430                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3431                 ctxt.uplink_seid = vsi->uplink_seid;
3432                 ctxt.connection_type = 0x1;
3433                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3434
3435                 /**
3436                  * Do not configure switch ID to enable VEB switch by
3437                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3438                  * if the source mac address of packet sent from VF is not
3439                  * listed in the VEB's mac table, the VEB will switch the
3440                  * packet back to the VF. Need to enable it when HW issue
3441                  * is fixed.
3442                  */
3443
3444                 /* Configure port/vlan */
3445                 ctxt.info.valid_sections |=
3446                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3447                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3448                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3449                                                 I40E_DEFAULT_TCMAP);
3450                 if (ret != I40E_SUCCESS) {
3451                         PMD_DRV_LOG(ERR, "Failed to configure "
3452                                     "TC queue mapping");
3453                         goto fail_msix_alloc;
3454                 }
3455                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3456                 ctxt.info.valid_sections |=
3457                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3458                 /**
3459                  * Since VSI is not created yet, only configure parameter,
3460                  * will add vsi below.
3461                  */
3462
3463                 i40e_config_qinq(hw, vsi);
3464         } else if (type == I40E_VSI_VMDQ2) {
3465                 memset(&ctxt, 0, sizeof(ctxt));
3466                 /*
3467                  * For other VSI, the uplink_seid equals to uplink VSI's
3468                  * uplink_seid since they share same VEB
3469                  */
3470                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3471                 ctxt.pf_num = hw->pf_id;
3472                 ctxt.vf_num = 0;
3473                 ctxt.uplink_seid = vsi->uplink_seid;
3474                 ctxt.connection_type = 0x1;
3475                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3476
3477                 ctxt.info.valid_sections |=
3478                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3479                 /* user_param carries flag to enable loop back */
3480                 if (user_param) {
3481                         ctxt.info.switch_id =
3482                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3483                         ctxt.info.switch_id |=
3484                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3485                 }
3486
3487                 /* Configure port/vlan */
3488                 ctxt.info.valid_sections |=
3489                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3490                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3491                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3492                                                 I40E_DEFAULT_TCMAP);
3493                 if (ret != I40E_SUCCESS) {
3494                         PMD_DRV_LOG(ERR, "Failed to configure "
3495                                         "TC queue mapping");
3496                         goto fail_msix_alloc;
3497                 }
3498                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3499                 ctxt.info.valid_sections |=
3500                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3501         } else if (type == I40E_VSI_FDIR) {
3502                 memset(&ctxt, 0, sizeof(ctxt));
3503                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3504                 ctxt.pf_num = hw->pf_id;
3505                 ctxt.vf_num = 0;
3506                 ctxt.uplink_seid = vsi->uplink_seid;
3507                 ctxt.connection_type = 0x1;     /* regular data port */
3508                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3509                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3510                                                 I40E_DEFAULT_TCMAP);
3511                 if (ret != I40E_SUCCESS) {
3512                         PMD_DRV_LOG(ERR, "Failed to configure "
3513                                         "TC queue mapping.");
3514                         goto fail_msix_alloc;
3515                 }
3516                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3517                 ctxt.info.valid_sections |=
3518                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3519         } else {
3520                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3521                 goto fail_msix_alloc;
3522         }
3523
3524         if (vsi->type != I40E_VSI_MAIN) {
3525                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3526                 if (ret != I40E_SUCCESS) {
3527                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3528                                     hw->aq.asq_last_status);
3529                         goto fail_msix_alloc;
3530                 }
3531                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3532                 vsi->info.valid_sections = 0;
3533                 vsi->seid = ctxt.seid;
3534                 vsi->vsi_id = ctxt.vsi_number;
3535                 vsi->sib_vsi_list.vsi = vsi;
3536                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3537                                 &vsi->sib_vsi_list, list);
3538         }
3539
3540         /* MAC/VLAN configuration */
3541         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3542         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3543
3544         ret = i40e_vsi_add_mac(vsi, &filter);
3545         if (ret != I40E_SUCCESS) {
3546                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3547                 goto fail_msix_alloc;
3548         }
3549
3550         /* Get VSI BW information */
3551         i40e_vsi_dump_bw_config(vsi);
3552         return vsi;
3553 fail_msix_alloc:
3554         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3555 fail_queue_alloc:
3556         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3557 fail_mem:
3558         rte_free(vsi);
3559         return NULL;
3560 }
3561
3562 /* Configure vlan stripping on or off */
3563 int
3564 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3565 {
3566         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3567         struct i40e_vsi_context ctxt;
3568         uint8_t vlan_flags;
3569         int ret = I40E_SUCCESS;
3570
3571         /* Check if it has been already on or off */
3572         if (vsi->info.valid_sections &
3573                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3574                 if (on) {
3575                         if ((vsi->info.port_vlan_flags &
3576                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3577                                 return 0; /* already on */
3578                 } else {
3579                         if ((vsi->info.port_vlan_flags &
3580                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3581                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3582                                 return 0; /* already off */
3583                 }
3584         }
3585
3586         if (on)
3587                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3588         else
3589                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3590         vsi->info.valid_sections =
3591                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3592         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3593         vsi->info.port_vlan_flags |= vlan_flags;
3594         ctxt.seid = vsi->seid;
3595         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3596         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3597         if (ret)
3598                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3599                             on ? "enable" : "disable");
3600
3601         return ret;
3602 }
3603
3604 static int
3605 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3606 {
3607         struct rte_eth_dev_data *data = dev->data;
3608         int ret;
3609
3610         /* Apply vlan offload setting */
3611         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3612
3613         /* Apply double-vlan setting, not implemented yet */
3614
3615         /* Apply pvid setting */
3616         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3617                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3618         if (ret)
3619                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3620
3621         return ret;
3622 }
3623
3624 static int
3625 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3626 {
3627         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3628
3629         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3630 }
3631
3632 static int
3633 i40e_update_flow_control(struct i40e_hw *hw)
3634 {
3635 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3636         struct i40e_link_status link_status;
3637         uint32_t rxfc = 0, txfc = 0, reg;
3638         uint8_t an_info;
3639         int ret;
3640
3641         memset(&link_status, 0, sizeof(link_status));
3642         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3643         if (ret != I40E_SUCCESS) {
3644                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3645                 goto write_reg; /* Disable flow control */
3646         }
3647
3648         an_info = hw->phy.link_info.an_info;
3649         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3650                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3651                 ret = I40E_ERR_NOT_READY;
3652                 goto write_reg; /* Disable flow control */
3653         }
3654         /**
3655          * If link auto negotiation is enabled, flow control needs to
3656          * be configured according to it
3657          */
3658         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3659         case I40E_LINK_PAUSE_RXTX:
3660                 rxfc = 1;
3661                 txfc = 1;
3662                 hw->fc.current_mode = I40E_FC_FULL;
3663                 break;
3664         case I40E_AQ_LINK_PAUSE_RX:
3665                 rxfc = 1;
3666                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3667                 break;
3668         case I40E_AQ_LINK_PAUSE_TX:
3669                 txfc = 1;
3670                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3671                 break;
3672         default:
3673                 hw->fc.current_mode = I40E_FC_NONE;
3674                 break;
3675         }
3676
3677 write_reg:
3678         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3679                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3680         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3681         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3682         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3683         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3684
3685         return ret;
3686 }
3687
3688 /* PF setup */
3689 static int
3690 i40e_pf_setup(struct i40e_pf *pf)
3691 {
3692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3693         struct i40e_filter_control_settings settings;
3694         struct i40e_vsi *vsi;
3695         int ret;
3696
3697         /* Clear all stats counters */
3698         pf->offset_loaded = FALSE;
3699         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3700         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3701
3702         ret = i40e_pf_get_switch_config(pf);
3703         if (ret != I40E_SUCCESS) {
3704                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3705                 return ret;
3706         }
3707         if (pf->flags & I40E_FLAG_FDIR) {
3708                 /* make queue allocated first, let FDIR use queue pair 0*/
3709                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3710                 if (ret != I40E_FDIR_QUEUE_ID) {
3711                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3712                                     " ret =%d", ret);
3713                         pf->flags &= ~I40E_FLAG_FDIR;
3714                 }
3715         }
3716         /*  main VSI setup */
3717         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3718         if (!vsi) {
3719                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3720                 return I40E_ERR_NOT_READY;
3721         }
3722         pf->main_vsi = vsi;
3723
3724         /* Configure filter control */
3725         memset(&settings, 0, sizeof(settings));
3726         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3727                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3728         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3729                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3730         else {
3731                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3732                                                 hw->func_caps.rss_table_size);
3733                 return I40E_ERR_PARAM;
3734         }
3735         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3736                         "size: %u\n", hw->func_caps.rss_table_size);
3737         pf->hash_lut_size = hw->func_caps.rss_table_size;
3738
3739         /* Enable ethtype and macvlan filters */
3740         settings.enable_ethtype = TRUE;
3741         settings.enable_macvlan = TRUE;
3742         ret = i40e_set_filter_control(hw, &settings);
3743         if (ret)
3744                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3745                                                                 ret);
3746
3747         /* Update flow control according to the auto negotiation */
3748         i40e_update_flow_control(hw);
3749
3750         return I40E_SUCCESS;
3751 }
3752
3753 int
3754 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3755 {
3756         uint32_t reg;
3757         uint16_t j;
3758
3759         /**
3760          * Set or clear TX Queue Disable flags,
3761          * which is required by hardware.
3762          */
3763         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3764         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3765
3766         /* Wait until the request is finished */
3767         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3768                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3769                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3770                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3771                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3772                                                         & 0x1))) {
3773                         break;
3774                 }
3775         }
3776         if (on) {
3777                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3778                         return I40E_SUCCESS; /* already on, skip next steps */
3779
3780                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3781                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3782         } else {
3783                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3784                         return I40E_SUCCESS; /* already off, skip next steps */
3785                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3786         }
3787         /* Write the register */
3788         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3789         /* Check the result */
3790         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3791                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3792                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3793                 if (on) {
3794                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3795                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3796                                 break;
3797                 } else {
3798                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3799                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3800                                 break;
3801                 }
3802         }
3803         /* Check if it is timeout */
3804         if (j >= I40E_CHK_Q_ENA_COUNT) {
3805                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3806                             (on ? "enable" : "disable"), q_idx);
3807                 return I40E_ERR_TIMEOUT;
3808         }
3809
3810         return I40E_SUCCESS;
3811 }
3812
3813 /* Swith on or off the tx queues */
3814 static int
3815 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3816 {
3817         struct rte_eth_dev_data *dev_data = pf->dev_data;
3818         struct i40e_tx_queue *txq;
3819         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3820         uint16_t i;
3821         int ret;
3822
3823         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3824                 txq = dev_data->tx_queues[i];
3825                 /* Don't operate the queue if not configured or
3826                  * if starting only per queue */
3827                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3828                         continue;
3829                 if (on)
3830                         ret = i40e_dev_tx_queue_start(dev, i);
3831                 else
3832                         ret = i40e_dev_tx_queue_stop(dev, i);
3833                 if ( ret != I40E_SUCCESS)
3834                         return ret;
3835         }
3836
3837         return I40E_SUCCESS;
3838 }
3839
3840 int
3841 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3842 {
3843         uint32_t reg;
3844         uint16_t j;
3845
3846         /* Wait until the request is finished */
3847         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3848                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3849                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3850                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3851                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3852                         break;
3853         }
3854
3855         if (on) {
3856                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3857                         return I40E_SUCCESS; /* Already on, skip next steps */
3858                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3859         } else {
3860                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3861                         return I40E_SUCCESS; /* Already off, skip next steps */
3862                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3863         }
3864
3865         /* Write the register */
3866         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3867         /* Check the result */
3868         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3869                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3870                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3871                 if (on) {
3872                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3873                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3874                                 break;
3875                 } else {
3876                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3877                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3878                                 break;
3879                 }
3880         }
3881
3882         /* Check if it is timeout */
3883         if (j >= I40E_CHK_Q_ENA_COUNT) {
3884                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3885                             (on ? "enable" : "disable"), q_idx);
3886                 return I40E_ERR_TIMEOUT;
3887         }
3888
3889         return I40E_SUCCESS;
3890 }
3891 /* Switch on or off the rx queues */
3892 static int
3893 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3894 {
3895         struct rte_eth_dev_data *dev_data = pf->dev_data;
3896         struct i40e_rx_queue *rxq;
3897         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3898         uint16_t i;
3899         int ret;
3900
3901         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3902                 rxq = dev_data->rx_queues[i];
3903                 /* Don't operate the queue if not configured or
3904                  * if starting only per queue */
3905                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3906                         continue;
3907                 if (on)
3908                         ret = i40e_dev_rx_queue_start(dev, i);
3909                 else
3910                         ret = i40e_dev_rx_queue_stop(dev, i);
3911                 if (ret != I40E_SUCCESS)
3912                         return ret;
3913         }
3914
3915         return I40E_SUCCESS;
3916 }
3917
3918 /* Switch on or off all the rx/tx queues */
3919 int
3920 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3921 {
3922         int ret;
3923
3924         if (on) {
3925                 /* enable rx queues before enabling tx queues */
3926                 ret = i40e_dev_switch_rx_queues(pf, on);
3927                 if (ret) {
3928                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3929                         return ret;
3930                 }
3931                 ret = i40e_dev_switch_tx_queues(pf, on);
3932         } else {
3933                 /* Stop tx queues before stopping rx queues */
3934                 ret = i40e_dev_switch_tx_queues(pf, on);
3935                 if (ret) {
3936                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3937                         return ret;
3938                 }
3939                 ret = i40e_dev_switch_rx_queues(pf, on);
3940         }
3941
3942         return ret;
3943 }
3944
3945 /* Initialize VSI for TX */
3946 static int
3947 i40e_dev_tx_init(struct i40e_pf *pf)
3948 {
3949         struct rte_eth_dev_data *data = pf->dev_data;
3950         uint16_t i;
3951         uint32_t ret = I40E_SUCCESS;
3952         struct i40e_tx_queue *txq;
3953
3954         for (i = 0; i < data->nb_tx_queues; i++) {
3955                 txq = data->tx_queues[i];
3956                 if (!txq || !txq->q_set)
3957                         continue;
3958                 ret = i40e_tx_queue_init(txq);
3959                 if (ret != I40E_SUCCESS)
3960                         break;
3961         }
3962         if (ret == I40E_SUCCESS)
3963                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
3964                                      ->eth_dev);
3965
3966         return ret;
3967 }
3968
3969 /* Initialize VSI for RX */
3970 static int
3971 i40e_dev_rx_init(struct i40e_pf *pf)
3972 {
3973         struct rte_eth_dev_data *data = pf->dev_data;
3974         int ret = I40E_SUCCESS;
3975         uint16_t i;
3976         struct i40e_rx_queue *rxq;
3977
3978         i40e_pf_config_mq_rx(pf);
3979         for (i = 0; i < data->nb_rx_queues; i++) {
3980                 rxq = data->rx_queues[i];
3981                 if (!rxq || !rxq->q_set)
3982                         continue;
3983
3984                 ret = i40e_rx_queue_init(rxq);
3985                 if (ret != I40E_SUCCESS) {
3986                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3987                                     "initialization");
3988                         break;
3989                 }
3990         }
3991         if (ret == I40E_SUCCESS)
3992                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
3993                                      ->eth_dev);
3994
3995         return ret;
3996 }
3997
3998 static int
3999 i40e_dev_rxtx_init(struct i40e_pf *pf)
4000 {
4001         int err;
4002
4003         err = i40e_dev_tx_init(pf);
4004         if (err) {
4005                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4006                 return err;
4007         }
4008         err = i40e_dev_rx_init(pf);
4009         if (err) {
4010                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4011                 return err;
4012         }
4013
4014         return err;
4015 }
4016
4017 static int
4018 i40e_vmdq_setup(struct rte_eth_dev *dev)
4019 {
4020         struct rte_eth_conf *conf = &dev->data->dev_conf;
4021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4022         int i, err, conf_vsis, j, loop;
4023         struct i40e_vsi *vsi;
4024         struct i40e_vmdq_info *vmdq_info;
4025         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4026         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4027
4028         /*
4029          * Disable interrupt to avoid message from VF. Furthermore, it will
4030          * avoid race condition in VSI creation/destroy.
4031          */
4032         i40e_pf_disable_irq0(hw);
4033
4034         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4035                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4036                 return -ENOTSUP;
4037         }
4038
4039         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4040         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4041                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4042                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4043                         pf->max_nb_vmdq_vsi);
4044                 return -ENOTSUP;
4045         }
4046
4047         if (pf->vmdq != NULL) {
4048                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4049                 return 0;
4050         }
4051
4052         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4053                                 sizeof(*vmdq_info) * conf_vsis, 0);
4054
4055         if (pf->vmdq == NULL) {
4056                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4057                 return -ENOMEM;
4058         }
4059
4060         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4061
4062         /* Create VMDQ VSI */
4063         for (i = 0; i < conf_vsis; i++) {
4064                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4065                                 vmdq_conf->enable_loop_back);
4066                 if (vsi == NULL) {
4067                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4068                         err = -1;
4069                         goto err_vsi_setup;
4070                 }
4071                 vmdq_info = &pf->vmdq[i];
4072                 vmdq_info->pf = pf;
4073                 vmdq_info->vsi = vsi;
4074         }
4075         pf->nb_cfg_vmdq_vsi = conf_vsis;
4076
4077         /* Configure Vlan */
4078         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4079         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4080                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4081                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4082                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4083                                         vmdq_conf->pool_map[i].vlan_id, j);
4084
4085                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4086                                                 vmdq_conf->pool_map[i].vlan_id);
4087                                 if (err) {
4088                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4089                                         err = -1;
4090                                         goto err_vsi_setup;
4091                                 }
4092                         }
4093                 }
4094         }
4095
4096         i40e_pf_enable_irq0(hw);
4097
4098         return 0;
4099
4100 err_vsi_setup:
4101         for (i = 0; i < conf_vsis; i++)
4102                 if (pf->vmdq[i].vsi == NULL)
4103                         break;
4104                 else
4105                         i40e_vsi_release(pf->vmdq[i].vsi);
4106
4107         rte_free(pf->vmdq);
4108         pf->vmdq = NULL;
4109         i40e_pf_enable_irq0(hw);
4110         return err;
4111 }
4112
4113 static void
4114 i40e_stat_update_32(struct i40e_hw *hw,
4115                    uint32_t reg,
4116                    bool offset_loaded,
4117                    uint64_t *offset,
4118                    uint64_t *stat)
4119 {
4120         uint64_t new_data;
4121
4122         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4123         if (!offset_loaded)
4124                 *offset = new_data;
4125
4126         if (new_data >= *offset)
4127                 *stat = (uint64_t)(new_data - *offset);
4128         else
4129                 *stat = (uint64_t)((new_data +
4130                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4131 }
4132
4133 static void
4134 i40e_stat_update_48(struct i40e_hw *hw,
4135                    uint32_t hireg,
4136                    uint32_t loreg,
4137                    bool offset_loaded,
4138                    uint64_t *offset,
4139                    uint64_t *stat)
4140 {
4141         uint64_t new_data;
4142
4143         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4144         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4145                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4146
4147         if (!offset_loaded)
4148                 *offset = new_data;
4149
4150         if (new_data >= *offset)
4151                 *stat = new_data - *offset;
4152         else
4153                 *stat = (uint64_t)((new_data +
4154                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4155
4156         *stat &= I40E_48_BIT_MASK;
4157 }
4158
4159 /* Disable IRQ0 */
4160 void
4161 i40e_pf_disable_irq0(struct i40e_hw *hw)
4162 {
4163         /* Disable all interrupt types */
4164         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4165         I40E_WRITE_FLUSH(hw);
4166 }
4167
4168 /* Enable IRQ0 */
4169 void
4170 i40e_pf_enable_irq0(struct i40e_hw *hw)
4171 {
4172         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4173                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4174                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4175                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4176         I40E_WRITE_FLUSH(hw);
4177 }
4178
4179 static void
4180 i40e_pf_config_irq0(struct i40e_hw *hw)
4181 {
4182         /* read pending request and disable first */
4183         i40e_pf_disable_irq0(hw);
4184         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4185         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4186                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4187
4188         /* Link no queues with irq0 */
4189         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4190                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4191 }
4192
4193 static void
4194 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4195 {
4196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4198         int i;
4199         uint16_t abs_vf_id;
4200         uint32_t index, offset, val;
4201
4202         if (!pf->vfs)
4203                 return;
4204         /**
4205          * Try to find which VF trigger a reset, use absolute VF id to access
4206          * since the reg is global register.
4207          */
4208         for (i = 0; i < pf->vf_num; i++) {
4209                 abs_vf_id = hw->func_caps.vf_base_id + i;
4210                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4211                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4212                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4213                 /* VFR event occured */
4214                 if (val & (0x1 << offset)) {
4215                         int ret;
4216
4217                         /* Clear the event first */
4218                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4219                                                         (0x1 << offset));
4220                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4221                         /**
4222                          * Only notify a VF reset event occured,
4223                          * don't trigger another SW reset
4224                          */
4225                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4226                         if (ret != I40E_SUCCESS)
4227                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4228                 }
4229         }
4230 }
4231
4232 static void
4233 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4234 {
4235         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4236         struct i40e_arq_event_info info;
4237         uint16_t pending, opcode;
4238         int ret;
4239
4240         info.buf_len = I40E_AQ_BUF_SZ;
4241         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4242         if (!info.msg_buf) {
4243                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4244                 return;
4245         }
4246
4247         pending = 1;
4248         while (pending) {
4249                 ret = i40e_clean_arq_element(hw, &info, &pending);
4250
4251                 if (ret != I40E_SUCCESS) {
4252                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4253                                     "aq_err: %u", hw->aq.asq_last_status);
4254                         break;
4255                 }
4256                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4257
4258                 switch (opcode) {
4259                 case i40e_aqc_opc_send_msg_to_pf:
4260                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4261                         i40e_pf_host_handle_vf_msg(dev,
4262                                         rte_le_to_cpu_16(info.desc.retval),
4263                                         rte_le_to_cpu_32(info.desc.cookie_high),
4264                                         rte_le_to_cpu_32(info.desc.cookie_low),
4265                                         info.msg_buf,
4266                                         info.msg_len);
4267                         break;
4268                 default:
4269                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4270                                     opcode);
4271                         break;
4272                 }
4273         }
4274         rte_free(info.msg_buf);
4275 }
4276
4277 /*
4278  * Interrupt handler is registered as the alarm callback for handling LSC
4279  * interrupt in a definite of time, in order to wait the NIC into a stable
4280  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4281  * no need for link down interrupt.
4282  */
4283 static void
4284 i40e_dev_interrupt_delayed_handler(void *param)
4285 {
4286         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4288         uint32_t icr0;
4289
4290         /* read interrupt causes again */
4291         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4292
4293 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4294         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4295                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4296         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4297                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4298         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4299                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4300         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4301                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4302         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4303                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4304                                                                 "state\n");
4305         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4306                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4307         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4308                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4309 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4310
4311         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4312                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4313                 i40e_dev_handle_vfr_event(dev);
4314         }
4315         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4316                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4317                 i40e_dev_handle_aq_msg(dev);
4318         }
4319
4320         /* handle the link up interrupt in an alarm callback */
4321         i40e_dev_link_update(dev, 0);
4322         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4323
4324         i40e_pf_enable_irq0(hw);
4325         rte_intr_enable(&(dev->pci_dev->intr_handle));
4326 }
4327
4328 /**
4329  * Interrupt handler triggered by NIC  for handling
4330  * specific interrupt.
4331  *
4332  * @param handle
4333  *  Pointer to interrupt handle.
4334  * @param param
4335  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4336  *
4337  * @return
4338  *  void
4339  */
4340 static void
4341 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4342                            void *param)
4343 {
4344         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4345         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346         uint32_t icr0;
4347
4348         /* Disable interrupt */
4349         i40e_pf_disable_irq0(hw);
4350
4351         /* read out interrupt causes */
4352         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4353
4354         /* No interrupt event indicated */
4355         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4356                 PMD_DRV_LOG(INFO, "No interrupt event");
4357                 goto done;
4358         }
4359 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4360         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4361                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4362         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4363                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4364         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4365                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4366         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4367                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4368         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4369                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4370         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4371                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4372         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4373                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4374 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4375
4376         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4377                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4378                 i40e_dev_handle_vfr_event(dev);
4379         }
4380         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4381                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4382                 i40e_dev_handle_aq_msg(dev);
4383         }
4384
4385         /* Link Status Change interrupt */
4386         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4387 #define I40E_US_PER_SECOND 1000000
4388                 struct rte_eth_link link;
4389
4390                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4391                 memset(&link, 0, sizeof(link));
4392                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4393                 i40e_dev_link_update(dev, 0);
4394
4395                 /*
4396                  * For link up interrupt, it needs to wait 1 second to let the
4397                  * hardware be a stable state. Otherwise several consecutive
4398                  * interrupts can be observed.
4399                  * For link down interrupt, no need to wait.
4400                  */
4401                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4402                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4403                         return;
4404                 else
4405                         _rte_eth_dev_callback_process(dev,
4406                                 RTE_ETH_EVENT_INTR_LSC);
4407         }
4408
4409 done:
4410         /* Enable interrupt */
4411         i40e_pf_enable_irq0(hw);
4412         rte_intr_enable(&(dev->pci_dev->intr_handle));
4413 }
4414
4415 static int
4416 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4417                          struct i40e_macvlan_filter *filter,
4418                          int total)
4419 {
4420         int ele_num, ele_buff_size;
4421         int num, actual_num, i;
4422         uint16_t flags;
4423         int ret = I40E_SUCCESS;
4424         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4425         struct i40e_aqc_add_macvlan_element_data *req_list;
4426
4427         if (filter == NULL  || total == 0)
4428                 return I40E_ERR_PARAM;
4429         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4430         ele_buff_size = hw->aq.asq_buf_size;
4431
4432         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4433         if (req_list == NULL) {
4434                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4435                 return I40E_ERR_NO_MEMORY;
4436         }
4437
4438         num = 0;
4439         do {
4440                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4441                 memset(req_list, 0, ele_buff_size);
4442
4443                 for (i = 0; i < actual_num; i++) {
4444                         (void)rte_memcpy(req_list[i].mac_addr,
4445                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4446                         req_list[i].vlan_tag =
4447                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4448
4449                         switch (filter[num + i].filter_type) {
4450                         case RTE_MAC_PERFECT_MATCH:
4451                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4452                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4453                                 break;
4454                         case RTE_MACVLAN_PERFECT_MATCH:
4455                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4456                                 break;
4457                         case RTE_MAC_HASH_MATCH:
4458                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4459                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4460                                 break;
4461                         case RTE_MACVLAN_HASH_MATCH:
4462                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4463                                 break;
4464                         default:
4465                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4466                                 ret = I40E_ERR_PARAM;
4467                                 goto DONE;
4468                         }
4469
4470                         req_list[i].queue_number = 0;
4471
4472                         req_list[i].flags = rte_cpu_to_le_16(flags);
4473                 }
4474
4475                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4476                                                 actual_num, NULL);
4477                 if (ret != I40E_SUCCESS) {
4478                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4479                         goto DONE;
4480                 }
4481                 num += actual_num;
4482         } while (num < total);
4483
4484 DONE:
4485         rte_free(req_list);
4486         return ret;
4487 }
4488
4489 static int
4490 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4491                             struct i40e_macvlan_filter *filter,
4492                             int total)
4493 {
4494         int ele_num, ele_buff_size;
4495         int num, actual_num, i;
4496         uint16_t flags;
4497         int ret = I40E_SUCCESS;
4498         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4499         struct i40e_aqc_remove_macvlan_element_data *req_list;
4500
4501         if (filter == NULL  || total == 0)
4502                 return I40E_ERR_PARAM;
4503
4504         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4505         ele_buff_size = hw->aq.asq_buf_size;
4506
4507         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4508         if (req_list == NULL) {
4509                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4510                 return I40E_ERR_NO_MEMORY;
4511         }
4512
4513         num = 0;
4514         do {
4515                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4516                 memset(req_list, 0, ele_buff_size);
4517
4518                 for (i = 0; i < actual_num; i++) {
4519                         (void)rte_memcpy(req_list[i].mac_addr,
4520                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4521                         req_list[i].vlan_tag =
4522                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4523
4524                         switch (filter[num + i].filter_type) {
4525                         case RTE_MAC_PERFECT_MATCH:
4526                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4527                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4528                                 break;
4529                         case RTE_MACVLAN_PERFECT_MATCH:
4530                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4531                                 break;
4532                         case RTE_MAC_HASH_MATCH:
4533                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4534                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4535                                 break;
4536                         case RTE_MACVLAN_HASH_MATCH:
4537                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4538                                 break;
4539                         default:
4540                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4541                                 ret = I40E_ERR_PARAM;
4542                                 goto DONE;
4543                         }
4544                         req_list[i].flags = rte_cpu_to_le_16(flags);
4545                 }
4546
4547                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4548                                                 actual_num, NULL);
4549                 if (ret != I40E_SUCCESS) {
4550                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4551                         goto DONE;
4552                 }
4553                 num += actual_num;
4554         } while (num < total);
4555
4556 DONE:
4557         rte_free(req_list);
4558         return ret;
4559 }
4560
4561 /* Find out specific MAC filter */
4562 static struct i40e_mac_filter *
4563 i40e_find_mac_filter(struct i40e_vsi *vsi,
4564                          struct ether_addr *macaddr)
4565 {
4566         struct i40e_mac_filter *f;
4567
4568         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4569                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4570                         return f;
4571         }
4572
4573         return NULL;
4574 }
4575
4576 static bool
4577 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4578                          uint16_t vlan_id)
4579 {
4580         uint32_t vid_idx, vid_bit;
4581
4582         if (vlan_id > ETH_VLAN_ID_MAX)
4583                 return 0;
4584
4585         vid_idx = I40E_VFTA_IDX(vlan_id);
4586         vid_bit = I40E_VFTA_BIT(vlan_id);
4587
4588         if (vsi->vfta[vid_idx] & vid_bit)
4589                 return 1;
4590         else
4591                 return 0;
4592 }
4593
4594 static void
4595 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4596                          uint16_t vlan_id, bool on)
4597 {
4598         uint32_t vid_idx, vid_bit;
4599
4600         if (vlan_id > ETH_VLAN_ID_MAX)
4601                 return;
4602
4603         vid_idx = I40E_VFTA_IDX(vlan_id);
4604         vid_bit = I40E_VFTA_BIT(vlan_id);
4605
4606         if (on)
4607                 vsi->vfta[vid_idx] |= vid_bit;
4608         else
4609                 vsi->vfta[vid_idx] &= ~vid_bit;
4610 }
4611
4612 /**
4613  * Find all vlan options for specific mac addr,
4614  * return with actual vlan found.
4615  */
4616 static inline int
4617 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4618                            struct i40e_macvlan_filter *mv_f,
4619                            int num, struct ether_addr *addr)
4620 {
4621         int i;
4622         uint32_t j, k;
4623
4624         /**
4625          * Not to use i40e_find_vlan_filter to decrease the loop time,
4626          * although the code looks complex.
4627           */
4628         if (num < vsi->vlan_num)
4629                 return I40E_ERR_PARAM;
4630
4631         i = 0;
4632         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4633                 if (vsi->vfta[j]) {
4634                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4635                                 if (vsi->vfta[j] & (1 << k)) {
4636                                         if (i > num - 1) {
4637                                                 PMD_DRV_LOG(ERR, "vlan number "
4638                                                             "not match");
4639                                                 return I40E_ERR_PARAM;
4640                                         }
4641                                         (void)rte_memcpy(&mv_f[i].macaddr,
4642                                                         addr, ETH_ADDR_LEN);
4643                                         mv_f[i].vlan_id =
4644                                                 j * I40E_UINT32_BIT_SIZE + k;
4645                                         i++;
4646                                 }
4647                         }
4648                 }
4649         }
4650         return I40E_SUCCESS;
4651 }
4652
4653 static inline int
4654 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4655                            struct i40e_macvlan_filter *mv_f,
4656                            int num,
4657                            uint16_t vlan)
4658 {
4659         int i = 0;
4660         struct i40e_mac_filter *f;
4661
4662         if (num < vsi->mac_num)
4663                 return I40E_ERR_PARAM;
4664
4665         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4666                 if (i > num - 1) {
4667                         PMD_DRV_LOG(ERR, "buffer number not match");
4668                         return I40E_ERR_PARAM;
4669                 }
4670                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4671                                 ETH_ADDR_LEN);
4672                 mv_f[i].vlan_id = vlan;
4673                 mv_f[i].filter_type = f->mac_info.filter_type;
4674                 i++;
4675         }
4676
4677         return I40E_SUCCESS;
4678 }
4679
4680 static int
4681 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4682 {
4683         int i, num;
4684         struct i40e_mac_filter *f;
4685         struct i40e_macvlan_filter *mv_f;
4686         int ret = I40E_SUCCESS;
4687
4688         if (vsi == NULL || vsi->mac_num == 0)
4689                 return I40E_ERR_PARAM;
4690
4691         /* Case that no vlan is set */
4692         if (vsi->vlan_num == 0)
4693                 num = vsi->mac_num;
4694         else
4695                 num = vsi->mac_num * vsi->vlan_num;
4696
4697         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4698         if (mv_f == NULL) {
4699                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4700                 return I40E_ERR_NO_MEMORY;
4701         }
4702
4703         i = 0;
4704         if (vsi->vlan_num == 0) {
4705                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4706                         (void)rte_memcpy(&mv_f[i].macaddr,
4707                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4708                         mv_f[i].vlan_id = 0;
4709                         i++;
4710                 }
4711         } else {
4712                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4713                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4714                                         vsi->vlan_num, &f->mac_info.mac_addr);
4715                         if (ret != I40E_SUCCESS)
4716                                 goto DONE;
4717                         i += vsi->vlan_num;
4718                 }
4719         }
4720
4721         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4722 DONE:
4723         rte_free(mv_f);
4724
4725         return ret;
4726 }
4727
4728 int
4729 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4730 {
4731         struct i40e_macvlan_filter *mv_f;
4732         int mac_num;
4733         int ret = I40E_SUCCESS;
4734
4735         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4736                 return I40E_ERR_PARAM;
4737
4738         /* If it's already set, just return */
4739         if (i40e_find_vlan_filter(vsi,vlan))
4740                 return I40E_SUCCESS;
4741
4742         mac_num = vsi->mac_num;
4743
4744         if (mac_num == 0) {
4745                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4746                 return I40E_ERR_PARAM;
4747         }
4748
4749         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4750
4751         if (mv_f == NULL) {
4752                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4753                 return I40E_ERR_NO_MEMORY;
4754         }
4755
4756         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4757
4758         if (ret != I40E_SUCCESS)
4759                 goto DONE;
4760
4761         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4762
4763         if (ret != I40E_SUCCESS)
4764                 goto DONE;
4765
4766         i40e_set_vlan_filter(vsi, vlan, 1);
4767
4768         vsi->vlan_num++;
4769         ret = I40E_SUCCESS;
4770 DONE:
4771         rte_free(mv_f);
4772         return ret;
4773 }
4774
4775 int
4776 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4777 {
4778         struct i40e_macvlan_filter *mv_f;
4779         int mac_num;
4780         int ret = I40E_SUCCESS;
4781
4782         /**
4783          * Vlan 0 is the generic filter for untagged packets
4784          * and can't be removed.
4785          */
4786         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4787                 return I40E_ERR_PARAM;
4788
4789         /* If can't find it, just return */
4790         if (!i40e_find_vlan_filter(vsi, vlan))
4791                 return I40E_ERR_PARAM;
4792
4793         mac_num = vsi->mac_num;
4794
4795         if (mac_num == 0) {
4796                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4797                 return I40E_ERR_PARAM;
4798         }
4799
4800         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4801
4802         if (mv_f == NULL) {
4803                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4804                 return I40E_ERR_NO_MEMORY;
4805         }
4806
4807         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4808
4809         if (ret != I40E_SUCCESS)
4810                 goto DONE;
4811
4812         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4813
4814         if (ret != I40E_SUCCESS)
4815                 goto DONE;
4816
4817         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4818         if (vsi->vlan_num == 1) {
4819                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4820                 if (ret != I40E_SUCCESS)
4821                         goto DONE;
4822
4823                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4824                 if (ret != I40E_SUCCESS)
4825                         goto DONE;
4826         }
4827
4828         i40e_set_vlan_filter(vsi, vlan, 0);
4829
4830         vsi->vlan_num--;
4831         ret = I40E_SUCCESS;
4832 DONE:
4833         rte_free(mv_f);
4834         return ret;
4835 }
4836
4837 int
4838 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4839 {
4840         struct i40e_mac_filter *f;
4841         struct i40e_macvlan_filter *mv_f;
4842         int i, vlan_num = 0;
4843         int ret = I40E_SUCCESS;
4844
4845         /* If it's add and we've config it, return */
4846         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4847         if (f != NULL)
4848                 return I40E_SUCCESS;
4849         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4850                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4851
4852                 /**
4853                  * If vlan_num is 0, that's the first time to add mac,
4854                  * set mask for vlan_id 0.
4855                  */
4856                 if (vsi->vlan_num == 0) {
4857                         i40e_set_vlan_filter(vsi, 0, 1);
4858                         vsi->vlan_num = 1;
4859                 }
4860                 vlan_num = vsi->vlan_num;
4861         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4862                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4863                 vlan_num = 1;
4864
4865         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4866         if (mv_f == NULL) {
4867                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4868                 return I40E_ERR_NO_MEMORY;
4869         }
4870
4871         for (i = 0; i < vlan_num; i++) {
4872                 mv_f[i].filter_type = mac_filter->filter_type;
4873                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4874                                 ETH_ADDR_LEN);
4875         }
4876
4877         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4878                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4879                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4880                                         &mac_filter->mac_addr);
4881                 if (ret != I40E_SUCCESS)
4882                         goto DONE;
4883         }
4884
4885         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4886         if (ret != I40E_SUCCESS)
4887                 goto DONE;
4888
4889         /* Add the mac addr into mac list */
4890         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4891         if (f == NULL) {
4892                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4893                 ret = I40E_ERR_NO_MEMORY;
4894                 goto DONE;
4895         }
4896         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4897                         ETH_ADDR_LEN);
4898         f->mac_info.filter_type = mac_filter->filter_type;
4899         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4900         vsi->mac_num++;
4901
4902         ret = I40E_SUCCESS;
4903 DONE:
4904         rte_free(mv_f);
4905
4906         return ret;
4907 }
4908
4909 int
4910 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4911 {
4912         struct i40e_mac_filter *f;
4913         struct i40e_macvlan_filter *mv_f;
4914         int i, vlan_num;
4915         enum rte_mac_filter_type filter_type;
4916         int ret = I40E_SUCCESS;
4917
4918         /* Can't find it, return an error */
4919         f = i40e_find_mac_filter(vsi, addr);
4920         if (f == NULL)
4921                 return I40E_ERR_PARAM;
4922
4923         vlan_num = vsi->vlan_num;
4924         filter_type = f->mac_info.filter_type;
4925         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4926                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4927                 if (vlan_num == 0) {
4928                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4929                         return I40E_ERR_PARAM;
4930                 }
4931         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4932                         filter_type == RTE_MAC_HASH_MATCH)
4933                 vlan_num = 1;
4934
4935         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4936         if (mv_f == NULL) {
4937                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4938                 return I40E_ERR_NO_MEMORY;
4939         }
4940
4941         for (i = 0; i < vlan_num; i++) {
4942                 mv_f[i].filter_type = filter_type;
4943                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4944                                 ETH_ADDR_LEN);
4945         }
4946         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4947                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4948                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4949                 if (ret != I40E_SUCCESS)
4950                         goto DONE;
4951         }
4952
4953         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4954         if (ret != I40E_SUCCESS)
4955                 goto DONE;
4956
4957         /* Remove the mac addr into mac list */
4958         TAILQ_REMOVE(&vsi->mac_list, f, next);
4959         rte_free(f);
4960         vsi->mac_num--;
4961
4962         ret = I40E_SUCCESS;
4963 DONE:
4964         rte_free(mv_f);
4965         return ret;
4966 }
4967
4968 /* Configure hash enable flags for RSS */
4969 uint64_t
4970 i40e_config_hena(uint64_t flags)
4971 {
4972         uint64_t hena = 0;
4973
4974         if (!flags)
4975                 return hena;
4976
4977         if (flags & ETH_RSS_FRAG_IPV4)
4978                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4979         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4980                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4981         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4982                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4983         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4984                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4985         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4986                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4987         if (flags & ETH_RSS_FRAG_IPV6)
4988                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4989         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4990                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4991         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4992                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4993         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4994                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4995         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4996                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4997         if (flags & ETH_RSS_L2_PAYLOAD)
4998                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4999
5000         return hena;
5001 }
5002
5003 /* Parse the hash enable flags */
5004 uint64_t
5005 i40e_parse_hena(uint64_t flags)
5006 {
5007         uint64_t rss_hf = 0;
5008
5009         if (!flags)
5010                 return rss_hf;
5011         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5012                 rss_hf |= ETH_RSS_FRAG_IPV4;
5013         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5014                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5015         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5016                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5017         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5018                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5019         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5020                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5021         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5022                 rss_hf |= ETH_RSS_FRAG_IPV6;
5023         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5024                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5025         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5026                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5027         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5028                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5029         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5030                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5031         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5032                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5033
5034         return rss_hf;
5035 }
5036
5037 /* Disable RSS */
5038 static void
5039 i40e_pf_disable_rss(struct i40e_pf *pf)
5040 {
5041         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5042         uint64_t hena;
5043
5044         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5045         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5046         hena &= ~I40E_RSS_HENA_ALL;
5047         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5048         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5049         I40E_WRITE_FLUSH(hw);
5050 }
5051
5052 static int
5053 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
5054 {
5055         uint32_t *hash_key;
5056         uint8_t hash_key_len;
5057         uint64_t rss_hf;
5058         uint16_t i;
5059         uint64_t hena;
5060
5061         hash_key = (uint32_t *)(rss_conf->rss_key);
5062         hash_key_len = rss_conf->rss_key_len;
5063         if (hash_key != NULL && hash_key_len >=
5064                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5065                 /* Fill in RSS hash key */
5066                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5067                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5068         }
5069
5070         rss_hf = rss_conf->rss_hf;
5071         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5072         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5073         hena &= ~I40E_RSS_HENA_ALL;
5074         hena |= i40e_config_hena(rss_hf);
5075         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5076         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5077         I40E_WRITE_FLUSH(hw);
5078
5079         return 0;
5080 }
5081
5082 static int
5083 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5084                          struct rte_eth_rss_conf *rss_conf)
5085 {
5086         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5088         uint64_t hena;
5089
5090         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5091         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5092         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5093                 if (rss_hf != 0) /* Enable RSS */
5094                         return -EINVAL;
5095                 return 0; /* Nothing to do */
5096         }
5097         /* RSS enabled */
5098         if (rss_hf == 0) /* Disable RSS */
5099                 return -EINVAL;
5100
5101         return i40e_hw_rss_hash_set(hw, rss_conf);
5102 }
5103
5104 static int
5105 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5106                            struct rte_eth_rss_conf *rss_conf)
5107 {
5108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
5110         uint64_t hena;
5111         uint16_t i;
5112
5113         if (hash_key != NULL) {
5114                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5115                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5116                 rss_conf->rss_key_len = i * sizeof(uint32_t);
5117         }
5118         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5119         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5120         rss_conf->rss_hf = i40e_parse_hena(hena);
5121
5122         return 0;
5123 }
5124
5125 static int
5126 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5127 {
5128         switch (filter_type) {
5129         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5130                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5131                 break;
5132         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5133                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5134                 break;
5135         case RTE_TUNNEL_FILTER_IMAC_TENID:
5136                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5137                 break;
5138         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5139                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5140                 break;
5141         case ETH_TUNNEL_FILTER_IMAC:
5142                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5143                 break;
5144         default:
5145                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5146                 return -EINVAL;
5147         }
5148
5149         return 0;
5150 }
5151
5152 static int
5153 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5154                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5155                         uint8_t add)
5156 {
5157         uint16_t ip_type;
5158         uint8_t tun_type = 0;
5159         int val, ret = 0;
5160         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5161         struct i40e_vsi *vsi = pf->main_vsi;
5162         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5163         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5164
5165         cld_filter = rte_zmalloc("tunnel_filter",
5166                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5167                 0);
5168
5169         if (NULL == cld_filter) {
5170                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5171                 return -EINVAL;
5172         }
5173         pfilter = cld_filter;
5174
5175         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5176                         sizeof(struct ether_addr));
5177         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5178                         sizeof(struct ether_addr));
5179
5180         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5181         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5182                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5183                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5184                                 &tunnel_filter->ip_addr,
5185                                 sizeof(pfilter->ipaddr.v4.data));
5186         } else {
5187                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5188                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5189                                 &tunnel_filter->ip_addr,
5190                                 sizeof(pfilter->ipaddr.v6.data));
5191         }
5192
5193         /* check tunneled type */
5194         switch (tunnel_filter->tunnel_type) {
5195         case RTE_TUNNEL_TYPE_VXLAN:
5196                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5197                 break;
5198         case RTE_TUNNEL_TYPE_NVGRE:
5199                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5200                 break;
5201         default:
5202                 /* Other tunnel types is not supported. */
5203                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5204                 rte_free(cld_filter);
5205                 return -EINVAL;
5206         }
5207
5208         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5209                                                 &pfilter->flags);
5210         if (val < 0) {
5211                 rte_free(cld_filter);
5212                 return -EINVAL;
5213         }
5214
5215         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5216                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5217         pfilter->tenant_id = tunnel_filter->tenant_id;
5218         pfilter->queue_number = tunnel_filter->queue_id;
5219
5220         if (add)
5221                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5222         else
5223                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5224                                                 cld_filter, 1);
5225
5226         rte_free(cld_filter);
5227         return ret;
5228 }
5229
5230 static int
5231 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5232 {
5233         uint8_t i;
5234
5235         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5236                 if (pf->vxlan_ports[i] == port)
5237                         return i;
5238         }
5239
5240         return -1;
5241 }
5242
5243 static int
5244 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5245 {
5246         int  idx, ret;
5247         uint8_t filter_idx;
5248         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5249
5250         idx = i40e_get_vxlan_port_idx(pf, port);
5251
5252         /* Check if port already exists */
5253         if (idx >= 0) {
5254                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5255                 return -EINVAL;
5256         }
5257
5258         /* Now check if there is space to add the new port */
5259         idx = i40e_get_vxlan_port_idx(pf, 0);
5260         if (idx < 0) {
5261                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5262                         "not adding port %d", port);
5263                 return -ENOSPC;
5264         }
5265
5266         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5267                                         &filter_idx, NULL);
5268         if (ret < 0) {
5269                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5270                 return -1;
5271         }
5272
5273         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5274                          port,  filter_idx);
5275
5276         /* New port: add it and mark its index in the bitmap */
5277         pf->vxlan_ports[idx] = port;
5278         pf->vxlan_bitmap |= (1 << idx);
5279
5280         if (!(pf->flags & I40E_FLAG_VXLAN))
5281                 pf->flags |= I40E_FLAG_VXLAN;
5282
5283         return 0;
5284 }
5285
5286 static int
5287 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5288 {
5289         int idx;
5290         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5291
5292         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5293                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5294                 return -EINVAL;
5295         }
5296
5297         idx = i40e_get_vxlan_port_idx(pf, port);
5298
5299         if (idx < 0) {
5300                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5301                 return -EINVAL;
5302         }
5303
5304         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5305                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5306                 return -1;
5307         }
5308
5309         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5310                         port, idx);
5311
5312         pf->vxlan_ports[idx] = 0;
5313         pf->vxlan_bitmap &= ~(1 << idx);
5314
5315         if (!pf->vxlan_bitmap)
5316                 pf->flags &= ~I40E_FLAG_VXLAN;
5317
5318         return 0;
5319 }
5320
5321 /* Add UDP tunneling port */
5322 static int
5323 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5324                         struct rte_eth_udp_tunnel *udp_tunnel)
5325 {
5326         int ret = 0;
5327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5328
5329         if (udp_tunnel == NULL)
5330                 return -EINVAL;
5331
5332         switch (udp_tunnel->prot_type) {
5333         case RTE_TUNNEL_TYPE_VXLAN:
5334                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5335                 break;
5336
5337         case RTE_TUNNEL_TYPE_GENEVE:
5338         case RTE_TUNNEL_TYPE_TEREDO:
5339                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5340                 ret = -1;
5341                 break;
5342
5343         default:
5344                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5345                 ret = -1;
5346                 break;
5347         }
5348
5349         return ret;
5350 }
5351
5352 /* Remove UDP tunneling port */
5353 static int
5354 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5355                         struct rte_eth_udp_tunnel *udp_tunnel)
5356 {
5357         int ret = 0;
5358         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5359
5360         if (udp_tunnel == NULL)
5361                 return -EINVAL;
5362
5363         switch (udp_tunnel->prot_type) {
5364         case RTE_TUNNEL_TYPE_VXLAN:
5365                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5366                 break;
5367         case RTE_TUNNEL_TYPE_GENEVE:
5368         case RTE_TUNNEL_TYPE_TEREDO:
5369                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5370                 ret = -1;
5371                 break;
5372         default:
5373                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5374                 ret = -1;
5375                 break;
5376         }
5377
5378         return ret;
5379 }
5380
5381 /* Calculate the maximum number of contiguous PF queues that are configured */
5382 static int
5383 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5384 {
5385         struct rte_eth_dev_data *data = pf->dev_data;
5386         int i, num;
5387         struct i40e_rx_queue *rxq;
5388
5389         num = 0;
5390         for (i = 0; i < pf->lan_nb_qps; i++) {
5391                 rxq = data->rx_queues[i];
5392                 if (rxq && rxq->q_set)
5393                         num++;
5394                 else
5395                         break;
5396         }
5397
5398         return num;
5399 }
5400
5401 /* Configure RSS */
5402 static int
5403 i40e_pf_config_rss(struct i40e_pf *pf)
5404 {
5405         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5406         struct rte_eth_rss_conf rss_conf;
5407         uint32_t i, lut = 0;
5408         uint16_t j, num;
5409
5410         /*
5411          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5412          * It's necessary to calulate the actual PF queues that are configured.
5413          */
5414         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5415                 num = i40e_pf_calc_configured_queues_num(pf);
5416                 num = i40e_align_floor(num);
5417         } else
5418                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5419
5420         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5421                         num);
5422
5423         if (num == 0) {
5424                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5425                 return -ENOTSUP;
5426         }
5427
5428         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5429                 if (j == num)
5430                         j = 0;
5431                 lut = (lut << 8) | (j & ((0x1 <<
5432                         hw->func_caps.rss_table_entry_width) - 1));
5433                 if ((i & 3) == 3)
5434                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5435         }
5436
5437         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5438         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5439                 i40e_pf_disable_rss(pf);
5440                 return 0;
5441         }
5442         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5443                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5444                 /* Random default keys */
5445                 static uint32_t rss_key_default[] = {0x6b793944,
5446                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5447                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5448                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5449
5450                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5451                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5452                                                         sizeof(uint32_t);
5453         }
5454
5455         return i40e_hw_rss_hash_set(hw, &rss_conf);
5456 }
5457
5458 static int
5459 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5460                         struct rte_eth_tunnel_filter_conf *filter)
5461 {
5462         if (pf == NULL || filter == NULL) {
5463                 PMD_DRV_LOG(ERR, "Invalid parameter");
5464                 return -EINVAL;
5465         }
5466
5467         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5468                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5469                 return -EINVAL;
5470         }
5471
5472         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5473                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5474                 return -EINVAL;
5475         }
5476
5477         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5478                 (is_zero_ether_addr(filter->outer_mac))) {
5479                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5480                 return -EINVAL;
5481         }
5482
5483         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5484                 (is_zero_ether_addr(filter->inner_mac))) {
5485                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5486                 return -EINVAL;
5487         }
5488
5489         return 0;
5490 }
5491
5492 static int
5493 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5494                         void *arg)
5495 {
5496         struct rte_eth_tunnel_filter_conf *filter;
5497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5498         int ret = I40E_SUCCESS;
5499
5500         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5501
5502         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5503                 return I40E_ERR_PARAM;
5504
5505         switch (filter_op) {
5506         case RTE_ETH_FILTER_NOP:
5507                 if (!(pf->flags & I40E_FLAG_VXLAN))
5508                         ret = I40E_NOT_SUPPORTED;
5509         case RTE_ETH_FILTER_ADD:
5510                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5511                 break;
5512         case RTE_ETH_FILTER_DELETE:
5513                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5514                 break;
5515         default:
5516                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5517                 ret = I40E_ERR_PARAM;
5518                 break;
5519         }
5520
5521         return ret;
5522 }
5523
5524 static int
5525 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5526 {
5527         int ret = 0;
5528         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5529
5530         /* RSS setup */
5531         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5532                 ret = i40e_pf_config_rss(pf);
5533         else
5534                 i40e_pf_disable_rss(pf);
5535
5536         return ret;
5537 }
5538
5539 /* Get the symmetric hash enable configurations per port */
5540 static void
5541 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5542 {
5543         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5544
5545         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5546 }
5547
5548 /* Set the symmetric hash enable configurations per port */
5549 static void
5550 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5551 {
5552         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5553
5554         if (enable > 0) {
5555                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5556                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5557                                                         "been enabled");
5558                         return;
5559                 }
5560                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5561         } else {
5562                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5563                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5564                                                         "been disabled");
5565                         return;
5566                 }
5567                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5568         }
5569         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5570         I40E_WRITE_FLUSH(hw);
5571 }
5572
5573 /*
5574  * Get global configurations of hash function type and symmetric hash enable
5575  * per flow type (pctype). Note that global configuration means it affects all
5576  * the ports on the same NIC.
5577  */
5578 static int
5579 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5580                                    struct rte_eth_hash_global_conf *g_cfg)
5581 {
5582         uint32_t reg, mask = I40E_FLOW_TYPES;
5583         uint16_t i;
5584         enum i40e_filter_pctype pctype;
5585
5586         memset(g_cfg, 0, sizeof(*g_cfg));
5587         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5588         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5589                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5590         else
5591                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5592         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5593                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5594
5595         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5596                 if (!(mask & (1UL << i)))
5597                         continue;
5598                 mask &= ~(1UL << i);
5599                 /* Bit set indicats the coresponding flow type is supported */
5600                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5601                 pctype = i40e_flowtype_to_pctype(i);
5602                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5603                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5604                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5605         }
5606
5607         return 0;
5608 }
5609
5610 static int
5611 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5612 {
5613         uint32_t i;
5614         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5615
5616         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5617                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5618                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5619                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5620                                                 g_cfg->hash_func);
5621                 return -EINVAL;
5622         }
5623
5624         /*
5625          * As i40e supports less than 32 flow types, only first 32 bits need to
5626          * be checked.
5627          */
5628         mask0 = g_cfg->valid_bit_mask[0];
5629         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5630                 if (i == 0) {
5631                         /* Check if any unsupported flow type configured */
5632                         if ((mask0 | i40e_mask) ^ i40e_mask)
5633                                 goto mask_err;
5634                 } else {
5635                         if (g_cfg->valid_bit_mask[i])
5636                                 goto mask_err;
5637                 }
5638         }
5639
5640         return 0;
5641
5642 mask_err:
5643         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5644
5645         return -EINVAL;
5646 }
5647
5648 /*
5649  * Set global configurations of hash function type and symmetric hash enable
5650  * per flow type (pctype). Note any modifying global configuration will affect
5651  * all the ports on the same NIC.
5652  */
5653 static int
5654 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5655                                    struct rte_eth_hash_global_conf *g_cfg)
5656 {
5657         int ret;
5658         uint16_t i;
5659         uint32_t reg;
5660         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5661         enum i40e_filter_pctype pctype;
5662
5663         /* Check the input parameters */
5664         ret = i40e_hash_global_config_check(g_cfg);
5665         if (ret < 0)
5666                 return ret;
5667
5668         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5669                 if (!(mask0 & (1UL << i)))
5670                         continue;
5671                 mask0 &= ~(1UL << i);
5672                 pctype = i40e_flowtype_to_pctype(i);
5673                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5674                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5675                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5676         }
5677
5678         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5679         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5680                 /* Toeplitz */
5681                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5682                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5683                                                                 "Toeplitz");
5684                         goto out;
5685                 }
5686                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5687         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5688                 /* Simple XOR */
5689                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5690                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5691                                                         "Simple XOR");
5692                         goto out;
5693                 }
5694                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5695         } else
5696                 /* Use the default, and keep it as it is */
5697                 goto out;
5698
5699         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5700
5701 out:
5702         I40E_WRITE_FLUSH(hw);
5703
5704         return 0;
5705 }
5706
5707 static int
5708 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5709 {
5710         int ret = 0;
5711
5712         if (!hw || !info) {
5713                 PMD_DRV_LOG(ERR, "Invalid pointer");
5714                 return -EFAULT;
5715         }
5716
5717         switch (info->info_type) {
5718         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5719                 i40e_get_symmetric_hash_enable_per_port(hw,
5720                                         &(info->info.enable));
5721                 break;
5722         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5723                 ret = i40e_get_hash_filter_global_config(hw,
5724                                 &(info->info.global_conf));
5725                 break;
5726         default:
5727                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5728                                                         info->info_type);
5729                 ret = -EINVAL;
5730                 break;
5731         }
5732
5733         return ret;
5734 }
5735
5736 static int
5737 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5738 {
5739         int ret = 0;
5740
5741         if (!hw || !info) {
5742                 PMD_DRV_LOG(ERR, "Invalid pointer");
5743                 return -EFAULT;
5744         }
5745
5746         switch (info->info_type) {
5747         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5748                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5749                 break;
5750         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5751                 ret = i40e_set_hash_filter_global_config(hw,
5752                                 &(info->info.global_conf));
5753                 break;
5754         default:
5755                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5756                                                         info->info_type);
5757                 ret = -EINVAL;
5758                 break;
5759         }
5760
5761         return ret;
5762 }
5763
5764 /* Operations for hash function */
5765 static int
5766 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5767                       enum rte_filter_op filter_op,
5768                       void *arg)
5769 {
5770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5771         int ret = 0;
5772
5773         switch (filter_op) {
5774         case RTE_ETH_FILTER_NOP:
5775                 break;
5776         case RTE_ETH_FILTER_GET:
5777                 ret = i40e_hash_filter_get(hw,
5778                         (struct rte_eth_hash_filter_info *)arg);
5779                 break;
5780         case RTE_ETH_FILTER_SET:
5781                 ret = i40e_hash_filter_set(hw,
5782                         (struct rte_eth_hash_filter_info *)arg);
5783                 break;
5784         default:
5785                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5786                                                                 filter_op);
5787                 ret = -ENOTSUP;
5788                 break;
5789         }
5790
5791         return ret;
5792 }
5793
5794 /*
5795  * Configure ethertype filter, which can director packet by filtering
5796  * with mac address and ether_type or only ether_type
5797  */
5798 static int
5799 i40e_ethertype_filter_set(struct i40e_pf *pf,
5800                         struct rte_eth_ethertype_filter *filter,
5801                         bool add)
5802 {
5803         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5804         struct i40e_control_filter_stats stats;
5805         uint16_t flags = 0;
5806         int ret;
5807
5808         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5809                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5810                 return -EINVAL;
5811         }
5812         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5813                 filter->ether_type == ETHER_TYPE_IPv6) {
5814                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5815                         " control packet filter.", filter->ether_type);
5816                 return -EINVAL;
5817         }
5818         if (filter->ether_type == ETHER_TYPE_VLAN)
5819                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5820                         " not supported.");
5821
5822         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5823                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5824         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5825                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5826         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5827
5828         memset(&stats, 0, sizeof(stats));
5829         ret = i40e_aq_add_rem_control_packet_filter(hw,
5830                         filter->mac_addr.addr_bytes,
5831                         filter->ether_type, flags,
5832                         pf->main_vsi->seid,
5833                         filter->queue, add, &stats, NULL);
5834
5835         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5836                          " mac_etype_used = %u, etype_used = %u,"
5837                          " mac_etype_free = %u, etype_free = %u\n",
5838                          ret, stats.mac_etype_used, stats.etype_used,
5839                          stats.mac_etype_free, stats.etype_free);
5840         if (ret < 0)
5841                 return -ENOSYS;
5842         return 0;
5843 }
5844
5845 /*
5846  * Handle operations for ethertype filter.
5847  */
5848 static int
5849 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5850                                 enum rte_filter_op filter_op,
5851                                 void *arg)
5852 {
5853         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5854         int ret = 0;
5855
5856         if (filter_op == RTE_ETH_FILTER_NOP)
5857                 return ret;
5858
5859         if (arg == NULL) {
5860                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5861                             filter_op);
5862                 return -EINVAL;
5863         }
5864
5865         switch (filter_op) {
5866         case RTE_ETH_FILTER_ADD:
5867                 ret = i40e_ethertype_filter_set(pf,
5868                         (struct rte_eth_ethertype_filter *)arg,
5869                         TRUE);
5870                 break;
5871         case RTE_ETH_FILTER_DELETE:
5872                 ret = i40e_ethertype_filter_set(pf,
5873                         (struct rte_eth_ethertype_filter *)arg,
5874                         FALSE);
5875                 break;
5876         default:
5877                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5878                 ret = -ENOSYS;
5879                 break;
5880         }
5881         return ret;
5882 }
5883
5884 static int
5885 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5886                      enum rte_filter_type filter_type,
5887                      enum rte_filter_op filter_op,
5888                      void *arg)
5889 {
5890         int ret = 0;
5891
5892         if (dev == NULL)
5893                 return -EINVAL;
5894
5895         switch (filter_type) {
5896         case RTE_ETH_FILTER_HASH:
5897                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5898                 break;
5899         case RTE_ETH_FILTER_MACVLAN:
5900                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5901                 break;
5902         case RTE_ETH_FILTER_ETHERTYPE:
5903                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5904                 break;
5905         case RTE_ETH_FILTER_TUNNEL:
5906                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5907                 break;
5908         case RTE_ETH_FILTER_FDIR:
5909                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5910                 break;
5911         default:
5912                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5913                                                         filter_type);
5914                 ret = -EINVAL;
5915                 break;
5916         }
5917
5918         return ret;
5919 }
5920
5921 /*
5922  * As some registers wouldn't be reset unless a global hardware reset,
5923  * hardware initialization is needed to put those registers into an
5924  * expected initial state.
5925  */
5926 static void
5927 i40e_hw_init(struct i40e_hw *hw)
5928 {
5929         /* clear the PF Queue Filter control register */
5930         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5931
5932         /* Disable symmetric hash per port */
5933         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5934 }
5935
5936 enum i40e_filter_pctype
5937 i40e_flowtype_to_pctype(uint16_t flow_type)
5938 {
5939         static const enum i40e_filter_pctype pctype_table[] = {
5940                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5941                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5942                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5943                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5944                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5945                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5946                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5947                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5948                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5949                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5950                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5951                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5952                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5953                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5954                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5955                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5956                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5957                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5958                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5959         };
5960
5961         return pctype_table[flow_type];
5962 }
5963
5964 uint16_t
5965 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5966 {
5967         static const uint16_t flowtype_table[] = {
5968                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5969                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5970                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5971                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5972                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5973                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5974                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5975                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5976                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5977                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5978                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5979                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5980                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5981                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5982                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5983                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5984                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5985                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5986                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5987         };
5988
5989         return flowtype_table[pctype];
5990 }
5991
5992 /*
5993  * On X710, performance number is far from the expectation on recent firmware
5994  * versions; on XL710, performance number is also far from the expectation on
5995  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5996  * mode is enabled and port MAC address is equal to the packet destination MAC
5997  * address. The fix for this issue may not be integrated in the following
5998  * firmware version. So the workaround in software driver is needed. It needs
5999  * to modify the initial values of 3 internal only registers for both X710 and
6000  * XL710. Note that the values for X710 or XL710 could be different, and the
6001  * workaround can be removed when it is fixed in firmware in the future.
6002  */
6003
6004 /* For both X710 and XL710 */
6005 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
6006 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
6007
6008 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
6009 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
6010
6011 /* For X710 */
6012 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
6013 /* For XL710 */
6014 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
6015 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
6016
6017 static void
6018 i40e_configure_registers(struct i40e_hw *hw)
6019 {
6020         static struct {
6021                 uint32_t addr;
6022                 uint64_t val;
6023         } reg_table[] = {
6024                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
6025                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
6026                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
6027         };
6028         uint64_t reg;
6029         uint32_t i;
6030         int ret;
6031
6032         for (i = 0; i < RTE_DIM(reg_table); i++) {
6033                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
6034                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
6035                                 reg_table[i].val =
6036                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
6037                         else /* For X710 */
6038                                 reg_table[i].val =
6039                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
6040                 }
6041
6042                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
6043                                                         &reg, NULL);
6044                 if (ret < 0) {
6045                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
6046                                                         reg_table[i].addr);
6047                         break;
6048                 }
6049                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
6050                                                 reg_table[i].addr, reg);
6051                 if (reg == reg_table[i].val)
6052                         continue;
6053
6054                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
6055                                                 reg_table[i].val, NULL);
6056                 if (ret < 0) {
6057                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
6058                                 "address of 0x%"PRIx32, reg_table[i].val,
6059                                                         reg_table[i].addr);
6060                         break;
6061                 }
6062                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6063                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6064         }
6065 }
6066
6067 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6068 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6069 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6070 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6071 static int
6072 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6073 {
6074         uint32_t reg;
6075         int ret;
6076
6077         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6078                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6079                 return -EINVAL;
6080         }
6081
6082         /* Configure for double VLAN RX stripping */
6083         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6084         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6085                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6086                 ret = i40e_aq_debug_write_register(hw,
6087                                                    I40E_VSI_TSR(vsi->vsi_id),
6088                                                    reg, NULL);
6089                 if (ret < 0) {
6090                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6091                                     vsi->vsi_id);
6092                         return I40E_ERR_CONFIG;
6093                 }
6094         }
6095
6096         /* Configure for double VLAN TX insertion */
6097         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6098         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6099                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6100                 ret = i40e_aq_debug_write_register(hw,
6101                                                    I40E_VSI_L2TAGSTXVALID(
6102                                                    vsi->vsi_id), reg, NULL);
6103                 if (ret < 0) {
6104                         PMD_DRV_LOG(ERR, "Failed to update "
6105                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6106                         return I40E_ERR_CONFIG;
6107                 }
6108         }
6109
6110         return 0;
6111 }
6112
6113 /**
6114  * i40e_aq_add_mirror_rule
6115  * @hw: pointer to the hardware structure
6116  * @seid: VEB seid to add mirror rule to
6117  * @dst_id: destination vsi seid
6118  * @entries: Buffer which contains the entities to be mirrored
6119  * @count: number of entities contained in the buffer
6120  * @rule_id:the rule_id of the rule to be added
6121  *
6122  * Add a mirror rule for a given veb.
6123  *
6124  **/
6125 static enum i40e_status_code
6126 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6127                         uint16_t seid, uint16_t dst_id,
6128                         uint16_t rule_type, uint16_t *entries,
6129                         uint16_t count, uint16_t *rule_id)
6130 {
6131         struct i40e_aq_desc desc;
6132         struct i40e_aqc_add_delete_mirror_rule cmd;
6133         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6134                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6135                 &desc.params.raw;
6136         uint16_t buff_len;
6137         enum i40e_status_code status;
6138
6139         i40e_fill_default_direct_cmd_desc(&desc,
6140                                           i40e_aqc_opc_add_mirror_rule);
6141         memset(&cmd, 0, sizeof(cmd));
6142
6143         buff_len = sizeof(uint16_t) * count;
6144         desc.datalen = rte_cpu_to_le_16(buff_len);
6145         if (buff_len > 0)
6146                 desc.flags |= rte_cpu_to_le_16(
6147                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6148         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6149                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6150         cmd.num_entries = rte_cpu_to_le_16(count);
6151         cmd.seid = rte_cpu_to_le_16(seid);
6152         cmd.destination = rte_cpu_to_le_16(dst_id);
6153
6154         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6155         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6156         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6157                          "rule_id = %u"
6158                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6159                          hw->aq.asq_last_status, resp->rule_id,
6160                          resp->mirror_rules_used, resp->mirror_rules_free);
6161         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6162
6163         return status;
6164 }
6165
6166 /**
6167  * i40e_aq_del_mirror_rule
6168  * @hw: pointer to the hardware structure
6169  * @seid: VEB seid to add mirror rule to
6170  * @entries: Buffer which contains the entities to be mirrored
6171  * @count: number of entities contained in the buffer
6172  * @rule_id:the rule_id of the rule to be delete
6173  *
6174  * Delete a mirror rule for a given veb.
6175  *
6176  **/
6177 static enum i40e_status_code
6178 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6179                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6180                 uint16_t count, uint16_t rule_id)
6181 {
6182         struct i40e_aq_desc desc;
6183         struct i40e_aqc_add_delete_mirror_rule cmd;
6184         uint16_t buff_len = 0;
6185         enum i40e_status_code status;
6186         void *buff = NULL;
6187
6188         i40e_fill_default_direct_cmd_desc(&desc,
6189                                           i40e_aqc_opc_delete_mirror_rule);
6190         memset(&cmd, 0, sizeof(cmd));
6191         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6192                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6193                                                           I40E_AQ_FLAG_RD));
6194                 cmd.num_entries = count;
6195                 buff_len = sizeof(uint16_t) * count;
6196                 desc.datalen = rte_cpu_to_le_16(buff_len);
6197                 buff = (void *)entries;
6198         } else
6199                 /* rule id is filled in destination field for deleting mirror rule */
6200                 cmd.destination = rte_cpu_to_le_16(rule_id);
6201
6202         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6203                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6204         cmd.seid = rte_cpu_to_le_16(seid);
6205
6206         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6207         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6208
6209         return status;
6210 }
6211
6212 /**
6213  * i40e_mirror_rule_set
6214  * @dev: pointer to the hardware structure
6215  * @mirror_conf: mirror rule info
6216  * @sw_id: mirror rule's sw_id
6217  * @on: enable/disable
6218  *
6219  * set a mirror rule.
6220  *
6221  **/
6222 static int
6223 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6224                         struct rte_eth_mirror_conf *mirror_conf,
6225                         uint8_t sw_id, uint8_t on)
6226 {
6227         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6229         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6230         struct i40e_mirror_rule *parent = NULL;
6231         uint16_t seid, dst_seid, rule_id;
6232         uint16_t i, j = 0;
6233         int ret;
6234
6235         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6236
6237         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6238                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6239                         " without veb or vfs.");
6240                 return -ENOSYS;
6241         }
6242         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6243                 PMD_DRV_LOG(ERR, "mirror table is full.");
6244                 return -ENOSPC;
6245         }
6246         if (mirror_conf->dst_pool > pf->vf_num) {
6247                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6248                                  mirror_conf->dst_pool);
6249                 return -EINVAL;
6250         }
6251
6252         seid = pf->main_vsi->veb->seid;
6253
6254         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6255                 if (sw_id <= it->index) {
6256                         mirr_rule = it;
6257                         break;
6258                 }
6259                 parent = it;
6260         }
6261         if (mirr_rule && sw_id == mirr_rule->index) {
6262                 if (on) {
6263                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6264                         return -EEXIST;
6265                 } else {
6266                         ret = i40e_aq_del_mirror_rule(hw, seid,
6267                                         mirr_rule->rule_type,
6268                                         mirr_rule->entries,
6269                                         mirr_rule->num_entries, mirr_rule->id);
6270                         if (ret < 0) {
6271                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6272                                                    " ret = %d, aq_err = %d.",
6273                                                    ret, hw->aq.asq_last_status);
6274                                 return -ENOSYS;
6275                         }
6276                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6277                         rte_free(mirr_rule);
6278                         pf->nb_mirror_rule--;
6279                         return 0;
6280                 }
6281         } else if (!on) {
6282                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6283                 return -ENOENT;
6284         }
6285
6286         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6287                                 sizeof(struct i40e_mirror_rule) , 0);
6288         if (!mirr_rule) {
6289                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6290                 return I40E_ERR_NO_MEMORY;
6291         }
6292         switch (mirror_conf->rule_type) {
6293         case ETH_MIRROR_VLAN:
6294                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6295                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6296                                 mirr_rule->entries[j] =
6297                                         mirror_conf->vlan.vlan_id[i];
6298                                 j++;
6299                         }
6300                 }
6301                 if (j == 0) {
6302                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6303                         rte_free(mirr_rule);
6304                         return -EINVAL;
6305                 }
6306                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6307                 break;
6308         case ETH_MIRROR_VIRTUAL_POOL_UP:
6309         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6310                 /* check if the specified pool bit is out of range */
6311                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6312                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6313                         rte_free(mirr_rule);
6314                         return -EINVAL;
6315                 }
6316                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6317                         if (mirror_conf->pool_mask & (1ULL << i)) {
6318                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6319                                 j++;
6320                         }
6321                 }
6322                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6323                         /* add pf vsi to entries */
6324                         mirr_rule->entries[j] = pf->main_vsi_seid;
6325                         j++;
6326                 }
6327                 if (j == 0) {
6328                         PMD_DRV_LOG(ERR, "pool is not specified.");
6329                         rte_free(mirr_rule);
6330                         return -EINVAL;
6331                 }
6332                 /* egress and ingress in aq commands means from switch but not port */
6333                 mirr_rule->rule_type =
6334                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6335                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6336                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6337                 break;
6338         case ETH_MIRROR_UPLINK_PORT:
6339                 /* egress and ingress in aq commands means from switch but not port*/
6340                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6341                 break;
6342         case ETH_MIRROR_DOWNLINK_PORT:
6343                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6344                 break;
6345         default:
6346                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6347                         mirror_conf->rule_type);
6348                 rte_free(mirr_rule);
6349                 return -EINVAL;
6350         }
6351
6352         /* If the dst_pool is equal to vf_num, consider it as PF */
6353         if (mirror_conf->dst_pool == pf->vf_num)
6354                 dst_seid = pf->main_vsi_seid;
6355         else
6356                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6357
6358         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6359                                       mirr_rule->rule_type, mirr_rule->entries,
6360                                       j, &rule_id);
6361         if (ret < 0) {
6362                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6363                                    " ret = %d, aq_err = %d.",
6364                                    ret, hw->aq.asq_last_status);
6365                 rte_free(mirr_rule);
6366                 return -ENOSYS;
6367         }
6368
6369         mirr_rule->index = sw_id;
6370         mirr_rule->num_entries = j;
6371         mirr_rule->id = rule_id;
6372         mirr_rule->dst_vsi_seid = dst_seid;
6373
6374         if (parent)
6375                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6376         else
6377                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6378
6379         pf->nb_mirror_rule++;
6380         return 0;
6381 }
6382
6383 /**
6384  * i40e_mirror_rule_reset
6385  * @dev: pointer to the device
6386  * @sw_id: mirror rule's sw_id
6387  *
6388  * reset a mirror rule.
6389  *
6390  **/
6391 static int
6392 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6393 {
6394         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6396         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6397         uint16_t seid;
6398         int ret;
6399
6400         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6401
6402         seid = pf->main_vsi->veb->seid;
6403
6404         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6405                 if (sw_id == it->index) {
6406                         mirr_rule = it;
6407                         break;
6408                 }
6409         }
6410         if (mirr_rule) {
6411                 ret = i40e_aq_del_mirror_rule(hw, seid,
6412                                 mirr_rule->rule_type,
6413                                 mirr_rule->entries,
6414                                 mirr_rule->num_entries, mirr_rule->id);
6415                 if (ret < 0) {
6416                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6417                                            " status = %d, aq_err = %d.",
6418                                            ret, hw->aq.asq_last_status);
6419                         return -ENOSYS;
6420                 }
6421                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6422                 rte_free(mirr_rule);
6423                 pf->nb_mirror_rule--;
6424         } else {
6425                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6426                 return -ENOENT;
6427         }
6428         return 0;
6429 }
6430
6431 static int
6432 i40e_timesync_enable(struct rte_eth_dev *dev)
6433 {
6434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6435         struct rte_eth_link *link = &dev->data->dev_link;
6436         uint32_t tsync_ctl_l;
6437         uint32_t tsync_ctl_h;
6438         uint32_t tsync_inc_l;
6439         uint32_t tsync_inc_h;
6440
6441         switch (link->link_speed) {
6442         case ETH_LINK_SPEED_40G:
6443                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6444                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6445                 break;
6446         case ETH_LINK_SPEED_10G:
6447                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6448                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6449                 break;
6450         case ETH_LINK_SPEED_1000:
6451                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6452                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6453                 break;
6454         default:
6455                 tsync_inc_l = 0x0;
6456                 tsync_inc_h = 0x0;
6457         }
6458
6459         /* Clear timesync registers. */
6460         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6461         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6462         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6463         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6464         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6465         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6466         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6467
6468         /* Set the timesync increment value. */
6469         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6470         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6471
6472         /* Enable timestamping of PTP packets. */
6473         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6474         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6475
6476         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6477         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6478         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6479
6480         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6481         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6482
6483         return 0;
6484 }
6485
6486 static int
6487 i40e_timesync_disable(struct rte_eth_dev *dev)
6488 {
6489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6490         uint32_t tsync_ctl_l;
6491         uint32_t tsync_ctl_h;
6492
6493         /* Disable timestamping of transmitted PTP packets. */
6494         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6495         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6496
6497         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6498         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6499
6500         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6501         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6502
6503         /* Set the timesync increment value. */
6504         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6505         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6506
6507         return 0;
6508 }
6509
6510 static int
6511 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6512                                 struct timespec *timestamp, uint32_t flags)
6513 {
6514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6515         uint32_t sync_status;
6516         uint32_t rx_stmpl;
6517         uint32_t rx_stmph;
6518         uint32_t index = flags & 0x03;
6519
6520         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6521         if ((sync_status & (1 << index)) == 0)
6522                 return -EINVAL;
6523
6524         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6525         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6526
6527         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6528         timestamp->tv_nsec = 0;
6529
6530         return  0;
6531 }
6532
6533 static int
6534 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6535                                 struct timespec *timestamp)
6536 {
6537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6538         uint32_t sync_status;
6539         uint32_t tx_stmpl;
6540         uint32_t tx_stmph;
6541
6542         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6543         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6544                 return -EINVAL;
6545
6546         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6547         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6548
6549         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6550         timestamp->tv_nsec = 0;
6551
6552         return  0;
6553 }
6554
6555 /*
6556  * i40e_parse_dcb_configure - parse dcb configure from user
6557  * @dev: the device being configured
6558  * @dcb_cfg: pointer of the result of parse
6559  * @*tc_map: bit map of enabled traffic classes
6560  *
6561  * Returns 0 on success, negative value on failure
6562  */
6563 static int
6564 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
6565                          struct i40e_dcbx_config *dcb_cfg,
6566                          uint8_t *tc_map)
6567 {
6568         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
6569         uint8_t i, tc_bw, bw_lf;
6570
6571         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
6572
6573         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6574         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
6575                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
6576                 return -EINVAL;
6577         }
6578
6579         /* assume each tc has the same bw */
6580         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
6581         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6582                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
6583         /* to ensure the sum of tcbw is equal to 100 */
6584         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
6585         for (i = 0; i < bw_lf; i++)
6586                 dcb_cfg->etscfg.tcbwtable[i]++;
6587
6588         /* assume each tc has the same Transmission Selection Algorithm */
6589         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
6590                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
6591
6592         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
6593                 dcb_cfg->etscfg.prioritytable[i] =
6594                                 dcb_rx_conf->dcb_tc[i];
6595
6596         /* FW needs one App to configure HW */
6597         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
6598         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
6599         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
6600         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
6601
6602         if (dcb_rx_conf->nb_tcs == 0)
6603                 *tc_map = 1; /* tc0 only */
6604         else
6605                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
6606
6607         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
6608                 dcb_cfg->pfc.willing = 0;
6609                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
6610                 dcb_cfg->pfc.pfcenable = *tc_map;
6611         }
6612         return 0;
6613 }
6614
6615 /*
6616  * i40e_vsi_get_bw_info - Query VSI BW Information
6617  * @vsi: the VSI being queried
6618  *
6619  * Returns 0 on success, negative value on failure
6620  */
6621 static int
6622 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
6623 {
6624         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
6625         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
6626         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6627         int i, ret;
6628         uint32_t tc_bw_max;
6629
6630         /* Get the VSI level BW configuration */
6631         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
6632         if (ret) {
6633                 PMD_INIT_LOG(ERR,
6634                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
6635                          i40e_stat_str(hw, ret),
6636                          i40e_aq_str(hw, hw->aq.asq_last_status));
6637                 return -EINVAL;
6638         }
6639
6640         /* Get the VSI level BW configuration per TC */
6641         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
6642                                                   NULL);
6643         if (ret) {
6644                 PMD_INIT_LOG(ERR,
6645                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
6646                          i40e_stat_str(hw, ret),
6647                          i40e_aq_str(hw, hw->aq.asq_last_status));
6648                 return -EINVAL;
6649         }
6650
6651         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
6652                 PMD_INIT_LOG(WARNING,
6653                          "Enabled TCs mismatch from querying VSI BW info"
6654                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
6655                          bw_ets_config.tc_valid_bits);
6656                 /* Still continuing */
6657         }
6658
6659         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
6660         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
6661         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
6662                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
6663         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6664                 vsi->bw_info.bw_ets_share_credits[i] =
6665                                 bw_ets_config.share_credits[i];
6666                 vsi->bw_info.bw_ets_limit_credits[i] =
6667                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
6668                 /* 3 bits out of 4 for each TC */
6669                 vsi->bw_info.bw_ets_max_quanta[i] =
6670                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
6671                 PMD_INIT_LOG(DEBUG,
6672                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
6673                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
6674         }
6675
6676         return 0;
6677 }
6678
6679 static int
6680 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
6681                               struct i40e_aqc_vsi_properties_data *info,
6682                               uint8_t enabled_tcmap)
6683 {
6684         int ret, i, total_tc = 0;
6685         uint16_t qpnum_per_tc, bsf, qp_idx;
6686         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
6687
6688         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
6689         if (ret != I40E_SUCCESS)
6690                 return ret;
6691
6692         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6693                 if (enabled_tcmap & (1 << i))
6694                         total_tc++;
6695         }
6696         if (total_tc == 0)
6697                 total_tc = 1;
6698         vsi->enabled_tc = enabled_tcmap;
6699
6700         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
6701         /* Number of queues per enabled TC */
6702         if (qpnum_per_tc == 0) {
6703                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
6704                 return I40E_ERR_INVALID_QP_ID;
6705         }
6706         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
6707                                 I40E_MAX_Q_PER_TC);
6708         bsf = rte_bsf32(qpnum_per_tc);
6709
6710         /**
6711          * Configure TC and queue mapping parameters, for enabled TC,
6712          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
6713          * default queue will serve it.
6714          */
6715         qp_idx = 0;
6716         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6717                 if (vsi->enabled_tc & (1 << i)) {
6718                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
6719                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
6720                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
6721                         qp_idx += qpnum_per_tc;
6722                 } else
6723                         info->tc_mapping[i] = 0;
6724         }
6725
6726         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
6727         if (vsi->type == I40E_VSI_SRIOV) {
6728                 info->mapping_flags |=
6729                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
6730                 for (i = 0; i < vsi->nb_qps; i++)
6731                         info->queue_mapping[i] =
6732                                 rte_cpu_to_le_16(vsi->base_queue + i);
6733         } else {
6734                 info->mapping_flags |=
6735                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
6736                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
6737         }
6738         info->valid_sections |=
6739                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
6740
6741         return I40E_SUCCESS;
6742 }
6743
6744 /*
6745  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
6746  * @vsi: VSI to be configured
6747  * @tc_map: enabled TC bitmap
6748  *
6749  * Returns 0 on success, negative value on failure
6750  */
6751 static int
6752 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
6753 {
6754         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
6755         struct i40e_vsi_context ctxt;
6756         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6757         int ret = 0;
6758         int i;
6759
6760         /* Check if enabled_tc is same as existing or new TCs */
6761         if (vsi->enabled_tc == tc_map)
6762                 return ret;
6763
6764         /* configure tc bandwidth */
6765         memset(&bw_data, 0, sizeof(bw_data));
6766         bw_data.tc_valid_bits = tc_map;
6767         /* Enable ETS TCs with equal BW Share for now across all VSIs */
6768         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6769                 if (tc_map & BIT_ULL(i))
6770                         bw_data.tc_bw_credits[i] = 1;
6771         }
6772         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
6773         if (ret) {
6774                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
6775                         " per TC failed = %d",
6776                         hw->aq.asq_last_status);
6777                 goto out;
6778         }
6779         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
6780                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
6781
6782         /* Update Queue Pairs Mapping for currently enabled UPs */
6783         ctxt.seid = vsi->seid;
6784         ctxt.pf_num = hw->pf_id;
6785         ctxt.vf_num = 0;
6786         ctxt.uplink_seid = vsi->uplink_seid;
6787         ctxt.info = vsi->info;
6788         i40e_get_cap(hw);
6789         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
6790         if (ret)
6791                 goto out;
6792
6793         /* Update the VSI after updating the VSI queue-mapping information */
6794         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6795         if (ret) {
6796                 PMD_INIT_LOG(ERR, "Failed to configure "
6797                             "TC queue mapping = %d",
6798                             hw->aq.asq_last_status);
6799                 goto out;
6800         }
6801         /* update the local VSI info with updated queue map */
6802         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
6803                                         sizeof(vsi->info.tc_mapping));
6804         (void)rte_memcpy(&vsi->info.queue_mapping,
6805                         &ctxt.info.queue_mapping,
6806                 sizeof(vsi->info.queue_mapping));
6807         vsi->info.mapping_flags = ctxt.info.mapping_flags;
6808         vsi->info.valid_sections = 0;
6809
6810         /* Update current VSI BW information */
6811         ret = i40e_vsi_get_bw_info(vsi);
6812         if (ret) {
6813                 PMD_INIT_LOG(ERR,
6814                          "Failed updating vsi bw info, err %s aq_err %s",
6815                          i40e_stat_str(hw, ret),
6816                          i40e_aq_str(hw, hw->aq.asq_last_status));
6817                 goto out;
6818         }
6819
6820         vsi->enabled_tc = tc_map;
6821
6822 out:
6823         return ret;
6824 }
6825
6826 /*
6827  * i40e_dcb_hw_configure - program the dcb setting to hw
6828  * @pf: pf the configuration is taken on
6829  * @new_cfg: new configuration
6830  * @tc_map: enabled TC bitmap
6831  *
6832  * Returns 0 on success, negative value on failure
6833  */
6834 static enum i40e_status_code
6835 i40e_dcb_hw_configure(struct i40e_pf *pf,
6836                       struct i40e_dcbx_config *new_cfg,
6837                       uint8_t tc_map)
6838 {
6839         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6840         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
6841         struct i40e_vsi *main_vsi = pf->main_vsi;
6842         struct i40e_vsi_list *vsi_list;
6843         int i, ret;
6844         uint32_t val;
6845
6846         /* Use the FW API if FW > v4.4*/
6847         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
6848                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
6849                                   " to configure DCB");
6850                 return I40E_ERR_FIRMWARE_API_VERSION;
6851         }
6852
6853         /* Check if need reconfiguration */
6854         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
6855                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
6856                 return I40E_SUCCESS;
6857         }
6858
6859         /* Copy the new config to the current config */
6860         *old_cfg = *new_cfg;
6861         old_cfg->etsrec = old_cfg->etscfg;
6862         ret = i40e_set_dcb_config(hw);
6863         if (ret) {
6864                 PMD_INIT_LOG(ERR,
6865                          "Set DCB Config failed, err %s aq_err %s\n",
6866                          i40e_stat_str(hw, ret),
6867                          i40e_aq_str(hw, hw->aq.asq_last_status));
6868                 return ret;
6869         }
6870         /* set receive Arbiter to RR mode and ETS scheme by default */
6871         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
6872                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
6873                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
6874                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
6875                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
6876                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
6877                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
6878                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
6879                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
6880                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
6881                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
6882                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
6883                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
6884         }
6885         /* get local mib to check whether it is configured correctly */
6886         /* IEEE mode */
6887         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
6888         /* Get Local DCB Config */
6889         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
6890                                      &hw->local_dcbx_config);
6891
6892         /* Update each VSI */
6893         i40e_vsi_config_tc(main_vsi, tc_map);
6894         if (main_vsi->veb) {
6895                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
6896                         /* Beside main VSI, only enable default
6897                          * TC for other VSIs
6898                          */
6899                         ret = i40e_vsi_config_tc(vsi_list->vsi,
6900                                                 I40E_DEFAULT_TCMAP);
6901                         if (ret)
6902                                 PMD_INIT_LOG(WARNING,
6903                                          "Failed configuring TC for VSI seid=%d\n",
6904                                          vsi_list->vsi->seid);
6905                         /* continue */
6906                 }
6907         }
6908         return I40E_SUCCESS;
6909 }
6910
6911 /*
6912  * i40e_dcb_init_configure - initial dcb config
6913  * @dev: device being configured
6914  * @sw_dcb: indicate whether dcb is sw configured or hw offload
6915  *
6916  * Returns 0 on success, negative value on failure
6917  */
6918 static int
6919 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
6920 {
6921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6923         int ret = 0;
6924
6925         if ((pf->flags & I40E_FLAG_DCB) == 0) {
6926                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
6927                 return -ENOTSUP;
6928         }
6929
6930         /* DCB initialization:
6931          * Update DCB configuration from the Firmware and configure
6932          * LLDP MIB change event.
6933          */
6934         if (sw_dcb == TRUE) {
6935                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
6936                 if (ret != I40E_SUCCESS)
6937                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
6938
6939                 ret = i40e_init_dcb(hw);
6940                 /* if sw_dcb, lldp agent is stopped, the return from
6941                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
6942                  * adminq status.
6943                  */
6944                 if (ret != I40E_SUCCESS &&
6945                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
6946                         memset(&hw->local_dcbx_config, 0,
6947                                 sizeof(struct i40e_dcbx_config));
6948                         /* set dcb default configuration */
6949                         hw->local_dcbx_config.etscfg.willing = 0;
6950                         hw->local_dcbx_config.etscfg.maxtcs = 0;
6951                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
6952                         hw->local_dcbx_config.etscfg.tsatable[0] =
6953                                                 I40E_IEEE_TSA_ETS;
6954                         hw->local_dcbx_config.etsrec =
6955                                 hw->local_dcbx_config.etscfg;
6956                         hw->local_dcbx_config.pfc.willing = 0;
6957                         hw->local_dcbx_config.pfc.pfccap =
6958                                                 I40E_MAX_TRAFFIC_CLASS;
6959                         /* FW needs one App to configure HW */
6960                         hw->local_dcbx_config.numapps = 1;
6961                         hw->local_dcbx_config.app[0].selector =
6962                                                 I40E_APP_SEL_ETHTYPE;
6963                         hw->local_dcbx_config.app[0].priority = 3;
6964                         hw->local_dcbx_config.app[0].protocolid =
6965                                                 I40E_APP_PROTOID_FCOE;
6966                         ret = i40e_set_dcb_config(hw);
6967                         if (ret) {
6968                                 PMD_INIT_LOG(ERR, "default dcb config fails."
6969                                         " err = %d, aq_err = %d.", ret,
6970                                           hw->aq.asq_last_status);
6971                                 return -ENOSYS;
6972                         }
6973                 } else {
6974                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
6975                                           " aq_err = %d.", ret,
6976                                           hw->aq.asq_last_status);
6977                         return -ENOTSUP;
6978                 }
6979         } else {
6980                 ret = i40e_aq_start_lldp(hw, NULL);
6981                 if (ret != I40E_SUCCESS)
6982                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
6983
6984                 ret = i40e_init_dcb(hw);
6985                 if (!ret) {
6986                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
6987                                 PMD_INIT_LOG(ERR, "HW doesn't support"
6988                                                   " DCBX offload.");
6989                                 return -ENOTSUP;
6990                         }
6991                 } else {
6992                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
6993                                           " aq_err = %d.", ret,
6994                                           hw->aq.asq_last_status);
6995                         return -ENOTSUP;
6996                 }
6997         }
6998         return 0;
6999 }
7000
7001 /*
7002  * i40e_dcb_setup - setup dcb related config
7003  * @dev: device being configured
7004  *
7005  * Returns 0 on success, negative value on failure
7006  */
7007 static int
7008 i40e_dcb_setup(struct rte_eth_dev *dev)
7009 {
7010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7011         struct i40e_dcbx_config dcb_cfg;
7012         uint8_t tc_map = 0;
7013         int ret = 0;
7014
7015         if ((pf->flags & I40E_FLAG_DCB) == 0) {
7016                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
7017                 return -ENOTSUP;
7018         }
7019
7020         if (pf->vf_num != 0 ||
7021             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
7022                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
7023
7024         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
7025         if (ret) {
7026                 PMD_INIT_LOG(ERR, "invalid dcb config");
7027                 return -EINVAL;
7028         }
7029         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
7030         if (ret) {
7031                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
7032                 return -ENOSYS;
7033         }
7034         return 0;
7035 }
7036
7037 static int
7038 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
7039                       struct rte_eth_dcb_info *dcb_info)
7040 {
7041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7043         struct i40e_vsi *vsi = pf->main_vsi;
7044         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
7045         uint16_t bsf, tc_mapping;
7046         int i;
7047
7048         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7049                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
7050         else
7051                 dcb_info->nb_tcs = 1;
7052         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7053                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
7054         for (i = 0; i < dcb_info->nb_tcs; i++)
7055                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
7056
7057         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7058                 if (vsi->enabled_tc & (1 << i)) {
7059                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
7060                         /* only main vsi support multi TCs */
7061                         dcb_info->tc_queue.tc_rxq[0][i].base =
7062                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
7063                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
7064                         dcb_info->tc_queue.tc_txq[0][i].base =
7065                                 dcb_info->tc_queue.tc_rxq[0][i].base;
7066                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
7067                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
7068                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
7069                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
7070                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
7071                 }
7072         }
7073         return 0;
7074 }